1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1176AVM8A_cm7
4 **                          MIMXRT1176CVM8A_cm7
5 **                          MIMXRT1176DVMAA_cm7
6 **
7 **     Compilers:           Freescale C/C++ for Embedded ARM
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    IMXRT1170RM, Rev 1, 02/2021
14 **     Version:             rev. 1.0, 2020-12-29
15 **     Build:               b230613
16 **
17 **     Abstract:
18 **         CMSIS Peripheral Access Layer for MIMXRT1176_cm7
19 **
20 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016-2023 NXP
22 **     SPDX-License-Identifier: BSD-3-Clause
23 **
24 **     http:                 www.nxp.com
25 **     mail:                 support@nxp.com
26 **
27 **     Revisions:
28 **     - rev. 0.1 (2018-03-05)
29 **         Initial version.
30 **     - rev. 1.0 (2020-12-29)
31 **         Update header files to align with IMXRT1170RM Rev.0.
32 **
33 ** ###################################################################
34 */
35 
36 /*!
37  * @file MIMXRT1176_cm7.h
38  * @version 1.0
39  * @date 2020-12-29
40  * @brief CMSIS Peripheral Access Layer for MIMXRT1176_cm7
41  *
42  * CMSIS Peripheral Access Layer for MIMXRT1176_cm7
43  */
44 
45 #ifndef _MIMXRT1176_CM7_H_
46 #define _MIMXRT1176_CM7_H_                       /**< Symbol preventing repeated inclusion */
47 
48 /** Memory map major version (memory maps with equal major version number are
49  * compatible) */
50 #define MCU_MEM_MAP_VERSION 0x0100U
51 /** Memory map minor version */
52 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
53 
54 /* ----------------------------------------------------------------------------
55    --
56    ---------------------------------------------------------------------------- */
57 
58 /* Extra XRDC2 definition */
59 #define XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd))
60 #define XRDC2_GET_MRC(mem) ((mem) >> 5U)
61 #define XRDC2_GET_MRGD(mem) ((mem) & 31U)
62 #define XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac))
63 #define XRDC2_GET_PAC(periph) ((periph) >> 8U)
64 #define XRDC2_GET_PDAC(periph) ((periph) & 255U)
65 
66 
67 
68 /* ----------------------------------------------------------------------------
69    -- Interrupt vector numbers
70    ---------------------------------------------------------------------------- */
71 
72 /*!
73  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
74  * @{
75  */
76 
77 /** Interrupt Number Definitions */
78 #define NUMBER_OF_INT_VECTORS 234                /**< Number of interrupts in the Vector table */
79 
80 typedef enum IRQn {
81   /* Auxiliary constants */
82   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
83 
84   /* Core interrupts */
85   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
86   HardFault_IRQn               = -13,              /**< Cortex-M7 SV Hard Fault Interrupt */
87   MemoryManagement_IRQn        = -12,              /**< Cortex-M7 Memory Management Interrupt */
88   BusFault_IRQn                = -11,              /**< Cortex-M7 Bus Fault Interrupt */
89   UsageFault_IRQn              = -10,              /**< Cortex-M7 Usage Fault Interrupt */
90   SVCall_IRQn                  = -5,               /**< Cortex-M7 SV Call Interrupt */
91   DebugMonitor_IRQn            = -4,               /**< Cortex-M7 Debug Monitor Interrupt */
92   PendSV_IRQn                  = -2,               /**< Cortex-M7 Pend SV Interrupt */
93   SysTick_IRQn                 = -1,               /**< Cortex-M7 System Tick Interrupt */
94 
95   /* Device specific interrupts */
96   DMA0_DMA16_IRQn              = 0,                /**< DMA channel 0/16 transfer complete */
97   DMA1_DMA17_IRQn              = 1,                /**< DMA channel 1/17 transfer complete */
98   DMA2_DMA18_IRQn              = 2,                /**< DMA channel 2/18 transfer complete */
99   DMA3_DMA19_IRQn              = 3,                /**< DMA channel 3/19 transfer complete */
100   DMA4_DMA20_IRQn              = 4,                /**< DMA channel 4/20 transfer complete */
101   DMA5_DMA21_IRQn              = 5,                /**< DMA channel 5/21 transfer complete */
102   DMA6_DMA22_IRQn              = 6,                /**< DMA channel 6/22 transfer complete */
103   DMA7_DMA23_IRQn              = 7,                /**< DMA channel 7/23 transfer complete */
104   DMA8_DMA24_IRQn              = 8,                /**< DMA channel 8/24 transfer complete */
105   DMA9_DMA25_IRQn              = 9,                /**< DMA channel 9/25 transfer complete */
106   DMA10_DMA26_IRQn             = 10,               /**< DMA channel 10/26 transfer complete */
107   DMA11_DMA27_IRQn             = 11,               /**< DMA channel 11/27 transfer complete */
108   DMA12_DMA28_IRQn             = 12,               /**< DMA channel 12/28 transfer complete */
109   DMA13_DMA29_IRQn             = 13,               /**< DMA channel 13/29 transfer complete */
110   DMA14_DMA30_IRQn             = 14,               /**< DMA channel 14/30 transfer complete */
111   DMA15_DMA31_IRQn             = 15,               /**< DMA channel 15/31 transfer complete */
112   DMA_ERROR_IRQn               = 16,               /**< DMA error interrupt channels 0-15 / 16-31 */
113   CTI_TRIGGER_OUT0_IRQn        = 17,               /**< CTI_TRIGGER_OUT0 */
114   CTI_TRIGGER_OUT1_IRQn        = 18,               /**< CTI_TRIGGER_OUT1 */
115   CORE_IRQn                    = 19,               /**< CorePlatform exception IRQ */
116   LPUART1_IRQn                 = 20,               /**< LPUART1 TX interrupt and RX interrupt */
117   LPUART2_IRQn                 = 21,               /**< LPUART2 TX interrupt and RX interrupt */
118   LPUART3_IRQn                 = 22,               /**< LPUART3 TX interrupt and RX interrupt */
119   LPUART4_IRQn                 = 23,               /**< LPUART4 TX interrupt and RX interrupt */
120   LPUART5_IRQn                 = 24,               /**< LPUART5 TX interrupt and RX interrupt */
121   LPUART6_IRQn                 = 25,               /**< LPUART6 TX interrupt and RX interrupt */
122   LPUART7_IRQn                 = 26,               /**< LPUART7 TX interrupt and RX interrupt */
123   LPUART8_IRQn                 = 27,               /**< LPUART8 TX interrupt and RX interrupt */
124   LPUART9_IRQn                 = 28,               /**< LPUART9 TX interrupt and RX interrupt */
125   LPUART10_IRQn                = 29,               /**< LPUART10 TX interrupt and RX interrupt */
126   LPUART11_IRQn                = 30,               /**< LPUART11 TX interrupt and RX interrupt */
127   LPUART12_IRQn                = 31,               /**< LPUART12 TX interrupt and RX interrupt */
128   LPI2C1_IRQn                  = 32,               /**< LPI2C1 interrupt */
129   LPI2C2_IRQn                  = 33,               /**< LPI2C2 interrupt */
130   LPI2C3_IRQn                  = 34,               /**< LPI2C3 interrupt */
131   LPI2C4_IRQn                  = 35,               /**< LPI2C4 interrupt */
132   LPI2C5_IRQn                  = 36,               /**< LPI2C5 interrupt */
133   LPI2C6_IRQn                  = 37,               /**< LPI2C6 interrupt */
134   LPSPI1_IRQn                  = 38,               /**< LPSPI1 interrupt request line to the core */
135   LPSPI2_IRQn                  = 39,               /**< LPSPI2 interrupt request line to the core */
136   LPSPI3_IRQn                  = 40,               /**< LPSPI3 interrupt request line to the core */
137   LPSPI4_IRQn                  = 41,               /**< LPSPI4 interrupt request line to the core */
138   LPSPI5_IRQn                  = 42,               /**< LPSPI5 interrupt request line to the core */
139   LPSPI6_IRQn                  = 43,               /**< LPSPI6 interrupt request line to the core */
140   CAN1_IRQn                    = 44,               /**< CAN1 interrupt */
141   CAN1_ERROR_IRQn              = 45,               /**< CAN1 error interrupt */
142   CAN2_IRQn                    = 46,               /**< CAN2 interrupt */
143   CAN2_ERROR_IRQn              = 47,               /**< CAN2 error interrupt */
144   CAN3_IRQn                    = 48,               /**< CAN3 interrupt */
145   CAN3_ERROR_IRQn              = 49,               /**< CAN3 erro interrupt */
146   FLEXRAM_IRQn                 = 50,               /**< FlexRAM address out of range Or access hit IRQ */
147   KPP_IRQn                     = 51,               /**< Keypad nterrupt */
148   Reserved68_IRQn              = 52,               /**< Reserved interrupt */
149   GPR_IRQ_IRQn                 = 53,               /**< GPR interrupt */
150   eLCDIF_IRQn                  = 54,               /**< eLCDIF interrupt */
151   LCDIFv2_IRQn                 = 55,               /**< LCDIFv2 interrupt */
152   CSI_IRQn                     = 56,               /**< CSI interrupt */
153   PXP_IRQn                     = 57,               /**< PXP interrupt */
154   MIPI_CSI_IRQn                = 58,               /**< MIPI_CSI interrupt */
155   MIPI_DSI_IRQn                = 59,               /**< MIPI_DSI interrupt */
156   GPU2D_IRQn                   = 60,               /**< GPU2D interrupt */
157   GPIO6_Combined_0_15_IRQn     = 61,               /**< Combined interrupt indication for GPIO6 signal 0 throughout 15 */
158   GPIO6_Combined_16_31_IRQn    = 62,               /**< Combined interrupt indication for GPIO6 signal 16 throughout 31 */
159   DAC_IRQn                     = 63,               /**< DAC interrupt */
160   KEY_MANAGER_IRQn             = 64,               /**< PUF interrupt */
161   WDOG2_IRQn                   = 65,               /**< WDOG2 interrupt */
162   SNVS_HP_NON_TZ_IRQn          = 66,               /**< SRTC Consolidated Interrupt. Non TZ */
163   SNVS_HP_TZ_IRQn              = 67,               /**< SRTC Security Interrupt. TZ */
164   SNVS_PULSE_EVENT_IRQn        = 68,               /**< ON-OFF button press shorter than 5 secs (pulse event) */
165   CAAM_IRQ0_IRQn               = 69,               /**< CAAM interrupt queue for JQ0 */
166   CAAM_IRQ1_IRQn               = 70,               /**< CAAM interrupt queue for JQ1 */
167   CAAM_IRQ2_IRQn               = 71,               /**< CAAM interrupt queue for JQ2 */
168   CAAM_IRQ3_IRQn               = 72,               /**< CAAM interrupt queue for JQ3 */
169   CAAM_RECORVE_ERRPR_IRQn      = 73,               /**< CAAM interrupt for recoverable error */
170   CAAM_RTIC_IRQn               = 74,               /**< CAAM interrupt for RTIC */
171   CDOG_IRQn                    = 75,               /**< CDOG interrupt */
172   SAI1_IRQn                    = 76,               /**< SAI1 interrupt */
173   SAI2_IRQn                    = 77,               /**< SAI1 interrupt */
174   SAI3_RX_IRQn                 = 78,               /**< SAI3 interrupt */
175   SAI3_TX_IRQn                 = 79,               /**< SAI3 interrupt */
176   SAI4_RX_IRQn                 = 80,               /**< SAI4 interrupt */
177   SAI4_TX_IRQn                 = 81,               /**< SAI4 interrupt */
178   SPDIF_IRQn                   = 82,               /**< SPDIF interrupt */
179   TMPSNS_INT_IRQn              = 83,               /**< TMPSNS interrupt */
180   TMPSNS_LOW_HIGH_IRQn         = 84,               /**< TMPSNS low high interrupt */
181   TMPSNS_PANIC_IRQn            = 85,               /**< TMPSNS panic interrupt */
182   LPSR_LP8_BROWNOUT_IRQn       = 86,               /**< LPSR 1p8 brownout interrupt */
183   LPSR_LP0_BROWNOUT_IRQn       = 87,               /**< LPSR 1p0 brownout interrupt */
184   ADC1_IRQn                    = 88,               /**< ADC1 interrupt */
185   ADC2_IRQn                    = 89,               /**< ADC2 interrupt */
186   USBPHY1_IRQn                 = 90,               /**< USBPHY1 interrupt */
187   USBPHY2_IRQn                 = 91,               /**< USBPHY2 interrupt */
188   RDC_IRQn                     = 92,               /**< RDC interrupt */
189   GPIO13_Combined_0_31_IRQn    = 93,               /**< Combined interrupt indication for GPIO13 signal 0 throughout 31 */
190   Reserved110_IRQn             = 94,               /**< Reserved interrupt */
191   DCIC1_IRQn                   = 95,               /**< DCIC1 interrupt */
192   DCIC2_IRQn                   = 96,               /**< DCIC2 interrupt */
193   ASRC_IRQn                    = 97,               /**< ASRC interrupt */
194   FLEXRAM_ECC_IRQn             = 98,               /**< FlexRAM ECC fatal interrupt */
195   CM7_GPIO2_3_IRQn             = 99,               /**< CM7_GPIO2,CM7_GPIO3 interrupt */
196   GPIO1_Combined_0_15_IRQn     = 100,              /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
197   GPIO1_Combined_16_31_IRQn    = 101,              /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
198   GPIO2_Combined_0_15_IRQn     = 102,              /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
199   GPIO2_Combined_16_31_IRQn    = 103,              /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
200   GPIO3_Combined_0_15_IRQn     = 104,              /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
201   GPIO3_Combined_16_31_IRQn    = 105,              /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
202   GPIO4_Combined_0_15_IRQn     = 106,              /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
203   GPIO4_Combined_16_31_IRQn    = 107,              /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
204   GPIO5_Combined_0_15_IRQn     = 108,              /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
205   GPIO5_Combined_16_31_IRQn    = 109,              /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
206   FLEXIO1_IRQn                 = 110,              /**< FLEXIO1 interrupt */
207   FLEXIO2_IRQn                 = 111,              /**< FLEXIO2 interrupt */
208   WDOG1_IRQn                   = 112,              /**< WDOG1 interrupt */
209   RTWDOG3_IRQn                 = 113,              /**< RTWDOG3 interrupt */
210   EWM_IRQn                     = 114,              /**< EWM interrupt */
211   OCOTP_READ_FUSE_ERROR_IRQn   = 115,              /**< OCOTP read fuse error interrupt */
212   OCOTP_READ_DONE_ERROR_IRQn   = 116,              /**< OCOTP read fuse done interrupt */
213   GPC_IRQn                     = 117,              /**< GPC interrupt */
214   MUA_IRQn                     = 118,              /**< MUA interrupt */
215   GPT1_IRQn                    = 119,              /**< GPT1 interrupt */
216   GPT2_IRQn                    = 120,              /**< GPT2 interrupt */
217   GPT3_IRQn                    = 121,              /**< GPT3 interrupt */
218   GPT4_IRQn                    = 122,              /**< GPT4 interrupt */
219   GPT5_IRQn                    = 123,              /**< GPT5 interrupt */
220   GPT6_IRQn                    = 124,              /**< GPT6 interrupt */
221   PWM1_0_IRQn                  = 125,              /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
222   PWM1_1_IRQn                  = 126,              /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
223   PWM1_2_IRQn                  = 127,              /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
224   PWM1_3_IRQn                  = 128,              /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
225   PWM1_FAULT_IRQn              = 129,              /**< PWM1 fault or reload error interrupt */
226   FLEXSPI1_IRQn                = 130,              /**< FlexSPI1 interrupt */
227   FLEXSPI2_IRQn                = 131,              /**< FlexSPI2 interrupt */
228   SEMC_IRQn                    = 132,              /**< SEMC interrupt */
229   USDHC1_IRQn                  = 133,              /**< USDHC1 interrupt */
230   USDHC2_IRQn                  = 134,              /**< USDHC2 interrupt */
231   USB_OTG2_IRQn                = 135,              /**< USBO2 USB OTG2 */
232   USB_OTG1_IRQn                = 136,              /**< USBO2 USB OTG1 */
233   ENET_IRQn                    = 137,              /**< ENET interrupt */
234   ENET_1588_Timer_IRQn         = 138,              /**< ENET_1588_Timer interrupt */
235   ENET_1G_MAC0_Tx_Rx_1_IRQn    = 139,              /**< ENET 1G MAC0 transmit/receive 1 */
236   ENET_1G_MAC0_Tx_Rx_2_IRQn    = 140,              /**< ENET 1G MAC0 transmit/receive 2 */
237   ENET_1G_IRQn                 = 141,              /**< ENET 1G interrupt */
238   ENET_1G_1588_Timer_IRQn      = 142,              /**< ENET_1G_1588_Timer interrupt */
239   XBAR1_IRQ_0_1_IRQn           = 143,              /**< XBARA1 output signal 0, 1 interrupt */
240   XBAR1_IRQ_2_3_IRQn           = 144,              /**< XBARA1 output signal 2, 3 interrupt */
241   ADC_ETC_IRQ0_IRQn            = 145,              /**< ADCETC IRQ0 interrupt */
242   ADC_ETC_IRQ1_IRQn            = 146,              /**< ADCETC IRQ1 interrupt */
243   ADC_ETC_IRQ2_IRQn            = 147,              /**< ADCETC IRQ2 interrupt */
244   ADC_ETC_IRQ3_IRQn            = 148,              /**< ADCETC IRQ3 interrupt */
245   ADC_ETC_ERROR_IRQ_IRQn       = 149,              /**< ADCETC Error IRQ interrupt */
246   Reserved166_IRQn             = 150,              /**< Reserved interrupt */
247   Reserved167_IRQn             = 151,              /**< Reserved interrupt */
248   Reserved168_IRQn             = 152,              /**< Reserved interrupt */
249   Reserved169_IRQn             = 153,              /**< Reserved interrupt */
250   Reserved170_IRQn             = 154,              /**< Reserved interrupt */
251   PIT1_IRQn                    = 155,              /**< PIT1 interrupt */
252   PIT2_IRQn                    = 156,              /**< PIT2 interrupt */
253   ACMP1_IRQn                   = 157,              /**< ACMP interrupt */
254   ACMP2_IRQn                   = 158,              /**< ACMP interrupt */
255   ACMP3_IRQn                   = 159,              /**< ACMP interrupt */
256   ACMP4_IRQn                   = 160,              /**< ACMP interrupt */
257   Reserved177_IRQn             = 161,              /**< Reserved interrupt */
258   Reserved178_IRQn             = 162,              /**< Reserved interrupt */
259   Reserved179_IRQn             = 163,              /**< Reserved interrupt */
260   Reserved180_IRQn             = 164,              /**< Reserved interrupt */
261   ENC1_IRQn                    = 165,              /**< ENC1 interrupt */
262   ENC2_IRQn                    = 166,              /**< ENC2 interrupt */
263   ENC3_IRQn                    = 167,              /**< ENC3 interrupt */
264   ENC4_IRQn                    = 168,              /**< ENC4 interrupt */
265   Reserved185_IRQn             = 169,              /**< Reserved interrupt */
266   Reserved186_IRQn             = 170,              /**< Reserved interrupt */
267   TMR1_IRQn                    = 171,              /**< TMR1 interrupt */
268   TMR2_IRQn                    = 172,              /**< TMR2 interrupt */
269   TMR3_IRQn                    = 173,              /**< TMR3 interrupt */
270   TMR4_IRQn                    = 174,              /**< TMR4 interrupt */
271   SEMA4_CP0_IRQn               = 175,              /**< SEMA4 CP0 interrupt */
272   SEMA4_CP1_IRQn               = 176,              /**< SEMA4 CP1 interrupt */
273   PWM2_0_IRQn                  = 177,              /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
274   PWM2_1_IRQn                  = 178,              /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
275   PWM2_2_IRQn                  = 179,              /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
276   PWM2_3_IRQn                  = 180,              /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
277   PWM2_FAULT_IRQn              = 181,              /**< PWM2 fault or reload error interrupt */
278   PWM3_0_IRQn                  = 182,              /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
279   PWM3_1_IRQn                  = 183,              /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
280   PWM3_2_IRQn                  = 184,              /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
281   PWM3_3_IRQn                  = 185,              /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
282   PWM3_FAULT_IRQn              = 186,              /**< PWM3 fault or reload error interrupt */
283   PWM4_0_IRQn                  = 187,              /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
284   PWM4_1_IRQn                  = 188,              /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
285   PWM4_2_IRQn                  = 189,              /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
286   PWM4_3_IRQn                  = 190,              /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
287   PWM4_FAULT_IRQn              = 191,              /**< PWM4 fault or reload error interrupt */
288   Reserved208_IRQn             = 192,              /**< Reserved interrupt */
289   Reserved209_IRQn             = 193,              /**< Reserved interrupt */
290   Reserved210_IRQn             = 194,              /**< Reserved interrupt */
291   Reserved211_IRQn             = 195,              /**< Reserved interrupt */
292   Reserved212_IRQn             = 196,              /**< Reserved interrupt */
293   Reserved213_IRQn             = 197,              /**< Reserved interrupt */
294   Reserved214_IRQn             = 198,              /**< Reserved interrupt */
295   Reserved215_IRQn             = 199,              /**< Reserved interrupt */
296   PDM_HWVAD_EVENT_IRQn         = 200,              /**< HWVAD event interrupt */
297   PDM_HWVAD_ERROR_IRQn         = 201,              /**< HWVAD error interrupt */
298   PDM_EVENT_IRQn               = 202,              /**< PDM event interrupt */
299   PDM_ERROR_IRQn               = 203,              /**< PDM error interrupt */
300   EMVSIM1_IRQn                 = 204,              /**< EMVSIM1 interrupt */
301   EMVSIM2_IRQn                 = 205,              /**< EMVSIM2 interrupt */
302   MECC1_INT_IRQn               = 206,              /**< MECC1 int */
303   MECC1_FATAL_INT_IRQn         = 207,              /**< MECC1 fatal int */
304   MECC2_INT_IRQn               = 208,              /**< MECC2 int */
305   MECC2_FATAL_INT_IRQn         = 209,              /**< MECC2 fatal int */
306   XECC_FLEXSPI1_INT_IRQn       = 210,              /**< XECC int */
307   XECC_FLEXSPI1_FATAL_INT_IRQn = 211,              /**< XECC fatal int */
308   XECC_FLEXSPI2_INT_IRQn       = 212,              /**< XECC int */
309   XECC_FLEXSPI2_FATAL_INT_IRQn = 213,              /**< XECC fatal int */
310   XECC_SEMC_INT_IRQn           = 214,              /**< XECC int */
311   XECC_SEMC_FATAL_INT_IRQn     = 215,              /**< XECC fatal int */
312   ENET_QOS_IRQn                = 216,              /**< ENET_QOS interrupt */
313   ENET_QOS_PMT_IRQn            = 217               /**< ENET_QOS_PMT interrupt */
314 } IRQn_Type;
315 
316 /*!
317  * @}
318  */ /* end of group Interrupt_vector_numbers */
319 
320 
321 /* ----------------------------------------------------------------------------
322    -- Cortex M7 Core Configuration
323    ---------------------------------------------------------------------------- */
324 
325 /*!
326  * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
327  * @{
328  */
329 
330 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
331 #define __ICACHE_PRESENT               1         /**< Defines if an ICACHE is present or not */
332 #define __DCACHE_PRESENT               1         /**< Defines if an DCACHE is present or not */
333 #define __DTCM_PRESENT                 1         /**< Defines if an DTCM is present or not */
334 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
335 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
336 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
337 
338 #include "core_cm7.h"                  /* Core Peripheral Access Layer */
339 #include "system_MIMXRT1176_cm7.h"     /* Device specific configuration file */
340 
341 /*!
342  * @}
343  */ /* end of group Cortex_Core_Configuration */
344 
345 
346 /* ----------------------------------------------------------------------------
347    -- Mapping Information
348    ---------------------------------------------------------------------------- */
349 
350 /*!
351  * @addtogroup Mapping_Information Mapping Information
352  * @{
353  */
354 
355 /** Mapping Information */
356 /*!
357  * @addtogroup rdc_mapping
358  * @{
359  */
360 
361 /*******************************************************************************
362  * Definitions
363  ******************************************************************************/
364 
365 /*!
366  * @brief Structure for the RDC mapping
367  *
368  * Defines the structure for the RDC resource collections.
369  */
370 /*
371  * Domain of these masters are not assigned by RDC
372  * CM7, CM7_DMA: Always use domain ID 0.
373  * CM4, CM4_DMA: Use domain ID 0 in single core case, 1 in dual core case.
374  * CAAM: Defined in CAAM mst_a[x]icid[10]
375  * LCDIFv2: Defined in LCDIF2 user bit[0]
376  * SSARC: Defined in SSARC user bit[0]
377  */
378 
379 typedef enum _rdc_master
380 {
381     kRDC_Master_ENET_1G_TX          = 1U,          /**< ENET_1G_TX */
382     kRDC_Master_ENET_1G_RX          = 2U,          /**< ENET_1G_RX */
383     kRDC_Master_ENET                = 3U,          /**< ENET */
384     kRDC_Master_ENET_QOS            = 4U,          /**< ENET_QOS */
385     kRDC_Master_USDHC1              = 5U,          /**< USDHC1 */
386     kRDC_Master_USDHC2              = 6U,          /**< USDHC2 */
387     kRDC_Master_USB                 = 7U,          /**< USB */
388     kRDC_Master_GPU                 = 8U,          /**< GPU */
389     kRDC_Master_PXP                 = 9U,          /**< PXP */
390     kRDC_Master_LCDIF               = 10U,         /**< LCDIF */
391     kRDC_Master_CSI                 = 11U,         /**< CSI */
392 } rdc_master_t;
393 
394 typedef enum _rdc_mem
395 {
396     kRDC_Mem_MRC0_0                 = 0U,
397     kRDC_Mem_MRC0_1                 = 1U,
398     kRDC_Mem_MRC0_2                 = 2U,
399     kRDC_Mem_MRC0_3                 = 3U,
400     kRDC_Mem_MRC0_4                 = 4U,
401     kRDC_Mem_MRC0_5                 = 5U,
402     kRDC_Mem_MRC0_6                 = 6U,
403     kRDC_Mem_MRC0_7                 = 7U,
404     kRDC_Mem_MRC1_0                 = 8U,
405     kRDC_Mem_MRC1_1                 = 9U,
406     kRDC_Mem_MRC1_2                 = 10U,
407     kRDC_Mem_MRC1_3                 = 11U,
408     kRDC_Mem_MRC1_4                 = 12U,
409     kRDC_Mem_MRC1_5                 = 13U,
410     kRDC_Mem_MRC1_6                 = 14U,
411     kRDC_Mem_MRC1_7                 = 15U,
412     kRDC_Mem_MRC2_0                 = 16U,
413     kRDC_Mem_MRC2_1                 = 17U,
414     kRDC_Mem_MRC2_2                 = 18U,
415     kRDC_Mem_MRC2_3                 = 19U,
416     kRDC_Mem_MRC2_4                 = 20U,
417     kRDC_Mem_MRC2_5                 = 21U,
418     kRDC_Mem_MRC2_6                 = 22U,
419     kRDC_Mem_MRC2_7                 = 23U,
420     kRDC_Mem_MRC3_0                 = 24U,
421     kRDC_Mem_MRC3_1                 = 25U,
422     kRDC_Mem_MRC3_2                 = 26U,
423     kRDC_Mem_MRC3_3                 = 27U,
424     kRDC_Mem_MRC3_4                 = 28U,
425     kRDC_Mem_MRC3_5                 = 29U,
426     kRDC_Mem_MRC3_6                 = 30U,
427     kRDC_Mem_MRC3_7                 = 31U,
428     kRDC_Mem_MRC4_0                 = 32U,
429     kRDC_Mem_MRC4_1                 = 33U,
430     kRDC_Mem_MRC4_2                 = 34U,
431     kRDC_Mem_MRC4_3                 = 35U,
432     kRDC_Mem_MRC4_4                 = 36U,
433     kRDC_Mem_MRC4_5                 = 37U,
434     kRDC_Mem_MRC4_6                 = 38U,
435     kRDC_Mem_MRC4_7                 = 39U,
436     kRDC_Mem_MRC5_0                 = 40U,
437     kRDC_Mem_MRC5_1                 = 41U,
438     kRDC_Mem_MRC5_2                 = 42U,
439     kRDC_Mem_MRC5_3                 = 43U,
440     kRDC_Mem_MRC6_0                 = 44U,
441     kRDC_Mem_MRC6_1                 = 45U,
442     kRDC_Mem_MRC6_2                 = 46U,
443     kRDC_Mem_MRC6_3                 = 47U,
444     kRDC_Mem_MRC7_0                 = 48U,
445     kRDC_Mem_MRC7_1                 = 49U,
446     kRDC_Mem_MRC7_2                 = 50U,
447     kRDC_Mem_MRC7_3                 = 51U,
448     kRDC_Mem_MRC7_4                 = 52U,
449     kRDC_Mem_MRC7_5                 = 53U,
450     kRDC_Mem_MRC7_6                 = 54U,
451     kRDC_Mem_MRC7_7                 = 55U,
452     kRDC_Mem_MRC8_0                 = 56U,
453     kRDC_Mem_MRC8_1                 = 57U,
454     kRDC_Mem_MRC8_2                 = 58U,
455 } rdc_mem_t;
456 
457 typedef enum _rdc_periph
458 {
459     kRDC_Periph_MTR                 = 0U,          /**< MTR */
460     kRDC_Periph_MECC1               = 1U,          /**< MECC1 */
461     kRDC_Periph_MECC2               = 2U,          /**< MECC2 */
462     kRDC_Periph_FLEXSPI1            = 3U,          /**< FlexSPI1 */
463     kRDC_Periph_FLEXSPI2            = 4U,          /**< FlexSPI2 */
464     kRDC_Periph_SEMC                = 5U,          /**< SEMC */
465     kRDC_Periph_CM7_IMXRT           = 6U,          /**< CM7_IMXRT */
466     kRDC_Periph_EWM                 = 7U,          /**< EWM */
467     kRDC_Periph_WDOG1               = 8U,          /**< WDOG1 */
468     kRDC_Periph_WDOG2               = 9U,          /**< WDOG2 */
469     kRDC_Periph_WDOG3               = 10U,         /**< WDOG3 */
470     kRDC_Periph_AOI_XBAR            = 11U,         /**< AOI_XBAR */
471     kRDC_Periph_ADC_ETC             = 12U,         /**< ADC_ETC */
472     kRDC_Periph_CAAM_1              = 13U,         /**< CAAM_1 */
473     kRDC_Periph_ADC1                = 14U,         /**< ADC1 */
474     kRDC_Periph_ADC2                = 15U,         /**< ADC2 */
475     kRDC_Periph_TSC_DIG             = 16U,         /**< TSC_DIG */
476     kRDC_Periph_DAC                 = 17U,         /**< DAC */
477     kRDC_Periph_IEE                 = 18U,         /**< IEE */
478     kRDC_Periph_DMAMUX              = 19U,         /**< DMAMUX */
479     kRDC_Periph_EDMA                = 19U,         /**< EDMA */
480     kRDC_Periph_LPUART1             = 20U,         /**< LPUART1 */
481     kRDC_Periph_LPUART2             = 21U,         /**< LPUART2 */
482     kRDC_Periph_LPUART3             = 22U,         /**< LPUART3 */
483     kRDC_Periph_LPUART4             = 23U,         /**< LPUART4 */
484     kRDC_Periph_LPUART5             = 24U,         /**< LPUART5 */
485     kRDC_Periph_LPUART6             = 25U,         /**< LPUART6 */
486     kRDC_Periph_LPUART7             = 26U,         /**< LPUART7 */
487     kRDC_Periph_LPUART8             = 27U,         /**< LPUART8 */
488     kRDC_Periph_LPUART9             = 28U,         /**< LPUART9 */
489     kRDC_Periph_LPUART10            = 29U,         /**< LPUART10 */
490     kRDC_Periph_FLEXIO1             = 30U,         /**< FlexIO1 */
491     kRDC_Periph_FLEXIO2             = 31U,         /**< FlexIO2 */
492     kRDC_Periph_CAN1                = 32U,         /**< CAN1 */
493     kRDC_Periph_CAN2                = 33U,         /**< CAN2 */
494     kRDC_Periph_PIT1                = 34U,         /**< PIT1 */
495     kRDC_Periph_KPP                 = 35U,         /**< KPP */
496     kRDC_Periph_IOMUXC_GPR          = 36U,         /**< IOMUXC_GPR */
497     kRDC_Periph_IOMUXC              = 37U,         /**< IOMUXC */
498     kRDC_Periph_GPT1                = 38U,         /**< GPT1 */
499     kRDC_Periph_GPT2                = 39U,         /**< GPT2 */
500     kRDC_Periph_GPT3                = 40U,         /**< GPT3 */
501     kRDC_Periph_GPT4                = 41U,         /**< GPT4 */
502     kRDC_Periph_GPT5                = 42U,         /**< GPT5 */
503     kRDC_Periph_GPT6                = 43U,         /**< GPT6 */
504     kRDC_Periph_LPI2C1              = 44U,         /**< LPI2C1 */
505     kRDC_Periph_LPI2C2              = 45U,         /**< LPI2C2 */
506     kRDC_Periph_LPI2C3              = 46U,         /**< LPI2C3 */
507     kRDC_Periph_LPI2C4              = 47U,         /**< LPI2C4 */
508     kRDC_Periph_LPSPI1              = 48U,         /**< LPSPI1 */
509     kRDC_Periph_LPSPI2              = 49U,         /**< LPSPI2 */
510     kRDC_Periph_LPSPI3              = 50U,         /**< LPSPI3 */
511     kRDC_Periph_LPSPI4              = 51U,         /**< LPSPI4 */
512     kRDC_Periph_GPIO_1_6            = 52U,         /**< GPIO_1_6 */
513     kRDC_Periph_CCM_OBS             = 53U,         /**< CCM_OBS */
514     kRDC_Periph_SIM1                = 54U,         /**< SIM1 */
515     kRDC_Periph_SIM2                = 55U,         /**< SIM2 */
516     kRDC_Periph_QTIMER1             = 56U,         /**< QTimer1 */
517     kRDC_Periph_QTIMER2             = 57U,         /**< QTimer2 */
518     kRDC_Periph_QTIMER3             = 58U,         /**< QTimer3 */
519     kRDC_Periph_QTIMER4             = 59U,         /**< QTimer4 */
520     kRDC_Periph_ENC1                = 60U,         /**< ENC1 */
521     kRDC_Periph_ENC2                = 61U,         /**< ENC2 */
522     kRDC_Periph_ENC3                = 62U,         /**< ENC3 */
523     kRDC_Periph_ENC4                = 63U,         /**< ENC4 */
524     kRDC_Periph_FLEXPWM1            = 64U,         /**< FLEXPWM1 */
525     kRDC_Periph_FLEXPWM2            = 65U,         /**< FLEXPWM2 */
526     kRDC_Periph_FLEXPWM3            = 66U,         /**< FLEXPWM3 */
527     kRDC_Periph_FLEXPWM4            = 67U,         /**< FLEXPWM4 */
528     kRDC_Periph_CAAM_2              = 68U,         /**< CAAM_2 */
529     kRDC_Periph_CAAM_3              = 69U,         /**< CAAM_3 */
530     kRDC_Periph_ACMP1               = 70U,         /**< ACMP1 */
531     kRDC_Periph_ACMP2               = 71U,         /**< ACMP2 */
532     kRDC_Periph_ACMP3               = 72U,         /**< ACMP3 */
533     kRDC_Periph_ACMP4               = 73U,         /**< ACMP4 */
534     kRDC_Periph_CAAM                = 74U,         /**< CAAM */
535     kRDC_Periph_SPDIF               = 75U,         /**< SPDIF */
536     kRDC_Periph_SAI1                = 76U,         /**< SAI1 */
537     kRDC_Periph_SAI2                = 77U,         /**< SAI2 */
538     kRDC_Periph_SAI3                = 78U,         /**< SAI3 */
539     kRDC_Periph_ASRC                = 79U,         /**< ASRC */
540     kRDC_Periph_USDHC1              = 80U,         /**< USDHC1 */
541     kRDC_Periph_USDHC2              = 81U,         /**< USDHC2 */
542     kRDC_Periph_ENET_1G             = 82U,         /**< ENET_1G */
543     kRDC_Periph_ENET                = 83U,         /**< ENET */
544     kRDC_Periph_USB_PL301           = 84U,         /**< USB_PL301 */
545     kRDC_Periph_USBPHY2             = 85U,         /**< USBPHY2 */
546     kRDC_Periph_USB_OTG2            = 85U,         /**< USB_OTG2 */
547     kRDC_Periph_USBPHY1             = 86U,         /**< USBPHY1 */
548     kRDC_Periph_USB_OTG1            = 86U,         /**< USB_OTG1 */
549     kRDC_Periph_ENET_QOS            = 87U,         /**< ENET_QOS */
550     kRDC_Periph_CAAM_5              = 88U,         /**< CAAM_5 */
551     kRDC_Periph_CSI                 = 89U,         /**< CSI */
552     kRDC_Periph_LCDIF1              = 90U,         /**< LCDIF1 */
553     kRDC_Periph_LCDIF2              = 91U,         /**< LCDIF2 */
554     kRDC_Periph_MIPI_DSI            = 92U,         /**< MIPI_DSI */
555     kRDC_Periph_MIPI_CSI            = 93U,         /**< MIPI_CSI */
556     kRDC_Periph_PXP                 = 94U,         /**< PXP */
557     kRDC_Periph_VIDEO_MUX           = 95U,         /**< VIDEO_MUX */
558     kRDC_Periph_PGMC_SRC_GPC        = 96U,         /**< PGMC_SRC_GPC */
559     kRDC_Periph_IOMUXC_LPSR         = 97U,         /**< IOMUXC_LPSR */
560     kRDC_Periph_IOMUXC_LPSR_GPR     = 98U,         /**< IOMUXC_LPSR_GPR */
561     kRDC_Periph_WDOG4               = 99U,         /**< WDOG4 */
562     kRDC_Periph_DMAMUX_LPSR         = 100U,        /**< DMAMUX_LPSR */
563     kRDC_Periph_EDMA_LPSR           = 100U,        /**< EDMA_LPSR */
564     kRDC_Periph_Reserved            = 101U,        /**< Reserved */
565     kRDC_Periph_MIC                 = 102U,        /**< MIC */
566     kRDC_Periph_LPUART11            = 103U,        /**< LPUART11 */
567     kRDC_Periph_LPUART12            = 104U,        /**< LPUART12 */
568     kRDC_Periph_LPSPI5              = 105U,        /**< LPSPI5 */
569     kRDC_Periph_LPSPI6              = 106U,        /**< LPSPI6 */
570     kRDC_Periph_LPI2C5              = 107U,        /**< LPI2C5 */
571     kRDC_Periph_LPI2C6              = 108U,        /**< LPI2C6 */
572     kRDC_Periph_CAN3                = 109U,        /**< CAN3 */
573     kRDC_Periph_SAI4                = 110U,        /**< SAI4 */
574     kRDC_Periph_SEMA1               = 111U,        /**< SEMA1 */
575     kRDC_Periph_GPIO_7_12           = 112U,        /**< GPIO_7_12 */
576     kRDC_Periph_KEY_MANAGER         = 113U,        /**< KEY_MANAGER */
577     kRDC_Periph_ANATOP              = 114U,        /**< ANATOP */
578     kRDC_Periph_SNVS_HP_WRAPPER     = 115U,        /**< SNVS_HP_WRAPPER */
579     kRDC_Periph_IOMUXC_SNVS         = 116U,        /**< IOMUXC_SNVS */
580     kRDC_Periph_IOMUXC_SNVS_GPR     = 117U,        /**< IOMUXC_SNVS_GPR */
581     kRDC_Periph_SNVS_SRAM           = 118U,        /**< SNVS_SRAM */
582     kRDC_Periph_GPIO13              = 119U,        /**< GPIO13 */
583     kRDC_Periph_ROMCP               = 120U,        /**< ROMCP */
584     kRDC_Periph_DCDC                = 121U,        /**< DCDC */
585     kRDC_Periph_OCOTP_CTRL_WRAPPER  = 122U,        /**< OCOTP_CTRL_WRAPPER */
586     kRDC_Periph_PIT2                = 123U,        /**< PIT2 */
587     kRDC_Periph_SSARC               = 124U,        /**< SSARC */
588     kRDC_Periph_CCM                 = 125U,        /**< CCM */
589     kRDC_Periph_CAAM_6              = 126U,        /**< CAAM_6 */
590     kRDC_Periph_CAAM_7              = 127U,        /**< CAAM_7 */
591 } rdc_periph_t;
592 
593 /* @} */
594 
595 typedef enum _xbar_input_signal
596 {
597     kXBARA1_InputLogicLow           = 0|0x100U,    /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
598     kXBARA1_InputLogicHigh          = 1|0x100U,    /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
599     kXBARA1_InputRESERVED2          = 2|0x100U,    /**< XBARA1_IN2 input is reserved. */
600     kXBARA1_InputRESERVED3          = 3|0x100U,    /**< XBARA1_IN3 input is reserved. */
601     kXBARA1_InputIomuxXbarInout04   = 4|0x100U,    /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
602     kXBARA1_InputIomuxXbarInout05   = 5|0x100U,    /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
603     kXBARA1_InputIomuxXbarInout06   = 6|0x100U,    /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
604     kXBARA1_InputIomuxXbarInout07   = 7|0x100U,    /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
605     kXBARA1_InputIomuxXbarInout08   = 8|0x100U,    /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
606     kXBARA1_InputIomuxXbarInout09   = 9|0x100U,    /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
607     kXBARA1_InputIomuxXbarInout10   = 10|0x100U,   /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
608     kXBARA1_InputIomuxXbarInout11   = 11|0x100U,   /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
609     kXBARA1_InputIomuxXbarInout12   = 12|0x100U,   /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
610     kXBARA1_InputIomuxXbarInout13   = 13|0x100U,   /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
611     kXBARA1_InputIomuxXbarInout14   = 14|0x100U,   /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
612     kXBARA1_InputIomuxXbarInout15   = 15|0x100U,   /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
613     kXBARA1_InputIomuxXbarInout16   = 16|0x100U,   /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
614     kXBARA1_InputIomuxXbarInout17   = 17|0x100U,   /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
615     kXBARA1_InputIomuxXbarInout18   = 18|0x100U,   /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
616     kXBARA1_InputIomuxXbarInout19   = 19|0x100U,   /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
617     kXBARA1_InputIomuxXbarInout20   = 20|0x100U,   /**< IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input. */
618     kXBARA1_InputIomuxXbarInout21   = 21|0x100U,   /**< IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input. */
619     kXBARA1_InputIomuxXbarInout22   = 22|0x100U,   /**< IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input. */
620     kXBARA1_InputIomuxXbarInout23   = 23|0x100U,   /**< IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input. */
621     kXBARA1_InputIomuxXbarInout24   = 24|0x100U,   /**< IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input. */
622     kXBARA1_InputIomuxXbarInout25   = 25|0x100U,   /**< IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input. */
623     kXBARA1_InputIomuxXbarInout26   = 26|0x100U,   /**< IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input. */
624     kXBARA1_InputIomuxXbarInout27   = 27|0x100U,   /**< IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input. */
625     kXBARA1_InputIomuxXbarInout28   = 28|0x100U,   /**< IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input. */
626     kXBARA1_InputIomuxXbarInout29   = 29|0x100U,   /**< IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input. */
627     kXBARA1_InputIomuxXbarInout30   = 30|0x100U,   /**< IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input. */
628     kXBARA1_InputIomuxXbarInout31   = 31|0x100U,   /**< IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input. */
629     kXBARA1_InputIomuxXbarInout32   = 32|0x100U,   /**< IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input. */
630     kXBARA1_InputIomuxXbarInout33   = 33|0x100U,   /**< IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input. */
631     kXBARA1_InputIomuxXbarInout34   = 34|0x100U,   /**< IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input. */
632     kXBARA1_InputIomuxXbarInout35   = 35|0x100U,   /**< IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input. */
633     kXBARA1_InputIomuxXbarInout36   = 36|0x100U,   /**< IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input. */
634     kXBARA1_InputIomuxXbarInout37   = 37|0x100U,   /**< IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input. */
635     kXBARA1_InputIomuxXbarInout38   = 38|0x100U,   /**< IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input. */
636     kXBARA1_InputIomuxXbarInout39   = 39|0x100U,   /**< IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input. */
637     kXBARA1_InputIomuxXbarInout40   = 40|0x100U,   /**< IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input. */
638     kXBARA1_InputRESERVED41         = 41|0x100U,   /**< XBARA1_IN41 input is reserved. */
639     kXBARA1_InputAcmp1Out           = 42|0x100U,   /**< ACMP1_OUT output assigned to XBARA1_IN42 input. */
640     kXBARA1_InputAcmp2Out           = 43|0x100U,   /**< ACMP2_OUT output assigned to XBARA1_IN43 input. */
641     kXBARA1_InputAcmp3Out           = 44|0x100U,   /**< ACMP3_OUT output assigned to XBARA1_IN44 input. */
642     kXBARA1_InputAcmp4Out           = 45|0x100U,   /**< ACMP4_OUT output assigned to XBARA1_IN45 input. */
643     kXBARA1_InputRESERVED46         = 46|0x100U,   /**< XBARA1_IN46 input is reserved. */
644     kXBARA1_InputRESERVED47         = 47|0x100U,   /**< XBARA1_IN47 input is reserved. */
645     kXBARA1_InputRESERVED48         = 48|0x100U,   /**< XBARA1_IN48 input is reserved. */
646     kXBARA1_InputRESERVED49         = 49|0x100U,   /**< XBARA1_IN49 input is reserved. */
647     kXBARA1_InputQtimer1Timer0      = 50|0x100U,   /**< QTIMER1_TIMER0 output assigned to XBARA1_IN50 input. */
648     kXBARA1_InputQtimer1Timer1      = 51|0x100U,   /**< QTIMER1_TIMER1 output assigned to XBARA1_IN51 input. */
649     kXBARA1_InputQtimer1Timer2      = 52|0x100U,   /**< QTIMER1_TIMER2 output assigned to XBARA1_IN52 input. */
650     kXBARA1_InputQtimer1Timer3      = 53|0x100U,   /**< QTIMER1_TIMER3 output assigned to XBARA1_IN53 input. */
651     kXBARA1_InputQtimer2Timer0      = 54|0x100U,   /**< QTIMER2_TIMER0 output assigned to XBARA1_IN54 input. */
652     kXBARA1_InputQtimer2Timer1      = 55|0x100U,   /**< QTIMER2_TIMER1 output assigned to XBARA1_IN55 input. */
653     kXBARA1_InputQtimer2Timer2      = 56|0x100U,   /**< QTIMER2_TIMER2 output assigned to XBARA1_IN56 input. */
654     kXBARA1_InputQtimer2Timer3      = 57|0x100U,   /**< QTIMER2_TIMER3 output assigned to XBARA1_IN57 input. */
655     kXBARA1_InputQtimer3Timer0      = 58|0x100U,   /**< QTIMER3_TIMER0 output assigned to XBARA1_IN58 input. */
656     kXBARA1_InputQtimer3Timer1      = 59|0x100U,   /**< QTIMER3_TIMER1 output assigned to XBARA1_IN59 input. */
657     kXBARA1_InputQtimer3Timer2      = 60|0x100U,   /**< QTIMER3_TIMER2 output assigned to XBARA1_IN60 input. */
658     kXBARA1_InputQtimer3Timer3      = 61|0x100U,   /**< QTIMER3_TIMER3 output assigned to XBARA1_IN61 input. */
659     kXBARA1_InputQtimer4Timer0      = 62|0x100U,   /**< QTIMER4_TIMER0 output assigned to XBARA1_IN62 input. */
660     kXBARA1_InputQtimer4Timer1      = 63|0x100U,   /**< QTIMER4_TIMER1 output assigned to XBARA1_IN63 input. */
661     kXBARA1_InputQtimer4Timer2      = 64|0x100U,   /**< QTIMER4_TIMER2 output assigned to XBARA1_IN64 input. */
662     kXBARA1_InputQtimer4Timer3      = 65|0x100U,   /**< QTIMER4_TIMER3 output assigned to XBARA1_IN65 input. */
663     kXBARA1_InputRESERVED66         = 66|0x100U,   /**< XBARA1_IN66 input is reserved. */
664     kXBARA1_InputRESERVED67         = 67|0x100U,   /**< XBARA1_IN67 input is reserved. */
665     kXBARA1_InputRESERVED68         = 68|0x100U,   /**< XBARA1_IN68 input is reserved. */
666     kXBARA1_InputRESERVED69         = 69|0x100U,   /**< XBARA1_IN69 input is reserved. */
667     kXBARA1_InputRESERVED70         = 70|0x100U,   /**< XBARA1_IN70 input is reserved. */
668     kXBARA1_InputRESERVED71         = 71|0x100U,   /**< XBARA1_IN71 input is reserved. */
669     kXBARA1_InputRESERVED72         = 72|0x100U,   /**< XBARA1_IN72 input is reserved. */
670     kXBARA1_InputRESERVED73         = 73|0x100U,   /**< XBARA1_IN73 input is reserved. */
671     kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input. */
672     kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input. */
673     kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input. */
674     kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input. */
675     kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input. */
676     kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input. */
677     kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input. */
678     kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input. */
679     kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input. */
680     kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input. */
681     kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input. */
682     kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input. */
683     kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input. */
684     kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input. */
685     kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input. */
686     kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input. */
687     kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input. */
688     kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input. */
689     kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input. */
690     kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input. */
691     kXBARA1_InputRESERVED94         = 94|0x100U,   /**< XBARA1_IN94 input is reserved. */
692     kXBARA1_InputRESERVED95         = 95|0x100U,   /**< XBARA1_IN95 input is reserved. */
693     kXBARA1_InputRESERVED96         = 96|0x100U,   /**< XBARA1_IN96 input is reserved. */
694     kXBARA1_InputRESERVED97         = 97|0x100U,   /**< XBARA1_IN97 input is reserved. */
695     kXBARA1_InputRESERVED98         = 98|0x100U,   /**< XBARA1_IN98 input is reserved. */
696     kXBARA1_InputRESERVED99         = 99|0x100U,   /**< XBARA1_IN99 input is reserved. */
697     kXBARA1_InputRESERVED100        = 100|0x100U,  /**< XBARA1_IN100 input is reserved. */
698     kXBARA1_InputRESERVED101        = 101|0x100U,  /**< XBARA1_IN101 input is reserved. */
699     kXBARA1_InputPit1Trigger0       = 102|0x100U,  /**< PIT1_TRIGGER0 output assigned to XBARA1_IN102 input. */
700     kXBARA1_InputPit1Trigger1       = 103|0x100U,  /**< PIT1_TRIGGER1 output assigned to XBARA1_IN103 input. */
701     kXBARA1_InputPit1Trigger2       = 104|0x100U,  /**< PIT1_TRIGGER2 output assigned to XBARA1_IN104 input. */
702     kXBARA1_InputPit1Trigger3       = 105|0x100U,  /**< PIT1_TRIGGER3 output assigned to XBARA1_IN105 input. */
703     kXBARA1_InputDec1PosMatch       = 106|0x100U,  /**< DEC1_POS_MATCH output assigned to XBARA1_IN106 input. */
704     kXBARA1_InputDec2PosMatch       = 107|0x100U,  /**< DEC2_POS_MATCH output assigned to XBARA1_IN107 input. */
705     kXBARA1_InputDec3PosMatch       = 108|0x100U,  /**< DEC3_POS_MATCH output assigned to XBARA1_IN108 input. */
706     kXBARA1_InputDec4PosMatch       = 109|0x100U,  /**< DEC4_POS_MATCH output assigned to XBARA1_IN109 input. */
707     kXBARA1_InputRESERVED110        = 110|0x100U,  /**< XBARA1_IN110 input is reserved. */
708     kXBARA1_InputRESERVED111        = 111|0x100U,  /**< XBARA1_IN111 input is reserved. */
709     kXBARA1_InputDmaDone0           = 112|0x100U,  /**< DMA_DONE0 output assigned to XBARA1_IN112 input. */
710     kXBARA1_InputDmaDone1           = 113|0x100U,  /**< DMA_DONE1 output assigned to XBARA1_IN113 input. */
711     kXBARA1_InputDmaDone2           = 114|0x100U,  /**< DMA_DONE2 output assigned to XBARA1_IN114 input. */
712     kXBARA1_InputDmaDone3           = 115|0x100U,  /**< DMA_DONE3 output assigned to XBARA1_IN115 input. */
713     kXBARA1_InputDmaDone4           = 116|0x100U,  /**< DMA_DONE4 output assigned to XBARA1_IN116 input. */
714     kXBARA1_InputDmaDone5           = 117|0x100U,  /**< DMA_DONE5 output assigned to XBARA1_IN117 input. */
715     kXBARA1_InputDmaDone6           = 118|0x100U,  /**< DMA_DONE6 output assigned to XBARA1_IN118 input. */
716     kXBARA1_InputDmaDone7           = 119|0x100U,  /**< DMA_DONE7 output assigned to XBARA1_IN119 input. */
717     kXBARA1_InputDmaLpsrDone0       = 120|0x100U,  /**< DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input. */
718     kXBARA1_InputDmaLpsrDone1       = 121|0x100U,  /**< DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input. */
719     kXBARA1_InputDmaLpsrDone2       = 122|0x100U,  /**< DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input. */
720     kXBARA1_InputDmaLpsrDone3       = 123|0x100U,  /**< DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input. */
721     kXBARA1_InputDmaLpsrDone4       = 124|0x100U,  /**< DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input. */
722     kXBARA1_InputDmaLpsrDone5       = 125|0x100U,  /**< DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input. */
723     kXBARA1_InputDmaLpsrDone6       = 126|0x100U,  /**< DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input. */
724     kXBARA1_InputDmaLpsrDone7       = 127|0x100U,  /**< DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input. */
725     kXBARA1_InputAoi1Out0           = 128|0x100U,  /**< AOI1_OUT0 output assigned to XBARA1_IN128 input. */
726     kXBARA1_InputAoi1Out1           = 129|0x100U,  /**< AOI1_OUT1 output assigned to XBARA1_IN129 input. */
727     kXBARA1_InputAoi1Out2           = 130|0x100U,  /**< AOI1_OUT2 output assigned to XBARA1_IN130 input. */
728     kXBARA1_InputAoi1Out3           = 131|0x100U,  /**< AOI1_OUT3 output assigned to XBARA1_IN131 input. */
729     kXBARA1_InputAoi2Out0           = 132|0x100U,  /**< AOI2_OUT0 output assigned to XBARA1_IN132 input. */
730     kXBARA1_InputAoi2Out1           = 133|0x100U,  /**< AOI2_OUT1 output assigned to XBARA1_IN133 input. */
731     kXBARA1_InputAoi2Out2           = 134|0x100U,  /**< AOI2_OUT2 output assigned to XBARA1_IN134 input. */
732     kXBARA1_InputAoi2Out3           = 135|0x100U,  /**< AOI2_OUT3 output assigned to XBARA1_IN135 input. */
733     kXBARA1_InputAdcEtc0Coco0       = 136|0x100U,  /**< ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input. */
734     kXBARA1_InputAdcEtc0Coco1       = 137|0x100U,  /**< ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input. */
735     kXBARA1_InputAdcEtc0Coco2       = 138|0x100U,  /**< ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input. */
736     kXBARA1_InputAdcEtc0Coco3       = 139|0x100U,  /**< ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input. */
737     kXBARA1_InputAdcEtc1Coco0       = 140|0x100U,  /**< ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input. */
738     kXBARA1_InputAdcEtc1Coco1       = 141|0x100U,  /**< ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input. */
739     kXBARA1_InputAdcEtc1Coco2       = 142|0x100U,  /**< ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input. */
740     kXBARA1_InputAdcEtc1Coco3       = 143|0x100U,  /**< ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input. */
741     kXBARB2_InputLogicLow           = 0|0x200U,    /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
742     kXBARB2_InputLogicHigh          = 1|0x200U,    /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
743     kXBARB2_InputAcmp1Out           = 2|0x200U,    /**< ACMP1_OUT output assigned to XBARB2_IN2 input. */
744     kXBARB2_InputAcmp2Out           = 3|0x200U,    /**< ACMP2_OUT output assigned to XBARB2_IN3 input. */
745     kXBARB2_InputAcmp3Out           = 4|0x200U,    /**< ACMP3_OUT output assigned to XBARB2_IN4 input. */
746     kXBARB2_InputAcmp4Out           = 5|0x200U,    /**< ACMP4_OUT output assigned to XBARB2_IN5 input. */
747     kXBARB2_InputRESERVED6          = 6|0x200U,    /**< XBARB2_IN6 input is reserved. */
748     kXBARB2_InputRESERVED7          = 7|0x200U,    /**< XBARB2_IN7 input is reserved. */
749     kXBARB2_InputRESERVED8          = 8|0x200U,    /**< XBARB2_IN8 input is reserved. */
750     kXBARB2_InputRESERVED9          = 9|0x200U,    /**< XBARB2_IN9 input is reserved. */
751     kXBARB2_InputQtimer1Timer0      = 10|0x200U,   /**< QTIMER1_TIMER0 output assigned to XBARB2_IN10 input. */
752     kXBARB2_InputQtimer1Timer1      = 11|0x200U,   /**< QTIMER1_TIMER1 output assigned to XBARB2_IN11 input. */
753     kXBARB2_InputQtimer1Timer2      = 12|0x200U,   /**< QTIMER1_TIMER2 output assigned to XBARB2_IN12 input. */
754     kXBARB2_InputQtimer1Timer3      = 13|0x200U,   /**< QTIMER1_TIMER3 output assigned to XBARB2_IN13 input. */
755     kXBARB2_InputQtimer2Timer0      = 14|0x200U,   /**< QTIMER2_TIMER0 output assigned to XBARB2_IN14 input. */
756     kXBARB2_InputQtimer2Timer1      = 15|0x200U,   /**< QTIMER2_TIMER1 output assigned to XBARB2_IN15 input. */
757     kXBARB2_InputQtimer2Timer2      = 16|0x200U,   /**< QTIMER2_TIMER2 output assigned to XBARB2_IN16 input. */
758     kXBARB2_InputQtimer2Timer3      = 17|0x200U,   /**< QTIMER2_TIMER3 output assigned to XBARB2_IN17 input. */
759     kXBARB2_InputQtimer3Timer0      = 18|0x200U,   /**< QTIMER3_TIMER0 output assigned to XBARB2_IN18 input. */
760     kXBARB2_InputQtimer3Timer1      = 19|0x200U,   /**< QTIMER3_TIMER1 output assigned to XBARB2_IN19 input. */
761     kXBARB2_InputQtimer3Timer2      = 20|0x200U,   /**< QTIMER3_TIMER2 output assigned to XBARB2_IN20 input. */
762     kXBARB2_InputQtimer3Timer3      = 21|0x200U,   /**< QTIMER3_TIMER3 output assigned to XBARB2_IN21 input. */
763     kXBARB2_InputQtimer4Timer0      = 22|0x200U,   /**< QTIMER4_TIMER0 output assigned to XBARB2_IN22 input. */
764     kXBARB2_InputQtimer4Timer1      = 23|0x200U,   /**< QTIMER4_TIMER1 output assigned to XBARB2_IN23 input. */
765     kXBARB2_InputQtimer4Timer2      = 24|0x200U,   /**< QTIMER4_TIMER2 output assigned to XBARB2_IN24 input. */
766     kXBARB2_InputQtimer4Timer3      = 25|0x200U,   /**< QTIMER4_TIMER3 output assigned to XBARB2_IN25 input. */
767     kXBARB2_InputRESERVED26         = 26|0x200U,   /**< XBARB2_IN26 input is reserved. */
768     kXBARB2_InputRESERVED27         = 27|0x200U,   /**< XBARB2_IN27 input is reserved. */
769     kXBARB2_InputRESERVED28         = 28|0x200U,   /**< XBARB2_IN28 input is reserved. */
770     kXBARB2_InputRESERVED29         = 29|0x200U,   /**< XBARB2_IN29 input is reserved. */
771     kXBARB2_InputRESERVED30         = 30|0x200U,   /**< XBARB2_IN30 input is reserved. */
772     kXBARB2_InputRESERVED31         = 31|0x200U,   /**< XBARB2_IN31 input is reserved. */
773     kXBARB2_InputRESERVED32         = 32|0x200U,   /**< XBARB2_IN32 input is reserved. */
774     kXBARB2_InputRESERVED33         = 33|0x200U,   /**< XBARB2_IN33 input is reserved. */
775     kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
776     kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
777     kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input. */
778     kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input. */
779     kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input. */
780     kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input. */
781     kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input. */
782     kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input. */
783     kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input. */
784     kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input. */
785     kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input. */
786     kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input. */
787     kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input. */
788     kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input. */
789     kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input. */
790     kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input. */
791     kXBARB2_InputRESERVED50         = 50|0x200U,   /**< XBARB2_IN50 input is reserved. */
792     kXBARB2_InputRESERVED51         = 51|0x200U,   /**< XBARB2_IN51 input is reserved. */
793     kXBARB2_InputRESERVED52         = 52|0x200U,   /**< XBARB2_IN52 input is reserved. */
794     kXBARB2_InputRESERVED53         = 53|0x200U,   /**< XBARB2_IN53 input is reserved. */
795     kXBARB2_InputRESERVED54         = 54|0x200U,   /**< XBARB2_IN54 input is reserved. */
796     kXBARB2_InputRESERVED55         = 55|0x200U,   /**< XBARB2_IN55 input is reserved. */
797     kXBARB2_InputRESERVED56         = 56|0x200U,   /**< XBARB2_IN56 input is reserved. */
798     kXBARB2_InputRESERVED57         = 57|0x200U,   /**< XBARB2_IN57 input is reserved. */
799     kXBARB2_InputPit1Trigger0       = 58|0x200U,   /**< PIT1_TRIGGER0 output assigned to XBARB2_IN58 input. */
800     kXBARB2_InputPit1Trigger1       = 59|0x200U,   /**< PIT1_TRIGGER1 output assigned to XBARB2_IN59 input. */
801     kXBARB2_InputAdcEtc0Coco0       = 60|0x200U,   /**< ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input. */
802     kXBARB2_InputAdcEtc0Coco1       = 61|0x200U,   /**< ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input. */
803     kXBARB2_InputAdcEtc0Coco2       = 62|0x200U,   /**< ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input. */
804     kXBARB2_InputAdcEtc0Coco3       = 63|0x200U,   /**< ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input. */
805     kXBARB2_InputAdcEtc1Coco0       = 64|0x200U,   /**< ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input. */
806     kXBARB2_InputAdcEtc1Coco1       = 65|0x200U,   /**< ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input. */
807     kXBARB2_InputAdcEtc1Coco2       = 66|0x200U,   /**< ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input. */
808     kXBARB2_InputAdcEtc1Coco3       = 67|0x200U,   /**< ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input. */
809     kXBARB2_InputRESERVED68         = 68|0x200U,   /**< XBARB2_IN68 input is reserved. */
810     kXBARB2_InputRESERVED69         = 69|0x200U,   /**< XBARB2_IN69 input is reserved. */
811     kXBARB2_InputRESERVED70         = 70|0x200U,   /**< XBARB2_IN70 input is reserved. */
812     kXBARB2_InputRESERVED71         = 71|0x200U,   /**< XBARB2_IN71 input is reserved. */
813     kXBARB2_InputRESERVED72         = 72|0x200U,   /**< XBARB2_IN72 input is reserved. */
814     kXBARB2_InputRESERVED73         = 73|0x200U,   /**< XBARB2_IN73 input is reserved. */
815     kXBARB2_InputRESERVED74         = 74|0x200U,   /**< XBARB2_IN74 input is reserved. */
816     kXBARB2_InputRESERVED75         = 75|0x200U,   /**< XBARB2_IN75 input is reserved. */
817     kXBARB2_InputDec1PosMatch       = 76|0x200U,   /**< DEC1_POS_MATCH output assigned to XBARB2_IN76 input. */
818     kXBARB2_InputDec2PosMatch       = 77|0x200U,   /**< DEC2_POS_MATCH output assigned to XBARB2_IN77 input. */
819     kXBARB2_InputDec3PosMatch       = 78|0x200U,   /**< DEC3_POS_MATCH output assigned to XBARB2_IN78 input. */
820     kXBARB2_InputDec4PosMatch       = 79|0x200U,   /**< DEC4_POS_MATCH output assigned to XBARB2_IN79 input. */
821     kXBARB2_InputRESERVED80         = 80|0x200U,   /**< XBARB2_IN80 input is reserved. */
822     kXBARB2_InputRESERVED81         = 81|0x200U,   /**< XBARB2_IN81 input is reserved. */
823     kXBARB2_InputDmaDone0           = 82|0x200U,   /**< DMA_DONE0 output assigned to XBARB2_IN82 input. */
824     kXBARB2_InputDmaDone1           = 83|0x200U,   /**< DMA_DONE1 output assigned to XBARB2_IN83 input. */
825     kXBARB2_InputDmaDone2           = 84|0x200U,   /**< DMA_DONE2 output assigned to XBARB2_IN84 input. */
826     kXBARB2_InputDmaDone3           = 85|0x200U,   /**< DMA_DONE3 output assigned to XBARB2_IN85 input. */
827     kXBARB2_InputDmaDone4           = 86|0x200U,   /**< DMA_DONE4 output assigned to XBARB2_IN86 input. */
828     kXBARB2_InputDmaDone5           = 87|0x200U,   /**< DMA_DONE5 output assigned to XBARB2_IN87 input. */
829     kXBARB2_InputDmaDone6           = 88|0x200U,   /**< DMA_DONE6 output assigned to XBARB2_IN88 input. */
830     kXBARB2_InputDmaDone7           = 89|0x200U,   /**< DMA_DONE7 output assigned to XBARB2_IN89 input. */
831     kXBARB2_InputDmaLpsrDone0       = 90|0x200U,   /**< DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input. */
832     kXBARB2_InputDmaLpsrDone1       = 91|0x200U,   /**< DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input. */
833     kXBARB2_InputDmaLpsrDone2       = 92|0x200U,   /**< DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input. */
834     kXBARB2_InputDmaLpsrDone3       = 93|0x200U,   /**< DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input. */
835     kXBARB2_InputDmaLpsrDone4       = 94|0x200U,   /**< DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input. */
836     kXBARB2_InputDmaLpsrDone5       = 95|0x200U,   /**< DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input. */
837     kXBARB2_InputDmaLpsrDone6       = 96|0x200U,   /**< DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input. */
838     kXBARB2_InputDmaLpsrDone7       = 97|0x200U,   /**< DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input. */
839     kXBARB3_InputLogicLow           = 0|0x300U,    /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
840     kXBARB3_InputLogicHigh          = 1|0x300U,    /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
841     kXBARB3_InputAcmp1Out           = 2|0x300U,    /**< ACMP1_OUT output assigned to XBARB3_IN2 input. */
842     kXBARB3_InputAcmp2Out           = 3|0x300U,    /**< ACMP2_OUT output assigned to XBARB3_IN3 input. */
843     kXBARB3_InputAcmp3Out           = 4|0x300U,    /**< ACMP3_OUT output assigned to XBARB3_IN4 input. */
844     kXBARB3_InputAcmp4Out           = 5|0x300U,    /**< ACMP4_OUT output assigned to XBARB3_IN5 input. */
845     kXBARB3_InputRESERVED6          = 6|0x300U,    /**< XBARB3_IN6 input is reserved. */
846     kXBARB3_InputRESERVED7          = 7|0x300U,    /**< XBARB3_IN7 input is reserved. */
847     kXBARB3_InputRESERVED8          = 8|0x300U,    /**< XBARB3_IN8 input is reserved. */
848     kXBARB3_InputRESERVED9          = 9|0x300U,    /**< XBARB3_IN9 input is reserved. */
849     kXBARB3_InputQtimer1Timer0      = 10|0x300U,   /**< QTIMER1_TIMER0 output assigned to XBARB3_IN10 input. */
850     kXBARB3_InputQtimer1Timer1      = 11|0x300U,   /**< QTIMER1_TIMER1 output assigned to XBARB3_IN11 input. */
851     kXBARB3_InputQtimer1Timer2      = 12|0x300U,   /**< QTIMER1_TIMER2 output assigned to XBARB3_IN12 input. */
852     kXBARB3_InputQtimer1Timer3      = 13|0x300U,   /**< QTIMER1_TIMER3 output assigned to XBARB3_IN13 input. */
853     kXBARB3_InputQtimer2Timer0      = 14|0x300U,   /**< QTIMER2_TIMER0 output assigned to XBARB3_IN14 input. */
854     kXBARB3_InputQtimer2Timer1      = 15|0x300U,   /**< QTIMER2_TIMER1 output assigned to XBARB3_IN15 input. */
855     kXBARB3_InputQtimer2Timer2      = 16|0x300U,   /**< QTIMER2_TIMER2 output assigned to XBARB3_IN16 input. */
856     kXBARB3_InputQtimer2Timer3      = 17|0x300U,   /**< QTIMER2_TIMER3 output assigned to XBARB3_IN17 input. */
857     kXBARB3_InputQtimer3Timer0      = 18|0x300U,   /**< QTIMER3_TIMER0 output assigned to XBARB3_IN18 input. */
858     kXBARB3_InputQtimer3Timer1      = 19|0x300U,   /**< QTIMER3_TIMER1 output assigned to XBARB3_IN19 input. */
859     kXBARB3_InputQtimer3Timer2      = 20|0x300U,   /**< QTIMER3_TIMER2 output assigned to XBARB3_IN20 input. */
860     kXBARB3_InputQtimer3Timer3      = 21|0x300U,   /**< QTIMER3_TIMER3 output assigned to XBARB3_IN21 input. */
861     kXBARB3_InputQtimer4Timer0      = 22|0x300U,   /**< QTIMER4_TIMER0 output assigned to XBARB3_IN22 input. */
862     kXBARB3_InputQtimer4Timer1      = 23|0x300U,   /**< QTIMER4_TIMER1 output assigned to XBARB3_IN23 input. */
863     kXBARB3_InputQtimer4Timer2      = 24|0x300U,   /**< QTIMER4_TIMER2 output assigned to XBARB3_IN24 input. */
864     kXBARB3_InputQtimer4Timer3      = 25|0x300U,   /**< QTIMER4_TIMER3 output assigned to XBARB3_IN25 input. */
865     kXBARB3_InputRESERVED26         = 26|0x300U,   /**< XBARB3_IN26 input is reserved. */
866     kXBARB3_InputRESERVED27         = 27|0x300U,   /**< XBARB3_IN27 input is reserved. */
867     kXBARB3_InputRESERVED28         = 28|0x300U,   /**< XBARB3_IN28 input is reserved. */
868     kXBARB3_InputRESERVED29         = 29|0x300U,   /**< XBARB3_IN29 input is reserved. */
869     kXBARB3_InputRESERVED30         = 30|0x300U,   /**< XBARB3_IN30 input is reserved. */
870     kXBARB3_InputRESERVED31         = 31|0x300U,   /**< XBARB3_IN31 input is reserved. */
871     kXBARB3_InputRESERVED32         = 32|0x300U,   /**< XBARB3_IN32 input is reserved. */
872     kXBARB3_InputRESERVED33         = 33|0x300U,   /**< XBARB3_IN33 input is reserved. */
873     kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
874     kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
875     kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input. */
876     kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input. */
877     kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input. */
878     kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input. */
879     kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input. */
880     kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input. */
881     kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input. */
882     kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input. */
883     kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input. */
884     kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input. */
885     kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input. */
886     kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input. */
887     kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input. */
888     kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input. */
889     kXBARB3_InputRESERVED50         = 50|0x300U,   /**< XBARB3_IN50 input is reserved. */
890     kXBARB3_InputRESERVED51         = 51|0x300U,   /**< XBARB3_IN51 input is reserved. */
891     kXBARB3_InputRESERVED52         = 52|0x300U,   /**< XBARB3_IN52 input is reserved. */
892     kXBARB3_InputRESERVED53         = 53|0x300U,   /**< XBARB3_IN53 input is reserved. */
893     kXBARB3_InputRESERVED54         = 54|0x300U,   /**< XBARB3_IN54 input is reserved. */
894     kXBARB3_InputRESERVED55         = 55|0x300U,   /**< XBARB3_IN55 input is reserved. */
895     kXBARB3_InputRESERVED56         = 56|0x300U,   /**< XBARB3_IN56 input is reserved. */
896     kXBARB3_InputRESERVED57         = 57|0x300U,   /**< XBARB3_IN57 input is reserved. */
897     kXBARB3_InputPit1Trigger0       = 58|0x300U,   /**< PIT1_TRIGGER0 output assigned to XBARB3_IN58 input. */
898     kXBARB3_InputPit1Trigger1       = 59|0x300U,   /**< PIT1_TRIGGER1 output assigned to XBARB3_IN59 input. */
899     kXBARB3_InputAdcEtc0Coco0       = 60|0x300U,   /**< ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input. */
900     kXBARB3_InputAdcEtc0Coco1       = 61|0x300U,   /**< ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input. */
901     kXBARB3_InputAdcEtc0Coco2       = 62|0x300U,   /**< ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input. */
902     kXBARB3_InputAdcEtc0Coco3       = 63|0x300U,   /**< ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input. */
903     kXBARB3_InputAdcEtc1Coco0       = 64|0x300U,   /**< ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input. */
904     kXBARB3_InputAdcEtc1Coco1       = 65|0x300U,   /**< ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input. */
905     kXBARB3_InputAdcEtc1Coco2       = 66|0x300U,   /**< ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input. */
906     kXBARB3_InputAdcEtc1Coco3       = 67|0x300U,   /**< ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input. */
907     kXBARB3_InputRESERVED68         = 68|0x300U,   /**< XBARB3_IN68 input is reserved. */
908     kXBARB3_InputRESERVED69         = 69|0x300U,   /**< XBARB3_IN69 input is reserved. */
909     kXBARB3_InputRESERVED70         = 70|0x300U,   /**< XBARB3_IN70 input is reserved. */
910     kXBARB3_InputRESERVED71         = 71|0x300U,   /**< XBARB3_IN71 input is reserved. */
911     kXBARB3_InputRESERVED72         = 72|0x300U,   /**< XBARB3_IN72 input is reserved. */
912     kXBARB3_InputRESERVED73         = 73|0x300U,   /**< XBARB3_IN73 input is reserved. */
913     kXBARB3_InputRESERVED74         = 74|0x300U,   /**< XBARB3_IN74 input is reserved. */
914     kXBARB3_InputRESERVED75         = 75|0x300U,   /**< XBARB3_IN75 input is reserved. */
915     kXBARB3_InputDec1PosMatch       = 76|0x300U,   /**< DEC1_POS_MATCH output assigned to XBARB3_IN76 input. */
916     kXBARB3_InputDec2PosMatch       = 77|0x300U,   /**< DEC2_POS_MATCH output assigned to XBARB3_IN77 input. */
917     kXBARB3_InputDec3PosMatch       = 78|0x300U,   /**< DEC3_POS_MATCH output assigned to XBARB3_IN78 input. */
918     kXBARB3_InputDec4PosMatch       = 79|0x300U,   /**< DEC4_POS_MATCH output assigned to XBARB3_IN79 input. */
919     kXBARB3_InputRESERVED80         = 80|0x300U,   /**< XBARB3_IN80 input is reserved. */
920     kXBARB3_InputRESERVED81         = 81|0x300U,   /**< XBARB3_IN81 input is reserved. */
921     kXBARB3_InputDmaDone0           = 82|0x300U,   /**< DMA_DONE0 output assigned to XBARB3_IN82 input. */
922     kXBARB3_InputDmaDone1           = 83|0x300U,   /**< DMA_DONE1 output assigned to XBARB3_IN83 input. */
923     kXBARB3_InputDmaDone2           = 84|0x300U,   /**< DMA_DONE2 output assigned to XBARB3_IN84 input. */
924     kXBARB3_InputDmaDone3           = 85|0x300U,   /**< DMA_DONE3 output assigned to XBARB3_IN85 input. */
925     kXBARB3_InputDmaDone4           = 86|0x300U,   /**< DMA_DONE4 output assigned to XBARB3_IN86 input. */
926     kXBARB3_InputDmaDone5           = 87|0x300U,   /**< DMA_DONE5 output assigned to XBARB3_IN87 input. */
927     kXBARB3_InputDmaDone6           = 88|0x300U,   /**< DMA_DONE6 output assigned to XBARB3_IN88 input. */
928     kXBARB3_InputDmaDone7           = 89|0x300U,   /**< DMA_DONE7 output assigned to XBARB3_IN89 input. */
929     kXBARB3_InputDmaLpsrDone0       = 90|0x300U,   /**< DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input. */
930     kXBARB3_InputDmaLpsrDone1       = 91|0x300U,   /**< DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input. */
931     kXBARB3_InputDmaLpsrDone2       = 92|0x300U,   /**< DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input. */
932     kXBARB3_InputDmaLpsrDone3       = 93|0x300U,   /**< DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input. */
933     kXBARB3_InputDmaLpsrDone4       = 94|0x300U,   /**< DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input. */
934     kXBARB3_InputDmaLpsrDone5       = 95|0x300U,   /**< DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input. */
935     kXBARB3_InputDmaLpsrDone6       = 96|0x300U,   /**< DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input. */
936     kXBARB3_InputDmaLpsrDone7       = 97|0x300U,   /**< DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input. */
937 } xbar_input_signal_t;
938 
939 typedef enum _xbar_output_signal
940 {
941     kXBARA1_OutputDmaChMuxReq81     = 0|0x100U,    /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81 */
942     kXBARA1_OutputDmaChMuxReq82     = 1|0x100U,    /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82 */
943     kXBARA1_OutputDmaChMuxReq83     = 2|0x100U,    /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83 */
944     kXBARA1_OutputDmaChMuxReq84     = 3|0x100U,    /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84 */
945     kXBARA1_OutputIomuxXbarInout04  = 4|0x100U,    /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
946     kXBARA1_OutputIomuxXbarInout05  = 5|0x100U,    /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
947     kXBARA1_OutputIomuxXbarInout06  = 6|0x100U,    /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
948     kXBARA1_OutputIomuxXbarInout07  = 7|0x100U,    /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
949     kXBARA1_OutputIomuxXbarInout08  = 8|0x100U,    /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
950     kXBARA1_OutputIomuxXbarInout09  = 9|0x100U,    /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
951     kXBARA1_OutputIomuxXbarInout10  = 10|0x100U,   /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
952     kXBARA1_OutputIomuxXbarInout11  = 11|0x100U,   /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
953     kXBARA1_OutputIomuxXbarInout12  = 12|0x100U,   /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
954     kXBARA1_OutputIomuxXbarInout13  = 13|0x100U,   /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
955     kXBARA1_OutputIomuxXbarInout14  = 14|0x100U,   /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
956     kXBARA1_OutputIomuxXbarInout15  = 15|0x100U,   /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
957     kXBARA1_OutputIomuxXbarInout16  = 16|0x100U,   /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
958     kXBARA1_OutputIomuxXbarInout17  = 17|0x100U,   /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
959     kXBARA1_OutputIomuxXbarInout18  = 18|0x100U,   /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
960     kXBARA1_OutputIomuxXbarInout19  = 19|0x100U,   /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
961     kXBARA1_OutputIomuxXbarInout20  = 20|0x100U,   /**< XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20 */
962     kXBARA1_OutputIomuxXbarInout21  = 21|0x100U,   /**< XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21 */
963     kXBARA1_OutputIomuxXbarInout22  = 22|0x100U,   /**< XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22 */
964     kXBARA1_OutputIomuxXbarInout23  = 23|0x100U,   /**< XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23 */
965     kXBARA1_OutputIomuxXbarInout24  = 24|0x100U,   /**< XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24 */
966     kXBARA1_OutputIomuxXbarInout25  = 25|0x100U,   /**< XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25 */
967     kXBARA1_OutputIomuxXbarInout26  = 26|0x100U,   /**< XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26 */
968     kXBARA1_OutputIomuxXbarInout27  = 27|0x100U,   /**< XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27 */
969     kXBARA1_OutputIomuxXbarInout28  = 28|0x100U,   /**< XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28 */
970     kXBARA1_OutputIomuxXbarInout29  = 29|0x100U,   /**< XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29 */
971     kXBARA1_OutputIomuxXbarInout30  = 30|0x100U,   /**< XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30 */
972     kXBARA1_OutputIomuxXbarInout31  = 31|0x100U,   /**< XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31 */
973     kXBARA1_OutputIomuxXbarInout32  = 32|0x100U,   /**< XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32 */
974     kXBARA1_OutputIomuxXbarInout33  = 33|0x100U,   /**< XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33 */
975     kXBARA1_OutputIomuxXbarInout34  = 34|0x100U,   /**< XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34 */
976     kXBARA1_OutputIomuxXbarInout35  = 35|0x100U,   /**< XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35 */
977     kXBARA1_OutputIomuxXbarInout36  = 36|0x100U,   /**< XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36 */
978     kXBARA1_OutputIomuxXbarInout37  = 37|0x100U,   /**< XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37 */
979     kXBARA1_OutputIomuxXbarInout38  = 38|0x100U,   /**< XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38 */
980     kXBARA1_OutputIomuxXbarInout39  = 39|0x100U,   /**< XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39 */
981     kXBARA1_OutputIomuxXbarInout40  = 40|0x100U,   /**< XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40 */
982     kXBARA1_OutputAcmp1Sample       = 41|0x100U,   /**< XBARA1_OUT41 output assigned to ACMP1_SAMPLE */
983     kXBARA1_OutputAcmp2Sample       = 42|0x100U,   /**< XBARA1_OUT42 output assigned to ACMP2_SAMPLE */
984     kXBARA1_OutputAcmp3Sample       = 43|0x100U,   /**< XBARA1_OUT43 output assigned to ACMP3_SAMPLE */
985     kXBARA1_OutputAcmp4Sample       = 44|0x100U,   /**< XBARA1_OUT44 output assigned to ACMP4_SAMPLE */
986     kXBARA1_OutputRESERVED45        = 45|0x100U,   /**< XBARA1_OUT45 output is reserved. */
987     kXBARA1_OutputRESERVED46        = 46|0x100U,   /**< XBARA1_OUT46 output is reserved. */
988     kXBARA1_OutputRESERVED47        = 47|0x100U,   /**< XBARA1_OUT47 output is reserved. */
989     kXBARA1_OutputRESERVED48        = 48|0x100U,   /**< XBARA1_OUT48 output is reserved. */
990     kXBARA1_OutputFlexpwm1Pwm0Exta  = 49|0x100U,   /**< XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA */
991     kXBARA1_OutputFlexpwm1Pwm1Exta  = 50|0x100U,   /**< XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA */
992     kXBARA1_OutputFlexpwm1Pwm2Exta  = 51|0x100U,   /**< XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA */
993     kXBARA1_OutputFlexpwm1Pwm3Exta  = 52|0x100U,   /**< XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA */
994     kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC */
995     kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC */
996     kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC */
997     kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC */
998     kXBARA1_OutputFlexpwm1ExtClk    = 57|0x100U,   /**< XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK */
999     kXBARA1_OutputFlexpwm1Fault0    = 58|0x100U,   /**< XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0 */
1000     kXBARA1_OutputFlexpwm1Fault1    = 59|0x100U,   /**< XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1 */
1001     kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U,   /**< XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2 */
1002     kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U,   /**< XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3 */
1003     kXBARA1_OutputFlexpwm1ExtForce  = 62|0x100U,   /**< XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */
1004     kXBARA1_OutputFlexpwm2Pwm0Exta  = 63|0x100U,   /**< XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA */
1005     kXBARA1_OutputFlexpwm2Pwm1Exta  = 64|0x100U,   /**< XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA */
1006     kXBARA1_OutputFlexpwm2Pwm2Exta  = 65|0x100U,   /**< XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA */
1007     kXBARA1_OutputFlexpwm2Pwm3Exta  = 66|0x100U,   /**< XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA */
1008     kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC */
1009     kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC */
1010     kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC */
1011     kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC */
1012     kXBARA1_OutputFlexpwm2ExtClk    = 71|0x100U,   /**< XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK */
1013     kXBARA1_OutputFlexpwm2Fault0    = 72|0x100U,   /**< XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0 */
1014     kXBARA1_OutputFlexpwm2Fault1    = 73|0x100U,   /**< XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1 */
1015     kXBARA1_OutputFlexpwm2ExtForce  = 74|0x100U,   /**< XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */
1016     kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U,   /**< XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA */
1017     kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U,   /**< XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA */
1018     kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U,   /**< XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA */
1019     kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U,   /**< XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA */
1020     kXBARA1_OutputFlexpwm34ExtClk   = 79|0x100U,   /**< XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK */
1021     kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC */
1022     kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC */
1023     kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC */
1024     kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC */
1025     kXBARA1_OutputFlexpwm3Fault0    = 84|0x100U,   /**< XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0 */
1026     kXBARA1_OutputFlexpwm3Fault1    = 85|0x100U,   /**< XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1 */
1027     kXBARA1_OutputFlexpwm3ExtForce  = 86|0x100U,   /**< XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */
1028     kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC */
1029     kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC */
1030     kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC */
1031     kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC */
1032     kXBARA1_OutputFlexpwm4Fault0    = 91|0x100U,   /**< XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0 */
1033     kXBARA1_OutputFlexpwm4Fault1    = 92|0x100U,   /**< XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1 */
1034     kXBARA1_OutputFlexpwm4ExtForce  = 93|0x100U,   /**< XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */
1035     kXBARA1_OutputRESERVED94        = 94|0x100U,   /**< XBARA1_OUT94 output is reserved. */
1036     kXBARA1_OutputRESERVED95        = 95|0x100U,   /**< XBARA1_OUT95 output is reserved. */
1037     kXBARA1_OutputRESERVED96        = 96|0x100U,   /**< XBARA1_OUT96 output is reserved. */
1038     kXBARA1_OutputRESERVED97        = 97|0x100U,   /**< XBARA1_OUT97 output is reserved. */
1039     kXBARA1_OutputRESERVED98        = 98|0x100U,   /**< XBARA1_OUT98 output is reserved. */
1040     kXBARA1_OutputRESERVED99        = 99|0x100U,   /**< XBARA1_OUT99 output is reserved. */
1041     kXBARA1_OutputRESERVED100       = 100|0x100U,  /**< XBARA1_OUT100 output is reserved. */
1042     kXBARA1_OutputRESERVED101       = 101|0x100U,  /**< XBARA1_OUT101 output is reserved. */
1043     kXBARA1_OutputRESERVED102       = 102|0x100U,  /**< XBARA1_OUT102 output is reserved. */
1044     kXBARA1_OutputRESERVED103       = 103|0x100U,  /**< XBARA1_OUT103 output is reserved. */
1045     kXBARA1_OutputRESERVED104       = 104|0x100U,  /**< XBARA1_OUT104 output is reserved. */
1046     kXBARA1_OutputRESERVED105       = 105|0x100U,  /**< XBARA1_OUT105 output is reserved. */
1047     kXBARA1_OutputRESERVED106       = 106|0x100U,  /**< XBARA1_OUT106 output is reserved. */
1048     kXBARA1_OutputRESERVED107       = 107|0x100U,  /**< XBARA1_OUT107 output is reserved. */
1049     kXBARA1_OutputDec1Phasea        = 108|0x100U,  /**< XBARA1_OUT108 output assigned to DEC1_PHASEA */
1050     kXBARA1_OutputDec1Phaseb        = 109|0x100U,  /**< XBARA1_OUT109 output assigned to DEC1_PHASEB */
1051     kXBARA1_OutputDec1Index         = 110|0x100U,  /**< XBARA1_OUT110 output assigned to DEC1_INDEX */
1052     kXBARA1_OutputDec1Home          = 111|0x100U,  /**< XBARA1_OUT111 output assigned to DEC1_HOME */
1053     kXBARA1_OutputDec1Trigger       = 112|0x100U,  /**< XBARA1_OUT112 output assigned to DEC1_TRIGGER */
1054     kXBARA1_OutputDec2Phasea        = 113|0x100U,  /**< XBARA1_OUT113 output assigned to DEC2_PHASEA */
1055     kXBARA1_OutputDec2Phaseb        = 114|0x100U,  /**< XBARA1_OUT114 output assigned to DEC2_PHASEB */
1056     kXBARA1_OutputDec2Index         = 115|0x100U,  /**< XBARA1_OUT115 output assigned to DEC2_INDEX */
1057     kXBARA1_OutputDec2Home          = 116|0x100U,  /**< XBARA1_OUT116 output assigned to DEC2_HOME */
1058     kXBARA1_OutputDec2Trigger       = 117|0x100U,  /**< XBARA1_OUT117 output assigned to DEC2_TRIGGER */
1059     kXBARA1_OutputDec3Phasea        = 118|0x100U,  /**< XBARA1_OUT118 output assigned to DEC3_PHASEA */
1060     kXBARA1_OutputDec3Phaseb        = 119|0x100U,  /**< XBARA1_OUT119 output assigned to DEC3_PHASEB */
1061     kXBARA1_OutputDec3Index         = 120|0x100U,  /**< XBARA1_OUT120 output assigned to DEC3_INDEX */
1062     kXBARA1_OutputDec3Home          = 121|0x100U,  /**< XBARA1_OUT121 output assigned to DEC3_HOME */
1063     kXBARA1_OutputDec3Trigger       = 122|0x100U,  /**< XBARA1_OUT122 output assigned to DEC3_TRIGGER */
1064     kXBARA1_OutputDec4Phasea        = 123|0x100U,  /**< XBARA1_OUT123 output assigned to DEC4_PHASEA */
1065     kXBARA1_OutputDec4Phaseb        = 124|0x100U,  /**< XBARA1_OUT124 output assigned to DEC4_PHASEB */
1066     kXBARA1_OutputDec4Index         = 125|0x100U,  /**< XBARA1_OUT125 output assigned to DEC4_INDEX */
1067     kXBARA1_OutputDec4Home          = 126|0x100U,  /**< XBARA1_OUT126 output assigned to DEC4_HOME */
1068     kXBARA1_OutputDec4Trigger       = 127|0x100U,  /**< XBARA1_OUT127 output assigned to DEC4_TRIGGER */
1069     kXBARA1_OutputRESERVED128       = 128|0x100U,  /**< XBARA1_OUT128 output is reserved. */
1070     kXBARA1_OutputRESERVED129       = 129|0x100U,  /**< XBARA1_OUT129 output is reserved. */
1071     kXBARA1_OutputRESERVED130       = 130|0x100U,  /**< XBARA1_OUT130 output is reserved. */
1072     kXBARA1_OutputRESERVED131       = 131|0x100U,  /**< XBARA1_OUT131 output is reserved. */
1073     kXBARA1_OutputCan1              = 132|0x100U,  /**< XBARA1_OUT132 output assigned to CAN1 */
1074     kXBARA1_OutputCan2              = 133|0x100U,  /**< XBARA1_OUT133 output assigned to CAN2 */
1075     kXBARA1_OutputRESERVED134       = 134|0x100U,  /**< XBARA1_OUT134 output is reserved. */
1076     kXBARA1_OutputRESERVED135       = 135|0x100U,  /**< XBARA1_OUT135 output is reserved. */
1077     kXBARA1_OutputRESERVED136       = 136|0x100U,  /**< XBARA1_OUT136 output is reserved. */
1078     kXBARA1_OutputRESERVED137       = 137|0x100U,  /**< XBARA1_OUT137 output is reserved. */
1079     kXBARA1_OutputQtimer1Timer0     = 138|0x100U,  /**< XBARA1_OUT138 output assigned to QTIMER1_TIMER0 */
1080     kXBARA1_OutputQtimer1Timer1     = 139|0x100U,  /**< XBARA1_OUT139 output assigned to QTIMER1_TIMER1 */
1081     kXBARA1_OutputQtimer1Timer2     = 140|0x100U,  /**< XBARA1_OUT140 output assigned to QTIMER1_TIMER2 */
1082     kXBARA1_OutputQtimer1Timer3     = 141|0x100U,  /**< XBARA1_OUT141 output assigned to QTIMER1_TIMER3 */
1083     kXBARA1_OutputQtimer2Timer0     = 142|0x100U,  /**< XBARA1_OUT142 output assigned to QTIMER2_TIMER0 */
1084     kXBARA1_OutputQtimer2Timer1     = 143|0x100U,  /**< XBARA1_OUT143 output assigned to QTIMER2_TIMER1 */
1085     kXBARA1_OutputQtimer2Timer2     = 144|0x100U,  /**< XBARA1_OUT144 output assigned to QTIMER2_TIMER2 */
1086     kXBARA1_OutputQtimer2Timer3     = 145|0x100U,  /**< XBARA1_OUT145 output assigned to QTIMER2_TIMER3 */
1087     kXBARA1_OutputQtimer3Timer0     = 146|0x100U,  /**< XBARA1_OUT146 output assigned to QTIMER3_TIMER0 */
1088     kXBARA1_OutputQtimer3Timer1     = 147|0x100U,  /**< XBARA1_OUT147 output assigned to QTIMER3_TIMER1 */
1089     kXBARA1_OutputQtimer3Timer2     = 148|0x100U,  /**< XBARA1_OUT148 output assigned to QTIMER3_TIMER2 */
1090     kXBARA1_OutputQtimer3Timer3     = 149|0x100U,  /**< XBARA1_OUT149 output assigned to QTIMER3_TIMER3 */
1091     kXBARA1_OutputQtimer4Timer0     = 150|0x100U,  /**< XBARA1_OUT150 output assigned to QTIMER4_TIMER0 */
1092     kXBARA1_OutputQtimer4Timer1     = 151|0x100U,  /**< XBARA1_OUT151 output assigned to QTIMER4_TIMER1 */
1093     kXBARA1_OutputQtimer4Timer2     = 152|0x100U,  /**< XBARA1_OUT152 output assigned to QTIMER4_TIMER2 */
1094     kXBARA1_OutputQtimer4Timer3     = 153|0x100U,  /**< XBARA1_OUT153 output assigned to QTIMER4_TIMER3 */
1095     kXBARA1_OutputEwmEwmIn          = 154|0x100U,  /**< XBARA1_OUT154 output assigned to EWM_EWM_IN */
1096     kXBARA1_OutputAdcEtc0Coco0      = 155|0x100U,  /**< XBARA1_OUT155 output assigned to ADC_ETC0_COCO0 */
1097     kXBARA1_OutputAdcEtc0Coco1      = 156|0x100U,  /**< XBARA1_OUT156 output assigned to ADC_ETC0_COCO1 */
1098     kXBARA1_OutputAdcEtc0Coco2      = 157|0x100U,  /**< XBARA1_OUT157 output assigned to ADC_ETC0_COCO2 */
1099     kXBARA1_OutputAdcEtc0Coco3      = 158|0x100U,  /**< XBARA1_OUT158 output assigned to ADC_ETC0_COCO3 */
1100     kXBARA1_OutputAdcEtc1Coco0      = 159|0x100U,  /**< XBARA1_OUT159 output assigned to ADC_ETC1_COCO0 */
1101     kXBARA1_OutputAdcEtc1Coco1      = 160|0x100U,  /**< XBARA1_OUT160 output assigned to ADC_ETC1_COCO1 */
1102     kXBARA1_OutputAdcEtc1Coco2      = 161|0x100U,  /**< XBARA1_OUT161 output assigned to ADC_ETC1_COCO2 */
1103     kXBARA1_OutputAdcEtc1Coco3      = 162|0x100U,  /**< XBARA1_OUT162 output assigned to ADC_ETC1_COCO3 */
1104     kXBARA1_OutputRESERVED163       = 163|0x100U,  /**< XBARA1_OUT163 output is reserved. */
1105     kXBARA1_OutputRESERVED164       = 164|0x100U,  /**< XBARA1_OUT164 output is reserved. */
1106     kXBARA1_OutputRESERVED165       = 165|0x100U,  /**< XBARA1_OUT165 output is reserved. */
1107     kXBARA1_OutputRESERVED166       = 166|0x100U,  /**< XBARA1_OUT166 output is reserved. */
1108     kXBARA1_OutputRESERVED167       = 167|0x100U,  /**< XBARA1_OUT167 output is reserved. */
1109     kXBARA1_OutputRESERVED168       = 168|0x100U,  /**< XBARA1_OUT168 output is reserved. */
1110     kXBARA1_OutputRESERVED169       = 169|0x100U,  /**< XBARA1_OUT169 output is reserved. */
1111     kXBARA1_OutputRESERVED170       = 170|0x100U,  /**< XBARA1_OUT170 output is reserved. */
1112     kXBARA1_OutputFlexio1TrigIn0    = 171|0x100U,  /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0 */
1113     kXBARA1_OutputFlexio1TrigIn1    = 172|0x100U,  /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1 */
1114     kXBARA1_OutputFlexio2TrigIn0    = 173|0x100U,  /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0 */
1115     kXBARA1_OutputFlexio2TrigIn1    = 174|0x100U,  /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1 */
1116     kXBARB2_OutputAoi1In00          = 0|0x200U,    /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1117     kXBARB2_OutputAoi1In01          = 1|0x200U,    /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1118     kXBARB2_OutputAoi1In02          = 2|0x200U,    /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1119     kXBARB2_OutputAoi1In03          = 3|0x200U,    /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1120     kXBARB2_OutputAoi1In04          = 4|0x200U,    /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1121     kXBARB2_OutputAoi1In05          = 5|0x200U,    /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1122     kXBARB2_OutputAoi1In06          = 6|0x200U,    /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1123     kXBARB2_OutputAoi1In07          = 7|0x200U,    /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1124     kXBARB2_OutputAoi1In08          = 8|0x200U,    /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1125     kXBARB2_OutputAoi1In09          = 9|0x200U,    /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1126     kXBARB2_OutputAoi1In10          = 10|0x200U,   /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1127     kXBARB2_OutputAoi1In11          = 11|0x200U,   /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1128     kXBARB2_OutputAoi1In12          = 12|0x200U,   /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1129     kXBARB2_OutputAoi1In13          = 13|0x200U,   /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1130     kXBARB2_OutputAoi1In14          = 14|0x200U,   /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1131     kXBARB2_OutputAoi1In15          = 15|0x200U,   /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1132     kXBARB3_OutputAoi2In00          = 0|0x300U,    /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1133     kXBARB3_OutputAoi2In01          = 1|0x300U,    /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1134     kXBARB3_OutputAoi2In02          = 2|0x300U,    /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1135     kXBARB3_OutputAoi2In03          = 3|0x300U,    /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1136     kXBARB3_OutputAoi2In04          = 4|0x300U,    /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1137     kXBARB3_OutputAoi2In05          = 5|0x300U,    /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1138     kXBARB3_OutputAoi2In06          = 6|0x300U,    /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1139     kXBARB3_OutputAoi2In07          = 7|0x300U,    /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1140     kXBARB3_OutputAoi2In08          = 8|0x300U,    /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1141     kXBARB3_OutputAoi2In09          = 9|0x300U,    /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1142     kXBARB3_OutputAoi2In10          = 10|0x300U,   /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1143     kXBARB3_OutputAoi2In11          = 11|0x300U,   /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1144     kXBARB3_OutputAoi2In12          = 12|0x300U,   /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1145     kXBARB3_OutputAoi2In13          = 13|0x300U,   /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1146     kXBARB3_OutputAoi2In14          = 14|0x300U,   /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1147     kXBARB3_OutputAoi2In15          = 15|0x300U,   /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1148 } xbar_output_signal_t;
1149 
1150 /*!
1151  * @addtogroup iomuxc_lpsr_pads
1152  * @{ */
1153 
1154 /*******************************************************************************
1155  * Definitions
1156 *******************************************************************************/
1157 
1158 /*!
1159  * @brief Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD
1160  *
1161  * Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.
1162  */
1163 typedef enum _iomuxc_lpsr_sw_mux_ctl_pad
1164 {
1165     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
1166     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
1167     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
1168     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
1169     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
1170     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
1171     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
1172     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
1173     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
1174     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
1175     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
1176     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
1177     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
1178     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
1179     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
1180     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
1181 } iomuxc_lpsr_sw_mux_ctl_pad_t;
1182 
1183 /* @} */
1184 
1185 /*!
1186  * @addtogroup iomuxc_lpsr_pads
1187  * @{ */
1188 
1189 /*******************************************************************************
1190  * Definitions
1191 *******************************************************************************/
1192 
1193 /*!
1194  * @brief Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD
1195  *
1196  * Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.
1197  */
1198 typedef enum _iomuxc_lpsr_sw_pad_ctl_pad
1199 {
1200     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
1201     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
1202     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
1203     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
1204     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
1205     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
1206     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
1207     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
1208     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
1209     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
1210     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
1211     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
1212     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
1213     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
1214     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
1215     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
1216 } iomuxc_lpsr_sw_pad_ctl_pad_t;
1217 
1218 /* @} */
1219 
1220 /*!
1221  * @brief Enumeration for the IOMUXC_LPSR select input
1222  *
1223  * Defines the enumeration for the IOMUXC_LPSR select input collections.
1224  */
1225 typedef enum _iomuxc_lpsr_select_input
1226 {
1227     kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U, /**< IOMUXC select input index */
1228     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U, /**< IOMUXC select input index */
1229     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U, /**< IOMUXC select input index */
1230     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U, /**< IOMUXC select input index */
1231     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U, /**< IOMUXC select input index */
1232     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U, /**< IOMUXC select input index */
1233     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U, /**< IOMUXC select input index */
1234     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U, /**< IOMUXC select input index */
1235     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U, /**< IOMUXC select input index */
1236     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U, /**< IOMUXC select input index */
1237     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U, /**< IOMUXC select input index */
1238     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U, /**< IOMUXC select input index */
1239     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U, /**< IOMUXC select input index */
1240     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U, /**< IOMUXC select input index */
1241     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U, /**< IOMUXC select input index */
1242     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U, /**< IOMUXC select input index */
1243     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U, /**< IOMUXC select input index */
1244     kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U, /**< IOMUXC select input index */
1245     kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U, /**< IOMUXC select input index */
1246     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
1247     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U, /**< IOMUXC select input index */
1248     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U, /**< IOMUXC select input index */
1249     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
1250     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
1251 } iomuxc_lpsr_select_input_t;
1252 
1253 /*!
1254  * @addtogroup ssarc_mapping
1255  * @{
1256  */
1257 
1258 /*******************************************************************************
1259  * Definitions
1260  ******************************************************************************/
1261 
1262 /*!
1263  * @brief Structure for the SSARC mapping
1264  *
1265  * The name of power domain.
1266  */
1267 
1268 typedef enum _ssarc_power_domain_name
1269 {
1270     kSSARC_MEGAMIXPowerDomain       = 0U,          /**< MEGAMIX Power Domain, request from BPC0. */
1271     kSSARC_DISPLAYMIXPowerDomain    = 1U,          /**< DISPLAYMIX Power Domain, request from BPC1. */
1272     kSSARC_WAKEUPMIXPowerDomain     = 2U,          /**< WAKEUPMIX Power Domain, request from BPC2. */
1273     kSSARC_LPSRMIXPowerDomain       = 3U,          /**< LPSRMIX Power Domain, request from BPC3. */
1274     kSSARC_PowerDomain4             = 4U,          /**< MIPI PHY Power Domain, request from BPC4. */
1275     kSSARC_PowerDomain5             = 5U,          /**< Virtual power domain, request from BPC5. */
1276     kSSARC_PowerDomain6             = 6U,          /**< Virtual power domain, request from BPC6. */
1277     kSSARC_PowerDomain7             = 7U,          /**< Virtual power domain, request from BPC7. */
1278 } ssarc_power_domain_name_t;
1279 
1280  /*
1281  * @brief The name of cpu domain.
1282  */
1283 typedef enum _ssarc_cpu_domain_name
1284 {
1285     kSSARC_CM7Core                  = 0U,          /**< CM7 Core domain. */
1286     kSSARC_CM4Core                  = 1U,          /**< CM4 Core domain. */
1287 } ssarc_cpu_domain_name_t;
1288 
1289 /* @} */
1290 
1291 /*!
1292  * @addtogroup xrdc2_mapping
1293  * @{
1294  */
1295 
1296 /*******************************************************************************
1297  * Definitions
1298  ******************************************************************************/
1299 
1300 /*!
1301  * @brief Structure for the XRDC2 mapping
1302  *
1303  * Defines the structure for the XRDC2 resource collections.
1304  */
1305 
1306 typedef enum _xrdc2_master
1307 {
1308     kXRDC2_Master_M7_AHB            = 0U,          /**< M7 AHB */
1309     kXRDC2_Master_M4_AHBC           = 0U,          /**< M4 AHBC */
1310     kXRDC2_Master_M7_AXI            = 1U,          /**< M7 AXI */
1311     kXRDC2_Master_M4_AHBS           = 1U,          /**< M4 AHBS */
1312     kXRDC2_Master_CAAM              = 2U,          /**< CAAM */
1313     kXRDC2_Master_CSI               = 3U,          /**< CSI */
1314     kXRDC2_Master_M7_EDMA           = 4U,          /**< M7 EDMA */
1315     kXRDC2_Master_M4_EDMA           = 4U,          /**< M4 EDMA */
1316     kXRDC2_Master_ENET              = 5U,          /**< ENET */
1317     kXRDC2_Master_ENET_1G_RX        = 6U,          /**< ENET_1G_RX */
1318     kXRDC2_Master_ENET_1G_TX        = 7U,          /**< ENET_1G_TX */
1319     kXRDC2_Master_ENET_QOS          = 8U,          /**< ENET_QOS */
1320     kXRDC2_Master_GPU               = 9U,          /**< GPU */
1321     kXRDC2_Master_LCDIF             = 10U,         /**< LCDIF */
1322     kXRDC2_Master_LCDIFV2           = 11U,         /**< LCDIFV2 */
1323     kXRDC2_Master_PXP               = 12U,         /**< PXP */
1324     kXRDC2_Master_SSARC             = 14U,         /**< SSARC */
1325     kXRDC2_Master_USB               = 15U,         /**< USB */
1326     kXRDC2_Master_USDHC1            = 16U,         /**< USDHC1 */
1327     kXRDC2_Master_USDHC2            = 17U,         /**< USDHC2 */
1328 } xrdc2_master_t;
1329 
1330 typedef enum _xrdc2_mem
1331 {
1332     kXRDC2_Mem_CAAM_Region0         = XRDC2_MAKE_MEM(0, 0), /**< MRC0 Memory 0 */
1333     kXRDC2_Mem_CAAM_Region1         = XRDC2_MAKE_MEM(0, 1), /**< MRC0 Memory 1 */
1334     kXRDC2_Mem_CAAM_Region2         = XRDC2_MAKE_MEM(0, 2), /**< MRC0 Memory 2 */
1335     kXRDC2_Mem_CAAM_Region3         = XRDC2_MAKE_MEM(0, 3), /**< MRC0 Memory 3 */
1336     kXRDC2_Mem_CAAM_Region4         = XRDC2_MAKE_MEM(0, 4), /**< MRC0 Memory 4 */
1337     kXRDC2_Mem_CAAM_Region5         = XRDC2_MAKE_MEM(0, 5), /**< MRC0 Memory 5 */
1338     kXRDC2_Mem_CAAM_Region6         = XRDC2_MAKE_MEM(0, 6), /**< MRC0 Memory 6 */
1339     kXRDC2_Mem_CAAM_Region7         = XRDC2_MAKE_MEM(0, 7), /**< MRC0 Memory 7 */
1340     kXRDC2_Mem_CAAM_Region8         = XRDC2_MAKE_MEM(0, 8), /**< MRC0 Memory 8 */
1341     kXRDC2_Mem_CAAM_Region9         = XRDC2_MAKE_MEM(0, 9), /**< MRC0 Memory 9 */
1342     kXRDC2_Mem_CAAM_Region10        = XRDC2_MAKE_MEM(0, 10), /**< MRC0 Memory 10 */
1343     kXRDC2_Mem_CAAM_Region11        = XRDC2_MAKE_MEM(0, 11), /**< MRC0 Memory 11 */
1344     kXRDC2_Mem_CAAM_Region12        = XRDC2_MAKE_MEM(0, 12), /**< MRC0 Memory 12 */
1345     kXRDC2_Mem_CAAM_Region13        = XRDC2_MAKE_MEM(0, 13), /**< MRC0 Memory 13 */
1346     kXRDC2_Mem_CAAM_Region14        = XRDC2_MAKE_MEM(0, 14), /**< MRC0 Memory 14 */
1347     kXRDC2_Mem_CAAM_Region15        = XRDC2_MAKE_MEM(0, 15), /**< MRC0 Memory 15 */
1348     kXRDC2_Mem_FLEXSPI1_Region0     = XRDC2_MAKE_MEM(1, 0), /**< MRC1 Memory 0 */
1349     kXRDC2_Mem_FLEXSPI1_Region1     = XRDC2_MAKE_MEM(1, 1), /**< MRC1 Memory 1 */
1350     kXRDC2_Mem_FLEXSPI1_Region2     = XRDC2_MAKE_MEM(1, 2), /**< MRC1 Memory 2 */
1351     kXRDC2_Mem_FLEXSPI1_Region3     = XRDC2_MAKE_MEM(1, 3), /**< MRC1 Memory 3 */
1352     kXRDC2_Mem_FLEXSPI1_Region4     = XRDC2_MAKE_MEM(1, 4), /**< MRC1 Memory 4 */
1353     kXRDC2_Mem_FLEXSPI1_Region5     = XRDC2_MAKE_MEM(1, 5), /**< MRC1 Memory 5 */
1354     kXRDC2_Mem_FLEXSPI1_Region6     = XRDC2_MAKE_MEM(1, 6), /**< MRC1 Memory 6 */
1355     kXRDC2_Mem_FLEXSPI1_Region7     = XRDC2_MAKE_MEM(1, 7), /**< MRC1 Memory 7 */
1356     kXRDC2_Mem_FLEXSPI1_Region8     = XRDC2_MAKE_MEM(1, 8), /**< MRC1 Memory 8 */
1357     kXRDC2_Mem_FLEXSPI1_Region9     = XRDC2_MAKE_MEM(1, 9), /**< MRC1 Memory 9 */
1358     kXRDC2_Mem_FLEXSPI1_Region10    = XRDC2_MAKE_MEM(1, 10), /**< MRC1 Memory 10 */
1359     kXRDC2_Mem_FLEXSPI1_Region11    = XRDC2_MAKE_MEM(1, 11), /**< MRC1 Memory 11 */
1360     kXRDC2_Mem_FLEXSPI1_Region12    = XRDC2_MAKE_MEM(1, 12), /**< MRC1 Memory 12 */
1361     kXRDC2_Mem_FLEXSPI1_Region13    = XRDC2_MAKE_MEM(1, 13), /**< MRC1 Memory 13 */
1362     kXRDC2_Mem_FLEXSPI1_Region14    = XRDC2_MAKE_MEM(1, 14), /**< MRC1 Memory 14 */
1363     kXRDC2_Mem_FLEXSPI1_Region15    = XRDC2_MAKE_MEM(1, 15), /**< MRC1 Memory 15 */
1364     kXRDC2_Mem_FLEXSPI2_Region0     = XRDC2_MAKE_MEM(2, 0), /**< MRC2 Memory 0 */
1365     kXRDC2_Mem_FLEXSPI2_Region1     = XRDC2_MAKE_MEM(2, 1), /**< MRC2 Memory 1 */
1366     kXRDC2_Mem_FLEXSPI2_Region2     = XRDC2_MAKE_MEM(2, 2), /**< MRC2 Memory 2 */
1367     kXRDC2_Mem_FLEXSPI2_Region3     = XRDC2_MAKE_MEM(2, 3), /**< MRC2 Memory 3 */
1368     kXRDC2_Mem_FLEXSPI2_Region4     = XRDC2_MAKE_MEM(2, 4), /**< MRC2 Memory 4 */
1369     kXRDC2_Mem_FLEXSPI2_Region5     = XRDC2_MAKE_MEM(2, 5), /**< MRC2 Memory 5 */
1370     kXRDC2_Mem_FLEXSPI2_Region6     = XRDC2_MAKE_MEM(2, 6), /**< MRC2 Memory 6 */
1371     kXRDC2_Mem_FLEXSPI2_Region7     = XRDC2_MAKE_MEM(2, 7), /**< MRC2 Memory 7 */
1372     kXRDC2_Mem_FLEXSPI2_Region8     = XRDC2_MAKE_MEM(2, 8), /**< MRC2 Memory 8 */
1373     kXRDC2_Mem_FLEXSPI2_Region9     = XRDC2_MAKE_MEM(2, 9), /**< MRC2 Memory 9 */
1374     kXRDC2_Mem_FLEXSPI2_Region10    = XRDC2_MAKE_MEM(2, 10), /**< MRC2 Memory 10 */
1375     kXRDC2_Mem_FLEXSPI2_Region11    = XRDC2_MAKE_MEM(2, 11), /**< MRC2 Memory 11 */
1376     kXRDC2_Mem_FLEXSPI2_Region12    = XRDC2_MAKE_MEM(2, 12), /**< MRC2 Memory 12 */
1377     kXRDC2_Mem_FLEXSPI2_Region13    = XRDC2_MAKE_MEM(2, 13), /**< MRC2 Memory 13 */
1378     kXRDC2_Mem_FLEXSPI2_Region14    = XRDC2_MAKE_MEM(2, 14), /**< MRC2 Memory 14 */
1379     kXRDC2_Mem_FLEXSPI2_Region15    = XRDC2_MAKE_MEM(2, 15), /**< MRC2 Memory 15 */
1380     kXRDC2_Mem_M4LMEM_Region0       = XRDC2_MAKE_MEM(3, 0), /**< MRC3 Memory 0 */
1381     kXRDC2_Mem_M4LMEM_Region1       = XRDC2_MAKE_MEM(3, 1), /**< MRC3 Memory 1 */
1382     kXRDC2_Mem_M4LMEM_Region2       = XRDC2_MAKE_MEM(3, 2), /**< MRC3 Memory 2 */
1383     kXRDC2_Mem_M4LMEM_Region3       = XRDC2_MAKE_MEM(3, 3), /**< MRC3 Memory 3 */
1384     kXRDC2_Mem_M4LMEM_Region4       = XRDC2_MAKE_MEM(3, 4), /**< MRC3 Memory 4 */
1385     kXRDC2_Mem_M4LMEM_Region5       = XRDC2_MAKE_MEM(3, 5), /**< MRC3 Memory 5 */
1386     kXRDC2_Mem_M4LMEM_Region6       = XRDC2_MAKE_MEM(3, 6), /**< MRC3 Memory 6 */
1387     kXRDC2_Mem_M4LMEM_Region7       = XRDC2_MAKE_MEM(3, 7), /**< MRC3 Memory 7 */
1388     kXRDC2_Mem_M4LMEM_Region8       = XRDC2_MAKE_MEM(3, 8), /**< MRC3 Memory 8 */
1389     kXRDC2_Mem_M4LMEM_Region9       = XRDC2_MAKE_MEM(3, 9), /**< MRC3 Memory 9 */
1390     kXRDC2_Mem_M4LMEM_Region10      = XRDC2_MAKE_MEM(3, 10), /**< MRC3 Memory 10 */
1391     kXRDC2_Mem_M4LMEM_Region11      = XRDC2_MAKE_MEM(3, 11), /**< MRC3 Memory 11 */
1392     kXRDC2_Mem_M4LMEM_Region12      = XRDC2_MAKE_MEM(3, 12), /**< MRC3 Memory 12 */
1393     kXRDC2_Mem_M4LMEM_Region13      = XRDC2_MAKE_MEM(3, 13), /**< MRC3 Memory 13 */
1394     kXRDC2_Mem_M4LMEM_Region14      = XRDC2_MAKE_MEM(3, 14), /**< MRC3 Memory 14 */
1395     kXRDC2_Mem_M4LMEM_Region15      = XRDC2_MAKE_MEM(3, 15), /**< MRC3 Memory 15 */
1396     kXRDC2_Mem_M7OC_Region0         = XRDC2_MAKE_MEM(4, 0), /**< MRC4 Memory 0 */
1397     kXRDC2_Mem_M7OC_Region1         = XRDC2_MAKE_MEM(4, 1), /**< MRC4 Memory 1 */
1398     kXRDC2_Mem_M7OC_Region2         = XRDC2_MAKE_MEM(4, 2), /**< MRC4 Memory 2 */
1399     kXRDC2_Mem_M7OC_Region3         = XRDC2_MAKE_MEM(4, 3), /**< MRC4 Memory 3 */
1400     kXRDC2_Mem_M7OC_Region4         = XRDC2_MAKE_MEM(4, 4), /**< MRC4 Memory 4 */
1401     kXRDC2_Mem_M7OC_Region5         = XRDC2_MAKE_MEM(4, 5), /**< MRC4 Memory 5 */
1402     kXRDC2_Mem_M7OC_Region6         = XRDC2_MAKE_MEM(4, 6), /**< MRC4 Memory 6 */
1403     kXRDC2_Mem_M7OC_Region7         = XRDC2_MAKE_MEM(4, 7), /**< MRC4 Memory 7 */
1404     kXRDC2_Mem_M7OC_Region8         = XRDC2_MAKE_MEM(4, 8), /**< MRC4 Memory 8 */
1405     kXRDC2_Mem_M7OC_Region9         = XRDC2_MAKE_MEM(4, 9), /**< MRC4 Memory 9 */
1406     kXRDC2_Mem_M7OC_Region10        = XRDC2_MAKE_MEM(4, 10), /**< MRC4 Memory 10 */
1407     kXRDC2_Mem_M7OC_Region11        = XRDC2_MAKE_MEM(4, 11), /**< MRC4 Memory 11 */
1408     kXRDC2_Mem_M7OC_Region12        = XRDC2_MAKE_MEM(4, 12), /**< MRC4 Memory 12 */
1409     kXRDC2_Mem_M7OC_Region13        = XRDC2_MAKE_MEM(4, 13), /**< MRC4 Memory 13 */
1410     kXRDC2_Mem_M7OC_Region14        = XRDC2_MAKE_MEM(4, 14), /**< MRC4 Memory 14 */
1411     kXRDC2_Mem_M7OC_Region15        = XRDC2_MAKE_MEM(4, 15), /**< MRC4 Memory 15 */
1412     kXRDC2_Mem_MECC1_Region0        = XRDC2_MAKE_MEM(5, 0), /**< MRC5 Memory 0 */
1413     kXRDC2_Mem_MECC1_Region1        = XRDC2_MAKE_MEM(5, 1), /**< MRC5 Memory 1 */
1414     kXRDC2_Mem_MECC1_Region2        = XRDC2_MAKE_MEM(5, 2), /**< MRC5 Memory 2 */
1415     kXRDC2_Mem_MECC1_Region3        = XRDC2_MAKE_MEM(5, 3), /**< MRC5 Memory 3 */
1416     kXRDC2_Mem_MECC1_Region4        = XRDC2_MAKE_MEM(5, 4), /**< MRC5 Memory 4 */
1417     kXRDC2_Mem_MECC1_Region5        = XRDC2_MAKE_MEM(5, 5), /**< MRC5 Memory 5 */
1418     kXRDC2_Mem_MECC1_Region6        = XRDC2_MAKE_MEM(5, 6), /**< MRC5 Memory 6 */
1419     kXRDC2_Mem_MECC1_Region7        = XRDC2_MAKE_MEM(5, 7), /**< MRC5 Memory 7 */
1420     kXRDC2_Mem_MECC1_Region8        = XRDC2_MAKE_MEM(5, 8), /**< MRC5 Memory 8 */
1421     kXRDC2_Mem_MECC1_Region9        = XRDC2_MAKE_MEM(5, 9), /**< MRC5 Memory 9 */
1422     kXRDC2_Mem_MECC1_Region10       = XRDC2_MAKE_MEM(5, 10), /**< MRC5 Memory 10 */
1423     kXRDC2_Mem_MECC1_Region11       = XRDC2_MAKE_MEM(5, 11), /**< MRC5 Memory 11 */
1424     kXRDC2_Mem_MECC1_Region12       = XRDC2_MAKE_MEM(5, 12), /**< MRC5 Memory 12 */
1425     kXRDC2_Mem_MECC1_Region13       = XRDC2_MAKE_MEM(5, 13), /**< MRC5 Memory 13 */
1426     kXRDC2_Mem_MECC1_Region14       = XRDC2_MAKE_MEM(5, 14), /**< MRC5 Memory 14 */
1427     kXRDC2_Mem_MECC1_Region15       = XRDC2_MAKE_MEM(5, 15), /**< MRC5 Memory 15 */
1428     kXRDC2_Mem_MECC2_Region0        = XRDC2_MAKE_MEM(6, 0), /**< MRC6 Memory 0 */
1429     kXRDC2_Mem_MECC2_Region1        = XRDC2_MAKE_MEM(6, 1), /**< MRC6 Memory 1 */
1430     kXRDC2_Mem_MECC2_Region2        = XRDC2_MAKE_MEM(6, 2), /**< MRC6 Memory 2 */
1431     kXRDC2_Mem_MECC2_Region3        = XRDC2_MAKE_MEM(6, 3), /**< MRC6 Memory 3 */
1432     kXRDC2_Mem_MECC2_Region4        = XRDC2_MAKE_MEM(6, 4), /**< MRC6 Memory 4 */
1433     kXRDC2_Mem_MECC2_Region5        = XRDC2_MAKE_MEM(6, 5), /**< MRC6 Memory 5 */
1434     kXRDC2_Mem_MECC2_Region6        = XRDC2_MAKE_MEM(6, 6), /**< MRC6 Memory 6 */
1435     kXRDC2_Mem_MECC2_Region7        = XRDC2_MAKE_MEM(6, 7), /**< MRC6 Memory 7 */
1436     kXRDC2_Mem_MECC2_Region8        = XRDC2_MAKE_MEM(6, 8), /**< MRC6 Memory 8 */
1437     kXRDC2_Mem_MECC2_Region9        = XRDC2_MAKE_MEM(6, 9), /**< MRC6 Memory 9 */
1438     kXRDC2_Mem_MECC2_Region10       = XRDC2_MAKE_MEM(6, 10), /**< MRC6 Memory 10 */
1439     kXRDC2_Mem_MECC2_Region11       = XRDC2_MAKE_MEM(6, 11), /**< MRC6 Memory 11 */
1440     kXRDC2_Mem_MECC2_Region12       = XRDC2_MAKE_MEM(6, 12), /**< MRC6 Memory 12 */
1441     kXRDC2_Mem_MECC2_Region13       = XRDC2_MAKE_MEM(6, 13), /**< MRC6 Memory 13 */
1442     kXRDC2_Mem_MECC2_Region14       = XRDC2_MAKE_MEM(6, 14), /**< MRC6 Memory 14 */
1443     kXRDC2_Mem_MECC2_Region15       = XRDC2_MAKE_MEM(6, 15), /**< MRC6 Memory 15 */
1444     kXRDC2_Mem_SEMC_Region0         = XRDC2_MAKE_MEM(7, 0), /**< MRC7 Memory 0 */
1445     kXRDC2_Mem_SEMC_Region1         = XRDC2_MAKE_MEM(7, 1), /**< MRC7 Memory 1 */
1446     kXRDC2_Mem_SEMC_Region2         = XRDC2_MAKE_MEM(7, 2), /**< MRC7 Memory 2 */
1447     kXRDC2_Mem_SEMC_Region3         = XRDC2_MAKE_MEM(7, 3), /**< MRC7 Memory 3 */
1448     kXRDC2_Mem_SEMC_Region4         = XRDC2_MAKE_MEM(7, 4), /**< MRC7 Memory 4 */
1449     kXRDC2_Mem_SEMC_Region5         = XRDC2_MAKE_MEM(7, 5), /**< MRC7 Memory 5 */
1450     kXRDC2_Mem_SEMC_Region6         = XRDC2_MAKE_MEM(7, 6), /**< MRC7 Memory 6 */
1451     kXRDC2_Mem_SEMC_Region7         = XRDC2_MAKE_MEM(7, 7), /**< MRC7 Memory 7 */
1452     kXRDC2_Mem_SEMC_Region8         = XRDC2_MAKE_MEM(7, 8), /**< MRC7 Memory 8 */
1453     kXRDC2_Mem_SEMC_Region9         = XRDC2_MAKE_MEM(7, 9), /**< MRC7 Memory 9 */
1454     kXRDC2_Mem_SEMC_Region10        = XRDC2_MAKE_MEM(7, 10), /**< MRC7 Memory 10 */
1455     kXRDC2_Mem_SEMC_Region11        = XRDC2_MAKE_MEM(7, 11), /**< MRC7 Memory 11 */
1456     kXRDC2_Mem_SEMC_Region12        = XRDC2_MAKE_MEM(7, 12), /**< MRC7 Memory 12 */
1457     kXRDC2_Mem_SEMC_Region13        = XRDC2_MAKE_MEM(7, 13), /**< MRC7 Memory 13 */
1458     kXRDC2_Mem_SEMC_Region14        = XRDC2_MAKE_MEM(7, 14), /**< MRC7 Memory 14 */
1459     kXRDC2_Mem_SEMC_Region15        = XRDC2_MAKE_MEM(7, 15), /**< MRC7 Memory 15 */
1460 } xrdc2_mem_t;
1461 
1462 typedef enum _xrdc2_mem_slot
1463 {
1464     kXRDC2_MemSlot_GPV0             = 0U,          /**< GPV0 */
1465     kXRDC2_MemSlot_GPV1             = 1U,          /**< GPV1 */
1466     kXRDC2_MemSlot_GPV2             = 2U,          /**< GPV2 */
1467     kXRDC2_MemSlot_ROMCP            = 3U,          /**< ROMCP */
1468 } xrdc2_mem_slot_t;
1469 
1470 typedef enum _xrdc2_periph
1471 {
1472     kXRDC2_Periph_ACMP4             = XRDC2_MAKE_PERIPH(0, 108), /**< ACMP4 */
1473     kXRDC2_Periph_ACMP3             = XRDC2_MAKE_PERIPH(0, 107), /**< ACMP3 */
1474     kXRDC2_Periph_ACMP2             = XRDC2_MAKE_PERIPH(0, 106), /**< ACMP2 */
1475     kXRDC2_Periph_ACMP1             = XRDC2_MAKE_PERIPH(0, 105), /**< ACMP1 */
1476     kXRDC2_Periph_FLEXPWM4          = XRDC2_MAKE_PERIPH(0, 102), /**< FLEXPWM4 */
1477     kXRDC2_Periph_FLEXPWM3          = XRDC2_MAKE_PERIPH(0, 101), /**< FLEXPWM3 */
1478     kXRDC2_Periph_FLEXPWM2          = XRDC2_MAKE_PERIPH(0, 100), /**< FLEXPWM2 */
1479     kXRDC2_Periph_FLEXPWM1          = XRDC2_MAKE_PERIPH(0, 99 ), /**< FLEXPWM1 */
1480     kXRDC2_Periph_ENC4              = XRDC2_MAKE_PERIPH(0, 96 ), /**< ENC4 */
1481     kXRDC2_Periph_ENC3              = XRDC2_MAKE_PERIPH(0, 95 ), /**< ENC3 */
1482     kXRDC2_Periph_ENC2              = XRDC2_MAKE_PERIPH(0, 94 ), /**< ENC2 */
1483     kXRDC2_Periph_ENC1              = XRDC2_MAKE_PERIPH(0, 93 ), /**< ENC1 */
1484     kXRDC2_Periph_QTIMER4           = XRDC2_MAKE_PERIPH(0, 90 ), /**< QTIMER4 */
1485     kXRDC2_Periph_QTIMER3           = XRDC2_MAKE_PERIPH(0, 89 ), /**< QTIMER3 */
1486     kXRDC2_Periph_QTIMER2           = XRDC2_MAKE_PERIPH(0, 88 ), /**< QTIMER2 */
1487     kXRDC2_Periph_QTIMER1           = XRDC2_MAKE_PERIPH(0, 87 ), /**< QTIMER1 */
1488     kXRDC2_Periph_SIM2              = XRDC2_MAKE_PERIPH(0, 86 ), /**< SIM2 */
1489     kXRDC2_Periph_SIM1              = XRDC2_MAKE_PERIPH(0, 85 ), /**< SIM1 */
1490     kXRDC2_Periph_CCM_OBS           = XRDC2_MAKE_PERIPH(0, 84 ), /**< CCM_OBS */
1491     kXRDC2_Periph_GPIO6             = XRDC2_MAKE_PERIPH(0, 80 ), /**< GPIO6 */
1492     kXRDC2_Periph_GPIO5             = XRDC2_MAKE_PERIPH(0, 79 ), /**< GPIO5 */
1493     kXRDC2_Periph_GPIO4             = XRDC2_MAKE_PERIPH(0, 78 ), /**< GPIO4 */
1494     kXRDC2_Periph_GPIO3             = XRDC2_MAKE_PERIPH(0, 77 ), /**< GPIO3 */
1495     kXRDC2_Periph_GPIO2             = XRDC2_MAKE_PERIPH(0, 76 ), /**< GPIO2 */
1496     kXRDC2_Periph_GPIO1             = XRDC2_MAKE_PERIPH(0, 75 ), /**< GPIO1 */
1497     kXRDC2_Periph_LPSPI4            = XRDC2_MAKE_PERIPH(0, 72 ), /**< LPSPI4 */
1498     kXRDC2_Periph_LPSPI3            = XRDC2_MAKE_PERIPH(0, 71 ), /**< LPSPI3 */
1499     kXRDC2_Periph_LPSPI2            = XRDC2_MAKE_PERIPH(0, 70 ), /**< LPSPI2 */
1500     kXRDC2_Periph_LPSPI1            = XRDC2_MAKE_PERIPH(0, 69 ), /**< LPSPI1 */
1501     kXRDC2_Periph_LPI2C4            = XRDC2_MAKE_PERIPH(0, 68 ), /**< LPI2C4 */
1502     kXRDC2_Periph_LPI2C3            = XRDC2_MAKE_PERIPH(0, 67 ), /**< LPI2C3 */
1503     kXRDC2_Periph_LPI2C2            = XRDC2_MAKE_PERIPH(0, 66 ), /**< LPI2C2 */
1504     kXRDC2_Periph_LPI2C1            = XRDC2_MAKE_PERIPH(0, 65 ), /**< LPI2C1 */
1505     kXRDC2_Periph_GPT6              = XRDC2_MAKE_PERIPH(0, 64 ), /**< GPT6 */
1506     kXRDC2_Periph_GPT5              = XRDC2_MAKE_PERIPH(0, 63 ), /**< GPT5 */
1507     kXRDC2_Periph_GPT4              = XRDC2_MAKE_PERIPH(0, 62 ), /**< GPT4 */
1508     kXRDC2_Periph_GPT3              = XRDC2_MAKE_PERIPH(0, 61 ), /**< GPT3 */
1509     kXRDC2_Periph_GPT2              = XRDC2_MAKE_PERIPH(0, 60 ), /**< GPT2 */
1510     kXRDC2_Periph_GPT1              = XRDC2_MAKE_PERIPH(0, 59 ), /**< GPT1 */
1511     kXRDC2_Periph_IOMUXC            = XRDC2_MAKE_PERIPH(0, 58 ), /**< IOMUXC */
1512     kXRDC2_Periph_IOMUXC_GPR        = XRDC2_MAKE_PERIPH(0, 57 ), /**< IOMUXC_GPR */
1513     kXRDC2_Periph_KPP               = XRDC2_MAKE_PERIPH(0, 56 ), /**< KPP */
1514     kXRDC2_Periph_PIT1              = XRDC2_MAKE_PERIPH(0, 54 ), /**< PIT1 */
1515     kXRDC2_Periph_SEMC              = XRDC2_MAKE_PERIPH(0, 53 ), /**< SEMC */
1516     kXRDC2_Periph_FLEXSPI2          = XRDC2_MAKE_PERIPH(0, 52 ), /**< FLEXSPI2 */
1517     kXRDC2_Periph_FLEXSPI1          = XRDC2_MAKE_PERIPH(0, 51 ), /**< FLEXSPI1 */
1518     kXRDC2_Periph_CAN2              = XRDC2_MAKE_PERIPH(0, 50 ), /**< CAN2 */
1519     kXRDC2_Periph_CAN1              = XRDC2_MAKE_PERIPH(0, 49 ), /**< CAN1 */
1520     kXRDC2_Periph_AOI2              = XRDC2_MAKE_PERIPH(0, 47 ), /**< AOI2 */
1521     kXRDC2_Periph_AOI1              = XRDC2_MAKE_PERIPH(0, 46 ), /**< AOI1 */
1522     kXRDC2_Periph_FLEXIO2           = XRDC2_MAKE_PERIPH(0, 44 ), /**< FLEXIO2 */
1523     kXRDC2_Periph_FLEXIO1           = XRDC2_MAKE_PERIPH(0, 43 ), /**< FLEXIO1 */
1524     kXRDC2_Periph_LPUART10          = XRDC2_MAKE_PERIPH(0, 40 ), /**< LPUART10 */
1525     kXRDC2_Periph_LPUART9           = XRDC2_MAKE_PERIPH(0, 39 ), /**< LPUART9 */
1526     kXRDC2_Periph_LPUART8           = XRDC2_MAKE_PERIPH(0, 38 ), /**< LPUART8 */
1527     kXRDC2_Periph_LPUART7           = XRDC2_MAKE_PERIPH(0, 37 ), /**< LPUART7 */
1528     kXRDC2_Periph_LPUART6           = XRDC2_MAKE_PERIPH(0, 36 ), /**< LPUART6 */
1529     kXRDC2_Periph_LPUART5           = XRDC2_MAKE_PERIPH(0, 35 ), /**< LPUART5 */
1530     kXRDC2_Periph_LPUART4           = XRDC2_MAKE_PERIPH(0, 34 ), /**< LPUART4 */
1531     kXRDC2_Periph_LPUART3           = XRDC2_MAKE_PERIPH(0, 33 ), /**< LPUART3 */
1532     kXRDC2_Periph_LPUART2           = XRDC2_MAKE_PERIPH(0, 32 ), /**< LPUART2 */
1533     kXRDC2_Periph_LPUART1           = XRDC2_MAKE_PERIPH(0, 31 ), /**< LPUART1 */
1534     kXRDC2_Periph_DMA_CH_MUX        = XRDC2_MAKE_PERIPH(0, 29 ), /**< DMA_CH_MUX */
1535     kXRDC2_Periph_EDMA              = XRDC2_MAKE_PERIPH(0, 28 ), /**< EDMA */
1536     kXRDC2_Periph_IEE               = XRDC2_MAKE_PERIPH(0, 27 ), /**< IEE */
1537     kXRDC2_Periph_DAC               = XRDC2_MAKE_PERIPH(0, 25 ), /**< DAC */
1538     kXRDC2_Periph_TSC_DIG           = XRDC2_MAKE_PERIPH(0, 23 ), /**< TSC_DIG */
1539     kXRDC2_Periph_ADC2              = XRDC2_MAKE_PERIPH(0, 21 ), /**< ADC2 */
1540     kXRDC2_Periph_ADC1              = XRDC2_MAKE_PERIPH(0, 20 ), /**< ADC1 */
1541     kXRDC2_Periph_ADC_ETC           = XRDC2_MAKE_PERIPH(0, 18 ), /**< ADC_ETC */
1542     kXRDC2_Periph_XBAR3             = XRDC2_MAKE_PERIPH(0, 17 ), /**< XBAR3 */
1543     kXRDC2_Periph_XBAR2             = XRDC2_MAKE_PERIPH(0, 16 ), /**< XBAR2 */
1544     kXRDC2_Periph_XBAR1             = XRDC2_MAKE_PERIPH(0, 15 ), /**< XBAR1 */
1545     kXRDC2_Periph_WDOG3             = XRDC2_MAKE_PERIPH(0, 14 ), /**< WDOG3 */
1546     kXRDC2_Periph_WDOG2             = XRDC2_MAKE_PERIPH(0, 13 ), /**< WDOG2 */
1547     kXRDC2_Periph_WDOG1             = XRDC2_MAKE_PERIPH(0, 12 ), /**< WDOG1 */
1548     kXRDC2_Periph_EWM               = XRDC2_MAKE_PERIPH(0, 11 ), /**< EWM */
1549     kXRDC2_Periph_FLEXRAM           = XRDC2_MAKE_PERIPH(0, 10 ), /**< FLEXRAM */
1550     kXRDC2_Periph_XECC_SEMC         = XRDC2_MAKE_PERIPH(0, 9  ), /**< XECC_SEMC */
1551     kXRDC2_Periph_XECC_FLEXSPI2     = XRDC2_MAKE_PERIPH(0, 8  ), /**< XECC_FLEXSPI2 */
1552     kXRDC2_Periph_XECC_FLEXSPI1     = XRDC2_MAKE_PERIPH(0, 7  ), /**< XECC_FLEXSPI1 */
1553     kXRDC2_Periph_MECC2             = XRDC2_MAKE_PERIPH(0, 6  ), /**< MECC2 */
1554     kXRDC2_Periph_MECC1             = XRDC2_MAKE_PERIPH(0, 5  ), /**< MECC1 */
1555     kXRDC2_Periph_MTR               = XRDC2_MAKE_PERIPH(0, 4  ), /**< MTR */
1556     kXRDC2_Periph_SFA               = XRDC2_MAKE_PERIPH(0, 3  ), /**< SFA */
1557     kXRDC2_Periph_CAAM_DEBUG_3      = XRDC2_MAKE_PERIPH(1, 51 ), /**< CAAM_DEBUG_3 */
1558     kXRDC2_Periph_CAAM_DEBUG_2      = XRDC2_MAKE_PERIPH(1, 50 ), /**< CAAM_DEBUG_2 */
1559     kXRDC2_Periph_CAAM_DEBUG_1      = XRDC2_MAKE_PERIPH(1, 49 ), /**< CAAM_DEBUG_1 */
1560     kXRDC2_Periph_CAAM_DEBUG_0      = XRDC2_MAKE_PERIPH(1, 48 ), /**< CAAM_DEBUG_0 */
1561     kXRDC2_Periph_CAAM_RTIC_3       = XRDC2_MAKE_PERIPH(1, 43 ), /**< CAAM_RTIC_3 */
1562     kXRDC2_Periph_CAAM_RTIC_2       = XRDC2_MAKE_PERIPH(1, 42 ), /**< CAAM_RTIC_2 */
1563     kXRDC2_Periph_CAAM_RTIC_1       = XRDC2_MAKE_PERIPH(1, 41 ), /**< CAAM_RTIC_1 */
1564     kXRDC2_Periph_CAAM_RTIC_0       = XRDC2_MAKE_PERIPH(1, 40 ), /**< CAAM_RTIC_0 */
1565     kXRDC2_Periph_CAAM_JR3_3        = XRDC2_MAKE_PERIPH(1, 35 ), /**< CAAM_JR3_3 */
1566     kXRDC2_Periph_CAAM_JR3_2        = XRDC2_MAKE_PERIPH(1, 34 ), /**< CAAM_JR3_2 */
1567     kXRDC2_Periph_CAAM_JR3_1        = XRDC2_MAKE_PERIPH(1, 33 ), /**< CAAM_JR3_1 */
1568     kXRDC2_Periph_CAAM_JR3_0        = XRDC2_MAKE_PERIPH(1, 32 ), /**< CAAM_JR3_0 */
1569     kXRDC2_Periph_CAAM_JR2_3        = XRDC2_MAKE_PERIPH(1, 31 ), /**< CAAM_JR2_3 */
1570     kXRDC2_Periph_CAAM_JR2_2        = XRDC2_MAKE_PERIPH(1, 30 ), /**< CAAM_JR2_2 */
1571     kXRDC2_Periph_CAAM_JR2_1        = XRDC2_MAKE_PERIPH(1, 29 ), /**< CAAM_JR2_1 */
1572     kXRDC2_Periph_CAAM_JR2_0        = XRDC2_MAKE_PERIPH(1, 28 ), /**< CAAM_JR2_0 */
1573     kXRDC2_Periph_CAAM_JR1_3        = XRDC2_MAKE_PERIPH(1, 27 ), /**< CAAM_JR1_3 */
1574     kXRDC2_Periph_CAAM_JR1_2        = XRDC2_MAKE_PERIPH(1, 26 ), /**< CAAM_JR1_2 */
1575     kXRDC2_Periph_CAAM_JR1_1        = XRDC2_MAKE_PERIPH(1, 25 ), /**< CAAM_JR1_1 */
1576     kXRDC2_Periph_CAAM_JR1_0        = XRDC2_MAKE_PERIPH(1, 24 ), /**< CAAM_JR1_0 */
1577     kXRDC2_Periph_CAAM_JR0_3        = XRDC2_MAKE_PERIPH(1, 23 ), /**< CAAM_JR0_3 */
1578     kXRDC2_Periph_CAAM_JR0_2        = XRDC2_MAKE_PERIPH(1, 22 ), /**< CAAM_JR0_2 */
1579     kXRDC2_Periph_CAAM_JR0_1        = XRDC2_MAKE_PERIPH(1, 21 ), /**< CAAM_JR0_1 */
1580     kXRDC2_Periph_CAAM_JR0_0        = XRDC2_MAKE_PERIPH(1, 20 ), /**< CAAM_JR0_0 */
1581     kXRDC2_Periph_CAAM_GENERAL_3    = XRDC2_MAKE_PERIPH(1, 19 ), /**< CAAM_GENERAL_3 */
1582     kXRDC2_Periph_CAAM_GENERAL_2    = XRDC2_MAKE_PERIPH(1, 18 ), /**< CAAM_GENERAL_2 */
1583     kXRDC2_Periph_CAAM_GENERAL_1    = XRDC2_MAKE_PERIPH(1, 17 ), /**< CAAM_GENERAL_1 */
1584     kXRDC2_Periph_CAAM_GENERAL_0    = XRDC2_MAKE_PERIPH(1, 16 ), /**< CAAM_GENERAL_0 */
1585     kXRDC2_Periph_ENET_QOS          = XRDC2_MAKE_PERIPH(1, 15 ), /**< ENET_QOS */
1586     kXRDC2_Periph_USBPHY2           = XRDC2_MAKE_PERIPH(1, 14 ), /**< USBPHY2 */
1587     kXRDC2_Periph_USBPHY1           = XRDC2_MAKE_PERIPH(1, 13 ), /**< USBPHY1 */
1588     kXRDC2_Periph_USB_OTG           = XRDC2_MAKE_PERIPH(1, 12 ), /**< USB_OTG */
1589     kXRDC2_Periph_USB_OTG2          = XRDC2_MAKE_PERIPH(1, 11 ), /**< USB_OTG2 */
1590     kXRDC2_Periph_USB_PL301         = XRDC2_MAKE_PERIPH(1, 10 ), /**< USB_PL301 */
1591     kXRDC2_Periph_ENET              = XRDC2_MAKE_PERIPH(1, 9  ), /**< ENET */
1592     kXRDC2_Periph_ENET_1G           = XRDC2_MAKE_PERIPH(1, 8  ), /**< ENET_1G */
1593     kXRDC2_Periph_USDHC2            = XRDC2_MAKE_PERIPH(1, 7  ), /**< USDHC2 */
1594     kXRDC2_Periph_USDHC1            = XRDC2_MAKE_PERIPH(1, 6  ), /**< USDHC1 */
1595     kXRDC2_Periph_ASRC              = XRDC2_MAKE_PERIPH(1, 5  ), /**< ASRC */
1596     kXRDC2_Periph_SAI3              = XRDC2_MAKE_PERIPH(1, 3  ), /**< SAI3 */
1597     kXRDC2_Periph_SAI2              = XRDC2_MAKE_PERIPH(1, 2  ), /**< SAI2 */
1598     kXRDC2_Periph_SAI1              = XRDC2_MAKE_PERIPH(1, 1  ), /**< SAI1 */
1599     kXRDC2_Periph_SPDIF             = XRDC2_MAKE_PERIPH(1, 0  ), /**< SPDIF */
1600     kXRDC2_Periph_VIDEO_MUX         = XRDC2_MAKE_PERIPH(2, 6  ), /**< VIDEO_MUX */
1601     kXRDC2_Periph_PXP               = XRDC2_MAKE_PERIPH(2, 5  ), /**< PXP */
1602     kXRDC2_Periph_MIPI_CSI          = XRDC2_MAKE_PERIPH(2, 4  ), /**< MIPI_CSI */
1603     kXRDC2_Periph_MIPI_DSI          = XRDC2_MAKE_PERIPH(2, 3  ), /**< MIPI_DSI */
1604     kXRDC2_Periph_LCDIFV2           = XRDC2_MAKE_PERIPH(2, 2  ), /**< LCDIFV2 */
1605     kXRDC2_Periph_LCDIF             = XRDC2_MAKE_PERIPH(2, 1  ), /**< LCDIF */
1606     kXRDC2_Periph_CSI               = XRDC2_MAKE_PERIPH(2, 0  ), /**< CSI */
1607     kXRDC2_Periph_XRDC2_MGR_M7_3    = XRDC2_MAKE_PERIPH(3, 59 ), /**< XRDC2_MGR_M7_3 */
1608     kXRDC2_Periph_XRDC2_MGR_M7_2    = XRDC2_MAKE_PERIPH(3, 58 ), /**< XRDC2_MGR_M7_2 */
1609     kXRDC2_Periph_XRDC2_MGR_M7_1    = XRDC2_MAKE_PERIPH(3, 57 ), /**< XRDC2_MGR_M7_1 */
1610     kXRDC2_Periph_XRDC2_MGR_M7_0    = XRDC2_MAKE_PERIPH(3, 56 ), /**< XRDC2_MGR_M7_0 */
1611     kXRDC2_Periph_XRDC2_MGR_M4_3    = XRDC2_MAKE_PERIPH(3, 55 ), /**< XRDC2_MGR_M4_3 */
1612     kXRDC2_Periph_XRDC2_MGR_M4_2    = XRDC2_MAKE_PERIPH(3, 54 ), /**< XRDC2_MGR_M4_2 */
1613     kXRDC2_Periph_XRDC2_MGR_M4_1    = XRDC2_MAKE_PERIPH(3, 53 ), /**< XRDC2_MGR_M4_1 */
1614     kXRDC2_Periph_XRDC2_MGR_M4_0    = XRDC2_MAKE_PERIPH(3, 52 ), /**< XRDC2_MGR_M4_0 */
1615     kXRDC2_Periph_SEMA2             = XRDC2_MAKE_PERIPH(3, 51 ), /**< SEMA2 */
1616     kXRDC2_Periph_SEMA_HS           = XRDC2_MAKE_PERIPH(3, 50 ), /**< SEMA_HS */
1617     kXRDC2_Periph_CCM_1             = XRDC2_MAKE_PERIPH(3, 49 ), /**< CCM_1 */
1618     kXRDC2_Periph_CCM_0             = XRDC2_MAKE_PERIPH(3, 48 ), /**< CCM_0 */
1619     kXRDC2_Periph_SSARC_LP          = XRDC2_MAKE_PERIPH(3, 46 ), /**< SSARC_LP */
1620     kXRDC2_Periph_SSARC_HP          = XRDC2_MAKE_PERIPH(3, 45 ), /**< SSARC_HP */
1621     kXRDC2_Periph_PIT2              = XRDC2_MAKE_PERIPH(3, 44 ), /**< PIT2 */
1622     kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ), /**< OCOTP_CTRL_WRAPPER */
1623     kXRDC2_Periph_DCDC              = XRDC2_MAKE_PERIPH(3, 42 ), /**< DCDC */
1624     kXRDC2_Periph_ROMCP             = XRDC2_MAKE_PERIPH(3, 41 ), /**< ROMCP */
1625     kXRDC2_Periph_GPIO13            = XRDC2_MAKE_PERIPH(3, 40 ), /**< GPIO13 */
1626     kXRDC2_Periph_SNVS_SRAM         = XRDC2_MAKE_PERIPH(3, 39 ), /**< SNVS_SRAM */
1627     kXRDC2_Periph_IOMUXC_SNVS_GPR   = XRDC2_MAKE_PERIPH(3, 38 ), /**< IOMUXC_SNVS_GPR */
1628     kXRDC2_Periph_IOMUXC_SNVS       = XRDC2_MAKE_PERIPH(3, 37 ), /**< IOMUXC_SNVS */
1629     kXRDC2_Periph_SNVS_HP_WRAPPER   = XRDC2_MAKE_PERIPH(3, 36 ), /**< SNVS_HP_WRAPPER */
1630     kXRDC2_Periph_PGMC              = XRDC2_MAKE_PERIPH(3, 34 ), /**< PGMC */
1631     kXRDC2_Periph_ANATOP            = XRDC2_MAKE_PERIPH(3, 33 ), /**< ANATOP */
1632     kXRDC2_Periph_KEY_MANAGER       = XRDC2_MAKE_PERIPH(3, 32 ), /**< KEY_MANAGER */
1633     kXRDC2_Periph_RDC               = XRDC2_MAKE_PERIPH(3, 30 ), /**< RDC */
1634     kXRDC2_Periph_GPIO12            = XRDC2_MAKE_PERIPH(3, 28 ), /**< GPIO12 */
1635     kXRDC2_Periph_GPIO11            = XRDC2_MAKE_PERIPH(3, 27 ), /**< GPIO11 */
1636     kXRDC2_Periph_GPIO10            = XRDC2_MAKE_PERIPH(3, 26 ), /**< GPIO10 */
1637     kXRDC2_Periph_GPIO9             = XRDC2_MAKE_PERIPH(3, 25 ), /**< GPIO9 */
1638     kXRDC2_Periph_GPIO8             = XRDC2_MAKE_PERIPH(3, 24 ), /**< GPIO8 */
1639     kXRDC2_Periph_GPIO7             = XRDC2_MAKE_PERIPH(3, 23 ), /**< GPIO7 */
1640     kXRDC2_Periph_MU_B              = XRDC2_MAKE_PERIPH(3, 19 ), /**< MU_B */
1641     kXRDC2_Periph_MU_A              = XRDC2_MAKE_PERIPH(3, 18 ), /**< MU_A */
1642     kXRDC2_Periph_SEMA1             = XRDC2_MAKE_PERIPH(3, 17 ), /**< SEMA1 */
1643     kXRDC2_Periph_SAI4              = XRDC2_MAKE_PERIPH(3, 16 ), /**< SAI4 */
1644     kXRDC2_Periph_CAN3              = XRDC2_MAKE_PERIPH(3, 15 ), /**< CAN3 */
1645     kXRDC2_Periph_LPI2C6            = XRDC2_MAKE_PERIPH(3, 14 ), /**< LPI2C6 */
1646     kXRDC2_Periph_LPI2C5            = XRDC2_MAKE_PERIPH(3, 13 ), /**< LPI2C5 */
1647     kXRDC2_Periph_LPSPI6            = XRDC2_MAKE_PERIPH(3, 12 ), /**< LPSPI6 */
1648     kXRDC2_Periph_LPSPI5            = XRDC2_MAKE_PERIPH(3, 11 ), /**< LPSPI5 */
1649     kXRDC2_Periph_LPUART12          = XRDC2_MAKE_PERIPH(3, 10 ), /**< LPUART12 */
1650     kXRDC2_Periph_LPUART11          = XRDC2_MAKE_PERIPH(3, 9  ), /**< LPUART11 */
1651     kXRDC2_Periph_MIC               = XRDC2_MAKE_PERIPH(3, 8  ), /**< MIC */
1652     kXRDC2_Periph_DMA_CH_MUX_LPSR   = XRDC2_MAKE_PERIPH(3, 6  ), /**< DMA_CH_MUX_LPSR */
1653     kXRDC2_Periph_EDMA_LPSR         = XRDC2_MAKE_PERIPH(3, 5  ), /**< EDMA_LPSR */
1654     kXRDC2_Periph_WDOG4             = XRDC2_MAKE_PERIPH(3, 4  ), /**< WDOG4 */
1655     kXRDC2_Periph_IOMUXC_LPSR_GPR   = XRDC2_MAKE_PERIPH(3, 3  ), /**< IOMUXC_LPSR_GPR */
1656     kXRDC2_Periph_IOMUXC_LPSR       = XRDC2_MAKE_PERIPH(3, 2  ), /**< IOMUXC_LPSR */
1657     kXRDC2_Periph_SRC               = XRDC2_MAKE_PERIPH(3, 1  ), /**< SRC */
1658     kXRDC2_Periph_GPC               = XRDC2_MAKE_PERIPH(3, 0  ), /**< GPC */
1659     kXRDC2_Periph_GPU               = XRDC2_MAKE_PERIPH(4, 0  ), /**< GPU */
1660 } xrdc2_periph_t;
1661 
1662 /* @} */
1663 
1664 /*!
1665  * @addtogroup asrc_clock_source
1666  * @{
1667  */
1668 
1669 /*******************************************************************************
1670  * Definitions
1671  ******************************************************************************/
1672 
1673 /*!
1674  * @brief The ASRC clock source
1675  */
1676 
1677 typedef enum _asrc_clock_source
1678 {
1679     kASRC_ClockSourceNotAvalible    = -1,          /**< not avalible */
1680     kASRC_ClockSourceBitClock0_SAI1_TX = 0U,       /**< SAI1 TX */
1681     kASRC_ClockSourceBitClock1_SAI1_RX = 1U,       /**< SAI1 RX */
1682     kASRC_ClockSourceBitClock2_SAI2_TX = 2U,       /**< SAI2 TX */
1683     kASRC_ClockSourceBitClock3_SAI2_RX = 3U,       /**< SAI2 RX */
1684     kASRC_ClockSourceBitClock4_SAI3_TX = 4U,       /**< SAI3 TX */
1685     kASRC_ClockSourceBitClock5_SAI3_RX = 5U,       /**< SAI3 RX */
1686     kASRC_ClockSourceBitClock6_SAI4_TX = 6U,       /**< SAI4 TX */
1687     kASRC_ClockSourceBitClock7_SAI4_RX = 7U,       /**< SAI4 RX */
1688     kASRC_ClockSourceBitClock8_SPDIF_TX = 8U,      /**< SPDIF TX */
1689     kASRC_ClockSourceBitClock9_SPDIF_RX = 9U,      /**< SPDIF RX */
1690     kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */
1691     kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */
1692     kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */
1693     kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */
1694     kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */
1695 } asrc_clock_source_t;
1696 
1697 /*!
1698  * @addtogroup edma_request
1699  * @{
1700  */
1701 
1702 /*******************************************************************************
1703  * Definitions
1704  ******************************************************************************/
1705 
1706 /*!
1707  * @brief Structure for the DMA hardware request
1708  *
1709  * Defines the structure for the DMA hardware request collections. The user can configure the
1710  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
1711  * of the hardware request varies according  to the to SoC.
1712  */
1713 typedef enum _dma_request_source
1714 {
1715     kDmaRequestMuxFlexIO1Request2Request3 = 1|0x100U, /**< FlexIO1 Request2 and Request3 */
1716     kDmaRequestMuxFlexIO1Request4Request5 = 2|0x100U, /**< FlexIO1 Request4 and Request5 */
1717     kDmaRequestMuxFlexIO1Request6Request7 = 3|0x100U, /**< FlexIO1 Request6 and Request7 */
1718     kDmaRequestMuxFlexIO2Request0Request1 = 4|0x100U, /**< FlexIO2 Request0 and Request1 */
1719     kDmaRequestMuxFlexIO2Request2Request3 = 5|0x100U, /**< FlexIO2 Request2 and Request3 */
1720     kDmaRequestMuxFlexIO2Request4Request5 = 6|0x100U, /**< FlexIO2 Request4 and Request5 */
1721     kDmaRequestMuxFlexIO2Request6Request7 = 7|0x100U, /**< FlexIO2 Request6 and Request7 */
1722     kDmaRequestMuxLPUART1Tx         = 8|0x100U,    /**< LPUART1 Transmit */
1723     kDmaRequestMuxLPUART1Rx         = 9|0x100U,    /**< LPUART1 Receive */
1724     kDmaRequestMuxLPUART2Tx         = 10|0x100U,   /**< LPUART2 Transmit */
1725     kDmaRequestMuxLPUART2Rx         = 11|0x100U,   /**< LPUART2 Receive */
1726     kDmaRequestMuxLPUART3Tx         = 12|0x100U,   /**< LPUART3 Transmit */
1727     kDmaRequestMuxLPUART3Rx         = 13|0x100U,   /**< LPUART3 Receive */
1728     kDmaRequestMuxLPUART4Tx         = 14|0x100U,   /**< LPUART4 Transmit */
1729     kDmaRequestMuxLPUART4Rx         = 15|0x100U,   /**< LPUART4 Receive */
1730     kDmaRequestMuxLPUART5Tx         = 16|0x100U,   /**< LPUART5 Transmit */
1731     kDmaRequestMuxLPUART5Rx         = 17|0x100U,   /**< LPUART5 Receive */
1732     kDmaRequestMuxLPUART6Tx         = 18|0x100U,   /**< LPUART6 Transmit */
1733     kDmaRequestMuxLPUART6Rx         = 19|0x100U,   /**< LPUART6 Receive */
1734     kDmaRequestMuxLPUART7Tx         = 20|0x100U,   /**< LPUART7 Transmit */
1735     kDmaRequestMuxLPUART7Rx         = 21|0x100U,   /**< LPUART7 Receive */
1736     kDmaRequestMuxLPUART8Tx         = 22|0x100U,   /**< LPUART8 Transmit */
1737     kDmaRequestMuxLPUART8Rx         = 23|0x100U,   /**< LPUART8 Receive */
1738     kDmaRequestMuxLPUART9Tx         = 24|0x100U,   /**< LPUART9 Transmit */
1739     kDmaRequestMuxLPUART9Rx         = 25|0x100U,   /**< LPUART9 Receive */
1740     kDmaRequestMuxLPUART10Tx        = 26|0x100U,   /**< LPUART10 Transmit */
1741     kDmaRequestMuxLPUART10Rx        = 27|0x100U,   /**< LPUART10 Receive */
1742     kDmaRequestMuxLPUART11Tx        = 28|0x100U,   /**< LPUART11 Transmit */
1743     kDmaRequestMuxLPUART11Rx        = 29|0x100U,   /**< LPUART11 Receive */
1744     kDmaRequestMuxLPUART12Tx        = 30|0x100U,   /**< LPUART12 Transmit */
1745     kDmaRequestMuxLPUART12Rx        = 31|0x100U,   /**< LPUART12 Receive */
1746     kDmaRequestMuxCSI               = 32|0x100U,   /**< CSI */
1747     kDmaRequestMuxPxp               = 33|0x100U,   /**< PXP */
1748     kDmaRequestMuxeLCDIF            = 34|0x100U,   /**< eLCDIF */
1749     kDmaRequestMuxLCDIFv2           = 35|0x100U,   /**< LCDIFv2 */
1750     kDmaRequestMuxLPSPI1Rx          = 36|0x100U,   /**< LPSPI1 Receive */
1751     kDmaRequestMuxLPSPI1Tx          = 37|0x100U,   /**< LPSPI1 Transmit */
1752     kDmaRequestMuxLPSPI2Rx          = 38|0x100U,   /**< LPSPI2 Receive */
1753     kDmaRequestMuxLPSPI2Tx          = 39|0x100U,   /**< LPSPI2 Transmit */
1754     kDmaRequestMuxLPSPI3Rx          = 40|0x100U,   /**< LPSPI3 Receive */
1755     kDmaRequestMuxLPSPI3Tx          = 41|0x100U,   /**< LPSPI3 Transmit */
1756     kDmaRequestMuxLPSPI4Rx          = 42|0x100U,   /**< LPSPI4 Receive */
1757     kDmaRequestMuxLPSPI4Tx          = 43|0x100U,   /**< LPSPI4 Transmit */
1758     kDmaRequestMuxLPSPI5Rx          = 44|0x100U,   /**< LPSPI5 Receive */
1759     kDmaRequestMuxLPSPI5Tx          = 45|0x100U,   /**< LPSPI5 Transmit */
1760     kDmaRequestMuxLPSPI6Rx          = 46|0x100U,   /**< LPSPI6 Receive */
1761     kDmaRequestMuxLPSPI6Tx          = 47|0x100U,   /**< LPSPI6 Transmit */
1762     kDmaRequestMuxLPI2C1            = 48|0x100U,   /**< LPI2C1 */
1763     kDmaRequestMuxLPI2C2            = 49|0x100U,   /**< LPI2C2 */
1764     kDmaRequestMuxLPI2C3            = 50|0x100U,   /**< LPI2C3 */
1765     kDmaRequestMuxLPI2C4            = 51|0x100U,   /**< LPI2C4 */
1766     kDmaRequestMuxLPI2C5            = 52|0x100U,   /**< LPI2C5 */
1767     kDmaRequestMuxLPI2C6            = 53|0x100U,   /**< LPI2C6 */
1768     kDmaRequestMuxSai1Rx            = 54|0x100U,   /**< SAI1 Receive */
1769     kDmaRequestMuxSai1Tx            = 55|0x100U,   /**< SAI1 Transmit */
1770     kDmaRequestMuxSai2Rx            = 56|0x100U,   /**< SAI2 Receive */
1771     kDmaRequestMuxSai2Tx            = 57|0x100U,   /**< SAI2 Transmit */
1772     kDmaRequestMuxSai3Rx            = 58|0x100U,   /**< SAI3 Receive */
1773     kDmaRequestMuxSai3Tx            = 59|0x100U,   /**< SAI3 Transmit */
1774     kDmaRequestMuxSai4Rx            = 60|0x100U,   /**< SAI4 Receive */
1775     kDmaRequestMuxSai4Tx            = 61|0x100U,   /**< SAI4 Transmit */
1776     kDmaRequestMuxSpdifRx           = 62|0x100U,   /**< SPDIF Receive */
1777     kDmaRequestMuxSpdifTx           = 63|0x100U,   /**< SPDIF Transmit */
1778     kDmaRequestMuxADC_ETC           = 64|0x100U,   /**< ADC_ETC */
1779     kDmaRequestMuxFlexIO1Request0Request1 = 65|0x100U, /**< FlexIO1 Request0 and Request1 */
1780     kDmaRequestMuxADC1              = 66|0x100U,   /**< ADC1 */
1781     kDmaRequestMuxADC2              = 67|0x100U,   /**< ADC2 */
1782     kDmaRequestMuxACMP1             = 69|0x100U,   /**< ACMP1 */
1783     kDmaRequestMuxACMP2             = 70|0x100U,   /**< ACMP2 */
1784     kDmaRequestMuxACMP3             = 71|0x100U,   /**< ACMP3 */
1785     kDmaRequestMuxACMP4             = 72|0x100U,   /**< ACMP4 */
1786     kDmaRequestMuxFlexSPI1Rx        = 77|0x100U,   /**< FlexSPI1 Receive */
1787     kDmaRequestMuxFlexSPI1Tx        = 78|0x100U,   /**< FlexSPI1 Transmit */
1788     kDmaRequestMuxFlexSPI2Rx        = 79|0x100U,   /**< FlexSPI2 Receive */
1789     kDmaRequestMuxFlexSPI2Tx        = 80|0x100U,   /**< FlexSPI2 Transmit */
1790     kDmaRequestMuxXBAR1Request0     = 81|0x100U,   /**< XBAR1 Request 0 */
1791     kDmaRequestMuxXBAR1Request1     = 82|0x100U,   /**< XBAR1 Request 1 */
1792     kDmaRequestMuxXBAR1Request2     = 83|0x100U,   /**< XBAR1 Request 2 */
1793     kDmaRequestMuxXBAR1Request3     = 84|0x100U,   /**< XBAR1 Request 3 */
1794     kDmaRequestMuxFlexPWM1CaptureSub0 = 85|0x100U, /**< FlexPWM1 Capture sub-module0 */
1795     kDmaRequestMuxFlexPWM1CaptureSub1 = 86|0x100U, /**< FlexPWM1 Capture sub-module1 */
1796     kDmaRequestMuxFlexPWM1CaptureSub2 = 87|0x100U, /**< FlexPWM1 Capture sub-module2 */
1797     kDmaRequestMuxFlexPWM1CaptureSub3 = 88|0x100U, /**< FlexPWM1 Capture sub-module3 */
1798     kDmaRequestMuxFlexPWM1ValueSub0 = 89|0x100U,   /**< FlexPWM1 Value sub-module 0 */
1799     kDmaRequestMuxFlexPWM1ValueSub1 = 90|0x100U,   /**< FlexPWM1 Value sub-module 1 */
1800     kDmaRequestMuxFlexPWM1ValueSub2 = 91|0x100U,   /**< FlexPWM1 Value sub-module 2 */
1801     kDmaRequestMuxFlexPWM1ValueSub3 = 92|0x100U,   /**< FlexPWM1 Value sub-module 3 */
1802     kDmaRequestMuxFlexPWM2CaptureSub0 = 93|0x100U, /**< FlexPWM2 Capture sub-module0 */
1803     kDmaRequestMuxFlexPWM2CaptureSub1 = 94|0x100U, /**< FlexPWM2 Capture sub-module1 */
1804     kDmaRequestMuxFlexPWM2CaptureSub2 = 95|0x100U, /**< FlexPWM2 Capture sub-module2 */
1805     kDmaRequestMuxFlexPWM2CaptureSub3 = 96|0x100U, /**< FlexPWM2 Capture sub-module3 */
1806     kDmaRequestMuxFlexPWM2ValueSub0 = 97|0x100U,   /**< FlexPWM2 Value sub-module 0 */
1807     kDmaRequestMuxFlexPWM2ValueSub1 = 98|0x100U,   /**< FlexPWM2 Value sub-module 1 */
1808     kDmaRequestMuxFlexPWM2ValueSub2 = 99|0x100U,   /**< FlexPWM2 Value sub-module 2 */
1809     kDmaRequestMuxFlexPWM2ValueSub3 = 100|0x100U,  /**< FlexPWM2 Value sub-module 3 */
1810     kDmaRequestMuxFlexPWM3CaptureSub0 = 101|0x100U, /**< FlexPWM3 Capture sub-module0 */
1811     kDmaRequestMuxFlexPWM3CaptureSub1 = 102|0x100U, /**< FlexPWM3 Capture sub-module1 */
1812     kDmaRequestMuxFlexPWM3CaptureSub2 = 103|0x100U, /**< FlexPWM3 Capture sub-module2 */
1813     kDmaRequestMuxFlexPWM3CaptureSub3 = 104|0x100U, /**< FlexPWM3 Capture sub-module3 */
1814     kDmaRequestMuxFlexPWM3ValueSub0 = 105|0x100U,  /**< FlexPWM3 Value sub-module 0 */
1815     kDmaRequestMuxFlexPWM3ValueSub1 = 106|0x100U,  /**< FlexPWM3 Value sub-module 1 */
1816     kDmaRequestMuxFlexPWM3ValueSub2 = 107|0x100U,  /**< FlexPWM3 Value sub-module 2 */
1817     kDmaRequestMuxFlexPWM3ValueSub3 = 108|0x100U,  /**< FlexPWM3 Value sub-module 3 */
1818     kDmaRequestMuxFlexPWM4CaptureSub0 = 109|0x100U, /**< FlexPWM4 Capture sub-module0 */
1819     kDmaRequestMuxFlexPWM4CaptureSub1 = 110|0x100U, /**< FlexPWM4 Capture sub-module1 */
1820     kDmaRequestMuxFlexPWM4CaptureSub2 = 111|0x100U, /**< FlexPWM4 Capture sub-module2 */
1821     kDmaRequestMuxFlexPWM4CaptureSub3 = 112|0x100U, /**< FlexPWM4 Capture sub-module3 */
1822     kDmaRequestMuxFlexPWM4ValueSub0 = 113|0x100U,  /**< FlexPWM4 Value sub-module 0 */
1823     kDmaRequestMuxFlexPWM4ValueSub1 = 114|0x100U,  /**< FlexPWM4 Value sub-module 1 */
1824     kDmaRequestMuxFlexPWM4ValueSub2 = 115|0x100U,  /**< FlexPWM4 Value sub-module 2 */
1825     kDmaRequestMuxFlexPWM4ValueSub3 = 116|0x100U,  /**< FlexPWM4 Value sub-module 3 */
1826     kDmaRequestMuxQTIMER1CaptTimer0 = 133|0x100U,  /**< TMR1 Capture timer 0 */
1827     kDmaRequestMuxQTIMER1CaptTimer1 = 134|0x100U,  /**< TMR1 Capture timer 1 */
1828     kDmaRequestMuxQTIMER1CaptTimer2 = 135|0x100U,  /**< TMR1 Capture timer 2 */
1829     kDmaRequestMuxQTIMER1CaptTimer3 = 136|0x100U,  /**< TMR1 Capture timer 3 */
1830     kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 137|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
1831     kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 138|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
1832     kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 139|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
1833     kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 140|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
1834     kDmaRequestMuxQTIMER2CaptTimer0 = 141|0x100U,  /**< TMR2 Capture timer 0 */
1835     kDmaRequestMuxQTIMER2CaptTimer1 = 142|0x100U,  /**< TMR2 Capture timer 1 */
1836     kDmaRequestMuxQTIMER2CaptTimer2 = 143|0x100U,  /**< TMR2 Capture timer 2 */
1837     kDmaRequestMuxQTIMER2CaptTimer3 = 144|0x100U,  /**< TMR2 Capture timer 3 */
1838     kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 145|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
1839     kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 146|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
1840     kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 147|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
1841     kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 148|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
1842     kDmaRequestMuxQTIMER3CaptTimer0 = 149|0x100U,  /**< TMR3 Capture timer 0 */
1843     kDmaRequestMuxQTIMER3CaptTimer1 = 150|0x100U,  /**< TMR3 Capture timer 1 */
1844     kDmaRequestMuxQTIMER3CaptTimer2 = 151|0x100U,  /**< TMR3 Capture timer 2 */
1845     kDmaRequestMuxQTIMER3CaptTimer3 = 152|0x100U,  /**< TMR3 Capture timer 3 */
1846     kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 153|0x100U, /**< TMR3 cmpld1 in timer 0 or cmpld2 in timer 1 */
1847     kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 154|0x100U, /**< TMR3 cmpld1 in timer 1 or cmpld2 in timer 0 */
1848     kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 155|0x100U, /**< TMR3 cmpld1 in timer 2 or cmpld2 in timer 3 */
1849     kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 156|0x100U, /**< TMR3 cmpld1 in timer 3 or cmpld2 in timer 2 */
1850     kDmaRequestMuxQTIMER4CaptTimer0 = 157|0x100U,  /**< TMR4 Capture timer 0 */
1851     kDmaRequestMuxQTIMER4CaptTimer1 = 158|0x100U,  /**< TMR4 Capture timer 1 */
1852     kDmaRequestMuxQTIMER4CaptTimer2 = 159|0x100U,  /**< TMR4 Capture timer 2 */
1853     kDmaRequestMuxQTIMER4CaptTimer3 = 160|0x100U,  /**< TMR4 Capture timer 3 */
1854     kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 161|0x100U, /**< TMR4 cmpld1 in timer 0 or cmpld2 in timer 1 */
1855     kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 162|0x100U, /**< TMR4 cmpld1 in timer 1 or cmpld2 in timer 0 */
1856     kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 163|0x100U, /**< TMR4 cmpld1 in timer 2 or cmpld2 in timer 3 */
1857     kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 164|0x100U, /**< TMR4 cmpld1 in timer 3 or cmpld2 in timer 2 */
1858     kDmaRequestMuxPdm               = 181|0x100U,  /**< PDM */
1859     kDmaRequestMuxEnetTimer0        = 182|0x100U,  /**< ENET Timer0 */
1860     kDmaRequestMuxEnetTimer1        = 183|0x100U,  /**< ENET Timer1 */
1861     kDmaRequestMuxEnet1GTimer0      = 184|0x100U,  /**< ENET 1G Timer0 */
1862     kDmaRequestMuxEnet1GTimer1      = 185|0x100U,  /**< ENET 1G Timer1 */
1863     kDmaRequestMuxCAN1              = 186|0x100U,  /**< CAN1 */
1864     kDmaRequestMuxCAN2              = 187|0x100U,  /**< CAN2 */
1865     kDmaRequestMuxCAN3              = 188|0x100U,  /**< CAN3 */
1866     kDmaRequestMuxDAC               = 189|0x100U,  /**< DAC */
1867     kDmaRequestMuxASRCRequest1      = 191|0x100U,  /**< ASRC request 1 pair A input request */
1868     kDmaRequestMuxASRCRequest2      = 192|0x100U,  /**< ASRC request 2 pair B input request */
1869     kDmaRequestMuxASRCRequest3      = 193|0x100U,  /**< ASRC request 3 pair C input request */
1870     kDmaRequestMuxASRCRequest4      = 194|0x100U,  /**< ASRC request 4 pair A output request */
1871     kDmaRequestMuxASRCRequest5      = 195|0x100U,  /**< ASRC request 5 pair B output request */
1872     kDmaRequestMuxASRCRequest6      = 196|0x100U,  /**< ASRC request 6 pair C output request */
1873     kDmaRequestMuxEmvsim1Tx         = 197|0x100U,  /**< Emvsim1 Transmit */
1874     kDmaRequestMuxEmvsim1Rx         = 198|0x100U,  /**< Emvsim1 Receive */
1875     kDmaRequestMuxEmvsim2Tx         = 199|0x100U,  /**< Emvsim2 Transmit */
1876     kDmaRequestMuxEmvsim2Rx         = 200|0x100U,  /**< Emvsim2 Receive */
1877     kDmaRequestMuxEnetQosTimer0     = 201|0x100U,  /**< ENET_QOS Timer0 */
1878     kDmaRequestMuxEnetQosTimer1     = 202|0x100U,  /**< ENET_QOS Timer1 */
1879 } dma_request_source_t;
1880 
1881 /* @} */
1882 
1883 /*!
1884  * @addtogroup iomuxc_pads
1885  * @{ */
1886 
1887 /*******************************************************************************
1888  * Definitions
1889 *******************************************************************************/
1890 
1891 /*!
1892  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
1893  *
1894  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
1895  */
1896 typedef enum _iomuxc_sw_mux_ctl_pad
1897 {
1898     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1899     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1900     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1901     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1902     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1903     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1904     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1905     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1906     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1907     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1908     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1909     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1910     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1911     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1912     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1913     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1914     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1915     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1916     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1917     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1918     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1919     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1920     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1921     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1922     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1923     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1924     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1925     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1926     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1927     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1928     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1929     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1930     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1931     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1932     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1933     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1934     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1935     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1936     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1937     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1938     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1939     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1940     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1941     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1942     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1943     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1944     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1945     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1946     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1947     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1948     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1949     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1950     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1951     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1952     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1953     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1954     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1955     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1956     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1957     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1958     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1959     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1960     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1961     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1962     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1963     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1964     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1965     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1966     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1967     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1968     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1969     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1970     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1971     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1972     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1973     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1974     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1975     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1976     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1977     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1978     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1979     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1980     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1981     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1982     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1983     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1984     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1985     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1986     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1987     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1988     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1989     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1990     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1991     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1992     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1993     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1994     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1995     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1996     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1997     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1998     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1999     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2000     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2001     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2002     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2003     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2004     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2005     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2006     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2007     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2008     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2009     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2010     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2011     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2012     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2013     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2014     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2015     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
2016     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
2017     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
2018     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
2019     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
2020     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
2021     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
2022     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
2023     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
2024     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
2025     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
2026     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
2027     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
2028     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
2029     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
2030     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
2031     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
2032     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
2033     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
2034     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
2035     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
2036     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
2037     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
2038     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
2039     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_MUX_CTL_PAD index */
2040     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_MUX_CTL_PAD index */
2041     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_MUX_CTL_PAD index */
2042     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_MUX_CTL_PAD index */
2043 } iomuxc_sw_mux_ctl_pad_t;
2044 
2045 /* @} */
2046 
2047 /*!
2048  * @addtogroup iomuxc_pads
2049  * @{ */
2050 
2051 /*******************************************************************************
2052  * Definitions
2053 *******************************************************************************/
2054 
2055 /*!
2056  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
2057  *
2058  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
2059  */
2060 typedef enum _iomuxc_sw_pad_ctl_pad
2061 {
2062     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2063     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2064     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2065     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2066     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2067     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2068     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2069     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2070     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2071     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2072     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2073     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2074     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2075     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2076     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2077     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2078     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2079     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2080     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2081     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2082     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2083     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2084     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2085     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2086     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2087     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2088     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2089     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2090     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2091     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2092     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2093     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2094     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2095     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2096     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2097     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2098     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2099     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2100     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2101     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2102     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2103     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2104     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2105     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2106     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2107     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2108     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2109     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2110     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2111     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2112     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2113     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2114     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2115     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2116     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2117     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2118     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2119     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2120     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2121     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2122     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2123     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2124     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2125     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2126     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2127     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2128     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2129     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2130     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2131     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2132     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2133     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2134     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2135     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2136     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2137     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2138     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2139     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2140     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2141     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2142     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2143     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2144     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2145     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2146     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2147     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2148     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2149     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2150     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2151     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2152     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2153     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2154     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2155     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2156     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2157     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2158     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2159     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2160     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2161     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2162     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2163     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2164     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2165     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2166     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2167     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2168     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2169     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2170     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2171     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2172     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2173     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2174     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2175     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2176     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2177     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2178     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2179     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
2180     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
2181     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
2182     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
2183     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
2184     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
2185     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
2186     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
2187     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
2188     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
2189     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
2190     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
2191     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
2192     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
2193     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
2194     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
2195     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
2196     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
2197     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
2198     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
2199     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
2200     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
2201     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
2202     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
2203     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
2204     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
2205     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
2206     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
2207 } iomuxc_sw_pad_ctl_pad_t;
2208 
2209 /* @} */
2210 
2211 /*!
2212  * @brief Enumeration for the IOMUXC select input
2213  *
2214  * Defines the enumeration for the IOMUXC select input collections.
2215  */
2216 typedef enum _iomuxc_select_input
2217 {
2218     kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U,         /**< IOMUXC select input index */
2219     kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U,         /**< IOMUXC select input index */
2220     kIOMUXC_CCM_ENET_QOS_REF_CLK_SELECT_INPUT = 2U, /**< IOMUXC select input index */
2221     kIOMUXC_CCM_ENET_QOS_TX_CLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
2222     kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U,   /**< IOMUXC select input index */
2223     kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U,      /**< IOMUXC select input index */
2224     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U,  /**< IOMUXC select input index */
2225     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U,  /**< IOMUXC select input index */
2226     kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U,      /**< IOMUXC select input index */
2227     kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U,     /**< IOMUXC select input index */
2228     kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U,    /**< IOMUXC select input index */
2229     kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U, /**< IOMUXC select input index */
2230     kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U,  /**< IOMUXC select input index */
2231     kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
2232     kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U, /**< IOMUXC select input index */
2233     kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U, /**< IOMUXC select input index */
2234     kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U, /**< IOMUXC select input index */
2235     kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U, /**< IOMUXC select input index */
2236     kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U,  /**< IOMUXC select input index */
2237     kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
2238     kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U, /**< IOMUXC select input index */
2239     kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 21U, /**< IOMUXC select input index */
2240     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 = 22U, /**< IOMUXC select input index */
2241     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 = 23U, /**< IOMUXC select input index */
2242     kIOMUXC_ENET_QOS_PHY_RXDV_I_SELECT_INPUT = 24U, /**< IOMUXC select input index */
2243     kIOMUXC_ENET_QOS_PHY_RXER_I_SELECT_INPUT = 25U, /**< IOMUXC select input index */
2244     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U,    /**< IOMUXC select input index */
2245     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U,    /**< IOMUXC select input index */
2246     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U,    /**< IOMUXC select input index */
2247     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U,    /**< IOMUXC select input index */
2248     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U,    /**< IOMUXC select input index */
2249     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U,    /**< IOMUXC select input index */
2250     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U,    /**< IOMUXC select input index */
2251     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U,    /**< IOMUXC select input index */
2252     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U,    /**< IOMUXC select input index */
2253     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U,    /**< IOMUXC select input index */
2254     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U,    /**< IOMUXC select input index */
2255     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U,    /**< IOMUXC select input index */
2256     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U,    /**< IOMUXC select input index */
2257     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U,    /**< IOMUXC select input index */
2258     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U,    /**< IOMUXC select input index */
2259     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U,    /**< IOMUXC select input index */
2260     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U,    /**< IOMUXC select input index */
2261     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U,    /**< IOMUXC select input index */
2262     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U,    /**< IOMUXC select input index */
2263     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U,    /**< IOMUXC select input index */
2264     kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U,  /**< IOMUXC select input index */
2265     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U, /**< IOMUXC select input index */
2266     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U, /**< IOMUXC select input index */
2267     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U, /**< IOMUXC select input index */
2268     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U, /**< IOMUXC select input index */
2269     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U, /**< IOMUXC select input index */
2270     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U, /**< IOMUXC select input index */
2271     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U, /**< IOMUXC select input index */
2272     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U, /**< IOMUXC select input index */
2273     kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U,  /**< IOMUXC select input index */
2274     kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U,  /**< IOMUXC select input index */
2275     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U, /**< IOMUXC select input index */
2276     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U, /**< IOMUXC select input index */
2277     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U, /**< IOMUXC select input index */
2278     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U, /**< IOMUXC select input index */
2279     kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U,  /**< IOMUXC select input index */
2280     kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U,        /**< IOMUXC select input index */
2281     kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U,        /**< IOMUXC select input index */
2282     kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U,         /**< IOMUXC select input index */
2283     kIOMUXC_KPP_COL_SELECT_INPUT_6  = 65U,         /**< IOMUXC select input index */
2284     kIOMUXC_KPP_COL_SELECT_INPUT_7  = 66U,         /**< IOMUXC select input index */
2285     kIOMUXC_KPP_ROW_SELECT_INPUT_6  = 67U,         /**< IOMUXC select input index */
2286     kIOMUXC_KPP_ROW_SELECT_INPUT_7  = 68U,         /**< IOMUXC select input index */
2287     kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U,   /**< IOMUXC select input index */
2288     kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U,   /**< IOMUXC select input index */
2289     kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U,   /**< IOMUXC select input index */
2290     kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U,   /**< IOMUXC select input index */
2291     kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U,   /**< IOMUXC select input index */
2292     kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U,   /**< IOMUXC select input index */
2293     kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U,   /**< IOMUXC select input index */
2294     kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U,   /**< IOMUXC select input index */
2295     kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U, /**< IOMUXC select input index */
2296     kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U,   /**< IOMUXC select input index */
2297     kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U,   /**< IOMUXC select input index */
2298     kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U,   /**< IOMUXC select input index */
2299     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U, /**< IOMUXC select input index */
2300     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U, /**< IOMUXC select input index */
2301     kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U,   /**< IOMUXC select input index */
2302     kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U,   /**< IOMUXC select input index */
2303     kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U,   /**< IOMUXC select input index */
2304     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U, /**< IOMUXC select input index */
2305     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U, /**< IOMUXC select input index */
2306     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U, /**< IOMUXC select input index */
2307     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U, /**< IOMUXC select input index */
2308     kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U,   /**< IOMUXC select input index */
2309     kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U,   /**< IOMUXC select input index */
2310     kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U,   /**< IOMUXC select input index */
2311     kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U, /**< IOMUXC select input index */
2312     kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U,   /**< IOMUXC select input index */
2313     kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U,   /**< IOMUXC select input index */
2314     kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U,   /**< IOMUXC select input index */
2315     kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U, /**< IOMUXC select input index */
2316     kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U, /**< IOMUXC select input index */
2317     kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U, /**< IOMUXC select input index */
2318     kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U, /**< IOMUXC select input index */
2319     kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U, /**< IOMUXC select input index */
2320     kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U, /**< IOMUXC select input index */
2321     kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U, /**< IOMUXC select input index */
2322     kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U, /**< IOMUXC select input index */
2323     kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U, /**< IOMUXC select input index */
2324     kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U, /**< IOMUXC select input index */
2325     kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U, /**< IOMUXC select input index */
2326     kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U, /**< IOMUXC select input index */
2327     kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U, /**< IOMUXC select input index */
2328     kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U, /**< IOMUXC select input index */
2329     kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U, /**< IOMUXC select input index */
2330     kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U, /**< IOMUXC select input index */
2331     kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U, /**< IOMUXC select input index */
2332     kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U, /**< IOMUXC select input index */
2333     kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U, /**< IOMUXC select input index */
2334     kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U, /**< IOMUXC select input index */
2335     kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U, /**< IOMUXC select input index */
2336     kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U,   /**< IOMUXC select input index */
2337     kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U, /**< IOMUXC select input index */
2338     kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U,   /**< IOMUXC select input index */
2339     kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U,   /**< IOMUXC select input index */
2340     kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U,   /**< IOMUXC select input index */
2341     kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U,       /**< IOMUXC select input index */
2342     kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U, /**< IOMUXC select input index */
2343     kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U, /**< IOMUXC select input index */
2344     kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U,       /**< IOMUXC select input index */
2345     kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U, /**< IOMUXC select input index */
2346     kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U, /**< IOMUXC select input index */
2347     kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U,   /**< IOMUXC select input index */
2348     kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U,       /**< IOMUXC select input index */
2349     kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U,        /**< IOMUXC select input index */
2350     kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U,    /**< IOMUXC select input index */
2351     kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U,    /**< IOMUXC select input index */
2352     kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U, /**< IOMUXC select input index */
2353     kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U,  /**< IOMUXC select input index */
2354     kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U, /**< IOMUXC select input index */
2355     kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U,  /**< IOMUXC select input index */
2356     kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U,       /**< IOMUXC select input index */
2357     kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U,       /**< IOMUXC select input index */
2358     kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U,       /**< IOMUXC select input index */
2359     kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U,       /**< IOMUXC select input index */
2360     kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U,       /**< IOMUXC select input index */
2361     kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U,       /**< IOMUXC select input index */
2362     kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U,       /**< IOMUXC select input index */
2363     kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U,       /**< IOMUXC select input index */
2364     kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U,       /**< IOMUXC select input index */
2365     kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U,       /**< IOMUXC select input index */
2366     kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U,       /**< IOMUXC select input index */
2367     kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U,       /**< IOMUXC select input index */
2368     kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U,       /**< IOMUXC select input index */
2369     kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U,       /**< IOMUXC select input index */
2370     kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U,       /**< IOMUXC select input index */
2371     kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U,       /**< IOMUXC select input index */
2372 } iomuxc_select_input_t;
2373 
2374 
2375 /*!
2376  * @}
2377  */ /* end of group Mapping_Information */
2378 
2379 
2380 /* ----------------------------------------------------------------------------
2381    -- Device Peripheral Access Layer
2382    ---------------------------------------------------------------------------- */
2383 
2384 /*!
2385  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
2386  * @{
2387  */
2388 
2389 
2390 /*
2391 ** Start of section using anonymous unions
2392 */
2393 
2394 #if defined(__ARMCC_VERSION)
2395   #if (__ARMCC_VERSION >= 6010050)
2396     #pragma clang diagnostic push
2397   #else
2398     #pragma push
2399     #pragma anon_unions
2400   #endif
2401 #elif defined(__CWCC__)
2402   #pragma push
2403   #pragma cpp_extensions on
2404 #elif defined(__GNUC__)
2405   /* anonymous unions are enabled by default */
2406 #elif defined(__IAR_SYSTEMS_ICC__)
2407   #pragma language=extended
2408 #else
2409   #error Not supported compiler type
2410 #endif
2411 
2412 /* ----------------------------------------------------------------------------
2413    -- ADC Peripheral Access Layer
2414    ---------------------------------------------------------------------------- */
2415 
2416 /*!
2417  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
2418  * @{
2419  */
2420 
2421 /** ADC - Register Layout Typedef */
2422 typedef struct {
2423   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
2424   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
2425        uint8_t RESERVED_0[8];
2426   __IO uint32_t CTRL;                              /**< LPADC Control Register, offset: 0x10 */
2427   __IO uint32_t STAT;                              /**< LPADC Status Register, offset: 0x14 */
2428   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
2429   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
2430   __IO uint32_t CFG;                               /**< LPADC Configuration Register, offset: 0x20 */
2431   __IO uint32_t PAUSE;                             /**< LPADC Pause Register, offset: 0x24 */
2432        uint8_t RESERVED_1[8];
2433   __IO uint32_t FCTRL;                             /**< LPADC FIFO Control Register, offset: 0x30 */
2434   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
2435        uint8_t RESERVED_2[136];
2436   __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
2437        uint8_t RESERVED_3[32];
2438   struct {                                         /* offset: 0x100, array step: 0x8 */
2439     __IO uint32_t CMDL;                              /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
2440     __IO uint32_t CMDH;                              /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
2441   } CMD[15];
2442        uint8_t RESERVED_4[136];
2443   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
2444        uint8_t RESERVED_5[240];
2445   __I  uint32_t RESFIFO;                           /**< LPADC Data Result FIFO Register, offset: 0x300 */
2446 } ADC_Type;
2447 
2448 /* ----------------------------------------------------------------------------
2449    -- ADC Register Masks
2450    ---------------------------------------------------------------------------- */
2451 
2452 /*!
2453  * @addtogroup ADC_Register_Masks ADC Register Masks
2454  * @{
2455  */
2456 
2457 /*! @name VERID - Version ID Register */
2458 /*! @{ */
2459 
2460 #define ADC_VERID_RES_MASK                       (0x1U)
2461 #define ADC_VERID_RES_SHIFT                      (0U)
2462 /*! RES - Resolution
2463  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
2464  *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
2465  */
2466 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
2467 
2468 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
2469 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
2470 /*! DIFFEN - Differential Supported
2471  *  0b0..Differential operation not supported.
2472  *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
2473  */
2474 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
2475 
2476 #define ADC_VERID_MVI_MASK                       (0x8U)
2477 #define ADC_VERID_MVI_SHIFT                      (3U)
2478 /*! MVI - Multi Vref Implemented
2479  *  0b0..Single voltage reference input supported.
2480  *  0b1..Multiple voltage reference inputs supported.
2481  */
2482 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
2483 
2484 #define ADC_VERID_CSW_MASK                       (0x70U)
2485 #define ADC_VERID_CSW_SHIFT                      (4U)
2486 /*! CSW - Channel Scale Width
2487  *  0b000..Channel scaling not supported.
2488  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
2489  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
2490  */
2491 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
2492 
2493 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
2494 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
2495 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
2496  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
2497  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
2498  */
2499 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
2500 
2501 #define ADC_VERID_IADCKI_MASK                    (0x200U)
2502 #define ADC_VERID_IADCKI_SHIFT                   (9U)
2503 /*! IADCKI - Internal LPADC Clock implemented
2504  *  0b0..Internal clock source not implemented.
2505  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
2506  */
2507 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
2508 
2509 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
2510 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
2511 /*! CALOFSI - Calibration Offset Function Implemented
2512  *  0b0..Offset calibration and offset trimming not implemented.
2513  *  0b1..Offset calibration and offset trimming implemented.
2514  */
2515 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
2516 
2517 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
2518 #define ADC_VERID_MINOR_SHIFT                    (16U)
2519 /*! MINOR - Minor Version Number
2520  */
2521 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
2522 
2523 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
2524 #define ADC_VERID_MAJOR_SHIFT                    (24U)
2525 /*! MAJOR - Major Version Number
2526  */
2527 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
2528 /*! @} */
2529 
2530 /*! @name PARAM - Parameter Register */
2531 /*! @{ */
2532 
2533 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
2534 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
2535 /*! TRIG_NUM - Trigger Number
2536  *  0b00001000..8 hardware triggers implemented
2537  */
2538 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
2539 
2540 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
2541 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
2542 /*! FIFOSIZE - Result FIFO Depth
2543  *  0b00010000..Result FIFO depth = 16 datawords.
2544  */
2545 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
2546 
2547 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
2548 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
2549 /*! CV_NUM - Compare Value Number
2550  *  0b00000100..4 compare value registers implemented
2551  */
2552 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
2553 
2554 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
2555 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
2556 /*! CMD_NUM - Command Buffer Number
2557  *  0b00001111..15 command buffers implemented
2558  */
2559 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
2560 /*! @} */
2561 
2562 /*! @name CTRL - LPADC Control Register */
2563 /*! @{ */
2564 
2565 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
2566 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
2567 /*! ADCEN - LPADC Enable
2568  *  0b0..LPADC is disabled.
2569  *  0b1..LPADC is enabled.
2570  */
2571 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
2572 
2573 #define ADC_CTRL_RST_MASK                        (0x2U)
2574 #define ADC_CTRL_RST_SHIFT                       (1U)
2575 /*! RST - Software Reset
2576  *  0b0..LPADC logic is not reset.
2577  *  0b1..LPADC logic is reset.
2578  */
2579 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
2580 
2581 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
2582 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
2583 /*! DOZEN - Doze Enable
2584  *  0b0..LPADC is enabled in Doze mode.
2585  *  0b1..LPADC is disabled in Doze mode.
2586  */
2587 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
2588 
2589 #define ADC_CTRL_TRIG_SRC_MASK                   (0x18U)
2590 #define ADC_CTRL_TRIG_SRC_SHIFT                  (3U)
2591 /*! TRIG_SRC - Hardware trigger source selection
2592  *  0b00..ADC_ETC hw trigger , and HW trigger are enabled
2593  *  0b01..ADC_ETC hw trigger is enabled
2594  *  0b10..HW trigger is enabled
2595  *  0b11..Reserved
2596  */
2597 #define ADC_CTRL_TRIG_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
2598 
2599 #define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
2600 #define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
2601 /*! RSTFIFO - Reset FIFO
2602  *  0b0..No effect.
2603  *  0b1..FIFO is reset.
2604  */
2605 #define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
2606 /*! @} */
2607 
2608 /*! @name STAT - LPADC Status Register */
2609 /*! @{ */
2610 
2611 #define ADC_STAT_RDY_MASK                        (0x1U)
2612 #define ADC_STAT_RDY_SHIFT                       (0U)
2613 /*! RDY - Result FIFO Ready Flag
2614  *  0b0..Result FIFO data level not above watermark level.
2615  *  0b1..Result FIFO holding data above watermark level.
2616  */
2617 #define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
2618 
2619 #define ADC_STAT_FOF_MASK                        (0x2U)
2620 #define ADC_STAT_FOF_SHIFT                       (1U)
2621 /*! FOF - Result FIFO Overflow Flag
2622  *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
2623  *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
2624  */
2625 #define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
2626 
2627 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x100U)
2628 #define ADC_STAT_ADC_ACTIVE_SHIFT                (8U)
2629 /*! ADC_ACTIVE - ADC Active
2630  *  0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed.
2631  *  0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.
2632  */
2633 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
2634 
2635 #define ADC_STAT_TRGACT_MASK                     (0x70000U)
2636 #define ADC_STAT_TRGACT_SHIFT                    (16U)
2637 /*! TRGACT - Trigger Active
2638  *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
2639  *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
2640  *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
2641  *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
2642  */
2643 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
2644 
2645 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
2646 #define ADC_STAT_CMDACT_SHIFT                    (24U)
2647 /*! CMDACT - Command Active
2648  *  0b0000..No command is currently in progress.
2649  *  0b0001..Command 1 currently being executed.
2650  *  0b0010..Command 2 currently being executed.
2651  *  0b0011-0b1111..Associated command number is currently being executed.
2652  */
2653 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
2654 /*! @} */
2655 
2656 /*! @name IE - Interrupt Enable Register */
2657 /*! @{ */
2658 
2659 #define ADC_IE_FWMIE_MASK                        (0x1U)
2660 #define ADC_IE_FWMIE_SHIFT                       (0U)
2661 /*! FWMIE - FIFO Watermark Interrupt Enable
2662  *  0b0..FIFO watermark interrupts are not enabled.
2663  *  0b1..FIFO watermark interrupts are enabled.
2664  */
2665 #define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
2666 
2667 #define ADC_IE_FOFIE_MASK                        (0x2U)
2668 #define ADC_IE_FOFIE_SHIFT                       (1U)
2669 /*! FOFIE - Result FIFO Overflow Interrupt Enable
2670  *  0b0..FIFO overflow interrupts are not enabled.
2671  *  0b1..FIFO overflow interrupts are enabled.
2672  */
2673 #define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
2674 /*! @} */
2675 
2676 /*! @name DE - DMA Enable Register */
2677 /*! @{ */
2678 
2679 #define ADC_DE_FWMDE_MASK                        (0x1U)
2680 #define ADC_DE_FWMDE_SHIFT                       (0U)
2681 /*! FWMDE - FIFO Watermark DMA Enable
2682  *  0b0..DMA request disabled.
2683  *  0b1..DMA request enabled.
2684  */
2685 #define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
2686 /*! @} */
2687 
2688 /*! @name CFG - LPADC Configuration Register */
2689 /*! @{ */
2690 
2691 #define ADC_CFG_TPRICTRL_MASK                    (0x1U)
2692 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
2693 /*! TPRICTRL - LPADC trigger priority control
2694  *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
2695  *       the new command specified by the trigger is started.
2696  *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed
2697  *       (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
2698  *       trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
2699  *       conversion.
2700  */
2701 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
2702 
2703 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
2704 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
2705 /*! PWRSEL - Power Configuration Select
2706  *  0b00..Level 1 (Lowest power setting)
2707  *  0b01..Level 2
2708  *  0b10..Level 3
2709  *  0b11..Level 4 (Highest power setting)
2710  */
2711 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
2712 
2713 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
2714 #define ADC_CFG_REFSEL_SHIFT                     (6U)
2715 /*! REFSEL - Voltage Reference Selection
2716  *  0b00..(Default) Option 1 setting.
2717  *  0b01..Option 2 setting.
2718  *  0b10..Option 3 setting.
2719  *  0b11..Reserved
2720  */
2721 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
2722 
2723 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
2724 #define ADC_CFG_PUDLY_SHIFT                      (16U)
2725 /*! PUDLY - Power Up Delay
2726  */
2727 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
2728 
2729 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
2730 #define ADC_CFG_PWREN_SHIFT                      (28U)
2731 /*! PWREN - LPADC Analog Pre-Enable
2732  *  0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
2733  *  0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the
2734  *       cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
2735  *       detected trigger does not begin ADC operation until the power up delay time has passed.
2736  */
2737 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
2738 /*! @} */
2739 
2740 /*! @name PAUSE - LPADC Pause Register */
2741 /*! @{ */
2742 
2743 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
2744 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
2745 /*! PAUSEDLY - Pause Delay
2746  */
2747 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
2748 
2749 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
2750 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
2751 /*! PAUSEEN - PAUSE Option Enable
2752  *  0b0..Pause operation disabled
2753  *  0b1..Pause operation enabled
2754  */
2755 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
2756 /*! @} */
2757 
2758 /*! @name FCTRL - LPADC FIFO Control Register */
2759 /*! @{ */
2760 
2761 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
2762 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
2763 /*! FCOUNT - Result FIFO counter
2764  *  0b00000..No data stored in FIFO
2765  *  0b00001..1 dataword stored in FIFO
2766  *  0b00010..2 datawords stored in FIFO
2767  *  0b00100..4 datawords stored in FIFO
2768  *  0b01000..8 datawords stored in FIFO
2769  *  0b10000..16 datawords stored in FIFO
2770  */
2771 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
2772 
2773 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
2774 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
2775 /*! FWMARK - Watermark level selection
2776  *  0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion
2777  *  0b0001..Generates STAT[RDY] flag after 2nd successful conversion
2778  *  0b0010..Generates STAT[RDY] flag after 3rd successful conversion
2779  *  0b0011..Generates STAT[RDY] flag after 4th successful conversion
2780  *  0b0100..Generates STAT[RDY] flag after 5th successful conversion
2781  *  0b0101..Generates STAT[RDY] flag after 6th successful conversion
2782  *  0b0110..Generates STAT[RDY] flag after 7th successful conversion
2783  *  0b0111..Generates STAT[RDY] flag after 8th successful conversion
2784  *  0b1000..Generates STAT[RDY] flag after 9th successful conversion
2785  *  0b1001..Generates STAT[RDY] flag after 10th successful conversion
2786  *  0b1010..Generates STAT[RDY] flag after 11th successful conversion
2787  *  0b1011..Generates STAT[RDY] flag after 12th successful conversion
2788  *  0b1100..Generates STAT[RDY] flag after 13th successful conversion
2789  *  0b1101..Generates STAT[RDY] flag after 14th successful conversion
2790  *  0b1110..Generates STAT[RDY] flag after 15th successful conversion
2791  *  0b1111..Generates STAT[RDY] flag after 16th successful conversion
2792  */
2793 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
2794 /*! @} */
2795 
2796 /*! @name SWTRIG - Software Trigger Register */
2797 /*! @{ */
2798 
2799 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
2800 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
2801 /*! SWT0 - Software trigger 0 event
2802  *  0b0..No trigger 0 event generated.
2803  *  0b1..Trigger 0 event generated.
2804  */
2805 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
2806 
2807 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
2808 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
2809 /*! SWT1 - Software trigger 1 event
2810  *  0b0..No trigger 1 event generated.
2811  *  0b1..Trigger 1 event generated.
2812  */
2813 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
2814 
2815 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
2816 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
2817 /*! SWT2 - Software trigger 2 event
2818  *  0b0..No trigger 2 event generated.
2819  *  0b1..Trigger 2 event generated.
2820  */
2821 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
2822 
2823 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
2824 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
2825 /*! SWT3 - Software trigger 3 event
2826  *  0b0..No trigger 3 event generated.
2827  *  0b1..Trigger 3 event generated.
2828  */
2829 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
2830 
2831 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
2832 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
2833 /*! SWT4 - Software trigger 4 event
2834  *  0b0..No trigger 4 event generated.
2835  *  0b1..Trigger 4 event generated.
2836  */
2837 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
2838 
2839 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
2840 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
2841 /*! SWT5 - Software trigger 5 event
2842  *  0b0..No trigger 5 event generated.
2843  *  0b1..Trigger 5 event generated.
2844  */
2845 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
2846 
2847 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
2848 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
2849 /*! SWT6 - Software trigger 6 event
2850  *  0b0..No trigger 6 event generated.
2851  *  0b1..Trigger 6 event generated.
2852  */
2853 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
2854 
2855 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
2856 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
2857 /*! SWT7 - Software trigger 7 event
2858  *  0b0..No trigger 7 event generated.
2859  *  0b1..Trigger 7 event generated.
2860  */
2861 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
2862 /*! @} */
2863 
2864 /*! @name TCTRL - Trigger Control Register */
2865 /*! @{ */
2866 
2867 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
2868 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
2869 /*! HTEN - Trigger enable
2870  *  0b0..Hardware trigger source disabled
2871  *  0b1..Hardware trigger source enabled
2872  */
2873 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
2874 
2875 #define ADC_TCTRL_CMD_SEL_MASK                   (0x2U)
2876 #define ADC_TCTRL_CMD_SEL_SHIFT                  (1U)
2877 /*! CMD_SEL
2878  *  0b0..TCTRLa[TCMD] will determine the command
2879  *  0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is
2880  *       then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].
2881  */
2882 #define ADC_TCTRL_CMD_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
2883 
2884 #define ADC_TCTRL_TPRI_MASK                      (0x700U)
2885 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
2886 /*! TPRI - Trigger priority setting
2887  *  0b000..Set to highest priority, Level 1
2888  *  0b001-0b110..Set to corresponding priority level
2889  *  0b111..Set to lowest priority, Level 8
2890  */
2891 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
2892 
2893 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
2894 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
2895 /*! TDLY - Trigger delay select
2896  */
2897 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
2898 
2899 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
2900 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
2901 /*! TCMD - Trigger command select
2902  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
2903  *  0b0001..CMD1 is executed
2904  *  0b0010-0b1110..Corresponding CMD is executed
2905  *  0b1111..CMD15 is executed
2906  */
2907 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
2908 /*! @} */
2909 
2910 /* The count of ADC_TCTRL */
2911 #define ADC_TCTRL_COUNT                          (8U)
2912 
2913 /*! @name CMDL - LPADC Command Low Buffer Register */
2914 /*! @{ */
2915 
2916 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
2917 #define ADC_CMDL_ADCH_SHIFT                      (0U)
2918 /*! ADCH - Input channel select
2919  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
2920  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
2921  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
2922  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
2923  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
2924  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
2925  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
2926  */
2927 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
2928 
2929 #define ADC_CMDL_ABSEL_MASK                      (0x20U)
2930 #define ADC_CMDL_ABSEL_SHIFT                     (5U)
2931 /*! ABSEL - A-side vs. B-side Select
2932  *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
2933  *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
2934  */
2935 #define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
2936 
2937 #define ADC_CMDL_DIFF_MASK                       (0x40U)
2938 #define ADC_CMDL_DIFF_SHIFT                      (6U)
2939 /*! DIFF - Differential Mode Enable
2940  *  0b0..Single-ended mode.
2941  *  0b1..Differential mode.
2942  */
2943 #define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
2944 
2945 #define ADC_CMDL_CSCALE_MASK                     (0x2000U)
2946 #define ADC_CMDL_CSCALE_SHIFT                    (13U)
2947 /*! CSCALE - Channel Scale
2948  *  0b0..Scale selected analog channel (Factor of 30/64)
2949  *  0b1..(Default) Full scale (Factor of 1)
2950  */
2951 #define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
2952 /*! @} */
2953 
2954 /* The count of ADC_CMDL */
2955 #define ADC_CMDL_COUNT                           (15U)
2956 
2957 /*! @name CMDH - LPADC Command High Buffer Register */
2958 /*! @{ */
2959 
2960 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
2961 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
2962 /*! CMPEN - Compare Function Enable
2963  *  0b00..Compare disabled.
2964  *  0b01..Reserved
2965  *  0b10..Compare enabled. Store on true.
2966  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
2967  */
2968 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
2969 
2970 #define ADC_CMDH_LWI_MASK                        (0x80U)
2971 #define ADC_CMDH_LWI_SHIFT                       (7U)
2972 /*! LWI - Loop with Increment
2973  *  0b0..Auto channel increment disabled
2974  *  0b1..Auto channel increment enabled
2975  */
2976 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
2977 
2978 #define ADC_CMDH_STS_MASK                        (0x700U)
2979 #define ADC_CMDH_STS_SHIFT                       (8U)
2980 /*! STS - Sample Time Select
2981  *  0b000..Minimum sample time of 3 ADCK cycles.
2982  *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
2983  *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
2984  *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
2985  *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
2986  *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
2987  *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
2988  *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
2989  */
2990 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
2991 
2992 #define ADC_CMDH_AVGS_MASK                       (0x7000U)
2993 #define ADC_CMDH_AVGS_SHIFT                      (12U)
2994 /*! AVGS - Hardware Average Select
2995  *  0b000..Single conversion.
2996  *  0b001..2 conversions averaged.
2997  *  0b010..4 conversions averaged.
2998  *  0b011..8 conversions averaged.
2999  *  0b100..16 conversions averaged.
3000  *  0b101..32 conversions averaged.
3001  *  0b110..64 conversions averaged.
3002  *  0b111..128 conversions averaged.
3003  */
3004 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
3005 
3006 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
3007 #define ADC_CMDH_LOOP_SHIFT                      (16U)
3008 /*! LOOP - Loop Count Select
3009  *  0b0000..Looping not enabled. Command executes 1 time.
3010  *  0b0001..Loop 1 time. Command executes 2 times.
3011  *  0b0010..Loop 2 times. Command executes 3 times.
3012  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
3013  *  0b1111..Loop 15 times. Command executes 16 times.
3014  */
3015 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
3016 
3017 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
3018 #define ADC_CMDH_NEXT_SHIFT                      (24U)
3019 /*! NEXT - Next Command Select
3020  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
3021  *          trigger pending, begin command associated with lower priority trigger.
3022  *  0b0001..Select CMD1 command buffer register as next command.
3023  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
3024  *  0b1111..Select CMD15 command buffer register as next command.
3025  */
3026 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
3027 /*! @} */
3028 
3029 /* The count of ADC_CMDH */
3030 #define ADC_CMDH_COUNT                           (15U)
3031 
3032 /*! @name CV - Compare Value Register */
3033 /*! @{ */
3034 
3035 #define ADC_CV_CVL_MASK                          (0xFFFFU)
3036 #define ADC_CV_CVL_SHIFT                         (0U)
3037 /*! CVL - Compare Value Low
3038  */
3039 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
3040 
3041 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
3042 #define ADC_CV_CVH_SHIFT                         (16U)
3043 /*! CVH - Compare Value High.
3044  */
3045 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
3046 /*! @} */
3047 
3048 /* The count of ADC_CV */
3049 #define ADC_CV_COUNT                             (4U)
3050 
3051 /*! @name RESFIFO - LPADC Data Result FIFO Register */
3052 /*! @{ */
3053 
3054 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
3055 #define ADC_RESFIFO_D_SHIFT                      (0U)
3056 /*! D - Data result
3057  */
3058 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
3059 
3060 #define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
3061 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
3062 /*! TSRC - Trigger Source
3063  *  0b000..Trigger source 0 initiated this conversion.
3064  *  0b001..Trigger source 1 initiated this conversion.
3065  *  0b010-0b110..Corresponding trigger source initiated this conversion.
3066  *  0b111..Trigger source 7 initiated this conversion.
3067  */
3068 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
3069 
3070 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
3071 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
3072 /*! LOOPCNT - Loop count value
3073  *  0b0000..Result is from initial conversion in command.
3074  *  0b0001..Result is from second conversion in command.
3075  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
3076  *  0b1111..Result is from 16th conversion in command.
3077  */
3078 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
3079 
3080 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
3081 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
3082 /*! CMDSRC - Command Buffer Source
3083  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
3084  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
3085  *  0b0001..CMD1 buffer used as control settings for this conversion.
3086  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
3087  *  0b1111..CMD15 buffer used as control settings for this conversion.
3088  */
3089 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
3090 
3091 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
3092 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
3093 /*! VALID - FIFO entry is valid
3094  *  0b0..FIFO is empty. Discard any read from RESFIFO.
3095  *  0b1..FIFO record read from RESFIFO is valid.
3096  */
3097 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
3098 /*! @} */
3099 
3100 
3101 /*!
3102  * @}
3103  */ /* end of group ADC_Register_Masks */
3104 
3105 
3106 /* ADC - Peripheral instance base addresses */
3107 /** Peripheral LPADC1 base address */
3108 #define LPADC1_BASE                              (0x40050000u)
3109 /** Peripheral LPADC1 base pointer */
3110 #define LPADC1                                   ((ADC_Type *)LPADC1_BASE)
3111 /** Peripheral LPADC2 base address */
3112 #define LPADC2_BASE                              (0x40054000u)
3113 /** Peripheral LPADC2 base pointer */
3114 #define LPADC2                                   ((ADC_Type *)LPADC2_BASE)
3115 /** Array initializer of ADC peripheral base addresses */
3116 #define ADC_BASE_ADDRS                           { 0u, LPADC1_BASE, LPADC2_BASE }
3117 /** Array initializer of ADC peripheral base pointers */
3118 #define ADC_BASE_PTRS                            { (ADC_Type *)0u, LPADC1, LPADC2 }
3119 /** Interrupt vectors for the ADC peripheral type */
3120 #define ADC_IRQS                                 { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
3121 
3122 /*!
3123  * @}
3124  */ /* end of group ADC_Peripheral_Access_Layer */
3125 
3126 
3127 /* ----------------------------------------------------------------------------
3128    -- ADC_ETC Peripheral Access Layer
3129    ---------------------------------------------------------------------------- */
3130 
3131 /*!
3132  * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
3133  * @{
3134  */
3135 
3136 /** ADC_ETC - Register Layout Typedef */
3137 typedef struct {
3138   __IO uint32_t CTRL;                              /**< ADC_ETC Global Control Register, offset: 0x0 */
3139   __IO uint32_t DONE0_1_IRQ;                       /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
3140   __IO uint32_t DONE2_3_ERR_IRQ;                   /**< ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8 */
3141   __IO uint32_t DMA_CTRL;                          /**< ETC DMA control Register, offset: 0xC */
3142   struct {                                         /* offset: 0x10, array step: 0x28 */
3143     __IO uint32_t TRIGn_CTRL;                        /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
3144     __IO uint32_t TRIGn_COUNTER;                     /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
3145     __IO uint32_t TRIGn_CHAIN_1_0;                   /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
3146     __IO uint32_t TRIGn_CHAIN_3_2;                   /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
3147     __IO uint32_t TRIGn_CHAIN_5_4;                   /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
3148     __IO uint32_t TRIGn_CHAIN_7_6;                   /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
3149     __I  uint32_t TRIGn_RESULT_1_0;                  /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
3150     __I  uint32_t TRIGn_RESULT_3_2;                  /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
3151     __I  uint32_t TRIGn_RESULT_5_4;                  /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
3152     __I  uint32_t TRIGn_RESULT_7_6;                  /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
3153   } TRIG[8];
3154 } ADC_ETC_Type;
3155 
3156 /* ----------------------------------------------------------------------------
3157    -- ADC_ETC Register Masks
3158    ---------------------------------------------------------------------------- */
3159 
3160 /*!
3161  * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
3162  * @{
3163  */
3164 
3165 /*! @name CTRL - ADC_ETC Global Control Register */
3166 /*! @{ */
3167 
3168 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK            (0xFFU)
3169 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT           (0U)
3170 /*! TRIG_ENABLE
3171  *  0b00000000..disable all 8 external XBAR triggers.
3172  *  0b00000001..enable external XBAR trigger0.
3173  *  0b00000010..enable external XBAR trigger1.
3174  *  0b00000011..enable external XBAR trigger0 and trigger1.
3175  *  0b11111111..enable all 8 external XBAR triggers.
3176  */
3177 #define ADC_ETC_CTRL_TRIG_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
3178 
3179 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK            (0xFF0000U)
3180 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT           (16U)
3181 #define ADC_ETC_CTRL_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
3182 
3183 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK           (0x20000000U)
3184 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT          (29U)
3185 /*! DMA_MODE_SEL
3186  *  0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared.
3187  *  0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only.
3188  */
3189 #define ADC_ETC_CTRL_DMA_MODE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
3190 
3191 #define ADC_ETC_CTRL_SOFTRST_MASK                (0x80000000U)
3192 #define ADC_ETC_CTRL_SOFTRST_SHIFT               (31U)
3193 /*! SOFTRST
3194  *  0b0..ADC_ETC works normally.
3195  *  0b1..All registers inside ADC_ETC will be reset to the default value.
3196  */
3197 #define ADC_ETC_CTRL_SOFTRST(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
3198 /*! @} */
3199 
3200 /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
3201 /*! @{ */
3202 
3203 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK     (0x1U)
3204 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT    (0U)
3205 /*! TRIG0_DONE0
3206  *  0b0..No TRIG0_DONE0 interrupt detected
3207  *  0b1..TRIG0_DONE0 interrupt detected
3208  */
3209 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
3210 
3211 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK     (0x2U)
3212 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT    (1U)
3213 /*! TRIG1_DONE0
3214  *  0b0..No TRIG1_DONE0 interrupt detected
3215  *  0b1..TRIG1_DONE0 interrupt detected
3216  */
3217 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
3218 
3219 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK     (0x4U)
3220 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT    (2U)
3221 /*! TRIG2_DONE0
3222  *  0b0..No TRIG2_DONE0 interrupt detected
3223  *  0b1..TRIG2_DONE0 interrupt detected
3224  */
3225 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
3226 
3227 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK     (0x8U)
3228 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT    (3U)
3229 /*! TRIG3_DONE0
3230  *  0b0..No TRIG3_DONE0 interrupt detected
3231  *  0b1..TRIG3_DONE0 interrupt detected
3232  */
3233 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
3234 
3235 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK     (0x10U)
3236 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT    (4U)
3237 /*! TRIG4_DONE0
3238  *  0b0..No TRIG4_DONE0 interrupt detected
3239  *  0b1..TRIG4_DONE0 interrupt detected
3240  */
3241 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
3242 
3243 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK     (0x20U)
3244 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT    (5U)
3245 /*! TRIG5_DONE0
3246  *  0b0..No TRIG5_DONE0 interrupt detected
3247  *  0b1..TRIG5_DONE0 interrupt detected
3248  */
3249 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
3250 
3251 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK     (0x40U)
3252 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT    (6U)
3253 /*! TRIG6_DONE0
3254  *  0b0..No TRIG6_DONE0 interrupt detected
3255  *  0b1..TRIG6_DONE0 interrupt detected
3256  */
3257 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
3258 
3259 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK     (0x80U)
3260 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT    (7U)
3261 /*! TRIG7_DONE0
3262  *  0b0..No TRIG7_DONE0 interrupt detected
3263  *  0b1..TRIG7_DONE0 interrupt detected
3264  */
3265 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
3266 
3267 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK     (0x10000U)
3268 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT    (16U)
3269 /*! TRIG0_DONE1
3270  *  0b0..No TRIG0_DONE1 interrupt detected
3271  *  0b1..TRIG0_DONE1 interrupt detected
3272  */
3273 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
3274 
3275 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK     (0x20000U)
3276 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT    (17U)
3277 /*! TRIG1_DONE1
3278  *  0b0..No TRIG1_DONE1 interrupt detected
3279  *  0b1..TRIG1_DONE1 interrupt detected
3280  */
3281 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
3282 
3283 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK     (0x40000U)
3284 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT    (18U)
3285 /*! TRIG2_DONE1
3286  *  0b0..No TRIG2_DONE1 interrupt detected
3287  *  0b1..TRIG2_DONE1 interrupt detected
3288  */
3289 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
3290 
3291 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK     (0x80000U)
3292 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT    (19U)
3293 /*! TRIG3_DONE1
3294  *  0b0..No TRIG3_DONE1 interrupt detected
3295  *  0b1..TRIG3_DONE1 interrupt detected
3296  */
3297 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
3298 
3299 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK     (0x100000U)
3300 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT    (20U)
3301 /*! TRIG4_DONE1
3302  *  0b0..No TRIG4_DONE1 interrupt detected
3303  *  0b1..TRIG4_DONE1 interrupt detected
3304  */
3305 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
3306 
3307 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK     (0x200000U)
3308 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT    (21U)
3309 /*! TRIG5_DONE1
3310  *  0b0..No TRIG5_DONE1 interrupt detected
3311  *  0b1..TRIG5_DONE1 interrupt detected
3312  */
3313 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
3314 
3315 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK     (0x400000U)
3316 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT    (22U)
3317 /*! TRIG6_DONE1
3318  *  0b0..No TRIG6_DONE1 interrupt detected
3319  *  0b1..TRIG6_DONE1 interrupt detected
3320  */
3321 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
3322 
3323 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK     (0x800000U)
3324 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT    (23U)
3325 /*! TRIG7_DONE1
3326  *  0b0..No TRIG7_DONE1 interrupt detected
3327  *  0b1..TRIG7_DONE1 interrupt detected
3328  */
3329 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
3330 /*! @} */
3331 
3332 /*! @name DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register */
3333 /*! @{ */
3334 
3335 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
3336 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
3337 /*! TRIG0_DONE2
3338  *  0b0..No TRIG0_DONE2 interrupt detected
3339  *  0b1..TRIG0_DONE2 interrupt detected
3340  */
3341 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
3342 
3343 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
3344 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
3345 /*! TRIG1_DONE2
3346  *  0b0..No TRIG1_DONE2 interrupt detected
3347  *  0b1..TRIG1_DONE2 interrupt detected
3348  */
3349 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
3350 
3351 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
3352 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
3353 /*! TRIG2_DONE2
3354  *  0b0..No TRIG2_DONE2 interrupt detected
3355  *  0b1..TRIG2_DONE2 interrupt detected
3356  */
3357 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
3358 
3359 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
3360 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
3361 /*! TRIG3_DONE2
3362  *  0b0..No TRIG3_DONE2 interrupt detected
3363  *  0b1..TRIG3_DONE2 interrupt detected
3364  */
3365 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
3366 
3367 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
3368 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
3369 /*! TRIG4_DONE2
3370  *  0b0..No TRIG4_DONE2 interrupt detected
3371  *  0b1..TRIG4_DONE2 interrupt detected
3372  */
3373 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
3374 
3375 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
3376 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
3377 /*! TRIG5_DONE2
3378  *  0b0..No TRIG5_DONE2 interrupt detected
3379  *  0b1..TRIG5_DONE2 interrupt detected
3380  */
3381 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
3382 
3383 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
3384 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
3385 /*! TRIG6_DONE2
3386  *  0b0..No TRIG6_DONE2 interrupt detected
3387  *  0b1..TRIG6_DONE2 interrupt detected
3388  */
3389 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
3390 
3391 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
3392 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
3393 /*! TRIG7_DONE2
3394  *  0b0..No TRIG7_DONE2 interrupt detected
3395  *  0b1..TRIG7_DONE2 interrupt detected
3396  */
3397 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
3398 
3399 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
3400 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
3401 /*! TRIG0_DONE3
3402  *  0b0..No TRIG0_DONE3 interrupt detected
3403  *  0b1..TRIG0_DONE3 interrupt detected
3404  */
3405 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
3406 
3407 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
3408 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
3409 /*! TRIG1_DONE3
3410  *  0b0..No TRIG1_DONE3 interrupt detected
3411  *  0b1..TRIG1_DONE3 interrupt detected
3412  */
3413 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK)
3414 
3415 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
3416 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
3417 /*! TRIG2_DONE3
3418  *  0b0..No TRIG2_DONE3 interrupt detected
3419  *  0b1..TRIG2_DONE3 interrupt detected
3420  */
3421 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK)
3422 
3423 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
3424 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
3425 /*! TRIG3_DONE3
3426  *  0b0..No TRIG3_DONE3 interrupt detected
3427  *  0b1..TRIG3_DONE3 interrupt detected
3428  */
3429 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK)
3430 
3431 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
3432 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
3433 /*! TRIG4_DONE3
3434  *  0b0..No TRIG4_DONE3 interrupt detected
3435  *  0b1..TRIG4_DONE3 interrupt detected
3436  */
3437 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK)
3438 
3439 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
3440 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
3441 /*! TRIG5_DONE3
3442  *  0b0..No TRIG5_DONE3 interrupt detected
3443  *  0b1..TRIG5_DONE3 interrupt detected
3444  */
3445 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK)
3446 
3447 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
3448 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
3449 /*! TRIG6_DONE3
3450  *  0b0..No TRIG6_DONE3 interrupt detected
3451  *  0b1..TRIG6_DONE3 interrupt detected
3452  */
3453 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK)
3454 
3455 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
3456 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
3457 /*! TRIG7_DONE3
3458  *  0b0..No TRIG7_DONE3 interrupt detected
3459  *  0b1..TRIG7_DONE3 interrupt detected
3460  */
3461 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK)
3462 
3463 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK   (0x10000U)
3464 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT  (16U)
3465 /*! TRIG0_ERR
3466  *  0b0..No TRIG0_ERR interrupt detected
3467  *  0b1..TRIG0_ERR interrupt detected
3468  */
3469 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
3470 
3471 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK   (0x20000U)
3472 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT  (17U)
3473 /*! TRIG1_ERR
3474  *  0b0..No TRIG1_ERR interrupt detected
3475  *  0b1..TRIG1_ERR interrupt detected
3476  */
3477 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
3478 
3479 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK   (0x40000U)
3480 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT  (18U)
3481 /*! TRIG2_ERR
3482  *  0b0..No TRIG2_ERR interrupt detected
3483  *  0b1..TRIG2_ERR interrupt detected
3484  */
3485 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
3486 
3487 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK   (0x80000U)
3488 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT  (19U)
3489 /*! TRIG3_ERR
3490  *  0b0..No TRIG3_ERR interrupt detected
3491  *  0b1..TRIG3_ERR interrupt detected
3492  */
3493 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
3494 
3495 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK   (0x100000U)
3496 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT  (20U)
3497 /*! TRIG4_ERR
3498  *  0b0..No TRIG4_ERR interrupt detected
3499  *  0b1..TRIG4_ERR interrupt detected
3500  */
3501 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
3502 
3503 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK   (0x200000U)
3504 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT  (21U)
3505 /*! TRIG5_ERR
3506  *  0b0..No TRIG5_ERR interrupt detected
3507  *  0b1..TRIG5_ERR interrupt detected
3508  */
3509 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
3510 
3511 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK   (0x400000U)
3512 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT  (22U)
3513 /*! TRIG6_ERR
3514  *  0b0..No TRIG6_ERR interrupt detected
3515  *  0b1..TRIG6_ERR interrupt detected
3516  */
3517 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
3518 
3519 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK   (0x800000U)
3520 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT  (23U)
3521 /*! TRIG7_ERR
3522  *  0b0..No TRIG7_ERR interrupt detected
3523  *  0b1..TRIG7_ERR interrupt detected
3524  */
3525 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
3526 /*! @} */
3527 
3528 /*! @name DMA_CTRL - ETC DMA control Register */
3529 /*! @{ */
3530 
3531 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK       (0x1U)
3532 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT      (0U)
3533 /*! TRIG0_ENABLE
3534  *  0b0..TRIG0 DMA request disabled.
3535  *  0b1..TRIG0 DMA request enabled.
3536  */
3537 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
3538 
3539 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK       (0x2U)
3540 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT      (1U)
3541 /*! TRIG1_ENABLE
3542  *  0b0..TRIG1 DMA request disabled.
3543  *  0b1..TRIG1 DMA request enabled.
3544  */
3545 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
3546 
3547 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK       (0x4U)
3548 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT      (2U)
3549 /*! TRIG2_ENABLE
3550  *  0b0..TRIG2 DMA request disabled.
3551  *  0b1..TRIG2 DMA request enabled.
3552  */
3553 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
3554 
3555 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK       (0x8U)
3556 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT      (3U)
3557 /*! TRIG3_ENABLE
3558  *  0b0..TRIG3 DMA request disabled.
3559  *  0b1..TRIG3 DMA request enabled.
3560  */
3561 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
3562 
3563 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK       (0x10U)
3564 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT      (4U)
3565 /*! TRIG4_ENABLE
3566  *  0b0..TRIG4 DMA request disabled.
3567  *  0b1..TRIG4 DMA request enabled.
3568  */
3569 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
3570 
3571 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK       (0x20U)
3572 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT      (5U)
3573 /*! TRIG5_ENABLE
3574  *  0b0..TRIG5 DMA request disabled.
3575  *  0b1..TRIG5 DMA request enabled.
3576  */
3577 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
3578 
3579 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK       (0x40U)
3580 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT      (6U)
3581 /*! TRIG6_ENABLE
3582  *  0b0..TRIG6 DMA request disabled.
3583  *  0b1..TRIG6 DMA request enabled.
3584  */
3585 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
3586 
3587 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK       (0x80U)
3588 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT      (7U)
3589 /*! TRIG7_ENABLE
3590  *  0b0..TRIG7 DMA request disabled.
3591  *  0b1..TRIG7 DMA request enabled.
3592  */
3593 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
3594 
3595 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK          (0x10000U)
3596 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT         (16U)
3597 /*! TRIG0_REQ
3598  *  0b0..TRIG0_REQ not detected.
3599  *  0b1..TRIG0_REQ detected.
3600  */
3601 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
3602 
3603 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK          (0x20000U)
3604 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT         (17U)
3605 /*! TRIG1_REQ
3606  *  0b0..TRIG1_REQ not detected.
3607  *  0b1..TRIG1_REQ detected.
3608  */
3609 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
3610 
3611 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK          (0x40000U)
3612 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT         (18U)
3613 /*! TRIG2_REQ
3614  *  0b0..TRIG2_REQ not detected.
3615  *  0b1..TRIG2_REQ detected.
3616  */
3617 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
3618 
3619 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK          (0x80000U)
3620 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT         (19U)
3621 /*! TRIG3_REQ
3622  *  0b0..TRIG3_REQ not detected.
3623  *  0b1..TRIG3_REQ detected.
3624  */
3625 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
3626 
3627 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK          (0x100000U)
3628 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT         (20U)
3629 /*! TRIG4_REQ
3630  *  0b0..TRIG4_REQ not detected.
3631  *  0b1..TRIG4_REQ detected.
3632  */
3633 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
3634 
3635 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK          (0x200000U)
3636 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT         (21U)
3637 /*! TRIG5_REQ
3638  *  0b0..TRIG5_REQ not detected.
3639  *  0b1..TRIG5_REQ detected.
3640  */
3641 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
3642 
3643 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK          (0x400000U)
3644 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT         (22U)
3645 /*! TRIG6_REQ
3646  *  0b0..TRIG6_REQ not detected.
3647  *  0b1..TRIG6_REQ detected.
3648  */
3649 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
3650 
3651 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK          (0x800000U)
3652 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT         (23U)
3653 /*! TRIG7_REQ
3654  *  0b0..TRIG7_REQ not detected.
3655  *  0b1..TRIG7_REQ detected.
3656  */
3657 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
3658 /*! @} */
3659 
3660 /*! @name TRIGn_CTRL - ETC_TRIG Control Register */
3661 /*! @{ */
3662 
3663 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK          (0x1U)
3664 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT         (0U)
3665 /*! SW_TRIG
3666  *  0b0..No software trigger event generated.
3667  *  0b1..Software trigger event generated.
3668  */
3669 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
3670 
3671 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK        (0x10U)
3672 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT       (4U)
3673 /*! TRIG_MODE
3674  *  0b0..Hardware trigger. The softerware trigger will be ignored.
3675  *  0b1..Software trigger. The hardware trigger will be ignored.
3676  */
3677 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
3678 
3679 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK       (0x700U)
3680 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT      (8U)
3681 /*! TRIG_CHAIN
3682  *  0b000..Trigger chain length is 1
3683  *  0b001..Trigger chain length is 2
3684  *  0b010..Trigger chain length is 3
3685  *  0b011..Trigger chain length is 4
3686  *  0b100..Trigger chain length is 5
3687  *  0b101..Trigger chain length is 6
3688  *  0b110..Trigger chain length is 7
3689  *  0b111..Trigger chain length is 8
3690  */
3691 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
3692 
3693 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK    (0x7000U)
3694 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT   (12U)
3695 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
3696 
3697 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK        (0x10000U)
3698 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT       (16U)
3699 /*! SYNC_MODE
3700  *  0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently.
3701  *  0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously.
3702  */
3703 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
3704 
3705 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK      (0xFF000000U)
3706 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT     (24U)
3707 /*! CHAINx_DONE
3708  *  0b00000000..segment x done not detected.
3709  *  0b00000001..segment x done detected.
3710  */
3711 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
3712 /*! @} */
3713 
3714 /* The count of ADC_ETC_TRIGn_CTRL */
3715 #define ADC_ETC_TRIGn_CTRL_COUNT                 (8U)
3716 
3717 /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
3718 /*! @{ */
3719 
3720 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK    (0xFFFFU)
3721 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT   (0U)
3722 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
3723 
3724 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
3725 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
3726 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
3727 /*! @} */
3728 
3729 /* The count of ADC_ETC_TRIGn_COUNTER */
3730 #define ADC_ETC_TRIGn_COUNTER_COUNT              (8U)
3731 
3732 /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
3733 /*! @{ */
3734 
3735 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK       (0xFU)
3736 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT      (0U)
3737 /*! CSEL0
3738  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3739  *  0b0001..ADC CMD1 selected.
3740  *  0b0010..ADC CMD2 selected.
3741  *  0b0011..ADC CMD3 selected.
3742  *  0b0100..ADC CMD4 selected.
3743  *  0b0101..ADC CMD5 selected.
3744  *  0b0110..ADC CMD6 selected.
3745  *  0b0111..ADC CMD7 selected.
3746  *  0b1000..ADC CMD8 selected.
3747  *  0b1001..ADC CMD9 selected.
3748  *  0b1010..ADC CMD10 selected.
3749  *  0b1011..ADC CMD11 selected.
3750  *  0b1100..ADC CMD12 selected.
3751  *  0b1101..ADC CMD13 selected.
3752  *  0b1110..ADC CMD14 selected.
3753  *  0b1111..ADC CMD15 selected.
3754  */
3755 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
3756 
3757 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK       (0xFF0U)
3758 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT      (4U)
3759 /*! HWTS0
3760  *  0b00000000..no trigger selected
3761  *  0b00000001..ADC TRIG0 selected
3762  *  0b00000010..ADC TRIG1 selected
3763  *  0b00000100..ADC TRIG2 selected
3764  *  0b00001000..ADC TRIG3 selected
3765  *  0b00010000..ADC TRIG4 selected
3766  *  0b00100000..ADC TRIG5 selected
3767  *  0b01000000..ADC TRIG6 selected
3768  *  0b10000000..ADC TRIG7 selected
3769  */
3770 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
3771 
3772 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK        (0x1000U)
3773 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT       (12U)
3774 /*! B2B0
3775  *  0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached
3776  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3777  */
3778 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
3779 
3780 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK         (0x6000U)
3781 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT        (13U)
3782 /*! IE0
3783  *  0b00..Generate interrupt on Done0 when segment 0 finish.
3784  *  0b01..Generate interrupt on Done1 when segment 0 finish.
3785  *  0b10..Generate interrupt on Done2 when segment 0 finish.
3786  *  0b11..Generate interrupt on Done3 when segment 0 finish.
3787  */
3788 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
3789 
3790 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK      (0x8000U)
3791 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT     (15U)
3792 /*! IE0_EN
3793  *  0b0..Interrupt DONE disabled.
3794  *  0b1..Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0.
3795  */
3796 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
3797 
3798 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK       (0xF0000U)
3799 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT      (16U)
3800 /*! CSEL1
3801  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3802  *  0b0001..ADC CMD1 selected.
3803  *  0b0010..ADC CMD2 selected.
3804  *  0b0011..ADC CMD3 selected.
3805  *  0b0100..ADC CMD4 selected.
3806  *  0b0101..ADC CMD5 selected.
3807  *  0b0110..ADC CMD6 selected.
3808  *  0b0111..ADC CMD7 selected.
3809  *  0b1000..ADC CMD8 selected.
3810  *  0b1001..ADC CMD9 selected.
3811  *  0b1010..ADC CMD10 selected.
3812  *  0b1011..ADC CMD11 selected.
3813  *  0b1100..ADC CMD12 selected.
3814  *  0b1101..ADC CMD13 selected.
3815  *  0b1110..ADC CMD14 selected.
3816  *  0b1111..ADC CMD15 selected.
3817  */
3818 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
3819 
3820 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK       (0xFF00000U)
3821 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT      (20U)
3822 /*! HWTS1
3823  *  0b00000000..no trigger selected
3824  *  0b00000001..ADC TRIG0 selected
3825  *  0b00000010..ADC TRIG1 selected
3826  *  0b00000100..ADC TRIG2 selected
3827  *  0b00001000..ADC TRIG3 selected
3828  *  0b00010000..ADC TRIG4 selected
3829  *  0b00100000..ADC TRIG5 selected
3830  *  0b01000000..ADC TRIG6 selected
3831  *  0b10000000..ADC TRIG7 selected
3832  */
3833 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
3834 
3835 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK        (0x10000000U)
3836 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT       (28U)
3837 /*! B2B1
3838  *  0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached
3839  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3840  */
3841 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
3842 
3843 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK         (0x60000000U)
3844 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT        (29U)
3845 /*! IE1
3846  *  0b00..Generate interrupt on Done0 when Segment 1 finish.
3847  *  0b01..Generate interrupt on Done1 when Segment 1 finish.
3848  *  0b10..Generate interrupt on Done2 when Segment 1 finish.
3849  *  0b11..Generate interrupt on Done3 when Segment 1 finish.
3850  */
3851 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
3852 
3853 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK      (0x80000000U)
3854 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT     (31U)
3855 /*! IE1_EN
3856  *  0b0..Interrupt DONE disabled.
3857  *  0b1..Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1.
3858  */
3859 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
3860 /*! @} */
3861 
3862 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
3863 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT            (8U)
3864 
3865 /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
3866 /*! @{ */
3867 
3868 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK       (0xFU)
3869 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT      (0U)
3870 /*! CSEL2
3871  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3872  *  0b0001..ADC CMD1 selected.
3873  *  0b0010..ADC CMD2 selected.
3874  *  0b0011..ADC CMD3 selected.
3875  *  0b0100..ADC CMD4 selected.
3876  *  0b0101..ADC CMD5 selected.
3877  *  0b0110..ADC CMD6 selected.
3878  *  0b0111..ADC CMD7 selected.
3879  *  0b1000..ADC CMD8 selected.
3880  *  0b1001..ADC CMD9 selected.
3881  *  0b1010..ADC CMD10 selected.
3882  *  0b1011..ADC CMD11 selected.
3883  *  0b1100..ADC CMD12 selected.
3884  *  0b1101..ADC CMD13 selected.
3885  *  0b1110..ADC CMD14 selected.
3886  *  0b1111..ADC CMD15 selected.
3887  */
3888 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
3889 
3890 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK       (0xFF0U)
3891 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT      (4U)
3892 /*! HWTS2
3893  *  0b00000000..no trigger selected
3894  *  0b00000001..ADC TRIG0 selected
3895  *  0b00000010..ADC TRIG1 selected
3896  *  0b00000100..ADC TRIG2 selected
3897  *  0b00001000..ADC TRIG3 selected
3898  *  0b00010000..ADC TRIG4 selected
3899  *  0b00100000..ADC TRIG5 selected
3900  *  0b01000000..ADC TRIG6 selected
3901  *  0b10000000..ADC TRIG7 selected
3902  */
3903 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
3904 
3905 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK        (0x1000U)
3906 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT       (12U)
3907 /*! B2B2
3908  *  0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached
3909  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3910  */
3911 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
3912 
3913 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK         (0x6000U)
3914 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT        (13U)
3915 /*! IE2
3916  *  0b00..Generate interrupt on Done0 when segment 2 finish.
3917  *  0b01..Generate interrupt on Done1 when segment 2 finish.
3918  *  0b10..Generate interrupt on Done2 when segment 2 finish.
3919  *  0b11..Generate interrupt on Done3 when segment 2 finish.
3920  */
3921 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
3922 
3923 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK      (0x8000U)
3924 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT     (15U)
3925 /*! IE2_EN
3926  *  0b0..Interrupt DONE disabled.
3927  *  0b1..Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2.
3928  */
3929 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
3930 
3931 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK       (0xF0000U)
3932 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT      (16U)
3933 /*! CSEL3
3934  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3935  *  0b0001..ADC CMD1 selected.
3936  *  0b0010..ADC CMD2 selected.
3937  *  0b0011..ADC CMD3 selected.
3938  *  0b0100..ADC CMD4 selected.
3939  *  0b0101..ADC CMD5 selected.
3940  *  0b0110..ADC CMD6 selected.
3941  *  0b0111..ADC CMD7 selected.
3942  *  0b1000..ADC CMD8 selected.
3943  *  0b1001..ADC CMD9 selected.
3944  *  0b1010..ADC CMD10 selected.
3945  *  0b1011..ADC CMD11 selected.
3946  *  0b1100..ADC CMD12 selected.
3947  *  0b1101..ADC CMD13 selected.
3948  *  0b1110..ADC CMD14 selected.
3949  *  0b1111..ADC CMD15 selected.
3950  */
3951 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
3952 
3953 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK       (0xFF00000U)
3954 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT      (20U)
3955 /*! HWTS3
3956  *  0b00000000..no trigger selected
3957  *  0b00000001..ADC TRIG0 selected
3958  *  0b00000010..ADC TRIG1 selected
3959  *  0b00000100..ADC TRIG2 selected
3960  *  0b00001000..ADC TRIG3 selected
3961  *  0b00010000..ADC TRIG4 selected
3962  *  0b00100000..ADC TRIG5 selected
3963  *  0b01000000..ADC TRIG6 selected
3964  *  0b10000000..ADC TRIG7 selected
3965  */
3966 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
3967 
3968 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK        (0x10000000U)
3969 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT       (28U)
3970 /*! B2B3
3971  *  0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached
3972  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3973  */
3974 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
3975 
3976 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK         (0x60000000U)
3977 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT        (29U)
3978 /*! IE3
3979  *  0b00..Generate interrupt on Done0 when segment 3 finish.
3980  *  0b01..Generate interrupt on Done1 when segment 3 finish.
3981  *  0b10..Generate interrupt on Done2 when segment 3 finish.
3982  *  0b11..Generate interrupt on Done3 when segment 3 finish.
3983  */
3984 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
3985 
3986 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK      (0x80000000U)
3987 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT     (31U)
3988 /*! IE3_EN
3989  *  0b0..Interrupt DONE disabled.
3990  *  0b1..Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3.
3991  */
3992 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
3993 /*! @} */
3994 
3995 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
3996 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT            (8U)
3997 
3998 /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
3999 /*! @{ */
4000 
4001 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK       (0xFU)
4002 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT      (0U)
4003 /*! CSEL4
4004  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4005  *  0b0001..ADC CMD1 selected.
4006  *  0b0010..ADC CMD2 selected.
4007  *  0b0011..ADC CMD3 selected.
4008  *  0b0100..ADC CMD4 selected.
4009  *  0b0101..ADC CMD5 selected.
4010  *  0b0110..ADC CMD6 selected.
4011  *  0b0111..ADC CMD7 selected.
4012  *  0b1000..ADC CMD8 selected.
4013  *  0b1001..ADC CMD9 selected.
4014  *  0b1010..ADC CMD10 selected.
4015  *  0b1011..ADC CMD11 selected.
4016  *  0b1100..ADC CMD12 selected.
4017  *  0b1101..ADC CMD13 selected.
4018  *  0b1110..ADC CMD14 selected.
4019  *  0b1111..ADC CMD15 selected.
4020  */
4021 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
4022 
4023 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK       (0xFF0U)
4024 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT      (4U)
4025 /*! HWTS4
4026  *  0b00000000..no trigger selected
4027  *  0b00000001..ADC TRIG0 selected
4028  *  0b00000010..ADC TRIG1 selected
4029  *  0b00000100..ADC TRIG2 selected
4030  *  0b00001000..ADC TRIG3 selected
4031  *  0b00010000..ADC TRIG4 selected
4032  *  0b00100000..ADC TRIG5 selected
4033  *  0b01000000..ADC TRIG6 selected
4034  *  0b10000000..ADC TRIG7 selected
4035  */
4036 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
4037 
4038 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK        (0x1000U)
4039 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT       (12U)
4040 /*! B2B4
4041  *  0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached
4042  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4043  */
4044 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
4045 
4046 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK         (0x6000U)
4047 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT        (13U)
4048 /*! IE4
4049  *  0b00..Generate interrupt on Done0 when segment 4 finish.
4050  *  0b01..Generate interrupt on Done1 when segment 4 finish.
4051  *  0b10..Generate interrupt on Done2 when segment 4 finish.
4052  *  0b11..Generate interrupt on Done3 when segment 4 finish.
4053  */
4054 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
4055 
4056 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK      (0x8000U)
4057 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT     (15U)
4058 /*! IE4_EN
4059  *  0b0..Interrupt DONE disabled.
4060  *  0b1..Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4.
4061  */
4062 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
4063 
4064 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK       (0xF0000U)
4065 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT      (16U)
4066 /*! CSEL5
4067  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4068  *  0b0001..ADC CMD1 selected.
4069  *  0b0010..ADC CMD2 selected.
4070  *  0b0011..ADC CMD3 selected.
4071  *  0b0100..ADC CMD4 selected.
4072  *  0b0101..ADC CMD5 selected.
4073  *  0b0110..ADC CMD6 selected.
4074  *  0b0111..ADC CMD7 selected.
4075  *  0b1000..ADC CMD8 selected.
4076  *  0b1001..ADC CMD9 selected.
4077  *  0b1010..ADC CMD10 selected.
4078  *  0b1011..ADC CMD11 selected.
4079  *  0b1100..ADC CMD12 selected.
4080  *  0b1101..ADC CMD13 selected.
4081  *  0b1110..ADC CMD14 selected.
4082  *  0b1111..ADC CMD15 selected.
4083  */
4084 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
4085 
4086 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK       (0xFF00000U)
4087 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT      (20U)
4088 /*! HWTS5
4089  *  0b00000000..no trigger selected
4090  *  0b00000001..ADC TRIG0 selected
4091  *  0b00000010..ADC TRIG1 selected
4092  *  0b00000100..ADC TRIG2 selected
4093  *  0b00001000..ADC TRIG3 selected
4094  *  0b00010000..ADC TRIG4 selected
4095  *  0b00100000..ADC TRIG5 selected
4096  *  0b01000000..ADC TRIG6 selected
4097  *  0b10000000..ADC TRIG7 selected
4098  */
4099 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
4100 
4101 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK        (0x10000000U)
4102 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT       (28U)
4103 /*! B2B5
4104  *  0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached
4105  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4106  */
4107 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
4108 
4109 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK         (0x60000000U)
4110 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT        (29U)
4111 /*! IE5
4112  *  0b00..Generate interrupt on Done0 when segment 5 finish.
4113  *  0b01..Generate interrupt on Done1 when segment 5 finish.
4114  *  0b10..Generate interrupt on Done2 when segment 5 finish.
4115  *  0b11..Generate interrupt on Done3 when segment 5 finish.
4116  */
4117 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
4118 
4119 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK      (0x80000000U)
4120 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT     (31U)
4121 /*! IE5_EN
4122  *  0b0..Interrupt DONE disabled.
4123  *  0b1..Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5.
4124  */
4125 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
4126 /*! @} */
4127 
4128 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
4129 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT            (8U)
4130 
4131 /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
4132 /*! @{ */
4133 
4134 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK       (0xFU)
4135 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT      (0U)
4136 /*! CSEL6
4137  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4138  *  0b0001..ADC CMD1 selected.
4139  *  0b0010..ADC CMD2 selected.
4140  *  0b0011..ADC CMD3 selected.
4141  *  0b0100..ADC CMD4 selected.
4142  *  0b0101..ADC CMD5 selected.
4143  *  0b0110..ADC CMD6 selected.
4144  *  0b0111..ADC CMD7 selected.
4145  *  0b1000..ADC CMD8 selected.
4146  *  0b1001..ADC CMD9 selected.
4147  *  0b1010..ADC CMD10 selected.
4148  *  0b1011..ADC CMD11 selected.
4149  *  0b1100..ADC CMD12 selected.
4150  *  0b1101..ADC CMD13 selected.
4151  *  0b1110..ADC CMD14 selected.
4152  *  0b1111..ADC CMD15 selected.
4153  */
4154 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
4155 
4156 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK       (0xFF0U)
4157 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT      (4U)
4158 /*! HWTS6
4159  *  0b00000000..no trigger selected
4160  *  0b00000001..ADC TRIG0 selected
4161  *  0b00000010..ADC TRIG1 selected
4162  *  0b00000100..ADC TRIG2 selected
4163  *  0b00001000..ADC TRIG3 selected
4164  *  0b00010000..ADC TRIG4 selected
4165  *  0b00100000..ADC TRIG5 selected
4166  *  0b01000000..ADC TRIG6 selected
4167  *  0b10000000..ADC TRIG7 selected
4168  */
4169 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
4170 
4171 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK        (0x1000U)
4172 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT       (12U)
4173 /*! B2B6
4174  *  0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached
4175  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4176  */
4177 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
4178 
4179 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK         (0x6000U)
4180 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT        (13U)
4181 /*! IE6
4182  *  0b00..Generate interrupt on Done0 when segment 6 finish.
4183  *  0b01..Generate interrupt on Done1 when segment 6 finish.
4184  *  0b10..Generate interrupt on Done2 when segment 6 finish.
4185  *  0b11..Generate interrupt on Done3 when segment 6 finish.
4186  */
4187 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
4188 
4189 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK      (0x8000U)
4190 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT     (15U)
4191 /*! IE6_EN
4192  *  0b0..Interrupt DONE disabled.
4193  *  0b1..Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6.
4194  */
4195 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
4196 
4197 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK       (0xF0000U)
4198 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT      (16U)
4199 /*! CSEL7
4200  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4201  *  0b0001..ADC CMD1 selected.
4202  *  0b0010..ADC CMD2 selected.
4203  *  0b0011..ADC CMD3 selected.
4204  *  0b0100..ADC CMD4 selected.
4205  *  0b0101..ADC CMD5 selected.
4206  *  0b0110..ADC CMD6 selected.
4207  *  0b0111..ADC CMD7 selected.
4208  *  0b1000..ADC CMD8 selected.
4209  *  0b1001..ADC CMD9 selected.
4210  *  0b1010..ADC CMD10 selected.
4211  *  0b1011..ADC CMD11 selected.
4212  *  0b1100..ADC CMD12 selected.
4213  *  0b1101..ADC CMD13 selected.
4214  *  0b1110..ADC CMD14 selected.
4215  *  0b1111..ADC CMD15 selected.
4216  */
4217 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
4218 
4219 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK       (0xFF00000U)
4220 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT      (20U)
4221 /*! HWTS7
4222  *  0b00000000..no trigger selected
4223  *  0b00000001..ADC TRIG0 selected
4224  *  0b00000010..ADC TRIG1 selected
4225  *  0b00000100..ADC TRIG2 selected
4226  *  0b00001000..ADC TRIG3 selected
4227  *  0b00010000..ADC TRIG4 selected
4228  *  0b00100000..ADC TRIG5 selected
4229  *  0b01000000..ADC TRIG6 selected
4230  *  0b10000000..ADC TRIG7 selected
4231  */
4232 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
4233 
4234 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK        (0x10000000U)
4235 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT       (28U)
4236 /*! B2B7
4237  *  0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached
4238  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4239  */
4240 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
4241 
4242 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK         (0x60000000U)
4243 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT        (29U)
4244 /*! IE7
4245  *  0b00..Generate interrupt on Done0 when segment 7 finish.
4246  *  0b01..Generate interrupt on Done1 when segment 7 finish.
4247  *  0b10..Generate interrupt on Done2 when segment 7 finish.
4248  *  0b11..Generate interrupt on Done3 when segment 7 finish.
4249  */
4250 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
4251 
4252 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK      (0x80000000U)
4253 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT     (31U)
4254 /*! IE7_EN
4255  *  0b0..Interrupt DONE disabled.
4256  *  0b1..Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7.
4257  */
4258 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
4259 /*! @} */
4260 
4261 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
4262 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT            (8U)
4263 
4264 /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
4265 /*! @{ */
4266 
4267 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK      (0xFFFU)
4268 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT     (0U)
4269 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
4270 
4271 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK      (0xFFF0000U)
4272 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT     (16U)
4273 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
4274 /*! @} */
4275 
4276 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
4277 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT           (8U)
4278 
4279 /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
4280 /*! @{ */
4281 
4282 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK      (0xFFFU)
4283 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT     (0U)
4284 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
4285 
4286 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK      (0xFFF0000U)
4287 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT     (16U)
4288 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
4289 /*! @} */
4290 
4291 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
4292 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT           (8U)
4293 
4294 /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
4295 /*! @{ */
4296 
4297 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK      (0xFFFU)
4298 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT     (0U)
4299 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
4300 
4301 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK      (0xFFF0000U)
4302 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT     (16U)
4303 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
4304 /*! @} */
4305 
4306 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
4307 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT           (8U)
4308 
4309 /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
4310 /*! @{ */
4311 
4312 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK      (0xFFFU)
4313 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT     (0U)
4314 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
4315 
4316 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK      (0xFFF0000U)
4317 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT     (16U)
4318 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
4319 /*! @} */
4320 
4321 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
4322 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT           (8U)
4323 
4324 
4325 /*!
4326  * @}
4327  */ /* end of group ADC_ETC_Register_Masks */
4328 
4329 
4330 /* ADC_ETC - Peripheral instance base addresses */
4331 /** Peripheral ADC_ETC base address */
4332 #define ADC_ETC_BASE                             (0x40048000u)
4333 /** Peripheral ADC_ETC base pointer */
4334 #define ADC_ETC                                  ((ADC_ETC_Type *)ADC_ETC_BASE)
4335 /** Array initializer of ADC_ETC peripheral base addresses */
4336 #define ADC_ETC_BASE_ADDRS                       { ADC_ETC_BASE }
4337 /** Array initializer of ADC_ETC peripheral base pointers */
4338 #define ADC_ETC_BASE_PTRS                        { ADC_ETC }
4339 /** Interrupt vectors for the ADC_ETC peripheral type */
4340 #define ADC_ETC_IRQS                             { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
4341 #define ADC_ETC_FAULT_IRQS                       { ADC_ETC_ERROR_IRQ_IRQn }
4342 
4343 /*!
4344  * @}
4345  */ /* end of group ADC_ETC_Peripheral_Access_Layer */
4346 
4347 
4348 /* ----------------------------------------------------------------------------
4349    -- ANADIG_LDO_SNVS Peripheral Access Layer
4350    ---------------------------------------------------------------------------- */
4351 
4352 /*!
4353  * @addtogroup ANADIG_LDO_SNVS_Peripheral_Access_Layer ANADIG_LDO_SNVS Peripheral Access Layer
4354  * @{
4355  */
4356 
4357 /** ANADIG_LDO_SNVS - Register Layout Typedef */
4358 typedef struct {
4359        uint8_t RESERVED_0[1296];
4360   __IO uint32_t PMU_LDO_LPSR_ANA;                  /**< PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510 */
4361        uint8_t RESERVED_1[12];
4362   __IO uint32_t PMU_LDO_LPSR_DIG_2;                /**< PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520 */
4363        uint8_t RESERVED_2[12];
4364   __IO uint32_t PMU_LDO_LPSR_DIG;                  /**< PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530 */
4365 } ANADIG_LDO_SNVS_Type;
4366 
4367 /* ----------------------------------------------------------------------------
4368    -- ANADIG_LDO_SNVS Register Masks
4369    ---------------------------------------------------------------------------- */
4370 
4371 /*!
4372  * @addtogroup ANADIG_LDO_SNVS_Register_Masks ANADIG_LDO_SNVS Register Masks
4373  * @{
4374  */
4375 
4376 /*! @name PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER */
4377 /*! @{ */
4378 
4379 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U)
4380 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U)
4381 /*! REG_LP_EN - reg_lp_en
4382  */
4383 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK)
4384 
4385 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U)
4386 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U)
4387 /*! REG_DISABLE - reg_disable
4388  */
4389 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK)
4390 
4391 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
4392 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
4393 /*! PULL_DOWN_2MA_EN - pull_down_2ma_en
4394  */
4395 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK)
4396 
4397 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U)
4398 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U)
4399 /*! LPSR_ANA_CONTROL_MODE - LPSR_ANA_CONTROL_MODE
4400  *  0b0..SW Control
4401  *  0b1..HW Control
4402  */
4403 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK)
4404 
4405 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U)
4406 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U)
4407 /*! BYPASS_MODE_EN - bypass_mode_en
4408  */
4409 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK)
4410 
4411 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U)
4412 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U)
4413 /*! STANDBY_EN - standby_en
4414  */
4415 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK)
4416 
4417 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
4418 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
4419 /*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en
4420  */
4421 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
4422 
4423 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U)
4424 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U)
4425 /*! TRACK_MODE_EN - Track Mode Enable
4426  *  0b0..Normal use
4427  *  0b1..Switch preparation
4428  */
4429 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK)
4430 
4431 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
4432 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
4433 /*! PULL_DOWN_20UA_EN - pull_down_20ua_en
4434  */
4435 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK)
4436 /*! @} */
4437 
4438 /*! @name PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER */
4439 /*! @{ */
4440 
4441 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U)
4442 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U)
4443 /*! VOLTAGE_STEP_INC - voltage_step_inc
4444  */
4445 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK)
4446 /*! @} */
4447 
4448 /*! @name PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER */
4449 /*! @{ */
4450 
4451 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U)
4452 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U)
4453 /*! REG_EN - ENABLE_ILIMIT
4454  */
4455 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK)
4456 
4457 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U)
4458 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U)
4459 /*! LPSR_DIG_CONTROL_MODE - LPSR_DIG_CONTROL_MODE
4460  *  0b0..SW Control
4461  *  0b1..HW Control
4462  */
4463 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK)
4464 
4465 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U)
4466 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U)
4467 /*! STANDBY_EN - standby_en
4468  */
4469 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK)
4470 
4471 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U)
4472 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U)
4473 /*! TRACKING_MODE - tracking_mode
4474  */
4475 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK)
4476 
4477 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U)
4478 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U)
4479 /*! BYPASS_MODE - bypass_mode
4480  */
4481 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK)
4482 
4483 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
4484 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U)
4485 /*! VOLTAGE_SELECT - VOLTAGE_SELECT
4486  *  0b00000..Stable Voltage (range)
4487  *  0b00001..Stable Voltage (range)
4488  *  0b00010..Stable Voltage (range)
4489  *  0b00011..Stable Voltage (range)
4490  *  0b00100..Stable Voltage (range)
4491  *  0b00101..Stable Voltage (range)
4492  *  0b00110..Stable Voltage (range)
4493  *  0b00111..Stable Voltage (range)
4494  *  0b01000..Stable Voltage (range)
4495  *  0b01001..Stable Voltage (range)
4496  *  0b01010..Stable Voltage (range)
4497  *  0b01011..Stable Voltage (range)
4498  *  0b01100..Stable Voltage (range)
4499  *  0b01101..Stable Voltage (range)
4500  *  0b01110..Stable Voltage (range)
4501  *  0b01111..Stable Voltage (range)
4502  *  0b10000..Stable Voltage (range)
4503  *  0b10001..Stable Voltage (range)
4504  *  0b10010..Stable Voltage (range)
4505  *  0b10011..Stable Voltage (range)
4506  *  0b10100..Stable Voltage (range)
4507  *  0b10101..Stable Voltage (range)
4508  *  0b10110..Stable Voltage (range)
4509  *  0b10111..Stable Voltage (range)
4510  *  0b11000..Stable Voltage (range)
4511  *  0b11001..Stable Voltage (range)
4512  *  0b11010..Stable Voltage (range)
4513  *  0b11011..Stable Voltage (range)
4514  *  0b11100..Stable Voltage (range)
4515  *  0b11101..Stable Voltage (range)
4516  *  0b11110..Stable Voltage (range)
4517  *  0b11111..Stable Voltage (range)
4518  */
4519 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK)
4520 /*! @} */
4521 
4522 
4523 /*!
4524  * @}
4525  */ /* end of group ANADIG_LDO_SNVS_Register_Masks */
4526 
4527 
4528 /* ANADIG_LDO_SNVS - Peripheral instance base addresses */
4529 /** Peripheral ANADIG_LDO_SNVS base address */
4530 #define ANADIG_LDO_SNVS_BASE                     (0x40C84000u)
4531 /** Peripheral ANADIG_LDO_SNVS base pointer */
4532 #define ANADIG_LDO_SNVS                          ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
4533 /** Array initializer of ANADIG_LDO_SNVS peripheral base addresses */
4534 #define ANADIG_LDO_SNVS_BASE_ADDRS               { ANADIG_LDO_SNVS_BASE }
4535 /** Array initializer of ANADIG_LDO_SNVS peripheral base pointers */
4536 #define ANADIG_LDO_SNVS_BASE_PTRS                { ANADIG_LDO_SNVS }
4537 
4538 /*!
4539  * @}
4540  */ /* end of group ANADIG_LDO_SNVS_Peripheral_Access_Layer */
4541 
4542 
4543 /* ----------------------------------------------------------------------------
4544    -- ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4545    ---------------------------------------------------------------------------- */
4546 
4547 /*!
4548  * @addtogroup ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4549  * @{
4550  */
4551 
4552 /** ANADIG_LDO_SNVS_DIG - Register Layout Typedef */
4553 typedef struct {
4554        uint8_t RESERVED_0[1344];
4555   __IO uint32_t PMU_LDO_SNVS_DIG;                  /**< PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540 */
4556 } ANADIG_LDO_SNVS_DIG_Type;
4557 
4558 /* ----------------------------------------------------------------------------
4559    -- ANADIG_LDO_SNVS_DIG Register Masks
4560    ---------------------------------------------------------------------------- */
4561 
4562 /*!
4563  * @addtogroup ANADIG_LDO_SNVS_DIG_Register_Masks ANADIG_LDO_SNVS_DIG Register Masks
4564  * @{
4565  */
4566 
4567 /*! @name PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER */
4568 /*! @{ */
4569 
4570 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U)
4571 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U)
4572 /*! REG_LP_EN - REG_LP_EN
4573  */
4574 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK)
4575 
4576 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U)
4577 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U)
4578 /*! TEST_OVERRIDE - test_override
4579  */
4580 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK)
4581 
4582 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U)
4583 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U)
4584 /*! REG_EN - REG_EN
4585  */
4586 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK)
4587 /*! @} */
4588 
4589 
4590 /*!
4591  * @}
4592  */ /* end of group ANADIG_LDO_SNVS_DIG_Register_Masks */
4593 
4594 
4595 /* ANADIG_LDO_SNVS_DIG - Peripheral instance base addresses */
4596 /** Peripheral ANADIG_LDO_SNVS_DIG base address */
4597 #define ANADIG_LDO_SNVS_DIG_BASE                 (0x40C84000u)
4598 /** Peripheral ANADIG_LDO_SNVS_DIG base pointer */
4599 #define ANADIG_LDO_SNVS_DIG                      ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
4600 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base addresses */
4601 #define ANADIG_LDO_SNVS_DIG_BASE_ADDRS           { ANADIG_LDO_SNVS_DIG_BASE }
4602 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base pointers */
4603 #define ANADIG_LDO_SNVS_DIG_BASE_PTRS            { ANADIG_LDO_SNVS_DIG }
4604 
4605 /*!
4606  * @}
4607  */ /* end of group ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer */
4608 
4609 
4610 /* ----------------------------------------------------------------------------
4611    -- ANADIG_MISC Peripheral Access Layer
4612    ---------------------------------------------------------------------------- */
4613 
4614 /*!
4615  * @addtogroup ANADIG_MISC_Peripheral_Access_Layer ANADIG_MISC Peripheral Access Layer
4616  * @{
4617  */
4618 
4619 /** ANADIG_MISC - Register Layout Typedef */
4620 typedef struct {
4621        uint8_t RESERVED_0[2048];
4622   __I  uint32_t MISC_DIFPROG;                      /**< Chip Silicon Version Register, offset: 0x800 */
4623        uint8_t RESERVED_1[28];
4624   __IO uint32_t VDDSOC_AI_CTRL;                    /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x820 */
4625        uint8_t RESERVED_2[12];
4626   __IO uint32_t VDDSOC_AI_WDATA;                   /**< VDDSOC_AI_WDATA_REGISTER, offset: 0x830 */
4627        uint8_t RESERVED_3[12];
4628   __I  uint32_t VDDSOC_AI_RDATA;                   /**< VDDSOC_AI_RDATA_REGISTER, offset: 0x840 */
4629        uint8_t RESERVED_4[12];
4630   __IO uint32_t VDDSOC2PLL_AI_CTRL_1G;             /**< VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850 */
4631        uint8_t RESERVED_5[12];
4632   __IO uint32_t VDDSOC2PLL_AI_WDATA_1G;            /**< VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860 */
4633        uint8_t RESERVED_6[12];
4634   __I  uint32_t VDDSOC2PLL_AI_RDATA_1G;            /**< VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870 */
4635        uint8_t RESERVED_7[12];
4636   __IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO;          /**< VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880 */
4637        uint8_t RESERVED_8[12];
4638   __IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO;         /**< VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890 */
4639        uint8_t RESERVED_9[12];
4640   __I  uint32_t VDDSOC2PLL_AI_RDATA_AUDIO;         /**< VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0 */
4641        uint8_t RESERVED_10[12];
4642   __IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO;          /**< VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0 */
4643        uint8_t RESERVED_11[12];
4644   __IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO;         /**< VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0 */
4645        uint8_t RESERVED_12[12];
4646   __I  uint32_t VDDSOC2PLL_AI_RDATA_VIDEO;         /**< VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0 */
4647        uint8_t RESERVED_13[12];
4648   __IO uint32_t VDDLPSR_AI_CTRL;                   /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0 */
4649        uint8_t RESERVED_14[12];
4650   __IO uint32_t VDDLPSR_AI_WDATA;                  /**< VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0 */
4651        uint8_t RESERVED_15[12];
4652   __I  uint32_t VDDLPSR_AI_RDATA_REFTOP;           /**< VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900 */
4653        uint8_t RESERVED_16[12];
4654   __I  uint32_t VDDLPSR_AI_RDATA_TMPSNS;           /**< VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910 */
4655        uint8_t RESERVED_17[12];
4656   __IO uint32_t VDDLPSR_AI400M_CTRL;               /**< VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920 */
4657        uint8_t RESERVED_18[12];
4658   __IO uint32_t VDDLPSR_AI400M_WDATA;              /**< VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930 */
4659        uint8_t RESERVED_19[12];
4660   __I  uint32_t VDDLPSR_AI400M_RDATA;              /**< VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940 */
4661 } ANADIG_MISC_Type;
4662 
4663 /* ----------------------------------------------------------------------------
4664    -- ANADIG_MISC Register Masks
4665    ---------------------------------------------------------------------------- */
4666 
4667 /*!
4668  * @addtogroup ANADIG_MISC_Register_Masks ANADIG_MISC Register Masks
4669  * @{
4670  */
4671 
4672 /*! @name MISC_DIFPROG - Chip Silicon Version Register */
4673 /*! @{ */
4674 
4675 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK     (0xFFFFFFFFU)
4676 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT    (0U)
4677 /*! CHIPID - Chip ID
4678  */
4679 #define ANADIG_MISC_MISC_DIFPROG_CHIPID(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
4680 /*! @} */
4681 
4682 /*! @name VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4683 /*! @{ */
4684 
4685 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)
4686 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)
4687 /*! VDDSOC_AI_ADDR - VDDSOC_AI_ADDR
4688  */
4689 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)
4690 
4691 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)
4692 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)
4693 /*! VDDSOC_AIRWB - VDDSOC_AIRWB
4694  */
4695 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)
4696 /*! @} */
4697 
4698 /*! @name VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER */
4699 /*! @{ */
4700 
4701 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)
4702 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)
4703 /*! VDDSOC_AI_WDATA - VDDSOC_AI_WDATA
4704  */
4705 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)
4706 /*! @} */
4707 
4708 /*! @name VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER */
4709 /*! @{ */
4710 
4711 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)
4712 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)
4713 /*! VDDSOC_AI_RDATA - VDDSOC_AI_RDATA
4714  */
4715 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)
4716 /*! @} */
4717 
4718 /*! @name VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER */
4719 /*! @{ */
4720 
4721 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)
4722 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)
4723 /*! VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G
4724  */
4725 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)
4726 
4727 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)
4728 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)
4729 /*! VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G
4730  */
4731 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)
4732 
4733 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)
4734 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)
4735 /*! VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G
4736  */
4737 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)
4738 
4739 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)
4740 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)
4741 /*! VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G
4742  */
4743 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)
4744 /*! @} */
4745 
4746 /*! @name VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER */
4747 /*! @{ */
4748 
4749 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)
4750 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)
4751 /*! VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G
4752  */
4753 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)
4754 /*! @} */
4755 
4756 /*! @name VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER */
4757 /*! @{ */
4758 
4759 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)
4760 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)
4761 /*! VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G
4762  */
4763 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)
4764 /*! @} */
4765 
4766 /*! @name VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER */
4767 /*! @{ */
4768 
4769 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)
4770 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)
4771 /*! VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO
4772  */
4773 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)
4774 
4775 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)
4776 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)
4777 /*! VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO
4778  */
4779 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)
4780 
4781 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)
4782 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)
4783 /*! VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO
4784  */
4785 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)
4786 
4787 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)
4788 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)
4789 /*! VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB
4790  */
4791 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)
4792 /*! @} */
4793 
4794 /*! @name VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER */
4795 /*! @{ */
4796 
4797 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)
4798 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)
4799 /*! VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO
4800  */
4801 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)
4802 /*! @} */
4803 
4804 /*! @name VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER */
4805 /*! @{ */
4806 
4807 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)
4808 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)
4809 /*! VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO
4810  */
4811 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)
4812 /*! @} */
4813 
4814 /*! @name VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER */
4815 /*! @{ */
4816 
4817 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)
4818 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)
4819 /*! VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO
4820  */
4821 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)
4822 
4823 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)
4824 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)
4825 /*! VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO
4826  */
4827 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)
4828 
4829 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)
4830 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)
4831 /*! VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO
4832  */
4833 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)
4834 
4835 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)
4836 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)
4837 /*! VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO
4838  */
4839 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)
4840 /*! @} */
4841 
4842 /*! @name VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER */
4843 /*! @{ */
4844 
4845 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)
4846 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)
4847 /*! VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO
4848  */
4849 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)
4850 /*! @} */
4851 
4852 /*! @name VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER */
4853 /*! @{ */
4854 
4855 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)
4856 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)
4857 /*! VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO
4858  */
4859 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)
4860 /*! @} */
4861 
4862 /*! @name VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4863 /*! @{ */
4864 
4865 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)
4866 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)
4867 /*! VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR
4868  */
4869 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)
4870 
4871 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)
4872 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)
4873 /*! VDDLPSR_AIRWB - VDDLPSR_AIRWB
4874  */
4875 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)
4876 /*! @} */
4877 
4878 /*! @name VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER */
4879 /*! @{ */
4880 
4881 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)
4882 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)
4883 /*! VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA
4884  */
4885 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)
4886 /*! @} */
4887 
4888 /*! @name VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER */
4889 /*! @{ */
4890 
4891 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)
4892 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)
4893 /*! VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP
4894  */
4895 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)
4896 /*! @} */
4897 
4898 /*! @name VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER */
4899 /*! @{ */
4900 
4901 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)
4902 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)
4903 /*! VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS
4904  */
4905 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)
4906 /*! @} */
4907 
4908 /*! @name VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER */
4909 /*! @{ */
4910 
4911 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)
4912 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)
4913 /*! VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR
4914  */
4915 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)
4916 
4917 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)
4918 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)
4919 /*! VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M
4920  */
4921 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)
4922 
4923 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)
4924 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)
4925 /*! VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M
4926  */
4927 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)
4928 
4929 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)
4930 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)
4931 /*! VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB
4932  */
4933 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)
4934 /*! @} */
4935 
4936 /*! @name VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER */
4937 /*! @{ */
4938 
4939 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)
4940 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)
4941 /*! VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA
4942  */
4943 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)
4944 /*! @} */
4945 
4946 /*! @name VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER */
4947 /*! @{ */
4948 
4949 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)
4950 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)
4951 /*! VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA
4952  */
4953 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)
4954 /*! @} */
4955 
4956 
4957 /*!
4958  * @}
4959  */ /* end of group ANADIG_MISC_Register_Masks */
4960 
4961 
4962 /* ANADIG_MISC - Peripheral instance base addresses */
4963 /** Peripheral ANADIG_MISC base address */
4964 #define ANADIG_MISC_BASE                         (0x40C84000u)
4965 /** Peripheral ANADIG_MISC base pointer */
4966 #define ANADIG_MISC                              ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
4967 /** Array initializer of ANADIG_MISC peripheral base addresses */
4968 #define ANADIG_MISC_BASE_ADDRS                   { ANADIG_MISC_BASE }
4969 /** Array initializer of ANADIG_MISC peripheral base pointers */
4970 #define ANADIG_MISC_BASE_PTRS                    { ANADIG_MISC }
4971 
4972 /*!
4973  * @}
4974  */ /* end of group ANADIG_MISC_Peripheral_Access_Layer */
4975 
4976 
4977 /* ----------------------------------------------------------------------------
4978    -- ANADIG_OSC Peripheral Access Layer
4979    ---------------------------------------------------------------------------- */
4980 
4981 /*!
4982  * @addtogroup ANADIG_OSC_Peripheral_Access_Layer ANADIG_OSC Peripheral Access Layer
4983  * @{
4984  */
4985 
4986 /** ANADIG_OSC - Register Layout Typedef */
4987 typedef struct {
4988        uint8_t RESERVED_0[16];
4989   __IO uint32_t OSC_48M_CTRL;                      /**< 48MHz RCOSC Control Register, offset: 0x10 */
4990        uint8_t RESERVED_1[12];
4991   __IO uint32_t OSC_24M_CTRL;                      /**< 24MHz OSC Control Register, offset: 0x20 */
4992        uint8_t RESERVED_2[28];
4993   __I  uint32_t OSC_400M_CTRL0;                    /**< 400MHz RCOSC Control0 Register, offset: 0x40 */
4994        uint8_t RESERVED_3[12];
4995   __IO uint32_t OSC_400M_CTRL1;                    /**< 400MHz RCOSC Control1 Register, offset: 0x50 */
4996        uint8_t RESERVED_4[12];
4997   __IO uint32_t OSC_400M_CTRL2;                    /**< 400MHz RCOSC Control2 Register, offset: 0x60 */
4998        uint8_t RESERVED_5[92];
4999   __IO uint32_t OSC_16M_CTRL;                      /**< 16MHz RCOSC Control Register, offset: 0xC0 */
5000 } ANADIG_OSC_Type;
5001 
5002 /* ----------------------------------------------------------------------------
5003    -- ANADIG_OSC Register Masks
5004    ---------------------------------------------------------------------------- */
5005 
5006 /*!
5007  * @addtogroup ANADIG_OSC_Register_Masks ANADIG_OSC Register Masks
5008  * @{
5009  */
5010 
5011 /*! @name OSC_48M_CTRL - 48MHz RCOSC Control Register */
5012 /*! @{ */
5013 
5014 #define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK         (0x2U)
5015 #define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT        (1U)
5016 /*! TEN - 48MHz RCOSC Enable
5017  *  0b0..Power down
5018  *  0b1..Power up
5019  */
5020 #define ANADIG_OSC_OSC_48M_CTRL_TEN(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
5021 
5022 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U)
5023 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U)
5024 /*! RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable
5025  *  0b0..Disable
5026  *  0b1..Enable
5027  */
5028 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
5029 
5030 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U)
5031 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U)
5032 /*! RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode
5033  *  0b0..Software mode (default)
5034  *  0b1..GPC mode (Setpoint)
5035  */
5036 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
5037 
5038 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U)
5039 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U)
5040 /*! RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode
5041  *  0b0..Software mode (default)
5042  *  0b1..GPC mode (Setpoint)
5043  */
5044 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)
5045 /*! @} */
5046 
5047 /*! @name OSC_24M_CTRL - 24MHz OSC Control Register */
5048 /*! @{ */
5049 
5050 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK  (0x1U)
5051 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U)
5052 /*! BYPASS_CLK - 24MHz OSC Bypass Clock
5053  */
5054 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
5055 
5056 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
5057 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT  (1U)
5058 /*! BYPASS_EN - 24MHz OSC Bypass Enable
5059  *  0b0..Disable
5060  *  0b1..Enable
5061  */
5062 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
5063 
5064 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK       (0x4U)
5065 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT      (2U)
5066 /*! LP_EN - 24MHz OSC Low-Power Mode Enable
5067  *  0b0..High Gain mode (HP)
5068  *  0b1..Low-power mode (LP)
5069  */
5070 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
5071 
5072 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
5073 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
5074 /*! OSC_COMP_MODE - 24MHz OSC Comparator Mode
5075  *  0b0..Single-ended mode (default)
5076  *  0b1..Differential mode (test mode)
5077  */
5078 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
5079 
5080 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK      (0x10U)
5081 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT     (4U)
5082 /*! OSC_EN - 24MHz OSC Enable
5083  *  0b0..Disable
5084  *  0b1..Enable
5085  */
5086 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
5087 
5088 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
5089 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
5090 /*! OSC_24M_GATE - 24MHz OSC Gate Control
5091  *  0b0..Not Gated
5092  *  0b1..Gated
5093  */
5094 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
5095 
5096 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
5097 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
5098 /*! OSC_24M_STABLE - 24MHz OSC Stable
5099  *  0b0..Not Stable
5100  *  0b1..Stable
5101  */
5102 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
5103 
5104 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
5105 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
5106 /*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode
5107  *  0b0..Software mode (default)
5108  *  0b1..GPC mode (Setpoint)
5109  */
5110 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
5111 /*! @} */
5112 
5113 /*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */
5114 /*! @{ */
5115 
5116 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
5117 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
5118 /*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY
5119  */
5120 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
5121 /*! @} */
5122 
5123 /*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */
5124 /*! @{ */
5125 
5126 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK       (0x1U)
5127 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT      (0U)
5128 /*! PWD - Power down control for 400MHz RCOSC
5129  *  0b0..No Power down
5130  *  0b1..Power down
5131  */
5132 #define ANADIG_OSC_OSC_400M_CTRL1_PWD(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
5133 
5134 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
5135 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
5136 /*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC
5137  *  0b0..Not Gated
5138  *  0b1..Gated
5139  */
5140 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
5141 
5142 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
5143 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
5144 /*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode
5145  *  0b0..Software mode (default)
5146  *  0b1..GPC mode (Setpoint)
5147  */
5148 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
5149 /*! @} */
5150 
5151 /*! @name OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register */
5152 /*! @{ */
5153 
5154 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U)
5155 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U)
5156 /*! ENABLE_CLK - Clock enable
5157  *  0b0..Clock is disabled before entering GPC mode
5158  *  0b1..Clock is enabled before entering GPC mode
5159  */
5160 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
5161 
5162 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK  (0x400U)
5163 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
5164 /*! TUNE_BYP - Bypass tuning logic
5165  *  0b0..Use the output of tuning logic to run the oscillator
5166  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
5167  */
5168 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
5169 
5170 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
5171 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
5172 /*! OSC_TUNE_VAL - Oscillator Tune Value
5173  */
5174 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)
5175 /*! @} */
5176 
5177 /*! @name OSC_16M_CTRL - 16MHz RCOSC Control Register */
5178 /*! @{ */
5179 
5180 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U)
5181 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U)
5182 /*! EN_IRC4M16M - Enable Clock Output
5183  *  0b0..Disable
5184  *  0b1..Enable
5185  */
5186 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
5187 
5188 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U)
5189 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U)
5190 /*! EN_POWER_SAVE - Power Save Enable
5191  *  0b0..Disable
5192  *  0b1..Enable
5193  */
5194 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
5195 
5196 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U)
5197 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U)
5198 /*! SOURCE_SEL_16M - Source select
5199  *  0b0..16MHz Oscillator
5200  *  0b1..24MHz Oscillator
5201  */
5202 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
5203 
5204 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U)
5205 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U)
5206 /*! RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator
5207  *  0b0..Software mode (default)
5208  *  0b1..GPC mode (Setpoint)
5209  */
5210 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)
5211 /*! @} */
5212 
5213 
5214 /*!
5215  * @}
5216  */ /* end of group ANADIG_OSC_Register_Masks */
5217 
5218 
5219 /* ANADIG_OSC - Peripheral instance base addresses */
5220 /** Peripheral ANADIG_OSC base address */
5221 #define ANADIG_OSC_BASE                          (0x40C84000u)
5222 /** Peripheral ANADIG_OSC base pointer */
5223 #define ANADIG_OSC                               ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
5224 /** Array initializer of ANADIG_OSC peripheral base addresses */
5225 #define ANADIG_OSC_BASE_ADDRS                    { ANADIG_OSC_BASE }
5226 /** Array initializer of ANADIG_OSC peripheral base pointers */
5227 #define ANADIG_OSC_BASE_PTRS                     { ANADIG_OSC }
5228 
5229 /*!
5230  * @}
5231  */ /* end of group ANADIG_OSC_Peripheral_Access_Layer */
5232 
5233 
5234 /* ----------------------------------------------------------------------------
5235    -- ANADIG_PLL Peripheral Access Layer
5236    ---------------------------------------------------------------------------- */
5237 
5238 /*!
5239  * @addtogroup ANADIG_PLL_Peripheral_Access_Layer ANADIG_PLL Peripheral Access Layer
5240  * @{
5241  */
5242 
5243 /** ANADIG_PLL - Register Layout Typedef */
5244 typedef struct {
5245        uint8_t RESERVED_0[512];
5246   __IO uint32_t ARM_PLL_CTRL;                      /**< ARM_PLL_CTRL_REGISTER, offset: 0x200 */
5247        uint8_t RESERVED_1[12];
5248   __IO uint32_t SYS_PLL3_CTRL;                     /**< SYS_PLL3_CTRL_REGISTER, offset: 0x210 */
5249        uint8_t RESERVED_2[12];
5250   __IO uint32_t SYS_PLL3_UPDATE;                   /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x220 */
5251        uint8_t RESERVED_3[12];
5252   __IO uint32_t SYS_PLL3_PFD;                      /**< SYS_PLL3_PFD_REGISTER, offset: 0x230 */
5253        uint8_t RESERVED_4[12];
5254   __IO uint32_t SYS_PLL2_CTRL;                     /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */
5255        uint8_t RESERVED_5[12];
5256   __IO uint32_t SYS_PLL2_UPDATE;                   /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x250 */
5257        uint8_t RESERVED_6[12];
5258   __IO uint32_t SYS_PLL2_SS;                       /**< SYS_PLL2_SS_REGISTER, offset: 0x260 */
5259        uint8_t RESERVED_7[12];
5260   __IO uint32_t SYS_PLL2_PFD;                      /**< SYS_PLL2_PFD_REGISTER, offset: 0x270 */
5261        uint8_t RESERVED_8[44];
5262   __IO uint32_t SYS_PLL2_MFD;                      /**< SYS_PLL2_MFD_REGISTER, offset: 0x2A0 */
5263        uint8_t RESERVED_9[12];
5264   __IO uint32_t SYS_PLL1_SS;                       /**< SYS_PLL1_SS_REGISTER, offset: 0x2B0 */
5265        uint8_t RESERVED_10[12];
5266   __IO uint32_t SYS_PLL1_CTRL;                     /**< SYS_PLL1_CTRL_REGISTER, offset: 0x2C0 */
5267        uint8_t RESERVED_11[12];
5268   __IO uint32_t SYS_PLL1_DENOMINATOR;              /**< SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0 */
5269        uint8_t RESERVED_12[12];
5270   __IO uint32_t SYS_PLL1_NUMERATOR;                /**< SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0 */
5271        uint8_t RESERVED_13[12];
5272   __IO uint32_t SYS_PLL1_DIV_SELECT;               /**< SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0 */
5273        uint8_t RESERVED_14[12];
5274   __IO uint32_t PLL_AUDIO_CTRL;                    /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x300 */
5275        uint8_t RESERVED_15[12];
5276   __IO uint32_t PLL_AUDIO_SS;                      /**< PLL_AUDIO_SS_REGISTER, offset: 0x310 */
5277        uint8_t RESERVED_16[12];
5278   __IO uint32_t PLL_AUDIO_DENOMINATOR;             /**< PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320 */
5279        uint8_t RESERVED_17[12];
5280   __IO uint32_t PLL_AUDIO_NUMERATOR;               /**< PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330 */
5281        uint8_t RESERVED_18[12];
5282   __IO uint32_t PLL_AUDIO_DIV_SELECT;              /**< PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340 */
5283        uint8_t RESERVED_19[12];
5284   __IO uint32_t PLL_VIDEO_CTRL;                    /**< PLL_VIDEO_CTRL_REGISTER, offset: 0x350 */
5285        uint8_t RESERVED_20[12];
5286   __IO uint32_t PLL_VIDEO_SS;                      /**< PLL_VIDEO_SS_REGISTER, offset: 0x360 */
5287        uint8_t RESERVED_21[12];
5288   __IO uint32_t PLL_VIDEO_DENOMINATOR;             /**< PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370 */
5289        uint8_t RESERVED_22[12];
5290   __IO uint32_t PLL_VIDEO_NUMERATOR;               /**< PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380 */
5291        uint8_t RESERVED_23[12];
5292   __IO uint32_t PLL_VIDEO_DIV_SELECT;              /**< PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390 */
5293 } ANADIG_PLL_Type;
5294 
5295 /* ----------------------------------------------------------------------------
5296    -- ANADIG_PLL Register Masks
5297    ---------------------------------------------------------------------------- */
5298 
5299 /*!
5300  * @addtogroup ANADIG_PLL_Register_Masks ANADIG_PLL Register Masks
5301  * @{
5302  */
5303 
5304 /*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */
5305 /*! @{ */
5306 
5307 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK  (0xFFU)
5308 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
5309 /*! DIV_SELECT - DIV_SELECT
5310  */
5311 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
5312 
5313 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
5314 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
5315 /*! HOLD_RING_OFF - PLL Start up initialization
5316  *  0b0..Normal operation
5317  *  0b1..Initialize PLL start up
5318  */
5319 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
5320 
5321 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK     (0x2000U)
5322 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT    (13U)
5323 /*! POWERUP - Powers up the PLL.
5324  *  0b1..Power Up the PLL
5325  *  0b0..Power down the PLL
5326  */
5327 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
5328 
5329 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK  (0x4000U)
5330 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
5331 /*! ENABLE_CLK - Enable the clock output.
5332  *  0b0..Disable the clock
5333  *  0b1..Enable the clock
5334  */
5335 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
5336 
5337 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
5338 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
5339 /*! POST_DIV_SEL - POST_DIV_SEL
5340  *  0b00..Divide by 2
5341  *  0b01..Divide by 4
5342  *  0b10..Divide by 8
5343  *  0b11..Divide by 1
5344  */
5345 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
5346 
5347 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK      (0x20000U)
5348 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT     (17U)
5349 /*! BYPASS - Bypass the pll.
5350  *  0b1..Bypass Mode
5351  *  0b0..Function mode
5352  */
5353 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
5354 
5355 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
5356 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
5357 /*! ARM_PLL_STABLE - ARM_PLL_STABLE
5358  *  0b1..ARM PLL is stable
5359  *  0b0..ARM PLL is not stable
5360  */
5361 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
5362 
5363 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
5364 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
5365 /*! ARM_PLL_GATE - ARM_PLL_GATE
5366  *  0b1..Clock is gated
5367  *  0b0..Clock is not gated
5368  */
5369 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
5370 
5371 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
5372 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
5373 /*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode
5374  *  0b0..Software Mode (Default)
5375  *  0b1..GPC Mode
5376  */
5377 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
5378 /*! @} */
5379 
5380 /*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */
5381 /*! @{ */
5382 
5383 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
5384 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
5385 /*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate
5386  */
5387 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
5388 
5389 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
5390 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
5391 /*! PLL_REG_EN - Enable Internal PLL Regulator
5392  */
5393 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
5394 
5395 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
5396 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
5397 /*! HOLD_RING_OFF - PLL Start up initialization
5398  *  0b0..Normal operation
5399  *  0b1..Initialize PLL start up
5400  */
5401 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
5402 
5403 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
5404 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
5405 /*! ENABLE_CLK - Enable the clock output.
5406  *  0b0..Disable the clock
5407  *  0b1..Enable the clock
5408  */
5409 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
5410 
5411 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK     (0x10000U)
5412 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT    (16U)
5413 /*! BYPASS - BYPASS
5414  *  0b1..Bypass Mode
5415  *  0b0..Function mode
5416  */
5417 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
5418 
5419 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK    (0x200000U)
5420 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT   (21U)
5421 /*! POWERUP - Powers up the PLL.
5422  *  0b1..Power Up the PLL
5423  *  0b0..Power down the PLL
5424  */
5425 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
5426 
5427 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
5428 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
5429 /*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE
5430  *  0b0..Software Mode (Default)
5431  *  0b1..GPC Mode
5432  */
5433 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
5434 
5435 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
5436 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
5437 /*! SYS_PLL3_STABLE - SYS_PLL3_STABLE
5438  */
5439 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
5440 
5441 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
5442 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
5443 /*! SYS_PLL3_GATE - SYS_PLL3_GATE
5444  *  0b1..Clock is gated
5445  *  0b0..Clock is not gated
5446  */
5447 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
5448 
5449 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
5450 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
5451 /*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode
5452  *  0b0..Software Mode (Default)
5453  *  0b1..GPC Mode
5454  */
5455 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
5456 /*! @} */
5457 
5458 /*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */
5459 /*! @{ */
5460 
5461 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
5462 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
5463 /*! PFD0_UPDATE - PFD0_OVERRIDE
5464  */
5465 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
5466 
5467 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
5468 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
5469 /*! PFD1_UPDATE - PFD1_OVERRIDE
5470  */
5471 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
5472 
5473 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
5474 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
5475 /*! PFD2_UPDATE - PFD2_OVERRIDE
5476  */
5477 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
5478 
5479 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
5480 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
5481 /*! PFD3_UPDATE - PFD3_UPDATE
5482  */
5483 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
5484 
5485 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5486 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5487 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5488  *  0b0..Software Mode (Default)
5489  *  0b1..GPC Mode
5490  */
5491 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
5492 
5493 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5494 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5495 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5496  *  0b0..Software Mode (Default)
5497  *  0b1..GPC Mode
5498  */
5499 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
5500 
5501 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
5502 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
5503 /*! PDF2_CONTROL_MODE - pdf2_control_mode
5504  *  0b0..Software Mode (Default)
5505  *  0b1..GPC Mode
5506  */
5507 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)
5508 
5509 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5510 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5511 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5512  *  0b0..Software Mode (Default)
5513  *  0b1..GPC Mode
5514  */
5515 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
5516 /*! @} */
5517 
5518 /*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */
5519 /*! @{ */
5520 
5521 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK   (0x3FU)
5522 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT  (0U)
5523 /*! PFD0_FRAC - PFD0_FRAC
5524  */
5525 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
5526 
5527 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
5528 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
5529 /*! PFD0_STABLE - PFD0_STABLE
5530  */
5531 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
5532 
5533 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5534 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5535 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
5536  *  0b1..Fractional divider clock (reference ref_pfd0) is off (power savings
5537  *  0b0..ref_pfd0 fractional divider clock is enabled
5538  */
5539 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
5540 
5541 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK   (0x3F00U)
5542 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT  (8U)
5543 /*! PFD1_FRAC - PFD1_FRAC
5544  */
5545 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
5546 
5547 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
5548 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
5549 /*! PFD1_STABLE - PFD1_STABLE
5550  */
5551 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
5552 
5553 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5554 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5555 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
5556  *  0b1..Fractional divider clock (reference ref_pfd1) is off (power savings)
5557  *  0b0..ref_pfd1 fractional divider clock is enabled
5558  */
5559 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
5560 
5561 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5562 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT  (16U)
5563 /*! PFD2_FRAC - PFD2_FRAC
5564  */
5565 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
5566 
5567 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
5568 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
5569 /*! PFD2_STABLE - PFD2_STABLE
5570  */
5571 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
5572 
5573 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5574 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5575 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
5576  *  0b1..Fractional divider clock (reference ref_pfd2) is off (power savings)
5577  *  0b0..ref_pfd2 fractional divider clock is enabled
5578  */
5579 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
5580 
5581 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5582 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT  (24U)
5583 /*! PFD3_FRAC - PFD3_FRAC
5584  */
5585 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
5586 
5587 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
5588 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
5589 /*! PFD3_STABLE - PFD3_STABLE
5590  */
5591 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
5592 
5593 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5594 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5595 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
5596  *  0b1..Fractional divider clock (reference ref_pfd3) is off (power savings)
5597  *  0b0..ref_pfd3 fractional divider clock is enabled
5598  */
5599 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
5600 /*! @} */
5601 
5602 /*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */
5603 /*! @{ */
5604 
5605 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
5606 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
5607 /*! PLL_REG_EN - Enable Internal PLL Regulator
5608  */
5609 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
5610 
5611 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
5612 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
5613 /*! HOLD_RING_OFF - PLL Start up initialization
5614  *  0b0..Normal operation
5615  *  0b1..Initialize PLL start up
5616  */
5617 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
5618 
5619 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
5620 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
5621 /*! ENABLE_CLK - Enable the clock output.
5622  *  0b0..Disable the clock
5623  *  0b1..Enable the clock
5624  */
5625 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
5626 
5627 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK     (0x10000U)
5628 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT    (16U)
5629 /*! BYPASS - Bypass the pll.
5630  *  0b1..Bypass Mode
5631  *  0b0..Function mode
5632  */
5633 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
5634 
5635 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
5636 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
5637 /*! DITHER_ENABLE - DITHER_ENABLE
5638  *  0b0..Disable Dither
5639  *  0b1..Enable Dither
5640  */
5641 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
5642 
5643 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
5644 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
5645 /*! PFD_OFFSET_EN - PFD_OFFSET_EN
5646  */
5647 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
5648 
5649 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
5650 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
5651 /*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE
5652  */
5653 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
5654 
5655 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK    (0x800000U)
5656 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT   (23U)
5657 /*! POWERUP - Powers up the PLL.
5658  *  0b1..Power Up the PLL
5659  *  0b0..Power down the PLL
5660  */
5661 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
5662 
5663 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
5664 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
5665 /*! SYS_PLL2_STABLE - SYS_PLL2_STABLE
5666  */
5667 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
5668 
5669 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
5670 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
5671 /*! SYS_PLL2_GATE - SYS_PLL2_GATE
5672  *  0b1..Clock is gated
5673  *  0b0..Clock is not gated
5674  */
5675 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
5676 
5677 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
5678 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
5679 /*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode
5680  *  0b0..Software Mode (Default)
5681  *  0b1..GPC Mode
5682  */
5683 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
5684 /*! @} */
5685 
5686 /*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */
5687 /*! @{ */
5688 
5689 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
5690 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
5691 /*! PFD0_UPDATE - PFD0_UPDATE
5692  */
5693 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
5694 
5695 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
5696 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
5697 /*! PFD1_UPDATE - PFD1_UPDATE
5698  */
5699 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
5700 
5701 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
5702 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
5703 /*! PFD2_UPDATE - PFD2_UPDATE
5704  */
5705 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
5706 
5707 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
5708 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
5709 /*! PFD3_UPDATE - PFD3_UPDATE
5710  */
5711 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
5712 
5713 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5714 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5715 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5716  *  0b0..Software Mode (Default)
5717  *  0b1..GPC Mode
5718  */
5719 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
5720 
5721 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5722 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5723 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5724  *  0b0..Software Mode (Default)
5725  *  0b1..GPC Mode
5726  */
5727 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
5728 
5729 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
5730 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
5731 /*! PFD2_CONTROL_MODE - pfd2_control_mode
5732  *  0b0..Software Mode (Default)
5733  *  0b1..GPC Mode
5734  */
5735 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
5736 
5737 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5738 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5739 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5740  *  0b0..Software Mode (Default)
5741  *  0b1..GPC Mode
5742  */
5743 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
5744 /*! @} */
5745 
5746 /*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */
5747 /*! @{ */
5748 
5749 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK         (0x7FFFU)
5750 #define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT        (0U)
5751 /*! STEP - STEP
5752  */
5753 #define ANADIG_PLL_SYS_PLL2_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
5754 
5755 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK       (0x8000U)
5756 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT      (15U)
5757 /*! ENABLE - ENABLE
5758  *  0b1..Enable Spread Spectrum
5759  *  0b0..Disable Spread Spectrum
5760  */
5761 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
5762 
5763 #define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK         (0xFFFF0000U)
5764 #define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT        (16U)
5765 /*! STOP - STOP
5766  */
5767 #define ANADIG_PLL_SYS_PLL2_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
5768 /*! @} */
5769 
5770 /*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */
5771 /*! @{ */
5772 
5773 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK   (0x3FU)
5774 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT  (0U)
5775 /*! PFD0_FRAC - PFD0_FRAC
5776  */
5777 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
5778 
5779 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
5780 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
5781 /*! PFD0_STABLE - PFD0_STABLE
5782  */
5783 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
5784 
5785 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5786 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5787 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
5788  */
5789 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
5790 
5791 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK   (0x3F00U)
5792 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT  (8U)
5793 /*! PFD1_FRAC - PFD1_FRAC
5794  */
5795 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
5796 
5797 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
5798 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
5799 /*! PFD1_STABLE - PFD1_STABLE
5800  */
5801 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
5802 
5803 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5804 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5805 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
5806  */
5807 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
5808 
5809 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5810 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT  (16U)
5811 /*! PFD2_FRAC - PFD2_FRAC
5812  */
5813 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
5814 
5815 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
5816 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
5817 /*! PFD2_STABLE - PFD2_STABLE
5818  */
5819 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
5820 
5821 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5822 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5823 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
5824  */
5825 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
5826 
5827 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5828 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT  (24U)
5829 /*! PFD3_FRAC - PFD3_FRAC
5830  */
5831 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
5832 
5833 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
5834 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
5835 /*! PFD3_STABLE - PFD3_STABLE
5836  */
5837 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
5838 
5839 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5840 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5841 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
5842  */
5843 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
5844 /*! @} */
5845 
5846 /*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */
5847 /*! @{ */
5848 
5849 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK         (0x3FFFFFFFU)
5850 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT        (0U)
5851 /*! MFD - Denominator
5852  */
5853 #define ANADIG_PLL_SYS_PLL2_MFD_MFD(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
5854 /*! @} */
5855 
5856 /*! @name SYS_PLL1_SS - SYS_PLL1_SS_REGISTER */
5857 /*! @{ */
5858 
5859 #define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK         (0x7FFFU)
5860 #define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT        (0U)
5861 /*! STEP - STEP
5862  */
5863 #define ANADIG_PLL_SYS_PLL1_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)
5864 
5865 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK       (0x8000U)
5866 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT      (15U)
5867 /*! ENABLE - ENABLE
5868  *  0b1..Enable Spread Spectrum
5869  *  0b0..Disable Spread Spectrum
5870  */
5871 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)
5872 
5873 #define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK         (0xFFFF0000U)
5874 #define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT        (16U)
5875 /*! STOP - STOP
5876  */
5877 #define ANADIG_PLL_SYS_PLL1_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)
5878 /*! @} */
5879 
5880 /*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */
5881 /*! @{ */
5882 
5883 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
5884 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
5885 /*! ENABLE_CLK - ENABLE_CLK
5886  */
5887 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
5888 
5889 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
5890 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
5891 /*! SYS_PLL1_GATE - SYS_PLL1_GATE
5892  *  0b1..Gate the output
5893  *  0b0..No gate
5894  */
5895 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
5896 
5897 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
5898 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
5899 /*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2
5900  */
5901 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
5902 
5903 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
5904 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
5905 /*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5
5906  */
5907 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
5908 
5909 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
5910 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
5911 /*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE
5912  *  0b0..Software Mode (Default)
5913  *  0b1..GPC Mode
5914  */
5915 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
5916 
5917 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
5918 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
5919 /*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE
5920  *  0b0..Software Mode (Default)
5921  *  0b1..GPC Mode
5922  */
5923 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
5924 
5925 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
5926 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
5927 /*! SYS_PLL1_STABLE - SYS_PLL1_STABLE
5928  */
5929 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
5930 
5931 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
5932 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
5933 /*! SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY
5934  */
5935 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)
5936 
5937 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
5938 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
5939 /*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE
5940  *  0b0..Software Mode (Default)
5941  *  0b1..GPC Mode
5942  */
5943 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
5944 /*! @} */
5945 
5946 /*! @name SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER */
5947 /*! @{ */
5948 
5949 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
5950 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
5951 /*! DENOM - DENOM
5952  */
5953 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)
5954 /*! @} */
5955 
5956 /*! @name SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER */
5957 /*! @{ */
5958 
5959 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
5960 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT  (0U)
5961 /*! NUM - NUM
5962  */
5963 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)
5964 /*! @} */
5965 
5966 /*! @name SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER */
5967 /*! @{ */
5968 
5969 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
5970 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
5971 /*! DIV_SELECT - DIV_SELECT
5972  */
5973 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)
5974 /*! @} */
5975 
5976 /*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */
5977 /*! @{ */
5978 
5979 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
5980 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
5981 /*! ENABLE_CLK - ENABLE_CLK
5982  */
5983 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
5984 
5985 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
5986 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
5987 /*! PLL_AUDIO_GATE - PLL_AUDIO_GATE
5988  *  0b1..Gate the output
5989  *  0b0..No gate
5990  */
5991 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
5992 
5993 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
5994 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
5995 /*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE
5996  */
5997 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
5998 
5999 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
6000 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
6001 /*! PLL_AUDIO_AI_BUSY - pll_audio_ai_busy
6002  */
6003 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)
6004 
6005 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
6006 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
6007 /*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode
6008  *  0b0..Software Mode (Default)
6009  *  0b1..GPC Mode
6010  */
6011 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
6012 /*! @} */
6013 
6014 /*! @name PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER */
6015 /*! @{ */
6016 
6017 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK        (0x7FFFU)
6018 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT       (0U)
6019 /*! STEP - STEP
6020  */
6021 #define ANADIG_PLL_PLL_AUDIO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)
6022 
6023 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK      (0x8000U)
6024 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT     (15U)
6025 /*! ENABLE - ENABLE
6026  *  0b1..Enable Spread Spectrum
6027  *  0b0..Disable Spread Spectrum
6028  */
6029 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)
6030 
6031 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK        (0xFFFF0000U)
6032 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT       (16U)
6033 /*! STOP - STOP
6034  */
6035 #define ANADIG_PLL_PLL_AUDIO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)
6036 /*! @} */
6037 
6038 /*! @name PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER */
6039 /*! @{ */
6040 
6041 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6042 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
6043 /*! DENOM - DENOM
6044  */
6045 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)
6046 /*! @} */
6047 
6048 /*! @name PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER */
6049 /*! @{ */
6050 
6051 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
6052 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
6053 /*! NUM - NUM
6054  */
6055 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)
6056 /*! @} */
6057 
6058 /*! @name PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER */
6059 /*! @{ */
6060 
6061 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6062 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6063 /*! PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT
6064  */
6065 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)
6066 /*! @} */
6067 
6068 /*! @name PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER */
6069 /*! @{ */
6070 
6071 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
6072 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
6073 /*! ENABLE_CLK - ENABLE_CLK
6074  */
6075 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)
6076 
6077 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
6078 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
6079 /*! PLL_VIDEO_GATE - PLL_VIDEO_GATE
6080  *  0b1..Gate the output
6081  *  0b0..No gate
6082  */
6083 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)
6084 
6085 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
6086 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
6087 /*! PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr
6088  */
6089 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)
6090 
6091 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
6092 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
6093 /*! PLL_VIDEO_STABLE - PLL_VIDEO_STABLE
6094  */
6095 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)
6096 
6097 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
6098 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
6099 /*! PLL_VIDEO_AI_BUSY - pll_video_ai_busy
6100  */
6101 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)
6102 
6103 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
6104 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
6105 /*! PLL_VIDEO_CONTROL_MODE - pll_video_control_mode
6106  *  0b0..Software Mode (Default)
6107  *  0b1..GPC Mode
6108  */
6109 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)
6110 /*! @} */
6111 
6112 /*! @name PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER */
6113 /*! @{ */
6114 
6115 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK        (0x7FFFU)
6116 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT       (0U)
6117 /*! STEP - STEP
6118  */
6119 #define ANADIG_PLL_PLL_VIDEO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)
6120 
6121 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK      (0x8000U)
6122 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT     (15U)
6123 /*! ENABLE - ENABLE
6124  *  0b1..Enable Spread Spectrum
6125  *  0b0..Disable Spread Spectrum
6126  */
6127 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)
6128 
6129 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK        (0xFFFF0000U)
6130 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT       (16U)
6131 /*! STOP - STOP
6132  */
6133 #define ANADIG_PLL_PLL_VIDEO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)
6134 /*! @} */
6135 
6136 /*! @name PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER */
6137 /*! @{ */
6138 
6139 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6140 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
6141 /*! DENOM - DENOM
6142  */
6143 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)
6144 /*! @} */
6145 
6146 /*! @name PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER */
6147 /*! @{ */
6148 
6149 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
6150 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
6151 /*! NUM - NUM
6152  */
6153 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)
6154 /*! @} */
6155 
6156 /*! @name PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER */
6157 /*! @{ */
6158 
6159 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
6160 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
6161 /*! DIV_SELECT - DIV_SELECT
6162  */
6163 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)
6164 /*! @} */
6165 
6166 
6167 /*!
6168  * @}
6169  */ /* end of group ANADIG_PLL_Register_Masks */
6170 
6171 
6172 /* ANADIG_PLL - Peripheral instance base addresses */
6173 /** Peripheral ANADIG_PLL base address */
6174 #define ANADIG_PLL_BASE                          (0x40C84000u)
6175 /** Peripheral ANADIG_PLL base pointer */
6176 #define ANADIG_PLL                               ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
6177 /** Array initializer of ANADIG_PLL peripheral base addresses */
6178 #define ANADIG_PLL_BASE_ADDRS                    { ANADIG_PLL_BASE }
6179 /** Array initializer of ANADIG_PLL peripheral base pointers */
6180 #define ANADIG_PLL_BASE_PTRS                     { ANADIG_PLL }
6181 
6182 /*!
6183  * @}
6184  */ /* end of group ANADIG_PLL_Peripheral_Access_Layer */
6185 
6186 
6187 /* ----------------------------------------------------------------------------
6188    -- ANADIG_PMU Peripheral Access Layer
6189    ---------------------------------------------------------------------------- */
6190 
6191 /*!
6192  * @addtogroup ANADIG_PMU_Peripheral_Access_Layer ANADIG_PMU Peripheral Access Layer
6193  * @{
6194  */
6195 
6196 /** ANADIG_PMU - Register Layout Typedef */
6197 typedef struct {
6198        uint8_t RESERVED_0[1280];
6199   __IO uint32_t PMU_LDO_PLL;                       /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */
6200        uint8_t RESERVED_1[76];
6201   __IO uint32_t PMU_BIAS_CTRL;                     /**< PMU_BIAS_CTRL_REGISTER, offset: 0x550 */
6202        uint8_t RESERVED_2[12];
6203   __IO uint32_t PMU_BIAS_CTRL2;                    /**< PMU_BIAS_CTRL2_REGISTER, offset: 0x560 */
6204        uint8_t RESERVED_3[12];
6205   __IO uint32_t PMU_REF_CTRL;                      /**< PMU_REF_CTRL_REGISTER, offset: 0x570 */
6206        uint8_t RESERVED_4[12];
6207   __IO uint32_t PMU_POWER_DETECT_CTRL;             /**< PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580 */
6208        uint8_t RESERVED_5[124];
6209   __IO uint32_t LDO_PLL_ENABLE_SP;                 /**< LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600 */
6210        uint8_t RESERVED_6[12];
6211   __IO uint32_t LDO_LPSR_ANA_ENABLE_SP;            /**< LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610 */
6212        uint8_t RESERVED_7[12];
6213   __IO uint32_t LDO_LPSR_ANA_LP_MODE_SP;           /**< LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620 */
6214        uint8_t RESERVED_8[12];
6215   __IO uint32_t LDO_LPSR_ANA_TRACKING_EN_SP;       /**< LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630 */
6216        uint8_t RESERVED_9[12];
6217   __IO uint32_t LDO_LPSR_ANA_BYPASS_EN_SP;         /**< LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640 */
6218        uint8_t RESERVED_10[12];
6219   __IO uint32_t LDO_LPSR_ANA_STBY_EN_SP;           /**< LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650 */
6220        uint8_t RESERVED_11[12];
6221   __IO uint32_t LDO_LPSR_DIG_ENABLE_SP;            /**< LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660 */
6222        uint8_t RESERVED_12[12];
6223   __IO uint32_t LDO_LPSR_DIG_TRG_SP0;              /**< LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670 */
6224        uint8_t RESERVED_13[12];
6225   __IO uint32_t LDO_LPSR_DIG_TRG_SP1;              /**< LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680 */
6226        uint8_t RESERVED_14[12];
6227   __IO uint32_t LDO_LPSR_DIG_TRG_SP2;              /**< LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690 */
6228        uint8_t RESERVED_15[12];
6229   __IO uint32_t LDO_LPSR_DIG_TRG_SP3;              /**< LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0 */
6230        uint8_t RESERVED_16[12];
6231   __IO uint32_t LDO_LPSR_DIG_LP_MODE_SP;           /**< LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0 */
6232        uint8_t RESERVED_17[12];
6233   __IO uint32_t LDO_LPSR_DIG_TRACKING_EN_SP;       /**< LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0 */
6234        uint8_t RESERVED_18[12];
6235   __IO uint32_t LDO_LPSR_DIG_BYPASS_EN_SP;         /**< LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0 */
6236        uint8_t RESERVED_19[12];
6237   __IO uint32_t LDO_LPSR_DIG_STBY_EN_SP;           /**< LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0 */
6238        uint8_t RESERVED_20[12];
6239   __IO uint32_t BANDGAP_ENABLE_SP;                 /**< BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0 */
6240        uint8_t RESERVED_21[12];
6241   __IO uint32_t FBB_M7_ENABLE_SP;                  /**< FBB_M7_ENABLE_SP_REGISTER, offset: 0x700 */
6242        uint8_t RESERVED_22[12];
6243   __IO uint32_t RBB_SOC_ENABLE_SP;                 /**< RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710 */
6244        uint8_t RESERVED_23[12];
6245   __IO uint32_t RBB_LPSR_ENABLE_SP;                /**< RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720 */
6246        uint8_t RESERVED_24[12];
6247   __IO uint32_t BANDGAP_STBY_EN_SP;                /**< BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730 */
6248        uint8_t RESERVED_25[12];
6249   __IO uint32_t PLL_LDO_STBY_EN_SP;                /**< PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740 */
6250        uint8_t RESERVED_26[12];
6251   __IO uint32_t FBB_M7_STBY_EN_SP;                 /**< FBB_M7_STBY_EN_SP_REGISTER, offset: 0x750 */
6252        uint8_t RESERVED_27[12];
6253   __IO uint32_t RBB_SOC_STBY_EN_SP;                /**< RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760 */
6254        uint8_t RESERVED_28[12];
6255   __IO uint32_t RBB_LPSR_STBY_EN_SP;               /**< RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770 */
6256        uint8_t RESERVED_29[12];
6257   __IO uint32_t FBB_M7_CONFIGURE;                  /**< FBB_M7_CONFIGURE_REGISTER, offset: 0x780 */
6258        uint8_t RESERVED_30[12];
6259   __IO uint32_t RBB_LPSR_CONFIGURE;                /**< RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790 */
6260        uint8_t RESERVED_31[12];
6261   __IO uint32_t RBB_SOC_CONFIGURE;                 /**< RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0 */
6262        uint8_t RESERVED_32[12];
6263   __I  uint32_t REFTOP_OTP_TRIM_VALUE;             /**< REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0 */
6264        uint8_t RESERVED_33[28];
6265   __I  uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE;       /**< LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0 */
6266 } ANADIG_PMU_Type;
6267 
6268 /* ----------------------------------------------------------------------------
6269    -- ANADIG_PMU Register Masks
6270    ---------------------------------------------------------------------------- */
6271 
6272 /*!
6273  * @addtogroup ANADIG_PMU_Register_Masks ANADIG_PMU Register Masks
6274  * @{
6275  */
6276 
6277 /*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */
6278 /*! @{ */
6279 
6280 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U)
6281 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U)
6282 /*! LDO_PLL_ENABLE - LDO_PLL_ENABLE
6283  */
6284 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK)
6285 
6286 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
6287 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
6288 /*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE
6289  *  0b0..SW Control
6290  *  0b1..HW Control
6291  */
6292 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
6293 
6294 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U)
6295 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U)
6296 /*! LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle
6297  */
6298 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK)
6299 
6300 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U)
6301 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U)
6302 /*! LDO_PLL_AI_BUSY - ldo_pll_busy
6303  */
6304 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK)
6305 /*! @} */
6306 
6307 /*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */
6308 /*! @{ */
6309 
6310 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
6311 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
6312 /*! WB_CFG_1P8 - wb_cfg_1p8
6313  */
6314 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
6315 
6316 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
6317 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
6318 /*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8
6319  *  0b0..VDD_LV1
6320  *  0b1..VDD_LV2
6321  */
6322 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
6323 /*! @} */
6324 
6325 /*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */
6326 /*! @{ */
6327 
6328 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU)
6329 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U)
6330 /*! WB_TST_MD - TMOD_wb_tst_md_1p8
6331  */
6332 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK)
6333 
6334 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U)
6335 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U)
6336 /*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8
6337  *  0b001..No BB
6338  *  0b010..BB
6339  *  0b100..BB
6340  */
6341 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
6342 
6343 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
6344 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
6345 /*! WB_ADJ_1P8 - wb_adj_1p8
6346  *  0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF
6347  *  0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF
6348  *  0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF
6349  *  0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF
6350  *  0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF
6351  *  0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF
6352  *  0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF
6353  *  0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF
6354  *  0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF
6355  *  0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF
6356  *  0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF
6357  *  0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF
6358  *  0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF
6359  *  0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF
6360  *  0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF
6361  *  0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
6362  */
6363 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
6364 
6365 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK (0x200000U)
6366 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT (21U)
6367 /*! FBB_M7_CONTROL_MODE - FBB_M7_CONTROL_MODE
6368  *  0b0..SW Control
6369  *  0b1..HW Control
6370  */
6371 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
6372 
6373 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U)
6374 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U)
6375 /*! RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE
6376  *  0b0..SW Control
6377  *  0b1..HW Control
6378  */
6379 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK)
6380 
6381 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U)
6382 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U)
6383 /*! RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE
6384  *  0b0..SW Control
6385  *  0b1..HW Control
6386  */
6387 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK)
6388 
6389 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK     (0x1000000U)
6390 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT    (24U)
6391 /*! WB_EN - wb_en
6392  */
6393 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
6394 
6395 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U)
6396 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U)
6397 /*! WB_TST_DIG_OUT - Digital output
6398  */
6399 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK)
6400 
6401 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK     (0x4000000U)
6402 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT    (26U)
6403 /*! WB_OK - Digital Output pin.
6404  */
6405 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
6406 /*! @} */
6407 
6408 /*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */
6409 /*! @{ */
6410 
6411 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U)
6412 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U)
6413 /*! REF_AI_TOGGLE - ref_ai_toggle
6414  */
6415 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK)
6416 
6417 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U)
6418 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U)
6419 /*! REF_AI_BUSY - ref_ai_busy
6420  */
6421 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK)
6422 
6423 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK  (0x4U)
6424 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U)
6425 /*! REF_ENABLE - REF_ENABLE
6426  */
6427 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK)
6428 
6429 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
6430 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
6431 /*! REF_CONTROL_MODE - REF_CONTROL_MODE
6432  *  0b0..SW Control
6433  *  0b1..HW Control
6434  */
6435 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
6436 
6437 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
6438 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
6439 /*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer
6440  */
6441 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
6442 /*! @} */
6443 
6444 /*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */
6445 /*! @{ */
6446 
6447 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U)
6448 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U)
6449 /*! CKGB_LPSR1P0 - ckgb_lpsr1p0
6450  */
6451 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK)
6452 /*! @} */
6453 
6454 /*! @name LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER */
6455 /*! @{ */
6456 
6457 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6458 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6459 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6460  *  0b0..ON
6461  *  0b1..OFF
6462  */
6463 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6464 
6465 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6466 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6467 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6468  *  0b0..ON
6469  *  0b1..OFF
6470  */
6471 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6472 
6473 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6474 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6475 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6476  *  0b0..ON
6477  *  0b1..OFF
6478  */
6479 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6480 
6481 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6482 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6483 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6484  *  0b0..ON
6485  *  0b1..OFF
6486  */
6487 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6488 
6489 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6490 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6491 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6492  *  0b0..ON
6493  *  0b1..OFF
6494  */
6495 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6496 
6497 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6498 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6499 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6500  *  0b0..ON
6501  *  0b1..OFF
6502  */
6503 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6504 
6505 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6506 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6507 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6508  *  0b0..ON
6509  *  0b1..OFF
6510  */
6511 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6512 
6513 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6514 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6515 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6516  *  0b0..ON
6517  *  0b1..OFF
6518  */
6519 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6520 
6521 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6522 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6523 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6524  *  0b0..ON
6525  *  0b1..OFF
6526  */
6527 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6528 
6529 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6530 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6531 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6532  *  0b0..ON
6533  *  0b1..OFF
6534  */
6535 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6536 
6537 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6538 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6539 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6540  *  0b0..ON
6541  *  0b1..OFF
6542  */
6543 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6544 
6545 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6546 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6547 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6548  *  0b0..ON
6549  *  0b1..OFF
6550  */
6551 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6552 
6553 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6554 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6555 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6556  *  0b0..ON
6557  *  0b1..OFF
6558  */
6559 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6560 
6561 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6562 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6563 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6564  *  0b0..ON
6565  *  0b1..OFF
6566  */
6567 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6568 
6569 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6570 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6571 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6572  *  0b0..ON
6573  *  0b1..OFF
6574  */
6575 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6576 
6577 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6578 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6579 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6580  *  0b0..ON
6581  *  0b1..OFF
6582  */
6583 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6584 /*! @} */
6585 
6586 /*! @name LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER */
6587 /*! @{ */
6588 
6589 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6590 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6591 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6592  *  0b0..ON
6593  *  0b1..OFF
6594  */
6595 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6596 
6597 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6598 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6599 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6600  *  0b0..ON
6601  *  0b1..OFF
6602  */
6603 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6604 
6605 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6606 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6607 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6608  *  0b0..ON
6609  *  0b1..OFF
6610  */
6611 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6612 
6613 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6614 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6615 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6616  *  0b0..ON
6617  *  0b1..OFF
6618  */
6619 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6620 
6621 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6622 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6623 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6624  *  0b0..ON
6625  *  0b1..OFF
6626  */
6627 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6628 
6629 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6630 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6631 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6632  *  0b0..ON
6633  *  0b1..OFF
6634  */
6635 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6636 
6637 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6638 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6639 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6640  *  0b0..ON
6641  *  0b1..OFF
6642  */
6643 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6644 
6645 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6646 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6647 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6648  *  0b0..ON
6649  *  0b1..OFF
6650  */
6651 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6652 
6653 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6654 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6655 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6656  *  0b0..ON
6657  *  0b1..OFF
6658  */
6659 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6660 
6661 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6662 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6663 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6664  *  0b0..ON
6665  *  0b1..OFF
6666  */
6667 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6668 
6669 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6670 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6671 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6672  *  0b0..ON
6673  *  0b1..OFF
6674  */
6675 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6676 
6677 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6678 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6679 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6680  *  0b0..ON
6681  *  0b1..OFF
6682  */
6683 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6684 
6685 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6686 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6687 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6688  *  0b0..ON
6689  *  0b1..OFF
6690  */
6691 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6692 
6693 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6694 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6695 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6696  *  0b0..ON
6697  *  0b1..OFF
6698  */
6699 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6700 
6701 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6702 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6703 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6704  *  0b0..ON
6705  *  0b1..OFF
6706  */
6707 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6708 
6709 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6710 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6711 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6712  *  0b0..ON
6713  *  0b1..OFF
6714  */
6715 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6716 /*! @} */
6717 
6718 /*! @name LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER */
6719 /*! @{ */
6720 
6721 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
6722 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
6723 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
6724  *  0b0..LP
6725  *  0b1..HP
6726  */
6727 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
6728 
6729 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
6730 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
6731 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
6732  *  0b0..LP
6733  *  0b1..HP
6734  */
6735 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
6736 
6737 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U)
6738 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U)
6739 /*! LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2
6740  *  0b0..LP
6741  *  0b1..HP
6742  */
6743 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK)
6744 
6745 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U)
6746 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U)
6747 /*! LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3
6748  *  0b0..LP
6749  *  0b1..HP
6750  */
6751 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK)
6752 
6753 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U)
6754 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U)
6755 /*! LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4
6756  *  0b0..LP
6757  *  0b1..HP
6758  */
6759 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK)
6760 
6761 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U)
6762 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U)
6763 /*! LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5
6764  *  0b0..LP
6765  *  0b1..HP
6766  */
6767 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK)
6768 
6769 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U)
6770 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U)
6771 /*! LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6
6772  *  0b0..LP
6773  *  0b1..HP
6774  */
6775 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK)
6776 
6777 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U)
6778 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U)
6779 /*! LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7
6780  *  0b0..LP
6781  *  0b1..HP
6782  */
6783 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK)
6784 
6785 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U)
6786 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U)
6787 /*! LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8
6788  *  0b0..LP
6789  *  0b1..HP
6790  */
6791 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK)
6792 
6793 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U)
6794 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U)
6795 /*! LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9
6796  *  0b0..LP
6797  *  0b1..HP
6798  */
6799 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK)
6800 
6801 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U)
6802 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U)
6803 /*! LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10
6804  *  0b0..LP
6805  *  0b1..HP
6806  */
6807 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK)
6808 
6809 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U)
6810 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U)
6811 /*! LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11
6812  *  0b0..LP
6813  *  0b1..HP
6814  */
6815 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK)
6816 
6817 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U)
6818 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U)
6819 /*! LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12
6820  *  0b0..LP
6821  *  0b1..HP
6822  */
6823 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK)
6824 
6825 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U)
6826 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U)
6827 /*! LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13
6828  *  0b0..LP
6829  *  0b1..HP
6830  */
6831 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK)
6832 
6833 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U)
6834 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U)
6835 /*! LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14
6836  *  0b0..LP
6837  *  0b1..HP
6838  */
6839 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK)
6840 
6841 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U)
6842 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U)
6843 /*! LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15
6844  *  0b0..LP
6845  *  0b1..HP
6846  */
6847 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK)
6848 /*! @} */
6849 
6850 /*! @name LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER */
6851 /*! @{ */
6852 
6853 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
6854 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
6855 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
6856  *  0b0..Disabled
6857  *  0b1..Enabled
6858  */
6859 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
6860 
6861 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
6862 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
6863 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
6864  *  0b0..Disabled
6865  *  0b1..Enabled
6866  */
6867 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
6868 
6869 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
6870 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
6871 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
6872  *  0b0..Disabled
6873  *  0b1..Enabled
6874  */
6875 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
6876 
6877 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
6878 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
6879 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
6880  *  0b0..Disabled
6881  *  0b1..Enabled
6882  */
6883 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
6884 
6885 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
6886 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
6887 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
6888  *  0b0..Disabled
6889  *  0b1..Enabled
6890  */
6891 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
6892 
6893 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
6894 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
6895 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
6896  *  0b0..Disabled
6897  *  0b1..Enabled
6898  */
6899 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
6900 
6901 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
6902 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
6903 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
6904  *  0b0..Disabled
6905  *  0b1..Enabled
6906  */
6907 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
6908 
6909 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
6910 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
6911 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
6912  *  0b0..Disabled
6913  *  0b1..Enabled
6914  */
6915 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
6916 
6917 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
6918 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
6919 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
6920  *  0b0..Disabled
6921  *  0b1..Enabled
6922  */
6923 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
6924 
6925 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
6926 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
6927 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
6928  *  0b0..Disabled
6929  *  0b1..Enabled
6930  */
6931 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
6932 
6933 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
6934 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
6935 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
6936  *  0b0..Disabled
6937  *  0b1..Enabled
6938  */
6939 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
6940 
6941 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
6942 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
6943 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
6944  *  0b0..Disabled
6945  *  0b1..Enabled
6946  */
6947 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
6948 
6949 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
6950 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
6951 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
6952  *  0b0..Disabled
6953  *  0b1..Enabled
6954  */
6955 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
6956 
6957 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
6958 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
6959 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
6960  *  0b0..Disabled
6961  *  0b1..Enabled
6962  */
6963 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
6964 
6965 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
6966 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
6967 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
6968  *  0b0..Disabled
6969  *  0b1..Enabled
6970  */
6971 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
6972 
6973 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
6974 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
6975 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
6976  *  0b0..Disabled
6977  *  0b1..Enabled
6978  */
6979 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
6980 /*! @} */
6981 
6982 /*! @name LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER */
6983 /*! @{ */
6984 
6985 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
6986 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
6987 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
6988  *  0b0..Disabled
6989  *  0b1..Enabled
6990  */
6991 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
6992 
6993 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
6994 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
6995 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
6996  *  0b0..Disabled
6997  *  0b1..Enabled
6998  */
6999 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
7000 
7001 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
7002 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
7003 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
7004  *  0b0..Disabled
7005  *  0b1..Enabled
7006  */
7007 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
7008 
7009 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
7010 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
7011 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
7012  *  0b0..Disabled
7013  *  0b1..Enabled
7014  */
7015 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
7016 
7017 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
7018 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
7019 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
7020  *  0b0..Disabled
7021  *  0b1..Enabled
7022  */
7023 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7024 
7025 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7026 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7027 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
7028  *  0b0..Disabled
7029  *  0b1..Enabled
7030  */
7031 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7032 
7033 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7034 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7035 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
7036  *  0b0..Disabled
7037  *  0b1..Enabled
7038  */
7039 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7040 
7041 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7042 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7043 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
7044  *  0b0..Disabled
7045  *  0b1..Enabled
7046  */
7047 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7048 
7049 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7050 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7051 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT
7052  *  0b0..Disabled
7053  *  0b1..Enabled
7054  */
7055 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7056 
7057 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7058 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7059 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
7060  *  0b0..Disabled
7061  *  0b1..Enabled
7062  */
7063 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7064 
7065 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7066 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7067 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
7068  *  0b0..Disabled
7069  *  0b1..Enabled
7070  */
7071 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7072 
7073 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7074 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7075 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
7076  *  0b0..Disabled
7077  *  0b1..Enabled
7078  */
7079 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7080 
7081 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7082 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7083 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
7084  *  0b0..Disabled
7085  *  0b1..Enabled
7086  */
7087 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7088 
7089 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7090 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7091 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
7092  *  0b0..Disabled
7093  *  0b1..Enabled
7094  */
7095 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7096 
7097 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7098 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7099 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
7100  *  0b0..Disabled
7101  *  0b1..Enabled
7102  */
7103 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7104 
7105 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7106 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7107 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
7108  *  0b0..Disabled
7109  *  0b1..Enabled
7110  */
7111 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7112 /*! @} */
7113 
7114 /*! @name LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER */
7115 /*! @{ */
7116 
7117 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7118 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7119 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
7120  *  0b0..Disabled
7121  *  0b1..Enabled
7122  */
7123 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7124 
7125 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7126 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7127 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
7128  *  0b0..Disabled
7129  *  0b1..Enabled
7130  */
7131 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7132 
7133 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7134 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7135 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
7136  *  0b0..Disabled
7137  *  0b1..Enabled
7138  */
7139 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7140 
7141 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7142 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7143 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7144  *  0b0..Disabled
7145  *  0b1..Enabled
7146  */
7147 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7148 
7149 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7150 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7151 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7152  *  0b0..Disabled
7153  *  0b1..Enabled
7154  */
7155 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7156 
7157 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7158 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7159 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7160  *  0b0..Disabled
7161  *  0b1..Enabled
7162  */
7163 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7164 
7165 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7166 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7167 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7168  *  0b0..Disabled
7169  *  0b1..Enabled
7170  */
7171 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7172 
7173 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7174 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7175 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7176  *  0b0..Disabled
7177  *  0b1..Enabled
7178  */
7179 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7180 
7181 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7182 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7183 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7184  *  0b0..Disabled
7185  *  0b1..Enabled
7186  */
7187 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7188 
7189 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7190 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7191 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7192  *  0b0..Disabled
7193  *  0b1..Enabled
7194  */
7195 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7196 
7197 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7198 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7199 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7200  *  0b0..Disabled
7201  *  0b1..Enabled
7202  */
7203 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7204 
7205 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7206 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7207 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7208  *  0b0..Disabled
7209  *  0b1..Enabled
7210  */
7211 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7212 
7213 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7214 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7215 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7216  *  0b0..Disabled
7217  *  0b1..Enabled
7218  */
7219 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7220 
7221 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7222 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7223 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7224  *  0b0..Disabled
7225  *  0b1..Enabled
7226  */
7227 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7228 
7229 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7230 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7231 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
7232  *  0b0..Disabled
7233  *  0b1..Enabled
7234  */
7235 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7236 
7237 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7238 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7239 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
7240  *  0b0..Disabled
7241  *  0b1..Enabled
7242  */
7243 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7244 /*! @} */
7245 
7246 /*! @name LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER */
7247 /*! @{ */
7248 
7249 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7250 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7251 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
7252  *  0b0..ON
7253  *  0b1..OFF
7254  */
7255 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7256 
7257 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7258 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7259 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
7260  *  0b0..ON
7261  *  0b1..OFF
7262  */
7263 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
7264 
7265 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
7266 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
7267 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
7268  *  0b0..ON
7269  *  0b1..OFF
7270  */
7271 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
7272 
7273 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
7274 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
7275 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
7276  *  0b0..ON
7277  *  0b1..OFF
7278  */
7279 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
7280 
7281 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
7282 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
7283 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
7284  *  0b0..ON
7285  *  0b1..OFF
7286  */
7287 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
7288 
7289 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
7290 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
7291 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
7292  *  0b0..ON
7293  *  0b1..OFF
7294  */
7295 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
7296 
7297 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
7298 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
7299 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
7300  *  0b0..ON
7301  *  0b1..OFF
7302  */
7303 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
7304 
7305 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
7306 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
7307 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
7308  *  0b0..ON
7309  *  0b1..OFF
7310  */
7311 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
7312 
7313 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
7314 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
7315 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
7316  *  0b0..ON
7317  *  0b1..OFF
7318  */
7319 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
7320 
7321 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
7322 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
7323 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
7324  *  0b0..ON
7325  *  0b1..OFF
7326  */
7327 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
7328 
7329 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
7330 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
7331 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
7332  *  0b0..ON
7333  *  0b1..OFF
7334  */
7335 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
7336 
7337 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
7338 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
7339 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
7340  *  0b0..ON
7341  *  0b1..OFF
7342  */
7343 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
7344 
7345 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
7346 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
7347 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
7348  *  0b0..ON
7349  *  0b1..OFF
7350  */
7351 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
7352 
7353 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
7354 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
7355 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
7356  *  0b0..ON
7357  *  0b1..OFF
7358  */
7359 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
7360 
7361 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
7362 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
7363 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
7364  *  0b0..ON
7365  *  0b1..OFF
7366  */
7367 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
7368 
7369 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
7370 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
7371 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
7372  *  0b0..ON
7373  *  0b1..OFF
7374  */
7375 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
7376 /*! @} */
7377 
7378 /*! @name LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER */
7379 /*! @{ */
7380 
7381 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU)
7382 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U)
7383 /*! VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0
7384  */
7385 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK)
7386 
7387 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U)
7388 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U)
7389 /*! VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1
7390  */
7391 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK)
7392 
7393 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U)
7394 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U)
7395 /*! VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2
7396  */
7397 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK)
7398 
7399 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U)
7400 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U)
7401 /*! VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3
7402  */
7403 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK)
7404 /*! @} */
7405 
7406 /*! @name LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER */
7407 /*! @{ */
7408 
7409 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU)
7410 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U)
7411 /*! VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4
7412  */
7413 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK)
7414 
7415 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U)
7416 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U)
7417 /*! VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5
7418  */
7419 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK)
7420 
7421 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U)
7422 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U)
7423 /*! VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6
7424  */
7425 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK)
7426 
7427 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U)
7428 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U)
7429 /*! VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7
7430  */
7431 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK)
7432 /*! @} */
7433 
7434 /*! @name LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER */
7435 /*! @{ */
7436 
7437 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU)
7438 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U)
7439 /*! VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8
7440  */
7441 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK)
7442 
7443 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U)
7444 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U)
7445 /*! VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9
7446  */
7447 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK)
7448 
7449 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U)
7450 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U)
7451 /*! VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10
7452  */
7453 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK)
7454 
7455 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U)
7456 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U)
7457 /*! VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11
7458  */
7459 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK)
7460 /*! @} */
7461 
7462 /*! @name LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER */
7463 /*! @{ */
7464 
7465 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU)
7466 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U)
7467 /*! VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12
7468  */
7469 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK)
7470 
7471 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U)
7472 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U)
7473 /*! VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13
7474  */
7475 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK)
7476 
7477 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U)
7478 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U)
7479 /*! VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14
7480  */
7481 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK)
7482 
7483 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U)
7484 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U)
7485 /*! VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15
7486  */
7487 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK)
7488 /*! @} */
7489 
7490 /*! @name LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER */
7491 /*! @{ */
7492 
7493 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
7494 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
7495 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
7496  *  0b0..LP
7497  *  0b1..HP
7498  */
7499 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
7500 
7501 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
7502 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
7503 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
7504  *  0b0..LP
7505  *  0b1..HP
7506  */
7507 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
7508 
7509 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U)
7510 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U)
7511 /*! LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2
7512  *  0b0..LP
7513  *  0b1..HP
7514  */
7515 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK)
7516 
7517 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U)
7518 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U)
7519 /*! LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3
7520  *  0b0..LP
7521  *  0b1..HP
7522  */
7523 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK)
7524 
7525 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U)
7526 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U)
7527 /*! LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4
7528  *  0b0..LP
7529  *  0b1..HP
7530  */
7531 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK)
7532 
7533 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U)
7534 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U)
7535 /*! LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5
7536  *  0b0..LP
7537  *  0b1..HP
7538  */
7539 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK)
7540 
7541 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U)
7542 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U)
7543 /*! LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6
7544  *  0b0..LP
7545  *  0b1..HP
7546  */
7547 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK)
7548 
7549 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U)
7550 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U)
7551 /*! LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7
7552  *  0b0..LP
7553  *  0b1..HP
7554  */
7555 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK)
7556 
7557 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U)
7558 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U)
7559 /*! LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8
7560  *  0b0..LP
7561  *  0b1..HP
7562  */
7563 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK)
7564 
7565 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U)
7566 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U)
7567 /*! LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9
7568  *  0b0..LP
7569  *  0b1..HP
7570  */
7571 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK)
7572 
7573 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U)
7574 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U)
7575 /*! LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10
7576  *  0b0..LP
7577  *  0b1..HP
7578  */
7579 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK)
7580 
7581 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U)
7582 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U)
7583 /*! LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11
7584  *  0b0..LP
7585  *  0b1..HP
7586  */
7587 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK)
7588 
7589 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U)
7590 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U)
7591 /*! LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12
7592  *  0b0..LP
7593  *  0b1..HP
7594  */
7595 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK)
7596 
7597 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U)
7598 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U)
7599 /*! LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13
7600  *  0b0..LP
7601  *  0b1..HP
7602  */
7603 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK)
7604 
7605 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U)
7606 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U)
7607 /*! LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14
7608  *  0b0..LP
7609  *  0b1..HP
7610  */
7611 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK)
7612 
7613 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U)
7614 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U)
7615 /*! LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15
7616  *  0b0..LP
7617  *  0b1..HP
7618  */
7619 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK)
7620 /*! @} */
7621 
7622 /*! @name LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER */
7623 /*! @{ */
7624 
7625 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
7626 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
7627 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
7628  *  0b0..Disabled
7629  *  0b1..Enabled
7630  */
7631 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
7632 
7633 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
7634 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
7635 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
7636  *  0b0..Disabled
7637  *  0b1..Enabled
7638  */
7639 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
7640 
7641 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
7642 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
7643 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
7644  *  0b0..Disabled
7645  *  0b1..Enabled
7646  */
7647 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
7648 
7649 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
7650 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
7651 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
7652  *  0b0..Disabled
7653  *  0b1..Enabled
7654  */
7655 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
7656 
7657 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
7658 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
7659 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
7660  *  0b0..Disabled
7661  *  0b1..Enabled
7662  */
7663 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
7664 
7665 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
7666 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
7667 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
7668  *  0b0..Disabled
7669  *  0b1..Enabled
7670  */
7671 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
7672 
7673 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
7674 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
7675 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
7676  *  0b0..Disabled
7677  *  0b1..Enabled
7678  */
7679 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
7680 
7681 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
7682 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
7683 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
7684  *  0b0..Disabled
7685  *  0b1..Enabled
7686  */
7687 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
7688 
7689 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
7690 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
7691 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
7692  *  0b0..Disabled
7693  *  0b1..Enabled
7694  */
7695 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
7696 
7697 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
7698 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
7699 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
7700  *  0b0..Disabled
7701  *  0b1..Enabled
7702  */
7703 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
7704 
7705 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
7706 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
7707 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
7708  *  0b0..Disabled
7709  *  0b1..Enabled
7710  */
7711 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
7712 
7713 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
7714 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
7715 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
7716  *  0b0..Disabled
7717  *  0b1..Enabled
7718  */
7719 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
7720 
7721 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
7722 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
7723 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
7724  *  0b0..Disabled
7725  *  0b1..Enabled
7726  */
7727 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
7728 
7729 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
7730 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
7731 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
7732  *  0b0..Disabled
7733  *  0b1..Enabled
7734  */
7735 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
7736 
7737 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
7738 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
7739 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
7740  *  0b0..Disabled
7741  *  0b1..Enabled
7742  */
7743 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
7744 
7745 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
7746 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
7747 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
7748  *  0b0..Disabled
7749  *  0b1..Enabled
7750  */
7751 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
7752 /*! @} */
7753 
7754 /*! @name LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER */
7755 /*! @{ */
7756 
7757 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
7758 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
7759 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
7760  *  0b0..Disabled
7761  *  0b1..Enabled
7762  */
7763 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
7764 
7765 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
7766 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
7767 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
7768  *  0b0..Disabled
7769  *  0b1..Enabled
7770  */
7771 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
7772 
7773 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
7774 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
7775 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
7776  *  0b0..Disabled
7777  *  0b1..Enabled
7778  */
7779 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
7780 
7781 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
7782 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
7783 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
7784  *  0b0..Disabled
7785  *  0b1..Enabled
7786  */
7787 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
7788 
7789 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
7790 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
7791 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
7792  *  0b0..Disabled
7793  *  0b1..Enabled
7794  */
7795 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7796 
7797 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7798 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7799 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
7800  *  0b0..Disabled
7801  *  0b1..Enabled
7802  */
7803 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7804 
7805 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7806 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7807 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
7808  *  0b0..Disabled
7809  *  0b1..Enabled
7810  */
7811 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7812 
7813 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7814 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7815 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
7816  *  0b0..Disabled
7817  *  0b1..Enabled
7818  */
7819 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7820 
7821 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7822 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7823 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8
7824  *  0b0..Disabled
7825  *  0b1..Enabled
7826  */
7827 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7828 
7829 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7830 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7831 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
7832  *  0b0..Disabled
7833  *  0b1..Enabled
7834  */
7835 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7836 
7837 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7838 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7839 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
7840  *  0b0..Disabled
7841  *  0b1..Enabled
7842  */
7843 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7844 
7845 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7846 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7847 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
7848  *  0b0..Disabled
7849  *  0b1..Enabled
7850  */
7851 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7852 
7853 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7854 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7855 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
7856  *  0b0..Disabled
7857  *  0b1..Enabled
7858  */
7859 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7860 
7861 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7862 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7863 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
7864  *  0b0..Disabled
7865  *  0b1..Enabled
7866  */
7867 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7868 
7869 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7870 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7871 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
7872  *  0b0..Disabled
7873  *  0b1..Enabled
7874  */
7875 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7876 
7877 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7878 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7879 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
7880  *  0b0..Disabled
7881  *  0b1..Enabled
7882  */
7883 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7884 /*! @} */
7885 
7886 /*! @name LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER */
7887 /*! @{ */
7888 
7889 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7890 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7891 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
7892  *  0b0..Disabled
7893  *  0b1..Enabled
7894  */
7895 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7896 
7897 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7898 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7899 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
7900  *  0b0..Disabled
7901  *  0b1..Enabled
7902  */
7903 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7904 
7905 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7906 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7907 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
7908  *  0b0..Disabled
7909  *  0b1..Enabled
7910  */
7911 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7912 
7913 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7914 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7915 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7916  *  0b0..Disabled
7917  *  0b1..Enabled
7918  */
7919 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7920 
7921 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7922 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7923 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7924  *  0b0..Disabled
7925  *  0b1..Enabled
7926  */
7927 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7928 
7929 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7930 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7931 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7932  *  0b0..Disabled
7933  *  0b1..Enabled
7934  */
7935 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7936 
7937 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7938 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7939 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7940  *  0b0..Disabled
7941  *  0b1..Enabled
7942  */
7943 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7944 
7945 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7946 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7947 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7948  *  0b0..Disabled
7949  *  0b1..Enabled
7950  */
7951 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7952 
7953 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7954 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7955 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7956  *  0b0..Disabled
7957  *  0b1..Enabled
7958  */
7959 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7960 
7961 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7962 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7963 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7964  *  0b0..Disabled
7965  *  0b1..Enabled
7966  */
7967 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7968 
7969 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7970 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7971 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7972  *  0b0..Disabled
7973  *  0b1..Enabled
7974  */
7975 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7976 
7977 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7978 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7979 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7980  *  0b0..Disabled
7981  *  0b1..Enabled
7982  */
7983 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7984 
7985 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7986 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7987 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7988  *  0b0..Disabled
7989  *  0b1..Enabled
7990  */
7991 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7992 
7993 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7994 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7995 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7996  *  0b0..Disabled
7997  *  0b1..Enabled
7998  */
7999 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8000 
8001 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8002 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8003 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
8004  *  0b0..Disabled
8005  *  0b1..Enabled
8006  */
8007 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8008 
8009 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8010 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8011 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
8012  *  0b0..Disabled
8013  *  0b1..Enabled
8014  */
8015 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8016 /*! @} */
8017 
8018 /*! @name BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER */
8019 /*! @{ */
8020 
8021 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8022 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8023 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8024  *  0b0..ON
8025  *  0b1..OFF
8026  */
8027 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8028 
8029 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8030 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8031 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8032  *  0b0..ON
8033  *  0b1..OFF
8034  */
8035 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8036 
8037 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8038 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8039 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8040  *  0b0..ON
8041  *  0b1..OFF
8042  */
8043 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8044 
8045 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8046 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8047 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8048  *  0b0..ON
8049  *  0b1..OFF
8050  */
8051 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8052 
8053 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8054 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8055 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8056  *  0b0..ON
8057  *  0b1..OFF
8058  */
8059 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8060 
8061 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8062 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8063 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8064  *  0b0..ON
8065  *  0b1..OFF
8066  */
8067 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8068 
8069 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8070 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8071 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5
8072  *  0b0..ON
8073  *  0b1..OFF
8074  */
8075 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8076 
8077 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8078 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8079 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8080  *  0b0..ON
8081  *  0b1..OFF
8082  */
8083 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8084 
8085 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8086 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8087 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8088  *  0b0..ON
8089  *  0b1..OFF
8090  */
8091 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8092 
8093 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8094 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8095 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8096  *  0b0..ON
8097  *  0b1..OFF
8098  */
8099 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8100 
8101 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8102 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8103 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8104  *  0b0..ON
8105  *  0b1..OFF
8106  */
8107 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8108 
8109 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8110 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8111 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8112  *  0b0..ON
8113  *  0b1..OFF
8114  */
8115 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8116 
8117 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8118 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8119 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8120  *  0b0..ON
8121  *  0b1..OFF
8122  */
8123 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8124 
8125 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8126 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8127 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8128  *  0b0..ON
8129  *  0b1..OFF
8130  */
8131 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8132 
8133 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8134 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8135 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8136  *  0b0..ON
8137  *  0b1..OFF
8138  */
8139 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8140 
8141 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8142 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8143 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8144  *  0b0..ON
8145  *  0b1..OFF
8146  */
8147 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8148 /*! @} */
8149 
8150 /*! @name FBB_M7_ENABLE_SP - FBB_M7_ENABLE_SP_REGISTER */
8151 /*! @{ */
8152 
8153 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8154 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8155 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8156  *  0b0..ON
8157  *  0b1..OFF
8158  */
8159 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8160 
8161 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8162 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8163 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8164  *  0b0..ON
8165  *  0b1..OFF
8166  */
8167 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8168 
8169 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8170 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8171 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8172  *  0b0..ON
8173  *  0b1..OFF
8174  */
8175 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8176 
8177 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8178 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8179 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8180  *  0b0..ON
8181  *  0b1..OFF
8182  */
8183 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8184 
8185 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8186 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8187 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8188  *  0b0..ON
8189  *  0b1..OFF
8190  */
8191 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8192 
8193 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8194 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8195 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8196  *  0b0..ON
8197  *  0b1..OFF
8198  */
8199 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8200 
8201 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8202 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8203 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8204  *  0b0..ON
8205  *  0b1..OFF
8206  */
8207 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8208 
8209 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8210 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8211 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8212  *  0b0..ON
8213  *  0b1..OFF
8214  */
8215 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8216 
8217 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8218 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8219 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8220  *  0b0..ON
8221  *  0b1..OFF
8222  */
8223 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8224 
8225 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8226 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8227 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8228  *  0b0..ON
8229  *  0b1..OFF
8230  */
8231 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8232 
8233 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8234 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8235 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8236  *  0b0..ON
8237  *  0b1..OFF
8238  */
8239 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8240 
8241 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8242 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8243 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8244  *  0b0..ON
8245  *  0b1..OFF
8246  */
8247 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8248 
8249 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8250 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8251 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8252  *  0b0..ON
8253  *  0b1..OFF
8254  */
8255 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8256 
8257 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8258 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8259 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8260  *  0b0..ON
8261  *  0b1..OFF
8262  */
8263 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8264 
8265 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8266 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8267 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8268  *  0b0..ON
8269  *  0b1..OFF
8270  */
8271 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8272 
8273 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8274 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8275 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8276  *  0b0..ON
8277  *  0b1..OFF
8278  */
8279 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8280 /*! @} */
8281 
8282 /*! @name RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER */
8283 /*! @{ */
8284 
8285 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8286 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8287 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8288  *  0b0..ON
8289  *  0b1..OFF
8290  */
8291 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8292 
8293 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8294 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8295 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8296  *  0b0..ON
8297  *  0b1..OFF
8298  */
8299 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8300 
8301 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8302 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8303 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8304  *  0b0..ON
8305  *  0b1..OFF
8306  */
8307 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8308 
8309 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8310 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8311 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8312  *  0b0..ON
8313  *  0b1..OFF
8314  */
8315 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8316 
8317 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8318 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8319 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8320  *  0b0..ON
8321  *  0b1..OFF
8322  */
8323 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8324 
8325 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8326 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8327 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8328  *  0b0..ON
8329  *  0b1..OFF
8330  */
8331 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8332 
8333 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8334 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8335 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8336  *  0b0..ON
8337  *  0b1..OFF
8338  */
8339 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8340 
8341 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8342 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8343 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8344  *  0b0..ON
8345  *  0b1..OFF
8346  */
8347 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8348 
8349 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8350 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8351 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8352  *  0b0..ON
8353  *  0b1..OFF
8354  */
8355 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8356 
8357 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8358 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8359 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8360  *  0b0..ON
8361  *  0b1..OFF
8362  */
8363 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8364 
8365 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8366 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8367 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8368  *  0b0..ON
8369  *  0b1..OFF
8370  */
8371 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8372 
8373 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8374 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8375 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8376  *  0b0..ON
8377  *  0b1..OFF
8378  */
8379 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8380 
8381 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8382 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8383 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8384  *  0b0..ON
8385  *  0b1..OFF
8386  */
8387 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8388 
8389 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8390 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8391 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8392  *  0b0..ON
8393  *  0b1..OFF
8394  */
8395 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8396 
8397 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8398 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8399 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8400  *  0b0..ON
8401  *  0b1..OFF
8402  */
8403 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8404 
8405 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8406 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8407 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8408  *  0b0..ON
8409  *  0b1..OFF
8410  */
8411 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8412 /*! @} */
8413 
8414 /*! @name RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER */
8415 /*! @{ */
8416 
8417 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8418 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8419 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8420  *  0b0..ON
8421  *  0b1..OFF
8422  */
8423 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8424 
8425 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8426 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8427 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8428  *  0b0..ON
8429  *  0b1..OFF
8430  */
8431 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8432 
8433 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8434 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8435 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8436  *  0b0..ON
8437  *  0b1..OFF
8438  */
8439 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8440 
8441 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8442 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8443 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8444  *  0b0..ON
8445  *  0b1..OFF
8446  */
8447 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8448 
8449 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8450 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8451 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8452  *  0b0..ON
8453  *  0b1..OFF
8454  */
8455 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8456 
8457 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8458 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8459 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8460  *  0b0..ON
8461  *  0b1..OFF
8462  */
8463 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8464 
8465 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8466 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8467 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8468  *  0b0..ON
8469  *  0b1..OFF
8470  */
8471 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8472 
8473 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8474 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8475 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8476  *  0b0..ON
8477  *  0b1..OFF
8478  */
8479 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8480 
8481 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8482 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8483 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8484  *  0b0..ON
8485  *  0b1..OFF
8486  */
8487 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8488 
8489 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8490 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8491 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8492  *  0b0..ON
8493  *  0b1..OFF
8494  */
8495 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8496 
8497 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8498 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8499 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8500  *  0b0..ON
8501  *  0b1..OFF
8502  */
8503 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8504 
8505 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8506 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8507 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8508  *  0b0..ON
8509  *  0b1..OFF
8510  */
8511 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8512 
8513 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8514 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8515 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8516  *  0b0..ON
8517  *  0b1..OFF
8518  */
8519 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8520 
8521 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8522 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8523 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8524  *  0b0..ON
8525  *  0b1..OFF
8526  */
8527 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8528 
8529 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8530 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8531 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8532  *  0b0..ON
8533  *  0b1..OFF
8534  */
8535 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8536 
8537 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8538 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8539 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8540  *  0b0..ON
8541  *  0b1..OFF
8542  */
8543 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8544 /*! @} */
8545 
8546 /*! @name BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER */
8547 /*! @{ */
8548 
8549 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8550 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8551 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT
8552  *  0b0..Disabled
8553  *  0b1..Enabled
8554  */
8555 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8556 
8557 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8558 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8559 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT
8560  *  0b0..Disabled
8561  *  0b1..Enabled
8562  */
8563 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8564 
8565 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8566 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8567 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT
8568  *  0b0..Disabled
8569  *  0b1..Enabled
8570  */
8571 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8572 
8573 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8574 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8575 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT
8576  *  0b0..Disabled
8577  *  0b1..Enabled
8578  */
8579 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8580 
8581 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8582 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8583 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT
8584  *  0b0..Disabled
8585  *  0b1..Enabled
8586  */
8587 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8588 
8589 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8590 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8591 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT
8592  *  0b0..Disabled
8593  *  0b1..Enabled
8594  */
8595 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8596 
8597 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8598 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8599 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT
8600  *  0b0..Disabled
8601  *  0b1..Enabled
8602  */
8603 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8604 
8605 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8606 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8607 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT
8608  *  0b0..Disabled
8609  *  0b1..Enabled
8610  */
8611 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8612 
8613 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8614 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8615 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT
8616  *  0b0..Disabled
8617  *  0b1..Enabled
8618  */
8619 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8620 
8621 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8622 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8623 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT
8624  *  0b0..Disabled
8625  *  0b1..Enabled
8626  */
8627 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8628 
8629 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8630 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8631 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT
8632  *  0b0..Disabled
8633  *  0b1..Enabled
8634  */
8635 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8636 
8637 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8638 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8639 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT
8640  *  0b0..Disabled
8641  *  0b1..Enabled
8642  */
8643 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8644 
8645 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8646 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8647 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT
8648  *  0b0..Disabled
8649  *  0b1..Enabled
8650  */
8651 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8652 
8653 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8654 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8655 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT
8656  *  0b0..Disabled
8657  *  0b1..Enabled
8658  */
8659 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8660 
8661 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8662 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8663 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT
8664  *  0b0..Disabled
8665  *  0b1..Enabled
8666  */
8667 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8668 
8669 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8670 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8671 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT
8672  *  0b0..Disabled
8673  *  0b1..Enabled
8674  */
8675 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8676 /*! @} */
8677 
8678 /*! @name PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER */
8679 /*! @{ */
8680 
8681 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8682 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8683 /*! STBY_EN_SETPOINT0 - Standby mode
8684  *  0b0..Disabled
8685  *  0b1..Enabled
8686  */
8687 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8688 
8689 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8690 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8691 /*! STBY_EN_SETPOINT1 - Standby mode
8692  *  0b0..Disabled
8693  *  0b1..Enabled
8694  */
8695 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8696 
8697 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8698 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8699 /*! STBY_EN_SETPOINT2 - Standby mode
8700  *  0b0..Disabled
8701  *  0b1..Enabled
8702  */
8703 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8704 
8705 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8706 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8707 /*! STBY_EN_SETPOINT3 - Standby mode
8708  *  0b0..Disabled
8709  *  0b1..Enabled
8710  */
8711 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8712 
8713 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8714 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8715 /*! STBY_EN_SETPOINT4 - Standby mode
8716  *  0b0..Disabled
8717  *  0b1..Enabled
8718  */
8719 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8720 
8721 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8722 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8723 /*! STBY_EN_SETPOINT5 - Standby mode
8724  *  0b0..Disabled
8725  *  0b1..Enabled
8726  */
8727 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8728 
8729 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8730 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8731 /*! STBY_EN_SETPOINT6 - Standby mode
8732  *  0b0..Disabled
8733  *  0b1..Enabled
8734  */
8735 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8736 
8737 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8738 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8739 /*! STBY_EN_SETPOINT7 - Standby mode
8740  *  0b0..Disabled
8741  *  0b1..Enabled
8742  */
8743 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8744 
8745 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8746 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8747 /*! STBY_EN_SETPOINT8 - Standby mode
8748  *  0b0..Disabled
8749  *  0b1..Enabled
8750  */
8751 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8752 
8753 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8754 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8755 /*! STBY_EN_SETPOINT9 - Standby mode
8756  *  0b0..Disabled
8757  *  0b1..Enabled
8758  */
8759 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8760 
8761 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8762 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8763 /*! STBY_EN_SETPOINT10 - Standby mode
8764  *  0b0..Disabled
8765  *  0b1..Enabled
8766  */
8767 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8768 
8769 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8770 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8771 /*! STBY_EN_SETPOINT11 - Standby mode
8772  *  0b0..Disabled
8773  *  0b1..Enabled
8774  */
8775 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8776 
8777 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8778 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8779 /*! STBY_EN_SETPOINT12 - Standby mode
8780  *  0b0..Disabled
8781  *  0b1..Enabled
8782  */
8783 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8784 
8785 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8786 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8787 /*! STBY_EN_SETPOINT13 - Standby mode
8788  *  0b0..Disabled
8789  *  0b1..Enabled
8790  */
8791 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8792 
8793 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8794 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8795 /*! STBY_EN_SETPOINT14 - Standby mode
8796  *  0b0..Disabled
8797  *  0b1..Enabled
8798  */
8799 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8800 
8801 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8802 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8803 /*! STBY_EN_SETPOINT15 - Standby mode
8804  *  0b0..Disabled
8805  *  0b1..Enabled
8806  */
8807 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8808 /*! @} */
8809 
8810 /*! @name FBB_M7_STBY_EN_SP - FBB_M7_STBY_EN_SP_REGISTER */
8811 /*! @{ */
8812 
8813 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8814 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8815 /*! STBY_EN_SETPOINT0 - Standby mode
8816  *  0b0..Disabled
8817  *  0b1..Enabled
8818  */
8819 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8820 
8821 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8822 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8823 /*! STBY_EN_SETPOINT1 - Standby mode
8824  *  0b0..Disabled
8825  *  0b1..Enabled
8826  */
8827 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8828 
8829 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8830 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8831 /*! STBY_EN_SETPOINT2 - Standby mode
8832  *  0b0..Disabled
8833  *  0b1..Enabled
8834  */
8835 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8836 
8837 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8838 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8839 /*! STBY_EN_SETPOINT3 - Standby mode
8840  *  0b0..Disabled
8841  *  0b1..Enabled
8842  */
8843 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8844 
8845 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8846 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8847 /*! STBY_EN_SETPOINT4 - Standby mode
8848  *  0b0..Disabled
8849  *  0b1..Enabled
8850  */
8851 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8852 
8853 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8854 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8855 /*! STBY_EN_SETPOINT5 - Standby mode
8856  *  0b0..Disabled
8857  *  0b1..Enabled
8858  */
8859 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8860 
8861 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8862 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8863 /*! STBY_EN_SETPOINT6 - Standby mode
8864  *  0b0..Disabled
8865  *  0b1..Enabled
8866  */
8867 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8868 
8869 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8870 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8871 /*! STBY_EN_SETPOINT7 - Standby mode
8872  *  0b0..Disabled
8873  *  0b1..Enabled
8874  */
8875 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8876 
8877 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8878 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8879 /*! STBY_EN_SETPOINT8 - Standby mode
8880  *  0b0..Disabled
8881  *  0b1..Enabled
8882  */
8883 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8884 
8885 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8886 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8887 /*! STBY_EN_SETPOINT9 - Standby mode
8888  *  0b0..Disabled
8889  *  0b1..Enabled
8890  */
8891 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8892 
8893 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8894 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8895 /*! STBY_EN_SETPOINT10 - Standby mode
8896  *  0b0..Disabled
8897  *  0b1..Enabled
8898  */
8899 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8900 
8901 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8902 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8903 /*! STBY_EN_SETPOINT11 - Standby mode
8904  *  0b0..Disabled
8905  *  0b1..Enabled
8906  */
8907 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8908 
8909 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8910 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8911 /*! STBY_EN_SETPOINT12 - Standby mode
8912  *  0b0..Disabled
8913  *  0b1..Enabled
8914  */
8915 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8916 
8917 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8918 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8919 /*! STBY_EN_SETPOINT13 - Standby mode
8920  *  0b0..Disabled
8921  *  0b1..Enabled
8922  */
8923 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8924 
8925 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8926 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8927 /*! STBY_EN_SETPOINT14 - Standby mode
8928  *  0b0..Disabled
8929  *  0b1..Enabled
8930  */
8931 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8932 
8933 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8934 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8935 /*! STBY_EN_SETPOINT15 - Standby mode
8936  *  0b0..Disabled
8937  *  0b1..Enabled
8938  */
8939 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8940 /*! @} */
8941 
8942 /*! @name RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER */
8943 /*! @{ */
8944 
8945 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8946 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8947 /*! STBY_EN_SETPOINT0 - Standby mode
8948  *  0b0..Disabled
8949  *  0b1..Enabled
8950  */
8951 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8952 
8953 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8954 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8955 /*! STBY_EN_SETPOINT1 - Standby mode
8956  *  0b0..Disabled
8957  *  0b1..Enabled
8958  */
8959 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8960 
8961 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8962 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8963 /*! STBY_EN_SETPOINT2 - Standby mode
8964  *  0b0..Disabled
8965  *  0b1..Enabled
8966  */
8967 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8968 
8969 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8970 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8971 /*! STBY_EN_SETPOINT3 - Standby mode
8972  *  0b0..Disabled
8973  *  0b1..Enabled
8974  */
8975 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8976 
8977 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8978 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8979 /*! STBY_EN_SETPOINT4 - Standby mode
8980  *  0b0..Disabled
8981  *  0b1..Enabled
8982  */
8983 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8984 
8985 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8986 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8987 /*! STBY_EN_SETPOINT5 - Standby mode
8988  *  0b0..Disabled
8989  *  0b1..Enabled
8990  */
8991 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8992 
8993 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8994 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8995 /*! STBY_EN_SETPOINT6 - Standby mode
8996  *  0b0..Disabled
8997  *  0b1..Enabled
8998  */
8999 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
9000 
9001 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
9002 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
9003 /*! STBY_EN_SETPOINT7 - Standby mode
9004  *  0b0..Disabled
9005  *  0b1..Enabled
9006  */
9007 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
9008 
9009 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
9010 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
9011 /*! STBY_EN_SETPOINT8 - Standby mode
9012  *  0b0..Disabled
9013  *  0b1..Enabled
9014  */
9015 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
9016 
9017 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
9018 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
9019 /*! STBY_EN_SETPOINT9 - Standby mode
9020  *  0b0..Disabled
9021  *  0b1..Enabled
9022  */
9023 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
9024 
9025 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
9026 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
9027 /*! STBY_EN_SETPOINT10 - Standby mode
9028  *  0b0..Disabled
9029  *  0b1..Enabled
9030  */
9031 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
9032 
9033 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
9034 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
9035 /*! STBY_EN_SETPOINT11 - Standby mode
9036  *  0b0..Disabled
9037  *  0b1..Enabled
9038  */
9039 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
9040 
9041 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
9042 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
9043 /*! STBY_EN_SETPOINT12 - Standby mode
9044  *  0b0..Disabled
9045  *  0b1..Enabled
9046  */
9047 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
9048 
9049 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
9050 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
9051 /*! STBY_EN_SETPOINT13 - Standby mode
9052  *  0b0..Disabled
9053  *  0b1..Enabled
9054  */
9055 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
9056 
9057 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
9058 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
9059 /*! STBY_EN_SETPOINT14 - Standby mode
9060  *  0b0..Disabled
9061  *  0b1..Enabled
9062  */
9063 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
9064 
9065 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
9066 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
9067 /*! STBY_EN_SETPOINT15 - Standby mode
9068  *  0b0..Disabled
9069  *  0b1..Enabled
9070  */
9071 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
9072 /*! @} */
9073 
9074 /*! @name RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER */
9075 /*! @{ */
9076 
9077 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
9078 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
9079 /*! STBY_EN_SETPOINT0 - Standby mode
9080  *  0b0..Disabled
9081  *  0b1..Enabled
9082  */
9083 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
9084 
9085 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
9086 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
9087 /*! STBY_EN_SETPOINT1 - Standby mode
9088  *  0b0..Disabled
9089  *  0b1..Enabled
9090  */
9091 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
9092 
9093 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
9094 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
9095 /*! STBY_EN_SETPOINT2 - Standby mode
9096  *  0b0..Disabled
9097  *  0b1..Enabled
9098  */
9099 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
9100 
9101 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
9102 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
9103 /*! STBY_EN_SETPOINT3 - Standby mode
9104  *  0b0..Disabled
9105  *  0b1..Enabled
9106  */
9107 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
9108 
9109 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
9110 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
9111 /*! STBY_EN_SETPOINT4 - Standby mode
9112  *  0b0..Disabled
9113  *  0b1..Enabled
9114  */
9115 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
9116 
9117 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
9118 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
9119 /*! STBY_EN_SETPOINT5 - Standby mode
9120  *  0b0..Disabled
9121  *  0b1..Enabled
9122  */
9123 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
9124 
9125 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
9126 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
9127 /*! STBY_EN_SETPOINT6 - Standby mode
9128  *  0b0..Disabled
9129  *  0b1..Enabled
9130  */
9131 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
9132 
9133 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
9134 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
9135 /*! STBY_EN_SETPOINT7 - Standby mode
9136  *  0b0..Disabled
9137  *  0b1..Enabled
9138  */
9139 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
9140 
9141 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
9142 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
9143 /*! STBY_EN_SETPOINT8 - Standby mode
9144  *  0b0..Disabled
9145  *  0b1..Enabled
9146  */
9147 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
9148 
9149 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
9150 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
9151 /*! STBY_EN_SETPOINT9 - Standby mode
9152  *  0b0..Disabled
9153  *  0b1..Enabled
9154  */
9155 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
9156 
9157 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
9158 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
9159 /*! STBY_EN_SETPOINT10 - Standby mode
9160  *  0b0..Disabled
9161  *  0b1..Enabled
9162  */
9163 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
9164 
9165 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
9166 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
9167 /*! STBY_EN_SETPOINT11 - Standby mode
9168  *  0b0..Disabled
9169  *  0b1..Enabled
9170  */
9171 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
9172 
9173 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
9174 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
9175 /*! STBY_EN_SETPOINT12 - Standby mode
9176  *  0b0..Disabled
9177  *  0b1..Enabled
9178  */
9179 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
9180 
9181 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
9182 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
9183 /*! STBY_EN_SETPOINT13 - Standby mode
9184  *  0b0..Disabled
9185  *  0b1..Enabled
9186  */
9187 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
9188 
9189 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
9190 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
9191 /*! STBY_EN_SETPOINT14 - Standby mode
9192  *  0b0..Disabled
9193  *  0b1..Enabled
9194  */
9195 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
9196 
9197 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
9198 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
9199 /*! STBY_EN_SETPOINT15 - Standby mode
9200  *  0b0..Disabled
9201  *  0b1..Enabled
9202  */
9203 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
9204 /*! @} */
9205 
9206 /*! @name FBB_M7_CONFIGURE - FBB_M7_CONFIGURE_REGISTER */
9207 /*! @{ */
9208 
9209 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9210 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9211 /*! WB_CFG_PW - wb_cfg_pw
9212  */
9213 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK)
9214 
9215 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9216 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9217 /*! WB_CFG_NW - wb_cfg_nw
9218  */
9219 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK)
9220 
9221 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9222 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9223 /*! OSCILLATOR_BITS - oscillator_bits
9224  */
9225 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK)
9226 
9227 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9228 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9229 /*! REGULATOR_STRENGTH - regulator_strength
9230  */
9231 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK)
9232 /*! @} */
9233 
9234 /*! @name RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER */
9235 /*! @{ */
9236 
9237 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9238 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9239 /*! WB_CFG_PW - wb_cfg_pw
9240  */
9241 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK)
9242 
9243 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9244 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9245 /*! WB_CFG_NW - wb_cfg_nw
9246  */
9247 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK)
9248 
9249 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9250 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9251 /*! OSCILLATOR_BITS - oscillator_bits
9252  */
9253 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK)
9254 
9255 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9256 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9257 /*! REGULATOR_STRENGTH - regulator_strength
9258  */
9259 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK)
9260 /*! @} */
9261 
9262 /*! @name RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER */
9263 /*! @{ */
9264 
9265 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9266 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9267 /*! WB_CFG_PW - wb_cfg_pw
9268  */
9269 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK)
9270 
9271 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9272 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9273 /*! WB_CFG_NW - wb_cfg_nw
9274  */
9275 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK)
9276 
9277 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9278 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9279 /*! OSCILLATOR_BITS - oscillator_bits
9280  */
9281 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK)
9282 
9283 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9284 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9285 /*! REGULATOR_STRENGTH - regulator_strength
9286  */
9287 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK)
9288 /*! @} */
9289 
9290 /*! @name REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER */
9291 /*! @{ */
9292 
9293 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U)
9294 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U)
9295 /*! REFTOP_IBZTCADJ - REFTOP_IBZTCADJ
9296  */
9297 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK)
9298 
9299 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U)
9300 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U)
9301 /*! REFTOP_VBGADJ - REFTOP_VBGADJ
9302  */
9303 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK)
9304 
9305 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U)
9306 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U)
9307 /*! REFTOP_TRIM_EN - REFTOP_TRIM_EN
9308  */
9309 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK)
9310 /*! @} */
9311 
9312 /*! @name LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER */
9313 /*! @{ */
9314 
9315 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U)
9316 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U)
9317 /*! LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM
9318  */
9319 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK)
9320 
9321 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U)
9322 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U)
9323 /*! LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN
9324  */
9325 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK)
9326 /*! @} */
9327 
9328 
9329 /*!
9330  * @}
9331  */ /* end of group ANADIG_PMU_Register_Masks */
9332 
9333 
9334 /* ANADIG_PMU - Peripheral instance base addresses */
9335 /** Peripheral ANADIG_PMU base address */
9336 #define ANADIG_PMU_BASE                          (0x40C84000u)
9337 /** Peripheral ANADIG_PMU base pointer */
9338 #define ANADIG_PMU                               ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
9339 /** Array initializer of ANADIG_PMU peripheral base addresses */
9340 #define ANADIG_PMU_BASE_ADDRS                    { ANADIG_PMU_BASE }
9341 /** Array initializer of ANADIG_PMU peripheral base pointers */
9342 #define ANADIG_PMU_BASE_PTRS                     { ANADIG_PMU }
9343 
9344 /*!
9345  * @}
9346  */ /* end of group ANADIG_PMU_Peripheral_Access_Layer */
9347 
9348 
9349 /* ----------------------------------------------------------------------------
9350    -- ANADIG_TEMPSENSOR Peripheral Access Layer
9351    ---------------------------------------------------------------------------- */
9352 
9353 /*!
9354  * @addtogroup ANADIG_TEMPSENSOR_Peripheral_Access_Layer ANADIG_TEMPSENSOR Peripheral Access Layer
9355  * @{
9356  */
9357 
9358 /** ANADIG_TEMPSENSOR - Register Layout Typedef */
9359 typedef struct {
9360        uint8_t RESERVED_0[1024];
9361   __IO uint32_t TEMPSENSOR;                        /**< Tempsensor Register, offset: 0x400 */
9362        uint8_t RESERVED_1[44];
9363   __I  uint32_t TEMPSNS_OTP_TRIM_VALUE;            /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430 */
9364 } ANADIG_TEMPSENSOR_Type;
9365 
9366 /* ----------------------------------------------------------------------------
9367    -- ANADIG_TEMPSENSOR Register Masks
9368    ---------------------------------------------------------------------------- */
9369 
9370 /*!
9371  * @addtogroup ANADIG_TEMPSENSOR_Register_Masks ANADIG_TEMPSENSOR Register Masks
9372  * @{
9373  */
9374 
9375 /*! @name TEMPSENSOR - Tempsensor Register */
9376 /*! @{ */
9377 
9378 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U)
9379 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U)
9380 /*! TEMPSNS_AI_TOGGLE - AI toggle
9381  */
9382 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK)
9383 
9384 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U)
9385 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U)
9386 /*! TEMPSNS_AI_BUSY - AI Busy monitor
9387  */
9388 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK)
9389 /*! @} */
9390 
9391 /*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */
9392 /*! @{ */
9393 
9394 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
9395 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
9396 /*! TEMPSNS_TEMP_VAL - Temperature Value at 25C
9397  */
9398 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK)
9399 /*! @} */
9400 
9401 
9402 /*!
9403  * @}
9404  */ /* end of group ANADIG_TEMPSENSOR_Register_Masks */
9405 
9406 
9407 /* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
9408 /** Peripheral ANADIG_TEMPSENSOR base address */
9409 #define ANADIG_TEMPSENSOR_BASE                   (0x40C84000u)
9410 /** Peripheral ANADIG_TEMPSENSOR base pointer */
9411 #define ANADIG_TEMPSENSOR                        ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
9412 /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
9413 #define ANADIG_TEMPSENSOR_BASE_ADDRS             { ANADIG_TEMPSENSOR_BASE }
9414 /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
9415 #define ANADIG_TEMPSENSOR_BASE_PTRS              { ANADIG_TEMPSENSOR }
9416 
9417 /*!
9418  * @}
9419  */ /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
9420 
9421 
9422 /* ----------------------------------------------------------------------------
9423    -- AOI Peripheral Access Layer
9424    ---------------------------------------------------------------------------- */
9425 
9426 /*!
9427  * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
9428  * @{
9429  */
9430 
9431 /** AOI - Register Layout Typedef */
9432 typedef struct {
9433   struct {                                         /* offset: 0x0, array step: 0x4 */
9434     __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
9435     __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
9436   } BFCRT[4];
9437 } AOI_Type;
9438 
9439 /* ----------------------------------------------------------------------------
9440    -- AOI Register Masks
9441    ---------------------------------------------------------------------------- */
9442 
9443 /*!
9444  * @addtogroup AOI_Register_Masks AOI Register Masks
9445  * @{
9446  */
9447 
9448 /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
9449 /*! @{ */
9450 
9451 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
9452 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
9453 /*! PT1_DC - Product term 1, D input configuration
9454  *  0b00..Force the D input in this product term to a logical zero
9455  *  0b01..Pass the D input in this product term
9456  *  0b10..Complement the D input in this product term
9457  *  0b11..Force the D input in this product term to a logical one
9458  */
9459 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
9460 
9461 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
9462 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
9463 /*! PT1_CC - Product term 1, C input configuration
9464  *  0b00..Force the C input in this product term to a logical zero
9465  *  0b01..Pass the C input in this product term
9466  *  0b10..Complement the C input in this product term
9467  *  0b11..Force the C input in this product term to a logical one
9468  */
9469 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
9470 
9471 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
9472 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
9473 /*! PT1_BC - Product term 1, B input configuration
9474  *  0b00..Force the B input in this product term to a logical zero
9475  *  0b01..Pass the B input in this product term
9476  *  0b10..Complement the B input in this product term
9477  *  0b11..Force the B input in this product term to a logical one
9478  */
9479 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
9480 
9481 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
9482 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
9483 /*! PT1_AC - Product term 1, A input configuration
9484  *  0b00..Force the A input in this product term to a logical zero
9485  *  0b01..Pass the A input in this product term
9486  *  0b10..Complement the A input in this product term
9487  *  0b11..Force the A input in this product term to a logical one
9488  */
9489 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
9490 
9491 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
9492 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
9493 /*! PT0_DC - Product term 0, D input configuration
9494  *  0b00..Force the D input in this product term to a logical zero
9495  *  0b01..Pass the D input in this product term
9496  *  0b10..Complement the D input in this product term
9497  *  0b11..Force the D input in this product term to a logical one
9498  */
9499 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
9500 
9501 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
9502 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
9503 /*! PT0_CC - Product term 0, C input configuration
9504  *  0b00..Force the C input in this product term to a logical zero
9505  *  0b01..Pass the C input in this product term
9506  *  0b10..Complement the C input in this product term
9507  *  0b11..Force the C input in this product term to a logical one
9508  */
9509 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
9510 
9511 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
9512 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
9513 /*! PT0_BC - Product term 0, B input configuration
9514  *  0b00..Force the B input in this product term to a logical zero
9515  *  0b01..Pass the B input in this product term
9516  *  0b10..Complement the B input in this product term
9517  *  0b11..Force the B input in this product term to a logical one
9518  */
9519 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
9520 
9521 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
9522 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
9523 /*! PT0_AC - Product term 0, A input configuration
9524  *  0b00..Force the A input in this product term to a logical zero
9525  *  0b01..Pass the A input in this product term
9526  *  0b10..Complement the A input in this product term
9527  *  0b11..Force the A input in this product term to a logical one
9528  */
9529 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
9530 /*! @} */
9531 
9532 /* The count of AOI_BFCRT01 */
9533 #define AOI_BFCRT01_COUNT                        (4U)
9534 
9535 /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
9536 /*! @{ */
9537 
9538 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
9539 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
9540 /*! PT3_DC - Product term 3, D input configuration
9541  *  0b00..Force the D input in this product term to a logical zero
9542  *  0b01..Pass the D input in this product term
9543  *  0b10..Complement the D input in this product term
9544  *  0b11..Force the D input in this product term to a logical one
9545  */
9546 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
9547 
9548 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
9549 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
9550 /*! PT3_CC - Product term 3, C input configuration
9551  *  0b00..Force the C input in this product term to a logical zero
9552  *  0b01..Pass the C input in this product term
9553  *  0b10..Complement the C input in this product term
9554  *  0b11..Force the C input in this product term to a logical one
9555  */
9556 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
9557 
9558 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
9559 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
9560 /*! PT3_BC - Product term 3, B input configuration
9561  *  0b00..Force the B input in this product term to a logical zero
9562  *  0b01..Pass the B input in this product term
9563  *  0b10..Complement the B input in this product term
9564  *  0b11..Force the B input in this product term to a logical one
9565  */
9566 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
9567 
9568 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
9569 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
9570 /*! PT3_AC - Product term 3, A input configuration
9571  *  0b00..Force the A input in this product term to a logical zero
9572  *  0b01..Pass the A input in this product term
9573  *  0b10..Complement the A input in this product term
9574  *  0b11..Force the A input in this product term to a logical one
9575  */
9576 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
9577 
9578 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
9579 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
9580 /*! PT2_DC - Product term 2, D input configuration
9581  *  0b00..Force the D input in this product term to a logical zero
9582  *  0b01..Pass the D input in this product term
9583  *  0b10..Complement the D input in this product term
9584  *  0b11..Force the D input in this product term to a logical one
9585  */
9586 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
9587 
9588 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
9589 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
9590 /*! PT2_CC - Product term 2, C input configuration
9591  *  0b00..Force the C input in this product term to a logical zero
9592  *  0b01..Pass the C input in this product term
9593  *  0b10..Complement the C input in this product term
9594  *  0b11..Force the C input in this product term to a logical one
9595  */
9596 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
9597 
9598 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
9599 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
9600 /*! PT2_BC - Product term 2, B input configuration
9601  *  0b00..Force the B input in this product term to a logical zero
9602  *  0b01..Pass the B input in this product term
9603  *  0b10..Complement the B input in this product term
9604  *  0b11..Force the B input in this product term to a logical one
9605  */
9606 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
9607 
9608 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
9609 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
9610 /*! PT2_AC - Product term 2, A input configuration
9611  *  0b00..Force the A input in this product term to a logical zero
9612  *  0b01..Pass the A input in this product term
9613  *  0b10..Complement the A input in this product term
9614  *  0b11..Force the A input in this product term to a logical one
9615  */
9616 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
9617 /*! @} */
9618 
9619 /* The count of AOI_BFCRT23 */
9620 #define AOI_BFCRT23_COUNT                        (4U)
9621 
9622 
9623 /*!
9624  * @}
9625  */ /* end of group AOI_Register_Masks */
9626 
9627 
9628 /* AOI - Peripheral instance base addresses */
9629 /** Peripheral AOI1 base address */
9630 #define AOI1_BASE                                (0x400B8000u)
9631 /** Peripheral AOI1 base pointer */
9632 #define AOI1                                     ((AOI_Type *)AOI1_BASE)
9633 /** Peripheral AOI2 base address */
9634 #define AOI2_BASE                                (0x400BC000u)
9635 /** Peripheral AOI2 base pointer */
9636 #define AOI2                                     ((AOI_Type *)AOI2_BASE)
9637 /** Array initializer of AOI peripheral base addresses */
9638 #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE }
9639 /** Array initializer of AOI peripheral base pointers */
9640 #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2 }
9641 
9642 /*!
9643  * @}
9644  */ /* end of group AOI_Peripheral_Access_Layer */
9645 
9646 
9647 /* ----------------------------------------------------------------------------
9648    -- ASRC Peripheral Access Layer
9649    ---------------------------------------------------------------------------- */
9650 
9651 /*!
9652  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
9653  * @{
9654  */
9655 
9656 /** ASRC - Register Layout Typedef */
9657 typedef struct {
9658   __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
9659   __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
9660        uint8_t RESERVED_0[4];
9661   __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
9662   __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
9663   __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
9664   __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
9665   __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
9666   __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
9667        uint8_t RESERVED_1[28];
9668   __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
9669   __IO uint32_t ASRTFR1;                           /**< ASRC Task Queue FIFO Register 1, offset: 0x54 */
9670        uint8_t RESERVED_2[4];
9671   __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
9672   __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
9673   __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
9674   __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
9675   __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
9676   __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
9677   __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
9678        uint8_t RESERVED_3[8];
9679   __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
9680   __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
9681   __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
9682   __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
9683   __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
9684   __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
9685   __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
9686   __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
9687   __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
9688   __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
9689   __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
9690   __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
9691   __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
9692   __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
9693        uint8_t RESERVED_4[8];
9694   __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
9695 } ASRC_Type;
9696 
9697 /* ----------------------------------------------------------------------------
9698    -- ASRC Register Masks
9699    ---------------------------------------------------------------------------- */
9700 
9701 /*!
9702  * @addtogroup ASRC_Register_Masks ASRC Register Masks
9703  * @{
9704  */
9705 
9706 /*! @name ASRCTR - ASRC Control Register */
9707 /*! @{ */
9708 
9709 #define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
9710 #define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
9711 /*! ASRCEN - ASRCEN
9712  *  0b0..operation of ASRC disabled
9713  *  0b1..operation ASRC is enabled
9714  */
9715 #define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
9716 
9717 #define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
9718 #define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
9719 /*! ASREA - ASREA
9720  *  0b0..operation of conversion A is disabled
9721  *  0b1..operation of conversion A is enabled
9722  */
9723 #define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
9724 
9725 #define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
9726 #define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
9727 /*! ASREB - ASREB
9728  *  0b0..operation of conversion B is disabled
9729  *  0b1..operation of conversion B is enabled
9730  */
9731 #define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
9732 
9733 #define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
9734 #define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
9735 /*! ASREC - ASREC
9736  *  0b0..operation of conversion C is disabled
9737  *  0b1..operation of conversion C is enabled
9738  */
9739 #define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
9740 
9741 #define ASRC_ASRCTR_SRST_MASK                    (0x10U)
9742 #define ASRC_ASRCTR_SRST_SHIFT                   (4U)
9743 /*! SRST - SRST
9744  *  0b0..ASRC Software reset cleared
9745  *  0b1..ASRC Software reset generated. NOTE: This is a self-clear bit
9746  */
9747 #define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
9748 
9749 #define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
9750 #define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
9751 /*! IDRA - IDRA
9752  *  0b0..ASRC internal measured ratio is used
9753  *  0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used
9754  */
9755 #define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
9756 
9757 #define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
9758 #define ASRC_ASRCTR_USRA_SHIFT                   (14U)
9759 /*! USRA - USRA
9760  *  0b1..Use ratio as the input to ASRC for pair A
9761  *  0b0..Do not use ratio as the input to ASRC for pair A
9762  */
9763 #define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
9764 
9765 #define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
9766 #define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
9767 /*! IDRB - IDRB
9768  *  0b0..ASRC internal measured ratio is used
9769  *  0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used
9770  */
9771 #define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
9772 
9773 #define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
9774 #define ASRC_ASRCTR_USRB_SHIFT                   (16U)
9775 /*! USRB - USRB
9776  *  0b1..Use ratio as the input to ASRC for pair B
9777  *  0b0..Do not use ratio as the input to ASRC for pair B
9778  */
9779 #define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
9780 
9781 #define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
9782 #define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
9783 /*! IDRC - IDRC
9784  *  0b0..ASRC internal measured ratio is used
9785  *  0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used
9786  */
9787 #define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
9788 
9789 #define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
9790 #define ASRC_ASRCTR_USRC_SHIFT                   (18U)
9791 /*! USRC - USRC
9792  *  0b1..Use ratio as the input to ASRC for pair C
9793  *  0b0..Do not use ratio as the input to ASRC for pair C
9794  */
9795 #define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
9796 
9797 #define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
9798 #define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
9799 /*! ATSA - ATSA
9800  *  0b1..Pair A automatically updates its pre-processing and post-processing options
9801  *  0b0..Pair A does not automatically update its pre-processing and post-processing options
9802  */
9803 #define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
9804 
9805 #define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
9806 #define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
9807 /*! ATSB - ATSB
9808  *  0b1..Pair B automatically updates its pre-processing and post-processing options
9809  *  0b0..Pair B does not automatically update its pre-processing and post-processing options
9810  */
9811 #define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
9812 
9813 #define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
9814 #define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
9815 /*! ATSC - ATSC
9816  *  0b1..Pair C automatically updates its pre-processing and post-processing options
9817  *  0b0..Pair C does not automatically update its pre-processing and post-processing options
9818  */
9819 #define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
9820 /*! @} */
9821 
9822 /*! @name ASRIER - ASRC Interrupt Enable Register */
9823 /*! @{ */
9824 
9825 #define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
9826 #define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
9827 /*! ADIEA - ADIEA
9828  *  0b1..interrupt enabled
9829  *  0b0..interrupt disabled
9830  */
9831 #define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
9832 
9833 #define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
9834 #define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
9835 /*! ADIEB - ADIEB
9836  *  0b1..interrupt enabled
9837  *  0b0..interrupt disabled
9838  */
9839 #define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
9840 
9841 #define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
9842 #define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
9843 /*! ADIEC - ADIEC
9844  *  0b1..interrupt enabled
9845  *  0b0..interrupt disabled
9846  */
9847 #define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
9848 
9849 #define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
9850 #define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
9851 /*! ADOEA - ADOEA
9852  *  0b1..interrupt enabled
9853  *  0b0..interrupt disabled
9854  */
9855 #define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
9856 
9857 #define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
9858 #define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
9859 /*! ADOEB - ADOEB
9860  *  0b1..interrupt enabled
9861  *  0b0..interrupt disabled
9862  */
9863 #define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
9864 
9865 #define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
9866 #define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
9867 /*! ADOEC - ADOEC
9868  *  0b1..interrupt enabled
9869  *  0b0..interrupt disabled
9870  */
9871 #define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
9872 
9873 #define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
9874 #define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
9875 /*! AOLIE - AOLIE
9876  *  0b1..interrupt enabled
9877  *  0b0..interrupt disabled
9878  */
9879 #define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
9880 
9881 #define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
9882 #define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
9883 /*! AFPWE - AFPWE
9884  *  0b1..interrupt enabled
9885  *  0b0..interrupt disabled
9886  */
9887 #define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
9888 /*! @} */
9889 
9890 /*! @name ASRCNCR - ASRC Channel Number Configuration Register */
9891 /*! @{ */
9892 
9893 #define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
9894 #define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
9895 /*! ANCA - ANCA
9896  *  0b0000..0 channels in A (Pair A is disabled)
9897  *  0b0001..1 channel in A
9898  *  0b0010..2 channels in A
9899  *  0b0011..3 channels in A
9900  *  0b0100..4 channels in A
9901  *  0b0101..5 channels in A
9902  *  0b0110..6 channels in A
9903  *  0b0111..7 channels in A
9904  *  0b1000..8 channels in A
9905  *  0b1001..9 channels in A
9906  *  0b1010..10 channels in A
9907  *  0b1011-0b1111..Should not be used.
9908  */
9909 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
9910 
9911 #define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
9912 #define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
9913 /*! ANCB - ANCB
9914  *  0b0000..0 channels in B (Pair B is disabled)
9915  *  0b0001..1 channel in B
9916  *  0b0010..2 channels in B
9917  *  0b0011..3 channels in B
9918  *  0b0100..4 channels in B
9919  *  0b0101..5 channels in B
9920  *  0b0110..6 channels in B
9921  *  0b0111..7 channels in B
9922  *  0b1000..8 channels in B
9923  *  0b1001..9 channels in B
9924  *  0b1010..10 channels in B
9925  *  0b1011-0b1111..Should not be used.
9926  */
9927 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
9928 
9929 #define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
9930 #define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
9931 /*! ANCC - ANCC
9932  *  0b0000..0 channels in C (Pair C is disabled)
9933  *  0b0001..1 channel in C
9934  *  0b0010..2 channels in C
9935  *  0b0011..3 channels in C
9936  *  0b0100..4 channels in C
9937  *  0b0101..5 channels in C
9938  *  0b0110..6 channels in C
9939  *  0b0111..7 channels in C
9940  *  0b1000..8 channels in C
9941  *  0b1001..9 channels in C
9942  *  0b1010..10 channels in C
9943  *  0b1011-0b1111..Should not be used.
9944  */
9945 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
9946 /*! @} */
9947 
9948 /*! @name ASRCFG - ASRC Filter Configuration Status Register */
9949 /*! @{ */
9950 
9951 #define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
9952 #define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
9953 /*! PREMODA - PREMODA
9954  *  0b00..Select Upsampling-by-2
9955  *  0b01..Select Direct-Connection
9956  *  0b10..Select Downsampling-by-2
9957  *  0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use.
9958  */
9959 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
9960 
9961 #define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
9962 #define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
9963 /*! POSTMODA - POSTMODA
9964  *  0b00..Select Upsampling-by-2
9965  *  0b01..Select Direct-Connection
9966  *  0b10..Select Downsampling-by-2
9967  *  0b11..Reserved.
9968  */
9969 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
9970 
9971 #define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
9972 #define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
9973 /*! PREMODB - PREMODB
9974  *  0b00..Select Upsampling-by-2
9975  *  0b01..Select Direct-Connection
9976  *  0b10..Select Downsampling-by-2
9977  *  0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use.
9978  */
9979 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
9980 
9981 #define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
9982 #define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
9983 /*! POSTMODB - POSTMODB
9984  *  0b00..Select Upsampling-by-2
9985  *  0b01..Select Direct-Connection
9986  *  0b10..Select Downsampling-by-2
9987  *  0b11..Reserved.
9988  */
9989 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
9990 
9991 #define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
9992 #define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
9993 /*! PREMODC - PREMODC
9994  *  0b00..Select Upsampling-by-2
9995  *  0b01..Select Direct-Connection
9996  *  0b10..Select Downsampling-by-2
9997  *  0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use.
9998  */
9999 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
10000 
10001 #define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
10002 #define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
10003 /*! POSTMODC - POSTMODC
10004  *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
10005  *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
10006  *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
10007  *  0b11..Reserved.
10008  */
10009 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
10010 
10011 #define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
10012 #define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
10013 /*! NDPRA - NDPRA
10014  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
10015  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
10016  */
10017 #define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
10018 
10019 #define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
10020 #define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
10021 /*! NDPRB - NDPRB
10022  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
10023  *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
10024  */
10025 #define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
10026 
10027 #define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
10028 #define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
10029 /*! NDPRC - NDPRC
10030  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
10031  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
10032  */
10033 #define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
10034 
10035 #define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
10036 #define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
10037 /*! INIRQA - INIRQA
10038  *  0b0..Initialization for Conversion Pair A not served
10039  *  0b1..Initialization for Conversion Pair A served
10040  */
10041 #define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
10042 
10043 #define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
10044 #define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
10045 /*! INIRQB - INIRQB
10046  *  0b0..Initialization for Conversion Pair B not served
10047  *  0b1..Initialization for Conversion Pair B served
10048  */
10049 #define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
10050 
10051 #define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
10052 #define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
10053 /*! INIRQC - INIRQC
10054  *  0b0..Initialization for Conversion Pair C not served
10055  *  0b1..Initialization for Conversion Pair C served
10056  */
10057 #define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
10058 /*! @} */
10059 
10060 /*! @name ASRCSR - ASRC Clock Source Register */
10061 /*! @{ */
10062 
10063 #define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
10064 #define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
10065 /*! AICSA - AICSA
10066  *  0b0000..bit clock 0
10067  *  0b0001..bit clock 1
10068  *  0b0010..bit clock 2
10069  *  0b0011..bit clock 3
10070  *  0b0100..bit clock 4
10071  *  0b0101..bit clock 5
10072  *  0b0110..bit clock 6
10073  *  0b0111..bit clock 7
10074  *  0b1000..bit clock 8
10075  *  0b1001..bit clock 9
10076  *  0b1010..bit clock A
10077  *  0b1011..bit clock B
10078  *  0b1100..bit clock C
10079  *  0b1101..bit clock D
10080  *  0b1110..bit clock E
10081  *  0b1111..clock disabled, connected to zero
10082  */
10083 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
10084 
10085 #define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
10086 #define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
10087 /*! AICSB - AICSB
10088  *  0b0000..bit clock 0
10089  *  0b0001..bit clock 1
10090  *  0b0010..bit clock 2
10091  *  0b0011..bit clock 3
10092  *  0b0100..bit clock 4
10093  *  0b0101..bit clock 5
10094  *  0b0110..bit clock 6
10095  *  0b0111..bit clock 7
10096  *  0b1000..bit clock 8
10097  *  0b1001..bit clock 9
10098  *  0b1010..bit clock A
10099  *  0b1011..bit clock B
10100  *  0b1100..bit clock C
10101  *  0b1101..bit clock D
10102  *  0b1110..bit clock E
10103  *  0b1111..clock disabled, connected to zero
10104  */
10105 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
10106 
10107 #define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
10108 #define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
10109 /*! AICSC - AICSC
10110  *  0b0000..bit clock 0
10111  *  0b0001..bit clock 1
10112  *  0b0010..bit clock 2
10113  *  0b0011..bit clock 3
10114  *  0b0100..bit clock 4
10115  *  0b0101..bit clock 5
10116  *  0b0110..bit clock 6
10117  *  0b0111..bit clock 7
10118  *  0b1000..bit clock 8
10119  *  0b1001..bit clock 9
10120  *  0b1010..bit clock A
10121  *  0b1011..bit clock B
10122  *  0b1100..bit clock C
10123  *  0b1101..bit clock D
10124  *  0b1110..bit clock E
10125  *  0b1111..clock disabled, connected to zero
10126  */
10127 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
10128 
10129 #define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
10130 #define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
10131 /*! AOCSA - AOCSA
10132  *  0b0000..bit clock 0
10133  *  0b0001..bit clock 1
10134  *  0b0010..bit clock 2
10135  *  0b0011..bit clock 3
10136  *  0b0100..bit clock 4
10137  *  0b0101..bit clock 5
10138  *  0b0110..bit clock 6
10139  *  0b0111..bit clock 7
10140  *  0b1000..bit clock 8
10141  *  0b1001..bit clock 9
10142  *  0b1010..bit clock A
10143  *  0b1011..bit clock B
10144  *  0b1100..bit clock C
10145  *  0b1101..bit clock D
10146  *  0b1110..bit clock E
10147  *  0b1111..clock disabled, connected to zero
10148  */
10149 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
10150 
10151 #define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
10152 #define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
10153 /*! AOCSB - AOCSB
10154  *  0b0000..bit clock 0
10155  *  0b0001..bit clock 1
10156  *  0b0010..bit clock 2
10157  *  0b0011..bit clock 3
10158  *  0b0100..bit clock 4
10159  *  0b0101..bit clock 5
10160  *  0b0110..bit clock 6
10161  *  0b0111..bit clock 7
10162  *  0b1000..bit clock 8
10163  *  0b1001..bit clock 9
10164  *  0b1010..bit clock A
10165  *  0b1011..bit clock B
10166  *  0b1100..bit clock C
10167  *  0b1101..bit clock D
10168  *  0b1110..bit clock E
10169  *  0b1111..clock disabled, connected to zero
10170  */
10171 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
10172 
10173 #define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
10174 #define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
10175 /*! AOCSC - AOCSC
10176  *  0b0000..bit clock 0
10177  *  0b0001..bit clock 1
10178  *  0b0010..bit clock 2
10179  *  0b0011..bit clock 3
10180  *  0b0100..bit clock 4
10181  *  0b0101..bit clock 5
10182  *  0b0110..bit clock 6
10183  *  0b0111..bit clock 7
10184  *  0b1000..bit clock 8
10185  *  0b1001..bit clock 9
10186  *  0b1010..bit clock A
10187  *  0b1011..bit clock B
10188  *  0b1100..bit clock C
10189  *  0b1101..bit clock D
10190  *  0b1110..bit clock E
10191  *  0b1111..clock disabled, connected to zero
10192  */
10193 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
10194 /*! @} */
10195 
10196 /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
10197 /*! @{ */
10198 
10199 #define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
10200 #define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
10201 /*! AICPA - AICPA
10202  */
10203 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
10204 
10205 #define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
10206 #define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
10207 /*! AICDA - AICDA
10208  */
10209 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
10210 
10211 #define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
10212 #define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
10213 /*! AICPB - AICPB
10214  */
10215 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
10216 
10217 #define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
10218 #define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
10219 /*! AICDB - AICDB
10220  */
10221 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
10222 
10223 #define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
10224 #define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
10225 /*! AOCPA - AOCPA
10226  */
10227 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
10228 
10229 #define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
10230 #define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
10231 /*! AOCDA - AOCDA
10232  */
10233 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
10234 
10235 #define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
10236 #define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
10237 /*! AOCPB - AOCPB
10238  */
10239 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
10240 
10241 #define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
10242 #define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
10243 /*! AOCDB - AOCDB
10244  */
10245 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
10246 /*! @} */
10247 
10248 /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
10249 /*! @{ */
10250 
10251 #define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
10252 #define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
10253 /*! AICPC - AICPC
10254  */
10255 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
10256 
10257 #define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
10258 #define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
10259 /*! AICDC - AICDC
10260  */
10261 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
10262 
10263 #define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
10264 #define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
10265 /*! AOCPC - AOCPC
10266  */
10267 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
10268 
10269 #define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
10270 #define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
10271 /*! AOCDC - AOCDC
10272  */
10273 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
10274 /*! @} */
10275 
10276 /*! @name ASRSTR - ASRC Status Register */
10277 /*! @{ */
10278 
10279 #define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
10280 #define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
10281 /*! AIDEA - AIDEA
10282  *  0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1
10283  *  0b0..The threshold has been met and no data input A interrupt is generated
10284  */
10285 #define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
10286 
10287 #define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
10288 #define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
10289 /*! AIDEB - AIDEB
10290  *  0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1
10291  *  0b0..The threshold has been met and no data input B interrupt is generated
10292  */
10293 #define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
10294 
10295 #define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
10296 #define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
10297 /*! AIDEC - AIDEC
10298  *  0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1
10299  *  0b0..The threshold has been met and no data input C interrupt is generated
10300  */
10301 #define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
10302 
10303 #define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
10304 #define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
10305 /*! AODFA - AODFA
10306  *  0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1
10307  *  0b0..The threshold has not yet been met and no data output A interrupt is generated
10308  */
10309 #define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
10310 
10311 #define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
10312 #define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
10313 /*! AODFB - AODFB
10314  *  0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1
10315  *  0b0..The threshold has not yet been met and no data output B interrupt is generated
10316  */
10317 #define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
10318 
10319 #define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
10320 #define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
10321 /*! AODFC - AODFC
10322  *  0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1
10323  *  0b0..The threshold has not yet been met and no data output C interrupt is generated
10324  */
10325 #define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
10326 
10327 #define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
10328 #define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
10329 /*! AOLE - AOLE
10330  *  0b1..Task rate is too high
10331  *  0b0..No overload
10332  */
10333 #define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
10334 
10335 #define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
10336 #define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
10337 /*! FPWT - FPWT
10338  *  0b0..ASRC is not in wait state
10339  *  0b1..ASRC is in wait state
10340  */
10341 #define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
10342 
10343 #define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
10344 #define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
10345 /*! AIDUA - AIDUA
10346  *  0b0..No Underflow in Input data buffer A
10347  *  0b1..Underflow in Input data buffer A
10348  */
10349 #define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
10350 
10351 #define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
10352 #define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
10353 /*! AIDUB - AIDUB
10354  *  0b0..No Underflow in Input data buffer B
10355  *  0b1..Underflow in Input data buffer B
10356  */
10357 #define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
10358 
10359 #define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
10360 #define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
10361 /*! AIDUC - AIDUC
10362  *  0b0..No Underflow in Input data buffer C
10363  *  0b1..Underflow in Input data buffer C
10364  */
10365 #define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
10366 
10367 #define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
10368 #define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
10369 /*! AODOA - AODOA
10370  *  0b0..No Overflow in Output data buffer A
10371  *  0b1..Overflow in Output data buffer A
10372  */
10373 #define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
10374 
10375 #define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
10376 #define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
10377 /*! AODOB - AODOB
10378  *  0b0..No Overflow in Output data buffer B
10379  *  0b1..Overflow in Output data buffer B
10380  */
10381 #define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
10382 
10383 #define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
10384 #define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
10385 /*! AODOC - AODOC
10386  *  0b0..No Overflow in Output data buffer C
10387  *  0b1..Overflow in Output data buffer C
10388  */
10389 #define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
10390 
10391 #define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
10392 #define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
10393 /*! AIOLA - AIOLA
10394  *  0b0..Pair A input task is not oveloaded
10395  *  0b1..Pair A input task is oveloaded
10396  */
10397 #define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
10398 
10399 #define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
10400 #define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
10401 /*! AIOLB - AIOLB
10402  *  0b0..Pair B input task is not oveloaded
10403  *  0b1..Pair B input task is oveloaded
10404  */
10405 #define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
10406 
10407 #define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
10408 #define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
10409 /*! AIOLC - AIOLC
10410  *  0b0..Pair C input task is not oveloaded
10411  *  0b1..Pair C input task is oveloaded
10412  */
10413 #define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
10414 
10415 #define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
10416 #define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
10417 /*! AOOLA - AOOLA
10418  *  0b0..Pair A output task is not oveloaded
10419  *  0b1..Pair A output task is oveloaded
10420  */
10421 #define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
10422 
10423 #define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
10424 #define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
10425 /*! AOOLB - AOOLB
10426  *  0b0..Pair B output task is not oveloaded
10427  *  0b1..Pair B output task is oveloaded
10428  */
10429 #define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
10430 
10431 #define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
10432 #define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
10433 /*! AOOLC - AOOLC
10434  *  0b0..Pair C output task is not oveloaded
10435  *  0b1..Pair C output task is oveloaded
10436  */
10437 #define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
10438 
10439 #define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
10440 #define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
10441 /*! ATQOL - ATQOL
10442  *  0b0..Task queue FIFO logic is not oveloaded
10443  *  0b1..Task queue FIFO logic is oveloaded
10444  */
10445 #define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
10446 
10447 #define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
10448 #define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
10449 /*! DSLCNT - DSLCNT
10450  *  0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO
10451  *  0b1..New DSL counter information is stored in the internal ASRC FIFO
10452  */
10453 #define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
10454 /*! @} */
10455 
10456 /*! @name ASRPM - ASRC Parameter Register n */
10457 /*! @{ */
10458 
10459 #define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
10460 #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
10461 /*! PARAMETER_VALUE - PARAMETER_VALUE
10462  */
10463 #define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
10464 /*! @} */
10465 
10466 /* The count of ASRC_ASRPM */
10467 #define ASRC_ASRPM_COUNT                         (5U)
10468 
10469 /*! @name ASRTFR1 - ASRC Task Queue FIFO Register 1 */
10470 /*! @{ */
10471 
10472 #define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
10473 #define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
10474 /*! TF_BASE - TF_BASE
10475  */
10476 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
10477 
10478 #define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
10479 #define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
10480 /*! TF_FILL - TF_FILL
10481  */
10482 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
10483 /*! @} */
10484 
10485 /*! @name ASRCCR - ASRC Channel Counter Register */
10486 /*! @{ */
10487 
10488 #define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
10489 #define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
10490 /*! ACIA - ACIA
10491  */
10492 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
10493 
10494 #define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
10495 #define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
10496 /*! ACIB - ACIB
10497  */
10498 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
10499 
10500 #define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
10501 #define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
10502 /*! ACIC - ACIC
10503  */
10504 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
10505 
10506 #define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
10507 #define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
10508 /*! ACOA - ACOA
10509  */
10510 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
10511 
10512 #define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
10513 #define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
10514 /*! ACOB - ACOB
10515  */
10516 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
10517 
10518 #define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
10519 #define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
10520 /*! ACOC - ACOC
10521  */
10522 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
10523 /*! @} */
10524 
10525 /*! @name ASRDIA - ASRC Data Input Register for Pair x */
10526 /*! @{ */
10527 
10528 #define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
10529 #define ASRC_ASRDIA_DATA_SHIFT                   (0U)
10530 /*! DATA - DATA
10531  */
10532 #define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
10533 /*! @} */
10534 
10535 /*! @name ASRDOA - ASRC Data Output Register for Pair x */
10536 /*! @{ */
10537 
10538 #define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
10539 #define ASRC_ASRDOA_DATA_SHIFT                   (0U)
10540 /*! DATA - DATA
10541  */
10542 #define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
10543 /*! @} */
10544 
10545 /*! @name ASRDIB - ASRC Data Input Register for Pair x */
10546 /*! @{ */
10547 
10548 #define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
10549 #define ASRC_ASRDIB_DATA_SHIFT                   (0U)
10550 /*! DATA - DATA
10551  */
10552 #define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
10553 /*! @} */
10554 
10555 /*! @name ASRDOB - ASRC Data Output Register for Pair x */
10556 /*! @{ */
10557 
10558 #define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
10559 #define ASRC_ASRDOB_DATA_SHIFT                   (0U)
10560 /*! DATA - DATA
10561  */
10562 #define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
10563 /*! @} */
10564 
10565 /*! @name ASRDIC - ASRC Data Input Register for Pair x */
10566 /*! @{ */
10567 
10568 #define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
10569 #define ASRC_ASRDIC_DATA_SHIFT                   (0U)
10570 /*! DATA - DATA
10571  */
10572 #define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
10573 /*! @} */
10574 
10575 /*! @name ASRDOC - ASRC Data Output Register for Pair x */
10576 /*! @{ */
10577 
10578 #define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
10579 #define ASRC_ASRDOC_DATA_SHIFT                   (0U)
10580 /*! DATA - DATA
10581  */
10582 #define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
10583 /*! @} */
10584 
10585 /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
10586 /*! @{ */
10587 
10588 #define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
10589 #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
10590 /*! IDRATIOA_H - IDRATIOA_H
10591  */
10592 #define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
10593 /*! @} */
10594 
10595 /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
10596 /*! @{ */
10597 
10598 #define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
10599 #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
10600 /*! IDRATIOA_L - IDRATIOA_L
10601  */
10602 #define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
10603 /*! @} */
10604 
10605 /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
10606 /*! @{ */
10607 
10608 #define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
10609 #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
10610 /*! IDRATIOB_H - IDRATIOB_H
10611  */
10612 #define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
10613 /*! @} */
10614 
10615 /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
10616 /*! @{ */
10617 
10618 #define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
10619 #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
10620 /*! IDRATIOB_L - IDRATIOB_L
10621  */
10622 #define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
10623 /*! @} */
10624 
10625 /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
10626 /*! @{ */
10627 
10628 #define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
10629 #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
10630 /*! IDRATIOC_H - IDRATIOC_H
10631  */
10632 #define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
10633 /*! @} */
10634 
10635 /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
10636 /*! @{ */
10637 
10638 #define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
10639 #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
10640 /*! IDRATIOC_L - IDRATIOC_L
10641  */
10642 #define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
10643 /*! @} */
10644 
10645 /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
10646 /*! @{ */
10647 
10648 #define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
10649 #define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
10650 /*! ASR76K - ASR76K
10651  */
10652 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
10653 /*! @} */
10654 
10655 /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
10656 /*! @{ */
10657 
10658 #define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
10659 #define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
10660 /*! ASR56K - ASR56K
10661  */
10662 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
10663 /*! @} */
10664 
10665 /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
10666 /*! @{ */
10667 
10668 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
10669 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
10670 /*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
10671  */
10672 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
10673 
10674 #define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
10675 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
10676 /*! RSYNOFA - RSYNOFA
10677  *  0b1..Force ASRCCR[ACOA]=0
10678  *  0b0..Do not touch ASRCCR[ACOA]
10679  */
10680 #define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
10681 
10682 #define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
10683 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
10684 /*! RSYNIFA - RSYNIFA
10685  *  0b1..Force ASRCCR[ACIA]=0
10686  *  0b0..Do not touch ASRCCR[ACIA]
10687  */
10688 #define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
10689 
10690 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
10691 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
10692 /*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
10693  */
10694 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
10695 
10696 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
10697 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
10698 /*! BYPASSPOLYA - BYPASSPOLYA
10699  *  0b1..Bypass polyphase filtering.
10700  *  0b0..Don't bypass polyphase filtering.
10701  */
10702 #define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
10703 
10704 #define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
10705 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
10706 /*! BUFSTALLA - BUFSTALLA
10707  *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
10708  *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
10709  */
10710 #define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
10711 
10712 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
10713 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
10714 /*! EXTTHRSHA - EXTTHRSHA
10715  *  0b1..Use external defined thresholds.
10716  *  0b0..Use default thresholds.
10717  */
10718 #define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
10719 
10720 #define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
10721 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
10722 /*! ZEROBUFA - ZEROBUFA
10723  *  0b1..Don't zeroize the buffer
10724  *  0b0..Zeroize the buffer
10725  */
10726 #define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
10727 /*! @} */
10728 
10729 /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
10730 /*! @{ */
10731 
10732 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
10733 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
10734 /*! INFIFO_FILLA - INFIFO_FILLA
10735  */
10736 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
10737 
10738 #define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
10739 #define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
10740 /*! IAEA - IAEA
10741  *  0b1..Input FIFO is near empty for Pair A
10742  *  0b0..Input FIFO is not near empty for Pair A
10743  */
10744 #define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
10745 
10746 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
10747 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
10748 /*! OUTFIFO_FILLA - OUTFIFO_FILLA
10749  */
10750 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
10751 
10752 #define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
10753 #define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
10754 /*! OAFA - OAFA
10755  *  0b1..Output FIFO is near full for Pair A
10756  *  0b0..Output FIFO is not near full for Pair A
10757  */
10758 #define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
10759 /*! @} */
10760 
10761 /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
10762 /*! @{ */
10763 
10764 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
10765 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
10766 /*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
10767  */
10768 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
10769 
10770 #define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
10771 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
10772 /*! RSYNOFB - RSYNOFB
10773  *  0b1..Force ASRCCR[ACOB]=0
10774  *  0b0..Do not touch ASRCCR[ACOB]
10775  */
10776 #define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
10777 
10778 #define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
10779 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
10780 /*! RSYNIFB - RSYNIFB
10781  *  0b1..Force ASRCCR[ACIB]=0
10782  *  0b0..Do not touch ASRCCR[ACIB]
10783  */
10784 #define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
10785 
10786 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
10787 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
10788 /*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
10789  */
10790 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
10791 
10792 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
10793 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
10794 /*! BYPASSPOLYB - BYPASSPOLYB
10795  *  0b1..Bypass polyphase filtering.
10796  *  0b0..Don't bypass polyphase filtering.
10797  */
10798 #define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
10799 
10800 #define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
10801 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
10802 /*! BUFSTALLB - BUFSTALLB
10803  *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
10804  *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
10805  */
10806 #define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
10807 
10808 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
10809 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
10810 /*! EXTTHRSHB - EXTTHRSHB
10811  *  0b1..Use external defined thresholds.
10812  *  0b0..Use default thresholds.
10813  */
10814 #define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
10815 
10816 #define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
10817 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
10818 /*! ZEROBUFB - ZEROBUFB
10819  *  0b1..Don't zeroize the buffer
10820  *  0b0..Zeroize the buffer
10821  */
10822 #define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
10823 /*! @} */
10824 
10825 /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
10826 /*! @{ */
10827 
10828 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
10829 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
10830 /*! INFIFO_FILLB - INFIFO_FILLB
10831  */
10832 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
10833 
10834 #define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
10835 #define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
10836 /*! IAEB - IAEB
10837  *  0b1..Input FIFO is near empty for Pair B
10838  *  0b0..Input FIFO is not near empty for Pair B
10839  */
10840 #define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
10841 
10842 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
10843 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
10844 /*! OUTFIFO_FILLB - OUTFIFO_FILLB
10845  */
10846 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
10847 
10848 #define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
10849 #define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
10850 /*! OAFB - OAFB
10851  *  0b1..Output FIFO is near full for Pair B
10852  *  0b0..Output FIFO is not near full for Pair B
10853  */
10854 #define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
10855 /*! @} */
10856 
10857 /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
10858 /*! @{ */
10859 
10860 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
10861 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
10862 /*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
10863  */
10864 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
10865 
10866 #define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
10867 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
10868 /*! RSYNOFC - RSYNOFC
10869  *  0b1..Force ASRCCR[ACOC]=0
10870  *  0b0..Do not touch ASRCCR[ACOC]
10871  */
10872 #define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
10873 
10874 #define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
10875 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
10876 /*! RSYNIFC - RSYNIFC
10877  *  0b1..Force ASRCCR[ACIC]=0
10878  *  0b0..Do not touch ASRCCR[ACIC]
10879  */
10880 #define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
10881 
10882 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
10883 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
10884 /*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
10885  */
10886 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
10887 
10888 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
10889 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
10890 /*! BYPASSPOLYC - BYPASSPOLYC
10891  *  0b1..Bypass polyphase filtering.
10892  *  0b0..Don't bypass polyphase filtering.
10893  */
10894 #define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
10895 
10896 #define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
10897 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
10898 /*! BUFSTALLC - BUFSTALLC
10899  *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
10900  *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
10901  */
10902 #define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
10903 
10904 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
10905 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
10906 /*! EXTTHRSHC - EXTTHRSHC
10907  *  0b1..Use external defined thresholds.
10908  *  0b0..Use default thresholds.
10909  */
10910 #define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
10911 
10912 #define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
10913 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
10914 /*! ZEROBUFC - ZEROBUFC
10915  *  0b1..Don't zeroize the buffer
10916  *  0b0..Zeroize the buffer
10917  */
10918 #define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
10919 /*! @} */
10920 
10921 /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
10922 /*! @{ */
10923 
10924 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
10925 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
10926 /*! INFIFO_FILLC - INFIFO_FILLC
10927  */
10928 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
10929 
10930 #define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
10931 #define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
10932 /*! IAEC - IAEC
10933  *  0b1..Input FIFO is near empty for Pair C
10934  *  0b0..Input FIFO is not near empty for Pair C
10935  */
10936 #define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
10937 
10938 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
10939 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
10940 /*! OUTFIFO_FILLC - OUTFIFO_FILLC
10941  */
10942 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
10943 
10944 #define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
10945 #define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
10946 /*! OAFC - OAFC
10947  *  0b1..Output FIFO is near full for Pair C
10948  *  0b0..Output FIFO is not near full for Pair C
10949  */
10950 #define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
10951 /*! @} */
10952 
10953 /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
10954 /*! @{ */
10955 
10956 #define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
10957 #define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
10958 /*! OW16 - OW16
10959  *  0b1..16-bit output data
10960  *  0b0..24-bit output data.
10961  */
10962 #define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
10963 
10964 #define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
10965 #define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
10966 /*! OSGN - OSGN
10967  *  0b1..Sign extension.
10968  *  0b0..No sign extension.
10969  */
10970 #define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
10971 
10972 #define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
10973 #define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
10974 /*! OMSB - OMSB
10975  *  0b1..MSB aligned.
10976  *  0b0..LSB aligned.
10977  */
10978 #define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
10979 
10980 #define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
10981 #define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
10982 /*! IMSB - IMSB
10983  *  0b1..MSB aligned.
10984  *  0b0..LSB aligned.
10985  */
10986 #define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
10987 
10988 #define ASRC_ASRMCR1_IWD_MASK                    (0x600U)
10989 #define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
10990 /*! IWD - IWD
10991  *  0b00..24-bit audio data.
10992  *  0b01..16-bit audio data.
10993  *  0b10..8-bit audio data.
10994  *  0b11..Reserved.
10995  */
10996 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
10997 /*! @} */
10998 
10999 /* The count of ASRC_ASRMCR1 */
11000 #define ASRC_ASRMCR1_COUNT                       (3U)
11001 
11002 
11003 /*!
11004  * @}
11005  */ /* end of group ASRC_Register_Masks */
11006 
11007 
11008 /* ASRC - Peripheral instance base addresses */
11009 /** Peripheral ASRC base address */
11010 #define ASRC_BASE                                (0x40414000u)
11011 /** Peripheral ASRC base pointer */
11012 #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
11013 /** Array initializer of ASRC peripheral base addresses */
11014 #define ASRC_BASE_ADDRS                          { ASRC_BASE }
11015 /** Array initializer of ASRC peripheral base pointers */
11016 #define ASRC_BASE_PTRS                           { ASRC }
11017 /** Interrupt vectors for the ASRC peripheral type */
11018 #define ASRC_IRQS                                { ASRC_IRQn }
11019 
11020 /*!
11021  * @}
11022  */ /* end of group ASRC_Peripheral_Access_Layer */
11023 
11024 
11025 /* ----------------------------------------------------------------------------
11026    -- AUDIO_PLL Peripheral Access Layer
11027    ---------------------------------------------------------------------------- */
11028 
11029 /*!
11030  * @addtogroup AUDIO_PLL_Peripheral_Access_Layer AUDIO_PLL Peripheral Access Layer
11031  * @{
11032  */
11033 
11034 /** AUDIO_PLL - Register Layout Typedef */
11035 typedef struct {
11036   struct {                                         /* offset: 0x0 */
11037     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
11038     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
11039     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
11040     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
11041   } CTRL0;
11042   struct {                                         /* offset: 0x10 */
11043     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
11044     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
11045     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
11046     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
11047   } SPREAD_SPECTRUM;
11048   struct {                                         /* offset: 0x20 */
11049     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
11050     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
11051     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
11052     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
11053   } NUMERATOR;
11054   struct {                                         /* offset: 0x30 */
11055     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
11056     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
11057     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
11058     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
11059   } DENOMINATOR;
11060 } AUDIO_PLL_Type;
11061 
11062 /* ----------------------------------------------------------------------------
11063    -- AUDIO_PLL Register Masks
11064    ---------------------------------------------------------------------------- */
11065 
11066 /*!
11067  * @addtogroup AUDIO_PLL_Register_Masks AUDIO_PLL Register Masks
11068  * @{
11069  */
11070 
11071 /*! @name CTRL0 - Fractional PLL Control Register */
11072 /*! @{ */
11073 
11074 #define AUDIO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
11075 #define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
11076 /*! DIV_SELECT - DIV_SELECT
11077  */
11078 #define AUDIO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK)
11079 
11080 #define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
11081 #define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
11082 /*! ENABLE_ALT - ENABLE_ALT
11083  *  0b0..Disable the alternate clock output
11084  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
11085  */
11086 #define AUDIO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK)
11087 
11088 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
11089 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
11090 /*! HOLD_RING_OFF - PLL Start up initialization
11091  *  0b0..Normal operation
11092  *  0b1..Initialize PLL start up
11093  */
11094 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK)
11095 
11096 #define AUDIO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
11097 #define AUDIO_PLL_CTRL0_POWERUP_SHIFT            (14U)
11098 /*! POWERUP - POWERUP
11099  *  0b1..Power Up the PLL
11100  *  0b0..Power down the PLL
11101  */
11102 #define AUDIO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK)
11103 
11104 #define AUDIO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
11105 #define AUDIO_PLL_CTRL0_ENABLE_SHIFT             (15U)
11106 /*! ENABLE - ENABLE
11107  *  0b1..Enable the clock output
11108  *  0b0..Disable the clock output
11109  */
11110 #define AUDIO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK)
11111 
11112 #define AUDIO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
11113 #define AUDIO_PLL_CTRL0_BYPASS_SHIFT             (16U)
11114 /*! BYPASS - BYPASS
11115  *  0b1..Bypass the PLL
11116  *  0b0..No Bypass
11117  */
11118 #define AUDIO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK)
11119 
11120 #define AUDIO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
11121 #define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
11122 /*! DITHER_EN - DITHER_EN
11123  *  0b0..Disable Dither
11124  *  0b1..Enable Dither
11125  */
11126 #define AUDIO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK)
11127 
11128 #define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
11129 #define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
11130 /*! BIAS_TRIM - BIAS_TRIM
11131  */
11132 #define AUDIO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK)
11133 
11134 #define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
11135 #define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
11136 /*! PLL_REG_EN - PLL_REG_EN
11137  */
11138 #define AUDIO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK)
11139 
11140 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
11141 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
11142 /*! POST_DIV_SEL - Post Divide Select
11143  *  0b000..Divide by 1
11144  *  0b001..Divide by 2
11145  *  0b010..Divide by 4
11146  *  0b011..Divide by 8
11147  *  0b100..Divide by 16
11148  *  0b101..Divide by 32
11149  */
11150 #define AUDIO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
11151 
11152 #define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
11153 #define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
11154 /*! BIAS_SELECT - BIAS_SELECT
11155  *  0b0..Used in SoCs with a bias current of 10uA
11156  *  0b1..Used in SoCs with a bias current of 2uA
11157  */
11158 #define AUDIO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK)
11159 /*! @} */
11160 
11161 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
11162 /*! @{ */
11163 
11164 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
11165 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
11166 /*! STEP - Step
11167  */
11168 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK)
11169 
11170 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
11171 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
11172 /*! ENABLE - Enable
11173  */
11174 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
11175 
11176 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
11177 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
11178 /*! STOP - Stop
11179  */
11180 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK)
11181 /*! @} */
11182 
11183 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
11184 /*! @{ */
11185 
11186 #define AUDIO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
11187 #define AUDIO_PLL_NUMERATOR_NUM_SHIFT            (0U)
11188 /*! NUM - Numerator
11189  */
11190 #define AUDIO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK)
11191 /*! @} */
11192 
11193 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
11194 /*! @{ */
11195 
11196 #define AUDIO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
11197 #define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
11198 /*! DENOM - Denominator
11199  */
11200 #define AUDIO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK)
11201 /*! @} */
11202 
11203 
11204 /*!
11205  * @}
11206  */ /* end of group AUDIO_PLL_Register_Masks */
11207 
11208 
11209 /* AUDIO_PLL - Peripheral instance base addresses */
11210 /** Peripheral AUDIO_PLL base address */
11211 #define AUDIO_PLL_BASE                           (0u)
11212 /** Peripheral AUDIO_PLL base pointer */
11213 #define AUDIO_PLL                                ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
11214 /** Array initializer of AUDIO_PLL peripheral base addresses */
11215 #define AUDIO_PLL_BASE_ADDRS                     { AUDIO_PLL_BASE }
11216 /** Array initializer of AUDIO_PLL peripheral base pointers */
11217 #define AUDIO_PLL_BASE_PTRS                      { AUDIO_PLL }
11218 
11219 /*!
11220  * @}
11221  */ /* end of group AUDIO_PLL_Peripheral_Access_Layer */
11222 
11223 
11224 /* ----------------------------------------------------------------------------
11225    -- CAAM Peripheral Access Layer
11226    ---------------------------------------------------------------------------- */
11227 
11228 /*!
11229  * @addtogroup CAAM_Peripheral_Access_Layer CAAM Peripheral Access Layer
11230  * @{
11231  */
11232 
11233 /** CAAM - Register Layout Typedef */
11234 typedef struct {
11235        uint8_t RESERVED_0[4];
11236   __IO uint32_t MCFGR;                             /**< Master Configuration Register, offset: 0x4 */
11237   __IO uint32_t PAGE0_SDID;                        /**< Page 0 SDID Register, offset: 0x8 */
11238   __IO uint32_t SCFGR;                             /**< Security Configuration Register, offset: 0xC */
11239   struct {                                         /* offset: 0x10, array step: 0x8 */
11240     __IO uint32_t JRDID_MS;                          /**< Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8 */
11241     __IO uint32_t JRDID_LS;                          /**< Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8 */
11242   } JRADID[4];
11243        uint8_t RESERVED_1[40];
11244   __IO uint32_t DEBUGCTL;                          /**< Debug Control Register, offset: 0x58 */
11245   __IO uint32_t JRSTARTR;                          /**< Job Ring Start Register, offset: 0x5C */
11246   __IO uint32_t RTIC_OWN;                          /**< RTIC OWN Register, offset: 0x60 */
11247   struct {                                         /* offset: 0x64, array step: 0x8 */
11248     __IO uint32_t RTIC_DID;                          /**< RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8 */
11249          uint8_t RESERVED_0[4];
11250   } RTICADID[4];
11251        uint8_t RESERVED_2[16];
11252   __IO uint32_t DECORSR;                           /**< DECO Request Source Register, offset: 0x94 */
11253        uint8_t RESERVED_3[4];
11254   __IO uint32_t DECORR;                            /**< DECO Request Register, offset: 0x9C */
11255   struct {                                         /* offset: 0xA0, array step: 0x8 */
11256     __IO uint32_t DECODID_MS;                        /**< DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8 */
11257     __IO uint32_t DECODID_LS;                        /**< DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8 */
11258   } DECONDID[1];
11259        uint8_t RESERVED_4[120];
11260   __IO uint32_t DAR;                               /**< DECO Availability Register, offset: 0x120 */
11261   __O  uint32_t DRR;                               /**< DECO Reset Register, offset: 0x124 */
11262        uint8_t RESERVED_5[92];
11263   struct {                                         /* offset: 0x184, array step: 0x8 */
11264     __IO uint32_t JRSMVBAR;                          /**< Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8 */
11265          uint8_t RESERVED_0[4];
11266   } JRNSMVBAR[4];
11267        uint8_t RESERVED_6[124];
11268   __IO uint32_t PBSL;                              /**< Peak Bandwidth Smoothing Limit Register, offset: 0x220 */
11269        uint8_t RESERVED_7[28];
11270   struct {                                         /* offset: 0x240, array step: 0x10 */
11271     __I  uint32_t DMA_AIDL_MAP_MS;                   /**< DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10 */
11272     __I  uint32_t DMA_AIDL_MAP_LS;                   /**< DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10 */
11273     __I  uint32_t DMA_AIDM_MAP_MS;                   /**< DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10 */
11274     __I  uint32_t DMA_AIDM_MAP_LS;                   /**< DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10 */
11275   } AID_CNTS[1];
11276   __I  uint32_t DMA0_AID_ENB;                      /**< DMA0 AXI ID Enable Register, offset: 0x250 */
11277        uint8_t RESERVED_8[12];
11278   __IO uint64_t DMA0_ARD_TC;                       /**< DMA0 AXI Read Timing Check Register, offset: 0x260 */
11279        uint8_t RESERVED_9[4];
11280   __IO uint32_t DMA0_ARD_LAT;                      /**< DMA0 Read Timing Check Latency Register, offset: 0x26C */
11281   __IO uint64_t DMA0_AWR_TC;                       /**< DMA0 AXI Write Timing Check Register, offset: 0x270 */
11282        uint8_t RESERVED_10[4];
11283   __IO uint32_t DMA0_AWR_LAT;                      /**< DMA0 Write Timing Check Latency Register, offset: 0x27C */
11284        uint8_t RESERVED_11[128];
11285   __IO uint8_t MPPKR[64];                          /**< Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1 */
11286        uint8_t RESERVED_12[64];
11287   __IO uint8_t MPMR[32];                           /**< Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1 */
11288        uint8_t RESERVED_13[32];
11289   __I  uint8_t MPTESTR[32];                        /**< Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1 */
11290        uint8_t RESERVED_14[24];
11291   __I  uint32_t MPECC;                             /**< Manufacturing Protection ECC Register, offset: 0x3F8 */
11292        uint8_t RESERVED_15[4];
11293   __IO uint32_t JDKEKR[8];                         /**< Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4 */
11294   __IO uint32_t TDKEKR[8];                         /**< Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4 */
11295   __IO uint32_t TDSKR[8];                          /**< Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4 */
11296        uint8_t RESERVED_16[128];
11297   __IO uint64_t SKNR;                              /**< Secure Key Nonce Register, offset: 0x4E0 */
11298        uint8_t RESERVED_17[36];
11299   __I  uint32_t DMA_STA;                           /**< DMA Status Register, offset: 0x50C */
11300   __I  uint32_t DMA_X_AID_7_4_MAP;                 /**< DMA_X_AID_7_4_MAP, offset: 0x510 */
11301   __I  uint32_t DMA_X_AID_3_0_MAP;                 /**< DMA_X_AID_3_0_MAP, offset: 0x514 */
11302   __I  uint32_t DMA_X_AID_15_12_MAP;               /**< DMA_X_AID_15_12_MAP, offset: 0x518 */
11303   __I  uint32_t DMA_X_AID_11_8_MAP;                /**< DMA_X_AID_11_8_MAP, offset: 0x51C */
11304        uint8_t RESERVED_18[4];
11305   __I  uint32_t DMA_X_AID_15_0_EN;                 /**< DMA_X AXI ID Map Enable Register, offset: 0x524 */
11306        uint8_t RESERVED_19[8];
11307   __IO uint32_t DMA_X_ARTC_CTL;                    /**< DMA_X AXI Read Timing Check Control Register, offset: 0x530 */
11308   __IO uint32_t DMA_X_ARTC_LC;                     /**< DMA_X AXI Read Timing Check Late Count Register, offset: 0x534 */
11309   __IO uint32_t DMA_X_ARTC_SC;                     /**< DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538 */
11310   __IO uint32_t DMA_X_ARTC_LAT;                    /**< DMA_X Read Timing Check Latency Register, offset: 0x53C */
11311   __IO uint32_t DMA_X_AWTC_CTL;                    /**< DMA_X AXI Write Timing Check Control Register, offset: 0x540 */
11312   __IO uint32_t DMA_X_AWTC_LC;                     /**< DMA_X AXI Write Timing Check Late Count Register, offset: 0x544 */
11313   __IO uint32_t DMA_X_AWTC_SC;                     /**< DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548 */
11314   __IO uint32_t DMA_X_AWTC_LAT;                    /**< DMA_X Write Timing Check Latency Register, offset: 0x54C */
11315        uint8_t RESERVED_20[176];
11316   __IO uint32_t RTMCTL;                            /**< RNG TRNG Miscellaneous Control Register, offset: 0x600 */
11317   __IO uint32_t RTSCMISC;                          /**< RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604 */
11318   __IO uint32_t RTPKRRNG;                          /**< RNG TRNG Poker Range Register, offset: 0x608 */
11319   union {                                          /* offset: 0x60C */
11320     __IO uint32_t RTPKRMAX;                          /**< RNG TRNG Poker Maximum Limit Register, offset: 0x60C */
11321     __I  uint32_t RTPKRSQ;                           /**< RNG TRNG Poker Square Calculation Result Register, offset: 0x60C */
11322   };
11323   __IO uint32_t RTSDCTL;                           /**< RNG TRNG Seed Control Register, offset: 0x610 */
11324   union {                                          /* offset: 0x614 */
11325     __IO uint32_t RTSBLIM;                           /**< RNG TRNG Sparse Bit Limit Register, offset: 0x614 */
11326     __I  uint32_t RTTOTSAM;                          /**< RNG TRNG Total Samples Register, offset: 0x614 */
11327   };
11328   __IO uint32_t RTFRQMIN;                          /**< RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618 */
11329   union {                                          /* offset: 0x61C */
11330     struct {                                         /* offset: 0x61C */
11331       __I  uint32_t RTFRQCNT;                          /**< RNG TRNG Frequency Count Register, offset: 0x61C */
11332       __I  uint32_t RTSCMC;                            /**< RNG TRNG Statistical Check Monobit Count Register, offset: 0x620 */
11333       __I  uint32_t RTSCR1C;                           /**< RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624 */
11334       __I  uint32_t RTSCR2C;                           /**< RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628 */
11335       __I  uint32_t RTSCR3C;                           /**< RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C */
11336       __I  uint32_t RTSCR4C;                           /**< RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630 */
11337       __I  uint32_t RTSCR5C;                           /**< RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634 */
11338       __I  uint32_t RTSCR6PC;                          /**< RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638 */
11339     } COUNT;
11340     struct {                                         /* offset: 0x61C */
11341       __IO uint32_t RTFRQMAX;                          /**< RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C */
11342       __IO uint32_t RTSCML;                            /**< RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620 */
11343       __IO uint32_t RTSCR1L;                           /**< RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624 */
11344       __IO uint32_t RTSCR2L;                           /**< RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628 */
11345       __IO uint32_t RTSCR3L;                           /**< RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C */
11346       __IO uint32_t RTSCR4L;                           /**< RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630 */
11347       __IO uint32_t RTSCR5L;                           /**< RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634 */
11348       __IO uint32_t RTSCR6PL;                          /**< RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638 */
11349     } LIMIT;
11350   };
11351   __I  uint32_t RTSTATUS;                          /**< RNG TRNG Status Register, offset: 0x63C */
11352   __I  uint32_t RTENT[16];                         /**< RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4 */
11353   __I  uint32_t RTPKRCNT10;                        /**< RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680 */
11354   __I  uint32_t RTPKRCNT32;                        /**< RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684 */
11355   __I  uint32_t RTPKRCNT54;                        /**< RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688 */
11356   __I  uint32_t RTPKRCNT76;                        /**< RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C */
11357   __I  uint32_t RTPKRCNT98;                        /**< RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690 */
11358   __I  uint32_t RTPKRCNTBA;                        /**< RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694 */
11359   __I  uint32_t RTPKRCNTDC;                        /**< RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698 */
11360   __I  uint32_t RTPKRCNTFE;                        /**< RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C */
11361        uint8_t RESERVED_21[32];
11362   __I  uint32_t RDSTA;                             /**< RNG DRNG Status Register, offset: 0x6C0 */
11363        uint8_t RESERVED_22[12];
11364   __I  uint32_t RDINT0;                            /**< RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0 */
11365   __I  uint32_t RDINT1;                            /**< RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4 */
11366        uint8_t RESERVED_23[8];
11367   __IO uint32_t RDHCNTL;                           /**< RNG DRNG Hash Control Register, offset: 0x6E0 */
11368   __I  uint32_t RDHDIG;                            /**< RNG DRNG Hash Digest Register, offset: 0x6E4 */
11369   __O  uint32_t RDHBUF;                            /**< RNG DRNG Hash Buffer Register, offset: 0x6E8 */
11370        uint8_t RESERVED_24[788];
11371   struct {                                         /* offset: 0xA00, array step: 0x10 */
11372     __I  uint32_t PX_SDID_PG0;                       /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */
11373     __IO uint32_t PX_SMAPR_PG0;                      /**< Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10 */
11374     __IO uint32_t PX_SMAG2_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10 */
11375     __IO uint32_t PX_SMAG1_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10 */
11376   } PX_PG0[16];
11377   __IO uint32_t REIS;                              /**< Recoverable Error Interrupt Status, offset: 0xB00 */
11378   __IO uint32_t REIE;                              /**< Recoverable Error Interrupt Enable, offset: 0xB04 */
11379   __I  uint32_t REIF;                              /**< Recoverable Error Interrupt Force, offset: 0xB08 */
11380   __IO uint32_t REIH;                              /**< Recoverable Error Interrupt Halt, offset: 0xB0C */
11381        uint8_t RESERVED_25[192];
11382   __IO uint32_t SMWPJRR[4];                        /**< Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4 */
11383        uint8_t RESERVED_26[4];
11384   __O  uint32_t SMCR_PG0;                          /**< Secure Memory Command Register, offset: 0xBE4 */
11385        uint8_t RESERVED_27[4];
11386   __I  uint32_t SMCSR_PG0;                         /**< Secure Memory Command Status Register, offset: 0xBEC */
11387        uint8_t RESERVED_28[8];
11388   __I  uint32_t CAAMVID_MS_TRAD;                   /**< CAAM Version ID Register, most-significant half, offset: 0xBF8 */
11389   __I  uint32_t CAAMVID_LS_TRAD;                   /**< CAAM Version ID Register, least-significant half, offset: 0xBFC */
11390   struct {                                         /* offset: 0xC00, array step: 0x20 */
11391     __I  uint64_t HT_JD_ADDR;                        /**< Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20 */
11392     __I  uint64_t HT_SD_ADDR;                        /**< Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20 */
11393     __I  uint32_t HT_JQ_CTRL_MS;                     /**< Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20 */
11394     __I  uint32_t HT_JQ_CTRL_LS;                     /**< Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20 */
11395          uint8_t RESERVED_0[4];
11396     __I  uint32_t HT_STATUS;                         /**< Holding Tank Status, array offset: 0xC1C, array step: 0x20 */
11397   } HTA[1];
11398        uint8_t RESERVED_29[4];
11399   __IO uint32_t JQ_DEBUG_SEL;                      /**< Job Queue Debug Select Register, offset: 0xC24 */
11400        uint8_t RESERVED_30[404];
11401   __I  uint32_t JRJIDU_LS;                         /**< Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC */
11402   __I  uint32_t JRJDJIFBC;                         /**< Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0 */
11403   __I  uint32_t JRJDJIF;                           /**< Job Ring Job-Done Job ID FIFO, offset: 0xDC4 */
11404        uint8_t RESERVED_31[28];
11405   __I  uint32_t JRJDS1;                            /**< Job Ring Job-Done Source 1, offset: 0xDE4 */
11406        uint8_t RESERVED_32[24];
11407   __I  uint64_t JRJDDA[1];                         /**< Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8 */
11408        uint8_t RESERVED_33[408];
11409   __I  uint32_t CRNR_MS;                           /**< CHA Revision Number Register, most-significant half, offset: 0xFA0 */
11410   __I  uint32_t CRNR_LS;                           /**< CHA Revision Number Register, least-significant half, offset: 0xFA4 */
11411   __I  uint32_t CTPR_MS;                           /**< Compile Time Parameters Register, most-significant half, offset: 0xFA8 */
11412   __I  uint32_t CTPR_LS;                           /**< Compile Time Parameters Register, least-significant half, offset: 0xFAC */
11413        uint8_t RESERVED_34[4];
11414   __I  uint32_t SMSTA;                             /**< Secure Memory Status Register, offset: 0xFB4 */
11415        uint8_t RESERVED_35[4];
11416   __I  uint32_t SMPO;                              /**< Secure Memory Partition Owners Register, offset: 0xFBC */
11417   __I  uint64_t FAR;                               /**< Fault Address Register, offset: 0xFC0 */
11418   __I  uint32_t FADID;                             /**< Fault Address DID Register, offset: 0xFC8 */
11419   __I  uint32_t FADR;                              /**< Fault Address Detail Register, offset: 0xFCC */
11420        uint8_t RESERVED_36[4];
11421   __I  uint32_t CSTA;                              /**< CAAM Status Register, offset: 0xFD4 */
11422   __I  uint32_t SMVID_MS;                          /**< Secure Memory Version ID Register, most-significant half, offset: 0xFD8 */
11423   __I  uint32_t SMVID_LS;                          /**< Secure Memory Version ID Register, least-significant half, offset: 0xFDC */
11424   __I  uint32_t RVID;                              /**< RTIC Version ID Register, offset: 0xFE0 */
11425   __I  uint32_t CCBVID;                            /**< CHA Cluster Block Version ID Register, offset: 0xFE4 */
11426   __I  uint32_t CHAVID_MS;                         /**< CHA Version ID Register, most-significant half, offset: 0xFE8 */
11427   __I  uint32_t CHAVID_LS;                         /**< CHA Version ID Register, least-significant half, offset: 0xFEC */
11428   __I  uint32_t CHANUM_MS;                         /**< CHA Number Register, most-significant half, offset: 0xFF0 */
11429   __I  uint32_t CHANUM_LS;                         /**< CHA Number Register, least-significant half, offset: 0xFF4 */
11430   __I  uint32_t CAAMVID_MS;                        /**< CAAM Version ID Register, most-significant half, offset: 0xFF8 */
11431   __I  uint32_t CAAMVID_LS;                        /**< CAAM Version ID Register, least-significant half, offset: 0xFFC */
11432        uint8_t RESERVED_37[61440];
11433   struct {                                         /* offset: 0x10000, array step: 0x10000 */
11434     __IO uint64_t IRBAR_JR;                          /**< Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000 */
11435          uint8_t RESERVED_0[4];
11436     __IO uint32_t IRSR_JR;                           /**< Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000 */
11437          uint8_t RESERVED_1[4];
11438     __IO uint32_t IRSAR_JR;                          /**< Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000 */
11439          uint8_t RESERVED_2[4];
11440     __IO uint32_t IRJAR_JR;                          /**< Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000 */
11441     __IO uint64_t ORBAR_JR;                          /**< Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000 */
11442          uint8_t RESERVED_3[4];
11443     __IO uint32_t ORSR_JR;                           /**< Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000 */
11444          uint8_t RESERVED_4[4];
11445     __IO uint32_t ORJRR_JR;                          /**< Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000 */
11446          uint8_t RESERVED_5[4];
11447     __IO uint32_t ORSFR_JR;                          /**< Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000 */
11448          uint8_t RESERVED_6[4];
11449     __I  uint32_t JRSTAR_JR;                         /**< Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000 */
11450          uint8_t RESERVED_7[4];
11451     __IO uint32_t JRINTR_JR;                         /**< Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000 */
11452     __IO uint32_t JRCFGR_JR_MS;                      /**< Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000 */
11453     __IO uint32_t JRCFGR_JR_LS;                      /**< Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000 */
11454          uint8_t RESERVED_8[4];
11455     __IO uint32_t IRRIR_JR;                          /**< Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000 */
11456          uint8_t RESERVED_9[4];
11457     __IO uint32_t ORWIR_JR;                          /**< Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000 */
11458          uint8_t RESERVED_10[4];
11459     __O  uint32_t JRCR_JR;                           /**< Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000 */
11460          uint8_t RESERVED_11[1684];
11461     __I  uint32_t JRAAV;                             /**< Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000 */
11462          uint8_t RESERVED_12[248];
11463     __I  uint64_t JRAAA[4];                          /**< Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8 */
11464          uint8_t RESERVED_13[480];
11465     struct {                                         /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11466       __I  uint32_t PX_SDID_JR;                        /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11467       __IO uint32_t PX_SMAPR_JR;                       /**< Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10 */
11468       __IO uint32_t PX_SMAG2_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10 */
11469       __IO uint32_t PX_SMAG1_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10 */
11470     } PX_JR[16];
11471          uint8_t RESERVED_14[228];
11472     __O  uint32_t SMCR_JR;                           /**< Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000 */
11473          uint8_t RESERVED_15[4];
11474     __I  uint32_t SMCSR_JR;                          /**< Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000 */
11475          uint8_t RESERVED_16[528];
11476     __I  uint32_t REIR0JR;                           /**< Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000 */
11477          uint8_t RESERVED_17[4];
11478     __I  uint64_t REIR2JR;                           /**< Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000 */
11479     __I  uint32_t REIR4JR;                           /**< Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000 */
11480     __I  uint32_t REIR5JR;                           /**< Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000 */
11481          uint8_t RESERVED_18[392];
11482     __I  uint32_t CRNR_MS_JR;                        /**< CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000 */
11483     __I  uint32_t CRNR_LS_JR;                        /**< CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000 */
11484     __I  uint32_t CTPR_MS_JR;                        /**< Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000 */
11485     __I  uint32_t CTPR_LS_JR;                        /**< Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000 */
11486          uint8_t RESERVED_19[4];
11487     __I  uint32_t SMSTA_JR;                          /**< Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000 */
11488          uint8_t RESERVED_20[4];
11489     __I  uint32_t SMPO_JR;                           /**< Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000 */
11490     __I  uint64_t FAR_JR;                            /**< Fault Address Register, array offset: 0x10FC0, array step: 0x10000 */
11491     __I  uint32_t FADID_JR;                          /**< Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000 */
11492     __I  uint32_t FADR_JR;                           /**< Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000 */
11493          uint8_t RESERVED_21[4];
11494     __I  uint32_t CSTA_JR;                           /**< CAAM Status Register, array offset: 0x10FD4, array step: 0x10000 */
11495     __I  uint32_t SMVID_MS_JR;                       /**< Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000 */
11496     __I  uint32_t SMVID_LS_JR;                       /**< Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000 */
11497     __I  uint32_t RVID_JR;                           /**< RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000 */
11498     __I  uint32_t CCBVID_JR;                         /**< CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000 */
11499     __I  uint32_t CHAVID_MS_JR;                      /**< CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000 */
11500     __I  uint32_t CHAVID_LS_JR;                      /**< CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000 */
11501     __I  uint32_t CHANUM_MS_JR;                      /**< CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000 */
11502     __I  uint32_t CHANUM_LS_JR;                      /**< CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000 */
11503     __I  uint32_t CAAMVID_MS_JR;                     /**< CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000 */
11504     __I  uint32_t CAAMVID_LS_JR;                     /**< CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000 */
11505          uint8_t RESERVED_22[61440];
11506   } JOBRING[4];
11507        uint8_t RESERVED_38[65540];
11508   __I  uint32_t RSTA;                              /**< RTIC Status Register, offset: 0x60004 */
11509        uint8_t RESERVED_39[4];
11510   __IO uint32_t RCMD;                              /**< RTIC Command Register, offset: 0x6000C */
11511        uint8_t RESERVED_40[4];
11512   __IO uint32_t RCTL;                              /**< RTIC Control Register, offset: 0x60014 */
11513        uint8_t RESERVED_41[4];
11514   __IO uint32_t RTHR;                              /**< RTIC Throttle Register, offset: 0x6001C */
11515        uint8_t RESERVED_42[8];
11516   __IO uint64_t RWDOG;                             /**< RTIC Watchdog Timer, offset: 0x60028 */
11517        uint8_t RESERVED_43[4];
11518   __IO uint32_t REND;                              /**< RTIC Endian Register, offset: 0x60034 */
11519        uint8_t RESERVED_44[200];
11520   struct {                                         /* offset: 0x60100, array step: index*0x20, index2*0x10 */
11521     __IO uint64_t RMA;                               /**< RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10 */
11522          uint8_t RESERVED_0[4];
11523     __IO uint32_t RML;                               /**< RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10 */
11524   } RM[4][2];
11525        uint8_t RESERVED_45[128];
11526   __IO uint32_t RMD[4][2][32];                     /**< RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4 */
11527        uint8_t RESERVED_46[2048];
11528   __I  uint32_t REIR0RTIC;                         /**< Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00 */
11529        uint8_t RESERVED_47[4];
11530   __I  uint64_t REIR2RTIC;                         /**< Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08 */
11531   __I  uint32_t REIR4RTIC;                         /**< Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10 */
11532   __I  uint32_t REIR5RTIC;                         /**< Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14 */
11533        uint8_t RESERVED_48[392];
11534   __I  uint32_t CRNR_MS_RTIC;                      /**< CHA Revision Number Register, most-significant half, offset: 0x60FA0 */
11535   __I  uint32_t CRNR_LS_RTIC;                      /**< CHA Revision Number Register, least-significant half, offset: 0x60FA4 */
11536   __I  uint32_t CTPR_MS_RTIC;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x60FA8 */
11537   __I  uint32_t CTPR_LS_RTIC;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x60FAC */
11538        uint8_t RESERVED_49[4];
11539   __I  uint32_t SMSTA_RTIC;                        /**< Secure Memory Status Register, offset: 0x60FB4 */
11540        uint8_t RESERVED_50[8];
11541   __I  uint64_t FAR_RTIC;                          /**< Fault Address Register, offset: 0x60FC0 */
11542   __I  uint32_t FADID_RTIC;                        /**< Fault Address DID Register, offset: 0x60FC8 */
11543   __I  uint32_t FADR_RTIC;                         /**< Fault Address Detail Register, offset: 0x60FCC */
11544        uint8_t RESERVED_51[4];
11545   __I  uint32_t CSTA_RTIC;                         /**< CAAM Status Register, offset: 0x60FD4 */
11546   __I  uint32_t SMVID_MS_RTIC;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x60FD8 */
11547   __I  uint32_t SMVID_LS_RTIC;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x60FDC */
11548   __I  uint32_t RVID_RTIC;                         /**< RTIC Version ID Register, offset: 0x60FE0 */
11549   __I  uint32_t CCBVID_RTIC;                       /**< CHA Cluster Block Version ID Register, offset: 0x60FE4 */
11550   __I  uint32_t CHAVID_MS_RTIC;                    /**< CHA Version ID Register, most-significant half, offset: 0x60FE8 */
11551   __I  uint32_t CHAVID_LS_RTIC;                    /**< CHA Version ID Register, least-significant half, offset: 0x60FEC */
11552   __I  uint32_t CHANUM_MS_RTIC;                    /**< CHA Number Register, most-significant half, offset: 0x60FF0 */
11553   __I  uint32_t CHANUM_LS_RTIC;                    /**< CHA Number Register, least-significant half, offset: 0x60FF4 */
11554   __I  uint32_t CAAMVID_MS_RTIC;                   /**< CAAM Version ID Register, most-significant half, offset: 0x60FF8 */
11555   __I  uint32_t CAAMVID_LS_RTIC;                   /**< CAAM Version ID Register, least-significant half, offset: 0x60FFC */
11556        uint8_t RESERVED_52[126976];
11557   struct {                                         /* offset: 0x80000, array step: 0xE3C */
11558          uint8_t RESERVED_0[4];
11559     union {                                          /* offset: 0x80004, array step: 0xE3C */
11560       __IO uint32_t CC1MR;                             /**< CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11561       __IO uint32_t CC1MR_PK;                          /**< CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11562       __IO uint32_t CC1MR_RNG;                         /**< CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C */
11563     };
11564          uint8_t RESERVED_1[4];
11565     __IO uint32_t CC1KSR;                            /**< CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C */
11566     __IO uint64_t CC1DSR;                            /**< CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C */
11567          uint8_t RESERVED_2[4];
11568     __IO uint32_t CC1ICVSR;                          /**< CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C */
11569          uint8_t RESERVED_3[20];
11570     __O  uint32_t CCCTRL;                            /**< CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C */
11571          uint8_t RESERVED_4[4];
11572     __IO uint32_t CICTL;                             /**< CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C */
11573          uint8_t RESERVED_5[4];
11574     __O  uint32_t CCWR;                              /**< CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C */
11575     __I  uint32_t CCSTA_MS;                          /**< CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C */
11576     __I  uint32_t CCSTA_LS;                          /**< CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C */
11577          uint8_t RESERVED_6[12];
11578     __IO uint32_t CC1AADSZR;                         /**< CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C */
11579          uint8_t RESERVED_7[4];
11580     __IO uint32_t CC1IVSZR;                          /**< CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C */
11581          uint8_t RESERVED_8[28];
11582     __IO uint32_t CPKASZR;                           /**< PKHA A Size Register, array offset: 0x80084, array step: 0xE3C */
11583          uint8_t RESERVED_9[4];
11584     __IO uint32_t CPKBSZR;                           /**< PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C */
11585          uint8_t RESERVED_10[4];
11586     __IO uint32_t CPKNSZR;                           /**< PKHA N Size Register, array offset: 0x80094, array step: 0xE3C */
11587          uint8_t RESERVED_11[4];
11588     __IO uint32_t CPKESZR;                           /**< PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C */
11589          uint8_t RESERVED_12[96];
11590     __IO uint32_t CC1CTXR[16];                       /**< CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4 */
11591          uint8_t RESERVED_13[192];
11592     __IO uint32_t CC1KR[8];                          /**< CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4 */
11593          uint8_t RESERVED_14[484];
11594     __IO uint32_t CC2MR;                             /**< CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C */
11595          uint8_t RESERVED_15[4];
11596     __IO uint32_t CC2KSR;                            /**< CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C */
11597     __IO uint64_t CC2DSR;                            /**< CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C */
11598          uint8_t RESERVED_16[4];
11599     __IO uint32_t CC2ICVSZR;                         /**< CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C */
11600          uint8_t RESERVED_17[224];
11601     __IO uint32_t CC2CTXR[18];                       /**< CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4 */
11602          uint8_t RESERVED_18[184];
11603     __IO uint32_t CC2KEYR[32];                       /**< CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4 */
11604          uint8_t RESERVED_19[320];
11605     __I  uint32_t CFIFOSTA;                          /**< CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C */
11606          uint8_t RESERVED_20[12];
11607     union {                                          /* offset: 0x807D0, array step: 0xE3C */
11608       __O  uint32_t CNFIFO;                            /**< CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C */
11609       __O  uint32_t CNFIFO_2;                          /**< CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C */
11610     };
11611          uint8_t RESERVED_21[12];
11612     __O  uint32_t CIFIFO;                            /**< CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C */
11613          uint8_t RESERVED_22[12];
11614     __I  uint64_t COFIFO;                            /**< CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C */
11615          uint8_t RESERVED_23[8];
11616     __IO uint32_t DJQCR_MS;                          /**< DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C */
11617     __I  uint32_t DJQCR_LS;                          /**< DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C */
11618     __I  uint64_t DDAR;                              /**< DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C */
11619     __I  uint32_t DOPSTA_MS;                         /**< DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C */
11620     __I  uint32_t DOPSTA_LS;                         /**< DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C */
11621          uint8_t RESERVED_24[8];
11622     __I  uint32_t DPDIDSR;                           /**< DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C */
11623     __I  uint32_t DODIDSR;                           /**< DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C */
11624          uint8_t RESERVED_25[24];
11625     struct {                                         /* offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11626       __IO uint32_t DMTH_MS;                           /**< DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11627       __IO uint32_t DMTH_LS;                           /**< DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8 */
11628     } DDMTHB[4];
11629          uint8_t RESERVED_26[32];
11630     struct {                                         /* offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11631       __IO uint32_t DGTR_0;                            /**< DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11632       __IO uint32_t DGTR_1;                            /**< DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10 */
11633       __IO uint32_t DGTR_2;                            /**< DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10 */
11634       __IO uint32_t DGTR_3;                            /**< DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10 */
11635     } DDGTR[1];
11636          uint8_t RESERVED_27[112];
11637     struct {                                         /* offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11638       __IO uint32_t DSTR_0;                            /**< DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11639       __IO uint32_t DSTR_1;                            /**< DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10 */
11640       __IO uint32_t DSTR_2;                            /**< DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10 */
11641       __IO uint32_t DSTR_3;                            /**< DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10 */
11642     } DDSTR[1];
11643          uint8_t RESERVED_28[240];
11644     __IO uint32_t DDESB[64];                         /**< DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4 */
11645          uint8_t RESERVED_29[768];
11646     __I  uint32_t DDJR;                              /**< DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C */
11647     __I  uint32_t DDDR;                              /**< DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C */
11648     __I  uint64_t DDJP;                              /**< DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C */
11649     __I  uint64_t DSDP;                              /**< DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C */
11650     __I  uint32_t DDDR_MS;                           /**< DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C */
11651     __I  uint32_t DDDR_LS;                           /**< DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C */
11652     __IO uint32_t SOL;                               /**< Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C */
11653     __IO uint32_t VSOL;                              /**< Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C */
11654     __IO uint32_t SIL;                               /**< Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C */
11655     __IO uint32_t VSIL;                              /**< Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C */
11656     __IO uint32_t DPOVRD;                            /**< Protocol Override Register, array offset: 0x80E30, array step: 0xE3C */
11657     __IO uint32_t UVSOL;                             /**< Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C */
11658     __IO uint32_t UVSIL;                             /**< Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C */
11659   } DC[1];
11660        uint8_t RESERVED_53[356];
11661   __I  uint32_t CRNR_MS_DC01;                      /**< CHA Revision Number Register, most-significant half, offset: 0x80FA0 */
11662   __I  uint32_t CRNR_LS_DC01;                      /**< CHA Revision Number Register, least-significant half, offset: 0x80FA4 */
11663   __I  uint32_t CTPR_MS_DC01;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x80FA8 */
11664   __I  uint32_t CTPR_LS_DC01;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x80FAC */
11665        uint8_t RESERVED_54[4];
11666   __I  uint32_t SMSTA_DC01;                        /**< Secure Memory Status Register, offset: 0x80FB4 */
11667        uint8_t RESERVED_55[8];
11668   __I  uint64_t FAR_DC01;                          /**< Fault Address Register, offset: 0x80FC0 */
11669   __I  uint32_t FADID_DC01;                        /**< Fault Address DID Register, offset: 0x80FC8 */
11670   __I  uint32_t FADR_DC01;                         /**< Fault Address Detail Register, offset: 0x80FCC */
11671        uint8_t RESERVED_56[4];
11672   __I  uint32_t CSTA_DC01;                         /**< CAAM Status Register, offset: 0x80FD4 */
11673   __I  uint32_t SMVID_MS_DC01;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x80FD8 */
11674   __I  uint32_t SMVID_LS_DC01;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x80FDC */
11675   __I  uint32_t RVID_DC01;                         /**< RTIC Version ID Register, offset: 0x80FE0 */
11676   __I  uint32_t CCBVID_DC01;                       /**< CHA Cluster Block Version ID Register, offset: 0x80FE4 */
11677   __I  uint32_t CHAVID_MS_DC01;                    /**< CHA Version ID Register, most-significant half, offset: 0x80FE8 */
11678   __I  uint32_t CHAVID_LS_DC01;                    /**< CHA Version ID Register, least-significant half, offset: 0x80FEC */
11679   __I  uint32_t CHANUM_MS_DC01;                    /**< CHA Number Register, most-significant half, offset: 0x80FF0 */
11680   __I  uint32_t CHANUM_LS_DC01;                    /**< CHA Number Register, least-significant half, offset: 0x80FF4 */
11681   __I  uint32_t CAAMVID_MS_DC01;                   /**< CAAM Version ID Register, most-significant half, offset: 0x80FF8 */
11682   __I  uint32_t CAAMVID_LS_DC01;                   /**< CAAM Version ID Register, least-significant half, offset: 0x80FFC */
11683 } CAAM_Type;
11684 
11685 /* ----------------------------------------------------------------------------
11686    -- CAAM Register Masks
11687    ---------------------------------------------------------------------------- */
11688 
11689 /*!
11690  * @addtogroup CAAM_Register_Masks CAAM Register Masks
11691  * @{
11692  */
11693 
11694 /*! @name MCFGR - Master Configuration Register */
11695 /*! @{ */
11696 
11697 #define CAAM_MCFGR_NORMAL_BURST_MASK             (0x1U)
11698 #define CAAM_MCFGR_NORMAL_BURST_SHIFT            (0U)
11699 /*! NORMAL_BURST
11700  *  0b0..Aligned 32 byte burst size target
11701  *  0b1..Aligned 64 byte burst size target
11702  */
11703 #define CAAM_MCFGR_NORMAL_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK)
11704 
11705 #define CAAM_MCFGR_LARGE_BURST_MASK              (0x4U)
11706 #define CAAM_MCFGR_LARGE_BURST_SHIFT             (2U)
11707 #define CAAM_MCFGR_LARGE_BURST(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK)
11708 
11709 #define CAAM_MCFGR_AXIPIPE_MASK                  (0xF0U)
11710 #define CAAM_MCFGR_AXIPIPE_SHIFT                 (4U)
11711 #define CAAM_MCFGR_AXIPIPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK)
11712 
11713 #define CAAM_MCFGR_AWCACHE_MASK                  (0xF00U)
11714 #define CAAM_MCFGR_AWCACHE_SHIFT                 (8U)
11715 #define CAAM_MCFGR_AWCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK)
11716 
11717 #define CAAM_MCFGR_ARCACHE_MASK                  (0xF000U)
11718 #define CAAM_MCFGR_ARCACHE_SHIFT                 (12U)
11719 #define CAAM_MCFGR_ARCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK)
11720 
11721 #define CAAM_MCFGR_PS_MASK                       (0x10000U)
11722 #define CAAM_MCFGR_PS_SHIFT                      (16U)
11723 /*! PS
11724  *  0b0..Pointers fit in one 32-bit word (pointers are 32-bit addresses).
11725  *  0b1..Pointers require two 32-bit words (pointers are 36-bit addresses).
11726  */
11727 #define CAAM_MCFGR_PS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK)
11728 
11729 #define CAAM_MCFGR_DWT_MASK                      (0x80000U)
11730 #define CAAM_MCFGR_DWT_SHIFT                     (19U)
11731 #define CAAM_MCFGR_DWT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK)
11732 
11733 #define CAAM_MCFGR_WRHD_MASK                     (0x8000000U)
11734 #define CAAM_MCFGR_WRHD_SHIFT                    (27U)
11735 #define CAAM_MCFGR_WRHD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK)
11736 
11737 #define CAAM_MCFGR_DMA_RST_MASK                  (0x10000000U)
11738 #define CAAM_MCFGR_DMA_RST_SHIFT                 (28U)
11739 #define CAAM_MCFGR_DMA_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK)
11740 
11741 #define CAAM_MCFGR_WDF_MASK                      (0x20000000U)
11742 #define CAAM_MCFGR_WDF_SHIFT                     (29U)
11743 #define CAAM_MCFGR_WDF(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK)
11744 
11745 #define CAAM_MCFGR_WDE_MASK                      (0x40000000U)
11746 #define CAAM_MCFGR_WDE_SHIFT                     (30U)
11747 #define CAAM_MCFGR_WDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK)
11748 
11749 #define CAAM_MCFGR_SWRST_MASK                    (0x80000000U)
11750 #define CAAM_MCFGR_SWRST_SHIFT                   (31U)
11751 #define CAAM_MCFGR_SWRST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK)
11752 /*! @} */
11753 
11754 /*! @name PAGE0_SDID - Page 0 SDID Register */
11755 /*! @{ */
11756 
11757 #define CAAM_PAGE0_SDID_SDID_MASK                (0x7FFFU)
11758 #define CAAM_PAGE0_SDID_SDID_SHIFT               (0U)
11759 #define CAAM_PAGE0_SDID_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK)
11760 /*! @} */
11761 
11762 /*! @name SCFGR - Security Configuration Register */
11763 /*! @{ */
11764 
11765 #define CAAM_SCFGR_PRIBLOB_MASK                  (0x3U)
11766 #define CAAM_SCFGR_PRIBLOB_SHIFT                 (0U)
11767 /*! PRIBLOB
11768  *  0b00..Private secure boot software blobs
11769  *  0b01..Private provisioning type 1 blobs
11770  *  0b10..Private provisioning type 2 blobs
11771  *  0b11..Normal operation blobs
11772  */
11773 #define CAAM_SCFGR_PRIBLOB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK)
11774 
11775 #define CAAM_SCFGR_RNGSH0_MASK                   (0x200U)
11776 #define CAAM_SCFGR_RNGSH0_SHIFT                  (9U)
11777 /*! RNGSH0
11778  *  0b0..When RNGSH0 is 0, RNG DRNG State Handle 0 can be instantiated in any mode. RNGSH0 is set to 0 only for testing.
11779  *  0b1..When RNGSH0 is 1, RNG DRNG State Handle 0 cannot be instantiated in deterministic (test) mode. RNGSHO
11780  *       should be set to 1 before the RNG is instantiated. If it is currently instantiated in a deterministic mode,
11781  *       it will be un-instantiated. Once this bit has been written to a 1, it cannot be changed to a 0 until the
11782  *       next power on reset.
11783  */
11784 #define CAAM_SCFGR_RNGSH0(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK)
11785 
11786 #define CAAM_SCFGR_LCK_TRNG_MASK                 (0x800U)
11787 #define CAAM_SCFGR_LCK_TRNG_SHIFT                (11U)
11788 #define CAAM_SCFGR_LCK_TRNG(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK)
11789 
11790 #define CAAM_SCFGR_VIRT_EN_MASK                  (0x8000U)
11791 #define CAAM_SCFGR_VIRT_EN_SHIFT                 (15U)
11792 /*! VIRT_EN
11793  *  0b0..Disable job ring virtualization
11794  *  0b1..Enable job ring virtualization
11795  */
11796 #define CAAM_SCFGR_VIRT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK)
11797 
11798 #define CAAM_SCFGR_MPMRL_MASK                    (0x4000000U)
11799 #define CAAM_SCFGR_MPMRL_SHIFT                   (26U)
11800 #define CAAM_SCFGR_MPMRL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK)
11801 
11802 #define CAAM_SCFGR_MPPKRC_MASK                   (0x8000000U)
11803 #define CAAM_SCFGR_MPPKRC_SHIFT                  (27U)
11804 #define CAAM_SCFGR_MPPKRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK)
11805 
11806 #define CAAM_SCFGR_MPCURVE_MASK                  (0xF0000000U)
11807 #define CAAM_SCFGR_MPCURVE_SHIFT                 (28U)
11808 #define CAAM_SCFGR_MPCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK)
11809 /*! @} */
11810 
11811 /*! @name JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half */
11812 /*! @{ */
11813 
11814 #define CAAM_JRDID_MS_PRIM_DID_MASK              (0xFU)
11815 #define CAAM_JRDID_MS_PRIM_DID_SHIFT             (0U)
11816 #define CAAM_JRDID_MS_PRIM_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK)
11817 
11818 #define CAAM_JRDID_MS_PRIM_TZ_MASK               (0x10U)
11819 #define CAAM_JRDID_MS_PRIM_TZ_SHIFT              (4U)
11820 #define CAAM_JRDID_MS_PRIM_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK)
11821 
11822 #define CAAM_JRDID_MS_SDID_MS_MASK               (0x7FE0U)
11823 #define CAAM_JRDID_MS_SDID_MS_SHIFT              (5U)
11824 #define CAAM_JRDID_MS_SDID_MS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK)
11825 
11826 #define CAAM_JRDID_MS_TZ_OWN_MASK                (0x8000U)
11827 #define CAAM_JRDID_MS_TZ_OWN_SHIFT               (15U)
11828 #define CAAM_JRDID_MS_TZ_OWN(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK)
11829 
11830 #define CAAM_JRDID_MS_AMTD_MASK                  (0x10000U)
11831 #define CAAM_JRDID_MS_AMTD_SHIFT                 (16U)
11832 #define CAAM_JRDID_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK)
11833 
11834 #define CAAM_JRDID_MS_LAMTD_MASK                 (0x20000U)
11835 #define CAAM_JRDID_MS_LAMTD_SHIFT                (17U)
11836 #define CAAM_JRDID_MS_LAMTD(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK)
11837 
11838 #define CAAM_JRDID_MS_PRIM_ICID_MASK             (0x3FF80000U)
11839 #define CAAM_JRDID_MS_PRIM_ICID_SHIFT            (19U)
11840 #define CAAM_JRDID_MS_PRIM_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK)
11841 
11842 #define CAAM_JRDID_MS_USE_OUT_MASK               (0x40000000U)
11843 #define CAAM_JRDID_MS_USE_OUT_SHIFT              (30U)
11844 #define CAAM_JRDID_MS_USE_OUT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK)
11845 
11846 #define CAAM_JRDID_MS_LDID_MASK                  (0x80000000U)
11847 #define CAAM_JRDID_MS_LDID_SHIFT                 (31U)
11848 #define CAAM_JRDID_MS_LDID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK)
11849 /*! @} */
11850 
11851 /* The count of CAAM_JRDID_MS */
11852 #define CAAM_JRDID_MS_COUNT                      (4U)
11853 
11854 /*! @name JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half */
11855 /*! @{ */
11856 
11857 #define CAAM_JRDID_LS_OUT_DID_MASK               (0xFU)
11858 #define CAAM_JRDID_LS_OUT_DID_SHIFT              (0U)
11859 #define CAAM_JRDID_LS_OUT_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK)
11860 
11861 #define CAAM_JRDID_LS_OUT_ICID_MASK              (0x3FF80000U)
11862 #define CAAM_JRDID_LS_OUT_ICID_SHIFT             (19U)
11863 #define CAAM_JRDID_LS_OUT_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK)
11864 /*! @} */
11865 
11866 /* The count of CAAM_JRDID_LS */
11867 #define CAAM_JRDID_LS_COUNT                      (4U)
11868 
11869 /*! @name DEBUGCTL - Debug Control Register */
11870 /*! @{ */
11871 
11872 #define CAAM_DEBUGCTL_STOP_MASK                  (0x10000U)
11873 #define CAAM_DEBUGCTL_STOP_SHIFT                 (16U)
11874 #define CAAM_DEBUGCTL_STOP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK)
11875 
11876 #define CAAM_DEBUGCTL_STOP_ACK_MASK              (0x20000U)
11877 #define CAAM_DEBUGCTL_STOP_ACK_SHIFT             (17U)
11878 #define CAAM_DEBUGCTL_STOP_ACK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK)
11879 /*! @} */
11880 
11881 /*! @name JRSTARTR - Job Ring Start Register */
11882 /*! @{ */
11883 
11884 #define CAAM_JRSTARTR_Start_JR0_MASK             (0x1U)
11885 #define CAAM_JRSTARTR_Start_JR0_SHIFT            (0U)
11886 /*! Start_JR0
11887  *  0b0..Stop Mode. The JR0DID register and the SMVBA register for Job Ring 0 can be written but the IRBAR, IRSR,
11888  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 are NOT accessible. If Job Ring 0 is
11889  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), the JR0DID and SMVBA register can be written only via a
11890  *       bus transaction that has ns=0.
11891  *  0b1..Start Mode. The JR0DID register and the SMVBA register for Job Ring 0 CANNOT be written but the IRBAR,
11892  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 ARE accessible. If Job Ring 0 is
11893  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11894  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0.
11895  */
11896 #define CAAM_JRSTARTR_Start_JR0(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK)
11897 
11898 #define CAAM_JRSTARTR_Start_JR1_MASK             (0x2U)
11899 #define CAAM_JRSTARTR_Start_JR1_SHIFT            (1U)
11900 /*! Start_JR1
11901  *  0b0..Stop Mode. The JR1DID register and the SMVBA register for Job Ring 1 can be written but the IRBAR, IRSR,
11902  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 are NOT accessible. If Job Ring 1 is
11903  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), the JR1DID and SMVBA register can be written only via a
11904  *       bus transaction that has ns=0.
11905  *  0b1..Start Mode. The JR1DID register and the SMVBA register for Job Ring 1 CANNOT be written but the IRBAR,
11906  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 ARE accessible. If Job Ring 1 is
11907  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11908  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0.
11909  */
11910 #define CAAM_JRSTARTR_Start_JR1(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK)
11911 
11912 #define CAAM_JRSTARTR_Start_JR2_MASK             (0x4U)
11913 #define CAAM_JRSTARTR_Start_JR2_SHIFT            (2U)
11914 /*! Start_JR2
11915  *  0b0..Stop Mode. The JR2DID register and the SMVBA register for Job Ring 2 can be written but the IRBAR, IRSR,
11916  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 are NOT accessible. If Job Ring 2 is
11917  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), the JR2DID and SMVBA register can be written only via a
11918  *       bus transaction that has ns=0.
11919  *  0b1..Start Mode. The JR2DID register and the SMVBA register for Job Ring 2 CANNOT be written but the IRBAR,
11920  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 ARE accessible. If Job Ring 2 is
11921  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11922  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0.
11923  */
11924 #define CAAM_JRSTARTR_Start_JR2(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK)
11925 
11926 #define CAAM_JRSTARTR_Start_JR3_MASK             (0x8U)
11927 #define CAAM_JRSTARTR_Start_JR3_SHIFT            (3U)
11928 /*! Start_JR3
11929  *  0b0..Stop Mode. The JR3DID register and the SMVBA register for Job Ring 3 can be written but the IRBAR, IRSR,
11930  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 are NOT accessible. If Job Ring 3 is
11931  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), the JR3DID and SMVBA register can be written only via a
11932  *       bus transaction that has ns=0.
11933  *  0b1..Start Mode. The JR3DID register and the SMVBA register for Job Ring 3 CANNOT be written but the IRBAR,
11934  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 ARE accessible. If Job Ring 3 is
11935  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11936  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 3 can be written only via a bus transaction that has ns=0.
11937  */
11938 #define CAAM_JRSTARTR_Start_JR3(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK)
11939 /*! @} */
11940 
11941 /*! @name RTIC_OWN - RTIC OWN Register */
11942 /*! @{ */
11943 
11944 #define CAAM_RTIC_OWN_ROWN_DID_MASK              (0xFU)
11945 #define CAAM_RTIC_OWN_ROWN_DID_SHIFT             (0U)
11946 /*! ROWN_DID - RTIC Owner's DID
11947  */
11948 #define CAAM_RTIC_OWN_ROWN_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK)
11949 
11950 #define CAAM_RTIC_OWN_ROWN_TZ_MASK               (0x10U)
11951 #define CAAM_RTIC_OWN_ROWN_TZ_SHIFT              (4U)
11952 #define CAAM_RTIC_OWN_ROWN_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK)
11953 
11954 #define CAAM_RTIC_OWN_LCK_MASK                   (0x80000000U)
11955 #define CAAM_RTIC_OWN_LCK_SHIFT                  (31U)
11956 #define CAAM_RTIC_OWN_LCK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK)
11957 /*! @} */
11958 
11959 /*! @name RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D */
11960 /*! @{ */
11961 
11962 #define CAAM_RTIC_DID_RTIC_DID_MASK              (0xFU)
11963 #define CAAM_RTIC_DID_RTIC_DID_SHIFT             (0U)
11964 #define CAAM_RTIC_DID_RTIC_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK)
11965 
11966 #define CAAM_RTIC_DID_RTIC_TZ_MASK               (0x10U)
11967 #define CAAM_RTIC_DID_RTIC_TZ_SHIFT              (4U)
11968 #define CAAM_RTIC_DID_RTIC_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK)
11969 
11970 #define CAAM_RTIC_DID_RTIC_ICID_MASK             (0x3FF80000U)
11971 #define CAAM_RTIC_DID_RTIC_ICID_SHIFT            (19U)
11972 #define CAAM_RTIC_DID_RTIC_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK)
11973 /*! @} */
11974 
11975 /* The count of CAAM_RTIC_DID */
11976 #define CAAM_RTIC_DID_COUNT                      (4U)
11977 
11978 /*! @name DECORSR - DECO Request Source Register */
11979 /*! @{ */
11980 
11981 #define CAAM_DECORSR_JR_MASK                     (0x3U)
11982 #define CAAM_DECORSR_JR_SHIFT                    (0U)
11983 #define CAAM_DECORSR_JR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK)
11984 
11985 #define CAAM_DECORSR_VALID_MASK                  (0x80000000U)
11986 #define CAAM_DECORSR_VALID_SHIFT                 (31U)
11987 #define CAAM_DECORSR_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK)
11988 /*! @} */
11989 
11990 /*! @name DECORR - DECO Request Register */
11991 /*! @{ */
11992 
11993 #define CAAM_DECORR_RQD0_MASK                    (0x1U)
11994 #define CAAM_DECORR_RQD0_SHIFT                   (0U)
11995 #define CAAM_DECORR_RQD0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK)
11996 
11997 #define CAAM_DECORR_DEN0_MASK                    (0x10000U)
11998 #define CAAM_DECORR_DEN0_SHIFT                   (16U)
11999 #define CAAM_DECORR_DEN0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK)
12000 /*! @} */
12001 
12002 /*! @name DECODID_MS - DECO0 DID Register - most significant half */
12003 /*! @{ */
12004 
12005 #define CAAM_DECODID_MS_DPRIM_DID_MASK           (0xFU)
12006 #define CAAM_DECODID_MS_DPRIM_DID_SHIFT          (0U)
12007 /*! DPRIM_DID - DECO Owner
12008  */
12009 #define CAAM_DECODID_MS_DPRIM_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK)
12010 
12011 #define CAAM_DECODID_MS_D_NS_MASK                (0x10U)
12012 #define CAAM_DECODID_MS_D_NS_SHIFT               (4U)
12013 #define CAAM_DECODID_MS_D_NS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK)
12014 
12015 #define CAAM_DECODID_MS_LCK_MASK                 (0x80000000U)
12016 #define CAAM_DECODID_MS_LCK_SHIFT                (31U)
12017 #define CAAM_DECODID_MS_LCK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK)
12018 /*! @} */
12019 
12020 /* The count of CAAM_DECODID_MS */
12021 #define CAAM_DECODID_MS_COUNT                    (1U)
12022 
12023 /*! @name DECODID_LS - DECO0 DID Register - least significant half */
12024 /*! @{ */
12025 
12026 #define CAAM_DECODID_LS_DSEQ_DID_MASK            (0xFU)
12027 #define CAAM_DECODID_LS_DSEQ_DID_SHIFT           (0U)
12028 #define CAAM_DECODID_LS_DSEQ_DID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK)
12029 
12030 #define CAAM_DECODID_LS_DSEQ_NS_MASK             (0x10U)
12031 #define CAAM_DECODID_LS_DSEQ_NS_SHIFT            (4U)
12032 #define CAAM_DECODID_LS_DSEQ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK)
12033 
12034 #define CAAM_DECODID_LS_DNSEQ_DID_MASK           (0xF0000U)
12035 #define CAAM_DECODID_LS_DNSEQ_DID_SHIFT          (16U)
12036 #define CAAM_DECODID_LS_DNSEQ_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK)
12037 
12038 #define CAAM_DECODID_LS_DNONSEQ_NS_MASK          (0x100000U)
12039 #define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT         (20U)
12040 #define CAAM_DECODID_LS_DNONSEQ_NS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK)
12041 /*! @} */
12042 
12043 /* The count of CAAM_DECODID_LS */
12044 #define CAAM_DECODID_LS_COUNT                    (1U)
12045 
12046 /*! @name DAR - DECO Availability Register */
12047 /*! @{ */
12048 
12049 #define CAAM_DAR_NYA0_MASK                       (0x1U)
12050 #define CAAM_DAR_NYA0_SHIFT                      (0U)
12051 #define CAAM_DAR_NYA0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK)
12052 /*! @} */
12053 
12054 /*! @name DRR - DECO Reset Register */
12055 /*! @{ */
12056 
12057 #define CAAM_DRR_RST0_MASK                       (0x1U)
12058 #define CAAM_DRR_RST0_SHIFT                      (0U)
12059 #define CAAM_DRR_RST0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK)
12060 /*! @} */
12061 
12062 /*! @name JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register */
12063 /*! @{ */
12064 
12065 #define CAAM_JRSMVBAR_SMVBA_MASK                 (0xFFFFFFFFU)
12066 #define CAAM_JRSMVBAR_SMVBA_SHIFT                (0U)
12067 #define CAAM_JRSMVBAR_SMVBA(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK)
12068 /*! @} */
12069 
12070 /* The count of CAAM_JRSMVBAR */
12071 #define CAAM_JRSMVBAR_COUNT                      (4U)
12072 
12073 /*! @name PBSL - Peak Bandwidth Smoothing Limit Register */
12074 /*! @{ */
12075 
12076 #define CAAM_PBSL_PBSL_MASK                      (0x7FU)
12077 #define CAAM_PBSL_PBSL_SHIFT                     (0U)
12078 #define CAAM_PBSL_PBSL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK)
12079 /*! @} */
12080 
12081 /*! @name DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS */
12082 /*! @{ */
12083 
12084 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK       (0xFFU)
12085 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT      (0U)
12086 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK)
12087 
12088 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK       (0xFF00U)
12089 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT      (8U)
12090 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK)
12091 
12092 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK       (0xFF0000U)
12093 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT      (16U)
12094 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK)
12095 
12096 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK       (0xFF000000U)
12097 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT      (24U)
12098 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK)
12099 /*! @} */
12100 
12101 /* The count of CAAM_DMA_AIDL_MAP_MS */
12102 #define CAAM_DMA_AIDL_MAP_MS_COUNT               (1U)
12103 
12104 /*! @name DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS */
12105 /*! @{ */
12106 
12107 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK       (0xFFU)
12108 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT      (0U)
12109 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK)
12110 
12111 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK       (0xFF00U)
12112 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT      (8U)
12113 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK)
12114 
12115 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK       (0xFF0000U)
12116 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT      (16U)
12117 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK)
12118 
12119 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK       (0xFF000000U)
12120 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT      (24U)
12121 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK)
12122 /*! @} */
12123 
12124 /* The count of CAAM_DMA_AIDL_MAP_LS */
12125 #define CAAM_DMA_AIDL_MAP_LS_COUNT               (1U)
12126 
12127 /*! @name DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS */
12128 /*! @{ */
12129 
12130 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK      (0xFFU)
12131 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT     (0U)
12132 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK)
12133 
12134 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK      (0xFF00U)
12135 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT     (8U)
12136 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK)
12137 
12138 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK      (0xFF0000U)
12139 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT     (16U)
12140 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK)
12141 
12142 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK      (0xFF000000U)
12143 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT     (24U)
12144 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK)
12145 /*! @} */
12146 
12147 /* The count of CAAM_DMA_AIDM_MAP_MS */
12148 #define CAAM_DMA_AIDM_MAP_MS_COUNT               (1U)
12149 
12150 /*! @name DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS */
12151 /*! @{ */
12152 
12153 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK       (0xFFU)
12154 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT      (0U)
12155 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK)
12156 
12157 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK       (0xFF00U)
12158 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT      (8U)
12159 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK)
12160 
12161 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK      (0xFF0000U)
12162 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT     (16U)
12163 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK)
12164 
12165 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK      (0xFF000000U)
12166 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT     (24U)
12167 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK)
12168 /*! @} */
12169 
12170 /* The count of CAAM_DMA_AIDM_MAP_LS */
12171 #define CAAM_DMA_AIDM_MAP_LS_COUNT               (1U)
12172 
12173 /*! @name DMA0_AID_ENB - DMA0 AXI ID Enable Register */
12174 /*! @{ */
12175 
12176 #define CAAM_DMA0_AID_ENB_AID0E_MASK             (0x1U)
12177 #define CAAM_DMA0_AID_ENB_AID0E_SHIFT            (0U)
12178 #define CAAM_DMA0_AID_ENB_AID0E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK)
12179 
12180 #define CAAM_DMA0_AID_ENB_AID1E_MASK             (0x2U)
12181 #define CAAM_DMA0_AID_ENB_AID1E_SHIFT            (1U)
12182 #define CAAM_DMA0_AID_ENB_AID1E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK)
12183 
12184 #define CAAM_DMA0_AID_ENB_AID2E_MASK             (0x4U)
12185 #define CAAM_DMA0_AID_ENB_AID2E_SHIFT            (2U)
12186 #define CAAM_DMA0_AID_ENB_AID2E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK)
12187 
12188 #define CAAM_DMA0_AID_ENB_AID3E_MASK             (0x8U)
12189 #define CAAM_DMA0_AID_ENB_AID3E_SHIFT            (3U)
12190 #define CAAM_DMA0_AID_ENB_AID3E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK)
12191 
12192 #define CAAM_DMA0_AID_ENB_AID4E_MASK             (0x10U)
12193 #define CAAM_DMA0_AID_ENB_AID4E_SHIFT            (4U)
12194 #define CAAM_DMA0_AID_ENB_AID4E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK)
12195 
12196 #define CAAM_DMA0_AID_ENB_AID5E_MASK             (0x20U)
12197 #define CAAM_DMA0_AID_ENB_AID5E_SHIFT            (5U)
12198 #define CAAM_DMA0_AID_ENB_AID5E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK)
12199 
12200 #define CAAM_DMA0_AID_ENB_AID6E_MASK             (0x40U)
12201 #define CAAM_DMA0_AID_ENB_AID6E_SHIFT            (6U)
12202 #define CAAM_DMA0_AID_ENB_AID6E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK)
12203 
12204 #define CAAM_DMA0_AID_ENB_AID7E_MASK             (0x80U)
12205 #define CAAM_DMA0_AID_ENB_AID7E_SHIFT            (7U)
12206 #define CAAM_DMA0_AID_ENB_AID7E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK)
12207 
12208 #define CAAM_DMA0_AID_ENB_AID8E_MASK             (0x100U)
12209 #define CAAM_DMA0_AID_ENB_AID8E_SHIFT            (8U)
12210 #define CAAM_DMA0_AID_ENB_AID8E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK)
12211 
12212 #define CAAM_DMA0_AID_ENB_AID9E_MASK             (0x200U)
12213 #define CAAM_DMA0_AID_ENB_AID9E_SHIFT            (9U)
12214 #define CAAM_DMA0_AID_ENB_AID9E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK)
12215 
12216 #define CAAM_DMA0_AID_ENB_AID10E_MASK            (0x400U)
12217 #define CAAM_DMA0_AID_ENB_AID10E_SHIFT           (10U)
12218 #define CAAM_DMA0_AID_ENB_AID10E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK)
12219 
12220 #define CAAM_DMA0_AID_ENB_AID11E_MASK            (0x800U)
12221 #define CAAM_DMA0_AID_ENB_AID11E_SHIFT           (11U)
12222 #define CAAM_DMA0_AID_ENB_AID11E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK)
12223 
12224 #define CAAM_DMA0_AID_ENB_AID12E_MASK            (0x1000U)
12225 #define CAAM_DMA0_AID_ENB_AID12E_SHIFT           (12U)
12226 #define CAAM_DMA0_AID_ENB_AID12E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK)
12227 
12228 #define CAAM_DMA0_AID_ENB_AID13E_MASK            (0x2000U)
12229 #define CAAM_DMA0_AID_ENB_AID13E_SHIFT           (13U)
12230 #define CAAM_DMA0_AID_ENB_AID13E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK)
12231 
12232 #define CAAM_DMA0_AID_ENB_AID14E_MASK            (0x4000U)
12233 #define CAAM_DMA0_AID_ENB_AID14E_SHIFT           (14U)
12234 #define CAAM_DMA0_AID_ENB_AID14E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK)
12235 
12236 #define CAAM_DMA0_AID_ENB_AID15E_MASK            (0x8000U)
12237 #define CAAM_DMA0_AID_ENB_AID15E_SHIFT           (15U)
12238 #define CAAM_DMA0_AID_ENB_AID15E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK)
12239 /*! @} */
12240 
12241 /*! @name DMA0_ARD_TC - DMA0 AXI Read Timing Check Register */
12242 /*! @{ */
12243 
12244 #define CAAM_DMA0_ARD_TC_ARSC_MASK               (0xFFFFFU)
12245 #define CAAM_DMA0_ARD_TC_ARSC_SHIFT              (0U)
12246 #define CAAM_DMA0_ARD_TC_ARSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK)
12247 
12248 #define CAAM_DMA0_ARD_TC_ARLC_MASK               (0xFFFFF000000U)
12249 #define CAAM_DMA0_ARD_TC_ARLC_SHIFT              (24U)
12250 #define CAAM_DMA0_ARD_TC_ARLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK)
12251 
12252 #define CAAM_DMA0_ARD_TC_ARL_MASK                (0xFFF000000000000U)
12253 #define CAAM_DMA0_ARD_TC_ARL_SHIFT               (48U)
12254 #define CAAM_DMA0_ARD_TC_ARL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK)
12255 
12256 #define CAAM_DMA0_ARD_TC_ARTL_MASK               (0x1000000000000000U)
12257 #define CAAM_DMA0_ARD_TC_ARTL_SHIFT              (60U)
12258 #define CAAM_DMA0_ARD_TC_ARTL(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK)
12259 
12260 #define CAAM_DMA0_ARD_TC_ARTT_MASK               (0x2000000000000000U)
12261 #define CAAM_DMA0_ARD_TC_ARTT_SHIFT              (61U)
12262 #define CAAM_DMA0_ARD_TC_ARTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK)
12263 
12264 #define CAAM_DMA0_ARD_TC_ARCT_MASK               (0x4000000000000000U)
12265 #define CAAM_DMA0_ARD_TC_ARCT_SHIFT              (62U)
12266 #define CAAM_DMA0_ARD_TC_ARCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK)
12267 
12268 #define CAAM_DMA0_ARD_TC_ARTCE_MASK              (0x8000000000000000U)
12269 #define CAAM_DMA0_ARD_TC_ARTCE_SHIFT             (63U)
12270 #define CAAM_DMA0_ARD_TC_ARTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK)
12271 /*! @} */
12272 
12273 /*! @name DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register */
12274 /*! @{ */
12275 
12276 #define CAAM_DMA0_ARD_LAT_SARL_MASK              (0xFFFFFFFFU)
12277 #define CAAM_DMA0_ARD_LAT_SARL_SHIFT             (0U)
12278 #define CAAM_DMA0_ARD_LAT_SARL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK)
12279 /*! @} */
12280 
12281 /*! @name DMA0_AWR_TC - DMA0 AXI Write Timing Check Register */
12282 /*! @{ */
12283 
12284 #define CAAM_DMA0_AWR_TC_AWSC_MASK               (0xFFFFFU)
12285 #define CAAM_DMA0_AWR_TC_AWSC_SHIFT              (0U)
12286 #define CAAM_DMA0_AWR_TC_AWSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK)
12287 
12288 #define CAAM_DMA0_AWR_TC_AWLC_MASK               (0xFFFFF000000U)
12289 #define CAAM_DMA0_AWR_TC_AWLC_SHIFT              (24U)
12290 #define CAAM_DMA0_AWR_TC_AWLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK)
12291 
12292 #define CAAM_DMA0_AWR_TC_AWL_MASK                (0xFFF000000000000U)
12293 #define CAAM_DMA0_AWR_TC_AWL_SHIFT               (48U)
12294 #define CAAM_DMA0_AWR_TC_AWL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK)
12295 
12296 #define CAAM_DMA0_AWR_TC_AWTT_MASK               (0x2000000000000000U)
12297 #define CAAM_DMA0_AWR_TC_AWTT_SHIFT              (61U)
12298 #define CAAM_DMA0_AWR_TC_AWTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK)
12299 
12300 #define CAAM_DMA0_AWR_TC_AWCT_MASK               (0x4000000000000000U)
12301 #define CAAM_DMA0_AWR_TC_AWCT_SHIFT              (62U)
12302 #define CAAM_DMA0_AWR_TC_AWCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK)
12303 
12304 #define CAAM_DMA0_AWR_TC_AWTCE_MASK              (0x8000000000000000U)
12305 #define CAAM_DMA0_AWR_TC_AWTCE_SHIFT             (63U)
12306 #define CAAM_DMA0_AWR_TC_AWTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK)
12307 /*! @} */
12308 
12309 /*! @name DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register */
12310 /*! @{ */
12311 
12312 #define CAAM_DMA0_AWR_LAT_SAWL_MASK              (0xFFFFFFFFU)
12313 #define CAAM_DMA0_AWR_LAT_SAWL_SHIFT             (0U)
12314 #define CAAM_DMA0_AWR_LAT_SAWL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK)
12315 /*! @} */
12316 
12317 /*! @name MPPKR - Manufacturing Protection Private Key Register */
12318 /*! @{ */
12319 
12320 #define CAAM_MPPKR_MPPrivK_MASK                  (0xFFU)
12321 #define CAAM_MPPKR_MPPrivK_SHIFT                 (0U)
12322 #define CAAM_MPPKR_MPPrivK(x)                    (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK)
12323 /*! @} */
12324 
12325 /* The count of CAAM_MPPKR */
12326 #define CAAM_MPPKR_COUNT                         (64U)
12327 
12328 /*! @name MPMR - Manufacturing Protection Message Register */
12329 /*! @{ */
12330 
12331 #define CAAM_MPMR_MPMSG_MASK                     (0xFFU)
12332 #define CAAM_MPMR_MPMSG_SHIFT                    (0U)
12333 #define CAAM_MPMR_MPMSG(x)                       (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK)
12334 /*! @} */
12335 
12336 /* The count of CAAM_MPMR */
12337 #define CAAM_MPMR_COUNT                          (32U)
12338 
12339 /*! @name MPTESTR - Manufacturing Protection Test Register */
12340 /*! @{ */
12341 
12342 #define CAAM_MPTESTR_TEST_VALUE_MASK             (0xFFU)
12343 #define CAAM_MPTESTR_TEST_VALUE_SHIFT            (0U)
12344 #define CAAM_MPTESTR_TEST_VALUE(x)               (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK)
12345 /*! @} */
12346 
12347 /* The count of CAAM_MPTESTR */
12348 #define CAAM_MPTESTR_COUNT                       (32U)
12349 
12350 /*! @name MPECC - Manufacturing Protection ECC Register */
12351 /*! @{ */
12352 
12353 #define CAAM_MPECC_MP_SYNDROME_MASK              (0x1FF0000U)
12354 #define CAAM_MPECC_MP_SYNDROME_SHIFT             (16U)
12355 /*! MP_SYNDROME
12356  *  0b000000000..The MP Key in the SFP passes the ECC check.
12357  *  0b000000001-0b111111111..The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome.
12358  */
12359 #define CAAM_MPECC_MP_SYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK)
12360 
12361 #define CAAM_MPECC_MP_ZERO_MASK                  (0x8000000U)
12362 #define CAAM_MPECC_MP_ZERO_SHIFT                 (27U)
12363 /*! MP_ZERO
12364  *  0b0..The MP Key in the SFP has a non-zero value.
12365  *  0b1..The MP Key in the SFP is all zeros (unprogrammed).
12366  */
12367 #define CAAM_MPECC_MP_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK)
12368 /*! @} */
12369 
12370 /*! @name JDKEKR - Job Descriptor Key Encryption Key Register */
12371 /*! @{ */
12372 
12373 #define CAAM_JDKEKR_JDKEK_MASK                   (0xFFFFFFFFU)
12374 #define CAAM_JDKEKR_JDKEK_SHIFT                  (0U)
12375 #define CAAM_JDKEKR_JDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK)
12376 /*! @} */
12377 
12378 /* The count of CAAM_JDKEKR */
12379 #define CAAM_JDKEKR_COUNT                        (8U)
12380 
12381 /*! @name TDKEKR - Trusted Descriptor Key Encryption Key Register */
12382 /*! @{ */
12383 
12384 #define CAAM_TDKEKR_TDKEK_MASK                   (0xFFFFFFFFU)
12385 #define CAAM_TDKEKR_TDKEK_SHIFT                  (0U)
12386 #define CAAM_TDKEKR_TDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK)
12387 /*! @} */
12388 
12389 /* The count of CAAM_TDKEKR */
12390 #define CAAM_TDKEKR_COUNT                        (8U)
12391 
12392 /*! @name TDSKR - Trusted Descriptor Signing Key Register */
12393 /*! @{ */
12394 
12395 #define CAAM_TDSKR_TDSK_MASK                     (0xFFFFFFFFU)
12396 #define CAAM_TDSKR_TDSK_SHIFT                    (0U)
12397 #define CAAM_TDSKR_TDSK(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK)
12398 /*! @} */
12399 
12400 /* The count of CAAM_TDSKR */
12401 #define CAAM_TDSKR_COUNT                         (8U)
12402 
12403 /*! @name SKNR - Secure Key Nonce Register */
12404 /*! @{ */
12405 
12406 #define CAAM_SKNR_SK_NONCE_LS_MASK               (0xFFFFFFFFU)
12407 #define CAAM_SKNR_SK_NONCE_LS_SHIFT              (0U)
12408 #define CAAM_SKNR_SK_NONCE_LS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK)
12409 
12410 #define CAAM_SKNR_SK_NONCE_MS_MASK               (0x7FFF00000000U)
12411 #define CAAM_SKNR_SK_NONCE_MS_SHIFT              (32U)
12412 #define CAAM_SKNR_SK_NONCE_MS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK)
12413 /*! @} */
12414 
12415 /*! @name DMA_STA - DMA Status Register */
12416 /*! @{ */
12417 
12418 #define CAAM_DMA_STA_DMA0_ETIF_MASK              (0x1FU)
12419 #define CAAM_DMA_STA_DMA0_ETIF_SHIFT             (0U)
12420 #define CAAM_DMA_STA_DMA0_ETIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK)
12421 
12422 #define CAAM_DMA_STA_DMA0_ITIF_MASK              (0x20U)
12423 #define CAAM_DMA_STA_DMA0_ITIF_SHIFT             (5U)
12424 #define CAAM_DMA_STA_DMA0_ITIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK)
12425 
12426 #define CAAM_DMA_STA_DMA0_IDLE_MASK              (0x80U)
12427 #define CAAM_DMA_STA_DMA0_IDLE_SHIFT             (7U)
12428 #define CAAM_DMA_STA_DMA0_IDLE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK)
12429 /*! @} */
12430 
12431 /*! @name DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP */
12432 /*! @{ */
12433 
12434 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK     (0xFFU)
12435 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT    (0U)
12436 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK)
12437 
12438 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK     (0xFF00U)
12439 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT    (8U)
12440 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK)
12441 
12442 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK     (0xFF0000U)
12443 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT    (16U)
12444 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK)
12445 
12446 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK     (0xFF000000U)
12447 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT    (24U)
12448 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK)
12449 /*! @} */
12450 
12451 /*! @name DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP */
12452 /*! @{ */
12453 
12454 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK     (0xFFU)
12455 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT    (0U)
12456 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK)
12457 
12458 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK     (0xFF00U)
12459 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT    (8U)
12460 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK)
12461 
12462 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK     (0xFF0000U)
12463 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT    (16U)
12464 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK)
12465 
12466 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK     (0xFF000000U)
12467 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT    (24U)
12468 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK)
12469 /*! @} */
12470 
12471 /*! @name DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP */
12472 /*! @{ */
12473 
12474 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK  (0xFFU)
12475 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U)
12476 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK)
12477 
12478 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK  (0xFF00U)
12479 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U)
12480 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK)
12481 
12482 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK  (0xFF0000U)
12483 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U)
12484 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK)
12485 
12486 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK  (0xFF000000U)
12487 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U)
12488 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK)
12489 /*! @} */
12490 
12491 /*! @name DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP */
12492 /*! @{ */
12493 
12494 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK    (0xFFU)
12495 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT   (0U)
12496 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK)
12497 
12498 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK    (0xFF00U)
12499 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT   (8U)
12500 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK)
12501 
12502 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK   (0xFF0000U)
12503 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT  (16U)
12504 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK)
12505 
12506 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK   (0xFF000000U)
12507 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT  (24U)
12508 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK)
12509 /*! @} */
12510 
12511 /*! @name DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register */
12512 /*! @{ */
12513 
12514 #define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK        (0x1U)
12515 #define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT       (0U)
12516 #define CAAM_DMA_X_AID_15_0_EN_AID0E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK)
12517 
12518 #define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK        (0x2U)
12519 #define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT       (1U)
12520 #define CAAM_DMA_X_AID_15_0_EN_AID1E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK)
12521 
12522 #define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK        (0x4U)
12523 #define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT       (2U)
12524 #define CAAM_DMA_X_AID_15_0_EN_AID2E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK)
12525 
12526 #define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK        (0x8U)
12527 #define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT       (3U)
12528 #define CAAM_DMA_X_AID_15_0_EN_AID3E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK)
12529 
12530 #define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK        (0x10U)
12531 #define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT       (4U)
12532 #define CAAM_DMA_X_AID_15_0_EN_AID4E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK)
12533 
12534 #define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK        (0x20U)
12535 #define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT       (5U)
12536 #define CAAM_DMA_X_AID_15_0_EN_AID5E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK)
12537 
12538 #define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK        (0x40U)
12539 #define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT       (6U)
12540 #define CAAM_DMA_X_AID_15_0_EN_AID6E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK)
12541 
12542 #define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK        (0x80U)
12543 #define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT       (7U)
12544 #define CAAM_DMA_X_AID_15_0_EN_AID7E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK)
12545 
12546 #define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK        (0x100U)
12547 #define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT       (8U)
12548 #define CAAM_DMA_X_AID_15_0_EN_AID8E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK)
12549 
12550 #define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK        (0x200U)
12551 #define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT       (9U)
12552 #define CAAM_DMA_X_AID_15_0_EN_AID9E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK)
12553 
12554 #define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK       (0x400U)
12555 #define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT      (10U)
12556 #define CAAM_DMA_X_AID_15_0_EN_AID10E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK)
12557 
12558 #define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK       (0x800U)
12559 #define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT      (11U)
12560 #define CAAM_DMA_X_AID_15_0_EN_AID11E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK)
12561 
12562 #define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK       (0x1000U)
12563 #define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT      (12U)
12564 #define CAAM_DMA_X_AID_15_0_EN_AID12E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK)
12565 
12566 #define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK       (0x2000U)
12567 #define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT      (13U)
12568 #define CAAM_DMA_X_AID_15_0_EN_AID13E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK)
12569 
12570 #define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK       (0x4000U)
12571 #define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT      (14U)
12572 #define CAAM_DMA_X_AID_15_0_EN_AID14E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK)
12573 
12574 #define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK       (0x8000U)
12575 #define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT      (15U)
12576 #define CAAM_DMA_X_AID_15_0_EN_AID15E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK)
12577 /*! @} */
12578 
12579 /*! @name DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register */
12580 /*! @{ */
12581 
12582 #define CAAM_DMA_X_ARTC_CTL_ART_MASK             (0xFFFU)
12583 #define CAAM_DMA_X_ARTC_CTL_ART_SHIFT            (0U)
12584 #define CAAM_DMA_X_ARTC_CTL_ART(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK)
12585 
12586 #define CAAM_DMA_X_ARTC_CTL_ARL_MASK             (0xFFF0000U)
12587 #define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT            (16U)
12588 #define CAAM_DMA_X_ARTC_CTL_ARL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK)
12589 
12590 #define CAAM_DMA_X_ARTC_CTL_ARTL_MASK            (0x10000000U)
12591 #define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT           (28U)
12592 #define CAAM_DMA_X_ARTC_CTL_ARTL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK)
12593 
12594 #define CAAM_DMA_X_ARTC_CTL_ARTT_MASK            (0x20000000U)
12595 #define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT           (29U)
12596 #define CAAM_DMA_X_ARTC_CTL_ARTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK)
12597 
12598 #define CAAM_DMA_X_ARTC_CTL_ARCT_MASK            (0x40000000U)
12599 #define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT           (30U)
12600 #define CAAM_DMA_X_ARTC_CTL_ARCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK)
12601 
12602 #define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK           (0x80000000U)
12603 #define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT          (31U)
12604 #define CAAM_DMA_X_ARTC_CTL_ARTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK)
12605 /*! @} */
12606 
12607 /*! @name DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register */
12608 /*! @{ */
12609 
12610 #define CAAM_DMA_X_ARTC_LC_ARLC_MASK             (0xFFFFFU)
12611 #define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT            (0U)
12612 #define CAAM_DMA_X_ARTC_LC_ARLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK)
12613 /*! @} */
12614 
12615 /*! @name DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register */
12616 /*! @{ */
12617 
12618 #define CAAM_DMA_X_ARTC_SC_ARSC_MASK             (0xFFFFFU)
12619 #define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT            (0U)
12620 #define CAAM_DMA_X_ARTC_SC_ARSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK)
12621 /*! @} */
12622 
12623 /*! @name DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register */
12624 /*! @{ */
12625 
12626 #define CAAM_DMA_X_ARTC_LAT_SARL_MASK            (0xFFFFFFFFU)
12627 #define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT           (0U)
12628 #define CAAM_DMA_X_ARTC_LAT_SARL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK)
12629 /*! @} */
12630 
12631 /*! @name DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register */
12632 /*! @{ */
12633 
12634 #define CAAM_DMA_X_AWTC_CTL_AWT_MASK             (0xFFFU)
12635 #define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT            (0U)
12636 #define CAAM_DMA_X_AWTC_CTL_AWT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK)
12637 
12638 #define CAAM_DMA_X_AWTC_CTL_AWL_MASK             (0xFFF0000U)
12639 #define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT            (16U)
12640 #define CAAM_DMA_X_AWTC_CTL_AWL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK)
12641 
12642 #define CAAM_DMA_X_AWTC_CTL_AWTT_MASK            (0x20000000U)
12643 #define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT           (29U)
12644 #define CAAM_DMA_X_AWTC_CTL_AWTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK)
12645 
12646 #define CAAM_DMA_X_AWTC_CTL_AWCT_MASK            (0x40000000U)
12647 #define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT           (30U)
12648 #define CAAM_DMA_X_AWTC_CTL_AWCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK)
12649 
12650 #define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK           (0x80000000U)
12651 #define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT          (31U)
12652 #define CAAM_DMA_X_AWTC_CTL_AWTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK)
12653 /*! @} */
12654 
12655 /*! @name DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register */
12656 /*! @{ */
12657 
12658 #define CAAM_DMA_X_AWTC_LC_AWLC_MASK             (0xFFFFFU)
12659 #define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT            (0U)
12660 #define CAAM_DMA_X_AWTC_LC_AWLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK)
12661 /*! @} */
12662 
12663 /*! @name DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register */
12664 /*! @{ */
12665 
12666 #define CAAM_DMA_X_AWTC_SC_AWSC_MASK             (0xFFFFFU)
12667 #define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT            (0U)
12668 #define CAAM_DMA_X_AWTC_SC_AWSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK)
12669 /*! @} */
12670 
12671 /*! @name DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register */
12672 /*! @{ */
12673 
12674 #define CAAM_DMA_X_AWTC_LAT_SAWL_MASK            (0xFFFFFFFFU)
12675 #define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT           (0U)
12676 #define CAAM_DMA_X_AWTC_LAT_SAWL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK)
12677 /*! @} */
12678 
12679 /*! @name RTMCTL - RNG TRNG Miscellaneous Control Register */
12680 /*! @{ */
12681 
12682 #define CAAM_RTMCTL_SAMP_MODE_MASK               (0x3U)
12683 #define CAAM_RTMCTL_SAMP_MODE_SHIFT              (0U)
12684 /*! SAMP_MODE
12685  *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
12686  *  0b01..use raw data into both Entropy shifter and Statistical Checker
12687  *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
12688  *  0b11..undefined/reserved.
12689  */
12690 #define CAAM_RTMCTL_SAMP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK)
12691 
12692 #define CAAM_RTMCTL_OSC_DIV_MASK                 (0xCU)
12693 #define CAAM_RTMCTL_OSC_DIV_SHIFT                (2U)
12694 /*! OSC_DIV
12695  *  0b00..use ring oscillator with no divide
12696  *  0b01..use ring oscillator divided-by-2
12697  *  0b10..use ring oscillator divided-by-4
12698  *  0b11..use ring oscillator divided-by-8
12699  */
12700 #define CAAM_RTMCTL_OSC_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK)
12701 
12702 #define CAAM_RTMCTL_CLK_OUT_EN_MASK              (0x10U)
12703 #define CAAM_RTMCTL_CLK_OUT_EN_SHIFT             (4U)
12704 #define CAAM_RTMCTL_CLK_OUT_EN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK)
12705 
12706 #define CAAM_RTMCTL_TRNG_ACC_MASK                (0x20U)
12707 #define CAAM_RTMCTL_TRNG_ACC_SHIFT               (5U)
12708 #define CAAM_RTMCTL_TRNG_ACC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK)
12709 
12710 #define CAAM_RTMCTL_RST_DEF_MASK                 (0x40U)
12711 #define CAAM_RTMCTL_RST_DEF_SHIFT                (6U)
12712 #define CAAM_RTMCTL_RST_DEF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK)
12713 
12714 #define CAAM_RTMCTL_FORCE_SYSCLK_MASK            (0x80U)
12715 #define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT           (7U)
12716 #define CAAM_RTMCTL_FORCE_SYSCLK(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK)
12717 
12718 #define CAAM_RTMCTL_FCT_FAIL_MASK                (0x100U)
12719 #define CAAM_RTMCTL_FCT_FAIL_SHIFT               (8U)
12720 #define CAAM_RTMCTL_FCT_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK)
12721 
12722 #define CAAM_RTMCTL_FCT_VAL_MASK                 (0x200U)
12723 #define CAAM_RTMCTL_FCT_VAL_SHIFT                (9U)
12724 #define CAAM_RTMCTL_FCT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK)
12725 
12726 #define CAAM_RTMCTL_ENT_VAL_MASK                 (0x400U)
12727 #define CAAM_RTMCTL_ENT_VAL_SHIFT                (10U)
12728 #define CAAM_RTMCTL_ENT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK)
12729 
12730 #define CAAM_RTMCTL_TST_OUT_MASK                 (0x800U)
12731 #define CAAM_RTMCTL_TST_OUT_SHIFT                (11U)
12732 #define CAAM_RTMCTL_TST_OUT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK)
12733 
12734 #define CAAM_RTMCTL_ERR_MASK                     (0x1000U)
12735 #define CAAM_RTMCTL_ERR_SHIFT                    (12U)
12736 #define CAAM_RTMCTL_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK)
12737 
12738 #define CAAM_RTMCTL_TSTOP_OK_MASK                (0x2000U)
12739 #define CAAM_RTMCTL_TSTOP_OK_SHIFT               (13U)
12740 #define CAAM_RTMCTL_TSTOP_OK(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK)
12741 
12742 #define CAAM_RTMCTL_PRGM_MASK                    (0x10000U)
12743 #define CAAM_RTMCTL_PRGM_SHIFT                   (16U)
12744 #define CAAM_RTMCTL_PRGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK)
12745 /*! @} */
12746 
12747 /*! @name RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register */
12748 /*! @{ */
12749 
12750 #define CAAM_RTSCMISC_LRUN_MAX_MASK              (0xFFU)
12751 #define CAAM_RTSCMISC_LRUN_MAX_SHIFT             (0U)
12752 #define CAAM_RTSCMISC_LRUN_MAX(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK)
12753 
12754 #define CAAM_RTSCMISC_RTY_CNT_MASK               (0xF0000U)
12755 #define CAAM_RTSCMISC_RTY_CNT_SHIFT              (16U)
12756 #define CAAM_RTSCMISC_RTY_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK)
12757 /*! @} */
12758 
12759 /*! @name RTPKRRNG - RNG TRNG Poker Range Register */
12760 /*! @{ */
12761 
12762 #define CAAM_RTPKRRNG_PKR_RNG_MASK               (0xFFFFU)
12763 #define CAAM_RTPKRRNG_PKR_RNG_SHIFT              (0U)
12764 #define CAAM_RTPKRRNG_PKR_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK)
12765 /*! @} */
12766 
12767 /*! @name RTPKRMAX - RNG TRNG Poker Maximum Limit Register */
12768 /*! @{ */
12769 
12770 #define CAAM_RTPKRMAX_PKR_MAX_MASK               (0xFFFFFFU)
12771 #define CAAM_RTPKRMAX_PKR_MAX_SHIFT              (0U)
12772 #define CAAM_RTPKRMAX_PKR_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK)
12773 /*! @} */
12774 
12775 /*! @name RTPKRSQ - RNG TRNG Poker Square Calculation Result Register */
12776 /*! @{ */
12777 
12778 #define CAAM_RTPKRSQ_PKR_SQ_MASK                 (0xFFFFFFU)
12779 #define CAAM_RTPKRSQ_PKR_SQ_SHIFT                (0U)
12780 #define CAAM_RTPKRSQ_PKR_SQ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK)
12781 /*! @} */
12782 
12783 /*! @name RTSDCTL - RNG TRNG Seed Control Register */
12784 /*! @{ */
12785 
12786 #define CAAM_RTSDCTL_SAMP_SIZE_MASK              (0xFFFFU)
12787 #define CAAM_RTSDCTL_SAMP_SIZE_SHIFT             (0U)
12788 #define CAAM_RTSDCTL_SAMP_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK)
12789 
12790 #define CAAM_RTSDCTL_ENT_DLY_MASK                (0xFFFF0000U)
12791 #define CAAM_RTSDCTL_ENT_DLY_SHIFT               (16U)
12792 #define CAAM_RTSDCTL_ENT_DLY(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK)
12793 /*! @} */
12794 
12795 /*! @name RTSBLIM - RNG TRNG Sparse Bit Limit Register */
12796 /*! @{ */
12797 
12798 #define CAAM_RTSBLIM_SB_LIM_MASK                 (0x3FFU)
12799 #define CAAM_RTSBLIM_SB_LIM_SHIFT                (0U)
12800 #define CAAM_RTSBLIM_SB_LIM(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK)
12801 /*! @} */
12802 
12803 /*! @name RTTOTSAM - RNG TRNG Total Samples Register */
12804 /*! @{ */
12805 
12806 #define CAAM_RTTOTSAM_TOT_SAM_MASK               (0xFFFFFU)
12807 #define CAAM_RTTOTSAM_TOT_SAM_SHIFT              (0U)
12808 #define CAAM_RTTOTSAM_TOT_SAM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK)
12809 /*! @} */
12810 
12811 /*! @name RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register */
12812 /*! @{ */
12813 
12814 #define CAAM_RTFRQMIN_FRQ_MIN_MASK               (0x3FFFFFU)
12815 #define CAAM_RTFRQMIN_FRQ_MIN_SHIFT              (0U)
12816 #define CAAM_RTFRQMIN_FRQ_MIN(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK)
12817 /*! @} */
12818 
12819 /*! @name RTFRQCNT - RNG TRNG Frequency Count Register */
12820 /*! @{ */
12821 
12822 #define CAAM_RTFRQCNT_FRQ_CNT_MASK               (0x3FFFFFU)
12823 #define CAAM_RTFRQCNT_FRQ_CNT_SHIFT              (0U)
12824 #define CAAM_RTFRQCNT_FRQ_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK)
12825 /*! @} */
12826 
12827 /*! @name RTSCMC - RNG TRNG Statistical Check Monobit Count Register */
12828 /*! @{ */
12829 
12830 #define CAAM_RTSCMC_MONO_CNT_MASK                (0xFFFFU)
12831 #define CAAM_RTSCMC_MONO_CNT_SHIFT               (0U)
12832 #define CAAM_RTSCMC_MONO_CNT(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK)
12833 /*! @} */
12834 
12835 /*! @name RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register */
12836 /*! @{ */
12837 
12838 #define CAAM_RTSCR1C_R1_0_COUNT_MASK             (0x7FFFU)
12839 #define CAAM_RTSCR1C_R1_0_COUNT_SHIFT            (0U)
12840 #define CAAM_RTSCR1C_R1_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK)
12841 
12842 #define CAAM_RTSCR1C_R1_1_COUNT_MASK             (0x7FFF0000U)
12843 #define CAAM_RTSCR1C_R1_1_COUNT_SHIFT            (16U)
12844 #define CAAM_RTSCR1C_R1_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK)
12845 /*! @} */
12846 
12847 /*! @name RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register */
12848 /*! @{ */
12849 
12850 #define CAAM_RTSCR2C_R2_0_COUNT_MASK             (0x3FFFU)
12851 #define CAAM_RTSCR2C_R2_0_COUNT_SHIFT            (0U)
12852 #define CAAM_RTSCR2C_R2_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK)
12853 
12854 #define CAAM_RTSCR2C_R2_1_COUNT_MASK             (0x3FFF0000U)
12855 #define CAAM_RTSCR2C_R2_1_COUNT_SHIFT            (16U)
12856 #define CAAM_RTSCR2C_R2_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK)
12857 /*! @} */
12858 
12859 /*! @name RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register */
12860 /*! @{ */
12861 
12862 #define CAAM_RTSCR3C_R3_0_COUNT_MASK             (0x1FFFU)
12863 #define CAAM_RTSCR3C_R3_0_COUNT_SHIFT            (0U)
12864 #define CAAM_RTSCR3C_R3_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK)
12865 
12866 #define CAAM_RTSCR3C_R3_1_COUNT_MASK             (0x1FFF0000U)
12867 #define CAAM_RTSCR3C_R3_1_COUNT_SHIFT            (16U)
12868 #define CAAM_RTSCR3C_R3_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK)
12869 /*! @} */
12870 
12871 /*! @name RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register */
12872 /*! @{ */
12873 
12874 #define CAAM_RTSCR4C_R4_0_COUNT_MASK             (0xFFFU)
12875 #define CAAM_RTSCR4C_R4_0_COUNT_SHIFT            (0U)
12876 #define CAAM_RTSCR4C_R4_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK)
12877 
12878 #define CAAM_RTSCR4C_R4_1_COUNT_MASK             (0xFFF0000U)
12879 #define CAAM_RTSCR4C_R4_1_COUNT_SHIFT            (16U)
12880 #define CAAM_RTSCR4C_R4_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK)
12881 /*! @} */
12882 
12883 /*! @name RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register */
12884 /*! @{ */
12885 
12886 #define CAAM_RTSCR5C_R5_0_COUNT_MASK             (0x7FFU)
12887 #define CAAM_RTSCR5C_R5_0_COUNT_SHIFT            (0U)
12888 #define CAAM_RTSCR5C_R5_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK)
12889 
12890 #define CAAM_RTSCR5C_R5_1_COUNT_MASK             (0x7FF0000U)
12891 #define CAAM_RTSCR5C_R5_1_COUNT_SHIFT            (16U)
12892 #define CAAM_RTSCR5C_R5_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK)
12893 /*! @} */
12894 
12895 /*! @name RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register */
12896 /*! @{ */
12897 
12898 #define CAAM_RTSCR6PC_R6P_0_COUNT_MASK           (0x7FFU)
12899 #define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT          (0U)
12900 #define CAAM_RTSCR6PC_R6P_0_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK)
12901 
12902 #define CAAM_RTSCR6PC_R6P_1_COUNT_MASK           (0x7FF0000U)
12903 #define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT          (16U)
12904 #define CAAM_RTSCR6PC_R6P_1_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK)
12905 /*! @} */
12906 
12907 /*! @name RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register */
12908 /*! @{ */
12909 
12910 #define CAAM_RTFRQMAX_FRQ_MAX_MASK               (0x3FFFFFU)
12911 #define CAAM_RTFRQMAX_FRQ_MAX_SHIFT              (0U)
12912 #define CAAM_RTFRQMAX_FRQ_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK)
12913 /*! @} */
12914 
12915 /*! @name RTSCML - RNG TRNG Statistical Check Monobit Limit Register */
12916 /*! @{ */
12917 
12918 #define CAAM_RTSCML_MONO_MAX_MASK                (0xFFFFU)
12919 #define CAAM_RTSCML_MONO_MAX_SHIFT               (0U)
12920 #define CAAM_RTSCML_MONO_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK)
12921 
12922 #define CAAM_RTSCML_MONO_RNG_MASK                (0xFFFF0000U)
12923 #define CAAM_RTSCML_MONO_RNG_SHIFT               (16U)
12924 #define CAAM_RTSCML_MONO_RNG(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK)
12925 /*! @} */
12926 
12927 /*! @name RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register */
12928 /*! @{ */
12929 
12930 #define CAAM_RTSCR1L_RUN1_MAX_MASK               (0x7FFFU)
12931 #define CAAM_RTSCR1L_RUN1_MAX_SHIFT              (0U)
12932 #define CAAM_RTSCR1L_RUN1_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK)
12933 
12934 #define CAAM_RTSCR1L_RUN1_RNG_MASK               (0x7FFF0000U)
12935 #define CAAM_RTSCR1L_RUN1_RNG_SHIFT              (16U)
12936 #define CAAM_RTSCR1L_RUN1_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK)
12937 /*! @} */
12938 
12939 /*! @name RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register */
12940 /*! @{ */
12941 
12942 #define CAAM_RTSCR2L_RUN2_MAX_MASK               (0x3FFFU)
12943 #define CAAM_RTSCR2L_RUN2_MAX_SHIFT              (0U)
12944 #define CAAM_RTSCR2L_RUN2_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK)
12945 
12946 #define CAAM_RTSCR2L_RUN2_RNG_MASK               (0x3FFF0000U)
12947 #define CAAM_RTSCR2L_RUN2_RNG_SHIFT              (16U)
12948 #define CAAM_RTSCR2L_RUN2_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK)
12949 /*! @} */
12950 
12951 /*! @name RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register */
12952 /*! @{ */
12953 
12954 #define CAAM_RTSCR3L_RUN3_MAX_MASK               (0x1FFFU)
12955 #define CAAM_RTSCR3L_RUN3_MAX_SHIFT              (0U)
12956 #define CAAM_RTSCR3L_RUN3_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK)
12957 
12958 #define CAAM_RTSCR3L_RUN3_RNG_MASK               (0x1FFF0000U)
12959 #define CAAM_RTSCR3L_RUN3_RNG_SHIFT              (16U)
12960 #define CAAM_RTSCR3L_RUN3_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK)
12961 /*! @} */
12962 
12963 /*! @name RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register */
12964 /*! @{ */
12965 
12966 #define CAAM_RTSCR4L_RUN4_MAX_MASK               (0xFFFU)
12967 #define CAAM_RTSCR4L_RUN4_MAX_SHIFT              (0U)
12968 #define CAAM_RTSCR4L_RUN4_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK)
12969 
12970 #define CAAM_RTSCR4L_RUN4_RNG_MASK               (0xFFF0000U)
12971 #define CAAM_RTSCR4L_RUN4_RNG_SHIFT              (16U)
12972 #define CAAM_RTSCR4L_RUN4_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK)
12973 /*! @} */
12974 
12975 /*! @name RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register */
12976 /*! @{ */
12977 
12978 #define CAAM_RTSCR5L_RUN5_MAX_MASK               (0x7FFU)
12979 #define CAAM_RTSCR5L_RUN5_MAX_SHIFT              (0U)
12980 #define CAAM_RTSCR5L_RUN5_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK)
12981 
12982 #define CAAM_RTSCR5L_RUN5_RNG_MASK               (0x7FF0000U)
12983 #define CAAM_RTSCR5L_RUN5_RNG_SHIFT              (16U)
12984 #define CAAM_RTSCR5L_RUN5_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK)
12985 /*! @} */
12986 
12987 /*! @name RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register */
12988 /*! @{ */
12989 
12990 #define CAAM_RTSCR6PL_RUN6P_MAX_MASK             (0x7FFU)
12991 #define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT            (0U)
12992 #define CAAM_RTSCR6PL_RUN6P_MAX(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK)
12993 
12994 #define CAAM_RTSCR6PL_RUN6P_RNG_MASK             (0x7FF0000U)
12995 #define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT            (16U)
12996 #define CAAM_RTSCR6PL_RUN6P_RNG(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK)
12997 /*! @} */
12998 
12999 /*! @name RTSTATUS - RNG TRNG Status Register */
13000 /*! @{ */
13001 
13002 #define CAAM_RTSTATUS_F1BR0TF_MASK               (0x1U)
13003 #define CAAM_RTSTATUS_F1BR0TF_SHIFT              (0U)
13004 #define CAAM_RTSTATUS_F1BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK)
13005 
13006 #define CAAM_RTSTATUS_F1BR1TF_MASK               (0x2U)
13007 #define CAAM_RTSTATUS_F1BR1TF_SHIFT              (1U)
13008 #define CAAM_RTSTATUS_F1BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK)
13009 
13010 #define CAAM_RTSTATUS_F2BR0TF_MASK               (0x4U)
13011 #define CAAM_RTSTATUS_F2BR0TF_SHIFT              (2U)
13012 #define CAAM_RTSTATUS_F2BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK)
13013 
13014 #define CAAM_RTSTATUS_F2BR1TF_MASK               (0x8U)
13015 #define CAAM_RTSTATUS_F2BR1TF_SHIFT              (3U)
13016 #define CAAM_RTSTATUS_F2BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK)
13017 
13018 #define CAAM_RTSTATUS_F3BR01TF_MASK              (0x10U)
13019 #define CAAM_RTSTATUS_F3BR01TF_SHIFT             (4U)
13020 #define CAAM_RTSTATUS_F3BR01TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK)
13021 
13022 #define CAAM_RTSTATUS_F3BR1TF_MASK               (0x20U)
13023 #define CAAM_RTSTATUS_F3BR1TF_SHIFT              (5U)
13024 #define CAAM_RTSTATUS_F3BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK)
13025 
13026 #define CAAM_RTSTATUS_F4BR0TF_MASK               (0x40U)
13027 #define CAAM_RTSTATUS_F4BR0TF_SHIFT              (6U)
13028 #define CAAM_RTSTATUS_F4BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK)
13029 
13030 #define CAAM_RTSTATUS_F4BR1TF_MASK               (0x80U)
13031 #define CAAM_RTSTATUS_F4BR1TF_SHIFT              (7U)
13032 #define CAAM_RTSTATUS_F4BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK)
13033 
13034 #define CAAM_RTSTATUS_F5BR0TF_MASK               (0x100U)
13035 #define CAAM_RTSTATUS_F5BR0TF_SHIFT              (8U)
13036 #define CAAM_RTSTATUS_F5BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK)
13037 
13038 #define CAAM_RTSTATUS_F5BR1TF_MASK               (0x200U)
13039 #define CAAM_RTSTATUS_F5BR1TF_SHIFT              (9U)
13040 #define CAAM_RTSTATUS_F5BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK)
13041 
13042 #define CAAM_RTSTATUS_F6PBR0TF_MASK              (0x400U)
13043 #define CAAM_RTSTATUS_F6PBR0TF_SHIFT             (10U)
13044 #define CAAM_RTSTATUS_F6PBR0TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK)
13045 
13046 #define CAAM_RTSTATUS_F6PBR1TF_MASK              (0x800U)
13047 #define CAAM_RTSTATUS_F6PBR1TF_SHIFT             (11U)
13048 #define CAAM_RTSTATUS_F6PBR1TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK)
13049 
13050 #define CAAM_RTSTATUS_FSBTF_MASK                 (0x1000U)
13051 #define CAAM_RTSTATUS_FSBTF_SHIFT                (12U)
13052 #define CAAM_RTSTATUS_FSBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK)
13053 
13054 #define CAAM_RTSTATUS_FLRTF_MASK                 (0x2000U)
13055 #define CAAM_RTSTATUS_FLRTF_SHIFT                (13U)
13056 #define CAAM_RTSTATUS_FLRTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK)
13057 
13058 #define CAAM_RTSTATUS_FPTF_MASK                  (0x4000U)
13059 #define CAAM_RTSTATUS_FPTF_SHIFT                 (14U)
13060 #define CAAM_RTSTATUS_FPTF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK)
13061 
13062 #define CAAM_RTSTATUS_FMBTF_MASK                 (0x8000U)
13063 #define CAAM_RTSTATUS_FMBTF_SHIFT                (15U)
13064 #define CAAM_RTSTATUS_FMBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK)
13065 
13066 #define CAAM_RTSTATUS_RETRY_COUNT_MASK           (0xF0000U)
13067 #define CAAM_RTSTATUS_RETRY_COUNT_SHIFT          (16U)
13068 #define CAAM_RTSTATUS_RETRY_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK)
13069 /*! @} */
13070 
13071 /*! @name RTENT - RNG TRNG Entropy Read Register */
13072 /*! @{ */
13073 
13074 #define CAAM_RTENT_ENT_MASK                      (0xFFFFFFFFU)
13075 #define CAAM_RTENT_ENT_SHIFT                     (0U)
13076 #define CAAM_RTENT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK)
13077 /*! @} */
13078 
13079 /* The count of CAAM_RTENT */
13080 #define CAAM_RTENT_COUNT                         (16U)
13081 
13082 /*! @name RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register */
13083 /*! @{ */
13084 
13085 #define CAAM_RTPKRCNT10_PKR_0_CNT_MASK           (0xFFFFU)
13086 #define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT          (0U)
13087 #define CAAM_RTPKRCNT10_PKR_0_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK)
13088 
13089 #define CAAM_RTPKRCNT10_PKR_1_CNT_MASK           (0xFFFF0000U)
13090 #define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT          (16U)
13091 #define CAAM_RTPKRCNT10_PKR_1_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK)
13092 /*! @} */
13093 
13094 /*! @name RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register */
13095 /*! @{ */
13096 
13097 #define CAAM_RTPKRCNT32_PKR_2_CNT_MASK           (0xFFFFU)
13098 #define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT          (0U)
13099 #define CAAM_RTPKRCNT32_PKR_2_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK)
13100 
13101 #define CAAM_RTPKRCNT32_PKR_3_CNT_MASK           (0xFFFF0000U)
13102 #define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT          (16U)
13103 #define CAAM_RTPKRCNT32_PKR_3_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK)
13104 /*! @} */
13105 
13106 /*! @name RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register */
13107 /*! @{ */
13108 
13109 #define CAAM_RTPKRCNT54_PKR_4_CNT_MASK           (0xFFFFU)
13110 #define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT          (0U)
13111 #define CAAM_RTPKRCNT54_PKR_4_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK)
13112 
13113 #define CAAM_RTPKRCNT54_PKR_5_CNT_MASK           (0xFFFF0000U)
13114 #define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT          (16U)
13115 #define CAAM_RTPKRCNT54_PKR_5_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK)
13116 /*! @} */
13117 
13118 /*! @name RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register */
13119 /*! @{ */
13120 
13121 #define CAAM_RTPKRCNT76_PKR_6_CNT_MASK           (0xFFFFU)
13122 #define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT          (0U)
13123 #define CAAM_RTPKRCNT76_PKR_6_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK)
13124 
13125 #define CAAM_RTPKRCNT76_PKR_7_CNT_MASK           (0xFFFF0000U)
13126 #define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT          (16U)
13127 #define CAAM_RTPKRCNT76_PKR_7_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK)
13128 /*! @} */
13129 
13130 /*! @name RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register */
13131 /*! @{ */
13132 
13133 #define CAAM_RTPKRCNT98_PKR_8_CNT_MASK           (0xFFFFU)
13134 #define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT          (0U)
13135 #define CAAM_RTPKRCNT98_PKR_8_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK)
13136 
13137 #define CAAM_RTPKRCNT98_PKR_9_CNT_MASK           (0xFFFF0000U)
13138 #define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT          (16U)
13139 #define CAAM_RTPKRCNT98_PKR_9_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK)
13140 /*! @} */
13141 
13142 /*! @name RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register */
13143 /*! @{ */
13144 
13145 #define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK           (0xFFFFU)
13146 #define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT          (0U)
13147 #define CAAM_RTPKRCNTBA_PKR_A_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK)
13148 
13149 #define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK           (0xFFFF0000U)
13150 #define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT          (16U)
13151 #define CAAM_RTPKRCNTBA_PKR_B_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK)
13152 /*! @} */
13153 
13154 /*! @name RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register */
13155 /*! @{ */
13156 
13157 #define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK           (0xFFFFU)
13158 #define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT          (0U)
13159 #define CAAM_RTPKRCNTDC_PKR_C_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK)
13160 
13161 #define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK           (0xFFFF0000U)
13162 #define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT          (16U)
13163 #define CAAM_RTPKRCNTDC_PKR_D_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK)
13164 /*! @} */
13165 
13166 /*! @name RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register */
13167 /*! @{ */
13168 
13169 #define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK           (0xFFFFU)
13170 #define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT          (0U)
13171 #define CAAM_RTPKRCNTFE_PKR_E_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK)
13172 
13173 #define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK           (0xFFFF0000U)
13174 #define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT          (16U)
13175 #define CAAM_RTPKRCNTFE_PKR_F_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK)
13176 /*! @} */
13177 
13178 /*! @name RDSTA - RNG DRNG Status Register */
13179 /*! @{ */
13180 
13181 #define CAAM_RDSTA_IF0_MASK                      (0x1U)
13182 #define CAAM_RDSTA_IF0_SHIFT                     (0U)
13183 #define CAAM_RDSTA_IF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK)
13184 
13185 #define CAAM_RDSTA_IF1_MASK                      (0x2U)
13186 #define CAAM_RDSTA_IF1_SHIFT                     (1U)
13187 #define CAAM_RDSTA_IF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK)
13188 
13189 #define CAAM_RDSTA_PR0_MASK                      (0x10U)
13190 #define CAAM_RDSTA_PR0_SHIFT                     (4U)
13191 #define CAAM_RDSTA_PR0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK)
13192 
13193 #define CAAM_RDSTA_PR1_MASK                      (0x20U)
13194 #define CAAM_RDSTA_PR1_SHIFT                     (5U)
13195 #define CAAM_RDSTA_PR1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK)
13196 
13197 #define CAAM_RDSTA_TF0_MASK                      (0x100U)
13198 #define CAAM_RDSTA_TF0_SHIFT                     (8U)
13199 #define CAAM_RDSTA_TF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK)
13200 
13201 #define CAAM_RDSTA_TF1_MASK                      (0x200U)
13202 #define CAAM_RDSTA_TF1_SHIFT                     (9U)
13203 #define CAAM_RDSTA_TF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK)
13204 
13205 #define CAAM_RDSTA_ERRCODE_MASK                  (0xF0000U)
13206 #define CAAM_RDSTA_ERRCODE_SHIFT                 (16U)
13207 #define CAAM_RDSTA_ERRCODE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK)
13208 
13209 #define CAAM_RDSTA_CE_MASK                       (0x100000U)
13210 #define CAAM_RDSTA_CE_SHIFT                      (20U)
13211 #define CAAM_RDSTA_CE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK)
13212 
13213 #define CAAM_RDSTA_SKVN_MASK                     (0x40000000U)
13214 #define CAAM_RDSTA_SKVN_SHIFT                    (30U)
13215 #define CAAM_RDSTA_SKVN(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK)
13216 
13217 #define CAAM_RDSTA_SKVT_MASK                     (0x80000000U)
13218 #define CAAM_RDSTA_SKVT_SHIFT                    (31U)
13219 #define CAAM_RDSTA_SKVT(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK)
13220 /*! @} */
13221 
13222 /*! @name RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register */
13223 /*! @{ */
13224 
13225 #define CAAM_RDINT0_RESINT0_MASK                 (0xFFFFFFFFU)
13226 #define CAAM_RDINT0_RESINT0_SHIFT                (0U)
13227 #define CAAM_RDINT0_RESINT0(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK)
13228 /*! @} */
13229 
13230 /*! @name RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register */
13231 /*! @{ */
13232 
13233 #define CAAM_RDINT1_RESINT1_MASK                 (0xFFFFFFFFU)
13234 #define CAAM_RDINT1_RESINT1_SHIFT                (0U)
13235 #define CAAM_RDINT1_RESINT1(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK)
13236 /*! @} */
13237 
13238 /*! @name RDHCNTL - RNG DRNG Hash Control Register */
13239 /*! @{ */
13240 
13241 #define CAAM_RDHCNTL_HD_MASK                     (0x1U)
13242 #define CAAM_RDHCNTL_HD_SHIFT                    (0U)
13243 #define CAAM_RDHCNTL_HD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK)
13244 
13245 #define CAAM_RDHCNTL_HB_MASK                     (0x2U)
13246 #define CAAM_RDHCNTL_HB_SHIFT                    (1U)
13247 #define CAAM_RDHCNTL_HB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK)
13248 
13249 #define CAAM_RDHCNTL_HI_MASK                     (0x4U)
13250 #define CAAM_RDHCNTL_HI_SHIFT                    (2U)
13251 #define CAAM_RDHCNTL_HI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK)
13252 
13253 #define CAAM_RDHCNTL_HTM_MASK                    (0x8U)
13254 #define CAAM_RDHCNTL_HTM_SHIFT                   (3U)
13255 #define CAAM_RDHCNTL_HTM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK)
13256 
13257 #define CAAM_RDHCNTL_HTC_MASK                    (0x10U)
13258 #define CAAM_RDHCNTL_HTC_SHIFT                   (4U)
13259 #define CAAM_RDHCNTL_HTC(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK)
13260 /*! @} */
13261 
13262 /*! @name RDHDIG - RNG DRNG Hash Digest Register */
13263 /*! @{ */
13264 
13265 #define CAAM_RDHDIG_HASHMD_MASK                  (0xFFFFFFFFU)
13266 #define CAAM_RDHDIG_HASHMD_SHIFT                 (0U)
13267 #define CAAM_RDHDIG_HASHMD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK)
13268 /*! @} */
13269 
13270 /*! @name RDHBUF - RNG DRNG Hash Buffer Register */
13271 /*! @{ */
13272 
13273 #define CAAM_RDHBUF_HASHBUF_MASK                 (0xFFFFFFFFU)
13274 #define CAAM_RDHBUF_HASHBUF_SHIFT                (0U)
13275 #define CAAM_RDHBUF_HASHBUF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK)
13276 /*! @} */
13277 
13278 /*! @name PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register */
13279 /*! @{ */
13280 
13281 #define CAAM_PX_SDID_PG0_SDID_MASK               (0xFFFFU)
13282 #define CAAM_PX_SDID_PG0_SDID_SHIFT              (0U)
13283 #define CAAM_PX_SDID_PG0_SDID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK)
13284 /*! @} */
13285 
13286 /* The count of CAAM_PX_SDID_PG0 */
13287 #define CAAM_PX_SDID_PG0_COUNT                   (16U)
13288 
13289 /*! @name PX_SMAPR_PG0 - Secure Memory Access Permissions register */
13290 /*! @{ */
13291 
13292 #define CAAM_PX_SMAPR_PG0_G1_READ_MASK           (0x1U)
13293 #define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT          (0U)
13294 /*! G1_READ
13295  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
13296  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
13297  *       Trusted Descriptor and G1_TDO=1).
13298  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13299  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
13300  */
13301 #define CAAM_PX_SMAPR_PG0_G1_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK)
13302 
13303 #define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK          (0x2U)
13304 #define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT         (1U)
13305 /*! G1_WRITE
13306  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13307  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
13308  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
13309  *       not a Trusted Descriptor or if G1_TDO=0).
13310  */
13311 #define CAAM_PX_SMAPR_PG0_G1_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK)
13312 
13313 #define CAAM_PX_SMAPR_PG0_G1_TDO_MASK            (0x4U)
13314 #define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT           (2U)
13315 /*! G1_TDO
13316  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13317  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13318  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
13319  *       G1_WRITE and G1_READ settings.
13320  */
13321 #define CAAM_PX_SMAPR_PG0_G1_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK)
13322 
13323 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK         (0x8U)
13324 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT        (3U)
13325 /*! G1_SMBLOB
13326  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
13327  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
13328  */
13329 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK)
13330 
13331 #define CAAM_PX_SMAPR_PG0_G2_READ_MASK           (0x10U)
13332 #define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT          (4U)
13333 /*! G2_READ
13334  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
13335  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
13336  *       Trusted Descriptor and G2_TDO=1).
13337  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13338  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
13339  */
13340 #define CAAM_PX_SMAPR_PG0_G2_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK)
13341 
13342 #define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK          (0x20U)
13343 #define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT         (5U)
13344 /*! G2_WRITE
13345  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13346  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
13347  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
13348  *       not a Trusted Descriptor or if G2_TDO=0).
13349  */
13350 #define CAAM_PX_SMAPR_PG0_G2_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK)
13351 
13352 #define CAAM_PX_SMAPR_PG0_G2_TDO_MASK            (0x40U)
13353 #define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT           (6U)
13354 /*! G2_TDO
13355  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13356  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13357  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
13358  *       G2_WRITE and G2_READ settings.
13359  */
13360 #define CAAM_PX_SMAPR_PG0_G2_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK)
13361 
13362 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK         (0x80U)
13363 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT        (7U)
13364 /*! G2_SMBLOB
13365  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
13366  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
13367  */
13368 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK)
13369 
13370 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK          (0x1000U)
13371 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT         (12U)
13372 /*! SMAG_LCK
13373  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
13374  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
13375  *       until the partition is de-allocated or a POR occurs.
13376  */
13377 #define CAAM_PX_SMAPR_PG0_SMAG_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK)
13378 
13379 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK          (0x2000U)
13380 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT         (13U)
13381 /*! SMAP_LCK
13382  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
13383  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
13384  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
13385  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
13386  */
13387 #define CAAM_PX_SMAPR_PG0_SMAP_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK)
13388 
13389 #define CAAM_PX_SMAPR_PG0_PSP_MASK               (0x4000U)
13390 #define CAAM_PX_SMAPR_PG0_PSP_SHIFT              (14U)
13391 /*! PSP
13392  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
13393  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
13394  */
13395 #define CAAM_PX_SMAPR_PG0_PSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK)
13396 
13397 #define CAAM_PX_SMAPR_PG0_CSP_MASK               (0x8000U)
13398 #define CAAM_PX_SMAPR_PG0_CSP_SHIFT              (15U)
13399 /*! CSP
13400  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
13401  *       released or a security alarm occurs.
13402  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
13403  *       partition is released or a security alarm occurs.
13404  */
13405 #define CAAM_PX_SMAPR_PG0_CSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK)
13406 
13407 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK    (0xFFFF0000U)
13408 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT   (16U)
13409 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK)
13410 /*! @} */
13411 
13412 /* The count of CAAM_PX_SMAPR_PG0 */
13413 #define CAAM_PX_SMAPR_PG0_COUNT                  (16U)
13414 
13415 /*! @name PX_SMAG2_PG0 - Secure Memory Access Group Registers */
13416 /*! @{ */
13417 
13418 #define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK           (0x1U)
13419 #define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT          (0U)
13420 #define CAAM_PX_SMAG2_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK)
13421 
13422 #define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK           (0x2U)
13423 #define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT          (1U)
13424 #define CAAM_PX_SMAG2_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK)
13425 
13426 #define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK           (0x4U)
13427 #define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT          (2U)
13428 #define CAAM_PX_SMAG2_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK)
13429 
13430 #define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK           (0x8U)
13431 #define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT          (3U)
13432 #define CAAM_PX_SMAG2_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK)
13433 
13434 #define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK           (0x10U)
13435 #define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT          (4U)
13436 #define CAAM_PX_SMAG2_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK)
13437 
13438 #define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK           (0x20U)
13439 #define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT          (5U)
13440 #define CAAM_PX_SMAG2_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK)
13441 
13442 #define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK           (0x40U)
13443 #define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT          (6U)
13444 #define CAAM_PX_SMAG2_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK)
13445 
13446 #define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK           (0x80U)
13447 #define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT          (7U)
13448 #define CAAM_PX_SMAG2_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK)
13449 
13450 #define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK           (0x100U)
13451 #define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT          (8U)
13452 #define CAAM_PX_SMAG2_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK)
13453 
13454 #define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK           (0x200U)
13455 #define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT          (9U)
13456 #define CAAM_PX_SMAG2_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK)
13457 
13458 #define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK           (0x400U)
13459 #define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT          (10U)
13460 #define CAAM_PX_SMAG2_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK)
13461 
13462 #define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK           (0x800U)
13463 #define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT          (11U)
13464 #define CAAM_PX_SMAG2_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK)
13465 
13466 #define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK           (0x1000U)
13467 #define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT          (12U)
13468 #define CAAM_PX_SMAG2_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK)
13469 
13470 #define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK           (0x2000U)
13471 #define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT          (13U)
13472 #define CAAM_PX_SMAG2_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK)
13473 
13474 #define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK           (0x4000U)
13475 #define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT          (14U)
13476 #define CAAM_PX_SMAG2_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK)
13477 
13478 #define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK           (0x8000U)
13479 #define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT          (15U)
13480 #define CAAM_PX_SMAG2_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK)
13481 
13482 #define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK           (0x10000U)
13483 #define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT          (16U)
13484 #define CAAM_PX_SMAG2_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK)
13485 
13486 #define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK           (0x20000U)
13487 #define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT          (17U)
13488 #define CAAM_PX_SMAG2_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK)
13489 
13490 #define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK           (0x40000U)
13491 #define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT          (18U)
13492 #define CAAM_PX_SMAG2_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK)
13493 
13494 #define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK           (0x80000U)
13495 #define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT          (19U)
13496 #define CAAM_PX_SMAG2_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK)
13497 
13498 #define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK           (0x100000U)
13499 #define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT          (20U)
13500 #define CAAM_PX_SMAG2_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK)
13501 
13502 #define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK           (0x200000U)
13503 #define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT          (21U)
13504 #define CAAM_PX_SMAG2_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK)
13505 
13506 #define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK           (0x400000U)
13507 #define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT          (22U)
13508 #define CAAM_PX_SMAG2_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK)
13509 
13510 #define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK           (0x800000U)
13511 #define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT          (23U)
13512 #define CAAM_PX_SMAG2_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK)
13513 
13514 #define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK           (0x1000000U)
13515 #define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT          (24U)
13516 #define CAAM_PX_SMAG2_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK)
13517 
13518 #define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK           (0x2000000U)
13519 #define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT          (25U)
13520 #define CAAM_PX_SMAG2_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK)
13521 
13522 #define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK           (0x4000000U)
13523 #define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT          (26U)
13524 #define CAAM_PX_SMAG2_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK)
13525 
13526 #define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK           (0x8000000U)
13527 #define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT          (27U)
13528 #define CAAM_PX_SMAG2_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK)
13529 
13530 #define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK           (0x10000000U)
13531 #define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT          (28U)
13532 #define CAAM_PX_SMAG2_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK)
13533 
13534 #define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK           (0x20000000U)
13535 #define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT          (29U)
13536 #define CAAM_PX_SMAG2_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK)
13537 
13538 #define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK           (0x40000000U)
13539 #define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT          (30U)
13540 #define CAAM_PX_SMAG2_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK)
13541 
13542 #define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK           (0x80000000U)
13543 #define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT          (31U)
13544 #define CAAM_PX_SMAG2_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK)
13545 /*! @} */
13546 
13547 /* The count of CAAM_PX_SMAG2_PG0 */
13548 #define CAAM_PX_SMAG2_PG0_COUNT                  (16U)
13549 
13550 /*! @name PX_SMAG1_PG0 - Secure Memory Access Group Registers */
13551 /*! @{ */
13552 
13553 #define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK           (0x1U)
13554 #define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT          (0U)
13555 #define CAAM_PX_SMAG1_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK)
13556 
13557 #define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK           (0x2U)
13558 #define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT          (1U)
13559 #define CAAM_PX_SMAG1_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK)
13560 
13561 #define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK           (0x4U)
13562 #define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT          (2U)
13563 #define CAAM_PX_SMAG1_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK)
13564 
13565 #define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK           (0x8U)
13566 #define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT          (3U)
13567 #define CAAM_PX_SMAG1_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK)
13568 
13569 #define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK           (0x10U)
13570 #define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT          (4U)
13571 #define CAAM_PX_SMAG1_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK)
13572 
13573 #define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK           (0x20U)
13574 #define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT          (5U)
13575 #define CAAM_PX_SMAG1_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK)
13576 
13577 #define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK           (0x40U)
13578 #define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT          (6U)
13579 #define CAAM_PX_SMAG1_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK)
13580 
13581 #define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK           (0x80U)
13582 #define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT          (7U)
13583 #define CAAM_PX_SMAG1_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK)
13584 
13585 #define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK           (0x100U)
13586 #define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT          (8U)
13587 #define CAAM_PX_SMAG1_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK)
13588 
13589 #define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK           (0x200U)
13590 #define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT          (9U)
13591 #define CAAM_PX_SMAG1_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK)
13592 
13593 #define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK           (0x400U)
13594 #define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT          (10U)
13595 #define CAAM_PX_SMAG1_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK)
13596 
13597 #define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK           (0x800U)
13598 #define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT          (11U)
13599 #define CAAM_PX_SMAG1_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK)
13600 
13601 #define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK           (0x1000U)
13602 #define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT          (12U)
13603 #define CAAM_PX_SMAG1_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK)
13604 
13605 #define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK           (0x2000U)
13606 #define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT          (13U)
13607 #define CAAM_PX_SMAG1_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK)
13608 
13609 #define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK           (0x4000U)
13610 #define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT          (14U)
13611 #define CAAM_PX_SMAG1_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK)
13612 
13613 #define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK           (0x8000U)
13614 #define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT          (15U)
13615 #define CAAM_PX_SMAG1_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK)
13616 
13617 #define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK           (0x10000U)
13618 #define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT          (16U)
13619 #define CAAM_PX_SMAG1_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK)
13620 
13621 #define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK           (0x20000U)
13622 #define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT          (17U)
13623 #define CAAM_PX_SMAG1_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK)
13624 
13625 #define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK           (0x40000U)
13626 #define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT          (18U)
13627 #define CAAM_PX_SMAG1_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK)
13628 
13629 #define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK           (0x80000U)
13630 #define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT          (19U)
13631 #define CAAM_PX_SMAG1_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK)
13632 
13633 #define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK           (0x100000U)
13634 #define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT          (20U)
13635 #define CAAM_PX_SMAG1_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK)
13636 
13637 #define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK           (0x200000U)
13638 #define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT          (21U)
13639 #define CAAM_PX_SMAG1_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK)
13640 
13641 #define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK           (0x400000U)
13642 #define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT          (22U)
13643 #define CAAM_PX_SMAG1_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK)
13644 
13645 #define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK           (0x800000U)
13646 #define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT          (23U)
13647 #define CAAM_PX_SMAG1_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK)
13648 
13649 #define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK           (0x1000000U)
13650 #define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT          (24U)
13651 #define CAAM_PX_SMAG1_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK)
13652 
13653 #define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK           (0x2000000U)
13654 #define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT          (25U)
13655 #define CAAM_PX_SMAG1_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK)
13656 
13657 #define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK           (0x4000000U)
13658 #define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT          (26U)
13659 #define CAAM_PX_SMAG1_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK)
13660 
13661 #define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK           (0x8000000U)
13662 #define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT          (27U)
13663 #define CAAM_PX_SMAG1_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK)
13664 
13665 #define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK           (0x10000000U)
13666 #define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT          (28U)
13667 #define CAAM_PX_SMAG1_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK)
13668 
13669 #define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK           (0x20000000U)
13670 #define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT          (29U)
13671 #define CAAM_PX_SMAG1_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK)
13672 
13673 #define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK           (0x40000000U)
13674 #define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT          (30U)
13675 #define CAAM_PX_SMAG1_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK)
13676 
13677 #define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK           (0x80000000U)
13678 #define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT          (31U)
13679 #define CAAM_PX_SMAG1_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK)
13680 /*! @} */
13681 
13682 /* The count of CAAM_PX_SMAG1_PG0 */
13683 #define CAAM_PX_SMAG1_PG0_COUNT                  (16U)
13684 
13685 /*! @name REIS - Recoverable Error Interrupt Status */
13686 /*! @{ */
13687 
13688 #define CAAM_REIS_CWDE_MASK                      (0x1U)
13689 #define CAAM_REIS_CWDE_SHIFT                     (0U)
13690 #define CAAM_REIS_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK)
13691 
13692 #define CAAM_REIS_RBAE_MASK                      (0x10000U)
13693 #define CAAM_REIS_RBAE_SHIFT                     (16U)
13694 #define CAAM_REIS_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK)
13695 
13696 #define CAAM_REIS_JBAE0_MASK                     (0x1000000U)
13697 #define CAAM_REIS_JBAE0_SHIFT                    (24U)
13698 #define CAAM_REIS_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK)
13699 
13700 #define CAAM_REIS_JBAE1_MASK                     (0x2000000U)
13701 #define CAAM_REIS_JBAE1_SHIFT                    (25U)
13702 #define CAAM_REIS_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK)
13703 
13704 #define CAAM_REIS_JBAE2_MASK                     (0x4000000U)
13705 #define CAAM_REIS_JBAE2_SHIFT                    (26U)
13706 #define CAAM_REIS_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK)
13707 
13708 #define CAAM_REIS_JBAE3_MASK                     (0x8000000U)
13709 #define CAAM_REIS_JBAE3_SHIFT                    (27U)
13710 #define CAAM_REIS_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK)
13711 /*! @} */
13712 
13713 /*! @name REIE - Recoverable Error Interrupt Enable */
13714 /*! @{ */
13715 
13716 #define CAAM_REIE_CWDE_MASK                      (0x1U)
13717 #define CAAM_REIE_CWDE_SHIFT                     (0U)
13718 #define CAAM_REIE_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK)
13719 
13720 #define CAAM_REIE_RBAE_MASK                      (0x10000U)
13721 #define CAAM_REIE_RBAE_SHIFT                     (16U)
13722 #define CAAM_REIE_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK)
13723 
13724 #define CAAM_REIE_JBAE0_MASK                     (0x1000000U)
13725 #define CAAM_REIE_JBAE0_SHIFT                    (24U)
13726 #define CAAM_REIE_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK)
13727 
13728 #define CAAM_REIE_JBAE1_MASK                     (0x2000000U)
13729 #define CAAM_REIE_JBAE1_SHIFT                    (25U)
13730 #define CAAM_REIE_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK)
13731 
13732 #define CAAM_REIE_JBAE2_MASK                     (0x4000000U)
13733 #define CAAM_REIE_JBAE2_SHIFT                    (26U)
13734 #define CAAM_REIE_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK)
13735 
13736 #define CAAM_REIE_JBAE3_MASK                     (0x8000000U)
13737 #define CAAM_REIE_JBAE3_SHIFT                    (27U)
13738 #define CAAM_REIE_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK)
13739 /*! @} */
13740 
13741 /*! @name REIF - Recoverable Error Interrupt Force */
13742 /*! @{ */
13743 
13744 #define CAAM_REIF_CWDE_MASK                      (0x1U)
13745 #define CAAM_REIF_CWDE_SHIFT                     (0U)
13746 #define CAAM_REIF_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK)
13747 
13748 #define CAAM_REIF_RBAE_MASK                      (0x10000U)
13749 #define CAAM_REIF_RBAE_SHIFT                     (16U)
13750 #define CAAM_REIF_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK)
13751 
13752 #define CAAM_REIF_JBAE0_MASK                     (0x1000000U)
13753 #define CAAM_REIF_JBAE0_SHIFT                    (24U)
13754 #define CAAM_REIF_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK)
13755 
13756 #define CAAM_REIF_JBAE1_MASK                     (0x2000000U)
13757 #define CAAM_REIF_JBAE1_SHIFT                    (25U)
13758 #define CAAM_REIF_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK)
13759 
13760 #define CAAM_REIF_JBAE2_MASK                     (0x4000000U)
13761 #define CAAM_REIF_JBAE2_SHIFT                    (26U)
13762 #define CAAM_REIF_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK)
13763 
13764 #define CAAM_REIF_JBAE3_MASK                     (0x8000000U)
13765 #define CAAM_REIF_JBAE3_SHIFT                    (27U)
13766 #define CAAM_REIF_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK)
13767 /*! @} */
13768 
13769 /*! @name REIH - Recoverable Error Interrupt Halt */
13770 /*! @{ */
13771 
13772 #define CAAM_REIH_CWDE_MASK                      (0x1U)
13773 #define CAAM_REIH_CWDE_SHIFT                     (0U)
13774 /*! CWDE
13775  *  0b0..Don't halt CAAM if CAAM watchdog expired.
13776  *  0b1..Halt CAAM if CAAM watchdog expired..
13777  */
13778 #define CAAM_REIH_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK)
13779 
13780 #define CAAM_REIH_RBAE_MASK                      (0x10000U)
13781 #define CAAM_REIH_RBAE_SHIFT                     (16U)
13782 /*! RBAE
13783  *  0b0..Don't halt CAAM if RTIC-initiated job execution caused bus access error.
13784  *  0b1..Halt CAAM if RTIC-initiated job execution caused bus access error.
13785  */
13786 #define CAAM_REIH_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK)
13787 
13788 #define CAAM_REIH_JBAE0_MASK                     (0x1000000U)
13789 #define CAAM_REIH_JBAE0_SHIFT                    (24U)
13790 /*! JBAE0
13791  *  0b0..Don't halt CAAM if JR0-initiated job execution caused bus access error.
13792  *  0b1..Halt CAAM if JR0-initiated job execution caused bus access error.
13793  */
13794 #define CAAM_REIH_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK)
13795 
13796 #define CAAM_REIH_JBAE1_MASK                     (0x2000000U)
13797 #define CAAM_REIH_JBAE1_SHIFT                    (25U)
13798 /*! JBAE1
13799  *  0b0..Don't halt CAAM if JR1-initiated job execution caused bus access error.
13800  *  0b1..Halt CAAM if JR1-initiated job execution caused bus access error.
13801  */
13802 #define CAAM_REIH_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK)
13803 
13804 #define CAAM_REIH_JBAE2_MASK                     (0x4000000U)
13805 #define CAAM_REIH_JBAE2_SHIFT                    (26U)
13806 /*! JBAE2
13807  *  0b0..Don't halt CAAM if JR2-initiated job execution caused bus access error.
13808  *  0b1..Halt CAAM if JR2-initiated job execution caused bus access error.
13809  */
13810 #define CAAM_REIH_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK)
13811 
13812 #define CAAM_REIH_JBAE3_MASK                     (0x8000000U)
13813 #define CAAM_REIH_JBAE3_SHIFT                    (27U)
13814 /*! JBAE3
13815  *  0b0..Don't halt CAAM if JR3-initiated job execution caused bus access error.
13816  *  0b1..Halt CAAM if JR3-initiated job execution caused bus access error.
13817  */
13818 #define CAAM_REIH_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK)
13819 /*! @} */
13820 
13821 /*! @name SMWPJRR - Secure Memory Write Protect Job Ring Register */
13822 /*! @{ */
13823 
13824 #define CAAM_SMWPJRR_SMR_WP_JRa_MASK             (0x1U)
13825 #define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT            (0U)
13826 #define CAAM_SMWPJRR_SMR_WP_JRa(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK)
13827 /*! @} */
13828 
13829 /* The count of CAAM_SMWPJRR */
13830 #define CAAM_SMWPJRR_COUNT                       (4U)
13831 
13832 /*! @name SMCR_PG0 - Secure Memory Command Register */
13833 /*! @{ */
13834 
13835 #define CAAM_SMCR_PG0_CMD_MASK                   (0xFU)
13836 #define CAAM_SMCR_PG0_CMD_SHIFT                  (0U)
13837 #define CAAM_SMCR_PG0_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK)
13838 
13839 #define CAAM_SMCR_PG0_PRTN_MASK                  (0xF00U)
13840 #define CAAM_SMCR_PG0_PRTN_SHIFT                 (8U)
13841 #define CAAM_SMCR_PG0_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK)
13842 
13843 #define CAAM_SMCR_PG0_PAGE_MASK                  (0xFFFF0000U)
13844 #define CAAM_SMCR_PG0_PAGE_SHIFT                 (16U)
13845 #define CAAM_SMCR_PG0_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK)
13846 /*! @} */
13847 
13848 /*! @name SMCSR_PG0 - Secure Memory Command Status Register */
13849 /*! @{ */
13850 
13851 #define CAAM_SMCSR_PG0_PRTN_MASK                 (0xFU)
13852 #define CAAM_SMCSR_PG0_PRTN_SHIFT                (0U)
13853 #define CAAM_SMCSR_PG0_PRTN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK)
13854 
13855 #define CAAM_SMCSR_PG0_PO_MASK                   (0xC0U)
13856 #define CAAM_SMCSR_PG0_PO_SHIFT                  (6U)
13857 /*! PO
13858  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
13859  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
13860  *  0b01..Page does not exist in this version or is not initialized yet.
13861  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
13862  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
13863  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
13864  *        upon de-allocation.
13865  */
13866 #define CAAM_SMCSR_PG0_PO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK)
13867 
13868 #define CAAM_SMCSR_PG0_AERR_MASK                 (0x3000U)
13869 #define CAAM_SMCSR_PG0_AERR_SHIFT                (12U)
13870 #define CAAM_SMCSR_PG0_AERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK)
13871 
13872 #define CAAM_SMCSR_PG0_CERR_MASK                 (0xC000U)
13873 #define CAAM_SMCSR_PG0_CERR_SHIFT                (14U)
13874 /*! CERR
13875  *  0b00..No Error.
13876  *  0b01..Command has not yet completed.
13877  *  0b10..A security failure occurred.
13878  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
13879  *        command completed. The additional command was ignored.
13880  */
13881 #define CAAM_SMCSR_PG0_CERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK)
13882 
13883 #define CAAM_SMCSR_PG0_PAGE_MASK                 (0xFFF0000U)
13884 #define CAAM_SMCSR_PG0_PAGE_SHIFT                (16U)
13885 #define CAAM_SMCSR_PG0_PAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK)
13886 /*! @} */
13887 
13888 /*! @name CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half */
13889 /*! @{ */
13890 
13891 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK        (0xFFU)
13892 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT       (0U)
13893 #define CAAM_CAAMVID_MS_TRAD_MIN_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK)
13894 
13895 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK        (0xFF00U)
13896 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT       (8U)
13897 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK)
13898 
13899 #define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK          (0xFFFF0000U)
13900 #define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT         (16U)
13901 #define CAAM_CAAMVID_MS_TRAD_IP_ID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK)
13902 /*! @} */
13903 
13904 /*! @name CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half */
13905 /*! @{ */
13906 
13907 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK     (0xFFU)
13908 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT    (0U)
13909 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK)
13910 
13911 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK        (0xFF00U)
13912 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT       (8U)
13913 #define CAAM_CAAMVID_LS_TRAD_ECO_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK)
13914 
13915 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK       (0xFF0000U)
13916 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT      (16U)
13917 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK)
13918 
13919 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK    (0xFF000000U)
13920 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT   (24U)
13921 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK)
13922 /*! @} */
13923 
13924 /*! @name HT_JD_ADDR - Holding Tank 0 Job Descriptor Address */
13925 /*! @{ */
13926 
13927 #define CAAM_HT_JD_ADDR_JD_ADDR_MASK             (0xFFFFFFFFFU)
13928 #define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT            (0U)
13929 #define CAAM_HT_JD_ADDR_JD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK)
13930 /*! @} */
13931 
13932 /* The count of CAAM_HT_JD_ADDR */
13933 #define CAAM_HT_JD_ADDR_COUNT                    (1U)
13934 
13935 /*! @name HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address */
13936 /*! @{ */
13937 
13938 #define CAAM_HT_SD_ADDR_SD_ADDR_MASK             (0xFFFFFFFFFU)
13939 #define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT            (0U)
13940 #define CAAM_HT_SD_ADDR_SD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK)
13941 /*! @} */
13942 
13943 /* The count of CAAM_HT_SD_ADDR */
13944 #define CAAM_HT_SD_ADDR_COUNT                    (1U)
13945 
13946 /*! @name HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half */
13947 /*! @{ */
13948 
13949 #define CAAM_HT_JQ_CTRL_MS_ID_MASK               (0x7U)
13950 #define CAAM_HT_JQ_CTRL_MS_ID_SHIFT              (0U)
13951 #define CAAM_HT_JQ_CTRL_MS_ID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK)
13952 
13953 #define CAAM_HT_JQ_CTRL_MS_SRC_MASK              (0x700U)
13954 #define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT             (8U)
13955 /*! SRC
13956  *  0b000..Job Ring 0
13957  *  0b001..Job Ring 1
13958  *  0b010..Job Ring 2
13959  *  0b011..Job Ring 3
13960  *  0b100..RTIC
13961  *  0b101..Reserved
13962  *  0b110..Reserved
13963  *  0b111..Reserved
13964  */
13965 #define CAAM_HT_JQ_CTRL_MS_SRC(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK)
13966 
13967 #define CAAM_HT_JQ_CTRL_MS_JDDS_MASK             (0x4000U)
13968 #define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT            (14U)
13969 /*! JDDS
13970  *  0b1..SEQ DID
13971  *  0b0..Non-SEQ DID
13972  */
13973 #define CAAM_HT_JQ_CTRL_MS_JDDS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK)
13974 
13975 #define CAAM_HT_JQ_CTRL_MS_AMTD_MASK             (0x8000U)
13976 #define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT            (15U)
13977 #define CAAM_HT_JQ_CTRL_MS_AMTD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK)
13978 
13979 #define CAAM_HT_JQ_CTRL_MS_SOB_MASK              (0x10000U)
13980 #define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT             (16U)
13981 #define CAAM_HT_JQ_CTRL_MS_SOB(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK)
13982 
13983 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK         (0x60000U)
13984 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT        (17U)
13985 /*! HT_ERROR
13986  *  0b00..No error
13987  *  0b01..Job Descriptor or Shared Descriptor length error
13988  *  0b10..AXI_error while reading a Job Ring Shared Descriptor or the remainder of a Job Ring Job Descriptor
13989  *  0b11..reserved
13990  */
13991 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK)
13992 
13993 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK       (0x80000U)
13994 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT      (19U)
13995 /*! DWORD_SWAP
13996  *  0b0..DWords are in the order most-significant word, least-significant word.
13997  *  0b1..DWords are in the order least-significant word, most-significant word.
13998  */
13999 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK)
14000 
14001 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK         (0x7C00000U)
14002 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT        (22U)
14003 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK)
14004 
14005 #define CAAM_HT_JQ_CTRL_MS_ILE_MASK              (0x8000000U)
14006 #define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT             (27U)
14007 /*! ILE
14008  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
14009  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
14010  */
14011 #define CAAM_HT_JQ_CTRL_MS_ILE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK)
14012 
14013 #define CAAM_HT_JQ_CTRL_MS_FOUR_MASK             (0x10000000U)
14014 #define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT            (28U)
14015 #define CAAM_HT_JQ_CTRL_MS_FOUR(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK)
14016 
14017 #define CAAM_HT_JQ_CTRL_MS_WHL_MASK              (0x20000000U)
14018 #define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT             (29U)
14019 #define CAAM_HT_JQ_CTRL_MS_WHL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK)
14020 /*! @} */
14021 
14022 /* The count of CAAM_HT_JQ_CTRL_MS */
14023 #define CAAM_HT_JQ_CTRL_MS_COUNT                 (1U)
14024 
14025 /*! @name HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half */
14026 /*! @{ */
14027 
14028 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK         (0xFU)
14029 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT        (0U)
14030 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK)
14031 
14032 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK          (0x10U)
14033 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT         (4U)
14034 /*! PRIM_TZ
14035  *  0b0..TrustZone NonSecureWorld
14036  *  0b1..TrustZone SecureWorld
14037  */
14038 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK)
14039 
14040 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK        (0xFFE0U)
14041 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT       (5U)
14042 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK)
14043 
14044 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK          (0xF0000U)
14045 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT         (16U)
14046 #define CAAM_HT_JQ_CTRL_LS_OUT_DID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK)
14047 
14048 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK         (0xFFE00000U)
14049 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT        (21U)
14050 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK)
14051 /*! @} */
14052 
14053 /* The count of CAAM_HT_JQ_CTRL_LS */
14054 #define CAAM_HT_JQ_CTRL_LS_COUNT                 (1U)
14055 
14056 /*! @name HT_STATUS - Holding Tank Status */
14057 /*! @{ */
14058 
14059 #define CAAM_HT_STATUS_PEND_0_MASK               (0x1U)
14060 #define CAAM_HT_STATUS_PEND_0_SHIFT              (0U)
14061 #define CAAM_HT_STATUS_PEND_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK)
14062 
14063 #define CAAM_HT_STATUS_IN_USE_MASK               (0x40000000U)
14064 #define CAAM_HT_STATUS_IN_USE_SHIFT              (30U)
14065 #define CAAM_HT_STATUS_IN_USE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK)
14066 
14067 #define CAAM_HT_STATUS_BC_MASK                   (0x80000000U)
14068 #define CAAM_HT_STATUS_BC_SHIFT                  (31U)
14069 #define CAAM_HT_STATUS_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK)
14070 /*! @} */
14071 
14072 /* The count of CAAM_HT_STATUS */
14073 #define CAAM_HT_STATUS_COUNT                     (1U)
14074 
14075 /*! @name JQ_DEBUG_SEL - Job Queue Debug Select Register */
14076 /*! @{ */
14077 
14078 #define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK            (0x1U)
14079 #define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT           (0U)
14080 #define CAAM_JQ_DEBUG_SEL_HT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK)
14081 
14082 #define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK            (0x70000U)
14083 #define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT           (16U)
14084 #define CAAM_JQ_DEBUG_SEL_JOB_ID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK)
14085 /*! @} */
14086 
14087 /*! @name JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half */
14088 /*! @{ */
14089 
14090 #define CAAM_JRJIDU_LS_JID00_MASK                (0x1U)
14091 #define CAAM_JRJIDU_LS_JID00_SHIFT               (0U)
14092 #define CAAM_JRJIDU_LS_JID00(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK)
14093 
14094 #define CAAM_JRJIDU_LS_JID01_MASK                (0x2U)
14095 #define CAAM_JRJIDU_LS_JID01_SHIFT               (1U)
14096 #define CAAM_JRJIDU_LS_JID01(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK)
14097 
14098 #define CAAM_JRJIDU_LS_JID02_MASK                (0x4U)
14099 #define CAAM_JRJIDU_LS_JID02_SHIFT               (2U)
14100 #define CAAM_JRJIDU_LS_JID02(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK)
14101 
14102 #define CAAM_JRJIDU_LS_JID03_MASK                (0x8U)
14103 #define CAAM_JRJIDU_LS_JID03_SHIFT               (3U)
14104 #define CAAM_JRJIDU_LS_JID03(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK)
14105 /*! @} */
14106 
14107 /*! @name JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC */
14108 /*! @{ */
14109 
14110 #define CAAM_JRJDJIFBC_BC_MASK                   (0x80000000U)
14111 #define CAAM_JRJDJIFBC_BC_SHIFT                  (31U)
14112 #define CAAM_JRJDJIFBC_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK)
14113 /*! @} */
14114 
14115 /*! @name JRJDJIF - Job Ring Job-Done Job ID FIFO */
14116 /*! @{ */
14117 
14118 #define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK           (0x7U)
14119 #define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT          (0U)
14120 #define CAAM_JRJDJIF_JOB_ID_ENTRY(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK)
14121 /*! @} */
14122 
14123 /*! @name JRJDS1 - Job Ring Job-Done Source 1 */
14124 /*! @{ */
14125 
14126 #define CAAM_JRJDS1_SRC_MASK                     (0x3U)
14127 #define CAAM_JRJDS1_SRC_SHIFT                    (0U)
14128 #define CAAM_JRJDS1_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK)
14129 
14130 #define CAAM_JRJDS1_VALID_MASK                   (0x80000000U)
14131 #define CAAM_JRJDS1_VALID_SHIFT                  (31U)
14132 #define CAAM_JRJDS1_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK)
14133 /*! @} */
14134 
14135 /*! @name JRJDDA - Job Ring Job-Done Descriptor Address 0 Register */
14136 /*! @{ */
14137 
14138 #define CAAM_JRJDDA_JD_ADDR_MASK                 (0xFFFFFFFFFU)
14139 #define CAAM_JRJDDA_JD_ADDR_SHIFT                (0U)
14140 #define CAAM_JRJDDA_JD_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK)
14141 /*! @} */
14142 
14143 /* The count of CAAM_JRJDDA */
14144 #define CAAM_JRJDDA_COUNT                        (1U)
14145 
14146 /*! @name CRNR_MS - CHA Revision Number Register, most-significant half */
14147 /*! @{ */
14148 
14149 #define CAAM_CRNR_MS_CRCRN_MASK                  (0xFU)
14150 #define CAAM_CRNR_MS_CRCRN_SHIFT                 (0U)
14151 #define CAAM_CRNR_MS_CRCRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK)
14152 
14153 #define CAAM_CRNR_MS_SNW9RN_MASK                 (0xF0U)
14154 #define CAAM_CRNR_MS_SNW9RN_SHIFT                (4U)
14155 #define CAAM_CRNR_MS_SNW9RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK)
14156 
14157 #define CAAM_CRNR_MS_ZERN_MASK                   (0xF00U)
14158 #define CAAM_CRNR_MS_ZERN_SHIFT                  (8U)
14159 #define CAAM_CRNR_MS_ZERN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK)
14160 
14161 #define CAAM_CRNR_MS_ZARN_MASK                   (0xF000U)
14162 #define CAAM_CRNR_MS_ZARN_SHIFT                  (12U)
14163 #define CAAM_CRNR_MS_ZARN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK)
14164 
14165 #define CAAM_CRNR_MS_DECORN_MASK                 (0xF000000U)
14166 #define CAAM_CRNR_MS_DECORN_SHIFT                (24U)
14167 #define CAAM_CRNR_MS_DECORN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK)
14168 
14169 #define CAAM_CRNR_MS_JRRN_MASK                   (0xF0000000U)
14170 #define CAAM_CRNR_MS_JRRN_SHIFT                  (28U)
14171 #define CAAM_CRNR_MS_JRRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK)
14172 /*! @} */
14173 
14174 /*! @name CRNR_LS - CHA Revision Number Register, least-significant half */
14175 /*! @{ */
14176 
14177 #define CAAM_CRNR_LS_AESRN_MASK                  (0xFU)
14178 #define CAAM_CRNR_LS_AESRN_SHIFT                 (0U)
14179 #define CAAM_CRNR_LS_AESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK)
14180 
14181 #define CAAM_CRNR_LS_DESRN_MASK                  (0xF0U)
14182 #define CAAM_CRNR_LS_DESRN_SHIFT                 (4U)
14183 #define CAAM_CRNR_LS_DESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK)
14184 
14185 #define CAAM_CRNR_LS_MDRN_MASK                   (0xF000U)
14186 #define CAAM_CRNR_LS_MDRN_SHIFT                  (12U)
14187 #define CAAM_CRNR_LS_MDRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK)
14188 
14189 #define CAAM_CRNR_LS_RNGRN_MASK                  (0xF0000U)
14190 #define CAAM_CRNR_LS_RNGRN_SHIFT                 (16U)
14191 #define CAAM_CRNR_LS_RNGRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK)
14192 
14193 #define CAAM_CRNR_LS_SNW8RN_MASK                 (0xF00000U)
14194 #define CAAM_CRNR_LS_SNW8RN_SHIFT                (20U)
14195 #define CAAM_CRNR_LS_SNW8RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK)
14196 
14197 #define CAAM_CRNR_LS_KASRN_MASK                  (0xF000000U)
14198 #define CAAM_CRNR_LS_KASRN_SHIFT                 (24U)
14199 #define CAAM_CRNR_LS_KASRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK)
14200 
14201 #define CAAM_CRNR_LS_PKRN_MASK                   (0xF0000000U)
14202 #define CAAM_CRNR_LS_PKRN_SHIFT                  (28U)
14203 /*! PKRN
14204  *  0b0000..PKHA-SDv1
14205  *  0b0001..PKHA-SDv2
14206  *  0b0010..PKHA-SDv3
14207  *  0b0011..PKHA-SDv4
14208  */
14209 #define CAAM_CRNR_LS_PKRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK)
14210 /*! @} */
14211 
14212 /*! @name CTPR_MS - Compile Time Parameters Register, most-significant half */
14213 /*! @{ */
14214 
14215 #define CAAM_CTPR_MS_VIRT_EN_INCL_MASK           (0x1U)
14216 #define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT          (0U)
14217 #define CAAM_CTPR_MS_VIRT_EN_INCL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK)
14218 
14219 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK      (0x2U)
14220 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT     (1U)
14221 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK)
14222 
14223 #define CAAM_CTPR_MS_REG_PG_SIZE_MASK            (0x10U)
14224 #define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT           (4U)
14225 #define CAAM_CTPR_MS_REG_PG_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK)
14226 
14227 #define CAAM_CTPR_MS_RNG_I_MASK                  (0x700U)
14228 #define CAAM_CTPR_MS_RNG_I_SHIFT                 (8U)
14229 #define CAAM_CTPR_MS_RNG_I(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK)
14230 
14231 #define CAAM_CTPR_MS_AI_INCL_MASK                (0x800U)
14232 #define CAAM_CTPR_MS_AI_INCL_SHIFT               (11U)
14233 #define CAAM_CTPR_MS_AI_INCL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK)
14234 
14235 #define CAAM_CTPR_MS_DPAA2_MASK                  (0x2000U)
14236 #define CAAM_CTPR_MS_DPAA2_SHIFT                 (13U)
14237 #define CAAM_CTPR_MS_DPAA2(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK)
14238 
14239 #define CAAM_CTPR_MS_IP_CLK_MASK                 (0x4000U)
14240 #define CAAM_CTPR_MS_IP_CLK_SHIFT                (14U)
14241 #define CAAM_CTPR_MS_IP_CLK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK)
14242 
14243 #define CAAM_CTPR_MS_MCFG_BURST_MASK             (0x10000U)
14244 #define CAAM_CTPR_MS_MCFG_BURST_SHIFT            (16U)
14245 #define CAAM_CTPR_MS_MCFG_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK)
14246 
14247 #define CAAM_CTPR_MS_MCFG_PS_MASK                (0x20000U)
14248 #define CAAM_CTPR_MS_MCFG_PS_SHIFT               (17U)
14249 #define CAAM_CTPR_MS_MCFG_PS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK)
14250 
14251 #define CAAM_CTPR_MS_SG8_MASK                    (0x40000U)
14252 #define CAAM_CTPR_MS_SG8_SHIFT                   (18U)
14253 #define CAAM_CTPR_MS_SG8(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK)
14254 
14255 #define CAAM_CTPR_MS_PM_EVT_BUS_MASK             (0x80000U)
14256 #define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT            (19U)
14257 #define CAAM_CTPR_MS_PM_EVT_BUS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK)
14258 
14259 #define CAAM_CTPR_MS_DECO_WD_MASK                (0x100000U)
14260 #define CAAM_CTPR_MS_DECO_WD_SHIFT               (20U)
14261 #define CAAM_CTPR_MS_DECO_WD(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK)
14262 
14263 #define CAAM_CTPR_MS_PC_MASK                     (0x200000U)
14264 #define CAAM_CTPR_MS_PC_SHIFT                    (21U)
14265 #define CAAM_CTPR_MS_PC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK)
14266 
14267 #define CAAM_CTPR_MS_C1C2_MASK                   (0x800000U)
14268 #define CAAM_CTPR_MS_C1C2_SHIFT                  (23U)
14269 #define CAAM_CTPR_MS_C1C2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK)
14270 
14271 #define CAAM_CTPR_MS_ACC_CTL_MASK                (0x1000000U)
14272 #define CAAM_CTPR_MS_ACC_CTL_SHIFT               (24U)
14273 #define CAAM_CTPR_MS_ACC_CTL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK)
14274 
14275 #define CAAM_CTPR_MS_QI_MASK                     (0x2000000U)
14276 #define CAAM_CTPR_MS_QI_SHIFT                    (25U)
14277 #define CAAM_CTPR_MS_QI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK)
14278 
14279 #define CAAM_CTPR_MS_AXI_PRI_MASK                (0x4000000U)
14280 #define CAAM_CTPR_MS_AXI_PRI_SHIFT               (26U)
14281 #define CAAM_CTPR_MS_AXI_PRI(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK)
14282 
14283 #define CAAM_CTPR_MS_AXI_LIODN_MASK              (0x8000000U)
14284 #define CAAM_CTPR_MS_AXI_LIODN_SHIFT             (27U)
14285 #define CAAM_CTPR_MS_AXI_LIODN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK)
14286 
14287 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK         (0xF0000000U)
14288 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT        (28U)
14289 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK)
14290 /*! @} */
14291 
14292 /*! @name CTPR_LS - Compile Time Parameters Register, least-significant half */
14293 /*! @{ */
14294 
14295 #define CAAM_CTPR_LS_KG_DS_MASK                  (0x1U)
14296 #define CAAM_CTPR_LS_KG_DS_SHIFT                 (0U)
14297 /*! KG_DS
14298  *  0b0..CAAM does not implement specialized support for Public Key Generation and Digital Signatures.
14299  *  0b1..CAAM implements specialized support for Public Key Generation and Digital Signatures.
14300  */
14301 #define CAAM_CTPR_LS_KG_DS(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK)
14302 
14303 #define CAAM_CTPR_LS_BLOB_MASK                   (0x2U)
14304 #define CAAM_CTPR_LS_BLOB_SHIFT                  (1U)
14305 /*! BLOB
14306  *  0b0..CAAM does not implement specialized support for encapsulating and decapsulating cryptographic blobs.
14307  *  0b1..CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs.
14308  */
14309 #define CAAM_CTPR_LS_BLOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK)
14310 
14311 #define CAAM_CTPR_LS_WIFI_MASK                   (0x4U)
14312 #define CAAM_CTPR_LS_WIFI_SHIFT                  (2U)
14313 /*! WIFI
14314  *  0b0..CAAM does not implement specialized support for the WIFI protocol.
14315  *  0b1..CAAM implements specialized support for the WIFI protocol.
14316  */
14317 #define CAAM_CTPR_LS_WIFI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK)
14318 
14319 #define CAAM_CTPR_LS_WIMAX_MASK                  (0x8U)
14320 #define CAAM_CTPR_LS_WIMAX_SHIFT                 (3U)
14321 /*! WIMAX
14322  *  0b0..CAAM does not implement specialized support for the WIMAX protocol.
14323  *  0b1..CAAM implements specialized support for the WIMAX protocol.
14324  */
14325 #define CAAM_CTPR_LS_WIMAX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK)
14326 
14327 #define CAAM_CTPR_LS_SRTP_MASK                   (0x10U)
14328 #define CAAM_CTPR_LS_SRTP_SHIFT                  (4U)
14329 /*! SRTP
14330  *  0b0..CAAM does not implement specialized support for the SRTP protocol.
14331  *  0b1..CAAM implements specialized support for the SRTP protocol.
14332  */
14333 #define CAAM_CTPR_LS_SRTP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK)
14334 
14335 #define CAAM_CTPR_LS_IPSEC_MASK                  (0x20U)
14336 #define CAAM_CTPR_LS_IPSEC_SHIFT                 (5U)
14337 /*! IPSEC
14338  *  0b0..CAAM does not implement specialized support for the IPSEC protocol.
14339  *  0b1..CAAM implements specialized support for the IPSEC protocol.
14340  */
14341 #define CAAM_CTPR_LS_IPSEC(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK)
14342 
14343 #define CAAM_CTPR_LS_IKE_MASK                    (0x40U)
14344 #define CAAM_CTPR_LS_IKE_SHIFT                   (6U)
14345 /*! IKE
14346  *  0b0..CAAM does not implement specialized support for the IKE protocol.
14347  *  0b1..CAAM implements specialized support for the IKE protocol.
14348  */
14349 #define CAAM_CTPR_LS_IKE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK)
14350 
14351 #define CAAM_CTPR_LS_SSL_TLS_MASK                (0x80U)
14352 #define CAAM_CTPR_LS_SSL_TLS_SHIFT               (7U)
14353 /*! SSL_TLS
14354  *  0b0..CAAM does not implement specialized support for the SSL and TLS protocols.
14355  *  0b1..CAAM implements specialized support for the SSL and TLS protocols.
14356  */
14357 #define CAAM_CTPR_LS_SSL_TLS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK)
14358 
14359 #define CAAM_CTPR_LS_TLS_PRF_MASK                (0x100U)
14360 #define CAAM_CTPR_LS_TLS_PRF_SHIFT               (8U)
14361 /*! TLS_PRF
14362  *  0b0..CAAM does not implement specialized support for the TLS protocol pseudo-random function.
14363  *  0b1..CAAM implements specialized support for the TLS protocol pseudo-random function.
14364  */
14365 #define CAAM_CTPR_LS_TLS_PRF(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK)
14366 
14367 #define CAAM_CTPR_LS_MACSEC_MASK                 (0x200U)
14368 #define CAAM_CTPR_LS_MACSEC_SHIFT                (9U)
14369 /*! MACSEC
14370  *  0b0..CAAM does not implement specialized support for the MACSEC protocol.
14371  *  0b1..CAAM implements specialized support for the MACSEC protocol.
14372  */
14373 #define CAAM_CTPR_LS_MACSEC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK)
14374 
14375 #define CAAM_CTPR_LS_RSA_MASK                    (0x400U)
14376 #define CAAM_CTPR_LS_RSA_SHIFT                   (10U)
14377 /*! RSA
14378  *  0b0..CAAM does not implement specialized support for RSA encrypt and decrypt operations.
14379  *  0b1..CAAM implements specialized support for RSA encrypt and decrypt operations.
14380  */
14381 #define CAAM_CTPR_LS_RSA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK)
14382 
14383 #define CAAM_CTPR_LS_P3G_LTE_MASK                (0x800U)
14384 #define CAAM_CTPR_LS_P3G_LTE_SHIFT               (11U)
14385 /*! P3G_LTE
14386  *  0b0..CAAM does not implement specialized support for 3G and LTE protocols.
14387  *  0b1..CAAM implements specialized support for 3G and LTE protocols.
14388  */
14389 #define CAAM_CTPR_LS_P3G_LTE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK)
14390 
14391 #define CAAM_CTPR_LS_DBL_CRC_MASK                (0x1000U)
14392 #define CAAM_CTPR_LS_DBL_CRC_SHIFT               (12U)
14393 /*! DBL_CRC
14394  *  0b0..CAAM does not implement specialized support for Double CRC.
14395  *  0b1..CAAM implements specialized support for Double CRC.
14396  */
14397 #define CAAM_CTPR_LS_DBL_CRC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK)
14398 
14399 #define CAAM_CTPR_LS_MAN_PROT_MASK               (0x2000U)
14400 #define CAAM_CTPR_LS_MAN_PROT_SHIFT              (13U)
14401 /*! MAN_PROT
14402  *  0b0..CAAM does not implement Manufacturing Protection functions.
14403  *  0b1..CAAM implements Manufacturing Protection functions.
14404  */
14405 #define CAAM_CTPR_LS_MAN_PROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK)
14406 
14407 #define CAAM_CTPR_LS_DKP_MASK                    (0x4000U)
14408 #define CAAM_CTPR_LS_DKP_SHIFT                   (14U)
14409 /*! DKP
14410  *  0b0..CAAM does not implement the Derived Key Protocol.
14411  *  0b1..CAAM implements the Derived Key Protocol.
14412  */
14413 #define CAAM_CTPR_LS_DKP(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK)
14414 /*! @} */
14415 
14416 /*! @name SMSTA - Secure Memory Status Register */
14417 /*! @{ */
14418 
14419 #define CAAM_SMSTA_STATE_MASK                    (0xFU)
14420 #define CAAM_SMSTA_STATE_SHIFT                   (0U)
14421 /*! STATE
14422  *  0b0000..Reset State
14423  *  0b0001..Initialize State
14424  *  0b0010..Normal State
14425  *  0b0011..Fail State
14426  */
14427 #define CAAM_SMSTA_STATE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK)
14428 
14429 #define CAAM_SMSTA_ACCERR_MASK                   (0xF0U)
14430 #define CAAM_SMSTA_ACCERR_SHIFT                  (4U)
14431 /*! ACCERR
14432  *  0b0000..No error occurred
14433  *  0b0001..A bus transaction attempted to access a page in Secure Memory, but the page was not allocated to any partition.
14434  *  0b0010..A bus transaction attempted to access a partition, but the transaction's TrustZone World, DID was not
14435  *          granted access to the partition in the partition's SMAG2/1JR registers.
14436  *  0b0011..A bus transaction attempted to read, but reads from this partition are not allowed.
14437  *  0b0100..A bus transaction attempted to write, but writes to this partition are not allowed.
14438  *  0b0110..A bus transaction attempted a non-key read, but the only reads permitted from this partition are key reads.
14439  *  0b1001..Secure Memory Blob import or export was attempted, but Secure Memory Blob access is not allowed for this partition.
14440  *  0b1010..A Descriptor attempted a Secure Memory Blob import or export, but not all of the pages referenced were from the same partition.
14441  *  0b1011..A memory access was directed to Secure Memory, but the specified address is not implemented in Secure
14442  *          Memory. The address was either outside the address range occupied by Secure Memory, or was within an
14443  *          unimplemented portion of the 4kbyte address block occupied by a 1Kbyte or 2Kbyte Secure Memory page.
14444  *  0b1100..A bus transaction was attempted, but the burst would have crossed a page boundary.
14445  *  0b1101..An attempt was made to access a page while it was still being initialized.
14446  */
14447 #define CAAM_SMSTA_ACCERR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK)
14448 
14449 #define CAAM_SMSTA_DID_MASK                      (0xF00U)
14450 #define CAAM_SMSTA_DID_SHIFT                     (8U)
14451 #define CAAM_SMSTA_DID(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK)
14452 
14453 #define CAAM_SMSTA_NS_MASK                       (0x1000U)
14454 #define CAAM_SMSTA_NS_SHIFT                      (12U)
14455 #define CAAM_SMSTA_NS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK)
14456 
14457 #define CAAM_SMSTA_SMR_WP_MASK                   (0x8000U)
14458 #define CAAM_SMSTA_SMR_WP_SHIFT                  (15U)
14459 #define CAAM_SMSTA_SMR_WP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK)
14460 
14461 #define CAAM_SMSTA_PAGE_MASK                     (0x7FF0000U)
14462 #define CAAM_SMSTA_PAGE_SHIFT                    (16U)
14463 #define CAAM_SMSTA_PAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK)
14464 
14465 #define CAAM_SMSTA_PART_MASK                     (0xF0000000U)
14466 #define CAAM_SMSTA_PART_SHIFT                    (28U)
14467 #define CAAM_SMSTA_PART(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK)
14468 /*! @} */
14469 
14470 /*! @name SMPO - Secure Memory Partition Owners Register */
14471 /*! @{ */
14472 
14473 #define CAAM_SMPO_PO0_MASK                       (0x3U)
14474 #define CAAM_SMPO_PO0_SHIFT                      (0U)
14475 /*! PO0
14476  *  0b00..Available; Unowned. A Job Ring owner may claim partition 0 by writing to the appropriate SMAPJR register
14477  *        address alias. Note that the entire register will return all 0s if read by a entity that does not own
14478  *        the Job Ring associated with the SMPO address alias that was read.
14479  *  0b01..Partition 0 does not exist in this version
14480  *  0b10..Another entity owns partition 0. Partition 0 is unavailable to the reader. If the reader attempts to
14481  *        de-allocate partition 0 or write to the SMAPJR register or SMAGJR register for partition 0 or allocate a
14482  *        page to or de-allocate a page from partition 0 the command will be ignored. (Note that if a CSP partition is
14483  *        de-allocated, all entities (including the owner that de-allocated the partition) will see a 0b10 value
14484  *        for that partition until all its pages have been zeroized.)
14485  *  0b11..The entity that read the SMPO register owns partition 0. Ownership is claimed when the access
14486  *        permissions register (SMAPJR) of an available partition is first written.
14487  */
14488 #define CAAM_SMPO_PO0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK)
14489 
14490 #define CAAM_SMPO_PO1_MASK                       (0xCU)
14491 #define CAAM_SMPO_PO1_SHIFT                      (2U)
14492 #define CAAM_SMPO_PO1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK)
14493 
14494 #define CAAM_SMPO_PO2_MASK                       (0x30U)
14495 #define CAAM_SMPO_PO2_SHIFT                      (4U)
14496 #define CAAM_SMPO_PO2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK)
14497 
14498 #define CAAM_SMPO_PO3_MASK                       (0xC0U)
14499 #define CAAM_SMPO_PO3_SHIFT                      (6U)
14500 #define CAAM_SMPO_PO3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK)
14501 
14502 #define CAAM_SMPO_PO4_MASK                       (0x300U)
14503 #define CAAM_SMPO_PO4_SHIFT                      (8U)
14504 #define CAAM_SMPO_PO4(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK)
14505 
14506 #define CAAM_SMPO_PO5_MASK                       (0xC00U)
14507 #define CAAM_SMPO_PO5_SHIFT                      (10U)
14508 #define CAAM_SMPO_PO5(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK)
14509 
14510 #define CAAM_SMPO_PO6_MASK                       (0x3000U)
14511 #define CAAM_SMPO_PO6_SHIFT                      (12U)
14512 #define CAAM_SMPO_PO6(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK)
14513 
14514 #define CAAM_SMPO_PO7_MASK                       (0xC000U)
14515 #define CAAM_SMPO_PO7_SHIFT                      (14U)
14516 #define CAAM_SMPO_PO7(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK)
14517 
14518 #define CAAM_SMPO_PO8_MASK                       (0x30000U)
14519 #define CAAM_SMPO_PO8_SHIFT                      (16U)
14520 #define CAAM_SMPO_PO8(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK)
14521 
14522 #define CAAM_SMPO_PO9_MASK                       (0xC0000U)
14523 #define CAAM_SMPO_PO9_SHIFT                      (18U)
14524 #define CAAM_SMPO_PO9(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK)
14525 
14526 #define CAAM_SMPO_PO10_MASK                      (0x300000U)
14527 #define CAAM_SMPO_PO10_SHIFT                     (20U)
14528 #define CAAM_SMPO_PO10(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK)
14529 
14530 #define CAAM_SMPO_PO11_MASK                      (0xC00000U)
14531 #define CAAM_SMPO_PO11_SHIFT                     (22U)
14532 #define CAAM_SMPO_PO11(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK)
14533 
14534 #define CAAM_SMPO_PO12_MASK                      (0x3000000U)
14535 #define CAAM_SMPO_PO12_SHIFT                     (24U)
14536 #define CAAM_SMPO_PO12(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK)
14537 
14538 #define CAAM_SMPO_PO13_MASK                      (0xC000000U)
14539 #define CAAM_SMPO_PO13_SHIFT                     (26U)
14540 #define CAAM_SMPO_PO13(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK)
14541 
14542 #define CAAM_SMPO_PO14_MASK                      (0x30000000U)
14543 #define CAAM_SMPO_PO14_SHIFT                     (28U)
14544 #define CAAM_SMPO_PO14(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK)
14545 
14546 #define CAAM_SMPO_PO15_MASK                      (0xC0000000U)
14547 #define CAAM_SMPO_PO15_SHIFT                     (30U)
14548 #define CAAM_SMPO_PO15(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK)
14549 /*! @} */
14550 
14551 /*! @name FAR - Fault Address Register */
14552 /*! @{ */
14553 
14554 #define CAAM_FAR_FAR_MASK                        (0xFFFFFFFFFU)
14555 #define CAAM_FAR_FAR_SHIFT                       (0U)
14556 #define CAAM_FAR_FAR(x)                          (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK)
14557 /*! @} */
14558 
14559 /*! @name FADID - Fault Address DID Register */
14560 /*! @{ */
14561 
14562 #define CAAM_FADID_FDID_MASK                     (0xFU)
14563 #define CAAM_FADID_FDID_SHIFT                    (0U)
14564 #define CAAM_FADID_FDID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK)
14565 
14566 #define CAAM_FADID_FNS_MASK                      (0x10U)
14567 #define CAAM_FADID_FNS_SHIFT                     (4U)
14568 #define CAAM_FADID_FNS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK)
14569 
14570 #define CAAM_FADID_FICID_MASK                    (0xFFE0U)
14571 #define CAAM_FADID_FICID_SHIFT                   (5U)
14572 #define CAAM_FADID_FICID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK)
14573 /*! @} */
14574 
14575 /*! @name FADR - Fault Address Detail Register */
14576 /*! @{ */
14577 
14578 #define CAAM_FADR_FSZ_MASK                       (0x7FU)
14579 #define CAAM_FADR_FSZ_SHIFT                      (0U)
14580 #define CAAM_FADR_FSZ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK)
14581 
14582 #define CAAM_FADR_TYP_MASK                       (0x80U)
14583 #define CAAM_FADR_TYP_SHIFT                      (7U)
14584 /*! TYP
14585  *  0b0..Read.
14586  *  0b1..Write.
14587  */
14588 #define CAAM_FADR_TYP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK)
14589 
14590 #define CAAM_FADR_BLKID_MASK                     (0xF00U)
14591 #define CAAM_FADR_BLKID_SHIFT                    (8U)
14592 /*! BLKID
14593  *  0b0100..job queue controller Burst Buffer
14594  *  0b0101..One of the Job Rings (see JSRC field)
14595  *  0b1000..DECO0
14596  */
14597 #define CAAM_FADR_BLKID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK)
14598 
14599 #define CAAM_FADR_JSRC_MASK                      (0x7000U)
14600 #define CAAM_FADR_JSRC_SHIFT                     (12U)
14601 /*! JSRC
14602  *  0b000..Job Ring 0
14603  *  0b001..Job Ring 1
14604  *  0b010..Job Ring 2
14605  *  0b011..Job Ring 3
14606  *  0b100..RTIC
14607  *  0b101..reserved
14608  *  0b110..reserved
14609  *  0b111..reserved
14610  */
14611 #define CAAM_FADR_JSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK)
14612 
14613 #define CAAM_FADR_DTYP_MASK                      (0x8000U)
14614 #define CAAM_FADR_DTYP_SHIFT                     (15U)
14615 /*! DTYP
14616  *  0b0..message data
14617  *  0b1..control data
14618  */
14619 #define CAAM_FADR_DTYP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK)
14620 
14621 #define CAAM_FADR_FSZ_EXT_MASK                   (0x70000U)
14622 #define CAAM_FADR_FSZ_EXT_SHIFT                  (16U)
14623 #define CAAM_FADR_FSZ_EXT(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK)
14624 
14625 #define CAAM_FADR_FKMOD_MASK                     (0x1000000U)
14626 #define CAAM_FADR_FKMOD_SHIFT                    (24U)
14627 /*! FKMOD
14628  *  0b0..CAAM DMA was not attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14629  *  0b1..CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14630  */
14631 #define CAAM_FADR_FKMOD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK)
14632 
14633 #define CAAM_FADR_FKEY_MASK                      (0x2000000U)
14634 #define CAAM_FADR_FKEY_SHIFT                     (25U)
14635 /*! FKEY
14636  *  0b0..CAAM DMA was not attempting to perform a key read from Secure Memory at the time of the DMA error.
14637  *  0b1..CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error.
14638  */
14639 #define CAAM_FADR_FKEY(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK)
14640 
14641 #define CAAM_FADR_FTDSC_MASK                     (0x4000000U)
14642 #define CAAM_FADR_FTDSC_SHIFT                    (26U)
14643 /*! FTDSC
14644  *  0b0..CAAM DMA was not executing a Trusted Descriptor at the time of the DMA error.
14645  *  0b1..CAAM DMA was executing a Trusted Descriptor at the time of the DMA error.
14646  */
14647 #define CAAM_FADR_FTDSC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK)
14648 
14649 #define CAAM_FADR_FBNDG_MASK                     (0x8000000U)
14650 #define CAAM_FADR_FBNDG_SHIFT                    (27U)
14651 /*! FBNDG
14652  *  0b0..CAAM DMA was not reading access permissions from a Secure Memory partition at the time of the DMA error.
14653  *  0b1..CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error.
14654  */
14655 #define CAAM_FADR_FBNDG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK)
14656 
14657 #define CAAM_FADR_FNS_MASK                       (0x10000000U)
14658 #define CAAM_FADR_FNS_SHIFT                      (28U)
14659 /*! FNS
14660  *  0b0..CAAM DMA was asserting ns=0 at the time of the DMA error.
14661  *  0b1..CAAM DMA was asserting ns=1 at the time of the DMA error.
14662  */
14663 #define CAAM_FADR_FNS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK)
14664 
14665 #define CAAM_FADR_FERR_MASK                      (0xC0000000U)
14666 #define CAAM_FADR_FERR_SHIFT                     (30U)
14667 /*! FERR
14668  *  0b00..OKAY - Normal Access
14669  *  0b01..Reserved
14670  *  0b10..SLVERR - Slave Error
14671  *  0b11..DECERR - Decode Error
14672  */
14673 #define CAAM_FADR_FERR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK)
14674 /*! @} */
14675 
14676 /*! @name CSTA - CAAM Status Register */
14677 /*! @{ */
14678 
14679 #define CAAM_CSTA_BSY_MASK                       (0x1U)
14680 #define CAAM_CSTA_BSY_SHIFT                      (0U)
14681 #define CAAM_CSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK)
14682 
14683 #define CAAM_CSTA_IDLE_MASK                      (0x2U)
14684 #define CAAM_CSTA_IDLE_SHIFT                     (1U)
14685 #define CAAM_CSTA_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK)
14686 
14687 #define CAAM_CSTA_TRNG_IDLE_MASK                 (0x4U)
14688 #define CAAM_CSTA_TRNG_IDLE_SHIFT                (2U)
14689 #define CAAM_CSTA_TRNG_IDLE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK)
14690 
14691 #define CAAM_CSTA_MOO_MASK                       (0x300U)
14692 #define CAAM_CSTA_MOO_SHIFT                      (8U)
14693 /*! MOO
14694  *  0b00..Non-Secure
14695  *  0b01..Secure
14696  *  0b10..Trusted
14697  *  0b11..Fail
14698  */
14699 #define CAAM_CSTA_MOO(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK)
14700 
14701 #define CAAM_CSTA_PLEND_MASK                     (0x400U)
14702 #define CAAM_CSTA_PLEND_SHIFT                    (10U)
14703 /*! PLEND
14704  *  0b0..Platform default is Little Endian
14705  *  0b1..Platform default is Big Endian
14706  */
14707 #define CAAM_CSTA_PLEND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK)
14708 /*! @} */
14709 
14710 /*! @name SMVID_MS - Secure Memory Version ID Register, most-significant half */
14711 /*! @{ */
14712 
14713 #define CAAM_SMVID_MS_NPAG_MASK                  (0x3FFU)
14714 #define CAAM_SMVID_MS_NPAG_SHIFT                 (0U)
14715 #define CAAM_SMVID_MS_NPAG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK)
14716 
14717 #define CAAM_SMVID_MS_NPRT_MASK                  (0xF000U)
14718 #define CAAM_SMVID_MS_NPRT_SHIFT                 (12U)
14719 #define CAAM_SMVID_MS_NPRT(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK)
14720 
14721 #define CAAM_SMVID_MS_MAX_NPAG_MASK              (0x3FF0000U)
14722 #define CAAM_SMVID_MS_MAX_NPAG_SHIFT             (16U)
14723 #define CAAM_SMVID_MS_MAX_NPAG(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK)
14724 /*! @} */
14725 
14726 /*! @name SMVID_LS - Secure Memory Version ID Register, least-significant half */
14727 /*! @{ */
14728 
14729 #define CAAM_SMVID_LS_SMNV_MASK                  (0xFFU)
14730 #define CAAM_SMVID_LS_SMNV_SHIFT                 (0U)
14731 #define CAAM_SMVID_LS_SMNV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK)
14732 
14733 #define CAAM_SMVID_LS_SMJV_MASK                  (0xFF00U)
14734 #define CAAM_SMVID_LS_SMJV_SHIFT                 (8U)
14735 #define CAAM_SMVID_LS_SMJV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK)
14736 
14737 #define CAAM_SMVID_LS_PSIZ_MASK                  (0x70000U)
14738 #define CAAM_SMVID_LS_PSIZ_SHIFT                 (16U)
14739 #define CAAM_SMVID_LS_PSIZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK)
14740 /*! @} */
14741 
14742 /*! @name RVID - RTIC Version ID Register */
14743 /*! @{ */
14744 
14745 #define CAAM_RVID_RMNV_MASK                      (0xFFU)
14746 #define CAAM_RVID_RMNV_SHIFT                     (0U)
14747 #define CAAM_RVID_RMNV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK)
14748 
14749 #define CAAM_RVID_RMJV_MASK                      (0xFF00U)
14750 #define CAAM_RVID_RMJV_SHIFT                     (8U)
14751 #define CAAM_RVID_RMJV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK)
14752 
14753 #define CAAM_RVID_SHA_256_MASK                   (0x20000U)
14754 #define CAAM_RVID_SHA_256_SHIFT                  (17U)
14755 /*! SHA_256
14756  *  0b0..RTIC cannot use the SHA-256 hashing algorithm.
14757  *  0b1..RTIC can use the SHA-256 hashing algorithm.
14758  */
14759 #define CAAM_RVID_SHA_256(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK)
14760 
14761 #define CAAM_RVID_SHA_512_MASK                   (0x80000U)
14762 #define CAAM_RVID_SHA_512_SHIFT                  (19U)
14763 /*! SHA_512
14764  *  0b0..RTIC cannot use the SHA-512 hashing algorithm.
14765  *  0b1..RTIC can use the SHA-512 hashing algorithm.
14766  */
14767 #define CAAM_RVID_SHA_512(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK)
14768 
14769 #define CAAM_RVID_MA_MASK                        (0x1000000U)
14770 #define CAAM_RVID_MA_SHIFT                       (24U)
14771 #define CAAM_RVID_MA(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK)
14772 
14773 #define CAAM_RVID_MB_MASK                        (0x2000000U)
14774 #define CAAM_RVID_MB_SHIFT                       (25U)
14775 #define CAAM_RVID_MB(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK)
14776 
14777 #define CAAM_RVID_MC_MASK                        (0x4000000U)
14778 #define CAAM_RVID_MC_SHIFT                       (26U)
14779 #define CAAM_RVID_MC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK)
14780 
14781 #define CAAM_RVID_MD_MASK                        (0x8000000U)
14782 #define CAAM_RVID_MD_SHIFT                       (27U)
14783 #define CAAM_RVID_MD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK)
14784 /*! @} */
14785 
14786 /*! @name CCBVID - CHA Cluster Block Version ID Register */
14787 /*! @{ */
14788 
14789 #define CAAM_CCBVID_AMNV_MASK                    (0xFFU)
14790 #define CAAM_CCBVID_AMNV_SHIFT                   (0U)
14791 #define CAAM_CCBVID_AMNV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK)
14792 
14793 #define CAAM_CCBVID_AMJV_MASK                    (0xFF00U)
14794 #define CAAM_CCBVID_AMJV_SHIFT                   (8U)
14795 #define CAAM_CCBVID_AMJV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK)
14796 
14797 #define CAAM_CCBVID_CAAM_ERA_MASK                (0xFF000000U)
14798 #define CAAM_CCBVID_CAAM_ERA_SHIFT               (24U)
14799 #define CAAM_CCBVID_CAAM_ERA(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK)
14800 /*! @} */
14801 
14802 /*! @name CHAVID_MS - CHA Version ID Register, most-significant half */
14803 /*! @{ */
14804 
14805 #define CAAM_CHAVID_MS_CRCVID_MASK               (0xFU)
14806 #define CAAM_CHAVID_MS_CRCVID_SHIFT              (0U)
14807 #define CAAM_CHAVID_MS_CRCVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK)
14808 
14809 #define CAAM_CHAVID_MS_SNW9VID_MASK              (0xF0U)
14810 #define CAAM_CHAVID_MS_SNW9VID_SHIFT             (4U)
14811 #define CAAM_CHAVID_MS_SNW9VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK)
14812 
14813 #define CAAM_CHAVID_MS_ZEVID_MASK                (0xF00U)
14814 #define CAAM_CHAVID_MS_ZEVID_SHIFT               (8U)
14815 #define CAAM_CHAVID_MS_ZEVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK)
14816 
14817 #define CAAM_CHAVID_MS_ZAVID_MASK                (0xF000U)
14818 #define CAAM_CHAVID_MS_ZAVID_SHIFT               (12U)
14819 #define CAAM_CHAVID_MS_ZAVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK)
14820 
14821 #define CAAM_CHAVID_MS_DECOVID_MASK              (0xF000000U)
14822 #define CAAM_CHAVID_MS_DECOVID_SHIFT             (24U)
14823 #define CAAM_CHAVID_MS_DECOVID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK)
14824 
14825 #define CAAM_CHAVID_MS_JRVID_MASK                (0xF0000000U)
14826 #define CAAM_CHAVID_MS_JRVID_SHIFT               (28U)
14827 #define CAAM_CHAVID_MS_JRVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK)
14828 /*! @} */
14829 
14830 /*! @name CHAVID_LS - CHA Version ID Register, least-significant half */
14831 /*! @{ */
14832 
14833 #define CAAM_CHAVID_LS_AESVID_MASK               (0xFU)
14834 #define CAAM_CHAVID_LS_AESVID_SHIFT              (0U)
14835 /*! AESVID
14836  *  0b0100..High-performance AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, CBCXCBC, CTRXCBC, XTS, and GCM modes
14837  *  0b0011..Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes
14838  */
14839 #define CAAM_CHAVID_LS_AESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK)
14840 
14841 #define CAAM_CHAVID_LS_DESVID_MASK               (0xF0U)
14842 #define CAAM_CHAVID_LS_DESVID_SHIFT              (4U)
14843 #define CAAM_CHAVID_LS_DESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK)
14844 
14845 #define CAAM_CHAVID_LS_MDVID_MASK                (0xF000U)
14846 #define CAAM_CHAVID_LS_MDVID_SHIFT               (12U)
14847 /*! MDVID
14848  *  0b0000..Low-power MDHA, with SHA-1, SHA-256, SHA 224, MD5 and HMAC
14849  *  0b0001..Low-power MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5 and HMAC
14850  *  0b0010..Medium-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14851  *  0b0011..High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14852  */
14853 #define CAAM_CHAVID_LS_MDVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK)
14854 
14855 #define CAAM_CHAVID_LS_RNGVID_MASK               (0xF0000U)
14856 #define CAAM_CHAVID_LS_RNGVID_SHIFT              (16U)
14857 /*! RNGVID
14858  *  0b0010..RNGB
14859  *  0b0100..RNG4
14860  */
14861 #define CAAM_CHAVID_LS_RNGVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK)
14862 
14863 #define CAAM_CHAVID_LS_SNW8VID_MASK              (0xF00000U)
14864 #define CAAM_CHAVID_LS_SNW8VID_SHIFT             (20U)
14865 #define CAAM_CHAVID_LS_SNW8VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
14866 
14867 #define CAAM_CHAVID_LS_KASVID_MASK               (0xF000000U)
14868 #define CAAM_CHAVID_LS_KASVID_SHIFT              (24U)
14869 #define CAAM_CHAVID_LS_KASVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK)
14870 
14871 #define CAAM_CHAVID_LS_PKVID_MASK                (0xF0000000U)
14872 #define CAAM_CHAVID_LS_PKVID_SHIFT               (28U)
14873 /*! PKVID
14874  *  0b0000..PKHA-XT (32-bit); minimum modulus five bytes
14875  *  0b0001..PKHA-SD (32-bit)
14876  *  0b0010..PKHA-SD (64-bit)
14877  *  0b0011..PKHA-SD (128-bit)
14878  */
14879 #define CAAM_CHAVID_LS_PKVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK)
14880 /*! @} */
14881 
14882 /*! @name CHANUM_MS - CHA Number Register, most-significant half */
14883 /*! @{ */
14884 
14885 #define CAAM_CHANUM_MS_CRCNUM_MASK               (0xFU)
14886 #define CAAM_CHANUM_MS_CRCNUM_SHIFT              (0U)
14887 #define CAAM_CHANUM_MS_CRCNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK)
14888 
14889 #define CAAM_CHANUM_MS_SNW9NUM_MASK              (0xF0U)
14890 #define CAAM_CHANUM_MS_SNW9NUM_SHIFT             (4U)
14891 #define CAAM_CHANUM_MS_SNW9NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK)
14892 
14893 #define CAAM_CHANUM_MS_ZENUM_MASK                (0xF00U)
14894 #define CAAM_CHANUM_MS_ZENUM_SHIFT               (8U)
14895 #define CAAM_CHANUM_MS_ZENUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK)
14896 
14897 #define CAAM_CHANUM_MS_ZANUM_MASK                (0xF000U)
14898 #define CAAM_CHANUM_MS_ZANUM_SHIFT               (12U)
14899 #define CAAM_CHANUM_MS_ZANUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK)
14900 
14901 #define CAAM_CHANUM_MS_DECONUM_MASK              (0xF000000U)
14902 #define CAAM_CHANUM_MS_DECONUM_SHIFT             (24U)
14903 #define CAAM_CHANUM_MS_DECONUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK)
14904 
14905 #define CAAM_CHANUM_MS_JRNUM_MASK                (0xF0000000U)
14906 #define CAAM_CHANUM_MS_JRNUM_SHIFT               (28U)
14907 #define CAAM_CHANUM_MS_JRNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK)
14908 /*! @} */
14909 
14910 /*! @name CHANUM_LS - CHA Number Register, least-significant half */
14911 /*! @{ */
14912 
14913 #define CAAM_CHANUM_LS_AESNUM_MASK               (0xFU)
14914 #define CAAM_CHANUM_LS_AESNUM_SHIFT              (0U)
14915 #define CAAM_CHANUM_LS_AESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK)
14916 
14917 #define CAAM_CHANUM_LS_DESNUM_MASK               (0xF0U)
14918 #define CAAM_CHANUM_LS_DESNUM_SHIFT              (4U)
14919 #define CAAM_CHANUM_LS_DESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK)
14920 
14921 #define CAAM_CHANUM_LS_ARC4NUM_MASK              (0xF00U)
14922 #define CAAM_CHANUM_LS_ARC4NUM_SHIFT             (8U)
14923 #define CAAM_CHANUM_LS_ARC4NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK)
14924 
14925 #define CAAM_CHANUM_LS_MDNUM_MASK                (0xF000U)
14926 #define CAAM_CHANUM_LS_MDNUM_SHIFT               (12U)
14927 #define CAAM_CHANUM_LS_MDNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK)
14928 
14929 #define CAAM_CHANUM_LS_RNGNUM_MASK               (0xF0000U)
14930 #define CAAM_CHANUM_LS_RNGNUM_SHIFT              (16U)
14931 #define CAAM_CHANUM_LS_RNGNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK)
14932 
14933 #define CAAM_CHANUM_LS_SNW8NUM_MASK              (0xF00000U)
14934 #define CAAM_CHANUM_LS_SNW8NUM_SHIFT             (20U)
14935 #define CAAM_CHANUM_LS_SNW8NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK)
14936 
14937 #define CAAM_CHANUM_LS_KASNUM_MASK               (0xF000000U)
14938 #define CAAM_CHANUM_LS_KASNUM_SHIFT              (24U)
14939 #define CAAM_CHANUM_LS_KASNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK)
14940 
14941 #define CAAM_CHANUM_LS_PKNUM_MASK                (0xF0000000U)
14942 #define CAAM_CHANUM_LS_PKNUM_SHIFT               (28U)
14943 #define CAAM_CHANUM_LS_PKNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK)
14944 /*! @} */
14945 
14946 /*! @name IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 */
14947 /*! @{ */
14948 
14949 #define CAAM_IRBAR_JR_IRBA_MASK                  (0xFFFFFFFFFU)
14950 #define CAAM_IRBAR_JR_IRBA_SHIFT                 (0U)
14951 #define CAAM_IRBAR_JR_IRBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK)
14952 /*! @} */
14953 
14954 /* The count of CAAM_IRBAR_JR */
14955 #define CAAM_IRBAR_JR_COUNT                      (4U)
14956 
14957 /*! @name IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 */
14958 /*! @{ */
14959 
14960 #define CAAM_IRSR_JR_IRS_MASK                    (0x3FFU)
14961 #define CAAM_IRSR_JR_IRS_SHIFT                   (0U)
14962 #define CAAM_IRSR_JR_IRS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK)
14963 /*! @} */
14964 
14965 /* The count of CAAM_IRSR_JR */
14966 #define CAAM_IRSR_JR_COUNT                       (4U)
14967 
14968 /*! @name IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 */
14969 /*! @{ */
14970 
14971 #define CAAM_IRSAR_JR_IRSA_MASK                  (0x3FFU)
14972 #define CAAM_IRSAR_JR_IRSA_SHIFT                 (0U)
14973 #define CAAM_IRSAR_JR_IRSA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK)
14974 /*! @} */
14975 
14976 /* The count of CAAM_IRSAR_JR */
14977 #define CAAM_IRSAR_JR_COUNT                      (4U)
14978 
14979 /*! @name IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 */
14980 /*! @{ */
14981 
14982 #define CAAM_IRJAR_JR_IRJA_MASK                  (0x3FFU)
14983 #define CAAM_IRJAR_JR_IRJA_SHIFT                 (0U)
14984 #define CAAM_IRJAR_JR_IRJA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK)
14985 /*! @} */
14986 
14987 /* The count of CAAM_IRJAR_JR */
14988 #define CAAM_IRJAR_JR_COUNT                      (4U)
14989 
14990 /*! @name ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 */
14991 /*! @{ */
14992 
14993 #define CAAM_ORBAR_JR_ORBA_MASK                  (0xFFFFFFFFFU)
14994 #define CAAM_ORBAR_JR_ORBA_SHIFT                 (0U)
14995 #define CAAM_ORBAR_JR_ORBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK)
14996 /*! @} */
14997 
14998 /* The count of CAAM_ORBAR_JR */
14999 #define CAAM_ORBAR_JR_COUNT                      (4U)
15000 
15001 /*! @name ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 */
15002 /*! @{ */
15003 
15004 #define CAAM_ORSR_JR_ORS_MASK                    (0x3FFU)
15005 #define CAAM_ORSR_JR_ORS_SHIFT                   (0U)
15006 #define CAAM_ORSR_JR_ORS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK)
15007 /*! @} */
15008 
15009 /* The count of CAAM_ORSR_JR */
15010 #define CAAM_ORSR_JR_COUNT                       (4U)
15011 
15012 /*! @name ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 */
15013 /*! @{ */
15014 
15015 #define CAAM_ORJRR_JR_ORJR_MASK                  (0x3FFU)
15016 #define CAAM_ORJRR_JR_ORJR_SHIFT                 (0U)
15017 #define CAAM_ORJRR_JR_ORJR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK)
15018 /*! @} */
15019 
15020 /* The count of CAAM_ORJRR_JR */
15021 #define CAAM_ORJRR_JR_COUNT                      (4U)
15022 
15023 /*! @name ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 */
15024 /*! @{ */
15025 
15026 #define CAAM_ORSFR_JR_ORSF_MASK                  (0x3FFU)
15027 #define CAAM_ORSFR_JR_ORSF_SHIFT                 (0U)
15028 #define CAAM_ORSFR_JR_ORSF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK)
15029 /*! @} */
15030 
15031 /* The count of CAAM_ORSFR_JR */
15032 #define CAAM_ORSFR_JR_COUNT                      (4U)
15033 
15034 /*! @name JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 */
15035 /*! @{ */
15036 
15037 #define CAAM_JRSTAR_JR_SSED_MASK                 (0xFFFFFFFU)
15038 #define CAAM_JRSTAR_JR_SSED_SHIFT                (0U)
15039 #define CAAM_JRSTAR_JR_SSED(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK)
15040 
15041 #define CAAM_JRSTAR_JR_SSRC_MASK                 (0xF0000000U)
15042 #define CAAM_JRSTAR_JR_SSRC_SHIFT                (28U)
15043 /*! SSRC
15044  *  0b0000..No Status Source (No Error or Status Reported)
15045  *  0b0001..Reserved
15046  *  0b0010..CCB Status Source (CCB Error Reported)
15047  *  0b0011..Jump Halt User Status Source (User-Provided Status Reported)
15048  *  0b0100..DECO Status Source (DECO Error Reported)
15049  *  0b0101..Reserved
15050  *  0b0110..Job Ring Status Source (Job Ring Error Reported)
15051  *  0b0111..Jump Halt Condition Codes (Condition Code Status Reported)
15052  */
15053 #define CAAM_JRSTAR_JR_SSRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK)
15054 /*! @} */
15055 
15056 /* The count of CAAM_JRSTAR_JR */
15057 #define CAAM_JRSTAR_JR_COUNT                     (4U)
15058 
15059 /*! @name JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 */
15060 /*! @{ */
15061 
15062 #define CAAM_JRINTR_JR_JRI_MASK                  (0x1U)
15063 #define CAAM_JRINTR_JR_JRI_SHIFT                 (0U)
15064 #define CAAM_JRINTR_JR_JRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK)
15065 
15066 #define CAAM_JRINTR_JR_JRE_MASK                  (0x2U)
15067 #define CAAM_JRINTR_JR_JRE_SHIFT                 (1U)
15068 #define CAAM_JRINTR_JR_JRE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK)
15069 
15070 #define CAAM_JRINTR_JR_HALT_MASK                 (0xCU)
15071 #define CAAM_JRINTR_JR_HALT_SHIFT                (2U)
15072 #define CAAM_JRINTR_JR_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK)
15073 
15074 #define CAAM_JRINTR_JR_ENTER_FAIL_MASK           (0x10U)
15075 #define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT          (4U)
15076 #define CAAM_JRINTR_JR_ENTER_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK)
15077 
15078 #define CAAM_JRINTR_JR_EXIT_FAIL_MASK            (0x20U)
15079 #define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT           (5U)
15080 #define CAAM_JRINTR_JR_EXIT_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK)
15081 
15082 #define CAAM_JRINTR_JR_ERR_TYPE_MASK             (0x1F00U)
15083 #define CAAM_JRINTR_JR_ERR_TYPE_SHIFT            (8U)
15084 /*! ERR_TYPE
15085  *  0b00001..Error writing status to Output Ring
15086  *  0b00011..Bad input ring base address (not on a 4-byte boundary).
15087  *  0b00100..Bad output ring base address (not on a 4-byte boundary).
15088  *  0b00101..Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when
15089  *           there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely
15090  *           result in not being able to get all jobs out into the output ring for processing by software. Resetting
15091  *           the job ring will almost certainly be necessary.
15092  *  0b00110..Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when
15093  *           there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in
15094  *           the holding tanks or DECOs), or when the Job Ring is halted.
15095  *  0b00111..Job Ring reset released before Job Ring is halted.
15096  *  0b01000..Removed too many jobs (ORJRR larger than ORSFR).
15097  *  0b01001..Added too many jobs (IRJAR larger than IRSAR).
15098  *  0b01010..Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless
15099  *           masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register.
15100  *  0b01011..Writing IRSA > IRS
15101  *  0b01100..Writing ORWI > ORS in bytes
15102  *  0b01101..Writing IRRI > IRS in bytes
15103  *  0b01110..Writing IRSA when ring is active
15104  *  0b01111..Writing IRRI when ring is active
15105  *  0b10000..Writing ORSF when ring is active
15106  *  0b10001..Writing ORWI when ring is active
15107  */
15108 #define CAAM_JRINTR_JR_ERR_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK)
15109 
15110 #define CAAM_JRINTR_JR_ERR_ORWI_MASK             (0x3FFF0000U)
15111 #define CAAM_JRINTR_JR_ERR_ORWI_SHIFT            (16U)
15112 #define CAAM_JRINTR_JR_ERR_ORWI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK)
15113 /*! @} */
15114 
15115 /* The count of CAAM_JRINTR_JR */
15116 #define CAAM_JRINTR_JR_COUNT                     (4U)
15117 
15118 /*! @name JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half */
15119 /*! @{ */
15120 
15121 #define CAAM_JRCFGR_JR_MS_MBSI_MASK              (0x1U)
15122 #define CAAM_JRCFGR_JR_MS_MBSI_SHIFT             (0U)
15123 #define CAAM_JRCFGR_JR_MS_MBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK)
15124 
15125 #define CAAM_JRCFGR_JR_MS_MHWSI_MASK             (0x2U)
15126 #define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT            (1U)
15127 #define CAAM_JRCFGR_JR_MS_MHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK)
15128 
15129 #define CAAM_JRCFGR_JR_MS_MWSI_MASK              (0x4U)
15130 #define CAAM_JRCFGR_JR_MS_MWSI_SHIFT             (2U)
15131 #define CAAM_JRCFGR_JR_MS_MWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK)
15132 
15133 #define CAAM_JRCFGR_JR_MS_CBSI_MASK              (0x10U)
15134 #define CAAM_JRCFGR_JR_MS_CBSI_SHIFT             (4U)
15135 #define CAAM_JRCFGR_JR_MS_CBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK)
15136 
15137 #define CAAM_JRCFGR_JR_MS_CHWSI_MASK             (0x20U)
15138 #define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT            (5U)
15139 #define CAAM_JRCFGR_JR_MS_CHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK)
15140 
15141 #define CAAM_JRCFGR_JR_MS_CWSI_MASK              (0x40U)
15142 #define CAAM_JRCFGR_JR_MS_CWSI_SHIFT             (6U)
15143 #define CAAM_JRCFGR_JR_MS_CWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK)
15144 
15145 #define CAAM_JRCFGR_JR_MS_MBSO_MASK              (0x100U)
15146 #define CAAM_JRCFGR_JR_MS_MBSO_SHIFT             (8U)
15147 #define CAAM_JRCFGR_JR_MS_MBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK)
15148 
15149 #define CAAM_JRCFGR_JR_MS_MHWSO_MASK             (0x200U)
15150 #define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT            (9U)
15151 #define CAAM_JRCFGR_JR_MS_MHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK)
15152 
15153 #define CAAM_JRCFGR_JR_MS_MWSO_MASK              (0x400U)
15154 #define CAAM_JRCFGR_JR_MS_MWSO_SHIFT             (10U)
15155 #define CAAM_JRCFGR_JR_MS_MWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK)
15156 
15157 #define CAAM_JRCFGR_JR_MS_CBSO_MASK              (0x1000U)
15158 #define CAAM_JRCFGR_JR_MS_CBSO_SHIFT             (12U)
15159 #define CAAM_JRCFGR_JR_MS_CBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK)
15160 
15161 #define CAAM_JRCFGR_JR_MS_CHWSO_MASK             (0x2000U)
15162 #define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT            (13U)
15163 #define CAAM_JRCFGR_JR_MS_CHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK)
15164 
15165 #define CAAM_JRCFGR_JR_MS_CWSO_MASK              (0x4000U)
15166 #define CAAM_JRCFGR_JR_MS_CWSO_SHIFT             (14U)
15167 #define CAAM_JRCFGR_JR_MS_CWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK)
15168 
15169 #define CAAM_JRCFGR_JR_MS_DMBS_MASK              (0x10000U)
15170 #define CAAM_JRCFGR_JR_MS_DMBS_SHIFT             (16U)
15171 #define CAAM_JRCFGR_JR_MS_DMBS(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK)
15172 
15173 #define CAAM_JRCFGR_JR_MS_PEO_MASK               (0x20000U)
15174 #define CAAM_JRCFGR_JR_MS_PEO_SHIFT              (17U)
15175 #define CAAM_JRCFGR_JR_MS_PEO(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK)
15176 
15177 #define CAAM_JRCFGR_JR_MS_DWSO_MASK              (0x40000U)
15178 #define CAAM_JRCFGR_JR_MS_DWSO_SHIFT             (18U)
15179 #define CAAM_JRCFGR_JR_MS_DWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK)
15180 
15181 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK         (0x20000000U)
15182 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT        (29U)
15183 #define CAAM_JRCFGR_JR_MS_FAIL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK)
15184 
15185 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK      (0x40000000U)
15186 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT     (30U)
15187 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK)
15188 /*! @} */
15189 
15190 /* The count of CAAM_JRCFGR_JR_MS */
15191 #define CAAM_JRCFGR_JR_MS_COUNT                  (4U)
15192 
15193 /*! @name JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half */
15194 /*! @{ */
15195 
15196 #define CAAM_JRCFGR_JR_LS_IMSK_MASK              (0x1U)
15197 #define CAAM_JRCFGR_JR_LS_IMSK_SHIFT             (0U)
15198 /*! IMSK
15199  *  0b0..Interrupt enabled.
15200  *  0b1..Interrupt masked.
15201  */
15202 #define CAAM_JRCFGR_JR_LS_IMSK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK)
15203 
15204 #define CAAM_JRCFGR_JR_LS_ICEN_MASK              (0x2U)
15205 #define CAAM_JRCFGR_JR_LS_ICEN_SHIFT             (1U)
15206 /*! ICEN
15207  *  0b0..Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is
15208  *       written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears
15209  *       the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will
15210  *       clear but reassert on the next clock cycle.
15211  *  0b1..Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the
15212  *       threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software
15213  *       removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met
15214  *       (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle.
15215  */
15216 #define CAAM_JRCFGR_JR_LS_ICEN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK)
15217 
15218 #define CAAM_JRCFGR_JR_LS_ICDCT_MASK             (0xFF00U)
15219 #define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT            (8U)
15220 #define CAAM_JRCFGR_JR_LS_ICDCT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK)
15221 
15222 #define CAAM_JRCFGR_JR_LS_ICTT_MASK              (0xFFFF0000U)
15223 #define CAAM_JRCFGR_JR_LS_ICTT_SHIFT             (16U)
15224 #define CAAM_JRCFGR_JR_LS_ICTT(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK)
15225 /*! @} */
15226 
15227 /* The count of CAAM_JRCFGR_JR_LS */
15228 #define CAAM_JRCFGR_JR_LS_COUNT                  (4U)
15229 
15230 /*! @name IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 */
15231 /*! @{ */
15232 
15233 #define CAAM_IRRIR_JR_IRRI_MASK                  (0x1FFFU)
15234 #define CAAM_IRRIR_JR_IRRI_SHIFT                 (0U)
15235 #define CAAM_IRRIR_JR_IRRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK)
15236 /*! @} */
15237 
15238 /* The count of CAAM_IRRIR_JR */
15239 #define CAAM_IRRIR_JR_COUNT                      (4U)
15240 
15241 /*! @name ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 */
15242 /*! @{ */
15243 
15244 #define CAAM_ORWIR_JR_ORWI_MASK                  (0x3FFFU)
15245 #define CAAM_ORWIR_JR_ORWI_SHIFT                 (0U)
15246 #define CAAM_ORWIR_JR_ORWI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK)
15247 /*! @} */
15248 
15249 /* The count of CAAM_ORWIR_JR */
15250 #define CAAM_ORWIR_JR_COUNT                      (4U)
15251 
15252 /*! @name JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 */
15253 /*! @{ */
15254 
15255 #define CAAM_JRCR_JR_RESET_MASK                  (0x1U)
15256 #define CAAM_JRCR_JR_RESET_SHIFT                 (0U)
15257 #define CAAM_JRCR_JR_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK)
15258 
15259 #define CAAM_JRCR_JR_PARK_MASK                   (0x2U)
15260 #define CAAM_JRCR_JR_PARK_SHIFT                  (1U)
15261 #define CAAM_JRCR_JR_PARK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK)
15262 /*! @} */
15263 
15264 /* The count of CAAM_JRCR_JR */
15265 #define CAAM_JRCR_JR_COUNT                       (4U)
15266 
15267 /*! @name JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register */
15268 /*! @{ */
15269 
15270 #define CAAM_JRAAV_V0_MASK                       (0x1U)
15271 #define CAAM_JRAAV_V0_SHIFT                      (0U)
15272 #define CAAM_JRAAV_V0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK)
15273 
15274 #define CAAM_JRAAV_V1_MASK                       (0x2U)
15275 #define CAAM_JRAAV_V1_SHIFT                      (1U)
15276 #define CAAM_JRAAV_V1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK)
15277 
15278 #define CAAM_JRAAV_V2_MASK                       (0x4U)
15279 #define CAAM_JRAAV_V2_SHIFT                      (2U)
15280 #define CAAM_JRAAV_V2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK)
15281 
15282 #define CAAM_JRAAV_V3_MASK                       (0x8U)
15283 #define CAAM_JRAAV_V3_SHIFT                      (3U)
15284 #define CAAM_JRAAV_V3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK)
15285 
15286 #define CAAM_JRAAV_BC_MASK                       (0x80000000U)
15287 #define CAAM_JRAAV_BC_SHIFT                      (31U)
15288 #define CAAM_JRAAV_BC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK)
15289 /*! @} */
15290 
15291 /* The count of CAAM_JRAAV */
15292 #define CAAM_JRAAV_COUNT                         (4U)
15293 
15294 /*! @name JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register */
15295 /*! @{ */
15296 
15297 #define CAAM_JRAAA_JD_ADDR_MASK                  (0xFFFFFFFFFU)
15298 #define CAAM_JRAAA_JD_ADDR_SHIFT                 (0U)
15299 #define CAAM_JRAAA_JD_ADDR(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK)
15300 /*! @} */
15301 
15302 /* The count of CAAM_JRAAA */
15303 #define CAAM_JRAAA_COUNT                         (4U)
15304 
15305 /* The count of CAAM_JRAAA */
15306 #define CAAM_JRAAA_COUNT2                        (4U)
15307 
15308 /*! @name PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register */
15309 /*! @{ */
15310 
15311 #define CAAM_PX_SDID_JR_SDID_MASK                (0xFFFFU)
15312 #define CAAM_PX_SDID_JR_SDID_SHIFT               (0U)
15313 #define CAAM_PX_SDID_JR_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK)
15314 /*! @} */
15315 
15316 /* The count of CAAM_PX_SDID_JR */
15317 #define CAAM_PX_SDID_JR_COUNT                    (4U)
15318 
15319 /* The count of CAAM_PX_SDID_JR */
15320 #define CAAM_PX_SDID_JR_COUNT2                   (16U)
15321 
15322 /*! @name PX_SMAPR_JR - Secure Memory Access Permissions register */
15323 /*! @{ */
15324 
15325 #define CAAM_PX_SMAPR_JR_G1_READ_MASK            (0x1U)
15326 #define CAAM_PX_SMAPR_JR_G1_READ_SHIFT           (0U)
15327 /*! G1_READ
15328  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
15329  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
15330  *       Trusted Descriptor and G1_TDO=1).
15331  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15332  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
15333  */
15334 #define CAAM_PX_SMAPR_JR_G1_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK)
15335 
15336 #define CAAM_PX_SMAPR_JR_G1_WRITE_MASK           (0x2U)
15337 #define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT          (1U)
15338 /*! G1_WRITE
15339  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15340  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
15341  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
15342  *       not a Trusted Descriptor or if G1_TDO=0).
15343  */
15344 #define CAAM_PX_SMAPR_JR_G1_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK)
15345 
15346 #define CAAM_PX_SMAPR_JR_G1_TDO_MASK             (0x4U)
15347 #define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT            (2U)
15348 /*! G1_TDO
15349  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15350  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15351  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
15352  *       G1_WRITE and G1_READ settings.
15353  */
15354 #define CAAM_PX_SMAPR_JR_G1_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK)
15355 
15356 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK          (0x8U)
15357 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT         (3U)
15358 /*! G1_SMBLOB
15359  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
15360  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
15361  */
15362 #define CAAM_PX_SMAPR_JR_G1_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK)
15363 
15364 #define CAAM_PX_SMAPR_JR_G2_READ_MASK            (0x10U)
15365 #define CAAM_PX_SMAPR_JR_G2_READ_SHIFT           (4U)
15366 /*! G2_READ
15367  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
15368  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
15369  *       Trusted Descriptor and G2_TDO=1).
15370  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15371  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
15372  */
15373 #define CAAM_PX_SMAPR_JR_G2_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK)
15374 
15375 #define CAAM_PX_SMAPR_JR_G2_WRITE_MASK           (0x20U)
15376 #define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT          (5U)
15377 /*! G2_WRITE
15378  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15379  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
15380  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
15381  *       not a Trusted Descriptor or if G2_TDO=0).
15382  */
15383 #define CAAM_PX_SMAPR_JR_G2_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK)
15384 
15385 #define CAAM_PX_SMAPR_JR_G2_TDO_MASK             (0x40U)
15386 #define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT            (6U)
15387 /*! G2_TDO
15388  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15389  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15390  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
15391  *       G2_WRITE and G2_READ settings.
15392  */
15393 #define CAAM_PX_SMAPR_JR_G2_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK)
15394 
15395 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK          (0x80U)
15396 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT         (7U)
15397 /*! G2_SMBLOB
15398  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
15399  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
15400  */
15401 #define CAAM_PX_SMAPR_JR_G2_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK)
15402 
15403 #define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK           (0x1000U)
15404 #define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT          (12U)
15405 /*! SMAG_LCK
15406  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
15407  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
15408  *       until the partition is de-allocated or a POR occurs.
15409  */
15410 #define CAAM_PX_SMAPR_JR_SMAG_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK)
15411 
15412 #define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK           (0x2000U)
15413 #define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT          (13U)
15414 /*! SMAP_LCK
15415  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
15416  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
15417  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
15418  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
15419  */
15420 #define CAAM_PX_SMAPR_JR_SMAP_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK)
15421 
15422 #define CAAM_PX_SMAPR_JR_PSP_MASK                (0x4000U)
15423 #define CAAM_PX_SMAPR_JR_PSP_SHIFT               (14U)
15424 /*! PSP
15425  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
15426  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
15427  */
15428 #define CAAM_PX_SMAPR_JR_PSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK)
15429 
15430 #define CAAM_PX_SMAPR_JR_CSP_MASK                (0x8000U)
15431 #define CAAM_PX_SMAPR_JR_CSP_SHIFT               (15U)
15432 /*! CSP
15433  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
15434  *       released or a security alarm occurs.
15435  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
15436  *       partition is released or a security alarm occurs.
15437  */
15438 #define CAAM_PX_SMAPR_JR_CSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK)
15439 
15440 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK     (0xFFFF0000U)
15441 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT    (16U)
15442 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK)
15443 /*! @} */
15444 
15445 /* The count of CAAM_PX_SMAPR_JR */
15446 #define CAAM_PX_SMAPR_JR_COUNT                   (4U)
15447 
15448 /* The count of CAAM_PX_SMAPR_JR */
15449 #define CAAM_PX_SMAPR_JR_COUNT2                  (16U)
15450 
15451 /*! @name PX_SMAG2_JR - Secure Memory Access Group Registers */
15452 /*! @{ */
15453 
15454 #define CAAM_PX_SMAG2_JR_Gx_ID00_MASK            (0x1U)
15455 #define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT           (0U)
15456 #define CAAM_PX_SMAG2_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK)
15457 
15458 #define CAAM_PX_SMAG2_JR_Gx_ID01_MASK            (0x2U)
15459 #define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT           (1U)
15460 #define CAAM_PX_SMAG2_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK)
15461 
15462 #define CAAM_PX_SMAG2_JR_Gx_ID02_MASK            (0x4U)
15463 #define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT           (2U)
15464 #define CAAM_PX_SMAG2_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK)
15465 
15466 #define CAAM_PX_SMAG2_JR_Gx_ID03_MASK            (0x8U)
15467 #define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT           (3U)
15468 #define CAAM_PX_SMAG2_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK)
15469 
15470 #define CAAM_PX_SMAG2_JR_Gx_ID04_MASK            (0x10U)
15471 #define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT           (4U)
15472 #define CAAM_PX_SMAG2_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK)
15473 
15474 #define CAAM_PX_SMAG2_JR_Gx_ID05_MASK            (0x20U)
15475 #define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT           (5U)
15476 #define CAAM_PX_SMAG2_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK)
15477 
15478 #define CAAM_PX_SMAG2_JR_Gx_ID06_MASK            (0x40U)
15479 #define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT           (6U)
15480 #define CAAM_PX_SMAG2_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK)
15481 
15482 #define CAAM_PX_SMAG2_JR_Gx_ID07_MASK            (0x80U)
15483 #define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT           (7U)
15484 #define CAAM_PX_SMAG2_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK)
15485 
15486 #define CAAM_PX_SMAG2_JR_Gx_ID08_MASK            (0x100U)
15487 #define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT           (8U)
15488 #define CAAM_PX_SMAG2_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK)
15489 
15490 #define CAAM_PX_SMAG2_JR_Gx_ID09_MASK            (0x200U)
15491 #define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT           (9U)
15492 #define CAAM_PX_SMAG2_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK)
15493 
15494 #define CAAM_PX_SMAG2_JR_Gx_ID10_MASK            (0x400U)
15495 #define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT           (10U)
15496 #define CAAM_PX_SMAG2_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK)
15497 
15498 #define CAAM_PX_SMAG2_JR_Gx_ID11_MASK            (0x800U)
15499 #define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT           (11U)
15500 #define CAAM_PX_SMAG2_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK)
15501 
15502 #define CAAM_PX_SMAG2_JR_Gx_ID12_MASK            (0x1000U)
15503 #define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT           (12U)
15504 #define CAAM_PX_SMAG2_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK)
15505 
15506 #define CAAM_PX_SMAG2_JR_Gx_ID13_MASK            (0x2000U)
15507 #define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT           (13U)
15508 #define CAAM_PX_SMAG2_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK)
15509 
15510 #define CAAM_PX_SMAG2_JR_Gx_ID14_MASK            (0x4000U)
15511 #define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT           (14U)
15512 #define CAAM_PX_SMAG2_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK)
15513 
15514 #define CAAM_PX_SMAG2_JR_Gx_ID15_MASK            (0x8000U)
15515 #define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT           (15U)
15516 #define CAAM_PX_SMAG2_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK)
15517 
15518 #define CAAM_PX_SMAG2_JR_Gx_ID16_MASK            (0x10000U)
15519 #define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT           (16U)
15520 #define CAAM_PX_SMAG2_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK)
15521 
15522 #define CAAM_PX_SMAG2_JR_Gx_ID17_MASK            (0x20000U)
15523 #define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT           (17U)
15524 #define CAAM_PX_SMAG2_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK)
15525 
15526 #define CAAM_PX_SMAG2_JR_Gx_ID18_MASK            (0x40000U)
15527 #define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT           (18U)
15528 #define CAAM_PX_SMAG2_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK)
15529 
15530 #define CAAM_PX_SMAG2_JR_Gx_ID19_MASK            (0x80000U)
15531 #define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT           (19U)
15532 #define CAAM_PX_SMAG2_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK)
15533 
15534 #define CAAM_PX_SMAG2_JR_Gx_ID20_MASK            (0x100000U)
15535 #define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT           (20U)
15536 #define CAAM_PX_SMAG2_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK)
15537 
15538 #define CAAM_PX_SMAG2_JR_Gx_ID21_MASK            (0x200000U)
15539 #define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT           (21U)
15540 #define CAAM_PX_SMAG2_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK)
15541 
15542 #define CAAM_PX_SMAG2_JR_Gx_ID22_MASK            (0x400000U)
15543 #define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT           (22U)
15544 #define CAAM_PX_SMAG2_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK)
15545 
15546 #define CAAM_PX_SMAG2_JR_Gx_ID23_MASK            (0x800000U)
15547 #define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT           (23U)
15548 #define CAAM_PX_SMAG2_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK)
15549 
15550 #define CAAM_PX_SMAG2_JR_Gx_ID24_MASK            (0x1000000U)
15551 #define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT           (24U)
15552 #define CAAM_PX_SMAG2_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK)
15553 
15554 #define CAAM_PX_SMAG2_JR_Gx_ID25_MASK            (0x2000000U)
15555 #define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT           (25U)
15556 #define CAAM_PX_SMAG2_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK)
15557 
15558 #define CAAM_PX_SMAG2_JR_Gx_ID26_MASK            (0x4000000U)
15559 #define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT           (26U)
15560 #define CAAM_PX_SMAG2_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK)
15561 
15562 #define CAAM_PX_SMAG2_JR_Gx_ID27_MASK            (0x8000000U)
15563 #define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT           (27U)
15564 #define CAAM_PX_SMAG2_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK)
15565 
15566 #define CAAM_PX_SMAG2_JR_Gx_ID28_MASK            (0x10000000U)
15567 #define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT           (28U)
15568 #define CAAM_PX_SMAG2_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK)
15569 
15570 #define CAAM_PX_SMAG2_JR_Gx_ID29_MASK            (0x20000000U)
15571 #define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT           (29U)
15572 #define CAAM_PX_SMAG2_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK)
15573 
15574 #define CAAM_PX_SMAG2_JR_Gx_ID30_MASK            (0x40000000U)
15575 #define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT           (30U)
15576 #define CAAM_PX_SMAG2_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK)
15577 
15578 #define CAAM_PX_SMAG2_JR_Gx_ID31_MASK            (0x80000000U)
15579 #define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT           (31U)
15580 #define CAAM_PX_SMAG2_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK)
15581 /*! @} */
15582 
15583 /* The count of CAAM_PX_SMAG2_JR */
15584 #define CAAM_PX_SMAG2_JR_COUNT                   (4U)
15585 
15586 /* The count of CAAM_PX_SMAG2_JR */
15587 #define CAAM_PX_SMAG2_JR_COUNT2                  (16U)
15588 
15589 /*! @name PX_SMAG1_JR - Secure Memory Access Group Registers */
15590 /*! @{ */
15591 
15592 #define CAAM_PX_SMAG1_JR_Gx_ID00_MASK            (0x1U)
15593 #define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT           (0U)
15594 #define CAAM_PX_SMAG1_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK)
15595 
15596 #define CAAM_PX_SMAG1_JR_Gx_ID01_MASK            (0x2U)
15597 #define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT           (1U)
15598 #define CAAM_PX_SMAG1_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK)
15599 
15600 #define CAAM_PX_SMAG1_JR_Gx_ID02_MASK            (0x4U)
15601 #define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT           (2U)
15602 #define CAAM_PX_SMAG1_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK)
15603 
15604 #define CAAM_PX_SMAG1_JR_Gx_ID03_MASK            (0x8U)
15605 #define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT           (3U)
15606 #define CAAM_PX_SMAG1_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK)
15607 
15608 #define CAAM_PX_SMAG1_JR_Gx_ID04_MASK            (0x10U)
15609 #define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT           (4U)
15610 #define CAAM_PX_SMAG1_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK)
15611 
15612 #define CAAM_PX_SMAG1_JR_Gx_ID05_MASK            (0x20U)
15613 #define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT           (5U)
15614 #define CAAM_PX_SMAG1_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK)
15615 
15616 #define CAAM_PX_SMAG1_JR_Gx_ID06_MASK            (0x40U)
15617 #define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT           (6U)
15618 #define CAAM_PX_SMAG1_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK)
15619 
15620 #define CAAM_PX_SMAG1_JR_Gx_ID07_MASK            (0x80U)
15621 #define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT           (7U)
15622 #define CAAM_PX_SMAG1_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK)
15623 
15624 #define CAAM_PX_SMAG1_JR_Gx_ID08_MASK            (0x100U)
15625 #define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT           (8U)
15626 #define CAAM_PX_SMAG1_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK)
15627 
15628 #define CAAM_PX_SMAG1_JR_Gx_ID09_MASK            (0x200U)
15629 #define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT           (9U)
15630 #define CAAM_PX_SMAG1_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK)
15631 
15632 #define CAAM_PX_SMAG1_JR_Gx_ID10_MASK            (0x400U)
15633 #define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT           (10U)
15634 #define CAAM_PX_SMAG1_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK)
15635 
15636 #define CAAM_PX_SMAG1_JR_Gx_ID11_MASK            (0x800U)
15637 #define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT           (11U)
15638 #define CAAM_PX_SMAG1_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK)
15639 
15640 #define CAAM_PX_SMAG1_JR_Gx_ID12_MASK            (0x1000U)
15641 #define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT           (12U)
15642 #define CAAM_PX_SMAG1_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK)
15643 
15644 #define CAAM_PX_SMAG1_JR_Gx_ID13_MASK            (0x2000U)
15645 #define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT           (13U)
15646 #define CAAM_PX_SMAG1_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK)
15647 
15648 #define CAAM_PX_SMAG1_JR_Gx_ID14_MASK            (0x4000U)
15649 #define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT           (14U)
15650 #define CAAM_PX_SMAG1_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK)
15651 
15652 #define CAAM_PX_SMAG1_JR_Gx_ID15_MASK            (0x8000U)
15653 #define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT           (15U)
15654 #define CAAM_PX_SMAG1_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK)
15655 
15656 #define CAAM_PX_SMAG1_JR_Gx_ID16_MASK            (0x10000U)
15657 #define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT           (16U)
15658 #define CAAM_PX_SMAG1_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK)
15659 
15660 #define CAAM_PX_SMAG1_JR_Gx_ID17_MASK            (0x20000U)
15661 #define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT           (17U)
15662 #define CAAM_PX_SMAG1_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK)
15663 
15664 #define CAAM_PX_SMAG1_JR_Gx_ID18_MASK            (0x40000U)
15665 #define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT           (18U)
15666 #define CAAM_PX_SMAG1_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK)
15667 
15668 #define CAAM_PX_SMAG1_JR_Gx_ID19_MASK            (0x80000U)
15669 #define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT           (19U)
15670 #define CAAM_PX_SMAG1_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK)
15671 
15672 #define CAAM_PX_SMAG1_JR_Gx_ID20_MASK            (0x100000U)
15673 #define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT           (20U)
15674 #define CAAM_PX_SMAG1_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK)
15675 
15676 #define CAAM_PX_SMAG1_JR_Gx_ID21_MASK            (0x200000U)
15677 #define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT           (21U)
15678 #define CAAM_PX_SMAG1_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK)
15679 
15680 #define CAAM_PX_SMAG1_JR_Gx_ID22_MASK            (0x400000U)
15681 #define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT           (22U)
15682 #define CAAM_PX_SMAG1_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK)
15683 
15684 #define CAAM_PX_SMAG1_JR_Gx_ID23_MASK            (0x800000U)
15685 #define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT           (23U)
15686 #define CAAM_PX_SMAG1_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK)
15687 
15688 #define CAAM_PX_SMAG1_JR_Gx_ID24_MASK            (0x1000000U)
15689 #define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT           (24U)
15690 #define CAAM_PX_SMAG1_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK)
15691 
15692 #define CAAM_PX_SMAG1_JR_Gx_ID25_MASK            (0x2000000U)
15693 #define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT           (25U)
15694 #define CAAM_PX_SMAG1_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK)
15695 
15696 #define CAAM_PX_SMAG1_JR_Gx_ID26_MASK            (0x4000000U)
15697 #define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT           (26U)
15698 #define CAAM_PX_SMAG1_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK)
15699 
15700 #define CAAM_PX_SMAG1_JR_Gx_ID27_MASK            (0x8000000U)
15701 #define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT           (27U)
15702 #define CAAM_PX_SMAG1_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK)
15703 
15704 #define CAAM_PX_SMAG1_JR_Gx_ID28_MASK            (0x10000000U)
15705 #define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT           (28U)
15706 #define CAAM_PX_SMAG1_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK)
15707 
15708 #define CAAM_PX_SMAG1_JR_Gx_ID29_MASK            (0x20000000U)
15709 #define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT           (29U)
15710 #define CAAM_PX_SMAG1_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK)
15711 
15712 #define CAAM_PX_SMAG1_JR_Gx_ID30_MASK            (0x40000000U)
15713 #define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT           (30U)
15714 #define CAAM_PX_SMAG1_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK)
15715 
15716 #define CAAM_PX_SMAG1_JR_Gx_ID31_MASK            (0x80000000U)
15717 #define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT           (31U)
15718 #define CAAM_PX_SMAG1_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK)
15719 /*! @} */
15720 
15721 /* The count of CAAM_PX_SMAG1_JR */
15722 #define CAAM_PX_SMAG1_JR_COUNT                   (4U)
15723 
15724 /* The count of CAAM_PX_SMAG1_JR */
15725 #define CAAM_PX_SMAG1_JR_COUNT2                  (16U)
15726 
15727 /*! @name SMCR_JR - Secure Memory Command Register */
15728 /*! @{ */
15729 
15730 #define CAAM_SMCR_JR_CMD_MASK                    (0xFU)
15731 #define CAAM_SMCR_JR_CMD_SHIFT                   (0U)
15732 #define CAAM_SMCR_JR_CMD(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK)
15733 
15734 #define CAAM_SMCR_JR_PRTN_MASK                   (0xF00U)
15735 #define CAAM_SMCR_JR_PRTN_SHIFT                  (8U)
15736 #define CAAM_SMCR_JR_PRTN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK)
15737 
15738 #define CAAM_SMCR_JR_PAGE_MASK                   (0xFFFF0000U)
15739 #define CAAM_SMCR_JR_PAGE_SHIFT                  (16U)
15740 #define CAAM_SMCR_JR_PAGE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK)
15741 /*! @} */
15742 
15743 /* The count of CAAM_SMCR_JR */
15744 #define CAAM_SMCR_JR_COUNT                       (4U)
15745 
15746 /*! @name SMCSR_JR - Secure Memory Command Status Register */
15747 /*! @{ */
15748 
15749 #define CAAM_SMCSR_JR_PRTN_MASK                  (0xFU)
15750 #define CAAM_SMCSR_JR_PRTN_SHIFT                 (0U)
15751 #define CAAM_SMCSR_JR_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK)
15752 
15753 #define CAAM_SMCSR_JR_PO_MASK                    (0xC0U)
15754 #define CAAM_SMCSR_JR_PO_SHIFT                   (6U)
15755 /*! PO
15756  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
15757  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
15758  *  0b01..Page does not exist in this version or is not initialized yet.
15759  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
15760  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
15761  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
15762  *        upon de-allocation.
15763  */
15764 #define CAAM_SMCSR_JR_PO(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK)
15765 
15766 #define CAAM_SMCSR_JR_AERR_MASK                  (0x3000U)
15767 #define CAAM_SMCSR_JR_AERR_SHIFT                 (12U)
15768 #define CAAM_SMCSR_JR_AERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK)
15769 
15770 #define CAAM_SMCSR_JR_CERR_MASK                  (0xC000U)
15771 #define CAAM_SMCSR_JR_CERR_SHIFT                 (14U)
15772 /*! CERR
15773  *  0b00..No Error.
15774  *  0b01..Command has not yet completed.
15775  *  0b10..A security failure occurred.
15776  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
15777  *        command completed. The additional command was ignored.
15778  */
15779 #define CAAM_SMCSR_JR_CERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK)
15780 
15781 #define CAAM_SMCSR_JR_PAGE_MASK                  (0xFFF0000U)
15782 #define CAAM_SMCSR_JR_PAGE_SHIFT                 (16U)
15783 #define CAAM_SMCSR_JR_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK)
15784 /*! @} */
15785 
15786 /* The count of CAAM_SMCSR_JR */
15787 #define CAAM_SMCSR_JR_COUNT                      (4U)
15788 
15789 /*! @name REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 */
15790 /*! @{ */
15791 
15792 #define CAAM_REIR0JR_TYPE_MASK                   (0x3000000U)
15793 #define CAAM_REIR0JR_TYPE_SHIFT                  (24U)
15794 #define CAAM_REIR0JR_TYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK)
15795 
15796 #define CAAM_REIR0JR_MISS_MASK                   (0x80000000U)
15797 #define CAAM_REIR0JR_MISS_SHIFT                  (31U)
15798 #define CAAM_REIR0JR_MISS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK)
15799 /*! @} */
15800 
15801 /* The count of CAAM_REIR0JR */
15802 #define CAAM_REIR0JR_COUNT                       (4U)
15803 
15804 /*! @name REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 */
15805 /*! @{ */
15806 
15807 #define CAAM_REIR2JR_ADDR_MASK                   (0xFFFFFFFFFU)
15808 #define CAAM_REIR2JR_ADDR_SHIFT                  (0U)
15809 #define CAAM_REIR2JR_ADDR(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK)
15810 /*! @} */
15811 
15812 /* The count of CAAM_REIR2JR */
15813 #define CAAM_REIR2JR_COUNT                       (4U)
15814 
15815 /*! @name REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 */
15816 /*! @{ */
15817 
15818 #define CAAM_REIR4JR_ICID_MASK                   (0x7FFU)
15819 #define CAAM_REIR4JR_ICID_SHIFT                  (0U)
15820 #define CAAM_REIR4JR_ICID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK)
15821 
15822 #define CAAM_REIR4JR_DID_MASK                    (0x7800U)
15823 #define CAAM_REIR4JR_DID_SHIFT                   (11U)
15824 #define CAAM_REIR4JR_DID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK)
15825 
15826 #define CAAM_REIR4JR_AXCACHE_MASK                (0xF0000U)
15827 #define CAAM_REIR4JR_AXCACHE_SHIFT               (16U)
15828 #define CAAM_REIR4JR_AXCACHE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK)
15829 
15830 #define CAAM_REIR4JR_AXPROT_MASK                 (0x700000U)
15831 #define CAAM_REIR4JR_AXPROT_SHIFT                (20U)
15832 #define CAAM_REIR4JR_AXPROT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK)
15833 
15834 #define CAAM_REIR4JR_RWB_MASK                    (0x800000U)
15835 #define CAAM_REIR4JR_RWB_SHIFT                   (23U)
15836 #define CAAM_REIR4JR_RWB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK)
15837 
15838 #define CAAM_REIR4JR_ERR_MASK                    (0x30000000U)
15839 #define CAAM_REIR4JR_ERR_SHIFT                   (28U)
15840 #define CAAM_REIR4JR_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK)
15841 
15842 #define CAAM_REIR4JR_MIX_MASK                    (0xC0000000U)
15843 #define CAAM_REIR4JR_MIX_SHIFT                   (30U)
15844 #define CAAM_REIR4JR_MIX(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK)
15845 /*! @} */
15846 
15847 /* The count of CAAM_REIR4JR */
15848 #define CAAM_REIR4JR_COUNT                       (4U)
15849 
15850 /*! @name REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 */
15851 /*! @{ */
15852 
15853 #define CAAM_REIR5JR_BID_MASK                    (0xF0000U)
15854 #define CAAM_REIR5JR_BID_SHIFT                   (16U)
15855 #define CAAM_REIR5JR_BID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK)
15856 
15857 #define CAAM_REIR5JR_BNDG_MASK                   (0x2000000U)
15858 #define CAAM_REIR5JR_BNDG_SHIFT                  (25U)
15859 #define CAAM_REIR5JR_BNDG(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK)
15860 
15861 #define CAAM_REIR5JR_TDSC_MASK                   (0x4000000U)
15862 #define CAAM_REIR5JR_TDSC_SHIFT                  (26U)
15863 #define CAAM_REIR5JR_TDSC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK)
15864 
15865 #define CAAM_REIR5JR_KMOD_MASK                   (0x8000000U)
15866 #define CAAM_REIR5JR_KMOD_SHIFT                  (27U)
15867 #define CAAM_REIR5JR_KMOD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK)
15868 
15869 #define CAAM_REIR5JR_KEY_MASK                    (0x10000000U)
15870 #define CAAM_REIR5JR_KEY_SHIFT                   (28U)
15871 #define CAAM_REIR5JR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK)
15872 
15873 #define CAAM_REIR5JR_SMA_MASK                    (0x20000000U)
15874 #define CAAM_REIR5JR_SMA_SHIFT                   (29U)
15875 #define CAAM_REIR5JR_SMA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK)
15876 /*! @} */
15877 
15878 /* The count of CAAM_REIR5JR */
15879 #define CAAM_REIR5JR_COUNT                       (4U)
15880 
15881 /*! @name RSTA - RTIC Status Register */
15882 /*! @{ */
15883 
15884 #define CAAM_RSTA_BSY_MASK                       (0x1U)
15885 #define CAAM_RSTA_BSY_SHIFT                      (0U)
15886 /*! BSY
15887  *  0b0..RTIC Idle.
15888  *  0b1..RTIC Busy.
15889  */
15890 #define CAAM_RSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK)
15891 
15892 #define CAAM_RSTA_HD_MASK                        (0x2U)
15893 #define CAAM_RSTA_HD_SHIFT                       (1U)
15894 /*! HD
15895  *  0b0..Boot authentication disabled
15896  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15897  */
15898 #define CAAM_RSTA_HD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK)
15899 
15900 #define CAAM_RSTA_SV_MASK                        (0x4U)
15901 #define CAAM_RSTA_SV_SHIFT                       (2U)
15902 /*! SV
15903  *  0b0..Memory block contents authenticated.
15904  *  0b1..Memory block hash doesn't match reference value.
15905  */
15906 #define CAAM_RSTA_SV(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK)
15907 
15908 #define CAAM_RSTA_HE_MASK                        (0x8U)
15909 #define CAAM_RSTA_HE_SHIFT                       (3U)
15910 /*! HE
15911  *  0b0..Memory block contents authenticated.
15912  *  0b1..Memory block hash doesn't match reference value.
15913  */
15914 #define CAAM_RSTA_HE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK)
15915 
15916 #define CAAM_RSTA_MIS_MASK                       (0xF0U)
15917 #define CAAM_RSTA_MIS_SHIFT                      (4U)
15918 /*! MIS
15919  *  0b0000..Memory Block X is valid or state unknown
15920  *  0b0001..Memory Block X has been corrupted
15921  */
15922 #define CAAM_RSTA_MIS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK)
15923 
15924 #define CAAM_RSTA_AE_MASK                        (0xF00U)
15925 #define CAAM_RSTA_AE_SHIFT                       (8U)
15926 /*! AE
15927  *  0b0000..All reads by RTIC were valid.
15928  *  0b0001..An illegal address was accessed by the RTIC
15929  */
15930 #define CAAM_RSTA_AE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK)
15931 
15932 #define CAAM_RSTA_WE_MASK                        (0x10000U)
15933 #define CAAM_RSTA_WE_SHIFT                       (16U)
15934 /*! WE
15935  *  0b0..No RTIC Watchdog timer error has occurred.
15936  *  0b1..RTIC Watchdog timer has expired prior to completing a round of hashing.
15937  */
15938 #define CAAM_RSTA_WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK)
15939 
15940 #define CAAM_RSTA_ABH_MASK                       (0x20000U)
15941 #define CAAM_RSTA_ABH_SHIFT                      (17U)
15942 #define CAAM_RSTA_ABH(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK)
15943 
15944 #define CAAM_RSTA_HOD_MASK                       (0x40000U)
15945 #define CAAM_RSTA_HOD_SHIFT                      (18U)
15946 #define CAAM_RSTA_HOD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK)
15947 
15948 #define CAAM_RSTA_RTD_MASK                       (0x80000U)
15949 #define CAAM_RSTA_RTD_SHIFT                      (19U)
15950 #define CAAM_RSTA_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK)
15951 
15952 #define CAAM_RSTA_CS_MASK                        (0x6000000U)
15953 #define CAAM_RSTA_CS_SHIFT                       (25U)
15954 /*! CS
15955  *  0b00..Idle State
15956  *  0b01..Single Hash State
15957  *  0b10..Run-time State
15958  *  0b11..Error State
15959  */
15960 #define CAAM_RSTA_CS(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK)
15961 /*! @} */
15962 
15963 /*! @name RCMD - RTIC Command Register */
15964 /*! @{ */
15965 
15966 #define CAAM_RCMD_CINT_MASK                      (0x1U)
15967 #define CAAM_RCMD_CINT_SHIFT                     (0U)
15968 /*! CINT
15969  *  0b0..Do not clear interrupt
15970  *  0b1..Clear interrupt. This bit cannot be modified during run-time checking mode
15971  */
15972 #define CAAM_RCMD_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK)
15973 
15974 #define CAAM_RCMD_HO_MASK                        (0x2U)
15975 #define CAAM_RCMD_HO_SHIFT                       (1U)
15976 /*! HO
15977  *  0b0..Boot authentication disabled
15978  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15979  */
15980 #define CAAM_RCMD_HO(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK)
15981 
15982 #define CAAM_RCMD_RTC_MASK                       (0x4U)
15983 #define CAAM_RCMD_RTC_SHIFT                      (2U)
15984 /*! RTC
15985  *  0b0..Run-time checking disabled
15986  *  0b1..Verify run-time memory blocks continually
15987  */
15988 #define CAAM_RCMD_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK)
15989 
15990 #define CAAM_RCMD_RTD_MASK                       (0x8U)
15991 #define CAAM_RCMD_RTD_SHIFT                      (3U)
15992 /*! RTD
15993  *  0b0..Allow Run Time Mode
15994  *  0b1..Prevent Run Time Mode
15995  */
15996 #define CAAM_RCMD_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK)
15997 /*! @} */
15998 
15999 /*! @name RCTL - RTIC Control Register */
16000 /*! @{ */
16001 
16002 #define CAAM_RCTL_IE_MASK                        (0x1U)
16003 #define CAAM_RCTL_IE_SHIFT                       (0U)
16004 /*! IE
16005  *  0b0..Interrupts disabled
16006  *  0b1..Interrupts enabled
16007  */
16008 #define CAAM_RCTL_IE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK)
16009 
16010 #define CAAM_RCTL_RREQS_MASK                     (0xEU)
16011 #define CAAM_RCTL_RREQS_SHIFT                    (1U)
16012 #define CAAM_RCTL_RREQS(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK)
16013 
16014 #define CAAM_RCTL_HOME_MASK                      (0xF0U)
16015 #define CAAM_RCTL_HOME_SHIFT                     (4U)
16016 #define CAAM_RCTL_HOME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK)
16017 
16018 #define CAAM_RCTL_RTME_MASK                      (0xF00U)
16019 #define CAAM_RCTL_RTME_SHIFT                     (8U)
16020 #define CAAM_RCTL_RTME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK)
16021 
16022 #define CAAM_RCTL_RTMU_MASK                      (0xF000U)
16023 #define CAAM_RCTL_RTMU_SHIFT                     (12U)
16024 #define CAAM_RCTL_RTMU(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK)
16025 
16026 #define CAAM_RCTL_RALG_MASK                      (0xF0000U)
16027 #define CAAM_RCTL_RALG_SHIFT                     (16U)
16028 #define CAAM_RCTL_RALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK)
16029 
16030 #define CAAM_RCTL_RIDLE_MASK                     (0x100000U)
16031 #define CAAM_RCTL_RIDLE_SHIFT                    (20U)
16032 #define CAAM_RCTL_RIDLE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK)
16033 /*! @} */
16034 
16035 /*! @name RTHR - RTIC Throttle Register */
16036 /*! @{ */
16037 
16038 #define CAAM_RTHR_RTHR_MASK                      (0xFFFFU)
16039 #define CAAM_RTHR_RTHR_SHIFT                     (0U)
16040 #define CAAM_RTHR_RTHR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK)
16041 /*! @} */
16042 
16043 /*! @name RWDOG - RTIC Watchdog Timer */
16044 /*! @{ */
16045 
16046 #define CAAM_RWDOG_RWDOG_MASK                    (0xFFFFFFFFU)
16047 #define CAAM_RWDOG_RWDOG_SHIFT                   (0U)
16048 #define CAAM_RWDOG_RWDOG(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK)
16049 /*! @} */
16050 
16051 /*! @name REND - RTIC Endian Register */
16052 /*! @{ */
16053 
16054 #define CAAM_REND_REPO_MASK                      (0xFU)
16055 #define CAAM_REND_REPO_SHIFT                     (0U)
16056 /*! REPO
16057  *  0bxxx1..Byte Swap Memory Block A
16058  *  0bxx1x..Byte Swap Memory Block B
16059  *  0bx1xx..Byte Swap Memory Block C
16060  *  0b1xxx..Byte Swap Memory Block D
16061  */
16062 #define CAAM_REND_REPO(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK)
16063 
16064 #define CAAM_REND_RBS_MASK                       (0xF0U)
16065 #define CAAM_REND_RBS_SHIFT                      (4U)
16066 /*! RBS
16067  *  0bxxx1..Byte Swap Memory Block A
16068  *  0bxx1x..Byte Swap Memory Block B
16069  *  0bx1xx..Byte Swap Memory Block C
16070  *  0b1xxx..Byte Swap Memory Block D
16071  */
16072 #define CAAM_REND_RBS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK)
16073 
16074 #define CAAM_REND_RHWS_MASK                      (0xF00U)
16075 #define CAAM_REND_RHWS_SHIFT                     (8U)
16076 /*! RHWS
16077  *  0bxxx1..Half-Word Swap Memory Block A
16078  *  0bxx1x..Half-Word Swap Memory Block B
16079  *  0bx1xx..Half-Word Swap Memory Block C
16080  *  0b1xxx..Half-Word Swap Memory Block D
16081  */
16082 #define CAAM_REND_RHWS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK)
16083 
16084 #define CAAM_REND_RWS_MASK                       (0xF000U)
16085 #define CAAM_REND_RWS_SHIFT                      (12U)
16086 /*! RWS
16087  *  0bxxx1..Word Swap Memory Block A
16088  *  0bxx1x..Word Swap Memory Block B
16089  *  0bx1xx..Word Swap Memory Block C
16090  *  0b1xxx..Word Swap Memory Block D
16091  */
16092 #define CAAM_REND_RWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK)
16093 /*! @} */
16094 
16095 /*! @name RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register */
16096 /*! @{ */
16097 
16098 #define CAAM_RMA_MEMBLKADDR_MASK                 (0xFFFFFFFFFU)
16099 #define CAAM_RMA_MEMBLKADDR_SHIFT                (0U)
16100 #define CAAM_RMA_MEMBLKADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK)
16101 /*! @} */
16102 
16103 /* The count of CAAM_RMA */
16104 #define CAAM_RMA_COUNT                           (4U)
16105 
16106 /* The count of CAAM_RMA */
16107 #define CAAM_RMA_COUNT2                          (2U)
16108 
16109 /*! @name RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register */
16110 /*! @{ */
16111 
16112 #define CAAM_RML_MEMBLKLEN_MASK                  (0xFFFFFFFFU)
16113 #define CAAM_RML_MEMBLKLEN_SHIFT                 (0U)
16114 #define CAAM_RML_MEMBLKLEN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK)
16115 /*! @} */
16116 
16117 /* The count of CAAM_RML */
16118 #define CAAM_RML_COUNT                           (4U)
16119 
16120 /* The count of CAAM_RML */
16121 #define CAAM_RML_COUNT2                          (2U)
16122 
16123 /*! @name RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 */
16124 /*! @{ */
16125 
16126 #define CAAM_RMD_RTIC_Hash_Result_MASK           (0xFFFFFFFFU)
16127 #define CAAM_RMD_RTIC_Hash_Result_SHIFT          (0U)
16128 #define CAAM_RMD_RTIC_Hash_Result(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK)
16129 /*! @} */
16130 
16131 /* The count of CAAM_RMD */
16132 #define CAAM_RMD_COUNT                           (4U)
16133 
16134 /* The count of CAAM_RMD */
16135 #define CAAM_RMD_COUNT2                          (2U)
16136 
16137 /* The count of CAAM_RMD */
16138 #define CAAM_RMD_COUNT3                          (32U)
16139 
16140 /*! @name REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC */
16141 /*! @{ */
16142 
16143 #define CAAM_REIR0RTIC_TYPE_MASK                 (0x3000000U)
16144 #define CAAM_REIR0RTIC_TYPE_SHIFT                (24U)
16145 #define CAAM_REIR0RTIC_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK)
16146 
16147 #define CAAM_REIR0RTIC_MISS_MASK                 (0x80000000U)
16148 #define CAAM_REIR0RTIC_MISS_SHIFT                (31U)
16149 #define CAAM_REIR0RTIC_MISS(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK)
16150 /*! @} */
16151 
16152 /*! @name REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC */
16153 /*! @{ */
16154 
16155 #define CAAM_REIR2RTIC_ADDR_MASK                 (0xFFFFFFFFFFFFFFFFU)
16156 #define CAAM_REIR2RTIC_ADDR_SHIFT                (0U)
16157 #define CAAM_REIR2RTIC_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK)
16158 /*! @} */
16159 
16160 /*! @name REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC */
16161 /*! @{ */
16162 
16163 #define CAAM_REIR4RTIC_ICID_MASK                 (0x7FFU)
16164 #define CAAM_REIR4RTIC_ICID_SHIFT                (0U)
16165 #define CAAM_REIR4RTIC_ICID(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK)
16166 
16167 #define CAAM_REIR4RTIC_DID_MASK                  (0x7800U)
16168 #define CAAM_REIR4RTIC_DID_SHIFT                 (11U)
16169 #define CAAM_REIR4RTIC_DID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK)
16170 
16171 #define CAAM_REIR4RTIC_AXCACHE_MASK              (0xF0000U)
16172 #define CAAM_REIR4RTIC_AXCACHE_SHIFT             (16U)
16173 #define CAAM_REIR4RTIC_AXCACHE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK)
16174 
16175 #define CAAM_REIR4RTIC_AXPROT_MASK               (0x700000U)
16176 #define CAAM_REIR4RTIC_AXPROT_SHIFT              (20U)
16177 #define CAAM_REIR4RTIC_AXPROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK)
16178 
16179 #define CAAM_REIR4RTIC_RWB_MASK                  (0x800000U)
16180 #define CAAM_REIR4RTIC_RWB_SHIFT                 (23U)
16181 #define CAAM_REIR4RTIC_RWB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK)
16182 
16183 #define CAAM_REIR4RTIC_ERR_MASK                  (0x30000000U)
16184 #define CAAM_REIR4RTIC_ERR_SHIFT                 (28U)
16185 #define CAAM_REIR4RTIC_ERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK)
16186 
16187 #define CAAM_REIR4RTIC_MIX_MASK                  (0xC0000000U)
16188 #define CAAM_REIR4RTIC_MIX_SHIFT                 (30U)
16189 #define CAAM_REIR4RTIC_MIX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK)
16190 /*! @} */
16191 
16192 /*! @name REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC */
16193 /*! @{ */
16194 
16195 #define CAAM_REIR5RTIC_BID_MASK                  (0xF0000U)
16196 #define CAAM_REIR5RTIC_BID_SHIFT                 (16U)
16197 #define CAAM_REIR5RTIC_BID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK)
16198 
16199 #define CAAM_REIR5RTIC_SAFE_MASK                 (0x1000000U)
16200 #define CAAM_REIR5RTIC_SAFE_SHIFT                (24U)
16201 #define CAAM_REIR5RTIC_SAFE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK)
16202 
16203 #define CAAM_REIR5RTIC_SMA_MASK                  (0x2000000U)
16204 #define CAAM_REIR5RTIC_SMA_SHIFT                 (25U)
16205 #define CAAM_REIR5RTIC_SMA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK)
16206 /*! @} */
16207 
16208 /*! @name CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms */
16209 /*! @{ */
16210 
16211 #define CAAM_CC1MR_ENC_MASK                      (0x1U)
16212 #define CAAM_CC1MR_ENC_SHIFT                     (0U)
16213 /*! ENC
16214  *  0b0..Decrypt.
16215  *  0b1..Encrypt.
16216  */
16217 #define CAAM_CC1MR_ENC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK)
16218 
16219 #define CAAM_CC1MR_ICV_TEST_MASK                 (0x2U)
16220 #define CAAM_CC1MR_ICV_TEST_SHIFT                (1U)
16221 #define CAAM_CC1MR_ICV_TEST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK)
16222 
16223 #define CAAM_CC1MR_AS_MASK                       (0xCU)
16224 #define CAAM_CC1MR_AS_SHIFT                      (2U)
16225 /*! AS
16226  *  0b00..Update
16227  *  0b01..Initialize
16228  *  0b10..Finalize
16229  *  0b11..Initialize/Finalize
16230  */
16231 #define CAAM_CC1MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK)
16232 
16233 #define CAAM_CC1MR_AAI_MASK                      (0x1FF0U)
16234 #define CAAM_CC1MR_AAI_SHIFT                     (4U)
16235 #define CAAM_CC1MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK)
16236 
16237 #define CAAM_CC1MR_ALG_MASK                      (0xFF0000U)
16238 #define CAAM_CC1MR_ALG_SHIFT                     (16U)
16239 /*! ALG
16240  *  0b00010000..AES
16241  *  0b00100000..DES
16242  *  0b00100001..3DES
16243  *  0b01010000..RNG
16244  */
16245 #define CAAM_CC1MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK)
16246 /*! @} */
16247 
16248 /* The count of CAAM_CC1MR */
16249 #define CAAM_CC1MR_COUNT                         (1U)
16250 
16251 /*! @name CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms */
16252 /*! @{ */
16253 
16254 #define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK          (0xFFFU)
16255 #define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT         (0U)
16256 #define CAAM_CC1MR_PK_PKHA_MODE_LS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK)
16257 
16258 #define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK          (0xF0000U)
16259 #define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT         (16U)
16260 #define CAAM_CC1MR_PK_PKHA_MODE_MS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK)
16261 /*! @} */
16262 
16263 /* The count of CAAM_CC1MR_PK */
16264 #define CAAM_CC1MR_PK_COUNT                      (1U)
16265 
16266 /*! @name CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 */
16267 /*! @{ */
16268 
16269 #define CAAM_CC1MR_RNG_TST_MASK                  (0x1U)
16270 #define CAAM_CC1MR_RNG_TST_SHIFT                 (0U)
16271 #define CAAM_CC1MR_RNG_TST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK)
16272 
16273 #define CAAM_CC1MR_RNG_PR_MASK                   (0x2U)
16274 #define CAAM_CC1MR_RNG_PR_SHIFT                  (1U)
16275 #define CAAM_CC1MR_RNG_PR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK)
16276 
16277 #define CAAM_CC1MR_RNG_AS_MASK                   (0xCU)
16278 #define CAAM_CC1MR_RNG_AS_SHIFT                  (2U)
16279 #define CAAM_CC1MR_RNG_AS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK)
16280 
16281 #define CAAM_CC1MR_RNG_SH_MASK                   (0x30U)
16282 #define CAAM_CC1MR_RNG_SH_SHIFT                  (4U)
16283 /*! SH
16284  *  0b00..State Handle 0
16285  *  0b01..State Handle 1
16286  *  0b10..Reserved
16287  *  0b11..Reserved
16288  */
16289 #define CAAM_CC1MR_RNG_SH(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK)
16290 
16291 #define CAAM_CC1MR_RNG_NZB_MASK                  (0x100U)
16292 #define CAAM_CC1MR_RNG_NZB_SHIFT                 (8U)
16293 /*! NZB
16294  *  0b0..Generate random data with all-zero bytes permitted.
16295  *  0b1..Generate random data without any all-zero bytes.
16296  */
16297 #define CAAM_CC1MR_RNG_NZB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK)
16298 
16299 #define CAAM_CC1MR_RNG_OBP_MASK                  (0x200U)
16300 #define CAAM_CC1MR_RNG_OBP_SHIFT                 (9U)
16301 /*! OBP
16302  *  0b0..No odd byte parity.
16303  *  0b1..Generate random data with odd byte parity.
16304  */
16305 #define CAAM_CC1MR_RNG_OBP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK)
16306 
16307 #define CAAM_CC1MR_RNG_PS_MASK                   (0x400U)
16308 #define CAAM_CC1MR_RNG_PS_SHIFT                  (10U)
16309 /*! PS
16310  *  0b0..No personalization string is included.
16311  *  0b1..A personalization string is included.
16312  */
16313 #define CAAM_CC1MR_RNG_PS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK)
16314 
16315 #define CAAM_CC1MR_RNG_AI_MASK                   (0x800U)
16316 #define CAAM_CC1MR_RNG_AI_SHIFT                  (11U)
16317 /*! AI
16318  *  0b0..No additional entropy input has been provided.
16319  *  0b1..Additional entropy input has been provided.
16320  */
16321 #define CAAM_CC1MR_RNG_AI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK)
16322 
16323 #define CAAM_CC1MR_RNG_SK_MASK                   (0x1000U)
16324 #define CAAM_CC1MR_RNG_SK_SHIFT                  (12U)
16325 /*! SK
16326  *  0b0..The destination for the RNG data is specified by the FIFO STORE command.
16327  *  0b1..The RNG data will go to the JDKEKR, TDKEKR and DSKR.
16328  */
16329 #define CAAM_CC1MR_RNG_SK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK)
16330 
16331 #define CAAM_CC1MR_RNG_ALG_MASK                  (0xFF0000U)
16332 #define CAAM_CC1MR_RNG_ALG_SHIFT                 (16U)
16333 /*! ALG
16334  *  0b01010000..RNG
16335  */
16336 #define CAAM_CC1MR_RNG_ALG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK)
16337 /*! @} */
16338 
16339 /* The count of CAAM_CC1MR_RNG */
16340 #define CAAM_CC1MR_RNG_COUNT                     (1U)
16341 
16342 /*! @name CC1KSR - CCB 0 Class 1 Key Size Register */
16343 /*! @{ */
16344 
16345 #define CAAM_CC1KSR_C1KS_MASK                    (0x7FU)
16346 #define CAAM_CC1KSR_C1KS_SHIFT                   (0U)
16347 #define CAAM_CC1KSR_C1KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK)
16348 /*! @} */
16349 
16350 /* The count of CAAM_CC1KSR */
16351 #define CAAM_CC1KSR_COUNT                        (1U)
16352 
16353 /*! @name CC1DSR - CCB 0 Class 1 Data Size Register */
16354 /*! @{ */
16355 
16356 #define CAAM_CC1DSR_C1DS_MASK                    (0xFFFFFFFFU)
16357 #define CAAM_CC1DSR_C1DS_SHIFT                   (0U)
16358 #define CAAM_CC1DSR_C1DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK)
16359 
16360 #define CAAM_CC1DSR_C1CY_MASK                    (0x100000000U)
16361 #define CAAM_CC1DSR_C1CY_SHIFT                   (32U)
16362 /*! C1CY
16363  *  0b0..No carry out of the C1 Data Size Reg.
16364  *  0b1..There was a carry out of the C1 Data Size Reg.
16365  */
16366 #define CAAM_CC1DSR_C1CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK)
16367 
16368 #define CAAM_CC1DSR_NUMBITS_MASK                 (0xE000000000000000U)
16369 #define CAAM_CC1DSR_NUMBITS_SHIFT                (61U)
16370 #define CAAM_CC1DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK)
16371 /*! @} */
16372 
16373 /* The count of CAAM_CC1DSR */
16374 #define CAAM_CC1DSR_COUNT                        (1U)
16375 
16376 /*! @name CC1ICVSR - CCB 0 Class 1 ICV Size Register */
16377 /*! @{ */
16378 
16379 #define CAAM_CC1ICVSR_C1ICVS_MASK                (0x1FU)
16380 #define CAAM_CC1ICVSR_C1ICVS_SHIFT               (0U)
16381 #define CAAM_CC1ICVSR_C1ICVS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK)
16382 /*! @} */
16383 
16384 /* The count of CAAM_CC1ICVSR */
16385 #define CAAM_CC1ICVSR_COUNT                      (1U)
16386 
16387 /*! @name CCCTRL - CCB 0 CHA Control Register */
16388 /*! @{ */
16389 
16390 #define CAAM_CCCTRL_CCB_MASK                     (0x1U)
16391 #define CAAM_CCCTRL_CCB_SHIFT                    (0U)
16392 /*! CCB
16393  *  0b0..Do Not Reset
16394  *  0b1..Reset CCB
16395  */
16396 #define CAAM_CCCTRL_CCB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK)
16397 
16398 #define CAAM_CCCTRL_AES_MASK                     (0x2U)
16399 #define CAAM_CCCTRL_AES_SHIFT                    (1U)
16400 /*! AES
16401  *  0b0..Do Not Reset
16402  *  0b1..Reset AES Accelerator
16403  */
16404 #define CAAM_CCCTRL_AES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK)
16405 
16406 #define CAAM_CCCTRL_DES_MASK                     (0x4U)
16407 #define CAAM_CCCTRL_DES_SHIFT                    (2U)
16408 /*! DES
16409  *  0b0..Do Not Reset
16410  *  0b1..Reset DES Accelerator
16411  */
16412 #define CAAM_CCCTRL_DES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK)
16413 
16414 #define CAAM_CCCTRL_PK_MASK                      (0x40U)
16415 #define CAAM_CCCTRL_PK_SHIFT                     (6U)
16416 /*! PK
16417  *  0b0..Do Not Reset
16418  *  0b1..Reset Public Key Hardware Accelerator
16419  */
16420 #define CAAM_CCCTRL_PK(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK)
16421 
16422 #define CAAM_CCCTRL_MD_MASK                      (0x80U)
16423 #define CAAM_CCCTRL_MD_SHIFT                     (7U)
16424 /*! MD
16425  *  0b0..Do Not Reset
16426  *  0b1..Reset Message Digest Hardware Accelerator
16427  */
16428 #define CAAM_CCCTRL_MD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK)
16429 
16430 #define CAAM_CCCTRL_CRC_MASK                     (0x100U)
16431 #define CAAM_CCCTRL_CRC_SHIFT                    (8U)
16432 /*! CRC
16433  *  0b0..Do Not Reset
16434  *  0b1..Reset CRC Accelerator
16435  */
16436 #define CAAM_CCCTRL_CRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK)
16437 
16438 #define CAAM_CCCTRL_RNG_MASK                     (0x200U)
16439 #define CAAM_CCCTRL_RNG_SHIFT                    (9U)
16440 /*! RNG
16441  *  0b0..Do Not Reset
16442  *  0b1..Reset Random Number Generator Block.
16443  */
16444 #define CAAM_CCCTRL_RNG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK)
16445 
16446 #define CAAM_CCCTRL_UA0_MASK                     (0x10000U)
16447 #define CAAM_CCCTRL_UA0_SHIFT                    (16U)
16448 /*! UA0
16449  *  0b0..Don't unload the PKHA A0 Memory.
16450  *  0b1..Unload the PKHA A0 Memory into OFIFO.
16451  */
16452 #define CAAM_CCCTRL_UA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK)
16453 
16454 #define CAAM_CCCTRL_UA1_MASK                     (0x20000U)
16455 #define CAAM_CCCTRL_UA1_SHIFT                    (17U)
16456 /*! UA1
16457  *  0b0..Don't unload the PKHA A1 Memory.
16458  *  0b1..Unload the PKHA A1 Memory into OFIFO.
16459  */
16460 #define CAAM_CCCTRL_UA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK)
16461 
16462 #define CAAM_CCCTRL_UA2_MASK                     (0x40000U)
16463 #define CAAM_CCCTRL_UA2_SHIFT                    (18U)
16464 /*! UA2
16465  *  0b0..Don't unload the PKHA A2 Memory.
16466  *  0b1..Unload the PKHA A2 Memory into OFIFO.
16467  */
16468 #define CAAM_CCCTRL_UA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK)
16469 
16470 #define CAAM_CCCTRL_UA3_MASK                     (0x80000U)
16471 #define CAAM_CCCTRL_UA3_SHIFT                    (19U)
16472 /*! UA3
16473  *  0b0..Don't unload the PKHA A3 Memory.
16474  *  0b1..Unload the PKHA A3 Memory into OFIFO.
16475  */
16476 #define CAAM_CCCTRL_UA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK)
16477 
16478 #define CAAM_CCCTRL_UB0_MASK                     (0x100000U)
16479 #define CAAM_CCCTRL_UB0_SHIFT                    (20U)
16480 /*! UB0
16481  *  0b0..Don't unload the PKHA B0 Memory.
16482  *  0b1..Unload the PKHA B0 Memory into OFIFO.
16483  */
16484 #define CAAM_CCCTRL_UB0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK)
16485 
16486 #define CAAM_CCCTRL_UB1_MASK                     (0x200000U)
16487 #define CAAM_CCCTRL_UB1_SHIFT                    (21U)
16488 /*! UB1
16489  *  0b0..Don't unload the PKHA B1 Memory.
16490  *  0b1..Unload the PKHA B1 Memory into OFIFO.
16491  */
16492 #define CAAM_CCCTRL_UB1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK)
16493 
16494 #define CAAM_CCCTRL_UB2_MASK                     (0x400000U)
16495 #define CAAM_CCCTRL_UB2_SHIFT                    (22U)
16496 /*! UB2
16497  *  0b0..Don't unload the PKHA B2 Memory.
16498  *  0b1..Unload the PKHA B2 Memory into OFIFO.
16499  */
16500 #define CAAM_CCCTRL_UB2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK)
16501 
16502 #define CAAM_CCCTRL_UB3_MASK                     (0x800000U)
16503 #define CAAM_CCCTRL_UB3_SHIFT                    (23U)
16504 /*! UB3
16505  *  0b0..Don't unload the PKHA B3 Memory.
16506  *  0b1..Unload the PKHA B3 Memory into OFIFO.
16507  */
16508 #define CAAM_CCCTRL_UB3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK)
16509 
16510 #define CAAM_CCCTRL_UN_MASK                      (0x1000000U)
16511 #define CAAM_CCCTRL_UN_SHIFT                     (24U)
16512 /*! UN
16513  *  0b0..Don't unload the PKHA N Memory.
16514  *  0b1..Unload the PKHA N Memory into OFIFO.
16515  */
16516 #define CAAM_CCCTRL_UN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK)
16517 
16518 #define CAAM_CCCTRL_UA_MASK                      (0x4000000U)
16519 #define CAAM_CCCTRL_UA_SHIFT                     (26U)
16520 /*! UA
16521  *  0b0..Don't unload the PKHA A Memory.
16522  *  0b1..Unload the PKHA A Memory into OFIFO.
16523  */
16524 #define CAAM_CCCTRL_UA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK)
16525 
16526 #define CAAM_CCCTRL_UB_MASK                      (0x8000000U)
16527 #define CAAM_CCCTRL_UB_SHIFT                     (27U)
16528 /*! UB
16529  *  0b0..Don't unload the PKHA B Memory.
16530  *  0b1..Unload the PKHA B Memory into OFIFO.
16531  */
16532 #define CAAM_CCCTRL_UB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK)
16533 /*! @} */
16534 
16535 /* The count of CAAM_CCCTRL */
16536 #define CAAM_CCCTRL_COUNT                        (1U)
16537 
16538 /*! @name CICTL - CCB 0 Interrupt Control Register */
16539 /*! @{ */
16540 
16541 #define CAAM_CICTL_ADI_MASK                      (0x2U)
16542 #define CAAM_CICTL_ADI_SHIFT                     (1U)
16543 #define CAAM_CICTL_ADI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK)
16544 
16545 #define CAAM_CICTL_DDI_MASK                      (0x4U)
16546 #define CAAM_CICTL_DDI_SHIFT                     (2U)
16547 #define CAAM_CICTL_DDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK)
16548 
16549 #define CAAM_CICTL_PDI_MASK                      (0x40U)
16550 #define CAAM_CICTL_PDI_SHIFT                     (6U)
16551 #define CAAM_CICTL_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK)
16552 
16553 #define CAAM_CICTL_MDI_MASK                      (0x80U)
16554 #define CAAM_CICTL_MDI_SHIFT                     (7U)
16555 #define CAAM_CICTL_MDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK)
16556 
16557 #define CAAM_CICTL_CDI_MASK                      (0x100U)
16558 #define CAAM_CICTL_CDI_SHIFT                     (8U)
16559 #define CAAM_CICTL_CDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK)
16560 
16561 #define CAAM_CICTL_RNDI_MASK                     (0x200U)
16562 #define CAAM_CICTL_RNDI_SHIFT                    (9U)
16563 #define CAAM_CICTL_RNDI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK)
16564 
16565 #define CAAM_CICTL_AEI_MASK                      (0x20000U)
16566 #define CAAM_CICTL_AEI_SHIFT                     (17U)
16567 /*! AEI
16568  *  0b0..No AESA error detected
16569  *  0b1..AESA error detected
16570  */
16571 #define CAAM_CICTL_AEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK)
16572 
16573 #define CAAM_CICTL_DEI_MASK                      (0x40000U)
16574 #define CAAM_CICTL_DEI_SHIFT                     (18U)
16575 /*! DEI
16576  *  0b0..No DESA error detected
16577  *  0b1..DESA error detected
16578  */
16579 #define CAAM_CICTL_DEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK)
16580 
16581 #define CAAM_CICTL_PEI_MASK                      (0x400000U)
16582 #define CAAM_CICTL_PEI_SHIFT                     (22U)
16583 /*! PEI
16584  *  0b0..No PKHA error detected
16585  *  0b1..PKHA error detected
16586  */
16587 #define CAAM_CICTL_PEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK)
16588 
16589 #define CAAM_CICTL_MEI_MASK                      (0x800000U)
16590 #define CAAM_CICTL_MEI_SHIFT                     (23U)
16591 /*! MEI
16592  *  0b0..No MDHA error detected
16593  *  0b1..MDHA error detected
16594  */
16595 #define CAAM_CICTL_MEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK)
16596 
16597 #define CAAM_CICTL_CEI_MASK                      (0x1000000U)
16598 #define CAAM_CICTL_CEI_SHIFT                     (24U)
16599 /*! CEI
16600  *  0b0..No CRCA error detected
16601  *  0b1..CRCA error detected
16602  */
16603 #define CAAM_CICTL_CEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK)
16604 
16605 #define CAAM_CICTL_RNEI_MASK                     (0x2000000U)
16606 #define CAAM_CICTL_RNEI_SHIFT                    (25U)
16607 /*! RNEI
16608  *  0b0..No RNG error detected
16609  *  0b1..RNG error detected
16610  */
16611 #define CAAM_CICTL_RNEI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK)
16612 /*! @} */
16613 
16614 /* The count of CAAM_CICTL */
16615 #define CAAM_CICTL_COUNT                         (1U)
16616 
16617 /*! @name CCWR - CCB 0 Clear Written Register */
16618 /*! @{ */
16619 
16620 #define CAAM_CCWR_C1M_MASK                       (0x1U)
16621 #define CAAM_CCWR_C1M_SHIFT                      (0U)
16622 /*! C1M
16623  *  0b0..Don't clear the Class 1 Mode Register.
16624  *  0b1..Clear the Class 1 Mode Register.
16625  */
16626 #define CAAM_CCWR_C1M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK)
16627 
16628 #define CAAM_CCWR_C1DS_MASK                      (0x4U)
16629 #define CAAM_CCWR_C1DS_SHIFT                     (2U)
16630 /*! C1DS
16631  *  0b0..Don't clear the Class 1 Data Size Register.
16632  *  0b1..Clear the Class 1 Data Size Register.
16633  */
16634 #define CAAM_CCWR_C1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK)
16635 
16636 #define CAAM_CCWR_C1ICV_MASK                     (0x8U)
16637 #define CAAM_CCWR_C1ICV_SHIFT                    (3U)
16638 /*! C1ICV
16639  *  0b0..Don't clear the Class 1 ICV Size Register.
16640  *  0b1..Clear the Class 1 ICV Size Register.
16641  */
16642 #define CAAM_CCWR_C1ICV(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK)
16643 
16644 #define CAAM_CCWR_C1C_MASK                       (0x20U)
16645 #define CAAM_CCWR_C1C_SHIFT                      (5U)
16646 /*! C1C
16647  *  0b0..Don't clear the Class 1 Context Register.
16648  *  0b1..Clear the Class 1 Context Register.
16649  */
16650 #define CAAM_CCWR_C1C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK)
16651 
16652 #define CAAM_CCWR_C1K_MASK                       (0x40U)
16653 #define CAAM_CCWR_C1K_SHIFT                      (6U)
16654 /*! C1K
16655  *  0b0..Don't clear the Class 1 Key Register.
16656  *  0b1..Clear the Class 1 Key Register.
16657  */
16658 #define CAAM_CCWR_C1K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK)
16659 
16660 #define CAAM_CCWR_CPKA_MASK                      (0x1000U)
16661 #define CAAM_CCWR_CPKA_SHIFT                     (12U)
16662 /*! CPKA
16663  *  0b0..Don't clear the PKHA A Size Register.
16664  *  0b1..Clear the PKHA A Size Register.
16665  */
16666 #define CAAM_CCWR_CPKA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK)
16667 
16668 #define CAAM_CCWR_CPKB_MASK                      (0x2000U)
16669 #define CAAM_CCWR_CPKB_SHIFT                     (13U)
16670 /*! CPKB
16671  *  0b0..Don't clear the PKHA B Size Register.
16672  *  0b1..Clear the PKHA B Size Register.
16673  */
16674 #define CAAM_CCWR_CPKB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK)
16675 
16676 #define CAAM_CCWR_CPKN_MASK                      (0x4000U)
16677 #define CAAM_CCWR_CPKN_SHIFT                     (14U)
16678 /*! CPKN
16679  *  0b0..Don't clear the PKHA N Size Register.
16680  *  0b1..Clear the PKHA N Size Register.
16681  */
16682 #define CAAM_CCWR_CPKN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK)
16683 
16684 #define CAAM_CCWR_CPKE_MASK                      (0x8000U)
16685 #define CAAM_CCWR_CPKE_SHIFT                     (15U)
16686 /*! CPKE
16687  *  0b0..Don't clear the PKHA E Size Register..
16688  *  0b1..Clear the PKHA E Size Register.
16689  */
16690 #define CAAM_CCWR_CPKE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK)
16691 
16692 #define CAAM_CCWR_C2M_MASK                       (0x10000U)
16693 #define CAAM_CCWR_C2M_SHIFT                      (16U)
16694 /*! C2M
16695  *  0b0..Don't clear the Class 2 Mode Register.
16696  *  0b1..Clear the Class 2 Mode Register.
16697  */
16698 #define CAAM_CCWR_C2M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK)
16699 
16700 #define CAAM_CCWR_C2DS_MASK                      (0x40000U)
16701 #define CAAM_CCWR_C2DS_SHIFT                     (18U)
16702 /*! C2DS
16703  *  0b0..Don't clear the Class 2 Data Size Register.
16704  *  0b1..Clear the Class 2 Data Size Register.
16705  */
16706 #define CAAM_CCWR_C2DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK)
16707 
16708 #define CAAM_CCWR_C2C_MASK                       (0x200000U)
16709 #define CAAM_CCWR_C2C_SHIFT                      (21U)
16710 /*! C2C
16711  *  0b0..Don't clear the Class 2 Context Register.
16712  *  0b1..Clear the Class 2 Context Register.
16713  */
16714 #define CAAM_CCWR_C2C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK)
16715 
16716 #define CAAM_CCWR_C2K_MASK                       (0x400000U)
16717 #define CAAM_CCWR_C2K_SHIFT                      (22U)
16718 /*! C2K
16719  *  0b0..Don't clear the Class 2 Key Register.
16720  *  0b1..Clear the Class 2 Key Register.
16721  */
16722 #define CAAM_CCWR_C2K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK)
16723 
16724 #define CAAM_CCWR_CDS_MASK                       (0x2000000U)
16725 #define CAAM_CCWR_CDS_SHIFT                      (25U)
16726 /*! CDS
16727  *  0b0..Don't clear the shared descriptor signal.
16728  *  0b1..Clear the shared descriptor signal.
16729  */
16730 #define CAAM_CCWR_CDS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK)
16731 
16732 #define CAAM_CCWR_C2D_MASK                       (0x4000000U)
16733 #define CAAM_CCWR_C2D_SHIFT                      (26U)
16734 /*! C2D
16735  *  0b0..Don't clear the Class 2 done interrrupt.
16736  *  0b1..Clear the Class 2 done interrrupt.
16737  */
16738 #define CAAM_CCWR_C2D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK)
16739 
16740 #define CAAM_CCWR_C1D_MASK                       (0x8000000U)
16741 #define CAAM_CCWR_C1D_SHIFT                      (27U)
16742 /*! C1D
16743  *  0b0..Don't clear the Class 1 done interrrupt.
16744  *  0b1..Clear the Class 1 done interrrupt.
16745  */
16746 #define CAAM_CCWR_C1D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK)
16747 
16748 #define CAAM_CCWR_C2RST_MASK                     (0x10000000U)
16749 #define CAAM_CCWR_C2RST_SHIFT                    (28U)
16750 /*! C2RST
16751  *  0b0..Don't reset the Class 2 CHA.
16752  *  0b1..Reset the Class 2 CHA.
16753  */
16754 #define CAAM_CCWR_C2RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK)
16755 
16756 #define CAAM_CCWR_C1RST_MASK                     (0x20000000U)
16757 #define CAAM_CCWR_C1RST_SHIFT                    (29U)
16758 /*! C1RST
16759  *  0b0..Don't reset the Class 1 CHA.
16760  *  0b1..Reset the Class 1 CHA.
16761  */
16762 #define CAAM_CCWR_C1RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK)
16763 
16764 #define CAAM_CCWR_COF_MASK                       (0x40000000U)
16765 #define CAAM_CCWR_COF_SHIFT                      (30U)
16766 /*! COF
16767  *  0b0..Don't clear the OFIFO.
16768  *  0b1..Clear the OFIFO.
16769  */
16770 #define CAAM_CCWR_COF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK)
16771 
16772 #define CAAM_CCWR_CIF_MASK                       (0x80000000U)
16773 #define CAAM_CCWR_CIF_SHIFT                      (31U)
16774 /*! CIF
16775  *  0b0..Don't clear the IFIFO.
16776  *  0b1..Clear the IFIFO.
16777  */
16778 #define CAAM_CCWR_CIF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK)
16779 /*! @} */
16780 
16781 /* The count of CAAM_CCWR */
16782 #define CAAM_CCWR_COUNT                          (1U)
16783 
16784 /*! @name CCSTA_MS - CCB 0 Status and Error Register, most-significant half */
16785 /*! @{ */
16786 
16787 #define CAAM_CCSTA_MS_ERRID1_MASK                (0xFU)
16788 #define CAAM_CCSTA_MS_ERRID1_SHIFT               (0U)
16789 /*! ERRID1
16790  *  0b0001..Mode Error
16791  *  0b0010..Data Size Error, including PKHA N Memory Size Error
16792  *  0b0011..Key Size Error, including PKHA E Memory Size Error
16793  *  0b0100..PKHA A Memory Size Error
16794  *  0b0101..PKHA B Memory Size Error
16795  *  0b0110..Data Arrived out of Sequence Error
16796  *  0b0111..PKHA Divide by Zero Error
16797  *  0b1000..PKHA Modulus Even Error
16798  *  0b1001..DES Key Parity Error
16799  *  0b1010..ICV Check Failed
16800  *  0b1011..Internal Hardware Failure
16801  *  0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and
16802  *          AAD provided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
16803  *  0b1101..Class 1 CHA is not reset
16804  *  0b1110..Invalid CHA combination was selected
16805  *  0b1111..Invalid CHA Selected
16806  */
16807 #define CAAM_CCSTA_MS_ERRID1(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK)
16808 
16809 #define CAAM_CCSTA_MS_CL1_MASK                   (0xF000U)
16810 #define CAAM_CCSTA_MS_CL1_SHIFT                  (12U)
16811 /*! CL1
16812  *  0b0001..AES
16813  *  0b0010..DES
16814  *  0b0101..RNG
16815  *  0b1000..Public Key
16816  */
16817 #define CAAM_CCSTA_MS_CL1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK)
16818 
16819 #define CAAM_CCSTA_MS_ERRID2_MASK                (0xF0000U)
16820 #define CAAM_CCSTA_MS_ERRID2_SHIFT               (16U)
16821 /*! ERRID2
16822  *  0b0001..Mode Error
16823  *  0b0010..Data Size Error
16824  *  0b0011..Key Size Error
16825  *  0b0110..Data Arrived out of Sequence Error
16826  *  0b1010..ICV Check Failed
16827  *  0b1011..Internal Hardware Failure
16828  *  0b1110..Invalid CHA combination was selected.
16829  *  0b1111..Invalid CHA Selected
16830  */
16831 #define CAAM_CCSTA_MS_ERRID2(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK)
16832 
16833 #define CAAM_CCSTA_MS_CL2_MASK                   (0xF0000000U)
16834 #define CAAM_CCSTA_MS_CL2_SHIFT                  (28U)
16835 /*! CL2
16836  *  0b0100..MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and SHA-512/224, SHA-512/256
16837  *  0b1001..CRC
16838  */
16839 #define CAAM_CCSTA_MS_CL2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK)
16840 /*! @} */
16841 
16842 /* The count of CAAM_CCSTA_MS */
16843 #define CAAM_CCSTA_MS_COUNT                      (1U)
16844 
16845 /*! @name CCSTA_LS - CCB 0 Status and Error Register, least-significant half */
16846 /*! @{ */
16847 
16848 #define CAAM_CCSTA_LS_AB_MASK                    (0x2U)
16849 #define CAAM_CCSTA_LS_AB_SHIFT                   (1U)
16850 /*! AB
16851  *  0b0..AESA Idle
16852  *  0b1..AESA Busy
16853  */
16854 #define CAAM_CCSTA_LS_AB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK)
16855 
16856 #define CAAM_CCSTA_LS_DB_MASK                    (0x4U)
16857 #define CAAM_CCSTA_LS_DB_SHIFT                   (2U)
16858 /*! DB
16859  *  0b0..DESA Idle
16860  *  0b1..DESA Busy
16861  */
16862 #define CAAM_CCSTA_LS_DB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK)
16863 
16864 #define CAAM_CCSTA_LS_PB_MASK                    (0x40U)
16865 #define CAAM_CCSTA_LS_PB_SHIFT                   (6U)
16866 /*! PB
16867  *  0b0..PKHA Idle
16868  *  0b1..PKHA Busy
16869  */
16870 #define CAAM_CCSTA_LS_PB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK)
16871 
16872 #define CAAM_CCSTA_LS_MB_MASK                    (0x80U)
16873 #define CAAM_CCSTA_LS_MB_SHIFT                   (7U)
16874 /*! MB
16875  *  0b0..MDHA Idle
16876  *  0b1..MDHA Busy
16877  */
16878 #define CAAM_CCSTA_LS_MB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK)
16879 
16880 #define CAAM_CCSTA_LS_CB_MASK                    (0x100U)
16881 #define CAAM_CCSTA_LS_CB_SHIFT                   (8U)
16882 /*! CB
16883  *  0b0..CRCA Idle
16884  *  0b1..CRCA Busy
16885  */
16886 #define CAAM_CCSTA_LS_CB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK)
16887 
16888 #define CAAM_CCSTA_LS_RNB_MASK                   (0x200U)
16889 #define CAAM_CCSTA_LS_RNB_SHIFT                  (9U)
16890 /*! RNB
16891  *  0b0..RNG Idle
16892  *  0b1..RNG Busy
16893  */
16894 #define CAAM_CCSTA_LS_RNB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK)
16895 
16896 #define CAAM_CCSTA_LS_PDI_MASK                   (0x10000U)
16897 #define CAAM_CCSTA_LS_PDI_SHIFT                  (16U)
16898 /*! PDI
16899  *  0b0..Not Done
16900  *  0b1..Done Interrupt
16901  */
16902 #define CAAM_CCSTA_LS_PDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK)
16903 
16904 #define CAAM_CCSTA_LS_SDI_MASK                   (0x20000U)
16905 #define CAAM_CCSTA_LS_SDI_SHIFT                  (17U)
16906 /*! SDI
16907  *  0b0..Not Done
16908  *  0b1..Done Interrupt
16909  */
16910 #define CAAM_CCSTA_LS_SDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK)
16911 
16912 #define CAAM_CCSTA_LS_PEI_MASK                   (0x100000U)
16913 #define CAAM_CCSTA_LS_PEI_SHIFT                  (20U)
16914 /*! PEI
16915  *  0b0..No Error
16916  *  0b1..Error Interrupt
16917  */
16918 #define CAAM_CCSTA_LS_PEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK)
16919 
16920 #define CAAM_CCSTA_LS_SEI_MASK                   (0x200000U)
16921 #define CAAM_CCSTA_LS_SEI_SHIFT                  (21U)
16922 /*! SEI
16923  *  0b0..No Error
16924  *  0b1..Error Interrupt
16925  */
16926 #define CAAM_CCSTA_LS_SEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK)
16927 
16928 #define CAAM_CCSTA_LS_PRM_MASK                   (0x10000000U)
16929 #define CAAM_CCSTA_LS_PRM_SHIFT                  (28U)
16930 /*! PRM
16931  *  0b0..The given number is NOT prime.
16932  *  0b1..The given number is probably prime.
16933  */
16934 #define CAAM_CCSTA_LS_PRM(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK)
16935 
16936 #define CAAM_CCSTA_LS_GCD_MASK                   (0x20000000U)
16937 #define CAAM_CCSTA_LS_GCD_SHIFT                  (29U)
16938 /*! GCD
16939  *  0b0..The greatest common divisor of two numbers is NOT one.
16940  *  0b1..The greatest common divisor of two numbers is one.
16941  */
16942 #define CAAM_CCSTA_LS_GCD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK)
16943 
16944 #define CAAM_CCSTA_LS_PIZ_MASK                   (0x40000000U)
16945 #define CAAM_CCSTA_LS_PIZ_SHIFT                  (30U)
16946 /*! PIZ
16947  *  0b0..The result of a Public Key operation is not zero.
16948  *  0b1..The result of a Public Key operation is zero.
16949  */
16950 #define CAAM_CCSTA_LS_PIZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK)
16951 /*! @} */
16952 
16953 /* The count of CAAM_CCSTA_LS */
16954 #define CAAM_CCSTA_LS_COUNT                      (1U)
16955 
16956 /*! @name CC1AADSZR - CCB 0 Class 1 AAD Size Register */
16957 /*! @{ */
16958 
16959 #define CAAM_CC1AADSZR_AASZ_MASK                 (0xFU)
16960 #define CAAM_CC1AADSZR_AASZ_SHIFT                (0U)
16961 #define CAAM_CC1AADSZR_AASZ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK)
16962 /*! @} */
16963 
16964 /* The count of CAAM_CC1AADSZR */
16965 #define CAAM_CC1AADSZR_COUNT                     (1U)
16966 
16967 /*! @name CC1IVSZR - CCB 0 Class 1 IV Size Register */
16968 /*! @{ */
16969 
16970 #define CAAM_CC1IVSZR_IVSZ_MASK                  (0xFU)
16971 #define CAAM_CC1IVSZR_IVSZ_SHIFT                 (0U)
16972 #define CAAM_CC1IVSZR_IVSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK)
16973 /*! @} */
16974 
16975 /* The count of CAAM_CC1IVSZR */
16976 #define CAAM_CC1IVSZR_COUNT                      (1U)
16977 
16978 /*! @name CPKASZR - PKHA A Size Register */
16979 /*! @{ */
16980 
16981 #define CAAM_CPKASZR_PKASZ_MASK                  (0x3FFU)
16982 #define CAAM_CPKASZR_PKASZ_SHIFT                 (0U)
16983 #define CAAM_CPKASZR_PKASZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK)
16984 /*! @} */
16985 
16986 /* The count of CAAM_CPKASZR */
16987 #define CAAM_CPKASZR_COUNT                       (1U)
16988 
16989 /*! @name CPKBSZR - PKHA B Size Register */
16990 /*! @{ */
16991 
16992 #define CAAM_CPKBSZR_PKBSZ_MASK                  (0x3FFU)
16993 #define CAAM_CPKBSZR_PKBSZ_SHIFT                 (0U)
16994 #define CAAM_CPKBSZR_PKBSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK)
16995 /*! @} */
16996 
16997 /* The count of CAAM_CPKBSZR */
16998 #define CAAM_CPKBSZR_COUNT                       (1U)
16999 
17000 /*! @name CPKNSZR - PKHA N Size Register */
17001 /*! @{ */
17002 
17003 #define CAAM_CPKNSZR_PKNSZ_MASK                  (0x3FFU)
17004 #define CAAM_CPKNSZR_PKNSZ_SHIFT                 (0U)
17005 #define CAAM_CPKNSZR_PKNSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK)
17006 /*! @} */
17007 
17008 /* The count of CAAM_CPKNSZR */
17009 #define CAAM_CPKNSZR_COUNT                       (1U)
17010 
17011 /*! @name CPKESZR - PKHA E Size Register */
17012 /*! @{ */
17013 
17014 #define CAAM_CPKESZR_PKESZ_MASK                  (0x3FFU)
17015 #define CAAM_CPKESZR_PKESZ_SHIFT                 (0U)
17016 #define CAAM_CPKESZR_PKESZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK)
17017 /*! @} */
17018 
17019 /* The count of CAAM_CPKESZR */
17020 #define CAAM_CPKESZR_COUNT                       (1U)
17021 
17022 /*! @name CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 */
17023 /*! @{ */
17024 
17025 #define CAAM_CC1CTXR_C1CTX_MASK                  (0xFFFFFFFFU)
17026 #define CAAM_CC1CTXR_C1CTX_SHIFT                 (0U)
17027 #define CAAM_CC1CTXR_C1CTX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK)
17028 /*! @} */
17029 
17030 /* The count of CAAM_CC1CTXR */
17031 #define CAAM_CC1CTXR_COUNT                       (1U)
17032 
17033 /* The count of CAAM_CC1CTXR */
17034 #define CAAM_CC1CTXR_COUNT2                      (16U)
17035 
17036 /*! @name CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 */
17037 /*! @{ */
17038 
17039 #define CAAM_CC1KR_C1KEY_MASK                    (0xFFFFFFFFU)
17040 #define CAAM_CC1KR_C1KEY_SHIFT                   (0U)
17041 #define CAAM_CC1KR_C1KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK)
17042 /*! @} */
17043 
17044 /* The count of CAAM_CC1KR */
17045 #define CAAM_CC1KR_COUNT                         (1U)
17046 
17047 /* The count of CAAM_CC1KR */
17048 #define CAAM_CC1KR_COUNT2                        (8U)
17049 
17050 /*! @name CC2MR - CCB 0 Class 2 Mode Register */
17051 /*! @{ */
17052 
17053 #define CAAM_CC2MR_AP_MASK                       (0x1U)
17054 #define CAAM_CC2MR_AP_SHIFT                      (0U)
17055 /*! AP
17056  *  0b0..Authenticate
17057  *  0b1..Protect
17058  */
17059 #define CAAM_CC2MR_AP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK)
17060 
17061 #define CAAM_CC2MR_ICV_MASK                      (0x2U)
17062 #define CAAM_CC2MR_ICV_SHIFT                     (1U)
17063 /*! ICV
17064  *  0b0..Don't compare the calculated ICV against a received ICV.
17065  *  0b1..Compare the calculated ICV against a received ICV.
17066  */
17067 #define CAAM_CC2MR_ICV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK)
17068 
17069 #define CAAM_CC2MR_AS_MASK                       (0xCU)
17070 #define CAAM_CC2MR_AS_SHIFT                      (2U)
17071 /*! AS
17072  *  0b00..Update.
17073  *  0b01..Initialize.
17074  *  0b10..Finalize.
17075  *  0b11..Initialize/Finalize.
17076  */
17077 #define CAAM_CC2MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK)
17078 
17079 #define CAAM_CC2MR_AAI_MASK                      (0x1FF0U)
17080 #define CAAM_CC2MR_AAI_SHIFT                     (4U)
17081 #define CAAM_CC2MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK)
17082 
17083 #define CAAM_CC2MR_ALG_MASK                      (0xFF0000U)
17084 #define CAAM_CC2MR_ALG_SHIFT                     (16U)
17085 /*! ALG
17086  *  0b01000000..MD5
17087  *  0b01000001..SHA-1
17088  *  0b01000010..SHA-224
17089  *  0b01000011..SHA-256
17090  *  0b01000100..SHA-384
17091  *  0b01000101..SHA-512
17092  *  0b01000110..SHA-512/224
17093  *  0b01000111..SHA-512/256
17094  *  0b10010000..CRC
17095  */
17096 #define CAAM_CC2MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK)
17097 /*! @} */
17098 
17099 /* The count of CAAM_CC2MR */
17100 #define CAAM_CC2MR_COUNT                         (1U)
17101 
17102 /*! @name CC2KSR - CCB 0 Class 2 Key Size Register */
17103 /*! @{ */
17104 
17105 #define CAAM_CC2KSR_C2KS_MASK                    (0xFFU)
17106 #define CAAM_CC2KSR_C2KS_SHIFT                   (0U)
17107 #define CAAM_CC2KSR_C2KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK)
17108 /*! @} */
17109 
17110 /* The count of CAAM_CC2KSR */
17111 #define CAAM_CC2KSR_COUNT                        (1U)
17112 
17113 /*! @name CC2DSR - CCB 0 Class 2 Data Size Register */
17114 /*! @{ */
17115 
17116 #define CAAM_CC2DSR_C2DS_MASK                    (0xFFFFFFFFU)
17117 #define CAAM_CC2DSR_C2DS_SHIFT                   (0U)
17118 #define CAAM_CC2DSR_C2DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK)
17119 
17120 #define CAAM_CC2DSR_C2CY_MASK                    (0x100000000U)
17121 #define CAAM_CC2DSR_C2CY_SHIFT                   (32U)
17122 /*! C2CY
17123  *  0b0..A write to the Class 2 Data Size Register did not cause a carry.
17124  *  0b1..A write to the Class 2 Data Size Register caused a carry.
17125  */
17126 #define CAAM_CC2DSR_C2CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK)
17127 
17128 #define CAAM_CC2DSR_NUMBITS_MASK                 (0xE000000000000000U)
17129 #define CAAM_CC2DSR_NUMBITS_SHIFT                (61U)
17130 #define CAAM_CC2DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK)
17131 /*! @} */
17132 
17133 /* The count of CAAM_CC2DSR */
17134 #define CAAM_CC2DSR_COUNT                        (1U)
17135 
17136 /*! @name CC2ICVSZR - CCB 0 Class 2 ICV Size Register */
17137 /*! @{ */
17138 
17139 #define CAAM_CC2ICVSZR_ICVSZ_MASK                (0xFU)
17140 #define CAAM_CC2ICVSZR_ICVSZ_SHIFT               (0U)
17141 #define CAAM_CC2ICVSZR_ICVSZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK)
17142 /*! @} */
17143 
17144 /* The count of CAAM_CC2ICVSZR */
17145 #define CAAM_CC2ICVSZR_COUNT                     (1U)
17146 
17147 /*! @name CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 */
17148 /*! @{ */
17149 
17150 #define CAAM_CC2CTXR_C2CTXR_MASK                 (0xFFFFFFFFU)
17151 #define CAAM_CC2CTXR_C2CTXR_SHIFT                (0U)
17152 #define CAAM_CC2CTXR_C2CTXR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK)
17153 /*! @} */
17154 
17155 /* The count of CAAM_CC2CTXR */
17156 #define CAAM_CC2CTXR_COUNT                       (1U)
17157 
17158 /* The count of CAAM_CC2CTXR */
17159 #define CAAM_CC2CTXR_COUNT2                      (18U)
17160 
17161 /*! @name CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 */
17162 /*! @{ */
17163 
17164 #define CAAM_CC2KEYR_C2KEY_MASK                  (0xFFFFFFFFU)
17165 #define CAAM_CC2KEYR_C2KEY_SHIFT                 (0U)
17166 #define CAAM_CC2KEYR_C2KEY(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK)
17167 /*! @} */
17168 
17169 /* The count of CAAM_CC2KEYR */
17170 #define CAAM_CC2KEYR_COUNT                       (1U)
17171 
17172 /* The count of CAAM_CC2KEYR */
17173 #define CAAM_CC2KEYR_COUNT2                      (32U)
17174 
17175 /*! @name CFIFOSTA - CCB 0 FIFO Status Register */
17176 /*! @{ */
17177 
17178 #define CAAM_CFIFOSTA_DECOOQHEAD_MASK            (0xFFU)
17179 #define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT           (0U)
17180 #define CAAM_CFIFOSTA_DECOOQHEAD(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK)
17181 
17182 #define CAAM_CFIFOSTA_DMAOQHEAD_MASK             (0xFF00U)
17183 #define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT            (8U)
17184 #define CAAM_CFIFOSTA_DMAOQHEAD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK)
17185 
17186 #define CAAM_CFIFOSTA_C2IQHEAD_MASK              (0xFF0000U)
17187 #define CAAM_CFIFOSTA_C2IQHEAD_SHIFT             (16U)
17188 #define CAAM_CFIFOSTA_C2IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK)
17189 
17190 #define CAAM_CFIFOSTA_C1IQHEAD_MASK              (0xFF000000U)
17191 #define CAAM_CFIFOSTA_C1IQHEAD_SHIFT             (24U)
17192 #define CAAM_CFIFOSTA_C1IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK)
17193 /*! @} */
17194 
17195 /* The count of CAAM_CFIFOSTA */
17196 #define CAAM_CFIFOSTA_COUNT                      (1U)
17197 
17198 /*! @name CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b */
17199 /*! @{ */
17200 
17201 #define CAAM_CNFIFO_DL_MASK                      (0xFFFU)
17202 #define CAAM_CNFIFO_DL_SHIFT                     (0U)
17203 #define CAAM_CNFIFO_DL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK)
17204 
17205 #define CAAM_CNFIFO_AST_MASK                     (0x4000U)
17206 #define CAAM_CNFIFO_AST_SHIFT                    (14U)
17207 #define CAAM_CNFIFO_AST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK)
17208 
17209 #define CAAM_CNFIFO_OC_MASK                      (0x8000U)
17210 #define CAAM_CNFIFO_OC_SHIFT                     (15U)
17211 /*! OC
17212  *  0b0..Allow the final word to be popped from the Output Data FIFO.
17213  *  0b1..Don't pop the final word from the Output Data FIFO.
17214  */
17215 #define CAAM_CNFIFO_OC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK)
17216 
17217 #define CAAM_CNFIFO_PTYPE_MASK                   (0x70000U)
17218 #define CAAM_CNFIFO_PTYPE_SHIFT                  (16U)
17219 #define CAAM_CNFIFO_PTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK)
17220 
17221 #define CAAM_CNFIFO_BND_MASK                     (0x80000U)
17222 #define CAAM_CNFIFO_BND_SHIFT                    (19U)
17223 /*! BND
17224  *  0b0..Don't pad.
17225  *  0b1..Pad to the next 16-byte boundary.
17226  */
17227 #define CAAM_CNFIFO_BND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK)
17228 
17229 #define CAAM_CNFIFO_DTYPE_MASK                   (0xF00000U)
17230 #define CAAM_CNFIFO_DTYPE_SHIFT                  (20U)
17231 #define CAAM_CNFIFO_DTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK)
17232 
17233 #define CAAM_CNFIFO_STYPE_MASK                   (0x3000000U)
17234 #define CAAM_CNFIFO_STYPE_SHIFT                  (24U)
17235 #define CAAM_CNFIFO_STYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK)
17236 
17237 #define CAAM_CNFIFO_FC1_MASK                     (0x4000000U)
17238 #define CAAM_CNFIFO_FC1_SHIFT                    (26U)
17239 /*! FC1
17240  *  0b0..Don't flush Class 1 data.
17241  *  0b1..Flush Class 1 data.
17242  */
17243 #define CAAM_CNFIFO_FC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK)
17244 
17245 #define CAAM_CNFIFO_FC2_MASK                     (0x8000000U)
17246 #define CAAM_CNFIFO_FC2_SHIFT                    (27U)
17247 /*! FC2
17248  *  0b0..Don't flush Class 2 data.
17249  *  0b1..Flush Class 2 data.
17250  */
17251 #define CAAM_CNFIFO_FC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK)
17252 
17253 #define CAAM_CNFIFO_LC1_MASK                     (0x10000000U)
17254 #define CAAM_CNFIFO_LC1_SHIFT                    (28U)
17255 /*! LC1
17256  *  0b0..This is not the last Class 1 data.
17257  *  0b1..This is the last Class 1 data.
17258  */
17259 #define CAAM_CNFIFO_LC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK)
17260 
17261 #define CAAM_CNFIFO_LC2_MASK                     (0x20000000U)
17262 #define CAAM_CNFIFO_LC2_SHIFT                    (29U)
17263 /*! LC2
17264  *  0b0..This is not the last Class 2 data.
17265  *  0b1..This is the last Class 2 data.
17266  */
17267 #define CAAM_CNFIFO_LC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK)
17268 
17269 #define CAAM_CNFIFO_DEST_MASK                    (0xC0000000U)
17270 #define CAAM_CNFIFO_DEST_SHIFT                   (30U)
17271 /*! DEST
17272  *  0b00..DECO Alignment Block. If DTYPE == Eh, data sent to the DECO Alignment Block is dropped. This is used to
17273  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17274  *        the DECO Alignment Block destination.
17275  *  0b01..Class 1.
17276  *  0b10..Class 2.
17277  *  0b11..Both Class 1 and Class 2.
17278  */
17279 #define CAAM_CNFIFO_DEST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK)
17280 /*! @} */
17281 
17282 /* The count of CAAM_CNFIFO */
17283 #define CAAM_CNFIFO_COUNT                        (1U)
17284 
17285 /*! @name CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b */
17286 /*! @{ */
17287 
17288 #define CAAM_CNFIFO_2_PL_MASK                    (0x7FU)
17289 #define CAAM_CNFIFO_2_PL_SHIFT                   (0U)
17290 #define CAAM_CNFIFO_2_PL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK)
17291 
17292 #define CAAM_CNFIFO_2_PS_MASK                    (0x400U)
17293 #define CAAM_CNFIFO_2_PS_SHIFT                   (10U)
17294 /*! PS
17295  *  0b0..C2 CHA snoops pad data from padding block.
17296  *  0b1..C2 CHA snoops pad data from OFIFO.
17297  */
17298 #define CAAM_CNFIFO_2_PS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK)
17299 
17300 #define CAAM_CNFIFO_2_BM_MASK                    (0x800U)
17301 #define CAAM_CNFIFO_2_BM_SHIFT                   (11U)
17302 /*! BM
17303  *  0b0..When padding, pad to power-of-2 boundary.
17304  *  0b1..When padding, pad to power-of-2 boundary minus 1 byte.
17305  */
17306 #define CAAM_CNFIFO_2_BM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK)
17307 
17308 #define CAAM_CNFIFO_2_PR_MASK                    (0x8000U)
17309 #define CAAM_CNFIFO_2_PR_SHIFT                   (15U)
17310 /*! PR
17311  *  0b0..No prediction resistance.
17312  *  0b1..Prediction resistance.
17313  */
17314 #define CAAM_CNFIFO_2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK)
17315 
17316 #define CAAM_CNFIFO_2_PTYPE_MASK                 (0x70000U)
17317 #define CAAM_CNFIFO_2_PTYPE_SHIFT                (16U)
17318 /*! PTYPE
17319  *  0b000..All Zero.
17320  *  0b001..Random with nonzero bytes.
17321  *  0b010..Incremented (starting with 01h), followed by a byte containing the value N-1, i.e., if N==1, a single byte is output with value 0h.
17322  *  0b011..Random.
17323  *  0b100..All Zero with last byte containing the number of 0 bytes, i.e., if N==1, a single byte is output with value 0h.
17324  *  0b101..Random with nonzero bytes with last byte 0.
17325  *  0b110..N bytes of padding all containing the value N-1.
17326  *  0b111..Random with nonzero bytes, with the last byte containing the value N-1.
17327  */
17328 #define CAAM_CNFIFO_2_PTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK)
17329 
17330 #define CAAM_CNFIFO_2_BND_MASK                   (0x80000U)
17331 #define CAAM_CNFIFO_2_BND_SHIFT                  (19U)
17332 /*! BND
17333  *  0b0..Don't add boundary padding.
17334  *  0b1..Add boundary padding.
17335  */
17336 #define CAAM_CNFIFO_2_BND(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK)
17337 
17338 #define CAAM_CNFIFO_2_DTYPE_MASK                 (0xF00000U)
17339 #define CAAM_CNFIFO_2_DTYPE_SHIFT                (20U)
17340 #define CAAM_CNFIFO_2_DTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK)
17341 
17342 #define CAAM_CNFIFO_2_STYPE_MASK                 (0x3000000U)
17343 #define CAAM_CNFIFO_2_STYPE_SHIFT                (24U)
17344 #define CAAM_CNFIFO_2_STYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK)
17345 
17346 #define CAAM_CNFIFO_2_FC1_MASK                   (0x4000000U)
17347 #define CAAM_CNFIFO_2_FC1_SHIFT                  (26U)
17348 /*! FC1
17349  *  0b0..Don't flush the Class 1 data.
17350  *  0b1..Flush the Class 1 data.
17351  */
17352 #define CAAM_CNFIFO_2_FC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK)
17353 
17354 #define CAAM_CNFIFO_2_FC2_MASK                   (0x8000000U)
17355 #define CAAM_CNFIFO_2_FC2_SHIFT                  (27U)
17356 /*! FC2
17357  *  0b0..Don't flush the Class 2 data.
17358  *  0b1..Flush the Class 2 data.
17359  */
17360 #define CAAM_CNFIFO_2_FC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK)
17361 
17362 #define CAAM_CNFIFO_2_LC1_MASK                   (0x10000000U)
17363 #define CAAM_CNFIFO_2_LC1_SHIFT                  (28U)
17364 /*! LC1
17365  *  0b0..This is not the last Class 1 data.
17366  *  0b1..This is the last Class 1 data.
17367  */
17368 #define CAAM_CNFIFO_2_LC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK)
17369 
17370 #define CAAM_CNFIFO_2_LC2_MASK                   (0x20000000U)
17371 #define CAAM_CNFIFO_2_LC2_SHIFT                  (29U)
17372 /*! LC2
17373  *  0b0..This is not the last Class 2 data.
17374  *  0b1..This is the last Class 2 data.
17375  */
17376 #define CAAM_CNFIFO_2_LC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK)
17377 
17378 #define CAAM_CNFIFO_2_DEST_MASK                  (0xC0000000U)
17379 #define CAAM_CNFIFO_2_DEST_SHIFT                 (30U)
17380 /*! DEST
17381  *  0b00..DECO Alignment Block. If DTYPE is Eh, data sent to the DECO Alignment Block is dropped. This is used to
17382  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17383  *        the DECO Alignment Block destination.
17384  *  0b01..Class 1.
17385  *  0b10..Class 2.
17386  *  0b11..Both Class 1 and Class 2.
17387  */
17388 #define CAAM_CNFIFO_2_DEST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK)
17389 /*! @} */
17390 
17391 /* The count of CAAM_CNFIFO_2 */
17392 #define CAAM_CNFIFO_2_COUNT                      (1U)
17393 
17394 /*! @name CIFIFO - CCB 0 Input Data FIFO */
17395 /*! @{ */
17396 
17397 #define CAAM_CIFIFO_IFIFO_MASK                   (0xFFFFFFFFU)
17398 #define CAAM_CIFIFO_IFIFO_SHIFT                  (0U)
17399 #define CAAM_CIFIFO_IFIFO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK)
17400 /*! @} */
17401 
17402 /* The count of CAAM_CIFIFO */
17403 #define CAAM_CIFIFO_COUNT                        (1U)
17404 
17405 /*! @name COFIFO - CCB 0 Output Data FIFO */
17406 /*! @{ */
17407 
17408 #define CAAM_COFIFO_OFIFO_MASK                   (0xFFFFFFFFFFFFFFFFU)
17409 #define CAAM_COFIFO_OFIFO_SHIFT                  (0U)
17410 #define CAAM_COFIFO_OFIFO(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK)
17411 /*! @} */
17412 
17413 /* The count of CAAM_COFIFO */
17414 #define CAAM_COFIFO_COUNT                        (1U)
17415 
17416 /*! @name DJQCR_MS - DECO0 Job Queue Control Register, most-significant half */
17417 /*! @{ */
17418 
17419 #define CAAM_DJQCR_MS_ID_MASK                    (0x7U)
17420 #define CAAM_DJQCR_MS_ID_SHIFT                   (0U)
17421 #define CAAM_DJQCR_MS_ID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK)
17422 
17423 #define CAAM_DJQCR_MS_SRC_MASK                   (0x700U)
17424 #define CAAM_DJQCR_MS_SRC_SHIFT                  (8U)
17425 /*! SRC
17426  *  0b000..Job Ring 0
17427  *  0b001..Job Ring 1
17428  *  0b010..Job Ring 2
17429  *  0b011..Job Ring 3
17430  *  0b100..RTIC
17431  *  0b101..Reserved
17432  *  0b110..Reserved
17433  *  0b111..Reserved
17434  */
17435 #define CAAM_DJQCR_MS_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK)
17436 
17437 #define CAAM_DJQCR_MS_AMTD_MASK                  (0x8000U)
17438 #define CAAM_DJQCR_MS_AMTD_SHIFT                 (15U)
17439 /*! AMTD
17440  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17441  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17442  */
17443 #define CAAM_DJQCR_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK)
17444 
17445 #define CAAM_DJQCR_MS_SOB_MASK                   (0x10000U)
17446 #define CAAM_DJQCR_MS_SOB_SHIFT                  (16U)
17447 /*! SOB
17448  *  0b0..Shared Descriptor has NOT been loaded.
17449  *  0b1..Shared Descriptor HAS been loaded.
17450  */
17451 #define CAAM_DJQCR_MS_SOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK)
17452 
17453 #define CAAM_DJQCR_MS_DWS_MASK                   (0x80000U)
17454 #define CAAM_DJQCR_MS_DWS_SHIFT                  (19U)
17455 /*! DWS
17456  *  0b0..Double Word Swap is NOT set.
17457  *  0b1..Double Word Swap is set.
17458  */
17459 #define CAAM_DJQCR_MS_DWS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK)
17460 
17461 #define CAAM_DJQCR_MS_SHR_FROM_MASK              (0x7000000U)
17462 #define CAAM_DJQCR_MS_SHR_FROM_SHIFT             (24U)
17463 #define CAAM_DJQCR_MS_SHR_FROM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK)
17464 
17465 #define CAAM_DJQCR_MS_ILE_MASK                   (0x8000000U)
17466 #define CAAM_DJQCR_MS_ILE_SHIFT                  (27U)
17467 /*! ILE
17468  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17469  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17470  */
17471 #define CAAM_DJQCR_MS_ILE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK)
17472 
17473 #define CAAM_DJQCR_MS_FOUR_MASK                  (0x10000000U)
17474 #define CAAM_DJQCR_MS_FOUR_SHIFT                 (28U)
17475 /*! FOUR
17476  *  0b0..DECO has not been given at least four words of the descriptor.
17477  *  0b1..DECO has been given at least four words of the descriptor.
17478  */
17479 #define CAAM_DJQCR_MS_FOUR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK)
17480 
17481 #define CAAM_DJQCR_MS_WHL_MASK                   (0x20000000U)
17482 #define CAAM_DJQCR_MS_WHL_SHIFT                  (29U)
17483 /*! WHL
17484  *  0b0..DECO has not been given the whole descriptor.
17485  *  0b1..DECO has been given the whole descriptor.
17486  */
17487 #define CAAM_DJQCR_MS_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK)
17488 
17489 #define CAAM_DJQCR_MS_SING_MASK                  (0x40000000U)
17490 #define CAAM_DJQCR_MS_SING_SHIFT                 (30U)
17491 /*! SING
17492  *  0b0..Do not tell DECO to execute the descriptor in single-step mode.
17493  *  0b1..Tell DECO to execute the descriptor in single-step mode.
17494  */
17495 #define CAAM_DJQCR_MS_SING(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK)
17496 
17497 #define CAAM_DJQCR_MS_STEP_MASK                  (0x80000000U)
17498 #define CAAM_DJQCR_MS_STEP_SHIFT                 (31U)
17499 /*! STEP
17500  *  0b0..DECO has not been told to execute the next command in the descriptor.
17501  *  0b1..DECO has been told to execute the next command in the descriptor.
17502  */
17503 #define CAAM_DJQCR_MS_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK)
17504 /*! @} */
17505 
17506 /* The count of CAAM_DJQCR_MS */
17507 #define CAAM_DJQCR_MS_COUNT                      (1U)
17508 
17509 /*! @name DJQCR_LS - DECO0 Job Queue Control Register, least-significant half */
17510 /*! @{ */
17511 
17512 #define CAAM_DJQCR_LS_CMD_MASK                   (0xFFFFFFFFU)
17513 #define CAAM_DJQCR_LS_CMD_SHIFT                  (0U)
17514 #define CAAM_DJQCR_LS_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK)
17515 /*! @} */
17516 
17517 /* The count of CAAM_DJQCR_LS */
17518 #define CAAM_DJQCR_LS_COUNT                      (1U)
17519 
17520 /*! @name DDAR - DECO0 Descriptor Address Register */
17521 /*! @{ */
17522 
17523 #define CAAM_DDAR_DPTR_MASK                      (0xFFFFFFFFFU)
17524 #define CAAM_DDAR_DPTR_SHIFT                     (0U)
17525 #define CAAM_DDAR_DPTR(x)                        (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK)
17526 /*! @} */
17527 
17528 /* The count of CAAM_DDAR */
17529 #define CAAM_DDAR_COUNT                          (1U)
17530 
17531 /*! @name DOPSTA_MS - DECO0 Operation Status Register, most-significant half */
17532 /*! @{ */
17533 
17534 #define CAAM_DOPSTA_MS_STATUS_MASK               (0xFFU)
17535 #define CAAM_DOPSTA_MS_STATUS_SHIFT              (0U)
17536 #define CAAM_DOPSTA_MS_STATUS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK)
17537 
17538 #define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK        (0x7F00U)
17539 #define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT       (8U)
17540 #define CAAM_DOPSTA_MS_COMMAND_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK)
17541 
17542 #define CAAM_DOPSTA_MS_NLJ_MASK                  (0x8000000U)
17543 #define CAAM_DOPSTA_MS_NLJ_SHIFT                 (27U)
17544 /*! NLJ
17545  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17546  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17547  */
17548 #define CAAM_DOPSTA_MS_NLJ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK)
17549 
17550 #define CAAM_DOPSTA_MS_STATUS_TYPE_MASK          (0xF0000000U)
17551 #define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT         (28U)
17552 /*! STATUS_TYPE
17553  *  0b0000..no error
17554  *  0b0001..DMA error
17555  *  0b0010..CCB error
17556  *  0b0011..Jump Halt User Status
17557  *  0b0100..DECO error
17558  *  0b0101, 0b0110..Reserved
17559  *  0b0111..Jump Halt Condition Code
17560  */
17561 #define CAAM_DOPSTA_MS_STATUS_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK)
17562 /*! @} */
17563 
17564 /* The count of CAAM_DOPSTA_MS */
17565 #define CAAM_DOPSTA_MS_COUNT                     (1U)
17566 
17567 /*! @name DOPSTA_LS - DECO0 Operation Status Register, least-significant half */
17568 /*! @{ */
17569 
17570 #define CAAM_DOPSTA_LS_OUT_CT_MASK               (0xFFFFFFFFU)
17571 #define CAAM_DOPSTA_LS_OUT_CT_SHIFT              (0U)
17572 #define CAAM_DOPSTA_LS_OUT_CT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK)
17573 /*! @} */
17574 
17575 /* The count of CAAM_DOPSTA_LS */
17576 #define CAAM_DOPSTA_LS_COUNT                     (1U)
17577 
17578 /*! @name DPDIDSR - DECO0 Primary DID Status Register */
17579 /*! @{ */
17580 
17581 #define CAAM_DPDIDSR_PRIM_DID_MASK               (0xFU)
17582 #define CAAM_DPDIDSR_PRIM_DID_SHIFT              (0U)
17583 #define CAAM_DPDIDSR_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK)
17584 
17585 #define CAAM_DPDIDSR_PRIM_ICID_MASK              (0x3FF80000U)
17586 #define CAAM_DPDIDSR_PRIM_ICID_SHIFT             (19U)
17587 #define CAAM_DPDIDSR_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK)
17588 /*! @} */
17589 
17590 /* The count of CAAM_DPDIDSR */
17591 #define CAAM_DPDIDSR_COUNT                       (1U)
17592 
17593 /*! @name DODIDSR - DECO0 Output DID Status Register */
17594 /*! @{ */
17595 
17596 #define CAAM_DODIDSR_OUT_DID_MASK                (0xFU)
17597 #define CAAM_DODIDSR_OUT_DID_SHIFT               (0U)
17598 #define CAAM_DODIDSR_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK)
17599 
17600 #define CAAM_DODIDSR_OUT_ICID_MASK               (0x3FF80000U)
17601 #define CAAM_DODIDSR_OUT_ICID_SHIFT              (19U)
17602 #define CAAM_DODIDSR_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK)
17603 /*! @} */
17604 
17605 /* The count of CAAM_DODIDSR */
17606 #define CAAM_DODIDSR_COUNT                       (1U)
17607 
17608 /*! @name DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS */
17609 /*! @{ */
17610 
17611 #define CAAM_DMTH_MS_MATH_MS_MASK                (0xFFFFFFFFU)
17612 #define CAAM_DMTH_MS_MATH_MS_SHIFT               (0U)
17613 #define CAAM_DMTH_MS_MATH_MS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK)
17614 /*! @} */
17615 
17616 /* The count of CAAM_DMTH_MS */
17617 #define CAAM_DMTH_MS_COUNT                       (1U)
17618 
17619 /* The count of CAAM_DMTH_MS */
17620 #define CAAM_DMTH_MS_COUNT2                      (4U)
17621 
17622 /*! @name DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS */
17623 /*! @{ */
17624 
17625 #define CAAM_DMTH_LS_MATH_LS_MASK                (0xFFFFFFFFU)
17626 #define CAAM_DMTH_LS_MATH_LS_SHIFT               (0U)
17627 #define CAAM_DMTH_LS_MATH_LS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK)
17628 /*! @} */
17629 
17630 /* The count of CAAM_DMTH_LS */
17631 #define CAAM_DMTH_LS_COUNT                       (1U)
17632 
17633 /* The count of CAAM_DMTH_LS */
17634 #define CAAM_DMTH_LS_COUNT2                      (4U)
17635 
17636 /*! @name DGTR_0 - DECO0 Gather Table Register 0 Word 0 */
17637 /*! @{ */
17638 
17639 #define CAAM_DGTR_0_ADDRESS_POINTER_MASK         (0xFU)
17640 #define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT        (0U)
17641 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
17642  */
17643 #define CAAM_DGTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK)
17644 /*! @} */
17645 
17646 /* The count of CAAM_DGTR_0 */
17647 #define CAAM_DGTR_0_COUNT                        (1U)
17648 
17649 /* The count of CAAM_DGTR_0 */
17650 #define CAAM_DGTR_0_COUNT2                       (1U)
17651 
17652 /*! @name DGTR_1 - DECO0 Gather Table Register 0 Word 1 */
17653 /*! @{ */
17654 
17655 #define CAAM_DGTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17656 #define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT        (0U)
17657 #define CAAM_DGTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK)
17658 /*! @} */
17659 
17660 /* The count of CAAM_DGTR_1 */
17661 #define CAAM_DGTR_1_COUNT                        (1U)
17662 
17663 /* The count of CAAM_DGTR_1 */
17664 #define CAAM_DGTR_1_COUNT2                       (1U)
17665 
17666 /*! @name DGTR_2 - DECO0 Gather Table Register 0 Word 2 */
17667 /*! @{ */
17668 
17669 #define CAAM_DGTR_2_Length_MASK                  (0x3FFFFFFFU)
17670 #define CAAM_DGTR_2_Length_SHIFT                 (0U)
17671 #define CAAM_DGTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK)
17672 
17673 #define CAAM_DGTR_2_F_MASK                       (0x40000000U)
17674 #define CAAM_DGTR_2_F_SHIFT                      (30U)
17675 /*! F
17676  *  0b0..This is not the last entry of the SGT.
17677  *  0b1..This is the last entry of the SGT.
17678  */
17679 #define CAAM_DGTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK)
17680 
17681 #define CAAM_DGTR_2_E_MASK                       (0x80000000U)
17682 #define CAAM_DGTR_2_E_SHIFT                      (31U)
17683 /*! E
17684  *  0b0..Address Pointer points to a memory buffer.
17685  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17686  */
17687 #define CAAM_DGTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK)
17688 /*! @} */
17689 
17690 /* The count of CAAM_DGTR_2 */
17691 #define CAAM_DGTR_2_COUNT                        (1U)
17692 
17693 /* The count of CAAM_DGTR_2 */
17694 #define CAAM_DGTR_2_COUNT2                       (1U)
17695 
17696 /*! @name DGTR_3 - DECO0 Gather Table Register 0 Word 3 */
17697 /*! @{ */
17698 
17699 #define CAAM_DGTR_3_Offset_MASK                  (0x1FFFU)
17700 #define CAAM_DGTR_3_Offset_SHIFT                 (0U)
17701 #define CAAM_DGTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK)
17702 /*! @} */
17703 
17704 /* The count of CAAM_DGTR_3 */
17705 #define CAAM_DGTR_3_COUNT                        (1U)
17706 
17707 /* The count of CAAM_DGTR_3 */
17708 #define CAAM_DGTR_3_COUNT2                       (1U)
17709 
17710 /*! @name DSTR_0 - DECO0 Scatter Table Register 0 Word 0 */
17711 /*! @{ */
17712 
17713 #define CAAM_DSTR_0_ADDRESS_POINTER_MASK         (0xFU)
17714 #define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT        (0U)
17715 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
17716  */
17717 #define CAAM_DSTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK)
17718 /*! @} */
17719 
17720 /* The count of CAAM_DSTR_0 */
17721 #define CAAM_DSTR_0_COUNT                        (1U)
17722 
17723 /* The count of CAAM_DSTR_0 */
17724 #define CAAM_DSTR_0_COUNT2                       (1U)
17725 
17726 /*! @name DSTR_1 - DECO0 Scatter Table Register 0 Word 1 */
17727 /*! @{ */
17728 
17729 #define CAAM_DSTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17730 #define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT        (0U)
17731 #define CAAM_DSTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK)
17732 /*! @} */
17733 
17734 /* The count of CAAM_DSTR_1 */
17735 #define CAAM_DSTR_1_COUNT                        (1U)
17736 
17737 /* The count of CAAM_DSTR_1 */
17738 #define CAAM_DSTR_1_COUNT2                       (1U)
17739 
17740 /*! @name DSTR_2 - DECO0 Scatter Table Register 0 Word 2 */
17741 /*! @{ */
17742 
17743 #define CAAM_DSTR_2_Length_MASK                  (0x3FFFFFFFU)
17744 #define CAAM_DSTR_2_Length_SHIFT                 (0U)
17745 #define CAAM_DSTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK)
17746 
17747 #define CAAM_DSTR_2_F_MASK                       (0x40000000U)
17748 #define CAAM_DSTR_2_F_SHIFT                      (30U)
17749 /*! F
17750  *  0b0..This is not the last entry of the SGT.
17751  *  0b1..This is the last entry of the SGT.
17752  */
17753 #define CAAM_DSTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK)
17754 
17755 #define CAAM_DSTR_2_E_MASK                       (0x80000000U)
17756 #define CAAM_DSTR_2_E_SHIFT                      (31U)
17757 /*! E
17758  *  0b0..Address Pointer points to a memory buffer.
17759  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17760  */
17761 #define CAAM_DSTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK)
17762 /*! @} */
17763 
17764 /* The count of CAAM_DSTR_2 */
17765 #define CAAM_DSTR_2_COUNT                        (1U)
17766 
17767 /* The count of CAAM_DSTR_2 */
17768 #define CAAM_DSTR_2_COUNT2                       (1U)
17769 
17770 /*! @name DSTR_3 - DECO0 Scatter Table Register 0 Word 3 */
17771 /*! @{ */
17772 
17773 #define CAAM_DSTR_3_Offset_MASK                  (0x1FFFU)
17774 #define CAAM_DSTR_3_Offset_SHIFT                 (0U)
17775 #define CAAM_DSTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK)
17776 /*! @} */
17777 
17778 /* The count of CAAM_DSTR_3 */
17779 #define CAAM_DSTR_3_COUNT                        (1U)
17780 
17781 /* The count of CAAM_DSTR_3 */
17782 #define CAAM_DSTR_3_COUNT2                       (1U)
17783 
17784 /*! @name DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 */
17785 /*! @{ */
17786 
17787 #define CAAM_DDESB_DESBW_MASK                    (0xFFFFFFFFU)
17788 #define CAAM_DDESB_DESBW_SHIFT                   (0U)
17789 #define CAAM_DDESB_DESBW(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK)
17790 /*! @} */
17791 
17792 /* The count of CAAM_DDESB */
17793 #define CAAM_DDESB_COUNT                         (1U)
17794 
17795 /* The count of CAAM_DDESB */
17796 #define CAAM_DDESB_COUNT2                        (64U)
17797 
17798 /*! @name DDJR - DECO0 Debug Job Register */
17799 /*! @{ */
17800 
17801 #define CAAM_DDJR_ID_MASK                        (0x7U)
17802 #define CAAM_DDJR_ID_SHIFT                       (0U)
17803 #define CAAM_DDJR_ID(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK)
17804 
17805 #define CAAM_DDJR_SRC_MASK                       (0x700U)
17806 #define CAAM_DDJR_SRC_SHIFT                      (8U)
17807 /*! SRC
17808  *  0b000..Job Ring 0
17809  *  0b001..Job Ring 1
17810  *  0b010..Job Ring 2
17811  *  0b011..Job Ring 3
17812  *  0b100..RTIC
17813  *  0b101, 0b110, 0b111..Reserved
17814  */
17815 #define CAAM_DDJR_SRC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK)
17816 
17817 #define CAAM_DDJR_JDDS_MASK                      (0x4000U)
17818 #define CAAM_DDJR_JDDS_SHIFT                     (14U)
17819 /*! JDDS
17820  *  0b1..SEQ DID
17821  *  0b0..Non-SEQ DID
17822  */
17823 #define CAAM_DDJR_JDDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK)
17824 
17825 #define CAAM_DDJR_AMTD_MASK                      (0x8000U)
17826 #define CAAM_DDJR_AMTD_SHIFT                     (15U)
17827 /*! AMTD
17828  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17829  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17830  */
17831 #define CAAM_DDJR_AMTD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK)
17832 
17833 #define CAAM_DDJR_GSD_MASK                       (0x10000U)
17834 #define CAAM_DDJR_GSD_SHIFT                      (16U)
17835 /*! GSD
17836  *  0b0..Shared Descriptor was NOT obtained from another DECO.
17837  *  0b1..Shared Descriptor was obtained from another DECO.
17838  */
17839 #define CAAM_DDJR_GSD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK)
17840 
17841 #define CAAM_DDJR_DWS_MASK                       (0x80000U)
17842 #define CAAM_DDJR_DWS_SHIFT                      (19U)
17843 /*! DWS
17844  *  0b0..Double Word Swap is NOT set.
17845  *  0b1..Double Word Swap is set.
17846  */
17847 #define CAAM_DDJR_DWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK)
17848 
17849 #define CAAM_DDJR_SHR_FROM_MASK                  (0x7000000U)
17850 #define CAAM_DDJR_SHR_FROM_SHIFT                 (24U)
17851 #define CAAM_DDJR_SHR_FROM(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK)
17852 
17853 #define CAAM_DDJR_ILE_MASK                       (0x8000000U)
17854 #define CAAM_DDJR_ILE_SHIFT                      (27U)
17855 /*! ILE
17856  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17857  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17858  */
17859 #define CAAM_DDJR_ILE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK)
17860 
17861 #define CAAM_DDJR_FOUR_MASK                      (0x10000000U)
17862 #define CAAM_DDJR_FOUR_SHIFT                     (28U)
17863 /*! FOUR
17864  *  0b0..DECO has not been given at least four words of the descriptor.
17865  *  0b1..DECO has been given at least four words of the descriptor.
17866  */
17867 #define CAAM_DDJR_FOUR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK)
17868 
17869 #define CAAM_DDJR_WHL_MASK                       (0x20000000U)
17870 #define CAAM_DDJR_WHL_SHIFT                      (29U)
17871 /*! WHL
17872  *  0b0..DECO has not been given the whole descriptor.
17873  *  0b1..DECO has been given the whole descriptor.
17874  */
17875 #define CAAM_DDJR_WHL(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK)
17876 
17877 #define CAAM_DDJR_SING_MASK                      (0x40000000U)
17878 #define CAAM_DDJR_SING_SHIFT                     (30U)
17879 /*! SING
17880  *  0b0..DECO has not been told to execute the descriptor in single-step mode.
17881  *  0b1..DECO has been told to execute the descriptor in single-step mode.
17882  */
17883 #define CAAM_DDJR_SING(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK)
17884 
17885 #define CAAM_DDJR_STEP_MASK                      (0x80000000U)
17886 #define CAAM_DDJR_STEP_SHIFT                     (31U)
17887 /*! STEP
17888  *  0b0..DECO has not been told to execute the next command in the descriptor.
17889  *  0b1..DECO has been told to execute the next command in the descriptor.
17890  */
17891 #define CAAM_DDJR_STEP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK)
17892 /*! @} */
17893 
17894 /* The count of CAAM_DDJR */
17895 #define CAAM_DDJR_COUNT                          (1U)
17896 
17897 /*! @name DDDR - DECO0 Debug DECO Register */
17898 /*! @{ */
17899 
17900 #define CAAM_DDDR_CT_MASK                        (0x1U)
17901 #define CAAM_DDDR_CT_SHIFT                       (0U)
17902 /*! CT
17903  *  0b0..This DECO is NOTcurrently generating the signature of a Trusted Descriptor.
17904  *  0b1..This DECO is currently generating the signature of a Trusted Descriptor.
17905  */
17906 #define CAAM_DDDR_CT(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK)
17907 
17908 #define CAAM_DDDR_BRB_MASK                       (0x2U)
17909 #define CAAM_DDDR_BRB_SHIFT                      (1U)
17910 /*! BRB
17911  *  0b0..The READ machine in the Burster is not busy.
17912  *  0b1..The READ machine in the Burster is busy.
17913  */
17914 #define CAAM_DDDR_BRB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK)
17915 
17916 #define CAAM_DDDR_BWB_MASK                       (0x4U)
17917 #define CAAM_DDDR_BWB_SHIFT                      (2U)
17918 /*! BWB
17919  *  0b0..The WRITE machine in the Burster is not busy.
17920  *  0b1..The WRITE machine in the Burster is busy.
17921  */
17922 #define CAAM_DDDR_BWB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK)
17923 
17924 #define CAAM_DDDR_NC_MASK                        (0x8U)
17925 #define CAAM_DDDR_NC_SHIFT                       (3U)
17926 /*! NC
17927  *  0b0..This DECO is currently executing a command.
17928  *  0b1..This DECO is not currently executing a command.
17929  */
17930 #define CAAM_DDDR_NC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK)
17931 
17932 #define CAAM_DDDR_CSA_MASK                       (0x10U)
17933 #define CAAM_DDDR_CSA_SHIFT                      (4U)
17934 #define CAAM_DDDR_CSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK)
17935 
17936 #define CAAM_DDDR_CMD_STAGE_MASK                 (0xE0U)
17937 #define CAAM_DDDR_CMD_STAGE_SHIFT                (5U)
17938 #define CAAM_DDDR_CMD_STAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK)
17939 
17940 #define CAAM_DDDR_CMD_INDEX_MASK                 (0x3F00U)
17941 #define CAAM_DDDR_CMD_INDEX_SHIFT                (8U)
17942 #define CAAM_DDDR_CMD_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK)
17943 
17944 #define CAAM_DDDR_NLJ_MASK                       (0x4000U)
17945 #define CAAM_DDDR_NLJ_SHIFT                      (14U)
17946 /*! NLJ
17947  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17948  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17949  */
17950 #define CAAM_DDDR_NLJ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK)
17951 
17952 #define CAAM_DDDR_PTCL_RUN_MASK                  (0x8000U)
17953 #define CAAM_DDDR_PTCL_RUN_SHIFT                 (15U)
17954 /*! PTCL_RUN
17955  *  0b0..No protocol is running in this DECO.
17956  *  0b1..A protocol is running in this DECO.
17957  */
17958 #define CAAM_DDDR_PTCL_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK)
17959 
17960 #define CAAM_DDDR_PDB_STALL_MASK                 (0x30000U)
17961 #define CAAM_DDDR_PDB_STALL_SHIFT                (16U)
17962 #define CAAM_DDDR_PDB_STALL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK)
17963 
17964 #define CAAM_DDDR_PDB_WB_ST_MASK                 (0xC0000U)
17965 #define CAAM_DDDR_PDB_WB_ST_SHIFT                (18U)
17966 #define CAAM_DDDR_PDB_WB_ST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK)
17967 
17968 #define CAAM_DDDR_DECO_STATE_MASK                (0xF00000U)
17969 #define CAAM_DDDR_DECO_STATE_SHIFT               (20U)
17970 #define CAAM_DDDR_DECO_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK)
17971 
17972 #define CAAM_DDDR_NSEQLSEL_MASK                  (0x3000000U)
17973 #define CAAM_DDDR_NSEQLSEL_SHIFT                 (24U)
17974 /*! NSEQLSEL
17975  *  0b01..SEQ DID
17976  *  0b10..Non-SEQ DID
17977  *  0b11..Trusted DID
17978  */
17979 #define CAAM_DDDR_NSEQLSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK)
17980 
17981 #define CAAM_DDDR_SEQLSEL_MASK                   (0xC000000U)
17982 #define CAAM_DDDR_SEQLSEL_SHIFT                  (26U)
17983 /*! SEQLSEL
17984  *  0b01..SEQ DID
17985  *  0b10..Non-SEQ DID
17986  *  0b11..Trusted DID
17987  */
17988 #define CAAM_DDDR_SEQLSEL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK)
17989 
17990 #define CAAM_DDDR_TRCT_MASK                      (0x30000000U)
17991 #define CAAM_DDDR_TRCT_SHIFT                     (28U)
17992 #define CAAM_DDDR_TRCT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK)
17993 
17994 #define CAAM_DDDR_SD_MASK                        (0x40000000U)
17995 #define CAAM_DDDR_SD_SHIFT                       (30U)
17996 /*! SD
17997  *  0b0..This DECO has not received a shared descriptor from another DECO.
17998  *  0b1..This DECO has received a shared descriptor from another DECO.
17999  */
18000 #define CAAM_DDDR_SD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK)
18001 
18002 #define CAAM_DDDR_VALID_MASK                     (0x80000000U)
18003 #define CAAM_DDDR_VALID_SHIFT                    (31U)
18004 /*! VALID
18005  *  0b0..No descriptor is currently running in this DECO.
18006  *  0b1..There is currently a descriptor running in this DECO.
18007  */
18008 #define CAAM_DDDR_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK)
18009 /*! @} */
18010 
18011 /* The count of CAAM_DDDR */
18012 #define CAAM_DDDR_COUNT                          (1U)
18013 
18014 /*! @name DDJP - DECO0 Debug Job Pointer */
18015 /*! @{ */
18016 
18017 #define CAAM_DDJP_JDPTR_MASK                     (0xFFFFFFFFFU)
18018 #define CAAM_DDJP_JDPTR_SHIFT                    (0U)
18019 #define CAAM_DDJP_JDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK)
18020 /*! @} */
18021 
18022 /* The count of CAAM_DDJP */
18023 #define CAAM_DDJP_COUNT                          (1U)
18024 
18025 /*! @name DSDP - DECO0 Debug Shared Pointer */
18026 /*! @{ */
18027 
18028 #define CAAM_DSDP_SDPTR_MASK                     (0xFFFFFFFFFU)
18029 #define CAAM_DSDP_SDPTR_SHIFT                    (0U)
18030 #define CAAM_DSDP_SDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK)
18031 /*! @} */
18032 
18033 /* The count of CAAM_DSDP */
18034 #define CAAM_DSDP_COUNT                          (1U)
18035 
18036 /*! @name DDDR_MS - DECO0 Debug DID, most-significant half */
18037 /*! @{ */
18038 
18039 #define CAAM_DDDR_MS_PRIM_DID_MASK               (0xFU)
18040 #define CAAM_DDDR_MS_PRIM_DID_SHIFT              (0U)
18041 #define CAAM_DDDR_MS_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK)
18042 
18043 #define CAAM_DDDR_MS_PRIM_TZ_MASK                (0x10U)
18044 #define CAAM_DDDR_MS_PRIM_TZ_SHIFT               (4U)
18045 /*! PRIM_TZ
18046  *  0b0..TrustZone NonSecureWorld
18047  *  0b1..TrustZone SecureWorld
18048  */
18049 #define CAAM_DDDR_MS_PRIM_TZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK)
18050 
18051 #define CAAM_DDDR_MS_PRIM_ICID_MASK              (0xFFE0U)
18052 #define CAAM_DDDR_MS_PRIM_ICID_SHIFT             (5U)
18053 #define CAAM_DDDR_MS_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK)
18054 
18055 #define CAAM_DDDR_MS_OUT_DID_MASK                (0xF0000U)
18056 #define CAAM_DDDR_MS_OUT_DID_SHIFT               (16U)
18057 #define CAAM_DDDR_MS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK)
18058 
18059 #define CAAM_DDDR_MS_OUT_ICID_MASK               (0xFFE00000U)
18060 #define CAAM_DDDR_MS_OUT_ICID_SHIFT              (21U)
18061 #define CAAM_DDDR_MS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK)
18062 /*! @} */
18063 
18064 /* The count of CAAM_DDDR_MS */
18065 #define CAAM_DDDR_MS_COUNT                       (1U)
18066 
18067 /*! @name DDDR_LS - DECO0 Debug DID, least-significant half */
18068 /*! @{ */
18069 
18070 #define CAAM_DDDR_LS_OUT_DID_MASK                (0xFU)
18071 #define CAAM_DDDR_LS_OUT_DID_SHIFT               (0U)
18072 #define CAAM_DDDR_LS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK)
18073 
18074 #define CAAM_DDDR_LS_OUT_ICID_MASK               (0x3FF80000U)
18075 #define CAAM_DDDR_LS_OUT_ICID_SHIFT              (19U)
18076 #define CAAM_DDDR_LS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK)
18077 /*! @} */
18078 
18079 /* The count of CAAM_DDDR_LS */
18080 #define CAAM_DDDR_LS_COUNT                       (1U)
18081 
18082 /*! @name SOL - Sequence Output Length Register */
18083 /*! @{ */
18084 
18085 #define CAAM_SOL_SOL_MASK                        (0xFFFFFFFFU)
18086 #define CAAM_SOL_SOL_SHIFT                       (0U)
18087 #define CAAM_SOL_SOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK)
18088 /*! @} */
18089 
18090 /* The count of CAAM_SOL */
18091 #define CAAM_SOL_COUNT                           (1U)
18092 
18093 /*! @name VSOL - Variable Sequence Output Length Register */
18094 /*! @{ */
18095 
18096 #define CAAM_VSOL_VSOL_MASK                      (0xFFFFFFFFU)
18097 #define CAAM_VSOL_VSOL_SHIFT                     (0U)
18098 #define CAAM_VSOL_VSOL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK)
18099 /*! @} */
18100 
18101 /* The count of CAAM_VSOL */
18102 #define CAAM_VSOL_COUNT                          (1U)
18103 
18104 /*! @name SIL - Sequence Input Length Register */
18105 /*! @{ */
18106 
18107 #define CAAM_SIL_SIL_MASK                        (0xFFFFFFFFU)
18108 #define CAAM_SIL_SIL_SHIFT                       (0U)
18109 #define CAAM_SIL_SIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK)
18110 /*! @} */
18111 
18112 /* The count of CAAM_SIL */
18113 #define CAAM_SIL_COUNT                           (1U)
18114 
18115 /*! @name VSIL - Variable Sequence Input Length Register */
18116 /*! @{ */
18117 
18118 #define CAAM_VSIL_VSIL_MASK                      (0xFFFFFFFFU)
18119 #define CAAM_VSIL_VSIL_SHIFT                     (0U)
18120 #define CAAM_VSIL_VSIL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK)
18121 /*! @} */
18122 
18123 /* The count of CAAM_VSIL */
18124 #define CAAM_VSIL_COUNT                          (1U)
18125 
18126 /*! @name DPOVRD - Protocol Override Register */
18127 /*! @{ */
18128 
18129 #define CAAM_DPOVRD_DPOVRD_MASK                  (0xFFFFFFFFU)
18130 #define CAAM_DPOVRD_DPOVRD_SHIFT                 (0U)
18131 #define CAAM_DPOVRD_DPOVRD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK)
18132 /*! @} */
18133 
18134 /* The count of CAAM_DPOVRD */
18135 #define CAAM_DPOVRD_COUNT                        (1U)
18136 
18137 /*! @name UVSOL - Variable Sequence Output Length Register; Upper 32 bits */
18138 /*! @{ */
18139 
18140 #define CAAM_UVSOL_UVSOL_MASK                    (0xFFFFFFFFU)
18141 #define CAAM_UVSOL_UVSOL_SHIFT                   (0U)
18142 #define CAAM_UVSOL_UVSOL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK)
18143 /*! @} */
18144 
18145 /* The count of CAAM_UVSOL */
18146 #define CAAM_UVSOL_COUNT                         (1U)
18147 
18148 /*! @name UVSIL - Variable Sequence Input Length Register; Upper 32 bits */
18149 /*! @{ */
18150 
18151 #define CAAM_UVSIL_UVSIL_MASK                    (0xFFFFFFFFU)
18152 #define CAAM_UVSIL_UVSIL_SHIFT                   (0U)
18153 #define CAAM_UVSIL_UVSIL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK)
18154 /*! @} */
18155 
18156 /* The count of CAAM_UVSIL */
18157 #define CAAM_UVSIL_COUNT                         (1U)
18158 
18159 
18160 /*!
18161  * @}
18162  */ /* end of group CAAM_Register_Masks */
18163 
18164 
18165 /* CAAM - Peripheral instance base addresses */
18166 /** Peripheral CAAM base address */
18167 #define CAAM_BASE                                (0x40440000u)
18168 /** Peripheral CAAM base pointer */
18169 #define CAAM                                     ((CAAM_Type *)CAAM_BASE)
18170 /** Array initializer of CAAM peripheral base addresses */
18171 #define CAAM_BASE_ADDRS                          { CAAM_BASE }
18172 /** Array initializer of CAAM peripheral base pointers */
18173 #define CAAM_BASE_PTRS                           { CAAM }
18174 
18175 /*!
18176  * @}
18177  */ /* end of group CAAM_Peripheral_Access_Layer */
18178 
18179 
18180 /* ----------------------------------------------------------------------------
18181    -- CAN Peripheral Access Layer
18182    ---------------------------------------------------------------------------- */
18183 
18184 /*!
18185  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
18186  * @{
18187  */
18188 
18189 /** CAN - Register Layout Typedef */
18190 typedef struct {
18191   __IO uint32_t MCR;                               /**< Module Configuration register, offset: 0x0 */
18192   __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
18193   __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
18194        uint8_t RESERVED_0[4];
18195   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask register, offset: 0x10 */
18196   __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
18197   __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
18198   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
18199   __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
18200   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
18201   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
18202   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
18203   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
18204   __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
18205   __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
18206        uint8_t RESERVED_1[8];
18207   __I  uint32_t CRCR;                              /**< CRC register, offset: 0x44 */
18208   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
18209   __I  uint32_t RXFIR;                             /**< Rx FIFO Information register, offset: 0x4C */
18210   __IO uint32_t CBT;                               /**< CAN Bit Timing register, offset: 0x50 */
18211        uint8_t RESERVED_2[44];
18212   union {                                          /* offset: 0x80 */
18213     struct {                                         /* offset: 0x80, array step: 0x10 */
18214       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
18215       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
18216       __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
18217     } MB_8B[64];
18218     struct {                                         /* offset: 0x80 */
18219       struct {                                         /* offset: 0x80, array step: 0x18 */
18220         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
18221         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
18222         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
18223       } MB_16B_L[21];
18224            uint8_t RESERVED_0[8];
18225       struct {                                         /* offset: 0x280, array step: 0x18 */
18226         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18 */
18227         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18 */
18228         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4 */
18229       } MB_16B_H[21];
18230     } MB_16B;
18231     struct {                                         /* offset: 0x80 */
18232       struct {                                         /* offset: 0x80, array step: 0x28 */
18233         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
18234         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
18235         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
18236       } MB_32B_L[12];
18237            uint8_t RESERVED_0[32];
18238       struct {                                         /* offset: 0x280, array step: 0x28 */
18239         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28 */
18240         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28 */
18241         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4 */
18242       } MB_32B_H[12];
18243     } MB_32B;
18244     struct {                                         /* offset: 0x80 */
18245       struct {                                         /* offset: 0x80, array step: 0x48 */
18246         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
18247         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
18248         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
18249       } MB_64B_L[7];
18250            uint8_t RESERVED_0[8];
18251       struct {                                         /* offset: 0x280, array step: 0x48 */
18252         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48 */
18253         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48 */
18254         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4 */
18255       } MB_64B_H[7];
18256     } MB_64B;
18257     struct {                                         /* offset: 0x80, array step: 0x10 */
18258       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
18259       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
18260       __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
18261       __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
18262     } MB[64];
18263   };
18264        uint8_t RESERVED_3[1024];
18265   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
18266        uint8_t RESERVED_4[352];
18267   __IO uint32_t MECR;                              /**< Memory Error Control register, offset: 0xAE0 */
18268   __IO uint32_t ERRIAR;                            /**< Error Injection Address register, offset: 0xAE4 */
18269   __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern register, offset: 0xAE8 */
18270   __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern register, offset: 0xAEC */
18271   __I  uint32_t RERRAR;                            /**< Error Report Address register, offset: 0xAF0 */
18272   __I  uint32_t RERRDR;                            /**< Error Report Data register, offset: 0xAF4 */
18273   __I  uint32_t RERRSYNR;                          /**< Error Report Syndrome register, offset: 0xAF8 */
18274   __IO uint32_t ERRSR;                             /**< Error Status register, offset: 0xAFC */
18275        uint8_t RESERVED_5[256];
18276   __IO uint32_t FDCTRL;                            /**< CAN FD Control register, offset: 0xC00 */
18277   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing register, offset: 0xC04 */
18278   __I  uint32_t FDCRC;                             /**< CAN FD CRC register, offset: 0xC08 */
18279 } CAN_Type;
18280 
18281 /* ----------------------------------------------------------------------------
18282    -- CAN Register Masks
18283    ---------------------------------------------------------------------------- */
18284 
18285 /*!
18286  * @addtogroup CAN_Register_Masks CAN Register Masks
18287  * @{
18288  */
18289 
18290 /*! @name MCR - Module Configuration register */
18291 /*! @{ */
18292 
18293 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
18294 #define CAN_MCR_MAXMB_SHIFT                      (0U)
18295 /*! MAXMB - Number Of The Last Message Buffer
18296  */
18297 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
18298 
18299 #define CAN_MCR_IDAM_MASK                        (0x300U)
18300 #define CAN_MCR_IDAM_SHIFT                       (8U)
18301 /*! IDAM - ID Acceptance Mode
18302  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
18303  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
18304  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
18305  *  0b11..Format D: All frames rejected.
18306  */
18307 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
18308 
18309 #define CAN_MCR_FDEN_MASK                        (0x800U)
18310 #define CAN_MCR_FDEN_SHIFT                       (11U)
18311 /*! FDEN - CAN FD operation enable
18312  *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
18313  *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
18314  */
18315 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
18316 
18317 #define CAN_MCR_AEN_MASK                         (0x1000U)
18318 #define CAN_MCR_AEN_SHIFT                        (12U)
18319 /*! AEN - Abort Enable
18320  *  0b0..Abort disabled.
18321  *  0b1..Abort enabled.
18322  */
18323 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
18324 
18325 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
18326 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
18327 /*! LPRIOEN - Local Priority Enable
18328  *  0b0..Local Priority disabled.
18329  *  0b1..Local Priority enabled.
18330  */
18331 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
18332 
18333 #define CAN_MCR_DMA_MASK                         (0x8000U)
18334 #define CAN_MCR_DMA_SHIFT                        (15U)
18335 /*! DMA - DMA Enable
18336  *  0b0..DMA feature for RX FIFO disabled.
18337  *  0b1..DMA feature for RX FIFO enabled.
18338  */
18339 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
18340 
18341 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
18342 #define CAN_MCR_IRMQ_SHIFT                       (16U)
18343 /*! IRMQ - Individual Rx Masking And Queue Enable
18344  *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
18345  *       applications, the reading of C/S word locks the MB even if it is EMPTY.
18346  *  0b1..Individual Rx masking and queue feature are enabled.
18347  */
18348 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
18349 
18350 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
18351 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
18352 /*! SRXDIS - Self Reception Disable
18353  *  0b0..Self-reception enabled.
18354  *  0b1..Self-reception disabled.
18355  */
18356 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
18357 
18358 #define CAN_MCR_DOZE_MASK                        (0x40000U)
18359 #define CAN_MCR_DOZE_SHIFT                       (18U)
18360 /*! DOZE - Doze Mode Enable
18361  *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
18362  *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
18363  */
18364 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
18365 
18366 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
18367 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
18368 /*! WAKSRC - Wake Up Source
18369  *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
18370  *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
18371  */
18372 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
18373 
18374 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
18375 #define CAN_MCR_LPMACK_SHIFT                     (20U)
18376 /*! LPMACK - Low-Power Mode Acknowledge
18377  *  0b0..FlexCAN is not in a low-power mode.
18378  *  0b1..FlexCAN is in a low-power mode.
18379  */
18380 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
18381 
18382 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
18383 #define CAN_MCR_WRNEN_SHIFT                      (21U)
18384 /*! WRNEN - Warning Interrupt Enable
18385  *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
18386  *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
18387  */
18388 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
18389 
18390 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
18391 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
18392 /*! SLFWAK - Self Wake Up
18393  *  0b0..FlexCAN Self Wake Up feature is disabled.
18394  *  0b1..FlexCAN Self Wake Up feature is enabled.
18395  */
18396 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
18397 
18398 #define CAN_MCR_SUPV_MASK                        (0x800000U)
18399 #define CAN_MCR_SUPV_SHIFT                       (23U)
18400 /*! SUPV - Supervisor Mode
18401  *  0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.
18402  *  0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
18403  *       behaves as though the access was done to an unimplemented register location.
18404  */
18405 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
18406 
18407 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
18408 #define CAN_MCR_FRZACK_SHIFT                     (24U)
18409 /*! FRZACK - Freeze Mode Acknowledge
18410  *  0b0..FlexCAN not in Freeze mode, prescaler running.
18411  *  0b1..FlexCAN in Freeze mode, prescaler stopped.
18412  */
18413 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
18414 
18415 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
18416 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
18417 /*! SOFTRST - Soft Reset
18418  *  0b0..No reset request.
18419  *  0b1..Resets the registers affected by soft reset.
18420  */
18421 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
18422 
18423 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
18424 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
18425 /*! WAKMSK - Wake Up Interrupt Mask
18426  *  0b0..Wake Up interrupt is disabled.
18427  *  0b1..Wake Up interrupt is enabled.
18428  */
18429 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
18430 
18431 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
18432 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
18433 /*! NOTRDY - FlexCAN Not Ready
18434  *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
18435  *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
18436  */
18437 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
18438 
18439 #define CAN_MCR_HALT_MASK                        (0x10000000U)
18440 #define CAN_MCR_HALT_SHIFT                       (28U)
18441 /*! HALT - Halt FlexCAN
18442  *  0b0..No Freeze mode request.
18443  *  0b1..Enters Freeze mode if the FRZ bit is asserted.
18444  */
18445 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
18446 
18447 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
18448 #define CAN_MCR_RFEN_SHIFT                       (29U)
18449 /*! RFEN - Rx FIFO Enable
18450  *  0b0..Rx FIFO not enabled.
18451  *  0b1..Rx FIFO enabled.
18452  */
18453 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
18454 
18455 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
18456 #define CAN_MCR_FRZ_SHIFT                        (30U)
18457 /*! FRZ - Freeze Enable
18458  *  0b0..Not enabled to enter Freeze mode.
18459  *  0b1..Enabled to enter Freeze mode.
18460  */
18461 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
18462 
18463 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
18464 #define CAN_MCR_MDIS_SHIFT                       (31U)
18465 /*! MDIS - Module Disable
18466  *  0b0..Enable the FlexCAN module.
18467  *  0b1..Disable the FlexCAN module.
18468  */
18469 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
18470 /*! @} */
18471 
18472 /*! @name CTRL1 - Control 1 register */
18473 /*! @{ */
18474 
18475 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
18476 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
18477 /*! PROPSEG - Propagation Segment
18478  */
18479 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
18480 
18481 #define CAN_CTRL1_LOM_MASK                       (0x8U)
18482 #define CAN_CTRL1_LOM_SHIFT                      (3U)
18483 /*! LOM - Listen-Only Mode
18484  *  0b0..Listen-Only mode is deactivated.
18485  *  0b1..FlexCAN module operates in Listen-Only mode.
18486  */
18487 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
18488 
18489 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
18490 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
18491 /*! LBUF - Lowest Buffer Transmitted First
18492  *  0b0..Buffer with highest priority is transmitted first.
18493  *  0b1..Lowest number buffer is transmitted first.
18494  */
18495 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
18496 
18497 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
18498 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
18499 /*! TSYN - Timer Sync
18500  *  0b0..Timer sync feature disabled
18501  *  0b1..Timer sync feature enabled
18502  */
18503 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
18504 
18505 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
18506 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
18507 /*! BOFFREC - Bus Off Recovery
18508  *  0b0..Automatic recovering from Bus Off state enabled.
18509  *  0b1..Automatic recovering from Bus Off state disabled.
18510  */
18511 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
18512 
18513 #define CAN_CTRL1_SMP_MASK                       (0x80U)
18514 #define CAN_CTRL1_SMP_SHIFT                      (7U)
18515 /*! SMP - CAN Bit Sampling
18516  *  0b0..Just one sample is used to determine the bit value.
18517  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
18518  *       preceding samples; a majority rule is used.
18519  */
18520 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
18521 
18522 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
18523 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
18524 /*! RWRNMSK - Rx Warning Interrupt Mask
18525  *  0b0..Rx Warning interrupt disabled.
18526  *  0b1..Rx Warning interrupt enabled.
18527  */
18528 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
18529 
18530 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
18531 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
18532 /*! TWRNMSK - Tx Warning Interrupt Mask
18533  *  0b0..Tx Warning interrupt disabled.
18534  *  0b1..Tx Warning interrupt enabled.
18535  */
18536 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
18537 
18538 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
18539 #define CAN_CTRL1_LPB_SHIFT                      (12U)
18540 /*! LPB - Loop Back Mode
18541  *  0b0..Loop Back disabled.
18542  *  0b1..Loop Back enabled.
18543  */
18544 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
18545 
18546 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
18547 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
18548 /*! CLKSRC - CAN Engine Clock Source
18549  *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
18550  *  0b1..The CAN engine clock source is the peripheral clock.
18551  */
18552 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
18553 
18554 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
18555 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
18556 /*! ERRMSK - Error Interrupt Mask
18557  *  0b0..Error interrupt disabled.
18558  *  0b1..Error interrupt enabled.
18559  */
18560 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
18561 
18562 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
18563 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
18564 /*! BOFFMSK - Bus Off Interrupt Mask
18565  *  0b0..Bus Off interrupt disabled.
18566  *  0b1..Bus Off interrupt enabled.
18567  */
18568 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
18569 
18570 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
18571 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
18572 /*! PSEG2 - Phase Segment 2
18573  */
18574 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
18575 
18576 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
18577 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
18578 /*! PSEG1 - Phase Segment 1
18579  */
18580 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
18581 
18582 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
18583 #define CAN_CTRL1_RJW_SHIFT                      (22U)
18584 /*! RJW - Resync Jump Width
18585  */
18586 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
18587 
18588 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
18589 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
18590 /*! PRESDIV - Prescaler Division Factor
18591  */
18592 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
18593 /*! @} */
18594 
18595 /*! @name TIMER - Free Running Timer */
18596 /*! @{ */
18597 
18598 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
18599 #define CAN_TIMER_TIMER_SHIFT                    (0U)
18600 /*! TIMER - Timer Value
18601  */
18602 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
18603 /*! @} */
18604 
18605 /*! @name RXMGMASK - Rx Mailboxes Global Mask register */
18606 /*! @{ */
18607 
18608 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
18609 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
18610 /*! MG - Rx Mailboxes Global Mask Bits
18611  */
18612 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
18613 /*! @} */
18614 
18615 /*! @name RX14MASK - Rx 14 Mask register */
18616 /*! @{ */
18617 
18618 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
18619 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
18620 /*! RX14M - Rx Buffer 14 Mask Bits
18621  */
18622 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
18623 /*! @} */
18624 
18625 /*! @name RX15MASK - Rx 15 Mask register */
18626 /*! @{ */
18627 
18628 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
18629 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
18630 /*! RX15M - Rx Buffer 15 Mask Bits
18631  */
18632 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
18633 /*! @} */
18634 
18635 /*! @name ECR - Error Counter */
18636 /*! @{ */
18637 
18638 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
18639 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
18640 /*! TXERRCNT - Transmit Error Counter
18641  */
18642 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
18643 
18644 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
18645 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
18646 /*! RXERRCNT - Receive Error Counter
18647  */
18648 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
18649 
18650 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
18651 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
18652 /*! TXERRCNT_FAST - Transmit Error Counter for fast bits
18653  */
18654 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
18655 
18656 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
18657 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
18658 /*! RXERRCNT_FAST - Receive Error Counter for fast bits
18659  */
18660 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
18661 /*! @} */
18662 
18663 /*! @name ESR1 - Error and Status 1 register */
18664 /*! @{ */
18665 
18666 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
18667 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
18668 /*! WAKINT - Wake-Up Interrupt
18669  *  0b0..No such occurrence.
18670  *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
18671  */
18672 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
18673 
18674 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
18675 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
18676 /*! ERRINT - Error Interrupt
18677  *  0b0..No such occurrence.
18678  *  0b1..Indicates setting of any error bit in the Error and Status register.
18679  */
18680 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
18681 
18682 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
18683 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
18684 /*! BOFFINT - Bus Off Interrupt
18685  *  0b0..No such occurrence.
18686  *  0b1..FlexCAN module entered Bus Off state.
18687  */
18688 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
18689 
18690 #define CAN_ESR1_RX_MASK                         (0x8U)
18691 #define CAN_ESR1_RX_SHIFT                        (3U)
18692 /*! RX - FlexCAN In Reception
18693  *  0b0..FlexCAN is not receiving a message.
18694  *  0b1..FlexCAN is receiving a message.
18695  */
18696 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
18697 
18698 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
18699 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
18700 /*! FLTCONF - Fault Confinement State
18701  *  0b00..Error Active
18702  *  0b01..Error Passive
18703  *  0b1x..Bus Off
18704  */
18705 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
18706 
18707 #define CAN_ESR1_TX_MASK                         (0x40U)
18708 #define CAN_ESR1_TX_SHIFT                        (6U)
18709 /*! TX - FlexCAN In Transmission
18710  *  0b0..FlexCAN is not transmitting a message.
18711  *  0b1..FlexCAN is transmitting a message.
18712  */
18713 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
18714 
18715 #define CAN_ESR1_IDLE_MASK                       (0x80U)
18716 #define CAN_ESR1_IDLE_SHIFT                      (7U)
18717 /*! IDLE - IDLE
18718  *  0b0..No such occurrence.
18719  *  0b1..CAN bus is now IDLE.
18720  */
18721 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
18722 
18723 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
18724 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
18725 /*! RXWRN - Rx Error Warning
18726  *  0b0..No such occurrence.
18727  *  0b1..RXERRCNT is greater than or equal to 96.
18728  */
18729 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
18730 
18731 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
18732 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
18733 /*! TXWRN - TX Error Warning
18734  *  0b0..No such occurrence.
18735  *  0b1..TXERRCNT is greater than or equal to 96.
18736  */
18737 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
18738 
18739 #define CAN_ESR1_STFERR_MASK                     (0x400U)
18740 #define CAN_ESR1_STFERR_SHIFT                    (10U)
18741 /*! STFERR - Stuffing Error
18742  *  0b0..No such occurrence.
18743  *  0b1..A stuffing error occurred since last read of this register.
18744  */
18745 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
18746 
18747 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
18748 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
18749 /*! FRMERR - Form Error
18750  *  0b0..No such occurrence.
18751  *  0b1..A Form Error occurred since last read of this register.
18752  */
18753 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
18754 
18755 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
18756 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
18757 /*! CRCERR - Cyclic Redundancy Check Error
18758  *  0b0..No such occurrence.
18759  *  0b1..A CRC error occurred since last read of this register.
18760  */
18761 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
18762 
18763 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
18764 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
18765 /*! ACKERR - Acknowledge Error
18766  *  0b0..No such occurrence.
18767  *  0b1..An ACK error occurred since last read of this register.
18768  */
18769 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
18770 
18771 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
18772 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
18773 /*! BIT0ERR - Bit0 Error
18774  *  0b0..No such occurrence.
18775  *  0b1..At least one bit sent as dominant is received as recessive.
18776  */
18777 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
18778 
18779 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
18780 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
18781 /*! BIT1ERR - Bit1 Error
18782  *  0b0..No such occurrence.
18783  *  0b1..At least one bit sent as recessive is received as dominant.
18784  */
18785 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
18786 
18787 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
18788 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
18789 /*! RWRNINT - Rx Warning Interrupt Flag
18790  *  0b0..No such occurrence.
18791  *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
18792  */
18793 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
18794 
18795 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
18796 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
18797 /*! TWRNINT - Tx Warning Interrupt Flag
18798  *  0b0..No such occurrence.
18799  *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
18800  */
18801 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
18802 
18803 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
18804 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
18805 /*! SYNCH - CAN Synchronization Status
18806  *  0b0..FlexCAN is not synchronized to the CAN bus.
18807  *  0b1..FlexCAN is synchronized to the CAN bus.
18808  */
18809 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
18810 
18811 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
18812 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
18813 /*! BOFFDONEINT - Bus Off Done Interrupt
18814  *  0b0..No such occurrence.
18815  *  0b1..FlexCAN module has completed Bus Off process.
18816  */
18817 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
18818 
18819 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
18820 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
18821 /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
18822  *  0b0..No such occurrence.
18823  *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
18824  */
18825 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
18826 
18827 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
18828 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
18829 /*! ERROVR - Error Overrun
18830  *  0b0..Overrun has not occurred.
18831  *  0b1..Overrun has occurred.
18832  */
18833 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
18834 
18835 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
18836 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
18837 /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
18838  *  0b0..No such occurrence.
18839  *  0b1..A stuffing error occurred since last read of this register.
18840  */
18841 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
18842 
18843 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
18844 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
18845 /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
18846  *  0b0..No such occurrence.
18847  *  0b1..A form error occurred since last read of this register.
18848  */
18849 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
18850 
18851 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
18852 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
18853 /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
18854  *  0b0..No such occurrence.
18855  *  0b1..A CRC error occurred since last read of this register.
18856  */
18857 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
18858 
18859 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
18860 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
18861 /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
18862  *  0b0..No such occurrence.
18863  *  0b1..At least one bit sent as dominant is received as recessive.
18864  */
18865 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
18866 
18867 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
18868 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
18869 /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
18870  *  0b0..No such occurrence.
18871  *  0b1..At least one bit sent as recessive is received as dominant.
18872  */
18873 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
18874 /*! @} */
18875 
18876 /*! @name IMASK2 - Interrupt Masks 2 register */
18877 /*! @{ */
18878 
18879 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
18880 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
18881 /*! BUF63TO32M - Buffer MBi Mask
18882  */
18883 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
18884 /*! @} */
18885 
18886 /*! @name IMASK1 - Interrupt Masks 1 register */
18887 /*! @{ */
18888 
18889 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
18890 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
18891 /*! BUF31TO0M - Buffer MBi Mask
18892  */
18893 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
18894 /*! @} */
18895 
18896 /*! @name IFLAG2 - Interrupt Flags 2 register */
18897 /*! @{ */
18898 
18899 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
18900 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
18901 /*! BUF63TO32I - Buffer MBi Interrupt
18902  */
18903 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
18904 /*! @} */
18905 
18906 /*! @name IFLAG1 - Interrupt Flags 1 register */
18907 /*! @{ */
18908 
18909 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
18910 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
18911 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
18912  *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
18913  *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
18914  */
18915 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
18916 
18917 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
18918 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
18919 /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
18920  */
18921 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
18922 
18923 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
18924 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
18925 /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
18926  *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
18927  *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
18928  *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
18929  */
18930 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
18931 
18932 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
18933 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
18934 /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
18935  *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
18936  *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
18937  */
18938 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
18939 
18940 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
18941 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
18942 /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
18943  *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
18944  *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
18945  */
18946 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
18947 
18948 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
18949 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
18950 /*! BUF31TO8I - Buffer MBi Interrupt
18951  */
18952 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
18953 /*! @} */
18954 
18955 /*! @name CTRL2 - Control 2 register */
18956 /*! @{ */
18957 
18958 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
18959 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
18960 /*! EDFLTDIS - Edge Filter Disable
18961  *  0b0..Edge filter is enabled
18962  *  0b1..Edge filter is disabled
18963  */
18964 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
18965 
18966 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
18967 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
18968 /*! ISOCANFDEN - ISO CAN FD Enable
18969  *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
18970  *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
18971  */
18972 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
18973 
18974 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
18975 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
18976 /*! PREXCEN - Protocol Exception Enable
18977  *  0b0..Protocol exception is disabled.
18978  *  0b1..Protocol exception is enabled.
18979  */
18980 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
18981 
18982 #define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
18983 #define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
18984 /*! TIMER_SRC - Timer Source
18985  *  0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
18986  *  0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
18987  *       to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
18988  *       details about the external time tick.
18989  */
18990 #define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
18991 
18992 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
18993 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
18994 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
18995  *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
18996  *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
18997  *       the incoming frame. Mask bits do apply.
18998  */
18999 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
19000 
19001 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
19002 #define CAN_CTRL2_RRS_SHIFT                      (17U)
19003 /*! RRS - Remote Request Storing
19004  *  0b0..Remote response frame is generated.
19005  *  0b1..Remote request frame is stored.
19006  */
19007 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
19008 
19009 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
19010 #define CAN_CTRL2_MRP_SHIFT                      (18U)
19011 /*! MRP - Mailboxes Reception Priority
19012  *  0b0..Matching starts from Rx FIFO and continues on mailboxes.
19013  *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
19014  */
19015 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
19016 
19017 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
19018 #define CAN_CTRL2_TASD_SHIFT                     (19U)
19019 /*! TASD - Tx Arbitration Start Delay
19020  */
19021 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
19022 
19023 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
19024 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
19025 /*! RFFN - Number Of Rx FIFO Filters
19026  */
19027 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
19028 
19029 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
19030 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
19031 /*! WRMFRZ - Write-Access To Memory In Freeze Mode
19032  *  0b0..Maintain the write access restrictions.
19033  *  0b1..Enable unrestricted write access to FlexCAN memory.
19034  */
19035 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
19036 
19037 #define CAN_CTRL2_ECRWRE_MASK                    (0x20000000U)
19038 #define CAN_CTRL2_ECRWRE_SHIFT                   (29U)
19039 /*! ECRWRE - Error-correction Configuration Register Write Enable
19040  *  0b0..Disable update.
19041  *  0b1..Enable update.
19042  */
19043 #define CAN_CTRL2_ECRWRE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
19044 
19045 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
19046 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
19047 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
19048  *  0b0..Bus off done interrupt disabled.
19049  *  0b1..Bus off done interrupt enabled.
19050  */
19051 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
19052 
19053 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
19054 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
19055 /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
19056  *  0b0..ERRINT_FAST error interrupt disabled.
19057  *  0b1..ERRINT_FAST error interrupt enabled.
19058  */
19059 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
19060 /*! @} */
19061 
19062 /*! @name ESR2 - Error and Status 2 register */
19063 /*! @{ */
19064 
19065 #define CAN_ESR2_IMB_MASK                        (0x2000U)
19066 #define CAN_ESR2_IMB_SHIFT                       (13U)
19067 /*! IMB - Inactive Mailbox
19068  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
19069  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
19070  */
19071 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
19072 
19073 #define CAN_ESR2_VPS_MASK                        (0x4000U)
19074 #define CAN_ESR2_VPS_SHIFT                       (14U)
19075 /*! VPS - Valid Priority Status
19076  *  0b0..Contents of IMB and LPTM are invalid.
19077  *  0b1..Contents of IMB and LPTM are valid.
19078  */
19079 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
19080 
19081 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
19082 #define CAN_ESR2_LPTM_SHIFT                      (16U)
19083 /*! LPTM - Lowest Priority Tx Mailbox
19084  */
19085 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
19086 /*! @} */
19087 
19088 /*! @name CRCR - CRC register */
19089 /*! @{ */
19090 
19091 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
19092 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
19093 /*! TXCRC - Transmitted CRC value
19094  */
19095 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
19096 
19097 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
19098 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
19099 /*! MBCRC - CRC Mailbox
19100  */
19101 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
19102 /*! @} */
19103 
19104 /*! @name RXFGMASK - Rx FIFO Global Mask register */
19105 /*! @{ */
19106 
19107 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
19108 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
19109 /*! FGM - Rx FIFO Global Mask Bits
19110  */
19111 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
19112 /*! @} */
19113 
19114 /*! @name RXFIR - Rx FIFO Information register */
19115 /*! @{ */
19116 
19117 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
19118 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
19119 /*! IDHIT - Identifier Acceptance Filter Hit Indicator
19120  */
19121 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
19122 /*! @} */
19123 
19124 /*! @name CBT - CAN Bit Timing register */
19125 /*! @{ */
19126 
19127 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
19128 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
19129 /*! EPSEG2 - Extended Phase Segment 2
19130  */
19131 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
19132 
19133 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
19134 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
19135 /*! EPSEG1 - Extended Phase Segment 1
19136  */
19137 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
19138 
19139 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
19140 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
19141 /*! EPROPSEG - Extended Propagation Segment
19142  */
19143 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
19144 
19145 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
19146 #define CAN_CBT_ERJW_SHIFT                       (16U)
19147 /*! ERJW - Extended Resync Jump Width
19148  */
19149 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
19150 
19151 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
19152 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
19153 /*! EPRESDIV - Extended Prescaler Division Factor
19154  */
19155 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
19156 
19157 #define CAN_CBT_BTF_MASK                         (0x80000000U)
19158 #define CAN_CBT_BTF_SHIFT                        (31U)
19159 /*! BTF - Bit Timing Format Enable
19160  *  0b0..Extended bit time definitions disabled.
19161  *  0b1..Extended bit time definitions enabled.
19162  */
19163 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
19164 /*! @} */
19165 
19166 /* The count of CAN_CS */
19167 #define CAN_CS_COUNT_MB8B                        (64U)
19168 
19169 /* The count of CAN_ID */
19170 #define CAN_ID_COUNT_MB8B                        (64U)
19171 
19172 /* The count of CAN_WORD */
19173 #define CAN_WORD_COUNT_MB8B                      (64U)
19174 
19175 /* The count of CAN_WORD */
19176 #define CAN_WORD_COUNT_MB8B2                     (2U)
19177 
19178 /* The count of CAN_CS */
19179 #define CAN_CS_COUNT_MB16B_L                     (21U)
19180 
19181 /* The count of CAN_ID */
19182 #define CAN_ID_COUNT_MB16B_L                     (21U)
19183 
19184 /* The count of CAN_WORD */
19185 #define CAN_WORD_COUNT_MB16B_L                   (21U)
19186 
19187 /* The count of CAN_WORD */
19188 #define CAN_WORD_COUNT_MB16B_L2                  (4U)
19189 
19190 /* The count of CAN_CS */
19191 #define CAN_CS_COUNT_MB16B_H                     (21U)
19192 
19193 /* The count of CAN_ID */
19194 #define CAN_ID_COUNT_MB16B_H                     (21U)
19195 
19196 /* The count of CAN_WORD */
19197 #define CAN_WORD_COUNT_MB16B_H                   (21U)
19198 
19199 /* The count of CAN_WORD */
19200 #define CAN_WORD_COUNT_MB16B_H2                  (4U)
19201 
19202 /* The count of CAN_CS */
19203 #define CAN_CS_COUNT_MB32B_L                     (12U)
19204 
19205 /* The count of CAN_ID */
19206 #define CAN_ID_COUNT_MB32B_L                     (12U)
19207 
19208 /* The count of CAN_WORD */
19209 #define CAN_WORD_COUNT_MB32B_L                   (12U)
19210 
19211 /* The count of CAN_WORD */
19212 #define CAN_WORD_COUNT_MB32B_L2                  (8U)
19213 
19214 /* The count of CAN_CS */
19215 #define CAN_CS_COUNT_MB32B_H                     (12U)
19216 
19217 /* The count of CAN_ID */
19218 #define CAN_ID_COUNT_MB32B_H                     (12U)
19219 
19220 /* The count of CAN_WORD */
19221 #define CAN_WORD_COUNT_MB32B_H                   (12U)
19222 
19223 /* The count of CAN_WORD */
19224 #define CAN_WORD_COUNT_MB32B_H2                  (8U)
19225 
19226 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
19227 /*! @{ */
19228 
19229 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
19230 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
19231 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
19232  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
19233  *    appears on the CAN bus.
19234  */
19235 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
19236 
19237 #define CAN_CS_DLC_MASK                          (0xF0000U)
19238 #define CAN_CS_DLC_SHIFT                         (16U)
19239 /*! DLC - Length of the data to be stored/transmitted.
19240  */
19241 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
19242 
19243 #define CAN_CS_RTR_MASK                          (0x100000U)
19244 #define CAN_CS_RTR_SHIFT                         (20U)
19245 /*! RTR - Remote Transmission Request. One/zero for remote/data frame.
19246  */
19247 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
19248 
19249 #define CAN_CS_IDE_MASK                          (0x200000U)
19250 #define CAN_CS_IDE_SHIFT                         (21U)
19251 /*! IDE - ID Extended. One/zero for extended/standard format frame.
19252  */
19253 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
19254 
19255 #define CAN_CS_SRR_MASK                          (0x400000U)
19256 #define CAN_CS_SRR_SHIFT                         (22U)
19257 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
19258  */
19259 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
19260 
19261 #define CAN_CS_CODE_MASK                         (0xF000000U)
19262 #define CAN_CS_CODE_SHIFT                        (24U)
19263 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
19264  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
19265  */
19266 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
19267 
19268 #define CAN_CS_ESI_MASK                          (0x20000000U)
19269 #define CAN_CS_ESI_SHIFT                         (29U)
19270 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
19271  */
19272 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19273 
19274 #define CAN_CS_BRS_MASK                          (0x40000000U)
19275 #define CAN_CS_BRS_SHIFT                         (30U)
19276 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
19277  */
19278 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19279 
19280 #define CAN_CS_EDL_MASK                          (0x80000000U)
19281 #define CAN_CS_EDL_SHIFT                         (31U)
19282 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
19283  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
19284  */
19285 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19286 /*! @} */
19287 
19288 /* The count of CAN_CS */
19289 #define CAN_CS_COUNT_MB64B_L                     (7U)
19290 
19291 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
19292 /*! @{ */
19293 
19294 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
19295 #define CAN_ID_EXT_SHIFT                         (0U)
19296 /*! EXT - Contains extended (LOW word) identifier of message buffer.
19297  */
19298 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19299 
19300 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
19301 #define CAN_ID_STD_SHIFT                         (18U)
19302 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
19303  */
19304 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19305 
19306 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
19307 #define CAN_ID_PRIO_SHIFT                        (29U)
19308 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
19309  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
19310  *    ID to define the transmission priority.
19311  */
19312 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19313 /*! @} */
19314 
19315 /* The count of CAN_ID */
19316 #define CAN_ID_COUNT_MB64B_L                     (7U)
19317 
19318 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
19319 /*! @{ */
19320 
19321 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
19322 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
19323 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
19324  */
19325 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19326 
19327 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
19328 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
19329 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
19330  */
19331 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19332 
19333 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
19334 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
19335 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
19336  */
19337 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19338 
19339 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
19340 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
19341 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
19342  */
19343 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19344 
19345 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
19346 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
19347 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
19348  */
19349 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19350 
19351 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
19352 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
19353 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
19354  */
19355 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19356 
19357 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
19358 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
19359 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
19360  */
19361 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19362 
19363 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
19364 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
19365 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
19366  */
19367 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19368 
19369 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
19370 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
19371 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
19372  */
19373 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19374 
19375 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
19376 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
19377 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
19378  */
19379 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19380 
19381 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
19382 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
19383 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
19384  */
19385 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19386 
19387 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
19388 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
19389 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
19390  */
19391 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19392 
19393 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
19394 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
19395 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
19396  */
19397 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19398 
19399 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
19400 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
19401 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
19402  */
19403 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19404 
19405 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
19406 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
19407 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
19408  */
19409 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19410 
19411 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
19412 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
19413 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
19414  */
19415 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19416 
19417 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
19418 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
19419 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
19420  */
19421 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19422 
19423 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
19424 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
19425 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
19426  */
19427 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19428 
19429 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
19430 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
19431 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
19432  */
19433 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19434 
19435 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
19436 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
19437 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
19438  */
19439 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19440 
19441 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
19442 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
19443 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
19444  */
19445 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19446 
19447 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
19448 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
19449 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
19450  */
19451 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19452 
19453 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
19454 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
19455 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
19456  */
19457 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19458 
19459 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
19460 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
19461 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
19462  */
19463 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19464 
19465 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
19466 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
19467 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
19468  */
19469 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19470 
19471 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
19472 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
19473 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
19474  */
19475 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19476 
19477 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
19478 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
19479 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
19480  */
19481 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19482 
19483 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
19484 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
19485 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
19486  */
19487 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19488 
19489 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
19490 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
19491 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
19492  */
19493 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19494 
19495 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
19496 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
19497 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
19498  */
19499 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19500 
19501 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
19502 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
19503 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
19504  */
19505 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19506 
19507 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
19508 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
19509 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
19510  */
19511 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19512 
19513 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
19514 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
19515 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
19516  */
19517 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19518 
19519 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
19520 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
19521 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
19522  */
19523 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19524 
19525 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
19526 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
19527 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
19528  */
19529 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19530 
19531 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
19532 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
19533 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
19534  */
19535 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19536 
19537 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
19538 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
19539 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
19540  */
19541 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19542 
19543 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
19544 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
19545 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
19546  */
19547 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19548 
19549 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
19550 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
19551 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
19552  */
19553 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19554 
19555 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
19556 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
19557 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
19558  */
19559 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19560 
19561 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
19562 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
19563 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
19564  */
19565 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19566 
19567 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
19568 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
19569 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
19570  */
19571 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19572 
19573 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
19574 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
19575 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
19576  */
19577 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19578 
19579 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
19580 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
19581 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
19582  */
19583 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19584 
19585 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
19586 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
19587 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
19588  */
19589 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19590 
19591 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
19592 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
19593 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
19594  */
19595 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19596 
19597 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
19598 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
19599 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
19600  */
19601 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19602 
19603 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
19604 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
19605 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
19606  */
19607 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19608 
19609 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
19610 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
19611 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
19612  */
19613 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19614 
19615 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
19616 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
19617 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
19618  */
19619 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19620 
19621 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
19622 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
19623 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
19624  */
19625 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19626 
19627 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
19628 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
19629 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
19630  */
19631 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19632 
19633 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
19634 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
19635 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
19636  */
19637 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19638 
19639 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
19640 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
19641 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
19642  */
19643 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19644 
19645 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
19646 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
19647 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
19648  */
19649 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19650 
19651 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
19652 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
19653 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
19654  */
19655 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19656 
19657 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
19658 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
19659 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
19660  */
19661 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19662 
19663 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
19664 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
19665 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
19666  */
19667 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19668 
19669 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
19670 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
19671 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
19672  */
19673 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19674 
19675 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
19676 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
19677 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
19678  */
19679 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19680 
19681 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
19682 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
19683 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
19684  */
19685 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19686 
19687 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
19688 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
19689 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
19690  */
19691 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19692 
19693 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
19694 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
19695 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
19696  */
19697 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19698 
19699 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
19700 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
19701 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
19702  */
19703 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19704 /*! @} */
19705 
19706 /* The count of CAN_WORD */
19707 #define CAN_WORD_COUNT_MB64B_L                   (7U)
19708 
19709 /* The count of CAN_WORD */
19710 #define CAN_WORD_COUNT_MB64B_L2                  (16U)
19711 
19712 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
19713 /*! @{ */
19714 
19715 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
19716 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
19717 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
19718  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
19719  *    appears on the CAN bus.
19720  */
19721 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
19722 
19723 #define CAN_CS_DLC_MASK                          (0xF0000U)
19724 #define CAN_CS_DLC_SHIFT                         (16U)
19725 /*! DLC - Length of the data to be stored/transmitted.
19726  */
19727 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
19728 
19729 #define CAN_CS_RTR_MASK                          (0x100000U)
19730 #define CAN_CS_RTR_SHIFT                         (20U)
19731 /*! RTR - Remote Transmission Request. One/zero for remote/data frame.
19732  */
19733 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
19734 
19735 #define CAN_CS_IDE_MASK                          (0x200000U)
19736 #define CAN_CS_IDE_SHIFT                         (21U)
19737 /*! IDE - ID Extended. One/zero for extended/standard format frame.
19738  */
19739 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
19740 
19741 #define CAN_CS_SRR_MASK                          (0x400000U)
19742 #define CAN_CS_SRR_SHIFT                         (22U)
19743 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
19744  */
19745 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
19746 
19747 #define CAN_CS_CODE_MASK                         (0xF000000U)
19748 #define CAN_CS_CODE_SHIFT                        (24U)
19749 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
19750  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
19751  */
19752 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
19753 
19754 #define CAN_CS_ESI_MASK                          (0x20000000U)
19755 #define CAN_CS_ESI_SHIFT                         (29U)
19756 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
19757  */
19758 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19759 
19760 #define CAN_CS_BRS_MASK                          (0x40000000U)
19761 #define CAN_CS_BRS_SHIFT                         (30U)
19762 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
19763  */
19764 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19765 
19766 #define CAN_CS_EDL_MASK                          (0x80000000U)
19767 #define CAN_CS_EDL_SHIFT                         (31U)
19768 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
19769  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
19770  */
19771 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19772 /*! @} */
19773 
19774 /* The count of CAN_CS */
19775 #define CAN_CS_COUNT_MB64B_H                     (7U)
19776 
19777 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
19778 /*! @{ */
19779 
19780 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
19781 #define CAN_ID_EXT_SHIFT                         (0U)
19782 /*! EXT - Contains extended (LOW word) identifier of message buffer.
19783  */
19784 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19785 
19786 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
19787 #define CAN_ID_STD_SHIFT                         (18U)
19788 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
19789  */
19790 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19791 
19792 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
19793 #define CAN_ID_PRIO_SHIFT                        (29U)
19794 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
19795  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
19796  *    ID to define the transmission priority.
19797  */
19798 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19799 /*! @} */
19800 
19801 /* The count of CAN_ID */
19802 #define CAN_ID_COUNT_MB64B_H                     (7U)
19803 
19804 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
19805 /*! @{ */
19806 
19807 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
19808 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
19809 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
19810  */
19811 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19812 
19813 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
19814 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
19815 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
19816  */
19817 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19818 
19819 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
19820 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
19821 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
19822  */
19823 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19824 
19825 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
19826 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
19827 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
19828  */
19829 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19830 
19831 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
19832 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
19833 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
19834  */
19835 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19836 
19837 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
19838 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
19839 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
19840  */
19841 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19842 
19843 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
19844 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
19845 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
19846  */
19847 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19848 
19849 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
19850 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
19851 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
19852  */
19853 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19854 
19855 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
19856 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
19857 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
19858  */
19859 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19860 
19861 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
19862 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
19863 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
19864  */
19865 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19866 
19867 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
19868 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
19869 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
19870  */
19871 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19872 
19873 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
19874 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
19875 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
19876  */
19877 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19878 
19879 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
19880 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
19881 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
19882  */
19883 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19884 
19885 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
19886 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
19887 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
19888  */
19889 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19890 
19891 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
19892 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
19893 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
19894  */
19895 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19896 
19897 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
19898 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
19899 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
19900  */
19901 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19902 
19903 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
19904 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
19905 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
19906  */
19907 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19908 
19909 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
19910 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
19911 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
19912  */
19913 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19914 
19915 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
19916 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
19917 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
19918  */
19919 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19920 
19921 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
19922 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
19923 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
19924  */
19925 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19926 
19927 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
19928 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
19929 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
19930  */
19931 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19932 
19933 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
19934 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
19935 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
19936  */
19937 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19938 
19939 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
19940 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
19941 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
19942  */
19943 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19944 
19945 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
19946 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
19947 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
19948  */
19949 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19950 
19951 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
19952 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
19953 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
19954  */
19955 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19956 
19957 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
19958 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
19959 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
19960  */
19961 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19962 
19963 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
19964 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
19965 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
19966  */
19967 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19968 
19969 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
19970 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
19971 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
19972  */
19973 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19974 
19975 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
19976 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
19977 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
19978  */
19979 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19980 
19981 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
19982 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
19983 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
19984  */
19985 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19986 
19987 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
19988 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
19989 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
19990  */
19991 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19992 
19993 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
19994 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
19995 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
19996  */
19997 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19998 
19999 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
20000 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
20001 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
20002  */
20003 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
20004 
20005 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
20006 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
20007 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
20008  */
20009 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
20010 
20011 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
20012 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
20013 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
20014  */
20015 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
20016 
20017 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
20018 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
20019 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
20020  */
20021 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
20022 
20023 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
20024 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
20025 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
20026  */
20027 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
20028 
20029 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
20030 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
20031 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
20032  */
20033 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
20034 
20035 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
20036 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
20037 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
20038  */
20039 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
20040 
20041 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
20042 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
20043 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
20044  */
20045 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
20046 
20047 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
20048 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
20049 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
20050  */
20051 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
20052 
20053 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
20054 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
20055 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
20056  */
20057 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
20058 
20059 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
20060 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
20061 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
20062  */
20063 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
20064 
20065 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
20066 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
20067 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
20068  */
20069 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
20070 
20071 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
20072 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
20073 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
20074  */
20075 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
20076 
20077 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
20078 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
20079 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
20080  */
20081 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
20082 
20083 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
20084 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
20085 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
20086  */
20087 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
20088 
20089 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
20090 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
20091 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
20092  */
20093 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
20094 
20095 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
20096 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
20097 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
20098  */
20099 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
20100 
20101 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
20102 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
20103 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
20104  */
20105 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
20106 
20107 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
20108 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
20109 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
20110  */
20111 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
20112 
20113 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
20114 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
20115 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
20116  */
20117 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
20118 
20119 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
20120 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
20121 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
20122  */
20123 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
20124 
20125 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
20126 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
20127 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
20128  */
20129 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
20130 
20131 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
20132 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
20133 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
20134  */
20135 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
20136 
20137 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
20138 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
20139 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
20140  */
20141 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
20142 
20143 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
20144 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
20145 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
20146  */
20147 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
20148 
20149 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
20150 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
20151 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
20152  */
20153 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
20154 
20155 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
20156 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
20157 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
20158  */
20159 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
20160 
20161 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
20162 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
20163 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
20164  */
20165 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
20166 
20167 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
20168 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
20169 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
20170  */
20171 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
20172 
20173 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
20174 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
20175 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
20176  */
20177 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
20178 
20179 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
20180 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
20181 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
20182  */
20183 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
20184 
20185 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
20186 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
20187 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
20188  */
20189 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
20190 /*! @} */
20191 
20192 /* The count of CAN_WORD */
20193 #define CAN_WORD_COUNT_MB64B_H                   (7U)
20194 
20195 /* The count of CAN_WORD */
20196 #define CAN_WORD_COUNT_MB64B_H2                  (16U)
20197 
20198 /* The count of CAN_CS */
20199 #define CAN_CS_COUNT                             (64U)
20200 
20201 /* The count of CAN_ID */
20202 #define CAN_ID_COUNT                             (64U)
20203 
20204 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
20205 /*! @{ */
20206 
20207 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
20208 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
20209 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
20210  */
20211 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
20212 
20213 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
20214 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
20215 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
20216  */
20217 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
20218 
20219 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
20220 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
20221 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
20222  */
20223 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
20224 
20225 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
20226 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
20227 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
20228  */
20229 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
20230 /*! @} */
20231 
20232 /* The count of CAN_WORD0 */
20233 #define CAN_WORD0_COUNT                          (64U)
20234 
20235 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
20236 /*! @{ */
20237 
20238 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
20239 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
20240 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
20241  */
20242 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
20243 
20244 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
20245 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
20246 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
20247  */
20248 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
20249 
20250 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
20251 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
20252 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
20253  */
20254 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
20255 
20256 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
20257 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
20258 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
20259  */
20260 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
20261 /*! @} */
20262 
20263 /* The count of CAN_WORD1 */
20264 #define CAN_WORD1_COUNT                          (64U)
20265 
20266 /*! @name RXIMR - Rx Individual Mask registers */
20267 /*! @{ */
20268 
20269 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
20270 #define CAN_RXIMR_MI_SHIFT                       (0U)
20271 /*! MI - Individual Mask Bits
20272  */
20273 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
20274 /*! @} */
20275 
20276 /* The count of CAN_RXIMR */
20277 #define CAN_RXIMR_COUNT                          (64U)
20278 
20279 /*! @name MECR - Memory Error Control register */
20280 /*! @{ */
20281 
20282 #define CAN_MECR_NCEFAFRZ_MASK                   (0x80U)
20283 #define CAN_MECR_NCEFAFRZ_SHIFT                  (7U)
20284 /*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
20285  *  0b0..Keep normal operation.
20286  *  0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
20287  */
20288 #define CAN_MECR_NCEFAFRZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
20289 
20290 #define CAN_MECR_ECCDIS_MASK                     (0x100U)
20291 #define CAN_MECR_ECCDIS_SHIFT                    (8U)
20292 /*! ECCDIS - Error Correction Disable
20293  *  0b0..Enable memory error correction.
20294  *  0b1..Disable memory error correction.
20295  */
20296 #define CAN_MECR_ECCDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
20297 
20298 #define CAN_MECR_RERRDIS_MASK                    (0x200U)
20299 #define CAN_MECR_RERRDIS_SHIFT                   (9U)
20300 /*! RERRDIS - Error Report Disable
20301  *  0b0..Enable updates of the error report registers.
20302  *  0b1..Disable updates of the error report registers.
20303  */
20304 #define CAN_MECR_RERRDIS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
20305 
20306 #define CAN_MECR_EXTERRIE_MASK                   (0x2000U)
20307 #define CAN_MECR_EXTERRIE_SHIFT                  (13U)
20308 /*! EXTERRIE - Extended Error Injection Enable
20309  *  0b0..Error injection is applied only to the 32-bit word.
20310  *  0b1..Error injection is applied to the 64-bit word.
20311  */
20312 #define CAN_MECR_EXTERRIE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
20313 
20314 #define CAN_MECR_FAERRIE_MASK                    (0x4000U)
20315 #define CAN_MECR_FAERRIE_SHIFT                   (14U)
20316 /*! FAERRIE - FlexCAN Access Error Injection Enable
20317  *  0b0..Injection is disabled.
20318  *  0b1..Injection is enabled.
20319  */
20320 #define CAN_MECR_FAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
20321 
20322 #define CAN_MECR_HAERRIE_MASK                    (0x8000U)
20323 #define CAN_MECR_HAERRIE_SHIFT                   (15U)
20324 /*! HAERRIE - Host Access Error Injection Enable
20325  *  0b0..Injection is disabled.
20326  *  0b1..Injection is enabled.
20327  */
20328 #define CAN_MECR_HAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
20329 
20330 #define CAN_MECR_CEI_MSK_MASK                    (0x10000U)
20331 #define CAN_MECR_CEI_MSK_SHIFT                   (16U)
20332 /*! CEI_MSK - Correctable Errors Interrupt Mask
20333  *  0b0..Interrupt is disabled.
20334  *  0b1..Interrupt is enabled.
20335  */
20336 #define CAN_MECR_CEI_MSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
20337 
20338 #define CAN_MECR_FANCEI_MSK_MASK                 (0x40000U)
20339 #define CAN_MECR_FANCEI_MSK_SHIFT                (18U)
20340 /*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
20341  *  0b0..Interrupt is disabled.
20342  *  0b1..Interrupt is enabled.
20343  */
20344 #define CAN_MECR_FANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
20345 
20346 #define CAN_MECR_HANCEI_MSK_MASK                 (0x80000U)
20347 #define CAN_MECR_HANCEI_MSK_SHIFT                (19U)
20348 /*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
20349  *  0b0..Interrupt is disabled.
20350  *  0b1..Interrupt is enabled.
20351  */
20352 #define CAN_MECR_HANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
20353 
20354 #define CAN_MECR_ECRWRDIS_MASK                   (0x80000000U)
20355 #define CAN_MECR_ECRWRDIS_SHIFT                  (31U)
20356 /*! ECRWRDIS - Error Configuration Register Write Disable
20357  *  0b0..Write is enabled.
20358  *  0b1..Write is disabled.
20359  */
20360 #define CAN_MECR_ECRWRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
20361 /*! @} */
20362 
20363 /*! @name ERRIAR - Error Injection Address register */
20364 /*! @{ */
20365 
20366 #define CAN_ERRIAR_INJADDR_L_MASK                (0x3U)
20367 #define CAN_ERRIAR_INJADDR_L_SHIFT               (0U)
20368 /*! INJADDR_L - Error Injection Address Low
20369  */
20370 #define CAN_ERRIAR_INJADDR_L(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
20371 
20372 #define CAN_ERRIAR_INJADDR_H_MASK                (0x3FFCU)
20373 #define CAN_ERRIAR_INJADDR_H_SHIFT               (2U)
20374 /*! INJADDR_H - Error Injection Address High
20375  */
20376 #define CAN_ERRIAR_INJADDR_H(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
20377 /*! @} */
20378 
20379 /*! @name ERRIDPR - Error Injection Data Pattern register */
20380 /*! @{ */
20381 
20382 #define CAN_ERRIDPR_DFLIP_MASK                   (0xFFFFFFFFU)
20383 #define CAN_ERRIDPR_DFLIP_SHIFT                  (0U)
20384 /*! DFLIP - Data flip pattern
20385  */
20386 #define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
20387 /*! @} */
20388 
20389 /*! @name ERRIPPR - Error Injection Parity Pattern register */
20390 /*! @{ */
20391 
20392 #define CAN_ERRIPPR_PFLIP0_MASK                  (0x1FU)
20393 #define CAN_ERRIPPR_PFLIP0_SHIFT                 (0U)
20394 /*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)
20395  */
20396 #define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
20397 
20398 #define CAN_ERRIPPR_PFLIP1_MASK                  (0x1F00U)
20399 #define CAN_ERRIPPR_PFLIP1_SHIFT                 (8U)
20400 /*! PFLIP1 - Parity Flip Pattern For Byte 1
20401  */
20402 #define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
20403 
20404 #define CAN_ERRIPPR_PFLIP2_MASK                  (0x1F0000U)
20405 #define CAN_ERRIPPR_PFLIP2_SHIFT                 (16U)
20406 /*! PFLIP2 - Parity Flip Pattern For Byte 2
20407  */
20408 #define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
20409 
20410 #define CAN_ERRIPPR_PFLIP3_MASK                  (0x1F000000U)
20411 #define CAN_ERRIPPR_PFLIP3_SHIFT                 (24U)
20412 /*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)
20413  */
20414 #define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
20415 /*! @} */
20416 
20417 /*! @name RERRAR - Error Report Address register */
20418 /*! @{ */
20419 
20420 #define CAN_RERRAR_ERRADDR_MASK                  (0x3FFFU)
20421 #define CAN_RERRAR_ERRADDR_SHIFT                 (0U)
20422 /*! ERRADDR - Address Where Error Detected
20423  */
20424 #define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
20425 
20426 #define CAN_RERRAR_SAID_MASK                     (0x70000U)
20427 #define CAN_RERRAR_SAID_SHIFT                    (16U)
20428 /*! SAID - SAID
20429  */
20430 #define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
20431 
20432 #define CAN_RERRAR_NCE_MASK                      (0x1000000U)
20433 #define CAN_RERRAR_NCE_SHIFT                     (24U)
20434 /*! NCE - Non-Correctable Error
20435  *  0b0..Reporting a correctable error
20436  *  0b1..Reporting a non-correctable error
20437  */
20438 #define CAN_RERRAR_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
20439 /*! @} */
20440 
20441 /*! @name RERRDR - Error Report Data register */
20442 /*! @{ */
20443 
20444 #define CAN_RERRDR_RDATA_MASK                    (0xFFFFFFFFU)
20445 #define CAN_RERRDR_RDATA_SHIFT                   (0U)
20446 /*! RDATA - Raw data word read from memory with error
20447  */
20448 #define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
20449 /*! @} */
20450 
20451 /*! @name RERRSYNR - Error Report Syndrome register */
20452 /*! @{ */
20453 
20454 #define CAN_RERRSYNR_SYND0_MASK                  (0x1FU)
20455 #define CAN_RERRSYNR_SYND0_SHIFT                 (0U)
20456 /*! SYND0 - Error Syndrome For Byte 0 (least significant)
20457  */
20458 #define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
20459 
20460 #define CAN_RERRSYNR_BE0_MASK                    (0x80U)
20461 #define CAN_RERRSYNR_BE0_SHIFT                   (7U)
20462 /*! BE0 - Byte Enabled For Byte 0 (least significant)
20463  *  0b0..The byte was not read.
20464  *  0b1..The byte was read.
20465  */
20466 #define CAN_RERRSYNR_BE0(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
20467 
20468 #define CAN_RERRSYNR_SYND1_MASK                  (0x1F00U)
20469 #define CAN_RERRSYNR_SYND1_SHIFT                 (8U)
20470 /*! SYND1 - Error Syndrome for Byte 1
20471  */
20472 #define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
20473 
20474 #define CAN_RERRSYNR_BE1_MASK                    (0x8000U)
20475 #define CAN_RERRSYNR_BE1_SHIFT                   (15U)
20476 /*! BE1 - Byte Enabled For Byte 1
20477  *  0b0..The byte was not read.
20478  *  0b1..The byte was read.
20479  */
20480 #define CAN_RERRSYNR_BE1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
20481 
20482 #define CAN_RERRSYNR_SYND2_MASK                  (0x1F0000U)
20483 #define CAN_RERRSYNR_SYND2_SHIFT                 (16U)
20484 /*! SYND2 - Error Syndrome For Byte 2
20485  */
20486 #define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
20487 
20488 #define CAN_RERRSYNR_BE2_MASK                    (0x800000U)
20489 #define CAN_RERRSYNR_BE2_SHIFT                   (23U)
20490 /*! BE2 - Byte Enabled For Byte 2
20491  *  0b0..The byte was not read.
20492  *  0b1..The byte was read.
20493  */
20494 #define CAN_RERRSYNR_BE2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
20495 
20496 #define CAN_RERRSYNR_SYND3_MASK                  (0x1F000000U)
20497 #define CAN_RERRSYNR_SYND3_SHIFT                 (24U)
20498 /*! SYND3 - Error Syndrome For Byte 3 (most significant)
20499  */
20500 #define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
20501 
20502 #define CAN_RERRSYNR_BE3_MASK                    (0x80000000U)
20503 #define CAN_RERRSYNR_BE3_SHIFT                   (31U)
20504 /*! BE3 - Byte Enabled For Byte 3 (most significant)
20505  *  0b0..The byte was not read.
20506  *  0b1..The byte was read.
20507  */
20508 #define CAN_RERRSYNR_BE3(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
20509 /*! @} */
20510 
20511 /*! @name ERRSR - Error Status register */
20512 /*! @{ */
20513 
20514 #define CAN_ERRSR_CEIOF_MASK                     (0x1U)
20515 #define CAN_ERRSR_CEIOF_SHIFT                    (0U)
20516 /*! CEIOF - Correctable Error Interrupt Overrun Flag
20517  *  0b0..No overrun on correctable errors
20518  *  0b1..Overrun on correctable errors
20519  */
20520 #define CAN_ERRSR_CEIOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
20521 
20522 #define CAN_ERRSR_FANCEIOF_MASK                  (0x4U)
20523 #define CAN_ERRSR_FANCEIOF_SHIFT                 (2U)
20524 /*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
20525  *  0b0..No overrun on non-correctable errors in FlexCAN access
20526  *  0b1..Overrun on non-correctable errors in FlexCAN access
20527  */
20528 #define CAN_ERRSR_FANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
20529 
20530 #define CAN_ERRSR_HANCEIOF_MASK                  (0x8U)
20531 #define CAN_ERRSR_HANCEIOF_SHIFT                 (3U)
20532 /*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
20533  *  0b0..No overrun on non-correctable errors in host access
20534  *  0b1..Overrun on non-correctable errors in host access
20535  */
20536 #define CAN_ERRSR_HANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
20537 
20538 #define CAN_ERRSR_CEIF_MASK                      (0x10000U)
20539 #define CAN_ERRSR_CEIF_SHIFT                     (16U)
20540 /*! CEIF - Correctable Error Interrupt Flag
20541  *  0b0..No correctable errors were detected so far.
20542  *  0b1..A correctable error was detected.
20543  */
20544 #define CAN_ERRSR_CEIF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
20545 
20546 #define CAN_ERRSR_FANCEIF_MASK                   (0x40000U)
20547 #define CAN_ERRSR_FANCEIF_SHIFT                  (18U)
20548 /*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
20549  *  0b0..No non-correctable errors were detected in FlexCAN accesses so far.
20550  *  0b1..A non-correctable error was detected in a FlexCAN access.
20551  */
20552 #define CAN_ERRSR_FANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
20553 
20554 #define CAN_ERRSR_HANCEIF_MASK                   (0x80000U)
20555 #define CAN_ERRSR_HANCEIF_SHIFT                  (19U)
20556 /*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
20557  *  0b0..No non-correctable errors were detected in host accesses so far.
20558  *  0b1..A non-correctable error was detected in a host access.
20559  */
20560 #define CAN_ERRSR_HANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
20561 /*! @} */
20562 
20563 /*! @name FDCTRL - CAN FD Control register */
20564 /*! @{ */
20565 
20566 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
20567 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
20568 /*! TDCVAL - Transceiver Delay Compensation Value
20569  */
20570 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
20571 
20572 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
20573 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
20574 /*! TDCOFF - Transceiver Delay Compensation Offset
20575  */
20576 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
20577 
20578 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
20579 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
20580 /*! TDCFAIL - Transceiver Delay Compensation Fail
20581  *  0b0..Measured loop delay is in range.
20582  *  0b1..Measured loop delay is out of range.
20583  */
20584 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
20585 
20586 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
20587 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
20588 /*! TDCEN - Transceiver Delay Compensation Enable
20589  *  0b0..TDC is disabled
20590  *  0b1..TDC is enabled
20591  */
20592 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
20593 
20594 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
20595 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
20596 /*! MBDSR0 - Message Buffer Data Size for Region 0
20597  *  0b00..Selects 8 bytes per message buffer.
20598  *  0b01..Selects 16 bytes per message buffer.
20599  *  0b10..Selects 32 bytes per message buffer.
20600  *  0b11..Selects 64 bytes per message buffer.
20601  */
20602 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
20603 
20604 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
20605 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
20606 /*! MBDSR1 - Message Buffer Data Size for Region 1
20607  *  0b00..Selects 8 bytes per message buffer.
20608  *  0b01..Selects 16 bytes per message buffer.
20609  *  0b10..Selects 32 bytes per message buffer.
20610  *  0b11..Selects 64 bytes per message buffer.
20611  */
20612 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
20613 
20614 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
20615 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
20616 /*! FDRATE - Bit Rate Switch Enable
20617  *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
20618  *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
20619  */
20620 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
20621 /*! @} */
20622 
20623 /*! @name FDCBT - CAN FD Bit Timing register */
20624 /*! @{ */
20625 
20626 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
20627 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
20628 /*! FPSEG2 - Fast Phase Segment 2
20629  */
20630 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
20631 
20632 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
20633 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
20634 /*! FPSEG1 - Fast Phase Segment 1
20635  */
20636 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
20637 
20638 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
20639 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
20640 /*! FPROPSEG - Fast Propagation Segment
20641  */
20642 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
20643 
20644 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
20645 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
20646 /*! FRJW - Fast Resync Jump Width
20647  */
20648 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
20649 
20650 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
20651 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
20652 /*! FPRESDIV - Fast Prescaler Division Factor
20653  */
20654 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
20655 /*! @} */
20656 
20657 /*! @name FDCRC - CAN FD CRC register */
20658 /*! @{ */
20659 
20660 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
20661 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
20662 /*! FD_TXCRC - Extended Transmitted CRC value
20663  */
20664 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
20665 
20666 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
20667 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
20668 /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
20669  */
20670 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
20671 /*! @} */
20672 
20673 
20674 /*!
20675  * @}
20676  */ /* end of group CAN_Register_Masks */
20677 
20678 
20679 /* CAN - Peripheral instance base addresses */
20680 /** Peripheral CAN1 base address */
20681 #define CAN1_BASE                                (0x400C4000u)
20682 /** Peripheral CAN1 base pointer */
20683 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
20684 /** Peripheral CAN2 base address */
20685 #define CAN2_BASE                                (0x400C8000u)
20686 /** Peripheral CAN2 base pointer */
20687 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
20688 /** Peripheral CAN3 base address */
20689 #define CAN3_BASE                                (0x40C3C000u)
20690 /** Peripheral CAN3 base pointer */
20691 #define CAN3                                     ((CAN_Type *)CAN3_BASE)
20692 /** Array initializer of CAN peripheral base addresses */
20693 #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
20694 /** Array initializer of CAN peripheral base pointers */
20695 #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
20696 /** Interrupt vectors for the CAN peripheral type */
20697 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20698 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20699 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20700 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20701 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20702 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20703 
20704 /*!
20705  * @}
20706  */ /* end of group CAN_Peripheral_Access_Layer */
20707 
20708 
20709 /* ----------------------------------------------------------------------------
20710    -- CAN_WRAPPER Peripheral Access Layer
20711    ---------------------------------------------------------------------------- */
20712 
20713 /*!
20714  * @addtogroup CAN_WRAPPER_Peripheral_Access_Layer CAN_WRAPPER Peripheral Access Layer
20715  * @{
20716  */
20717 
20718 /** CAN_WRAPPER - Register Layout Typedef */
20719 typedef struct {
20720        uint8_t RESERVED_0[2528];
20721   __IO uint32_t GFWR;                              /**< Glitch Filter Width Register, offset: 0x9E0 */
20722 } CAN_WRAPPER_Type;
20723 
20724 /* ----------------------------------------------------------------------------
20725    -- CAN_WRAPPER Register Masks
20726    ---------------------------------------------------------------------------- */
20727 
20728 /*!
20729  * @addtogroup CAN_WRAPPER_Register_Masks CAN_WRAPPER Register Masks
20730  * @{
20731  */
20732 
20733 /*! @name GFWR - Glitch Filter Width Register */
20734 /*! @{ */
20735 
20736 #define CAN_WRAPPER_GFWR_GFWR_MASK               (0xFFU)
20737 #define CAN_WRAPPER_GFWR_GFWR_SHIFT              (0U)
20738 /*! GFWR - Glitch Filter Width
20739  */
20740 #define CAN_WRAPPER_GFWR_GFWR(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK)
20741 /*! @} */
20742 
20743 
20744 /*!
20745  * @}
20746  */ /* end of group CAN_WRAPPER_Register_Masks */
20747 
20748 
20749 /* CAN_WRAPPER - Peripheral instance base addresses */
20750 /** Peripheral CAN1_WRAPPER base address */
20751 #define CAN1_WRAPPER_BASE                        (0x400C4000u)
20752 /** Peripheral CAN1_WRAPPER base pointer */
20753 #define CAN1_WRAPPER                             ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
20754 /** Peripheral CAN2_WRAPPER base address */
20755 #define CAN2_WRAPPER_BASE                        (0x400C8000u)
20756 /** Peripheral CAN2_WRAPPER base pointer */
20757 #define CAN2_WRAPPER                             ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
20758 /** Peripheral CAN3_WRAPPER base address */
20759 #define CAN3_WRAPPER_BASE                        (0x40C3C000u)
20760 /** Peripheral CAN3_WRAPPER base pointer */
20761 #define CAN3_WRAPPER                             ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
20762 /** Array initializer of CAN_WRAPPER peripheral base addresses */
20763 #define CAN_WRAPPER_BASE_ADDRS                   { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
20764 /** Array initializer of CAN_WRAPPER peripheral base pointers */
20765 #define CAN_WRAPPER_BASE_PTRS                    { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
20766 
20767 /*!
20768  * @}
20769  */ /* end of group CAN_WRAPPER_Peripheral_Access_Layer */
20770 
20771 
20772 /* ----------------------------------------------------------------------------
20773    -- CCM Peripheral Access Layer
20774    ---------------------------------------------------------------------------- */
20775 
20776 /*!
20777  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
20778  * @{
20779  */
20780 
20781 /** CCM - Register Layout Typedef */
20782 typedef struct {
20783   struct {                                         /* offset: 0x0, array step: 0x80 */
20784     __IO uint32_t CONTROL;                           /**< Clock root control, array offset: 0x0, array step: 0x80 */
20785     __IO uint32_t CONTROL_SET;                       /**< Clock root control, array offset: 0x4, array step: 0x80 */
20786     __IO uint32_t CONTROL_CLR;                       /**< Clock root control, array offset: 0x8, array step: 0x80 */
20787     __IO uint32_t CONTROL_TOG;                       /**< Clock root control, array offset: 0xC, array step: 0x80 */
20788          uint8_t RESERVED_0[16];
20789     __I  uint32_t STATUS0;                           /**< Clock root working status, array offset: 0x20, array step: 0x80 */
20790     __I  uint32_t STATUS1;                           /**< Clock root low power status, array offset: 0x24, array step: 0x80 */
20791          uint8_t RESERVED_1[4];
20792     __I  uint32_t CONFIG;                            /**< Clock root configuration, array offset: 0x2C, array step: 0x80 */
20793     __IO uint32_t AUTHEN;                            /**< Clock root access control, array offset: 0x30, array step: 0x80 */
20794     __IO uint32_t AUTHEN_SET;                        /**< Clock root access control, array offset: 0x34, array step: 0x80 */
20795     __IO uint32_t AUTHEN_CLR;                        /**< Clock root access control, array offset: 0x38, array step: 0x80 */
20796     __IO uint32_t AUTHEN_TOG;                        /**< Clock root access control, array offset: 0x3C, array step: 0x80 */
20797     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4 */
20798   } CLOCK_ROOT[79];
20799        uint8_t RESERVED_0[6272];
20800   struct {                                         /* offset: 0x4000, array step: 0x80 */
20801     __IO uint32_t CONTROL;                           /**< Clock group control, array offset: 0x4000, array step: 0x80 */
20802     __IO uint32_t CONTROL_SET;                       /**< Clock group control, array offset: 0x4004, array step: 0x80 */
20803     __IO uint32_t CONTROL_CLR;                       /**< Clock group control, array offset: 0x4008, array step: 0x80 */
20804     __IO uint32_t CONTROL_TOG;                       /**< Clock group control, array offset: 0x400C, array step: 0x80 */
20805          uint8_t RESERVED_0[16];
20806     __IO uint32_t STATUS0;                           /**< Clock group working status, array offset: 0x4020, array step: 0x80 */
20807     __I  uint32_t STATUS1;                           /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */
20808          uint8_t RESERVED_1[4];
20809     __I  uint32_t CONFIG;                            /**< Clock group configuration, array offset: 0x402C, array step: 0x80 */
20810     __IO uint32_t AUTHEN;                            /**< Clock group access control, array offset: 0x4030, array step: 0x80 */
20811     __IO uint32_t AUTHEN_SET;                        /**< Clock group access control, array offset: 0x4034, array step: 0x80 */
20812     __IO uint32_t AUTHEN_CLR;                        /**< Clock group access control, array offset: 0x4038, array step: 0x80 */
20813     __IO uint32_t AUTHEN_TOG;                        /**< Clock group access control, array offset: 0x403C, array step: 0x80 */
20814     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4 */
20815   } CLOCK_GROUP[2];
20816        uint8_t RESERVED_1[1792];
20817   struct {                                         /* offset: 0x4800, array step: 0x20 */
20818     __IO uint32_t GPR_SHARED;                        /**< General Purpose Register, array offset: 0x4800, array step: 0x20 */
20819     __IO uint32_t SET;                               /**< General Purpose Register, array offset: 0x4804, array step: 0x20 */
20820     __IO uint32_t CLR;                               /**< General Purpose Register, array offset: 0x4808, array step: 0x20 */
20821     __IO uint32_t TOG;                               /**< General Purpose Register, array offset: 0x480C, array step: 0x20 */
20822     __IO uint32_t AUTHEN;                            /**< GPR access control, array offset: 0x4810, array step: 0x20 */
20823     __IO uint32_t AUTHEN_SET;                        /**< GPR access control, array offset: 0x4814, array step: 0x20 */
20824     __IO uint32_t AUTHEN_CLR;                        /**< GPR access control, array offset: 0x4818, array step: 0x20 */
20825     __IO uint32_t AUTHEN_TOG;                        /**< GPR access control, array offset: 0x481C, array step: 0x20 */
20826   } GPR_SHARED[8];
20827        uint8_t RESERVED_2[800];
20828   __IO uint32_t GPR_PRIVATE1;                      /**< General Purpose Register, offset: 0x4C20 */
20829   __IO uint32_t GPR_PRIVATE1_SET;                  /**< General Purpose Register, offset: 0x4C24 */
20830   __IO uint32_t GPR_PRIVATE1_CLR;                  /**< General Purpose Register, offset: 0x4C28 */
20831   __IO uint32_t GPR_PRIVATE1_TOG;                  /**< General Purpose Register, offset: 0x4C2C */
20832   __IO uint32_t GPR_PRIVATE1_AUTHEN;               /**< GPR access control, offset: 0x4C30 */
20833   __IO uint32_t GPR_PRIVATE1_AUTHEN_SET;           /**< GPR access control, offset: 0x4C34 */
20834   __IO uint32_t GPR_PRIVATE1_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C38 */
20835   __IO uint32_t GPR_PRIVATE1_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C3C */
20836   __IO uint32_t GPR_PRIVATE2;                      /**< General Purpose Register, offset: 0x4C40 */
20837   __IO uint32_t GPR_PRIVATE2_SET;                  /**< General Purpose Register, offset: 0x4C44 */
20838   __IO uint32_t GPR_PRIVATE2_CLR;                  /**< General Purpose Register, offset: 0x4C48 */
20839   __IO uint32_t GPR_PRIVATE2_TOG;                  /**< General Purpose Register, offset: 0x4C4C */
20840   __IO uint32_t GPR_PRIVATE2_AUTHEN;               /**< GPR access control, offset: 0x4C50 */
20841   __IO uint32_t GPR_PRIVATE2_AUTHEN_SET;           /**< GPR access control, offset: 0x4C54 */
20842   __IO uint32_t GPR_PRIVATE2_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C58 */
20843   __IO uint32_t GPR_PRIVATE2_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C5C */
20844   __IO uint32_t GPR_PRIVATE3;                      /**< General Purpose Register, offset: 0x4C60 */
20845   __IO uint32_t GPR_PRIVATE3_SET;                  /**< General Purpose Register, offset: 0x4C64 */
20846   __IO uint32_t GPR_PRIVATE3_CLR;                  /**< General Purpose Register, offset: 0x4C68 */
20847   __IO uint32_t GPR_PRIVATE3_TOG;                  /**< General Purpose Register, offset: 0x4C6C */
20848   __IO uint32_t GPR_PRIVATE3_AUTHEN;               /**< GPR access control, offset: 0x4C70 */
20849   __IO uint32_t GPR_PRIVATE3_AUTHEN_SET;           /**< GPR access control, offset: 0x4C74 */
20850   __IO uint32_t GPR_PRIVATE3_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C78 */
20851   __IO uint32_t GPR_PRIVATE3_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C7C */
20852   __IO uint32_t GPR_PRIVATE4;                      /**< General Purpose Register, offset: 0x4C80 */
20853   __IO uint32_t GPR_PRIVATE4_SET;                  /**< General Purpose Register, offset: 0x4C84 */
20854   __IO uint32_t GPR_PRIVATE4_CLR;                  /**< General Purpose Register, offset: 0x4C88 */
20855   __IO uint32_t GPR_PRIVATE4_TOG;                  /**< General Purpose Register, offset: 0x4C8C */
20856   __IO uint32_t GPR_PRIVATE4_AUTHEN;               /**< GPR access control, offset: 0x4C90 */
20857   __IO uint32_t GPR_PRIVATE4_AUTHEN_SET;           /**< GPR access control, offset: 0x4C94 */
20858   __IO uint32_t GPR_PRIVATE4_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C98 */
20859   __IO uint32_t GPR_PRIVATE4_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C9C */
20860   __IO uint32_t GPR_PRIVATE5;                      /**< General Purpose Register, offset: 0x4CA0 */
20861   __IO uint32_t GPR_PRIVATE5_SET;                  /**< General Purpose Register, offset: 0x4CA4 */
20862   __IO uint32_t GPR_PRIVATE5_CLR;                  /**< General Purpose Register, offset: 0x4CA8 */
20863   __IO uint32_t GPR_PRIVATE5_TOG;                  /**< General Purpose Register, offset: 0x4CAC */
20864   __IO uint32_t GPR_PRIVATE5_AUTHEN;               /**< GPR access control, offset: 0x4CB0 */
20865   __IO uint32_t GPR_PRIVATE5_AUTHEN_SET;           /**< GPR access control, offset: 0x4CB4 */
20866   __IO uint32_t GPR_PRIVATE5_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CB8 */
20867   __IO uint32_t GPR_PRIVATE5_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CBC */
20868   __IO uint32_t GPR_PRIVATE6;                      /**< General Purpose Register, offset: 0x4CC0 */
20869   __IO uint32_t GPR_PRIVATE6_SET;                  /**< General Purpose Register, offset: 0x4CC4 */
20870   __IO uint32_t GPR_PRIVATE6_CLR;                  /**< General Purpose Register, offset: 0x4CC8 */
20871   __IO uint32_t GPR_PRIVATE6_TOG;                  /**< General Purpose Register, offset: 0x4CCC */
20872   __IO uint32_t GPR_PRIVATE6_AUTHEN;               /**< GPR access control, offset: 0x4CD0 */
20873   __IO uint32_t GPR_PRIVATE6_AUTHEN_SET;           /**< GPR access control, offset: 0x4CD4 */
20874   __IO uint32_t GPR_PRIVATE6_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CD8 */
20875   __IO uint32_t GPR_PRIVATE6_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CDC */
20876   __IO uint32_t GPR_PRIVATE7;                      /**< General Purpose Register, offset: 0x4CE0 */
20877   __IO uint32_t GPR_PRIVATE7_SET;                  /**< General Purpose Register, offset: 0x4CE4 */
20878   __IO uint32_t GPR_PRIVATE7_CLR;                  /**< General Purpose Register, offset: 0x4CE8 */
20879   __IO uint32_t GPR_PRIVATE7_TOG;                  /**< General Purpose Register, offset: 0x4CEC */
20880   __IO uint32_t GPR_PRIVATE7_AUTHEN;               /**< GPR access control, offset: 0x4CF0 */
20881   __IO uint32_t GPR_PRIVATE7_AUTHEN_SET;           /**< GPR access control, offset: 0x4CF4 */
20882   __IO uint32_t GPR_PRIVATE7_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CF8 */
20883   __IO uint32_t GPR_PRIVATE7_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CFC */
20884        uint8_t RESERVED_3[768];
20885   struct {                                         /* offset: 0x5000, array step: 0x20 */
20886     __IO uint32_t DIRECT;                            /**< Clock source direct control, array offset: 0x5000, array step: 0x20 */
20887     __IO uint32_t DOMAINr;                           /**< Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h */
20888     __IO uint32_t SETPOINT;                          /**< Clock source Setpoint setting, array offset: 0x5008, array step: 0x20 */
20889          uint8_t RESERVED_0[4];
20890     __I  uint32_t STATUS0;                           /**< Clock source working status, array offset: 0x5010, array step: 0x20 */
20891     __I  uint32_t STATUS1;                           /**< Clock source low power status, array offset: 0x5014, array step: 0x20 */
20892     __I  uint32_t CONFIG;                            /**< Clock source configuration, array offset: 0x5018, array step: 0x20 */
20893     __IO uint32_t AUTHEN;                            /**< Clock source access control, array offset: 0x501C, array step: 0x20 */
20894   } OSCPLL[29];
20895        uint8_t RESERVED_4[3168];
20896   struct {                                         /* offset: 0x6000, array step: 0x20 */
20897     __IO uint32_t DIRECT;                            /**< LPCG direct control, array offset: 0x6000, array step: 0x20 */
20898     __IO uint32_t DOMAINr;                           /**< LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h */
20899     __IO uint32_t SETPOINT;                          /**< LPCG Setpoint setting, array offset: 0x6008, array step: 0x20 */
20900          uint8_t RESERVED_0[4];
20901     __I  uint32_t STATUS0;                           /**< LPCG working status, array offset: 0x6010, array step: 0x20 */
20902     __I  uint32_t STATUS1;                           /**< LPCG low power status, array offset: 0x6014, array step: 0x20 */
20903     __I  uint32_t CONFIG;                            /**< LPCG configuration, array offset: 0x6018, array step: 0x20 */
20904     __IO uint32_t AUTHEN;                            /**< LPCG access control, array offset: 0x601C, array step: 0x20 */
20905   } LPCG[138];
20906 } CCM_Type;
20907 
20908 /* ----------------------------------------------------------------------------
20909    -- CCM Register Masks
20910    ---------------------------------------------------------------------------- */
20911 
20912 /*!
20913  * @addtogroup CCM_Register_Masks CCM Register Masks
20914  * @{
20915  */
20916 
20917 /*! @name CLOCK_ROOT_CONTROL - Clock root control */
20918 /*! @{ */
20919 
20920 #define CCM_CLOCK_ROOT_CONTROL_DIV_MASK          (0xFFU)
20921 #define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT         (0U)
20922 /*! DIV - Clock divider
20923  */
20924 #define CCM_CLOCK_ROOT_CONTROL_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
20925 
20926 #define CCM_CLOCK_ROOT_CONTROL_MUX_MASK          (0x700U)
20927 #define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT         (8U)
20928 /*! MUX - Clock multiplexer
20929  */
20930 #define CCM_CLOCK_ROOT_CONTROL_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
20931 
20932 #define CCM_CLOCK_ROOT_CONTROL_OFF_MASK          (0x1000000U)
20933 #define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT         (24U)
20934 /*! OFF - OFF
20935  *  0b0..Turn on clock
20936  *  0b1..Turn off clock
20937  */
20938 #define CCM_CLOCK_ROOT_CONTROL_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
20939 /*! @} */
20940 
20941 /* The count of CCM_CLOCK_ROOT_CONTROL */
20942 #define CCM_CLOCK_ROOT_CONTROL_COUNT             (79U)
20943 
20944 /*! @name CLOCK_ROOT_CONTROL_SET - Clock root control */
20945 /*! @{ */
20946 
20947 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK      (0xFFU)
20948 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT     (0U)
20949 /*! DIV - Clock divider
20950  */
20951 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
20952 
20953 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK      (0x700U)
20954 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT     (8U)
20955 /*! MUX - Clock multiplexer
20956  */
20957 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
20958 
20959 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK      (0x1000000U)
20960 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT     (24U)
20961 /*! OFF - OFF
20962  */
20963 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
20964 /*! @} */
20965 
20966 /* The count of CCM_CLOCK_ROOT_CONTROL_SET */
20967 #define CCM_CLOCK_ROOT_CONTROL_SET_COUNT         (79U)
20968 
20969 /*! @name CLOCK_ROOT_CONTROL_CLR - Clock root control */
20970 /*! @{ */
20971 
20972 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK      (0xFFU)
20973 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT     (0U)
20974 /*! DIV - Clock divider
20975  */
20976 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
20977 
20978 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK      (0x700U)
20979 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT     (8U)
20980 /*! MUX - Clock multiplexer
20981  */
20982 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
20983 
20984 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK      (0x1000000U)
20985 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT     (24U)
20986 /*! OFF - OFF
20987  */
20988 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
20989 /*! @} */
20990 
20991 /* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
20992 #define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT         (79U)
20993 
20994 /*! @name CLOCK_ROOT_CONTROL_TOG - Clock root control */
20995 /*! @{ */
20996 
20997 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK      (0xFFU)
20998 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT     (0U)
20999 /*! DIV - Clock divider
21000  */
21001 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
21002 
21003 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK      (0x700U)
21004 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT     (8U)
21005 /*! MUX - Clock multiplexer
21006  */
21007 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
21008 
21009 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK      (0x1000000U)
21010 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT     (24U)
21011 /*! OFF - OFF
21012  */
21013 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
21014 /*! @} */
21015 
21016 /* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
21017 #define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT         (79U)
21018 
21019 /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */
21020 /*! @{ */
21021 
21022 #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK          (0xFFU)
21023 #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT         (0U)
21024 /*! DIV - Current clock root DIV setting
21025  */
21026 #define CCM_CLOCK_ROOT_STATUS0_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
21027 
21028 #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK          (0x700U)
21029 #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT         (8U)
21030 /*! MUX - Current clock root MUX setting
21031  */
21032 #define CCM_CLOCK_ROOT_STATUS0_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
21033 
21034 #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK          (0x1000000U)
21035 #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT         (24U)
21036 /*! OFF - Current clock root OFF setting
21037  *  0b0..Clock is running
21038  *  0b1..Clock is disabled/off
21039  */
21040 #define CCM_CLOCK_ROOT_STATUS0_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
21041 
21042 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK    (0x8000000U)
21043 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT   (27U)
21044 /*! POWERDOWN - Current clock root POWERDOWN setting
21045  *  0b1..Clock root is Powered Down
21046  *  0b0..Clock root is running
21047  */
21048 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK)
21049 
21050 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
21051 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT  (28U)
21052 /*! SLICE_BUSY - Internal updating in generation logic
21053  *  0b1..Clock generation logic is applying the new setting
21054  *  0b0..Clock generation logic is not busy
21055  */
21056 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
21057 
21058 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
21059 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
21060 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
21061  *  0b1..Synchronization in process
21062  *  0b0..Synchronization not in process
21063  */
21064 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
21065 
21066 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
21067 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U)
21068 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
21069  *  0b1..Synchronization in process
21070  *  0b0..Synchronization not in process
21071  */
21072 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK)
21073 
21074 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK     (0x80000000U)
21075 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT    (31U)
21076 /*! CHANGING - Internal updating in clock root
21077  *  0b1..Clock generation logic is updating currently
21078  *  0b0..Clock Status is not updating currently
21079  */
21080 #define CCM_CLOCK_ROOT_STATUS0_CHANGING(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
21081 /*! @} */
21082 
21083 /* The count of CCM_CLOCK_ROOT_STATUS0 */
21084 #define CCM_CLOCK_ROOT_STATUS0_COUNT             (79U)
21085 
21086 /*! @name CLOCK_ROOT_STATUS1 - Clock root low power status */
21087 /*! @{ */
21088 
21089 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
21090 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U)
21091 /*! TARGET_SETPOINT - Target Setpoint
21092  */
21093 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK)
21094 
21095 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
21096 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
21097 /*! CURRENT_SETPOINT - Current Setpoint
21098  */
21099 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK)
21100 
21101 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
21102 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U)
21103 /*! DOWN_REQUEST - Clock frequency decrease request
21104  *  0b1..Frequency decrease requested
21105  *  0b0..Frequency decrease not requested
21106  */
21107 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK)
21108 
21109 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK    (0x2000000U)
21110 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT   (25U)
21111 /*! DOWN_DONE - Clock frequency decrease finish
21112  *  0b1..Frequency decrease completed
21113  *  0b0..Frequency decrease not completed
21114  */
21115 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK)
21116 
21117 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK   (0x4000000U)
21118 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT  (26U)
21119 /*! UP_REQUEST - Clock frequency increase request
21120  *  0b1..Frequency increase requested
21121  *  0b0..Frequency increase not requested
21122  */
21123 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK)
21124 
21125 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK      (0x8000000U)
21126 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT     (27U)
21127 /*! UP_DONE - Clock frequency increase finish
21128  *  0b1..Frequency increase completed
21129  *  0b0..Frequency increase not completed
21130  */
21131 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK)
21132 /*! @} */
21133 
21134 /* The count of CCM_CLOCK_ROOT_STATUS1 */
21135 #define CCM_CLOCK_ROOT_STATUS1_COUNT             (79U)
21136 
21137 /*! @name CLOCK_ROOT_CONFIG - Clock root configuration */
21138 /*! @{ */
21139 
21140 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
21141 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
21142 /*! SETPOINT_PRESENT - Setpoint present
21143  *  0b1..Setpoint is implemented.
21144  *  0b0..Setpoint is not implemented.
21145  */
21146 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK)
21147 /*! @} */
21148 
21149 /* The count of CCM_CLOCK_ROOT_CONFIG */
21150 #define CCM_CLOCK_ROOT_CONFIG_COUNT              (79U)
21151 
21152 /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */
21153 /*! @{ */
21154 
21155 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK       (0x1U)
21156 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT      (0U)
21157 /*! TZ_USER - User access
21158  *  0b1..Clock can be changed in user mode
21159  *  0b0..Clock cannot be changed in user mode
21160  */
21161 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
21162 
21163 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK         (0x2U)
21164 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT        (1U)
21165 /*! TZ_NS - Non-secure access
21166  *  0b0..Cannot be changed in Non-secure mode
21167  *  0b1..Can be changed in Non-secure mode
21168  */
21169 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
21170 
21171 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK       (0x10U)
21172 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT      (4U)
21173 /*! LOCK_TZ - Lock truszone setting
21174  *  0b0..Trustzone setting is not locked
21175  *  0b1..Trustzone setting is locked
21176  */
21177 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
21178 
21179 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK    (0xF00U)
21180 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT   (8U)
21181 /*! WHITE_LIST - Whitelist
21182  *  0b0000..This domain is NOT allowed to change clock
21183  *  0b0001..This domain is allowed to change clock
21184  */
21185 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
21186 
21187 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK     (0x1000U)
21188 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT    (12U)
21189 /*! LOCK_LIST - Lock Whitelist
21190  *  0b0..Whitelist is not locked
21191  *  0b1..Whitelist is locked
21192  */
21193 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
21194 
21195 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
21196 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
21197 /*! DOMAIN_MODE - Low power and access control by domain
21198  *  0b1..Clock works in Domain Mode
21199  *  0b0..Clock does NOT work in Domain Mode
21200  */
21201 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK)
21202 
21203 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
21204 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U)
21205 /*! SETPOINT_MODE - Low power and access control by Setpoint
21206  *  0b1..Clock works in Setpoint Mode
21207  *  0b0..Clock does NOT work in Setpoint Mode
21208  */
21209 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK)
21210 
21211 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK     (0x100000U)
21212 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT    (20U)
21213 /*! LOCK_MODE - Lock low power and access mode
21214  *  0b0..MODE is not locked
21215  *  0b1..MODE is locked
21216  */
21217 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK)
21218 /*! @} */
21219 
21220 /* The count of CCM_CLOCK_ROOT_AUTHEN */
21221 #define CCM_CLOCK_ROOT_AUTHEN_COUNT              (79U)
21222 
21223 /*! @name CLOCK_ROOT_AUTHEN_SET - Clock root access control */
21224 /*! @{ */
21225 
21226 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK   (0x1U)
21227 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT  (0U)
21228 /*! TZ_USER - User access
21229  */
21230 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK)
21231 
21232 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK     (0x2U)
21233 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT    (1U)
21234 /*! TZ_NS - Non-secure access
21235  */
21236 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK)
21237 
21238 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
21239 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
21240 /*! LOCK_TZ - Lock truszone setting
21241  */
21242 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK)
21243 
21244 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21245 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21246 /*! WHITE_LIST - Whitelist
21247  */
21248 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK)
21249 
21250 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21251 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21252 /*! LOCK_LIST - Lock Whitelist
21253  */
21254 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK)
21255 
21256 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21257 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21258 /*! DOMAIN_MODE - Low power and access control by domain
21259  */
21260 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK)
21261 
21262 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
21263 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
21264 /*! SETPOINT_MODE - Low power and access control by Setpoint
21265  */
21266 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK)
21267 
21268 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21269 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21270 /*! LOCK_MODE - Lock low power and access mode
21271  */
21272 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK)
21273 /*! @} */
21274 
21275 /* The count of CCM_CLOCK_ROOT_AUTHEN_SET */
21276 #define CCM_CLOCK_ROOT_AUTHEN_SET_COUNT          (79U)
21277 
21278 /*! @name CLOCK_ROOT_AUTHEN_CLR - Clock root access control */
21279 /*! @{ */
21280 
21281 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
21282 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
21283 /*! TZ_USER - User access
21284  */
21285 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK)
21286 
21287 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
21288 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
21289 /*! TZ_NS - Non-secure access
21290  */
21291 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK)
21292 
21293 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
21294 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
21295 /*! LOCK_TZ - Lock truszone setting
21296  */
21297 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK)
21298 
21299 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21300 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21301 /*! WHITE_LIST - Whitelist
21302  */
21303 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK)
21304 
21305 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21306 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21307 /*! LOCK_LIST - Lock Whitelist
21308  */
21309 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK)
21310 
21311 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21312 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21313 /*! DOMAIN_MODE - Low power and access control by domain
21314  */
21315 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK)
21316 
21317 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21318 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21319 /*! SETPOINT_MODE - Low power and access control by Setpoint
21320  */
21321 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK)
21322 
21323 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21324 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21325 /*! LOCK_MODE - Lock low power and access mode
21326  */
21327 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK)
21328 /*! @} */
21329 
21330 /* The count of CCM_CLOCK_ROOT_AUTHEN_CLR */
21331 #define CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT          (79U)
21332 
21333 /*! @name CLOCK_ROOT_AUTHEN_TOG - Clock root access control */
21334 /*! @{ */
21335 
21336 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
21337 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
21338 /*! TZ_USER - User access
21339  */
21340 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK)
21341 
21342 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
21343 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
21344 /*! TZ_NS - Non-secure access
21345  */
21346 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK)
21347 
21348 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
21349 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
21350 /*! LOCK_TZ - Lock truszone setting
21351  */
21352 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK)
21353 
21354 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21355 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21356 /*! WHITE_LIST - Whitelist
21357  */
21358 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK)
21359 
21360 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21361 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21362 /*! LOCK_LIST - Lock Whitelist
21363  */
21364 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK)
21365 
21366 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21367 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21368 /*! DOMAIN_MODE - Low power and access control by domain
21369  */
21370 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK)
21371 
21372 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21373 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21374 /*! SETPOINT_MODE - Low power and access control by Setpoint
21375  */
21376 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK)
21377 
21378 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21379 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21380 /*! LOCK_MODE - Lock low power and access mode
21381  */
21382 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK)
21383 /*! @} */
21384 
21385 /* The count of CCM_CLOCK_ROOT_AUTHEN_TOG */
21386 #define CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT          (79U)
21387 
21388 /*! @name CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting */
21389 /*! @{ */
21390 
21391 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU)
21392 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U)
21393 /*! DIV - Clock divider
21394  */
21395 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK)
21396 
21397 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U)
21398 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U)
21399 /*! MUX - Clock multiplexer
21400  */
21401 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK)
21402 
21403 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21404 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21405 /*! OFF - OFF
21406  *  0b1..OFF
21407  *  0b0..ON
21408  */
21409 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK)
21410 
21411 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21412 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21413 /*! GRADE - Grade
21414  */
21415 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK)
21416 /*! @} */
21417 
21418 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
21419 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U)
21420 
21421 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
21422 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U)
21423 
21424 /*! @name CLOCK_GROUP_CONTROL - Clock group control */
21425 /*! @{ */
21426 
21427 #define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK        (0xFU)
21428 #define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT       (0U)
21429 /*! DIV0 - Clock divider0
21430  */
21431 #define CCM_CLOCK_GROUP_CONTROL_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK)
21432 
21433 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK      (0xFF0000U)
21434 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT     (16U)
21435 /*! RSTDIV - Clock group global restart count
21436  */
21437 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK)
21438 
21439 #define CCM_CLOCK_GROUP_CONTROL_OFF_MASK         (0x1000000U)
21440 #define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT        (24U)
21441 /*! OFF - OFF
21442  *  0b0..Clock is running
21443  *  0b1..Turn off clock
21444  */
21445 #define CCM_CLOCK_GROUP_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK)
21446 /*! @} */
21447 
21448 /* The count of CCM_CLOCK_GROUP_CONTROL */
21449 #define CCM_CLOCK_GROUP_CONTROL_COUNT            (2U)
21450 
21451 /*! @name CLOCK_GROUP_CONTROL_SET - Clock group control */
21452 /*! @{ */
21453 
21454 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK    (0xFU)
21455 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT   (0U)
21456 /*! DIV0 - Clock divider0
21457  */
21458 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK)
21459 
21460 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK  (0xFF0000U)
21461 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U)
21462 /*! RSTDIV - Clock group global restart count
21463  */
21464 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK)
21465 
21466 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK     (0x1000000U)
21467 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT    (24U)
21468 /*! OFF - OFF
21469  */
21470 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK)
21471 /*! @} */
21472 
21473 /* The count of CCM_CLOCK_GROUP_CONTROL_SET */
21474 #define CCM_CLOCK_GROUP_CONTROL_SET_COUNT        (2U)
21475 
21476 /*! @name CLOCK_GROUP_CONTROL_CLR - Clock group control */
21477 /*! @{ */
21478 
21479 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK    (0xFU)
21480 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT   (0U)
21481 /*! DIV0 - Clock divider0
21482  */
21483 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK)
21484 
21485 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK  (0xFF0000U)
21486 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U)
21487 /*! RSTDIV - Clock group global restart count
21488  */
21489 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK)
21490 
21491 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK     (0x1000000U)
21492 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT    (24U)
21493 /*! OFF - OFF
21494  */
21495 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK)
21496 /*! @} */
21497 
21498 /* The count of CCM_CLOCK_GROUP_CONTROL_CLR */
21499 #define CCM_CLOCK_GROUP_CONTROL_CLR_COUNT        (2U)
21500 
21501 /*! @name CLOCK_GROUP_CONTROL_TOG - Clock group control */
21502 /*! @{ */
21503 
21504 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK    (0xFU)
21505 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT   (0U)
21506 /*! DIV0 - Clock divider0
21507  */
21508 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK)
21509 
21510 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK  (0xFF0000U)
21511 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U)
21512 /*! RSTDIV - Clock group global restart count
21513  */
21514 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK)
21515 
21516 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK     (0x1000000U)
21517 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT    (24U)
21518 /*! OFF - OFF
21519  */
21520 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK)
21521 /*! @} */
21522 
21523 /* The count of CCM_CLOCK_GROUP_CONTROL_TOG */
21524 #define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT        (2U)
21525 
21526 /*! @name CLOCK_GROUP_STATUS0 - Clock group working status */
21527 /*! @{ */
21528 
21529 #define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK        (0xFU)
21530 #define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT       (0U)
21531 /*! DIV0 - Clock divider
21532  */
21533 #define CCM_CLOCK_GROUP_STATUS0_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK)
21534 
21535 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK      (0xFF0000U)
21536 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT     (16U)
21537 /*! RSTDIV - Clock divider
21538  */
21539 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK)
21540 
21541 #define CCM_CLOCK_GROUP_STATUS0_OFF_MASK         (0x1000000U)
21542 #define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT        (24U)
21543 /*! OFF - OFF
21544  *  0b0..Clock is running.
21545  *  0b1..Turn off clock.
21546  */
21547 #define CCM_CLOCK_GROUP_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK)
21548 
21549 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK   (0x8000000U)
21550 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT  (27U)
21551 /*! POWERDOWN - Current clock root POWERDOWN setting
21552  *  0b1..Clock root is Powered Down
21553  *  0b0..Clock root is running
21554  */
21555 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK)
21556 
21557 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK  (0x10000000U)
21558 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U)
21559 /*! SLICE_BUSY - Internal updating in generation logic
21560  *  0b1..Clock generation logic is applying the new setting
21561  *  0b0..Clock generation logic is not busy
21562  */
21563 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK)
21564 
21565 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
21566 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U)
21567 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
21568  *  0b1..Synchronization in process
21569  *  0b0..Synchronization not in process
21570  */
21571 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK)
21572 
21573 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
21574 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U)
21575 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
21576  *  0b1..Synchronization in process
21577  *  0b0..Synchronization not in process
21578  */
21579 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK)
21580 
21581 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK    (0x80000000U)
21582 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT   (31U)
21583 /*! CHANGING - Internal updating in clock group
21584  *  0b1..Clock root logic is updating currently
21585  *  0b0..Clock root is not updating currently
21586  */
21587 #define CCM_CLOCK_GROUP_STATUS0_CHANGING(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK)
21588 /*! @} */
21589 
21590 /* The count of CCM_CLOCK_GROUP_STATUS0 */
21591 #define CCM_CLOCK_GROUP_STATUS0_COUNT            (2U)
21592 
21593 /*! @name CLOCK_GROUP_STATUS1 - Clock group low power/extend status */
21594 /*! @{ */
21595 
21596 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
21597 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U)
21598 /*! TARGET_SETPOINT - Next Setpoint to change to
21599  */
21600 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK)
21601 
21602 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
21603 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
21604 /*! CURRENT_SETPOINT - Current Setpoint
21605  */
21606 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK)
21607 
21608 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
21609 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U)
21610 /*! DOWN_REQUEST - Clock frequency decrease request
21611  *  0b1..Handshake signal with GPC status indicating frequency decrease is requested
21612  *  0b0..No handshake signal is not requested
21613  */
21614 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK)
21615 
21616 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK   (0x2000000U)
21617 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT  (25U)
21618 /*! DOWN_DONE - Clock frequency decrease complete
21619  *  0b1..Handshake signal with GPC status indicating frequency decrease is complete
21620  *  0b0..Handshake signal with GPC status indicating frequency decrease is not complete
21621  */
21622 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK)
21623 
21624 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK  (0x4000000U)
21625 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U)
21626 /*! UP_REQUEST - Clock frequency increase request
21627  *  0b1..Handshake signal with GPC status indicating frequency increase is requested
21628  *  0b0..No handshake signal is not requested
21629  */
21630 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK)
21631 
21632 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK     (0x8000000U)
21633 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT    (27U)
21634 /*! UP_DONE - Clock frequency increase complete
21635  *  0b1..Handshake signal with GPC status indicating frequency increase is complete
21636  *  0b0..Handshake signal with GPC status indicating frequency increase is not complete
21637  */
21638 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK)
21639 /*! @} */
21640 
21641 /* The count of CCM_CLOCK_GROUP_STATUS1 */
21642 #define CCM_CLOCK_GROUP_STATUS1_COUNT            (2U)
21643 
21644 /*! @name CLOCK_GROUP_CONFIG - Clock group configuration */
21645 /*! @{ */
21646 
21647 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
21648 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
21649 /*! SETPOINT_PRESENT - Setpoint present
21650  *  0b1..Setpoint is implemented.
21651  *  0b0..Setpoint is not implemented.
21652  */
21653 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK)
21654 /*! @} */
21655 
21656 /* The count of CCM_CLOCK_GROUP_CONFIG */
21657 #define CCM_CLOCK_GROUP_CONFIG_COUNT             (2U)
21658 
21659 /*! @name CLOCK_GROUP_AUTHEN - Clock group access control */
21660 /*! @{ */
21661 
21662 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK      (0x1U)
21663 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT     (0U)
21664 /*! TZ_USER - User access
21665  *  0b1..Clock can be changed in user mode.
21666  *  0b0..Clock cannot be changed in user mode.
21667  */
21668 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK)
21669 
21670 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK        (0x2U)
21671 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT       (1U)
21672 /*! TZ_NS - Non-secure access
21673  *  0b0..Cannot be changed in Non-secure mode.
21674  *  0b1..Can be changed in Non-secure mode.
21675  */
21676 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK)
21677 
21678 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK      (0x10U)
21679 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT     (4U)
21680 /*! LOCK_TZ - Lock truszone setting
21681  *  0b0..Trustzone setting is not locked.
21682  *  0b1..Trustzone setting is locked.
21683  */
21684 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK)
21685 
21686 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK   (0xF00U)
21687 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT  (8U)
21688 /*! WHITE_LIST - Whitelist
21689  */
21690 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK)
21691 
21692 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK    (0x1000U)
21693 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT   (12U)
21694 /*! LOCK_LIST - Lock Whitelist
21695  *  0b0..Whitelist is not locked.
21696  *  0b1..Whitelist is locked.
21697  */
21698 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK)
21699 
21700 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
21701 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21702 /*! DOMAIN_MODE - Low power and access control by domain
21703  *  0b1..Clock works in Domain Mode.
21704  *  0b0..Clock does not work in Domain Mode.
21705  */
21706 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK)
21707 
21708 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
21709 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U)
21710 /*! SETPOINT_MODE - Low power and access control by Setpoint
21711  */
21712 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK)
21713 
21714 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK    (0x100000U)
21715 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT   (20U)
21716 /*! LOCK_MODE - Lock low power and access mode
21717  *  0b0..MODE is not locked.
21718  *  0b1..MODE is locked.
21719  */
21720 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK)
21721 /*! @} */
21722 
21723 /* The count of CCM_CLOCK_GROUP_AUTHEN */
21724 #define CCM_CLOCK_GROUP_AUTHEN_COUNT             (2U)
21725 
21726 /*! @name CLOCK_GROUP_AUTHEN_SET - Clock group access control */
21727 /*! @{ */
21728 
21729 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK  (0x1U)
21730 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U)
21731 /*! TZ_USER - User access
21732  */
21733 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK)
21734 
21735 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK    (0x2U)
21736 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT   (1U)
21737 /*! TZ_NS - Non-secure access
21738  */
21739 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK)
21740 
21741 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
21742 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21743 /*! LOCK_TZ - Lock truszone setting
21744  */
21745 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK)
21746 
21747 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21748 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21749 /*! WHITE_LIST - Whitelist
21750  */
21751 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK)
21752 
21753 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21754 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21755 /*! LOCK_LIST - Lock Whitelist
21756  */
21757 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK)
21758 
21759 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21760 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21761 /*! DOMAIN_MODE - Low power and access control by domain
21762  */
21763 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK)
21764 
21765 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
21766 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
21767 /*! SETPOINT_MODE - Low power and access control by Setpoint
21768  */
21769 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK)
21770 
21771 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21772 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21773 /*! LOCK_MODE - Lock low power and access mode
21774  */
21775 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK)
21776 /*! @} */
21777 
21778 /* The count of CCM_CLOCK_GROUP_AUTHEN_SET */
21779 #define CCM_CLOCK_GROUP_AUTHEN_SET_COUNT         (2U)
21780 
21781 /*! @name CLOCK_GROUP_AUTHEN_CLR - Clock group access control */
21782 /*! @{ */
21783 
21784 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
21785 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21786 /*! TZ_USER - User access
21787  */
21788 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK)
21789 
21790 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
21791 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
21792 /*! TZ_NS - Non-secure access
21793  */
21794 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK)
21795 
21796 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
21797 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21798 /*! LOCK_TZ - Lock truszone setting
21799  */
21800 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK)
21801 
21802 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21803 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21804 /*! WHITE_LIST - Whitelist
21805  */
21806 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK)
21807 
21808 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21809 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21810 /*! LOCK_LIST - Lock Whitelist
21811  */
21812 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK)
21813 
21814 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21815 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21816 /*! DOMAIN_MODE - Low power and access control by domain
21817  */
21818 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK)
21819 
21820 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21821 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21822 /*! SETPOINT_MODE - Low power and access control by Setpoint
21823  */
21824 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK)
21825 
21826 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21827 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21828 /*! LOCK_MODE - Lock low power and access mode
21829  */
21830 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK)
21831 /*! @} */
21832 
21833 /* The count of CCM_CLOCK_GROUP_AUTHEN_CLR */
21834 #define CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT         (2U)
21835 
21836 /*! @name CLOCK_GROUP_AUTHEN_TOG - Clock group access control */
21837 /*! @{ */
21838 
21839 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
21840 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21841 /*! TZ_USER - User access
21842  */
21843 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK)
21844 
21845 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
21846 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
21847 /*! TZ_NS - Non-secure access
21848  */
21849 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK)
21850 
21851 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
21852 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21853 /*! LOCK_TZ - Lock truszone setting
21854  */
21855 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK)
21856 
21857 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21858 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21859 /*! WHITE_LIST - Whitelist
21860  */
21861 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK)
21862 
21863 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21864 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21865 /*! LOCK_LIST - Lock Whitelist
21866  */
21867 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK)
21868 
21869 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21870 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21871 /*! DOMAIN_MODE - Low power and access control by domain
21872  */
21873 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK)
21874 
21875 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21876 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21877 /*! SETPOINT_MODE - Low power and access control by Setpoint
21878  */
21879 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK)
21880 
21881 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21882 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21883 /*! LOCK_MODE - Lock low power and access mode
21884  */
21885 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK)
21886 /*! @} */
21887 
21888 /* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */
21889 #define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT         (2U)
21890 
21891 /*! @name CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting */
21892 /*! @{ */
21893 
21894 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU)
21895 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U)
21896 /*! DIV0 - Clock divider
21897  *  0b0000..Direct output.
21898  *  0b0001..Divide by 2.
21899  *  0b0010..Divide by 3.
21900  *  0b0011..Divide by 4.
21901  *  0b1111..Divide by 16.
21902  */
21903 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK)
21904 
21905 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U)
21906 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U)
21907 /*! RSTDIV - Clock group global restart count
21908  */
21909 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK)
21910 
21911 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21912 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21913 /*! OFF - OFF
21914  *  0b0..Clock is running.
21915  *  0b1..Turn off clock.
21916  */
21917 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK)
21918 
21919 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21920 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21921 /*! GRADE - Grade
21922  */
21923 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK)
21924 /*! @} */
21925 
21926 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21927 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U)
21928 
21929 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21930 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U)
21931 
21932 /*! @name GPR_SHARED - General Purpose Register */
21933 /*! @{ */
21934 
21935 #define CCM_GPR_SHARED_GPR_MASK                  (0xFFFFFFFFU)
21936 #define CCM_GPR_SHARED_GPR_SHIFT                 (0U)
21937 /*! GPR - GP register
21938  */
21939 #define CCM_GPR_SHARED_GPR(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK)
21940 /*! @} */
21941 
21942 /* The count of CCM_GPR_SHARED */
21943 #define CCM_GPR_SHARED_COUNT                     (8U)
21944 
21945 /*! @name GPR_SHARED_SET - General Purpose Register */
21946 /*! @{ */
21947 
21948 #define CCM_GPR_SHARED_SET_GPR_MASK              (0xFFFFFFFFU)
21949 #define CCM_GPR_SHARED_SET_GPR_SHIFT             (0U)
21950 /*! GPR - GP register
21951  */
21952 #define CCM_GPR_SHARED_SET_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK)
21953 /*! @} */
21954 
21955 /* The count of CCM_GPR_SHARED_SET */
21956 #define CCM_GPR_SHARED_SET_COUNT                 (8U)
21957 
21958 /*! @name GPR_SHARED_CLR - General Purpose Register */
21959 /*! @{ */
21960 
21961 #define CCM_GPR_SHARED_CLR_GPR_MASK              (0xFFFFFFFFU)
21962 #define CCM_GPR_SHARED_CLR_GPR_SHIFT             (0U)
21963 /*! GPR - GP register
21964  */
21965 #define CCM_GPR_SHARED_CLR_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK)
21966 /*! @} */
21967 
21968 /* The count of CCM_GPR_SHARED_CLR */
21969 #define CCM_GPR_SHARED_CLR_COUNT                 (8U)
21970 
21971 /*! @name GPR_SHARED_TOG - General Purpose Register */
21972 /*! @{ */
21973 
21974 #define CCM_GPR_SHARED_TOG_GPR_MASK              (0xFFFFFFFFU)
21975 #define CCM_GPR_SHARED_TOG_GPR_SHIFT             (0U)
21976 /*! GPR - GP register
21977  */
21978 #define CCM_GPR_SHARED_TOG_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK)
21979 /*! @} */
21980 
21981 /* The count of CCM_GPR_SHARED_TOG */
21982 #define CCM_GPR_SHARED_TOG_COUNT                 (8U)
21983 
21984 /*! @name GPR_SHARED_AUTHEN - GPR access control */
21985 /*! @{ */
21986 
21987 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK       (0x1U)
21988 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT      (0U)
21989 /*! TZ_USER - User access
21990  *  0b1..Clock can be changed in user mode.
21991  *  0b0..Clock cannot be changed in user mode.
21992  */
21993 #define CCM_GPR_SHARED_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK)
21994 
21995 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK         (0x2U)
21996 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT        (1U)
21997 /*! TZ_NS - Non-secure access
21998  *  0b0..Cannot be changed in Non-secure mode.
21999  *  0b1..Can be changed in Non-secure mode.
22000  */
22001 #define CCM_GPR_SHARED_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK)
22002 
22003 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK       (0x10U)
22004 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT      (4U)
22005 /*! LOCK_TZ - Lock truszone setting
22006  *  0b0..Trustzone setting is not locked.
22007  *  0b1..Trustzone setting is locked.
22008  */
22009 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK)
22010 
22011 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK    (0xF00U)
22012 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT   (8U)
22013 /*! WHITE_LIST - Whitelist
22014  *  0b0000..This domain is NOT allowed to change clock.
22015  *  0b0001..This domain is allowed to change clock.
22016  */
22017 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK)
22018 
22019 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK     (0x1000U)
22020 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT    (12U)
22021 /*! LOCK_LIST - Lock Whitelist
22022  *  0b0..Whitelist is not locked.
22023  *  0b1..Whitelist is locked.
22024  */
22025 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK)
22026 
22027 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
22028 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
22029 /*! DOMAIN_MODE - Low power and access control by domain
22030  *  0b1..Clock works in Domain Mode.
22031  *  0b0..Clock does NOT work in Domain Mode.
22032  */
22033 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK)
22034 
22035 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK     (0x100000U)
22036 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT    (20U)
22037 /*! LOCK_MODE - Lock low power and access mode
22038  *  0b0..MODE is not locked.
22039  *  0b1..MODE is locked.
22040  */
22041 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK)
22042 /*! @} */
22043 
22044 /* The count of CCM_GPR_SHARED_AUTHEN */
22045 #define CCM_GPR_SHARED_AUTHEN_COUNT              (8U)
22046 
22047 /*! @name GPR_SHARED_AUTHEN_SET - GPR access control */
22048 /*! @{ */
22049 
22050 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK   (0x1U)
22051 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT  (0U)
22052 /*! TZ_USER - User access
22053  */
22054 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK)
22055 
22056 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK     (0x2U)
22057 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT    (1U)
22058 /*! TZ_NS - Non-secure access
22059  */
22060 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK)
22061 
22062 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
22063 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
22064 /*! LOCK_TZ - Lock truszone setting
22065  */
22066 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK)
22067 
22068 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22069 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22070 /*! WHITE_LIST - Whitelist
22071  */
22072 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK)
22073 
22074 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22075 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22076 /*! LOCK_LIST - Lock Whitelist
22077  */
22078 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK)
22079 
22080 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22081 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22082 /*! DOMAIN_MODE - Low power and access control by domain
22083  */
22084 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK)
22085 
22086 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22087 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22088 /*! LOCK_MODE - Lock low power and access mode
22089  */
22090 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK)
22091 /*! @} */
22092 
22093 /* The count of CCM_GPR_SHARED_AUTHEN_SET */
22094 #define CCM_GPR_SHARED_AUTHEN_SET_COUNT          (8U)
22095 
22096 /*! @name GPR_SHARED_AUTHEN_CLR - GPR access control */
22097 /*! @{ */
22098 
22099 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
22100 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
22101 /*! TZ_USER - User access
22102  */
22103 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK)
22104 
22105 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
22106 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
22107 /*! TZ_NS - Non-secure access
22108  */
22109 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK)
22110 
22111 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
22112 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
22113 /*! LOCK_TZ - Lock truszone setting
22114  */
22115 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK)
22116 
22117 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22118 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22119 /*! WHITE_LIST - Whitelist
22120  */
22121 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK)
22122 
22123 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22124 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22125 /*! LOCK_LIST - Lock Whitelist
22126  */
22127 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK)
22128 
22129 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22130 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22131 /*! DOMAIN_MODE - Low power and access control by domain
22132  */
22133 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK)
22134 
22135 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22136 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22137 /*! LOCK_MODE - Lock low power and access mode
22138  */
22139 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK)
22140 /*! @} */
22141 
22142 /* The count of CCM_GPR_SHARED_AUTHEN_CLR */
22143 #define CCM_GPR_SHARED_AUTHEN_CLR_COUNT          (8U)
22144 
22145 /*! @name GPR_SHARED_AUTHEN_TOG - GPR access control */
22146 /*! @{ */
22147 
22148 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
22149 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
22150 /*! TZ_USER - User access
22151  */
22152 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK)
22153 
22154 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
22155 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
22156 /*! TZ_NS - Non-secure access
22157  */
22158 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK)
22159 
22160 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
22161 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
22162 /*! LOCK_TZ - Lock truszone setting
22163  */
22164 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK)
22165 
22166 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22167 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22168 /*! WHITE_LIST - Whitelist
22169  */
22170 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK)
22171 
22172 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22173 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22174 /*! LOCK_LIST - Lock Whitelist
22175  */
22176 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK)
22177 
22178 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22179 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22180 /*! DOMAIN_MODE - Low power and access control by domain
22181  */
22182 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK)
22183 
22184 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22185 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22186 /*! LOCK_MODE - Lock low power and access mode
22187  */
22188 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK)
22189 /*! @} */
22190 
22191 /* The count of CCM_GPR_SHARED_AUTHEN_TOG */
22192 #define CCM_GPR_SHARED_AUTHEN_TOG_COUNT          (8U)
22193 
22194 /*! @name GPR_PRIVATE1 - General Purpose Register */
22195 /*! @{ */
22196 
22197 #define CCM_GPR_PRIVATE1_GPR_MASK                (0xFFFFFFFFU)
22198 #define CCM_GPR_PRIVATE1_GPR_SHIFT               (0U)
22199 /*! GPR - GP register
22200  */
22201 #define CCM_GPR_PRIVATE1_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK)
22202 /*! @} */
22203 
22204 /*! @name GPR_PRIVATE1_SET - General Purpose Register */
22205 /*! @{ */
22206 
22207 #define CCM_GPR_PRIVATE1_SET_GPR_MASK            (0xFFFFFFFFU)
22208 #define CCM_GPR_PRIVATE1_SET_GPR_SHIFT           (0U)
22209 /*! GPR - GP register
22210  */
22211 #define CCM_GPR_PRIVATE1_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK)
22212 /*! @} */
22213 
22214 /*! @name GPR_PRIVATE1_CLR - General Purpose Register */
22215 /*! @{ */
22216 
22217 #define CCM_GPR_PRIVATE1_CLR_GPR_MASK            (0xFFFFFFFFU)
22218 #define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT           (0U)
22219 /*! GPR - GP register
22220  */
22221 #define CCM_GPR_PRIVATE1_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK)
22222 /*! @} */
22223 
22224 /*! @name GPR_PRIVATE1_TOG - General Purpose Register */
22225 /*! @{ */
22226 
22227 #define CCM_GPR_PRIVATE1_TOG_GPR_MASK            (0xFFFFFFFFU)
22228 #define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT           (0U)
22229 /*! GPR - GP register
22230  */
22231 #define CCM_GPR_PRIVATE1_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK)
22232 /*! @} */
22233 
22234 /*! @name GPR_PRIVATE1_AUTHEN - GPR access control */
22235 /*! @{ */
22236 
22237 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK     (0x1U)
22238 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT    (0U)
22239 /*! TZ_USER - User access
22240  *  0b1..Clock can be changed in user mode.
22241  *  0b0..Clock cannot be changed in user mode.
22242  */
22243 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK)
22244 
22245 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK       (0x2U)
22246 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT      (1U)
22247 /*! TZ_NS - Non-secure access
22248  *  0b0..Cannot be changed in Non-secure mode.
22249  *  0b1..Can be changed in Non-secure mode.
22250  */
22251 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK)
22252 
22253 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK     (0x10U)
22254 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT    (4U)
22255 /*! LOCK_TZ - Lock truszone setting
22256  *  0b0..Trustzone setting is not locked.
22257  *  0b1..Trustzone setting is locked.
22258  */
22259 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK)
22260 
22261 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22262 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U)
22263 /*! WHITE_LIST - Whitelist
22264  *  0b0000..This domain is NOT allowed to change clock.
22265  *  0b0001..This domain is allowed to change clock.
22266  */
22267 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK)
22268 
22269 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22270 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT  (12U)
22271 /*! LOCK_LIST - Lock Whitelist
22272  *  0b0..Whitelist is not locked.
22273  *  0b1..Whitelist is locked.
22274  */
22275 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK)
22276 
22277 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22278 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22279 /*! DOMAIN_MODE - Low power and access control by Domain
22280  *  0b1..Clock works in Domain Mode.
22281  *  0b0..Clock does NOT work in Domain Mode.
22282  */
22283 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK)
22284 
22285 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22286 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT  (20U)
22287 /*! LOCK_MODE - Lock low power and access mode
22288  *  0b0..MODE is not locked.
22289  *  0b1..MODE is locked.
22290  */
22291 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK)
22292 /*! @} */
22293 
22294 /*! @name GPR_PRIVATE1_AUTHEN_SET - GPR access control */
22295 /*! @{ */
22296 
22297 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U)
22298 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U)
22299 /*! TZ_USER - User access
22300  */
22301 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK)
22302 
22303 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22304 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22305 /*! TZ_NS - Non-secure access
22306  */
22307 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK)
22308 
22309 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22310 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22311 /*! LOCK_TZ - Lock truszone setting
22312  */
22313 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK)
22314 
22315 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22316 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22317 /*! WHITE_LIST - Whitelist
22318  */
22319 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK)
22320 
22321 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22322 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22323 /*! LOCK_LIST - Lock Whitelist
22324  */
22325 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK)
22326 
22327 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22328 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22329 /*! DOMAIN_MODE - Low power and access control by Domain
22330  */
22331 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK)
22332 
22333 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22334 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22335 /*! LOCK_MODE - Lock low power and access mode
22336  */
22337 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK)
22338 /*! @} */
22339 
22340 /*! @name GPR_PRIVATE1_AUTHEN_CLR - GPR access control */
22341 /*! @{ */
22342 
22343 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22344 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22345 /*! TZ_USER - User access
22346  */
22347 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK)
22348 
22349 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22350 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22351 /*! TZ_NS - Non-secure access
22352  */
22353 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK)
22354 
22355 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22356 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22357 /*! LOCK_TZ - Lock truszone setting
22358  */
22359 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK)
22360 
22361 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22362 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22363 /*! WHITE_LIST - Whitelist
22364  */
22365 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK)
22366 
22367 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22368 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22369 /*! LOCK_LIST - Lock Whitelist
22370  */
22371 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK)
22372 
22373 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22374 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22375 /*! DOMAIN_MODE - Low power and access control by Domain
22376  */
22377 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK)
22378 
22379 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22380 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22381 /*! LOCK_MODE - Lock low power and access mode
22382  */
22383 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK)
22384 /*! @} */
22385 
22386 /*! @name GPR_PRIVATE1_AUTHEN_TOG - GPR access control */
22387 /*! @{ */
22388 
22389 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22390 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22391 /*! TZ_USER - User access
22392  */
22393 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK)
22394 
22395 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22396 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22397 /*! TZ_NS - Non-secure access
22398  */
22399 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK)
22400 
22401 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22402 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22403 /*! LOCK_TZ - Lock truszone setting
22404  */
22405 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK)
22406 
22407 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22408 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22409 /*! WHITE_LIST - Whitelist
22410  */
22411 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK)
22412 
22413 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22414 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22415 /*! LOCK_LIST - Lock Whitelist
22416  */
22417 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK)
22418 
22419 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22420 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22421 /*! DOMAIN_MODE - Low power and access control by Domain
22422  */
22423 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK)
22424 
22425 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22426 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22427 /*! LOCK_MODE - Lock low power and access mode
22428  */
22429 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK)
22430 /*! @} */
22431 
22432 /*! @name GPR_PRIVATE2 - General Purpose Register */
22433 /*! @{ */
22434 
22435 #define CCM_GPR_PRIVATE2_GPR_MASK                (0xFFFFFFFFU)
22436 #define CCM_GPR_PRIVATE2_GPR_SHIFT               (0U)
22437 /*! GPR - GP register
22438  */
22439 #define CCM_GPR_PRIVATE2_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK)
22440 /*! @} */
22441 
22442 /*! @name GPR_PRIVATE2_SET - General Purpose Register */
22443 /*! @{ */
22444 
22445 #define CCM_GPR_PRIVATE2_SET_GPR_MASK            (0xFFFFFFFFU)
22446 #define CCM_GPR_PRIVATE2_SET_GPR_SHIFT           (0U)
22447 /*! GPR - GP register
22448  */
22449 #define CCM_GPR_PRIVATE2_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK)
22450 /*! @} */
22451 
22452 /*! @name GPR_PRIVATE2_CLR - General Purpose Register */
22453 /*! @{ */
22454 
22455 #define CCM_GPR_PRIVATE2_CLR_GPR_MASK            (0xFFFFFFFFU)
22456 #define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT           (0U)
22457 /*! GPR - GP register
22458  */
22459 #define CCM_GPR_PRIVATE2_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK)
22460 /*! @} */
22461 
22462 /*! @name GPR_PRIVATE2_TOG - General Purpose Register */
22463 /*! @{ */
22464 
22465 #define CCM_GPR_PRIVATE2_TOG_GPR_MASK            (0xFFFFFFFFU)
22466 #define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT           (0U)
22467 /*! GPR - GP register
22468  */
22469 #define CCM_GPR_PRIVATE2_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK)
22470 /*! @} */
22471 
22472 /*! @name GPR_PRIVATE2_AUTHEN - GPR access control */
22473 /*! @{ */
22474 
22475 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK     (0x1U)
22476 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT    (0U)
22477 /*! TZ_USER - User access
22478  *  0b1..Clock can be changed in user mode.
22479  *  0b0..Clock cannot be changed in user mode.
22480  */
22481 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK)
22482 
22483 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK       (0x2U)
22484 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT      (1U)
22485 /*! TZ_NS - Non-secure access
22486  *  0b0..Cannot be changed in Non-secure mode.
22487  *  0b1..Can be changed in Non-secure mode.
22488  */
22489 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK)
22490 
22491 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK     (0x10U)
22492 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT    (4U)
22493 /*! LOCK_TZ - Lock truszone setting
22494  *  0b0..Trustzone setting is not locked.
22495  *  0b1..Trustzone setting is locked.
22496  */
22497 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK)
22498 
22499 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22500 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U)
22501 /*! WHITE_LIST - Whitelist
22502  *  0b0000..This domain is NOT allowed to change clock.
22503  *  0b0001..This domain is allowed to change clock.
22504  */
22505 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK)
22506 
22507 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22508 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT  (12U)
22509 /*! LOCK_LIST - Lock Whitelist
22510  *  0b0..Whitelist is not locked.
22511  *  0b1..Whitelist is locked.
22512  */
22513 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK)
22514 
22515 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22516 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22517 /*! DOMAIN_MODE - Low power and access control by Domain
22518  *  0b1..Clock works in Domain Mode.
22519  *  0b0..Clock does NOT work in Domain Mode.
22520  */
22521 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK)
22522 
22523 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22524 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT  (20U)
22525 /*! LOCK_MODE - Lock low power and access mode
22526  *  0b0..MODE is not locked.
22527  *  0b1..MODE is locked.
22528  */
22529 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK)
22530 /*! @} */
22531 
22532 /*! @name GPR_PRIVATE2_AUTHEN_SET - GPR access control */
22533 /*! @{ */
22534 
22535 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U)
22536 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U)
22537 /*! TZ_USER - User access
22538  */
22539 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK)
22540 
22541 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22542 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22543 /*! TZ_NS - Non-secure access
22544  */
22545 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK)
22546 
22547 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22548 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22549 /*! LOCK_TZ - Lock truszone setting
22550  */
22551 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK)
22552 
22553 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22554 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22555 /*! WHITE_LIST - Whitelist
22556  */
22557 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK)
22558 
22559 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22560 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22561 /*! LOCK_LIST - Lock Whitelist
22562  */
22563 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK)
22564 
22565 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22566 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22567 /*! DOMAIN_MODE - Low power and access control by Domain
22568  */
22569 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK)
22570 
22571 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22572 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22573 /*! LOCK_MODE - Lock low power and access mode
22574  */
22575 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK)
22576 /*! @} */
22577 
22578 /*! @name GPR_PRIVATE2_AUTHEN_CLR - GPR access control */
22579 /*! @{ */
22580 
22581 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22582 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22583 /*! TZ_USER - User access
22584  */
22585 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK)
22586 
22587 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22588 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22589 /*! TZ_NS - Non-secure access
22590  */
22591 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK)
22592 
22593 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22594 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22595 /*! LOCK_TZ - Lock truszone setting
22596  */
22597 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK)
22598 
22599 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22600 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22601 /*! WHITE_LIST - Whitelist
22602  */
22603 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK)
22604 
22605 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22606 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22607 /*! LOCK_LIST - Lock Whitelist
22608  */
22609 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK)
22610 
22611 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22612 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22613 /*! DOMAIN_MODE - Low power and access control by Domain
22614  */
22615 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK)
22616 
22617 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22618 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22619 /*! LOCK_MODE - Lock low power and access mode
22620  */
22621 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK)
22622 /*! @} */
22623 
22624 /*! @name GPR_PRIVATE2_AUTHEN_TOG - GPR access control */
22625 /*! @{ */
22626 
22627 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22628 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22629 /*! TZ_USER - User access
22630  */
22631 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK)
22632 
22633 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22634 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22635 /*! TZ_NS - Non-secure access
22636  */
22637 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK)
22638 
22639 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22640 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22641 /*! LOCK_TZ - Lock truszone setting
22642  */
22643 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK)
22644 
22645 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22646 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22647 /*! WHITE_LIST - Whitelist
22648  */
22649 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK)
22650 
22651 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22652 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22653 /*! LOCK_LIST - Lock Whitelist
22654  */
22655 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK)
22656 
22657 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22658 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22659 /*! DOMAIN_MODE - Low power and access control by Domain
22660  */
22661 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK)
22662 
22663 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22664 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22665 /*! LOCK_MODE - Lock low power and access mode
22666  */
22667 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK)
22668 /*! @} */
22669 
22670 /*! @name GPR_PRIVATE3 - General Purpose Register */
22671 /*! @{ */
22672 
22673 #define CCM_GPR_PRIVATE3_GPR_MASK                (0xFFFFFFFFU)
22674 #define CCM_GPR_PRIVATE3_GPR_SHIFT               (0U)
22675 /*! GPR - GP register
22676  */
22677 #define CCM_GPR_PRIVATE3_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK)
22678 /*! @} */
22679 
22680 /*! @name GPR_PRIVATE3_SET - General Purpose Register */
22681 /*! @{ */
22682 
22683 #define CCM_GPR_PRIVATE3_SET_GPR_MASK            (0xFFFFFFFFU)
22684 #define CCM_GPR_PRIVATE3_SET_GPR_SHIFT           (0U)
22685 /*! GPR - GP register
22686  */
22687 #define CCM_GPR_PRIVATE3_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK)
22688 /*! @} */
22689 
22690 /*! @name GPR_PRIVATE3_CLR - General Purpose Register */
22691 /*! @{ */
22692 
22693 #define CCM_GPR_PRIVATE3_CLR_GPR_MASK            (0xFFFFFFFFU)
22694 #define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT           (0U)
22695 /*! GPR - GP register
22696  */
22697 #define CCM_GPR_PRIVATE3_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK)
22698 /*! @} */
22699 
22700 /*! @name GPR_PRIVATE3_TOG - General Purpose Register */
22701 /*! @{ */
22702 
22703 #define CCM_GPR_PRIVATE3_TOG_GPR_MASK            (0xFFFFFFFFU)
22704 #define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT           (0U)
22705 /*! GPR - GP register
22706  */
22707 #define CCM_GPR_PRIVATE3_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK)
22708 /*! @} */
22709 
22710 /*! @name GPR_PRIVATE3_AUTHEN - GPR access control */
22711 /*! @{ */
22712 
22713 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK     (0x1U)
22714 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT    (0U)
22715 /*! TZ_USER - User access
22716  *  0b1..Clock can be changed in user mode.
22717  *  0b0..Clock cannot be changed in user mode.
22718  */
22719 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK)
22720 
22721 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK       (0x2U)
22722 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT      (1U)
22723 /*! TZ_NS - Non-secure access
22724  *  0b0..Cannot be changed in Non-secure mode.
22725  *  0b1..Can be changed in Non-secure mode.
22726  */
22727 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK)
22728 
22729 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK     (0x10U)
22730 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT    (4U)
22731 /*! LOCK_TZ - Lock truszone setting
22732  *  0b0..Trustzone setting is not locked.
22733  *  0b1..Trustzone setting is locked.
22734  */
22735 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK)
22736 
22737 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22738 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U)
22739 /*! WHITE_LIST - Whitelist
22740  *  0b0000..This domain is NOT allowed to change clock.
22741  *  0b0001..This domain is allowed to change clock.
22742  */
22743 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK)
22744 
22745 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22746 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT  (12U)
22747 /*! LOCK_LIST - Lock Whitelist
22748  *  0b0..Whitelist is not locked.
22749  *  0b1..Whitelist is locked.
22750  */
22751 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK)
22752 
22753 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22754 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22755 /*! DOMAIN_MODE - Low power and access control by Domain
22756  *  0b1..Clock works in Domain Mode.
22757  *  0b0..Clock does NOT work in Domain Mode.
22758  */
22759 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK)
22760 
22761 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22762 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT  (20U)
22763 /*! LOCK_MODE - Lock low power and access mode
22764  *  0b0..MODE is not locked.
22765  *  0b1..MODE is locked.
22766  */
22767 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK)
22768 /*! @} */
22769 
22770 /*! @name GPR_PRIVATE3_AUTHEN_SET - GPR access control */
22771 /*! @{ */
22772 
22773 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U)
22774 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U)
22775 /*! TZ_USER - User access
22776  */
22777 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK)
22778 
22779 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22780 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22781 /*! TZ_NS - Non-secure access
22782  */
22783 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK)
22784 
22785 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22786 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22787 /*! LOCK_TZ - Lock truszone setting
22788  */
22789 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK)
22790 
22791 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22792 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22793 /*! WHITE_LIST - Whitelist
22794  */
22795 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK)
22796 
22797 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22798 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22799 /*! LOCK_LIST - Lock Whitelist
22800  */
22801 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK)
22802 
22803 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22804 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22805 /*! DOMAIN_MODE - Low power and access control by Domain
22806  */
22807 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK)
22808 
22809 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22810 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22811 /*! LOCK_MODE - Lock low power and access mode
22812  */
22813 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK)
22814 /*! @} */
22815 
22816 /*! @name GPR_PRIVATE3_AUTHEN_CLR - GPR access control */
22817 /*! @{ */
22818 
22819 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22820 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22821 /*! TZ_USER - User access
22822  */
22823 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK)
22824 
22825 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22826 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22827 /*! TZ_NS - Non-secure access
22828  */
22829 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK)
22830 
22831 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22832 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22833 /*! LOCK_TZ - Lock truszone setting
22834  */
22835 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK)
22836 
22837 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22838 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22839 /*! WHITE_LIST - Whitelist
22840  */
22841 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK)
22842 
22843 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22844 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22845 /*! LOCK_LIST - Lock Whitelist
22846  */
22847 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK)
22848 
22849 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22850 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22851 /*! DOMAIN_MODE - Low power and access control by Domain
22852  */
22853 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK)
22854 
22855 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22856 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22857 /*! LOCK_MODE - Lock low power and access mode
22858  */
22859 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK)
22860 /*! @} */
22861 
22862 /*! @name GPR_PRIVATE3_AUTHEN_TOG - GPR access control */
22863 /*! @{ */
22864 
22865 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22866 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22867 /*! TZ_USER - User access
22868  */
22869 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK)
22870 
22871 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22872 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22873 /*! TZ_NS - Non-secure access
22874  */
22875 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK)
22876 
22877 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22878 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22879 /*! LOCK_TZ - Lock truszone setting
22880  */
22881 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK)
22882 
22883 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22884 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22885 /*! WHITE_LIST - Whitelist
22886  */
22887 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK)
22888 
22889 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22890 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22891 /*! LOCK_LIST - Lock Whitelist
22892  */
22893 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK)
22894 
22895 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22896 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22897 /*! DOMAIN_MODE - Low power and access control by Domain
22898  */
22899 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK)
22900 
22901 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22902 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22903 /*! LOCK_MODE - Lock low power and access mode
22904  */
22905 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK)
22906 /*! @} */
22907 
22908 /*! @name GPR_PRIVATE4 - General Purpose Register */
22909 /*! @{ */
22910 
22911 #define CCM_GPR_PRIVATE4_GPR_MASK                (0xFFFFFFFFU)
22912 #define CCM_GPR_PRIVATE4_GPR_SHIFT               (0U)
22913 /*! GPR - GP register
22914  */
22915 #define CCM_GPR_PRIVATE4_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK)
22916 /*! @} */
22917 
22918 /*! @name GPR_PRIVATE4_SET - General Purpose Register */
22919 /*! @{ */
22920 
22921 #define CCM_GPR_PRIVATE4_SET_GPR_MASK            (0xFFFFFFFFU)
22922 #define CCM_GPR_PRIVATE4_SET_GPR_SHIFT           (0U)
22923 /*! GPR - GP register
22924  */
22925 #define CCM_GPR_PRIVATE4_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK)
22926 /*! @} */
22927 
22928 /*! @name GPR_PRIVATE4_CLR - General Purpose Register */
22929 /*! @{ */
22930 
22931 #define CCM_GPR_PRIVATE4_CLR_GPR_MASK            (0xFFFFFFFFU)
22932 #define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT           (0U)
22933 /*! GPR - GP register
22934  */
22935 #define CCM_GPR_PRIVATE4_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK)
22936 /*! @} */
22937 
22938 /*! @name GPR_PRIVATE4_TOG - General Purpose Register */
22939 /*! @{ */
22940 
22941 #define CCM_GPR_PRIVATE4_TOG_GPR_MASK            (0xFFFFFFFFU)
22942 #define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT           (0U)
22943 /*! GPR - GP register
22944  */
22945 #define CCM_GPR_PRIVATE4_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK)
22946 /*! @} */
22947 
22948 /*! @name GPR_PRIVATE4_AUTHEN - GPR access control */
22949 /*! @{ */
22950 
22951 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK     (0x1U)
22952 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT    (0U)
22953 /*! TZ_USER - User access
22954  *  0b1..Clock can be changed in user mode.
22955  *  0b0..Clock cannot be changed in user mode.
22956  */
22957 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK)
22958 
22959 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK       (0x2U)
22960 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT      (1U)
22961 /*! TZ_NS - Non-secure access
22962  *  0b0..Cannot be changed in Non-secure mode.
22963  *  0b1..Can be changed in Non-secure mode.
22964  */
22965 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK)
22966 
22967 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK     (0x10U)
22968 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT    (4U)
22969 /*! LOCK_TZ - Lock truszone setting
22970  *  0b0..Trustzone setting is not locked.
22971  *  0b1..Trustzone setting is locked.
22972  */
22973 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK)
22974 
22975 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22976 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U)
22977 /*! WHITE_LIST - Whitelist
22978  *  0b0000..This domain is NOT allowed to change clock.
22979  *  0b0001..This domain is allowed to change clock.
22980  */
22981 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK)
22982 
22983 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22984 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT  (12U)
22985 /*! LOCK_LIST - Lock Whitelist
22986  *  0b0..Whitelist is not locked.
22987  *  0b1..Whitelist is locked.
22988  */
22989 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK)
22990 
22991 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22992 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22993 /*! DOMAIN_MODE - Low power and access control by Domain
22994  *  0b1..Clock works in Domain Mode.
22995  *  0b0..Clock does NOT work in Domain Mode.
22996  */
22997 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK)
22998 
22999 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23000 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT  (20U)
23001 /*! LOCK_MODE - Lock low power and access mode
23002  *  0b0..MODE is not locked.
23003  *  0b1..MODE is locked.
23004  */
23005 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK)
23006 /*! @} */
23007 
23008 /*! @name GPR_PRIVATE4_AUTHEN_SET - GPR access control */
23009 /*! @{ */
23010 
23011 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U)
23012 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U)
23013 /*! TZ_USER - User access
23014  */
23015 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK)
23016 
23017 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23018 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23019 /*! TZ_NS - Non-secure access
23020  */
23021 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK)
23022 
23023 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23024 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23025 /*! LOCK_TZ - Lock truszone setting
23026  */
23027 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK)
23028 
23029 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23030 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23031 /*! WHITE_LIST - Whitelist
23032  */
23033 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK)
23034 
23035 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23036 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23037 /*! LOCK_LIST - Lock Whitelist
23038  */
23039 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK)
23040 
23041 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23042 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23043 /*! DOMAIN_MODE - Low power and access control by Domain
23044  */
23045 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK)
23046 
23047 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23048 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23049 /*! LOCK_MODE - Lock low power and access mode
23050  */
23051 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK)
23052 /*! @} */
23053 
23054 /*! @name GPR_PRIVATE4_AUTHEN_CLR - GPR access control */
23055 /*! @{ */
23056 
23057 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23058 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23059 /*! TZ_USER - User access
23060  */
23061 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK)
23062 
23063 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23064 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23065 /*! TZ_NS - Non-secure access
23066  */
23067 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK)
23068 
23069 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23070 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23071 /*! LOCK_TZ - Lock truszone setting
23072  */
23073 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK)
23074 
23075 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23076 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23077 /*! WHITE_LIST - Whitelist
23078  */
23079 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK)
23080 
23081 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23082 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23083 /*! LOCK_LIST - Lock Whitelist
23084  */
23085 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK)
23086 
23087 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23088 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23089 /*! DOMAIN_MODE - Low power and access control by Domain
23090  */
23091 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK)
23092 
23093 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23094 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23095 /*! LOCK_MODE - Lock low power and access mode
23096  */
23097 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK)
23098 /*! @} */
23099 
23100 /*! @name GPR_PRIVATE4_AUTHEN_TOG - GPR access control */
23101 /*! @{ */
23102 
23103 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23104 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23105 /*! TZ_USER - User access
23106  */
23107 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK)
23108 
23109 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23110 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23111 /*! TZ_NS - Non-secure access
23112  */
23113 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK)
23114 
23115 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23116 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23117 /*! LOCK_TZ - Lock truszone setting
23118  */
23119 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK)
23120 
23121 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23122 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23123 /*! WHITE_LIST - Whitelist
23124  */
23125 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK)
23126 
23127 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23128 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23129 /*! LOCK_LIST - Lock Whitelist
23130  */
23131 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK)
23132 
23133 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23134 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23135 /*! DOMAIN_MODE - Low power and access control by Domain
23136  */
23137 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK)
23138 
23139 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23140 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23141 /*! LOCK_MODE - Lock low power and access mode
23142  */
23143 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK)
23144 /*! @} */
23145 
23146 /*! @name GPR_PRIVATE5 - General Purpose Register */
23147 /*! @{ */
23148 
23149 #define CCM_GPR_PRIVATE5_GPR_MASK                (0xFFFFFFFFU)
23150 #define CCM_GPR_PRIVATE5_GPR_SHIFT               (0U)
23151 /*! GPR - GP register
23152  */
23153 #define CCM_GPR_PRIVATE5_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK)
23154 /*! @} */
23155 
23156 /*! @name GPR_PRIVATE5_SET - General Purpose Register */
23157 /*! @{ */
23158 
23159 #define CCM_GPR_PRIVATE5_SET_GPR_MASK            (0xFFFFFFFFU)
23160 #define CCM_GPR_PRIVATE5_SET_GPR_SHIFT           (0U)
23161 /*! GPR - GP register
23162  */
23163 #define CCM_GPR_PRIVATE5_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK)
23164 /*! @} */
23165 
23166 /*! @name GPR_PRIVATE5_CLR - General Purpose Register */
23167 /*! @{ */
23168 
23169 #define CCM_GPR_PRIVATE5_CLR_GPR_MASK            (0xFFFFFFFFU)
23170 #define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT           (0U)
23171 /*! GPR - GP register
23172  */
23173 #define CCM_GPR_PRIVATE5_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK)
23174 /*! @} */
23175 
23176 /*! @name GPR_PRIVATE5_TOG - General Purpose Register */
23177 /*! @{ */
23178 
23179 #define CCM_GPR_PRIVATE5_TOG_GPR_MASK            (0xFFFFFFFFU)
23180 #define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT           (0U)
23181 /*! GPR - GP register
23182  */
23183 #define CCM_GPR_PRIVATE5_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK)
23184 /*! @} */
23185 
23186 /*! @name GPR_PRIVATE5_AUTHEN - GPR access control */
23187 /*! @{ */
23188 
23189 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK     (0x1U)
23190 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT    (0U)
23191 /*! TZ_USER - User access
23192  *  0b1..Clock can be changed in user mode.
23193  *  0b0..Clock cannot be changed in user mode.
23194  */
23195 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK)
23196 
23197 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK       (0x2U)
23198 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT      (1U)
23199 /*! TZ_NS - Non-secure access
23200  *  0b0..Cannot be changed in Non-secure mode.
23201  *  0b1..Can be changed in Non-secure mode.
23202  */
23203 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK)
23204 
23205 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK     (0x10U)
23206 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT    (4U)
23207 /*! LOCK_TZ - Lock truszone setting
23208  *  0b0..Trustzone setting is not locked.
23209  *  0b1..Trustzone setting is locked.
23210  */
23211 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK)
23212 
23213 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK  (0xF00U)
23214 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U)
23215 /*! WHITE_LIST - Whitelist
23216  *  0b0000..This domain is NOT allowed to change clock.
23217  *  0b0001..This domain is allowed to change clock.
23218  */
23219 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK)
23220 
23221 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK   (0x1000U)
23222 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT  (12U)
23223 /*! LOCK_LIST - Lock Whitelist
23224  *  0b0..Whitelist is not locked.
23225  *  0b1..Whitelist is locked.
23226  */
23227 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK)
23228 
23229 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23230 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23231 /*! DOMAIN_MODE - Low power and access control by Domain
23232  *  0b1..Clock works in Domain Mode.
23233  *  0b0..Clock does NOT work in Domain Mode.
23234  */
23235 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK)
23236 
23237 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23238 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT  (20U)
23239 /*! LOCK_MODE - Lock low power and access mode
23240  *  0b0..MODE is not locked.
23241  *  0b1..MODE is locked.
23242  */
23243 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK)
23244 /*! @} */
23245 
23246 /*! @name GPR_PRIVATE5_AUTHEN_SET - GPR access control */
23247 /*! @{ */
23248 
23249 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U)
23250 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U)
23251 /*! TZ_USER - User access
23252  */
23253 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK)
23254 
23255 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23256 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23257 /*! TZ_NS - Non-secure access
23258  */
23259 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK)
23260 
23261 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23262 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23263 /*! LOCK_TZ - Lock truszone setting
23264  */
23265 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK)
23266 
23267 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23268 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23269 /*! WHITE_LIST - Whitelist
23270  */
23271 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK)
23272 
23273 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23274 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23275 /*! LOCK_LIST - Lock Whitelist
23276  */
23277 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK)
23278 
23279 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23280 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23281 /*! DOMAIN_MODE - Low power and access control by Domain
23282  */
23283 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK)
23284 
23285 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23286 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23287 /*! LOCK_MODE - Lock low power and access mode
23288  */
23289 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK)
23290 /*! @} */
23291 
23292 /*! @name GPR_PRIVATE5_AUTHEN_CLR - GPR access control */
23293 /*! @{ */
23294 
23295 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23296 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23297 /*! TZ_USER - User access
23298  */
23299 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK)
23300 
23301 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23302 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23303 /*! TZ_NS - Non-secure access
23304  */
23305 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK)
23306 
23307 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23308 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23309 /*! LOCK_TZ - Lock truszone setting
23310  */
23311 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK)
23312 
23313 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23314 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23315 /*! WHITE_LIST - Whitelist
23316  */
23317 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK)
23318 
23319 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23320 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23321 /*! LOCK_LIST - Lock Whitelist
23322  */
23323 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK)
23324 
23325 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23326 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23327 /*! DOMAIN_MODE - Low power and access control by Domain
23328  */
23329 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK)
23330 
23331 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23332 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23333 /*! LOCK_MODE - Lock low power and access mode
23334  */
23335 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK)
23336 /*! @} */
23337 
23338 /*! @name GPR_PRIVATE5_AUTHEN_TOG - GPR access control */
23339 /*! @{ */
23340 
23341 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23342 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23343 /*! TZ_USER - User access
23344  */
23345 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK)
23346 
23347 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23348 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23349 /*! TZ_NS - Non-secure access
23350  */
23351 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK)
23352 
23353 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23354 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23355 /*! LOCK_TZ - Lock truszone setting
23356  */
23357 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK)
23358 
23359 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23360 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23361 /*! WHITE_LIST - Whitelist
23362  */
23363 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK)
23364 
23365 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23366 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23367 /*! LOCK_LIST - Lock Whitelist
23368  */
23369 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK)
23370 
23371 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23372 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23373 /*! DOMAIN_MODE - Low power and access control by Domain
23374  */
23375 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK)
23376 
23377 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23378 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23379 /*! LOCK_MODE - Lock low power and access mode
23380  */
23381 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK)
23382 /*! @} */
23383 
23384 /*! @name GPR_PRIVATE6 - General Purpose Register */
23385 /*! @{ */
23386 
23387 #define CCM_GPR_PRIVATE6_GPR_MASK                (0xFFFFFFFFU)
23388 #define CCM_GPR_PRIVATE6_GPR_SHIFT               (0U)
23389 /*! GPR - GP register
23390  */
23391 #define CCM_GPR_PRIVATE6_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK)
23392 /*! @} */
23393 
23394 /*! @name GPR_PRIVATE6_SET - General Purpose Register */
23395 /*! @{ */
23396 
23397 #define CCM_GPR_PRIVATE6_SET_GPR_MASK            (0xFFFFFFFFU)
23398 #define CCM_GPR_PRIVATE6_SET_GPR_SHIFT           (0U)
23399 /*! GPR - GP register
23400  */
23401 #define CCM_GPR_PRIVATE6_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK)
23402 /*! @} */
23403 
23404 /*! @name GPR_PRIVATE6_CLR - General Purpose Register */
23405 /*! @{ */
23406 
23407 #define CCM_GPR_PRIVATE6_CLR_GPR_MASK            (0xFFFFFFFFU)
23408 #define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT           (0U)
23409 /*! GPR - GP register
23410  */
23411 #define CCM_GPR_PRIVATE6_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK)
23412 /*! @} */
23413 
23414 /*! @name GPR_PRIVATE6_TOG - General Purpose Register */
23415 /*! @{ */
23416 
23417 #define CCM_GPR_PRIVATE6_TOG_GPR_MASK            (0xFFFFFFFFU)
23418 #define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT           (0U)
23419 /*! GPR - GP register
23420  */
23421 #define CCM_GPR_PRIVATE6_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK)
23422 /*! @} */
23423 
23424 /*! @name GPR_PRIVATE6_AUTHEN - GPR access control */
23425 /*! @{ */
23426 
23427 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK     (0x1U)
23428 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT    (0U)
23429 /*! TZ_USER - User access
23430  *  0b1..Clock can be changed in user mode.
23431  *  0b0..Clock cannot be changed in user mode.
23432  */
23433 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK)
23434 
23435 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK       (0x2U)
23436 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT      (1U)
23437 /*! TZ_NS - Non-secure access
23438  *  0b0..Cannot be changed in Non-secure mode.
23439  *  0b1..Can be changed in Non-secure mode.
23440  */
23441 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK)
23442 
23443 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK     (0x10U)
23444 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT    (4U)
23445 /*! LOCK_TZ - Lock truszone setting
23446  *  0b0..Trustzone setting is not locked.
23447  *  0b1..Trustzone setting is locked.
23448  */
23449 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK)
23450 
23451 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK  (0xF00U)
23452 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U)
23453 /*! WHITE_LIST - Whitelist
23454  *  0b0000..This domain is NOT allowed to change clock.
23455  *  0b0001..This domain is allowed to change clock.
23456  */
23457 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK)
23458 
23459 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK   (0x1000U)
23460 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT  (12U)
23461 /*! LOCK_LIST - Lock Whitelist
23462  *  0b0..Whitelist is not locked.
23463  *  0b1..Whitelist is locked.
23464  */
23465 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK)
23466 
23467 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23468 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23469 /*! DOMAIN_MODE - Low power and access control by Domain
23470  *  0b1..Clock works in Domain Mode.
23471  *  0b0..Clock does NOT work in Domain Mode.
23472  */
23473 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK)
23474 
23475 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23476 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT  (20U)
23477 /*! LOCK_MODE - Lock low power and access mode
23478  *  0b0..MODE is not locked.
23479  *  0b1..MODE is locked.
23480  */
23481 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK)
23482 /*! @} */
23483 
23484 /*! @name GPR_PRIVATE6_AUTHEN_SET - GPR access control */
23485 /*! @{ */
23486 
23487 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U)
23488 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U)
23489 /*! TZ_USER - User access
23490  */
23491 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK)
23492 
23493 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23494 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23495 /*! TZ_NS - Non-secure access
23496  */
23497 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK)
23498 
23499 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23500 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23501 /*! LOCK_TZ - Lock truszone setting
23502  */
23503 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK)
23504 
23505 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23506 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23507 /*! WHITE_LIST - Whitelist
23508  */
23509 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK)
23510 
23511 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23512 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23513 /*! LOCK_LIST - Lock Whitelist
23514  */
23515 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK)
23516 
23517 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23518 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23519 /*! DOMAIN_MODE - Low power and access control by Domain
23520  */
23521 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK)
23522 
23523 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23524 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23525 /*! LOCK_MODE - Lock low power and access mode
23526  */
23527 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK)
23528 /*! @} */
23529 
23530 /*! @name GPR_PRIVATE6_AUTHEN_CLR - GPR access control */
23531 /*! @{ */
23532 
23533 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23534 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23535 /*! TZ_USER - User access
23536  */
23537 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK)
23538 
23539 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23540 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23541 /*! TZ_NS - Non-secure access
23542  */
23543 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK)
23544 
23545 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23546 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23547 /*! LOCK_TZ - Lock truszone setting
23548  */
23549 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK)
23550 
23551 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23552 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23553 /*! WHITE_LIST - Whitelist
23554  */
23555 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK)
23556 
23557 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23558 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23559 /*! LOCK_LIST - Lock Whitelist
23560  */
23561 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK)
23562 
23563 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23564 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23565 /*! DOMAIN_MODE - Low power and access control by Domain
23566  */
23567 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK)
23568 
23569 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23570 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23571 /*! LOCK_MODE - Lock low power and access mode
23572  */
23573 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK)
23574 /*! @} */
23575 
23576 /*! @name GPR_PRIVATE6_AUTHEN_TOG - GPR access control */
23577 /*! @{ */
23578 
23579 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23580 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23581 /*! TZ_USER - User access
23582  */
23583 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK)
23584 
23585 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23586 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23587 /*! TZ_NS - Non-secure access
23588  */
23589 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK)
23590 
23591 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23592 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23593 /*! LOCK_TZ - Lock truszone setting
23594  */
23595 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK)
23596 
23597 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23598 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23599 /*! WHITE_LIST - Whitelist
23600  */
23601 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK)
23602 
23603 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23604 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23605 /*! LOCK_LIST - Lock Whitelist
23606  */
23607 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK)
23608 
23609 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23610 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23611 /*! DOMAIN_MODE - Low power and access control by Domain
23612  */
23613 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK)
23614 
23615 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23616 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23617 /*! LOCK_MODE - Lock low power and access mode
23618  */
23619 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK)
23620 /*! @} */
23621 
23622 /*! @name GPR_PRIVATE7 - General Purpose Register */
23623 /*! @{ */
23624 
23625 #define CCM_GPR_PRIVATE7_GPR_MASK                (0xFFFFFFFFU)
23626 #define CCM_GPR_PRIVATE7_GPR_SHIFT               (0U)
23627 /*! GPR - GP register
23628  */
23629 #define CCM_GPR_PRIVATE7_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK)
23630 /*! @} */
23631 
23632 /*! @name GPR_PRIVATE7_SET - General Purpose Register */
23633 /*! @{ */
23634 
23635 #define CCM_GPR_PRIVATE7_SET_GPR_MASK            (0xFFFFFFFFU)
23636 #define CCM_GPR_PRIVATE7_SET_GPR_SHIFT           (0U)
23637 /*! GPR - GP register
23638  */
23639 #define CCM_GPR_PRIVATE7_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK)
23640 /*! @} */
23641 
23642 /*! @name GPR_PRIVATE7_CLR - General Purpose Register */
23643 /*! @{ */
23644 
23645 #define CCM_GPR_PRIVATE7_CLR_GPR_MASK            (0xFFFFFFFFU)
23646 #define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT           (0U)
23647 /*! GPR - GP register
23648  */
23649 #define CCM_GPR_PRIVATE7_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK)
23650 /*! @} */
23651 
23652 /*! @name GPR_PRIVATE7_TOG - General Purpose Register */
23653 /*! @{ */
23654 
23655 #define CCM_GPR_PRIVATE7_TOG_GPR_MASK            (0xFFFFFFFFU)
23656 #define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT           (0U)
23657 /*! GPR - GP register
23658  */
23659 #define CCM_GPR_PRIVATE7_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK)
23660 /*! @} */
23661 
23662 /*! @name GPR_PRIVATE7_AUTHEN - GPR access control */
23663 /*! @{ */
23664 
23665 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK     (0x1U)
23666 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT    (0U)
23667 /*! TZ_USER - User access
23668  *  0b1..Clock can be changed in user mode.
23669  *  0b0..Clock cannot be changed in user mode.
23670  */
23671 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK)
23672 
23673 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK       (0x2U)
23674 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT      (1U)
23675 /*! TZ_NS - Non-secure access
23676  *  0b0..Cannot be changed in Non-secure mode.
23677  *  0b1..Can be changed in Non-secure mode.
23678  */
23679 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK)
23680 
23681 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK     (0x10U)
23682 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT    (4U)
23683 /*! LOCK_TZ - Lock truszone setting
23684  *  0b0..Trustzone setting is not locked.
23685  *  0b1..Trustzone setting is locked.
23686  */
23687 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK)
23688 
23689 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK  (0xF00U)
23690 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U)
23691 /*! WHITE_LIST - Whitelist
23692  *  0b0000..This domain is NOT allowed to change clock.
23693  *  0b0001..This domain is allowed to change clock.
23694  */
23695 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK)
23696 
23697 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK   (0x1000U)
23698 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT  (12U)
23699 /*! LOCK_LIST - Lock Whitelist
23700  *  0b0..Whitelist is not locked.
23701  *  0b1..Whitelist is locked.
23702  */
23703 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK)
23704 
23705 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23706 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23707 /*! DOMAIN_MODE - Low power and access control by Domain
23708  *  0b1..Clock works in Domain Mode.
23709  *  0b0..Clock does NOT work in Domain Mode.
23710  */
23711 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK)
23712 
23713 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23714 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT  (20U)
23715 /*! LOCK_MODE - Lock low power and access mode
23716  *  0b0..MODE is not locked.
23717  *  0b1..MODE is locked.
23718  */
23719 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK)
23720 /*! @} */
23721 
23722 /*! @name GPR_PRIVATE7_AUTHEN_SET - GPR access control */
23723 /*! @{ */
23724 
23725 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U)
23726 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U)
23727 /*! TZ_USER - User access
23728  */
23729 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK)
23730 
23731 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23732 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23733 /*! TZ_NS - Non-secure access
23734  */
23735 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK)
23736 
23737 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23738 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23739 /*! LOCK_TZ - Lock truszone setting
23740  */
23741 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK)
23742 
23743 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23744 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23745 /*! WHITE_LIST - Whitelist
23746  */
23747 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK)
23748 
23749 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23750 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23751 /*! LOCK_LIST - Lock Whitelist
23752  */
23753 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK)
23754 
23755 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23756 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23757 /*! DOMAIN_MODE - Low power and access control by Domain
23758  */
23759 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK)
23760 
23761 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23762 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23763 /*! LOCK_MODE - Lock low power and access mode
23764  */
23765 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK)
23766 /*! @} */
23767 
23768 /*! @name GPR_PRIVATE7_AUTHEN_CLR - GPR access control */
23769 /*! @{ */
23770 
23771 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23772 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23773 /*! TZ_USER - User access
23774  */
23775 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK)
23776 
23777 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23778 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23779 /*! TZ_NS - Non-secure access
23780  */
23781 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK)
23782 
23783 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23784 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23785 /*! LOCK_TZ - Lock truszone setting
23786  */
23787 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK)
23788 
23789 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23790 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23791 /*! WHITE_LIST - Whitelist
23792  */
23793 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK)
23794 
23795 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23796 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23797 /*! LOCK_LIST - Lock Whitelist
23798  */
23799 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK)
23800 
23801 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23802 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23803 /*! DOMAIN_MODE - Low power and access control by Domain
23804  */
23805 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK)
23806 
23807 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23808 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23809 /*! LOCK_MODE - Lock low power and access mode
23810  */
23811 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK)
23812 /*! @} */
23813 
23814 /*! @name GPR_PRIVATE7_AUTHEN_TOG - GPR access control */
23815 /*! @{ */
23816 
23817 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23818 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23819 /*! TZ_USER - User access
23820  */
23821 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK)
23822 
23823 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23824 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23825 /*! TZ_NS - Non-secure access
23826  */
23827 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK)
23828 
23829 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23830 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23831 /*! LOCK_TZ - Lock truszone setting
23832  */
23833 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK)
23834 
23835 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23836 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23837 /*! WHITE_LIST - Whitelist
23838  */
23839 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK)
23840 
23841 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23842 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23843 /*! LOCK_LIST - Lock Whitelist
23844  */
23845 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK)
23846 
23847 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23848 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23849 /*! DOMAIN_MODE - Low power and access control by Domain
23850  */
23851 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK)
23852 
23853 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23854 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23855 /*! LOCK_MODE - Lock low power and access mode
23856  */
23857 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK)
23858 /*! @} */
23859 
23860 /*! @name OSCPLL_DIRECT - Clock source direct control */
23861 /*! @{ */
23862 
23863 #define CCM_OSCPLL_DIRECT_ON_MASK                (0x1U)
23864 #define CCM_OSCPLL_DIRECT_ON_SHIFT               (0U)
23865 /*! ON - turn on clock source
23866  *  0b0..OSCPLL is OFF
23867  *  0b1..OSCPLL is ON
23868  */
23869 #define CCM_OSCPLL_DIRECT_ON(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
23870 /*! @} */
23871 
23872 /* The count of CCM_OSCPLL_DIRECT */
23873 #define CCM_OSCPLL_DIRECT_COUNT                  (29U)
23874 
23875 /*! @name OSCPLL_DOMAIN - Clock source domain control */
23876 /*! @{ */
23877 
23878 #define CCM_OSCPLL_DOMAIN_LEVEL_MASK             (0x7U)
23879 #define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT            (0U)
23880 /*! LEVEL - Current dependence level
23881  *  0b000..This clock source is not needed in any mode, and can be turned off
23882  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23883  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23884  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23885  *  0b100..This clock source is always on in any mode (including SUSPEND)
23886  *  0b101, 0b110, 0b111..Reserved
23887  */
23888 #define CCM_OSCPLL_DOMAIN_LEVEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK)
23889 
23890 #define CCM_OSCPLL_DOMAIN_LEVEL0_MASK            (0x70000U)
23891 #define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT           (16U)
23892 /*! LEVEL0 - Dependence level
23893  *  0b000..This clock source is not needed in any mode, and can be turned off
23894  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23895  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23896  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23897  *  0b100..This clock source is always on in any mode (including SUSPEND)
23898  *  0b101, 0b110, 0b111..Reserved
23899  */
23900 #define CCM_OSCPLL_DOMAIN_LEVEL0(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK)
23901 
23902 #define CCM_OSCPLL_DOMAIN_LEVEL1_MASK            (0x700000U)
23903 #define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT           (20U)
23904 /*! LEVEL1 - Depend level
23905  *  0b000..This clock source is not needed in any mode, and can be turned off
23906  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23907  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23908  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23909  *  0b100..This clock source is always on in any mode (including SUSPEND)
23910  *  0b101, 0b110, 0b111..Reserved
23911  */
23912 #define CCM_OSCPLL_DOMAIN_LEVEL1(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK)
23913 
23914 #define CCM_OSCPLL_DOMAIN_LEVEL2_MASK            (0x7000000U)
23915 #define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT           (24U)
23916 /*! LEVEL2 - Depend level
23917  *  0b000..This clock source is not needed in any mode, and can be turned off
23918  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23919  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23920  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23921  *  0b100..This clock source is always on in any mode (including SUSPEND)
23922  *  0b101, 0b110, 0b111..Reserved
23923  */
23924 #define CCM_OSCPLL_DOMAIN_LEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK)
23925 
23926 #define CCM_OSCPLL_DOMAIN_LEVEL3_MASK            (0x70000000U)
23927 #define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT           (28U)
23928 /*! LEVEL3 - Depend level
23929  *  0b000..This clock source is not needed in any mode, and can be turned off
23930  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23931  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23932  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23933  *  0b100..This clock source is always on in any mode (including SUSPEND)
23934  *  0b101, 0b110, 0b111..Reserved
23935  */
23936 #define CCM_OSCPLL_DOMAIN_LEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK)
23937 /*! @} */
23938 
23939 /* The count of CCM_OSCPLL_DOMAIN */
23940 #define CCM_OSCPLL_DOMAIN_COUNT                  (29U)
23941 
23942 /*! @name OSCPLL_SETPOINT - Clock source Setpoint setting */
23943 /*! @{ */
23944 
23945 #define CCM_OSCPLL_SETPOINT_SETPOINT_MASK        (0xFFFFU)
23946 #define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT       (0U)
23947 /*! SETPOINT - Setpoint
23948  */
23949 #define CCM_OSCPLL_SETPOINT_SETPOINT(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK)
23950 
23951 #define CCM_OSCPLL_SETPOINT_STANDBY_MASK         (0xFFFF0000U)
23952 #define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT        (16U)
23953 /*! STANDBY - Standby
23954  */
23955 #define CCM_OSCPLL_SETPOINT_STANDBY(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK)
23956 /*! @} */
23957 
23958 /* The count of CCM_OSCPLL_SETPOINT */
23959 #define CCM_OSCPLL_SETPOINT_COUNT                (29U)
23960 
23961 /*! @name OSCPLL_STATUS0 - Clock source working status */
23962 /*! @{ */
23963 
23964 #define CCM_OSCPLL_STATUS0_ON_MASK               (0x1U)
23965 #define CCM_OSCPLL_STATUS0_ON_SHIFT              (0U)
23966 /*! ON - Clock source current state
23967  *  0b0..Clock source is OFF
23968  *  0b1..Clock source is ON
23969  */
23970 #define CCM_OSCPLL_STATUS0_ON(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
23971 
23972 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK     (0x10U)
23973 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT    (4U)
23974 /*! STATUS_EARLY - Clock source active
23975  *  0b1..Clock source is active
23976  *  0b0..Clock source is not active
23977  */
23978 #define CCM_OSCPLL_STATUS0_STATUS_EARLY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
23979 
23980 #define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK      (0x20U)
23981 #define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT     (5U)
23982 /*! STATUS_LATE - Clock source ready
23983  *  0b1..Clock source is ready to use
23984  *  0b0..Clock source is not ready to use
23985  */
23986 #define CCM_OSCPLL_STATUS0_STATUS_LATE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
23987 
23988 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK    (0xF00U)
23989 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT   (8U)
23990 /*! ACTIVE_DOMAIN - Domains that own this clock source
23991  *  0b0000..Clock not owned by any domain
23992  *  0b0001..Clock owned by Domain0
23993  *  0b0010..Clock owned by Domain1
23994  *  0b0011..Clock owned by Domain0 and Domain1
23995  *  0b0100..Clock owned by Domain2
23996  *  0b0101..Clock owned by Domain0 and Domain2
23997  *  0b0110..Clock owned by Domain1 and Domain2
23998  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
23999  *  0b1000..Clock owned by Domain3
24000  *  0b1001..Clock owned by Domain0 and Domain3
24001  *  0b1010..Clock owned by Domain1 and Domain3
24002  *  0b1011..Clock owned by Domain2 and Domain3
24003  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
24004  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
24005  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
24006  *  0b1111..Clock owned by all domains
24007  */
24008 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK)
24009 
24010 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK    (0xF000U)
24011 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT   (12U)
24012 /*! DOMAIN_ENABLE - Enable status from each domain
24013  *  0b0000..No domain request
24014  *  0b0001..Request from Domain0
24015  *  0b0010..Request from Domain1
24016  *  0b0011..Request from Domain0 and Domain1
24017  *  0b0100..Request from Domain2
24018  *  0b0101..Request from Domain0 and Domain2
24019  *  0b0110..Request from Domain1 and Domain2
24020  *  0b0111..Request from Domain0, Domain1 and Domain 2
24021  *  0b1000..Request from Domain3
24022  *  0b1001..Request from Domain0 and Domain3
24023  *  0b1010..Request from Domain1 and Domain3
24024  *  0b1011..Request from Domain2 and Domain3
24025  *  0b1100..Request from Domain0, Domain 1, and Domain3
24026  *  0b1101..Request from Domain0, Domain 2, and Domain3
24027  *  0b1110..Request from Domain1, Domain 2, and Domain3
24028  *  0b1111..Request from all domains
24029  */
24030 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK)
24031 
24032 #define CCM_OSCPLL_STATUS0_IN_USE_MASK           (0x10000000U)
24033 #define CCM_OSCPLL_STATUS0_IN_USE_SHIFT          (28U)
24034 /*! IN_USE - In use
24035  *  0b1..Clock source is being used by clock roots
24036  *  0b0..Clock source is not being used by clock roots
24037  */
24038 #define CCM_OSCPLL_STATUS0_IN_USE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
24039 /*! @} */
24040 
24041 /* The count of CCM_OSCPLL_STATUS0 */
24042 #define CCM_OSCPLL_STATUS0_COUNT                 (29U)
24043 
24044 /*! @name OSCPLL_STATUS1 - Clock source low power status */
24045 /*! @{ */
24046 
24047 #define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK        (0x3U)
24048 #define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT       (0U)
24049 /*! CPU0_MODE - Domain0 Low Power Mode
24050  *  0b00..Run
24051  *  0b01..Wait
24052  *  0b10..Stop
24053  *  0b11..Suspend
24054  */
24055 #define CCM_OSCPLL_STATUS1_CPU0_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK)
24056 
24057 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
24058 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
24059 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
24060  *  0b1..Request from domain to enter Low Power Mode
24061  *  0b0..No request
24062  */
24063 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK)
24064 
24065 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK   (0x8U)
24066 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT  (3U)
24067 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
24068  *  0b1..Clock is gated-off
24069  *  0b0..Clock is not gated
24070  */
24071 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK)
24072 
24073 #define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK        (0x30U)
24074 #define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT       (4U)
24075 /*! CPU1_MODE - Domain1 Low Power Mode
24076  *  0b00..Run
24077  *  0b01..Wait
24078  *  0b10..Stop
24079  *  0b11..Suspend
24080  */
24081 #define CCM_OSCPLL_STATUS1_CPU1_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK)
24082 
24083 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
24084 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
24085 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
24086  *  0b1..Request from domain to enter Low Power Mode
24087  *  0b0..No request
24088  */
24089 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK)
24090 
24091 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK   (0x80U)
24092 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT  (7U)
24093 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
24094  *  0b1..Clock is gated-off
24095  *  0b0..Clock is not gated
24096  */
24097 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK)
24098 
24099 #define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK        (0x300U)
24100 #define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT       (8U)
24101 /*! CPU2_MODE - Domain2 Low Power Mode
24102  *  0b00..Run
24103  *  0b01..Wait
24104  *  0b10..Stop
24105  *  0b11..Suspend
24106  */
24107 #define CCM_OSCPLL_STATUS1_CPU2_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK)
24108 
24109 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
24110 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
24111 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
24112  *  0b1..Request from domain to enter Low Power Mode
24113  *  0b0..No request
24114  */
24115 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK)
24116 
24117 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK   (0x800U)
24118 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT  (11U)
24119 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
24120  *  0b1..Clock is gated-off
24121  *  0b0..Clock is not gated
24122  */
24123 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK)
24124 
24125 #define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK        (0x3000U)
24126 #define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT       (12U)
24127 /*! CPU3_MODE - Domain3 Low Power Mode
24128  *  0b00..Run
24129  *  0b01..Wait
24130  *  0b10..Stop
24131  *  0b11..Suspend
24132  */
24133 #define CCM_OSCPLL_STATUS1_CPU3_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK)
24134 
24135 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
24136 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
24137 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
24138  *  0b1..Request from domain to enter Low Power Mode
24139  *  0b0..No request
24140  */
24141 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK)
24142 
24143 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK   (0x8000U)
24144 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT  (15U)
24145 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
24146  *  0b1..Clock is gated-off
24147  *  0b0..Clock is not gated
24148  */
24149 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK)
24150 
24151 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK  (0xF0000U)
24152 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U)
24153 /*! TARGET_SETPOINT - Next Setpoint to change to
24154  */
24155 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK)
24156 
24157 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
24158 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
24159 /*! CURRENT_SETPOINT - Current Setpoint
24160  */
24161 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK)
24162 
24163 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
24164 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
24165 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
24166  *  0b1..Clock gate requested to be turned off
24167  *  0b0..No request
24168  */
24169 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK)
24170 
24171 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
24172 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
24173 /*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC Setpoint
24174  *  0b1..Clock source is turned off
24175  *  0b0..Clock source is not turned off
24176  */
24177 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK)
24178 
24179 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
24180 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
24181 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
24182  *  0b1..Clock gate requested to be turned on
24183  *  0b0..No request
24184  */
24185 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK)
24186 
24187 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
24188 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
24189 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
24190  *  0b1..Request to turn on clock gate
24191  *  0b0..No request
24192  */
24193 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK)
24194 
24195 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U)
24196 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U)
24197 /*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby
24198  *  0b1..Clock gate requested to be turned off
24199  *  0b0..No request
24200  */
24201 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK)
24202 
24203 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK  (0x20000000U)
24204 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U)
24205 /*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby
24206  *  0b1..Clock source is turned off
24207  *  0b0..Clock source is not turned off
24208  */
24209 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK)
24210 
24211 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U)
24212 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U)
24213 /*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby
24214  *  0b1..Request to turn on Clock gate is complete
24215  *  0b0..Request to turn on Clock gate is not complete
24216  */
24217 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK)
24218 
24219 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U)
24220 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U)
24221 /*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby
24222  *  0b1..Clock gate requested to be turned on
24223  *  0b0..No request
24224  */
24225 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK)
24226 /*! @} */
24227 
24228 /* The count of CCM_OSCPLL_STATUS1 */
24229 #define CCM_OSCPLL_STATUS1_COUNT                 (29U)
24230 
24231 /*! @name OSCPLL_CONFIG - Clock source configuration */
24232 /*! @{ */
24233 
24234 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK  (0x2U)
24235 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U)
24236 /*! AUTOMODE_PRESENT - Automode Present
24237  *  0b1..Present
24238  *  0b0..Not present
24239  */
24240 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK)
24241 
24242 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK  (0x10U)
24243 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
24244 /*! SETPOINT_PRESENT - Setpoint present
24245  *  0b1..Setpoint is implemented.
24246  *  0b0..Setpoint is not implemented.
24247  */
24248 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK)
24249 /*! @} */
24250 
24251 /* The count of CCM_OSCPLL_CONFIG */
24252 #define CCM_OSCPLL_CONFIG_COUNT                  (29U)
24253 
24254 /*! @name OSCPLL_AUTHEN - Clock source access control */
24255 /*! @{ */
24256 
24257 #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK           (0x1U)
24258 #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT          (0U)
24259 /*! TZ_USER - User access
24260  *  0b1..Clock can be changed in user mode.
24261  *  0b0..Clock cannot be changed in user mode.
24262  */
24263 #define CCM_OSCPLL_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
24264 
24265 #define CCM_OSCPLL_AUTHEN_TZ_NS_MASK             (0x2U)
24266 #define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT            (1U)
24267 /*! TZ_NS - Non-secure access
24268  *  0b0..Cannot be changed in Non-secure mode.
24269  *  0b1..Can be changed in Non-secure mode.
24270  */
24271 #define CCM_OSCPLL_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
24272 
24273 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK           (0x10U)
24274 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT          (4U)
24275 /*! LOCK_TZ - lock truszone setting
24276  *  0b0..Trustzone setting is not locked.
24277  *  0b1..Trustzone setting is locked.
24278  */
24279 #define CCM_OSCPLL_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
24280 
24281 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK        (0xF00U)
24282 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT       (8U)
24283 /*! WHITE_LIST - Whitelist
24284  */
24285 #define CCM_OSCPLL_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
24286 
24287 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK         (0x1000U)
24288 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT        (12U)
24289 /*! LOCK_LIST - Lock Whitelist
24290  *  0b0..Whitelist is not locked.
24291  *  0b1..Whitelist is locked.
24292  */
24293 #define CCM_OSCPLL_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
24294 
24295 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK       (0x10000U)
24296 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT      (16U)
24297 /*! DOMAIN_MODE - Low power and access control by domain
24298  *  0b1..Clock works in Domain Mode.
24299  *  0b0..Clock does not work in Domain Mode.
24300  */
24301 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK)
24302 
24303 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK     (0x20000U)
24304 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT    (17U)
24305 /*! SETPOINT_MODE - LPCG works in Setpoint controlled Mode.
24306  */
24307 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK)
24308 
24309 #define CCM_OSCPLL_AUTHEN_CPULPM_MASK            (0x40000U)
24310 #define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT           (18U)
24311 /*! CPULPM - CPU Low Power Mode
24312  *  0b1..PLL functions in Low Power Mode
24313  *  0b0..PLL does not function in Low power Mode
24314  */
24315 #define CCM_OSCPLL_AUTHEN_CPULPM(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK)
24316 
24317 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK         (0x100000U)
24318 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT        (20U)
24319 /*! LOCK_MODE - Lock low power and access mode
24320  *  0b0..MODE is not locked.
24321  *  0b1..MODE is locked.
24322  */
24323 #define CCM_OSCPLL_AUTHEN_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK)
24324 /*! @} */
24325 
24326 /* The count of CCM_OSCPLL_AUTHEN */
24327 #define CCM_OSCPLL_AUTHEN_COUNT                  (29U)
24328 
24329 /*! @name LPCG_DIRECT - LPCG direct control */
24330 /*! @{ */
24331 
24332 #define CCM_LPCG_DIRECT_ON_MASK                  (0x1U)
24333 #define CCM_LPCG_DIRECT_ON_SHIFT                 (0U)
24334 /*! ON - LPCG on
24335  *  0b0..LPCG is OFF.
24336  *  0b1..LPCG is ON.
24337  */
24338 #define CCM_LPCG_DIRECT_ON(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
24339 /*! @} */
24340 
24341 /* The count of CCM_LPCG_DIRECT */
24342 #define CCM_LPCG_DIRECT_COUNT                    (138U)
24343 
24344 /*! @name LPCG_DOMAIN - LPCG domain control */
24345 /*! @{ */
24346 
24347 #define CCM_LPCG_DOMAIN_LEVEL_MASK               (0x7U)
24348 #define CCM_LPCG_DOMAIN_LEVEL_SHIFT              (0U)
24349 /*! LEVEL - Current dependence level
24350  *  0b000..This clock source is not needed in any mode, and can be turned off
24351  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
24352  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
24353  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
24354  *  0b100..This clock source is always on in any mode (including SUSPEND)
24355  *  0b101, 0b110, 0b111..Reserved
24356  */
24357 #define CCM_LPCG_DOMAIN_LEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK)
24358 
24359 #define CCM_LPCG_DOMAIN_LEVEL0_MASK              (0x70000U)
24360 #define CCM_LPCG_DOMAIN_LEVEL0_SHIFT             (16U)
24361 /*! LEVEL0 - Depend level
24362  *  0b000..This clock source is not needed in any mode, and can be turned off
24363  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
24364  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
24365  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
24366  *  0b100..This clock source is always on in any mode (including SUSPEND)
24367  *  0b101, 0b110, 0b111..Reserved
24368  */
24369 #define CCM_LPCG_DOMAIN_LEVEL0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK)
24370 
24371 #define CCM_LPCG_DOMAIN_LEVEL1_MASK              (0x700000U)
24372 #define CCM_LPCG_DOMAIN_LEVEL1_SHIFT             (20U)
24373 /*! LEVEL1 - Depend level
24374  *  0b000..This clock source is not needed in any mode, and can be turned off
24375  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
24376  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
24377  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
24378  *  0b100..This clock source is always on in any mode (including SUSPEND)
24379  *  0b101, 0b110, 0b111..Reserved
24380  */
24381 #define CCM_LPCG_DOMAIN_LEVEL1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK)
24382 
24383 #define CCM_LPCG_DOMAIN_LEVEL2_MASK              (0x7000000U)
24384 #define CCM_LPCG_DOMAIN_LEVEL2_SHIFT             (24U)
24385 /*! LEVEL2 - Depend level
24386  *  0b000..This clock source is not needed in any mode, and can be turned off
24387  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
24388  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
24389  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
24390  *  0b100..This clock source is always on in any mode (including SUSPEND)
24391  *  0b101, 0b110, 0b111..Reserved
24392  */
24393 #define CCM_LPCG_DOMAIN_LEVEL2(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK)
24394 
24395 #define CCM_LPCG_DOMAIN_LEVEL3_MASK              (0x70000000U)
24396 #define CCM_LPCG_DOMAIN_LEVEL3_SHIFT             (28U)
24397 /*! LEVEL3 - Depend level
24398  *  0b000..This clock source is not needed in any mode, and can be turned off
24399  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
24400  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
24401  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
24402  *  0b100..This clock source is always on in any mode (including SUSPEND)
24403  *  0b101, 0b110, 0b111..Reserved
24404  */
24405 #define CCM_LPCG_DOMAIN_LEVEL3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK)
24406 /*! @} */
24407 
24408 /* The count of CCM_LPCG_DOMAIN */
24409 #define CCM_LPCG_DOMAIN_COUNT                    (138U)
24410 
24411 /*! @name LPCG_SETPOINT - LPCG Setpoint setting */
24412 /*! @{ */
24413 
24414 #define CCM_LPCG_SETPOINT_SETPOINT_MASK          (0xFFFFU)
24415 #define CCM_LPCG_SETPOINT_SETPOINT_SHIFT         (0U)
24416 /*! SETPOINT - Setpoints
24417  */
24418 #define CCM_LPCG_SETPOINT_SETPOINT(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK)
24419 
24420 #define CCM_LPCG_SETPOINT_STANDBY_MASK           (0xFFFF0000U)
24421 #define CCM_LPCG_SETPOINT_STANDBY_SHIFT          (16U)
24422 /*! STANDBY - Standby
24423  */
24424 #define CCM_LPCG_SETPOINT_STANDBY(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK)
24425 /*! @} */
24426 
24427 /* The count of CCM_LPCG_SETPOINT */
24428 #define CCM_LPCG_SETPOINT_COUNT                  (138U)
24429 
24430 /*! @name LPCG_STATUS0 - LPCG working status */
24431 /*! @{ */
24432 
24433 #define CCM_LPCG_STATUS0_ON_MASK                 (0x1U)
24434 #define CCM_LPCG_STATUS0_ON_SHIFT                (0U)
24435 /*! ON - LPCG current state
24436  *  0b0..LPCG is OFF.
24437  *  0b1..LPCG is ON.
24438  */
24439 #define CCM_LPCG_STATUS0_ON(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
24440 
24441 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK      (0xF00U)
24442 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT     (8U)
24443 /*! ACTIVE_DOMAIN - Domains that own this clock gate
24444  *  0b0000..Clock not owned by any domain
24445  *  0b0001..Clock owned by Domain0
24446  *  0b0010..Clock owned by Domain1
24447  *  0b0011..Clock owned by Domain0 and Domain1
24448  *  0b0100..Clock owned by Domain2
24449  *  0b0101..Clock owned by Domain0 and Domain2
24450  *  0b0110..Clock owned by Domain1 and Domain2
24451  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
24452  *  0b1000..Clock owned by Domain3
24453  *  0b1001..Clock owned by Domain0 and Domain3
24454  *  0b1010..Clock owned by Domain1 and Domain3
24455  *  0b1011..Clock owned by Domain2 and Domain3
24456  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
24457  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
24458  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
24459  *  0b1111..Clock owned by all domains
24460  */
24461 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK)
24462 
24463 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK      (0xF000U)
24464 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT     (12U)
24465 /*! DOMAIN_ENABLE - Enable status from each domain
24466  *  0b0000..No domain request
24467  *  0b0001..Request from Domain0
24468  *  0b0010..Request from Domain1
24469  *  0b0011..Request from Domain0 and Domain1
24470  *  0b0100..Request from Domain2
24471  *  0b0101..Request from Domain0 and Domain2
24472  *  0b0110..Request from Domain1 and Domain2
24473  *  0b0111..Request from Domain0, Domain1 and Domain 2
24474  *  0b1000..Request from Domain3
24475  *  0b1001..Request from Domain0 and Domain3
24476  *  0b1010..Request from Domain1 and Domain3
24477  *  0b1011..Request from Domain2 and Domain3
24478  *  0b1100..Request from Domain0, Domain 1, and Domain3
24479  *  0b1101..Request from Domain0, Domain 2, and Domain3
24480  *  0b1110..Request from Domain1, Domain 2, and Domain3
24481  *  0b1111..Request from all domains
24482  */
24483 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK)
24484 /*! @} */
24485 
24486 /* The count of CCM_LPCG_STATUS0 */
24487 #define CCM_LPCG_STATUS0_COUNT                   (138U)
24488 
24489 /*! @name LPCG_STATUS1 - LPCG low power status */
24490 /*! @{ */
24491 
24492 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK          (0x3U)
24493 #define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT         (0U)
24494 /*! CPU0_MODE - Domain0 Low Power Mode
24495  *  0b00..Run
24496  *  0b01..Wait
24497  *  0b10..Stop
24498  *  0b11..Suspend
24499  */
24500 #define CCM_LPCG_STATUS1_CPU0_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
24501 
24502 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK  (0x4U)
24503 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
24504 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
24505  *  0b1..Request from domain to enter Low Power Mode
24506  *  0b0..No request
24507  */
24508 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK)
24509 
24510 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK     (0x8U)
24511 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT    (3U)
24512 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
24513  *  0b1..Clock is gated-off
24514  *  0b0..Clock is not gated
24515  */
24516 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK)
24517 
24518 #define CCM_LPCG_STATUS1_CPU1_MODE_MASK          (0x30U)
24519 #define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT         (4U)
24520 /*! CPU1_MODE - Domain1 Low Power Mode
24521  *  0b00..Run
24522  *  0b01..Wait
24523  *  0b10..Stop
24524  *  0b11..Suspend
24525  */
24526 #define CCM_LPCG_STATUS1_CPU1_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK)
24527 
24528 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK  (0x40U)
24529 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
24530 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
24531  *  0b1..Request from domain to enter Low Power Mode
24532  *  0b0..No request
24533  */
24534 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK)
24535 
24536 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK     (0x80U)
24537 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT    (7U)
24538 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
24539  *  0b1..Clock is gated-off
24540  *  0b0..Clock is not gated
24541  */
24542 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK)
24543 
24544 #define CCM_LPCG_STATUS1_CPU2_MODE_MASK          (0x300U)
24545 #define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT         (8U)
24546 /*! CPU2_MODE - Domain2 Low Power Mode
24547  *  0b00..Run
24548  *  0b01..Wait
24549  *  0b10..Stop
24550  *  0b11..Suspend
24551  */
24552 #define CCM_LPCG_STATUS1_CPU2_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK)
24553 
24554 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK  (0x400U)
24555 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
24556 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
24557  *  0b1..Request from domain to enter Low Power Mode
24558  *  0b0..No request
24559  */
24560 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK)
24561 
24562 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK     (0x800U)
24563 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT    (11U)
24564 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
24565  *  0b1..Clock is gated-off
24566  *  0b0..Clock is not gated
24567  */
24568 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK)
24569 
24570 #define CCM_LPCG_STATUS1_CPU3_MODE_MASK          (0x3000U)
24571 #define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT         (12U)
24572 /*! CPU3_MODE - Domain3 Low Power Mode
24573  *  0b00..Run
24574  *  0b01..Wait
24575  *  0b10..Stop
24576  *  0b11..Suspend
24577  */
24578 #define CCM_LPCG_STATUS1_CPU3_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK)
24579 
24580 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK  (0x4000U)
24581 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
24582 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
24583  *  0b1..Request from domain to enter Low Power Mode
24584  *  0b0..No request
24585  */
24586 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK)
24587 
24588 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK     (0x8000U)
24589 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT    (15U)
24590 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
24591  *  0b1..Clock is gated-off
24592  *  0b0..Clock is not gated
24593  */
24594 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK)
24595 
24596 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK    (0xF0000U)
24597 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
24598 /*! TARGET_SETPOINT - Next Setpoint to change to
24599  */
24600 #define CCM_LPCG_STATUS1_TARGET_SETPOINT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK)
24601 
24602 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
24603 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT  (20U)
24604 /*! CURRENT_SETPOINT - Current Setpoint
24605  */
24606 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK)
24607 
24608 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
24609 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
24610 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
24611  *  0b1..Clock gate requested to be turned off
24612  *  0b0..No request
24613  */
24614 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK)
24615 
24616 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK  (0x2000000U)
24617 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
24618 /*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC Setpoint
24619  *  0b1..Clock gate is turned off
24620  *  0b0..Clock gate is not turned off
24621  */
24622 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK)
24623 
24624 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
24625 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
24626 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
24627  *  0b1..Clock gate requested to be turned on
24628  *  0b0..No request
24629  */
24630 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK)
24631 
24632 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK   (0x8000000U)
24633 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT  (27U)
24634 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
24635  *  0b1..Clock gate is turned on
24636  *  0b0..Clock gate is not turned on
24637  */
24638 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK)
24639 /*! @} */
24640 
24641 /* The count of CCM_LPCG_STATUS1 */
24642 #define CCM_LPCG_STATUS1_COUNT                   (138U)
24643 
24644 /*! @name LPCG_CONFIG - LPCG configuration */
24645 /*! @{ */
24646 
24647 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK    (0x10U)
24648 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
24649 /*! SETPOINT_PRESENT - Setpoint present
24650  *  0b1..Setpoint is implemented.
24651  *  0b0..Setpoint is not implemented.
24652  */
24653 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK)
24654 /*! @} */
24655 
24656 /* The count of CCM_LPCG_CONFIG */
24657 #define CCM_LPCG_CONFIG_COUNT                    (138U)
24658 
24659 /*! @name LPCG_AUTHEN - LPCG access control */
24660 /*! @{ */
24661 
24662 #define CCM_LPCG_AUTHEN_TZ_USER_MASK             (0x1U)
24663 #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT            (0U)
24664 /*! TZ_USER - User access
24665  *  0b1..LPCG can be changed in user mode.
24666  *  0b0..LPCG cannot be changed in user mode.
24667  */
24668 #define CCM_LPCG_AUTHEN_TZ_USER(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
24669 
24670 #define CCM_LPCG_AUTHEN_TZ_NS_MASK               (0x2U)
24671 #define CCM_LPCG_AUTHEN_TZ_NS_SHIFT              (1U)
24672 /*! TZ_NS - Non-secure access
24673  *  0b0..Cannot be changed in Non-secure mode.
24674  *  0b1..Can be changed in Non-secure mode.
24675  */
24676 #define CCM_LPCG_AUTHEN_TZ_NS(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
24677 
24678 #define CCM_LPCG_AUTHEN_LOCK_TZ_MASK             (0x10U)
24679 #define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT            (4U)
24680 /*! LOCK_TZ - lock truszone setting
24681  *  0b0..Trustzone setting is not locked.
24682  *  0b1..Trustzone setting is locked.
24683  */
24684 #define CCM_LPCG_AUTHEN_LOCK_TZ(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
24685 
24686 #define CCM_LPCG_AUTHEN_WHITE_LIST_MASK          (0xF00U)
24687 #define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT         (8U)
24688 /*! WHITE_LIST - Whitelist
24689  */
24690 #define CCM_LPCG_AUTHEN_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
24691 
24692 #define CCM_LPCG_AUTHEN_LOCK_LIST_MASK           (0x1000U)
24693 #define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT          (12U)
24694 /*! LOCK_LIST - Lock Whitelist
24695  *  0b0..Whitelist is not locked.
24696  *  0b1..Whitelist is locked.
24697  */
24698 #define CCM_LPCG_AUTHEN_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
24699 
24700 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK         (0x10000U)
24701 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT        (16U)
24702 /*! DOMAIN_MODE - Low power and access control by domain
24703  *  0b1..Clock works in Domain Mode
24704  *  0b0..Clock does not work in Domain Mode
24705  */
24706 #define CCM_LPCG_AUTHEN_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK)
24707 
24708 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK       (0x20000U)
24709 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT      (17U)
24710 /*! SETPOINT_MODE - Low power and access control by Setpoint
24711  *  0b1..LPCG is functioning in Setpoint controlled Mode
24712  *  0b0..LPCG is not functioning in Setpoint controlled Mode
24713  */
24714 #define CCM_LPCG_AUTHEN_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK)
24715 
24716 #define CCM_LPCG_AUTHEN_CPULPM_MASK              (0x40000U)
24717 #define CCM_LPCG_AUTHEN_CPULPM_SHIFT             (18U)
24718 /*! CPULPM - CPU Low Power Mode
24719  *  0b1..LPCG is functioning in Low Power Mode
24720  *  0b0..LPCG is not functioning in Low power Mode
24721  */
24722 #define CCM_LPCG_AUTHEN_CPULPM(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK)
24723 
24724 #define CCM_LPCG_AUTHEN_LOCK_MODE_MASK           (0x100000U)
24725 #define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT          (20U)
24726 /*! LOCK_MODE - Lock low power and access mode
24727  *  0b0..MODE is not locked.
24728  *  0b1..MODE is locked.
24729  */
24730 #define CCM_LPCG_AUTHEN_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK)
24731 /*! @} */
24732 
24733 /* The count of CCM_LPCG_AUTHEN */
24734 #define CCM_LPCG_AUTHEN_COUNT                    (138U)
24735 
24736 
24737 /*!
24738  * @}
24739  */ /* end of group CCM_Register_Masks */
24740 
24741 
24742 /* CCM - Peripheral instance base addresses */
24743 /** Peripheral CCM base address */
24744 #define CCM_BASE                                 (0x40CC0000u)
24745 /** Peripheral CCM base pointer */
24746 #define CCM                                      ((CCM_Type *)CCM_BASE)
24747 /** Array initializer of CCM peripheral base addresses */
24748 #define CCM_BASE_ADDRS                           { CCM_BASE }
24749 /** Array initializer of CCM peripheral base pointers */
24750 #define CCM_BASE_PTRS                            { CCM }
24751 
24752 /*!
24753  * @}
24754  */ /* end of group CCM_Peripheral_Access_Layer */
24755 
24756 
24757 /* ----------------------------------------------------------------------------
24758    -- CCM_OBS Peripheral Access Layer
24759    ---------------------------------------------------------------------------- */
24760 
24761 /*!
24762  * @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer
24763  * @{
24764  */
24765 
24766 /** CCM_OBS - Register Layout Typedef */
24767 typedef struct {
24768   struct {                                         /* offset: 0x0, array step: 0x80 */
24769     __IO uint32_t CONTROL;                           /**< Observe control, array offset: 0x0, array step: 0x80 */
24770     __IO uint32_t CONTROL_SET;                       /**< Observe control, array offset: 0x4, array step: 0x80 */
24771     __IO uint32_t CONTROL_CLR;                       /**< Observe control, array offset: 0x8, array step: 0x80 */
24772     __IO uint32_t CONTROL_TOG;                       /**< Observe control, array offset: 0xC, array step: 0x80 */
24773          uint8_t RESERVED_0[16];
24774     __I  uint32_t STATUS0;                           /**< Observe status, array offset: 0x20, array step: 0x80 */
24775          uint8_t RESERVED_1[12];
24776     __IO uint32_t AUTHEN;                            /**< Observe access control, array offset: 0x30, array step: 0x80 */
24777     __IO uint32_t AUTHEN_SET;                        /**< Observe access control, array offset: 0x34, array step: 0x80 */
24778     __IO uint32_t AUTHEN_CLR;                        /**< Observe access control, array offset: 0x38, array step: 0x80 */
24779     __IO uint32_t AUTHEN_TOG;                        /**< Observe access control, array offset: 0x3C, array step: 0x80 */
24780     __I  uint32_t FREQUENCY_CURRENT;                 /**< Current frequency detected, array offset: 0x40, array step: 0x80 */
24781     __I  uint32_t FREQUENCY_MIN;                     /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */
24782     __I  uint32_t FREQUENCY_MAX;                     /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */
24783          uint8_t RESERVED_2[52];
24784   } OBSERVE[6];
24785 } CCM_OBS_Type;
24786 
24787 /* ----------------------------------------------------------------------------
24788    -- CCM_OBS Register Masks
24789    ---------------------------------------------------------------------------- */
24790 
24791 /*!
24792  * @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks
24793  * @{
24794  */
24795 
24796 /*! @name OBSERVE_CONTROL - Observe control */
24797 /*! @{ */
24798 
24799 #define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK      (0x1FFU)
24800 #define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT     (0U)
24801 /*! SELECT - Observe signal selector
24802  */
24803 #define CCM_OBS_OBSERVE_CONTROL_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK)
24804 
24805 #define CCM_OBS_OBSERVE_CONTROL_RAW_MASK         (0x1000U)
24806 #define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT        (12U)
24807 /*! RAW - Observe raw signal
24808  *  0b0..Select divided signal.
24809  *  0b1..Select raw signal.
24810  */
24811 #define CCM_OBS_OBSERVE_CONTROL_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK)
24812 
24813 #define CCM_OBS_OBSERVE_CONTROL_INV_MASK         (0x2000U)
24814 #define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT        (13U)
24815 /*! INV - Invert
24816  *  0b0..Clock phase remain same.
24817  *  0b1..Invert clock phase before measurement or send to IO.
24818  */
24819 #define CCM_OBS_OBSERVE_CONTROL_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK)
24820 
24821 #define CCM_OBS_OBSERVE_CONTROL_RESET_MASK       (0x8000U)
24822 #define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT      (15U)
24823 /*! RESET - Reset observe divider
24824  *  0b0..No reset
24825  *  0b1..Reset observe divider
24826  */
24827 #define CCM_OBS_OBSERVE_CONTROL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK)
24828 
24829 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK      (0xFF0000U)
24830 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT     (16U)
24831 /*! DIVIDE - Divider for observe signal
24832  */
24833 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK)
24834 
24835 #define CCM_OBS_OBSERVE_CONTROL_OFF_MASK         (0x1000000U)
24836 #define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT        (24U)
24837 /*! OFF - Turn off
24838  *  0b0..observe slice is on
24839  *  0b1..observe slice is off
24840  */
24841 #define CCM_OBS_OBSERVE_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK)
24842 /*! @} */
24843 
24844 /* The count of CCM_OBS_OBSERVE_CONTROL */
24845 #define CCM_OBS_OBSERVE_CONTROL_COUNT            (6U)
24846 
24847 /*! @name OBSERVE_CONTROL_SET - Observe control */
24848 /*! @{ */
24849 
24850 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK  (0x1FFU)
24851 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U)
24852 /*! SELECT - Observe signal selector
24853  */
24854 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK)
24855 
24856 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK     (0x1000U)
24857 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT    (12U)
24858 /*! RAW - Observe raw signal
24859  */
24860 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK)
24861 
24862 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK     (0x2000U)
24863 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT    (13U)
24864 /*! INV - Invert
24865  */
24866 #define CCM_OBS_OBSERVE_CONTROL_SET_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK)
24867 
24868 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK   (0x8000U)
24869 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT  (15U)
24870 /*! RESET - Reset observe divider
24871  */
24872 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK)
24873 
24874 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK  (0xFF0000U)
24875 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U)
24876 /*! DIVIDE - Divider for observe signal
24877  */
24878 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK)
24879 
24880 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK     (0x1000000U)
24881 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT    (24U)
24882 /*! OFF - Turn off
24883  */
24884 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK)
24885 /*! @} */
24886 
24887 /* The count of CCM_OBS_OBSERVE_CONTROL_SET */
24888 #define CCM_OBS_OBSERVE_CONTROL_SET_COUNT        (6U)
24889 
24890 /*! @name OBSERVE_CONTROL_CLR - Observe control */
24891 /*! @{ */
24892 
24893 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK  (0x1FFU)
24894 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U)
24895 /*! SELECT - Observe signal selector
24896  */
24897 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK)
24898 
24899 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK     (0x1000U)
24900 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT    (12U)
24901 /*! RAW - Observe raw signal
24902  */
24903 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK)
24904 
24905 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK     (0x2000U)
24906 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT    (13U)
24907 /*! INV - Invert
24908  */
24909 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK)
24910 
24911 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK   (0x8000U)
24912 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT  (15U)
24913 /*! RESET - Reset observe divider
24914  */
24915 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK)
24916 
24917 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK  (0xFF0000U)
24918 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U)
24919 /*! DIVIDE - Divider for observe signal
24920  */
24921 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
24922 
24923 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK     (0x1000000U)
24924 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT    (24U)
24925 /*! OFF - Turn off
24926  */
24927 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK)
24928 /*! @} */
24929 
24930 /* The count of CCM_OBS_OBSERVE_CONTROL_CLR */
24931 #define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT        (6U)
24932 
24933 /*! @name OBSERVE_CONTROL_TOG - Observe control */
24934 /*! @{ */
24935 
24936 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK  (0x1FFU)
24937 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U)
24938 /*! SELECT - Observe signal selector
24939  */
24940 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK)
24941 
24942 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK     (0x1000U)
24943 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT    (12U)
24944 /*! RAW - Observe raw signal
24945  */
24946 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK)
24947 
24948 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK     (0x2000U)
24949 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT    (13U)
24950 /*! INV - Invert
24951  */
24952 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK)
24953 
24954 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK   (0x8000U)
24955 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT  (15U)
24956 /*! RESET - Reset observe divider
24957  */
24958 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK)
24959 
24960 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK  (0xFF0000U)
24961 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U)
24962 /*! DIVIDE - Divider for observe signal
24963  */
24964 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
24965 
24966 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK     (0x1000000U)
24967 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT    (24U)
24968 /*! OFF - Turn off
24969  */
24970 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK)
24971 /*! @} */
24972 
24973 /* The count of CCM_OBS_OBSERVE_CONTROL_TOG */
24974 #define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT        (6U)
24975 
24976 /*! @name OBSERVE_STATUS0 - Observe status */
24977 /*! @{ */
24978 
24979 #define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK      (0x1FFU)
24980 #define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT     (0U)
24981 /*! SELECT - Select value
24982  */
24983 #define CCM_OBS_OBSERVE_STATUS0_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK)
24984 
24985 #define CCM_OBS_OBSERVE_STATUS0_RAW_MASK         (0x1000U)
24986 #define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT        (12U)
24987 /*! RAW - Observe raw signal
24988  *  0b0..Divided signal is selected
24989  *  0b1..Raw signal is selected
24990  */
24991 #define CCM_OBS_OBSERVE_STATUS0_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK)
24992 
24993 #define CCM_OBS_OBSERVE_STATUS0_INV_MASK         (0x2000U)
24994 #define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT        (13U)
24995 /*! INV - Polarity of the observe target
24996  *  0b1..Polarity of the observe target is inverted
24997  *  0b0..Polarity is not inverted
24998  */
24999 #define CCM_OBS_OBSERVE_STATUS0_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK)
25000 
25001 #define CCM_OBS_OBSERVE_STATUS0_RESET_MASK       (0x8000U)
25002 #define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT      (15U)
25003 /*! RESET - Reset state
25004  *  0b1..Observe divider is in reset state
25005  *  0b0..Observe divider is not in reset state
25006  */
25007 #define CCM_OBS_OBSERVE_STATUS0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK)
25008 
25009 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK      (0xFF0000U)
25010 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT     (16U)
25011 /*! DIVIDE - Divide value status. The clock will be divided by DIVIDE + 1.
25012  */
25013 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK)
25014 
25015 #define CCM_OBS_OBSERVE_STATUS0_OFF_MASK         (0x1000000U)
25016 #define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT        (24U)
25017 /*! OFF - Turn off slice
25018  *  0b0..observe slice is on
25019  *  0b1..observe slice is off
25020  */
25021 #define CCM_OBS_OBSERVE_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK)
25022 /*! @} */
25023 
25024 /* The count of CCM_OBS_OBSERVE_STATUS0 */
25025 #define CCM_OBS_OBSERVE_STATUS0_COUNT            (6U)
25026 
25027 /*! @name OBSERVE_AUTHEN - Observe access control */
25028 /*! @{ */
25029 
25030 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK      (0x1U)
25031 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT     (0U)
25032 /*! TZ_USER - User access
25033  *  0b1..Clock can be changed in user mode.
25034  *  0b0..Clock cannot be changed in user mode.
25035  */
25036 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK)
25037 
25038 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK        (0x2U)
25039 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT       (1U)
25040 /*! TZ_NS - Non-secure access
25041  *  0b0..Cannot be changed in Non-secure mode.
25042  *  0b1..Can be changed in Non-secure mode.
25043  */
25044 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK)
25045 
25046 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK      (0x10U)
25047 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT     (4U)
25048 /*! LOCK_TZ - Lock truszone setting
25049  *  0b0..Trustzone setting is not locked.
25050  *  0b1..Trustzone setting is locked.
25051  */
25052 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK)
25053 
25054 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK   (0xF00U)
25055 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT  (8U)
25056 /*! WHITE_LIST - White list
25057  *  0b1111..All domain can change.
25058  *  0b0010..Domain 1 can change.
25059  *  0b0011..Domain 0 and domain 1 can change.
25060  *  0b0000..No domain can change.
25061  *  0b0100..Domain 2 can change.
25062  *  0b0001..Domain 0 can change.
25063  */
25064 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK)
25065 
25066 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK    (0x1000U)
25067 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT   (12U)
25068 /*! LOCK_LIST - Lock white list
25069  *  0b0..White list is not locked.
25070  *  0b1..White list is locked.
25071  */
25072 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK)
25073 
25074 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
25075 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U)
25076 /*! DOMAIN_MODE - Low power and access control by domain
25077  *  0b1..Clock works in domain mode.
25078  *  0b0..Clock does not work in domain mode.
25079  */
25080 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK)
25081 
25082 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK    (0x100000U)
25083 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT   (20U)
25084 /*! LOCK_MODE - Lock low power and access mode
25085  *  0b0..MODE is not locked.
25086  *  0b1..MODE is locked.
25087  */
25088 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK)
25089 /*! @} */
25090 
25091 /* The count of CCM_OBS_OBSERVE_AUTHEN */
25092 #define CCM_OBS_OBSERVE_AUTHEN_COUNT             (6U)
25093 
25094 /*! @name OBSERVE_AUTHEN_SET - Observe access control */
25095 /*! @{ */
25096 
25097 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK  (0x1U)
25098 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U)
25099 /*! TZ_USER - User access
25100  */
25101 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
25102 
25103 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK    (0x2U)
25104 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT   (1U)
25105 /*! TZ_NS - Non-secure access
25106  */
25107 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
25108 
25109 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
25110 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
25111 /*! LOCK_TZ - Lock truszone setting
25112  */
25113 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
25114 
25115 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
25116 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
25117 /*! WHITE_LIST - White list
25118  */
25119 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
25120 
25121 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
25122 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
25123 /*! LOCK_LIST - Lock white list
25124  */
25125 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
25126 
25127 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
25128 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
25129 /*! DOMAIN_MODE - Low power and access control by domain
25130  */
25131 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK)
25132 
25133 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
25134 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
25135 /*! LOCK_MODE - Lock low power and access mode
25136  */
25137 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK)
25138 /*! @} */
25139 
25140 /* The count of CCM_OBS_OBSERVE_AUTHEN_SET */
25141 #define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT         (6U)
25142 
25143 /*! @name OBSERVE_AUTHEN_CLR - Observe access control */
25144 /*! @{ */
25145 
25146 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
25147 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U)
25148 /*! TZ_USER - User access
25149  */
25150 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
25151 
25152 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
25153 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
25154 /*! TZ_NS - Non-secure access
25155  */
25156 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
25157 
25158 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
25159 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
25160 /*! LOCK_TZ - Lock truszone setting
25161  */
25162 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
25163 
25164 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
25165 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
25166 /*! WHITE_LIST - White list
25167  */
25168 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
25169 
25170 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
25171 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
25172 /*! LOCK_LIST - Lock white list
25173  */
25174 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
25175 
25176 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
25177 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
25178 /*! DOMAIN_MODE - Low power and access control by domain
25179  */
25180 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK)
25181 
25182 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
25183 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
25184 /*! LOCK_MODE - Lock low power and access mode
25185  */
25186 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK)
25187 /*! @} */
25188 
25189 /* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */
25190 #define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT         (6U)
25191 
25192 /*! @name OBSERVE_AUTHEN_TOG - Observe access control */
25193 /*! @{ */
25194 
25195 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
25196 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U)
25197 /*! TZ_USER - User access
25198  */
25199 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
25200 
25201 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
25202 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
25203 /*! TZ_NS - Non-secure access
25204  */
25205 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
25206 
25207 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
25208 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
25209 /*! LOCK_TZ - Lock truszone setting
25210  */
25211 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
25212 
25213 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
25214 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
25215 /*! WHITE_LIST - White list
25216  */
25217 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
25218 
25219 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
25220 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
25221 /*! LOCK_LIST - Lock white list
25222  */
25223 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
25224 
25225 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
25226 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
25227 /*! DOMAIN_MODE - Low power and access control by domain
25228  */
25229 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK)
25230 
25231 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
25232 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
25233 /*! LOCK_MODE - Lock low power and access mode
25234  */
25235 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK)
25236 /*! @} */
25237 
25238 /* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */
25239 #define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT         (6U)
25240 
25241 /*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */
25242 /*! @{ */
25243 
25244 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
25245 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
25246 /*! FREQUENCY - Frequency
25247  */
25248 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
25249 /*! @} */
25250 
25251 /* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */
25252 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT  (6U)
25253 
25254 /*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */
25255 /*! @{ */
25256 
25257 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
25258 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
25259 /*! FREQUENCY - Frequency
25260  */
25261 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
25262 /*! @} */
25263 
25264 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */
25265 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT      (6U)
25266 
25267 /*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */
25268 /*! @{ */
25269 
25270 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
25271 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
25272 /*! FREQUENCY - Frequency
25273  */
25274 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
25275 /*! @} */
25276 
25277 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */
25278 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT      (6U)
25279 
25280 
25281 /*!
25282  * @}
25283  */ /* end of group CCM_OBS_Register_Masks */
25284 
25285 
25286 /* CCM_OBS - Peripheral instance base addresses */
25287 /** Peripheral CCM_OBS base address */
25288 #define CCM_OBS_BASE                             (0x40150000u)
25289 /** Peripheral CCM_OBS base pointer */
25290 #define CCM_OBS                                  ((CCM_OBS_Type *)CCM_OBS_BASE)
25291 /** Array initializer of CCM_OBS peripheral base addresses */
25292 #define CCM_OBS_BASE_ADDRS                       { CCM_OBS_BASE }
25293 /** Array initializer of CCM_OBS peripheral base pointers */
25294 #define CCM_OBS_BASE_PTRS                        { CCM_OBS }
25295 
25296 /*!
25297  * @}
25298  */ /* end of group CCM_OBS_Peripheral_Access_Layer */
25299 
25300 
25301 /* ----------------------------------------------------------------------------
25302    -- CDOG Peripheral Access Layer
25303    ---------------------------------------------------------------------------- */
25304 
25305 /*!
25306  * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
25307  * @{
25308  */
25309 
25310 /** CDOG - Register Layout Typedef */
25311 typedef struct {
25312   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
25313   __IO uint32_t RELOAD;                            /**< Instruction Timer reload, offset: 0x4 */
25314   __IO uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer, offset: 0x8 */
25315   __O  uint32_t SECURE_COUNTER;                    /**< Secure Counter, offset: 0xC */
25316   __I  uint32_t STATUS;                            /**< Status 1, offset: 0x10 */
25317   __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x14 */
25318   __IO uint32_t FLAGS;                             /**< Flags, offset: 0x18 */
25319   __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage, offset: 0x1C */
25320   __O  uint32_t START;                             /**< START Command, offset: 0x20 */
25321   __O  uint32_t STOP;                              /**< STOP Command, offset: 0x24 */
25322   __O  uint32_t RESTART;                           /**< RESTART Command, offset: 0x28 */
25323   __O  uint32_t ADD;                               /**< ADD Command, offset: 0x2C */
25324   __O  uint32_t ADD1;                              /**< ADD1 Command, offset: 0x30 */
25325   __O  uint32_t ADD16;                             /**< ADD16 Command, offset: 0x34 */
25326   __O  uint32_t ADD256;                            /**< ADD256 Command, offset: 0x38 */
25327   __O  uint32_t SUB;                               /**< SUB Command, offset: 0x3C */
25328   __O  uint32_t SUB1;                              /**< SUB1 Command, offset: 0x40 */
25329   __O  uint32_t SUB16;                             /**< SUB16 Command, offset: 0x44 */
25330   __O  uint32_t SUB256;                            /**< SUB256 Command, offset: 0x48 */
25331 } CDOG_Type;
25332 
25333 /* ----------------------------------------------------------------------------
25334    -- CDOG Register Masks
25335    ---------------------------------------------------------------------------- */
25336 
25337 /*!
25338  * @addtogroup CDOG_Register_Masks CDOG Register Masks
25339  * @{
25340  */
25341 
25342 /*! @name CONTROL - Control */
25343 /*! @{ */
25344 
25345 #define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
25346 #define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
25347 /*! LOCK_CTRL - Lock control
25348  *  0b01..Locked
25349  *  0b10..Unlocked
25350  */
25351 #define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
25352 
25353 #define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
25354 #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
25355 /*! TIMEOUT_CTRL - TIMEOUT fault control
25356  *  0b100..Disable both reset and interrupt
25357  *  0b001..Enable reset
25358  *  0b010..Enable interrupt
25359  */
25360 #define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
25361 
25362 #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
25363 #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
25364 /*! MISCOMPARE_CTRL - MISCOMPARE fault control
25365  *  0b100..Disable both reset and interrupt
25366  *  0b001..Enable reset
25367  *  0b010..Enable interrupt
25368  */
25369 #define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
25370 
25371 #define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
25372 #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
25373 /*! SEQUENCE_CTRL - SEQUENCE fault control
25374  *  0b001..Enable reset
25375  *  0b010..Enable interrupt
25376  *  0b100..Disable both reset and interrupt
25377  */
25378 #define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
25379 
25380 #define CDOG_CONTROL_CONTROL_CTRL_MASK           (0x3800U)
25381 #define CDOG_CONTROL_CONTROL_CTRL_SHIFT          (11U)
25382 /*! CONTROL_CTRL - CONTROL fault control
25383  *  0b001..Enable reset
25384  *  0b100..Disable reset
25385  */
25386 #define CDOG_CONTROL_CONTROL_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
25387 
25388 #define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
25389 #define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
25390 /*! STATE_CTRL - STATE fault control
25391  *  0b001..Enable reset
25392  *  0b010..Enable interrupt
25393  *  0b100..Disable both reset and interrupt
25394  */
25395 #define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
25396 
25397 #define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
25398 #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
25399 /*! ADDRESS_CTRL - ADDRESS fault control
25400  *  0b001..Enable reset
25401  *  0b010..Enable interrupt
25402  *  0b100..Disable both reset and interrupt
25403  */
25404 #define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
25405 
25406 #define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
25407 #define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
25408 /*! IRQ_PAUSE - IRQ pause control
25409  *  0b01..Keep the timer running
25410  *  0b10..Stop the timer
25411  */
25412 #define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
25413 
25414 #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
25415 #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
25416 /*! DEBUG_HALT_CTRL - DEBUG_HALT control
25417  *  0b01..Keep the timer running
25418  *  0b10..Stop the timer
25419  */
25420 #define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
25421 /*! @} */
25422 
25423 /*! @name RELOAD - Instruction Timer reload */
25424 /*! @{ */
25425 
25426 #define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
25427 #define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
25428 /*! RLOAD - Instruction Timer reload value
25429  */
25430 #define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
25431 /*! @} */
25432 
25433 /*! @name INSTRUCTION_TIMER - Instruction Timer */
25434 /*! @{ */
25435 
25436 #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
25437 #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
25438 /*! INSTIM - Current value of the Instruction Timer
25439  */
25440 #define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
25441 /*! @} */
25442 
25443 /*! @name SECURE_COUNTER - Secure Counter */
25444 /*! @{ */
25445 
25446 #define CDOG_SECURE_COUNTER_SECCNT_MASK          (0xFFFFFFFFU)
25447 #define CDOG_SECURE_COUNTER_SECCNT_SHIFT         (0U)
25448 /*! SECCNT - Secure Counter
25449  */
25450 #define CDOG_SECURE_COUNTER_SECCNT(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
25451 /*! @} */
25452 
25453 /*! @name STATUS - Status 1 */
25454 /*! @{ */
25455 
25456 #define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
25457 #define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
25458 /*! NUMTOF - Number of TIMEOUT faults since the last POR
25459  */
25460 #define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
25461 
25462 #define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
25463 #define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
25464 /*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR
25465  */
25466 #define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
25467 
25468 #define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
25469 #define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
25470 /*! NUMILSEQF - Number of SEQUENCE faults since the last POR
25471  */
25472 #define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
25473 
25474 #define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
25475 #define CDOG_STATUS_CURST_SHIFT                  (28U)
25476 /*! CURST - Current State
25477  */
25478 #define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
25479 /*! @} */
25480 
25481 /*! @name STATUS2 - Status 2 */
25482 /*! @{ */
25483 
25484 #define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
25485 #define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
25486 /*! NUMCNTF - Number of CONTROL faults since the last POR
25487  */
25488 #define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
25489 
25490 #define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
25491 #define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
25492 /*! NUMILLSTF - Number of STATE faults since the last POR
25493  */
25494 #define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
25495 
25496 #define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
25497 #define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
25498 /*! NUMILLA - Number of ADDRESS faults since the last POR
25499  */
25500 #define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
25501 /*! @} */
25502 
25503 /*! @name FLAGS - Flags */
25504 /*! @{ */
25505 
25506 #define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
25507 #define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
25508 /*! TO_FLAG - TIMEOUT fault flag
25509  *  0b0..A TIMEOUT fault has not occurred
25510  *  0b1..A TIMEOUT fault has occurred
25511  */
25512 #define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
25513 
25514 #define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
25515 #define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
25516 /*! MISCOM_FLAG - MISCOMPARE fault flag
25517  *  0b0..A MISCOMPARE fault has not occurred
25518  *  0b1..A MISCOMPARE fault has occurred
25519  */
25520 #define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
25521 
25522 #define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
25523 #define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
25524 /*! SEQ_FLAG - SEQUENCE fault flag
25525  *  0b0..A SEQUENCE fault has not occurred
25526  *  0b1..A SEQUENCE fault has occurred
25527  */
25528 #define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
25529 
25530 #define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
25531 #define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
25532 /*! CNT_FLAG - CONTROL fault flag
25533  *  0b0..A CONTROL fault has not occurred
25534  *  0b1..A CONTROL fault has occurred
25535  */
25536 #define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
25537 
25538 #define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
25539 #define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
25540 /*! STATE_FLAG - STATE fault flag
25541  *  0b0..A STATE fault has not occurred
25542  *  0b1..A STATE fault has occurred
25543  */
25544 #define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
25545 
25546 #define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
25547 #define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
25548 /*! ADDR_FLAG - ADDRESS fault flag
25549  *  0b0..An ADDRESS fault has not occurred
25550  *  0b1..An ADDRESS fault has occurred
25551  */
25552 #define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
25553 
25554 #define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
25555 #define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
25556 /*! POR_FLAG - Power-on reset flag
25557  *  0b0..A Power-on reset event has not occurred
25558  *  0b1..A Power-on reset event has occurred
25559  */
25560 #define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
25561 /*! @} */
25562 
25563 /*! @name PERSISTENT - Persistent Data Storage */
25564 /*! @{ */
25565 
25566 #define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
25567 #define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
25568 /*! PERSIS - Persistent Storage
25569  */
25570 #define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
25571 /*! @} */
25572 
25573 /*! @name START - START Command */
25574 /*! @{ */
25575 
25576 #define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
25577 #define CDOG_START_STRT_SHIFT                    (0U)
25578 /*! STRT - Start command
25579  */
25580 #define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
25581 /*! @} */
25582 
25583 /*! @name STOP - STOP Command */
25584 /*! @{ */
25585 
25586 #define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
25587 #define CDOG_STOP_STP_SHIFT                      (0U)
25588 /*! STP - Stop command
25589  */
25590 #define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
25591 /*! @} */
25592 
25593 /*! @name RESTART - RESTART Command */
25594 /*! @{ */
25595 
25596 #define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
25597 #define CDOG_RESTART_RSTRT_SHIFT                 (0U)
25598 /*! RSTRT - Restart command
25599  */
25600 #define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
25601 /*! @} */
25602 
25603 /*! @name ADD - ADD Command */
25604 /*! @{ */
25605 
25606 #define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
25607 #define CDOG_ADD_AD_SHIFT                        (0U)
25608 /*! AD - ADD Write Value
25609  */
25610 #define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
25611 /*! @} */
25612 
25613 /*! @name ADD1 - ADD1 Command */
25614 /*! @{ */
25615 
25616 #define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
25617 #define CDOG_ADD1_AD1_SHIFT                      (0U)
25618 /*! AD1 - ADD 1
25619  */
25620 #define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
25621 /*! @} */
25622 
25623 /*! @name ADD16 - ADD16 Command */
25624 /*! @{ */
25625 
25626 #define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
25627 #define CDOG_ADD16_AD16_SHIFT                    (0U)
25628 /*! AD16 - ADD 16
25629  */
25630 #define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
25631 /*! @} */
25632 
25633 /*! @name ADD256 - ADD256 Command */
25634 /*! @{ */
25635 
25636 #define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
25637 #define CDOG_ADD256_AD256_SHIFT                  (0U)
25638 /*! AD256 - ADD 256
25639  */
25640 #define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
25641 /*! @} */
25642 
25643 /*! @name SUB - SUB Command */
25644 /*! @{ */
25645 
25646 #define CDOG_SUB_S0B_MASK                        (0xFFFFFFFFU)
25647 #define CDOG_SUB_S0B_SHIFT                       (0U)
25648 /*! S0B - Subtract Write Value
25649  */
25650 #define CDOG_SUB_S0B(x)                          (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
25651 /*! @} */
25652 
25653 /*! @name SUB1 - SUB1 Command */
25654 /*! @{ */
25655 
25656 #define CDOG_SUB1_S1B_MASK                       (0xFFFFFFFFU)
25657 #define CDOG_SUB1_S1B_SHIFT                      (0U)
25658 /*! S1B - Subtract 1
25659  */
25660 #define CDOG_SUB1_S1B(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
25661 /*! @} */
25662 
25663 /*! @name SUB16 - SUB16 Command */
25664 /*! @{ */
25665 
25666 #define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
25667 #define CDOG_SUB16_SB16_SHIFT                    (0U)
25668 /*! SB16 - Subtract 16
25669  */
25670 #define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
25671 /*! @} */
25672 
25673 /*! @name SUB256 - SUB256 Command */
25674 /*! @{ */
25675 
25676 #define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
25677 #define CDOG_SUB256_SB256_SHIFT                  (0U)
25678 /*! SB256 - Subtract 256
25679  */
25680 #define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
25681 /*! @} */
25682 
25683 
25684 /*!
25685  * @}
25686  */ /* end of group CDOG_Register_Masks */
25687 
25688 
25689 /* CDOG - Peripheral instance base addresses */
25690 /** Peripheral CDOG base address */
25691 #define CDOG_BASE                                (0x41900000u)
25692 /** Peripheral CDOG base pointer */
25693 #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
25694 /** Array initializer of CDOG peripheral base addresses */
25695 #define CDOG_BASE_ADDRS                          { CDOG_BASE }
25696 /** Array initializer of CDOG peripheral base pointers */
25697 #define CDOG_BASE_PTRS                           { CDOG }
25698 /** Interrupt vectors for the CDOG peripheral type */
25699 #define CDOG_IRQS                                { CDOG_IRQn }
25700 
25701 /*!
25702  * @}
25703  */ /* end of group CDOG_Peripheral_Access_Layer */
25704 
25705 
25706 /* ----------------------------------------------------------------------------
25707    -- CMP Peripheral Access Layer
25708    ---------------------------------------------------------------------------- */
25709 
25710 /*!
25711  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
25712  * @{
25713  */
25714 
25715 /** CMP - Register Layout Typedef */
25716 typedef struct {
25717   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
25718   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
25719   __IO uint32_t C0;                                /**< CMP Control Register 0, offset: 0x8 */
25720   __IO uint32_t C1;                                /**< CMP Control Register 1, offset: 0xC */
25721   __IO uint32_t C2;                                /**< CMP Control Register 2, offset: 0x10 */
25722   __IO uint32_t C3;                                /**< CMP Control Register 3, offset: 0x14 */
25723 } CMP_Type;
25724 
25725 /* ----------------------------------------------------------------------------
25726    -- CMP Register Masks
25727    ---------------------------------------------------------------------------- */
25728 
25729 /*!
25730  * @addtogroup CMP_Register_Masks CMP Register Masks
25731  * @{
25732  */
25733 
25734 /*! @name VERID - Version ID Register */
25735 /*! @{ */
25736 
25737 #define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
25738 #define CMP_VERID_FEATURE_SHIFT                  (0U)
25739 /*! FEATURE - Feature Specification Number. This read only filed returns the feature set number.
25740  */
25741 #define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
25742 
25743 #define CMP_VERID_MINOR_MASK                     (0xFF0000U)
25744 #define CMP_VERID_MINOR_SHIFT                    (16U)
25745 /*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.
25746  */
25747 #define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
25748 
25749 #define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
25750 #define CMP_VERID_MAJOR_SHIFT                    (24U)
25751 /*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification.
25752  */
25753 #define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
25754 /*! @} */
25755 
25756 /*! @name PARAM - Parameter Register */
25757 /*! @{ */
25758 
25759 #define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
25760 #define CMP_PARAM_PARAM_SHIFT                    (0U)
25761 /*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.
25762  */
25763 #define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
25764 /*! @} */
25765 
25766 /*! @name C0 - CMP Control Register 0 */
25767 /*! @{ */
25768 
25769 #define CMP_C0_HYSTCTR_MASK                      (0x3U)
25770 #define CMP_C0_HYSTCTR_SHIFT                     (0U)
25771 /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
25772  *  0b00..The hard block output has level 0 hysteresis internally.
25773  *  0b01..The hard block output has level 1 hysteresis internally.
25774  *  0b10..The hard block output has level 2 hysteresis internally.
25775  *  0b11..The hard block output has level 3 hysteresis internally.
25776  */
25777 #define CMP_C0_HYSTCTR(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
25778 
25779 #define CMP_C0_FILTER_CNT_MASK                   (0x70U)
25780 #define CMP_C0_FILTER_CNT_SHIFT                  (4U)
25781 /*! FILTER_CNT - Filter Sample Count
25782  *  0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
25783  *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
25784  *  0b010..2 consecutive samples must agree.
25785  *  0b011..3 consecutive samples must agree.
25786  *  0b100..4 consecutive samples must agree.
25787  *  0b101..5 consecutive samples must agree.
25788  *  0b110..6 consecutive samples must agree.
25789  *  0b111..7 consecutive samples must agree.
25790  */
25791 #define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
25792 
25793 #define CMP_C0_EN_MASK                           (0x100U)
25794 #define CMP_C0_EN_SHIFT                          (8U)
25795 /*! EN - Comparator Module Enable
25796  *  0b0..Analog Comparator is disabled.
25797  *  0b1..Analog Comparator is enabled.
25798  */
25799 #define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
25800 
25801 #define CMP_C0_OPE_MASK                          (0x200U)
25802 #define CMP_C0_OPE_SHIFT                         (9U)
25803 /*! OPE - Comparator Output Pin Enable
25804  *  0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
25805  *  0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
25806  */
25807 #define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
25808 
25809 #define CMP_C0_COS_MASK                          (0x400U)
25810 #define CMP_C0_COS_SHIFT                         (10U)
25811 /*! COS - Comparator Output Select
25812  *  0b0..Set CMPO to equal COUT (filtered comparator output).
25813  *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
25814  */
25815 #define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
25816 
25817 #define CMP_C0_INVT_MASK                         (0x800U)
25818 #define CMP_C0_INVT_SHIFT                        (11U)
25819 /*! INVT - Comparator invert
25820  *  0b0..Does not invert the comparator output.
25821  *  0b1..Inverts the comparator output.
25822  */
25823 #define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
25824 
25825 #define CMP_C0_PMODE_MASK                        (0x1000U)
25826 #define CMP_C0_PMODE_SHIFT                       (12U)
25827 /*! PMODE - Power Mode Select
25828  *  0b0..Low Speed (LS) comparison mode is selected.
25829  *  0b1..High Speed (HS) comparison mode is selected.
25830  */
25831 #define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
25832 
25833 #define CMP_C0_WE_MASK                           (0x4000U)
25834 #define CMP_C0_WE_SHIFT                          (14U)
25835 /*! WE - Windowing Enable
25836  *  0b0..Windowing mode is not selected.
25837  *  0b1..Windowing mode is selected.
25838  */
25839 #define CMP_C0_WE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
25840 
25841 #define CMP_C0_SE_MASK                           (0x8000U)
25842 #define CMP_C0_SE_SHIFT                          (15U)
25843 /*! SE - Sample Enable
25844  *  0b0..Sampling mode is not selected.
25845  *  0b1..Sampling mode is selected.
25846  */
25847 #define CMP_C0_SE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
25848 
25849 #define CMP_C0_FPR_MASK                          (0xFF0000U)
25850 #define CMP_C0_FPR_SHIFT                         (16U)
25851 /*! FPR - Filter Sample Period
25852  */
25853 #define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
25854 
25855 #define CMP_C0_COUT_MASK                         (0x1000000U)
25856 #define CMP_C0_COUT_SHIFT                        (24U)
25857 /*! COUT - Analog Comparator Output
25858  */
25859 #define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
25860 
25861 #define CMP_C0_CFF_MASK                          (0x2000000U)
25862 #define CMP_C0_CFF_SHIFT                         (25U)
25863 /*! CFF - Analog Comparator Flag Falling
25864  *  0b0..A falling edge has not been detected on COUT.
25865  *  0b1..A falling edge on COUT has occurred.
25866  */
25867 #define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
25868 
25869 #define CMP_C0_CFR_MASK                          (0x4000000U)
25870 #define CMP_C0_CFR_SHIFT                         (26U)
25871 /*! CFR - Analog Comparator Flag Rising
25872  *  0b0..A rising edge has not been detected on COUT.
25873  *  0b1..A rising edge on COUT has occurred.
25874  */
25875 #define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
25876 
25877 #define CMP_C0_IEF_MASK                          (0x8000000U)
25878 #define CMP_C0_IEF_SHIFT                         (27U)
25879 /*! IEF - Comparator Interrupt Enable Falling
25880  *  0b0..Interrupt is disabled.
25881  *  0b1..Interrupt is enabled.
25882  */
25883 #define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
25884 
25885 #define CMP_C0_IER_MASK                          (0x10000000U)
25886 #define CMP_C0_IER_SHIFT                         (28U)
25887 /*! IER - Comparator Interrupt Enable Rising
25888  *  0b0..Interrupt is disabled.
25889  *  0b1..Interrupt is enabled.
25890  */
25891 #define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
25892 
25893 #define CMP_C0_DMAEN_MASK                        (0x40000000U)
25894 #define CMP_C0_DMAEN_SHIFT                       (30U)
25895 /*! DMAEN - DMA Enable
25896  *  0b0..DMA is disabled.
25897  *  0b1..DMA is enabled.
25898  */
25899 #define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
25900 
25901 #define CMP_C0_LINKEN_MASK                       (0x80000000U)
25902 #define CMP_C0_LINKEN_SHIFT                      (31U)
25903 /*! LINKEN - CMP to DAC link enable.
25904  *  0b0..CMP to DAC link is disabled
25905  *  0b1..CMP to DAC link is enabled.
25906  */
25907 #define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
25908 /*! @} */
25909 
25910 /*! @name C1 - CMP Control Register 1 */
25911 /*! @{ */
25912 
25913 #define CMP_C1_VOSEL_MASK                        (0xFFU)
25914 #define CMP_C1_VOSEL_SHIFT                       (0U)
25915 /*! VOSEL - DAC Output Voltage Select
25916  */
25917 #define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
25918 
25919 #define CMP_C1_DMODE_MASK                        (0x100U)
25920 #define CMP_C1_DMODE_SHIFT                       (8U)
25921 /*! DMODE - DAC Mode Selection
25922  *  0b0..DAC is selected to work in low speed and low power mode.
25923  *  0b1..DAC is selected to work in high speed high power mode.
25924  */
25925 #define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
25926 
25927 #define CMP_C1_VRSEL_MASK                        (0x200U)
25928 #define CMP_C1_VRSEL_SHIFT                       (9U)
25929 /*! VRSEL - Supply Voltage Reference Source Select
25930  *  0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
25931  *  0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
25932  */
25933 #define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
25934 
25935 #define CMP_C1_DACEN_MASK                        (0x400U)
25936 #define CMP_C1_DACEN_SHIFT                       (10U)
25937 /*! DACEN - DAC Enable
25938  *  0b0..DAC is disabled.
25939  *  0b1..DAC is enabled.
25940  */
25941 #define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
25942 
25943 #define CMP_C1_CHN0_MASK                         (0x10000U)
25944 #define CMP_C1_CHN0_SHIFT                        (16U)
25945 /*! CHN0 - Channel 0 input enable
25946  */
25947 #define CMP_C1_CHN0(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
25948 
25949 #define CMP_C1_CHN1_MASK                         (0x20000U)
25950 #define CMP_C1_CHN1_SHIFT                        (17U)
25951 /*! CHN1 - Channel 1 input enable
25952  */
25953 #define CMP_C1_CHN1(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
25954 
25955 #define CMP_C1_CHN2_MASK                         (0x40000U)
25956 #define CMP_C1_CHN2_SHIFT                        (18U)
25957 /*! CHN2 - Channel 2 input enable
25958  */
25959 #define CMP_C1_CHN2(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
25960 
25961 #define CMP_C1_CHN3_MASK                         (0x80000U)
25962 #define CMP_C1_CHN3_SHIFT                        (19U)
25963 /*! CHN3 - Channel 3 input enable
25964  */
25965 #define CMP_C1_CHN3(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
25966 
25967 #define CMP_C1_CHN4_MASK                         (0x100000U)
25968 #define CMP_C1_CHN4_SHIFT                        (20U)
25969 /*! CHN4 - Channel 4 input enable
25970  */
25971 #define CMP_C1_CHN4(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
25972 
25973 #define CMP_C1_CHN5_MASK                         (0x200000U)
25974 #define CMP_C1_CHN5_SHIFT                        (21U)
25975 /*! CHN5 - Channel 5 input enable
25976  */
25977 #define CMP_C1_CHN5(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
25978 
25979 #define CMP_C1_MSEL_MASK                         (0x7000000U)
25980 #define CMP_C1_MSEL_SHIFT                        (24U)
25981 /*! MSEL - Minus Input MUX Control
25982  *  0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
25983  *  0b001..External Input 1 for Minus Channel -- Reference Input 0
25984  *  0b010..External Input 2 for Minus Channel -- Reference Input 1
25985  *  0b011..External Input 3 for Minus Channel -- Reference Input 2
25986  *  0b100..External Input 4 for Minus Channel -- Reference Input 3
25987  *  0b101..External Input 5 for Minus Channel -- Reference Input 4
25988  *  0b110..External Input 6 for Minus Channel -- Reference Input 5
25989  *  0b111..Internal 8b DAC output
25990  */
25991 #define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
25992 
25993 #define CMP_C1_PSEL_MASK                         (0x70000000U)
25994 #define CMP_C1_PSEL_SHIFT                        (28U)
25995 /*! PSEL - Plus Input MUX Control
25996  *  0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
25997  *  0b001..External Input 1 for Plus Channel -- Reference Input 0
25998  *  0b010..External Input 2 for Plus Channel -- Reference Input 1
25999  *  0b011..External Input 3 for Plus Channel -- Reference Input 2
26000  *  0b100..External Input 4 for Plus Channel -- Reference Input 3
26001  *  0b101..External Input 5 for Plus Channel -- Reference Input 4
26002  *  0b110..External Input 6 for Plus Channel -- Reference Input 5
26003  *  0b111..Internal 8b DAC output
26004  */
26005 #define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
26006 /*! @} */
26007 
26008 /*! @name C2 - CMP Control Register 2 */
26009 /*! @{ */
26010 
26011 #define CMP_C2_ACOn_MASK                         (0x3FU)
26012 #define CMP_C2_ACOn_SHIFT                        (0U)
26013 /*! ACOn - ACOn
26014  */
26015 #define CMP_C2_ACOn(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
26016 
26017 #define CMP_C2_INITMOD_MASK                      (0x3F00U)
26018 #define CMP_C2_INITMOD_SHIFT                     (8U)
26019 /*! INITMOD - Comparator and DAC initialization delay modulus.
26020  */
26021 #define CMP_C2_INITMOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
26022 
26023 #define CMP_C2_NSAM_MASK                         (0xC000U)
26024 #define CMP_C2_NSAM_SHIFT                        (14U)
26025 /*! NSAM - Number of sample clocks
26026  *  0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
26027  *  0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
26028  *  0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
26029  *  0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
26030  */
26031 #define CMP_C2_NSAM(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
26032 
26033 #define CMP_C2_CH0F_MASK                         (0x10000U)
26034 #define CMP_C2_CH0F_SHIFT                        (16U)
26035 /*! CH0F - CH0F
26036  */
26037 #define CMP_C2_CH0F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
26038 
26039 #define CMP_C2_CH1F_MASK                         (0x20000U)
26040 #define CMP_C2_CH1F_SHIFT                        (17U)
26041 /*! CH1F - CH1F
26042  */
26043 #define CMP_C2_CH1F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
26044 
26045 #define CMP_C2_CH2F_MASK                         (0x40000U)
26046 #define CMP_C2_CH2F_SHIFT                        (18U)
26047 /*! CH2F - CH2F
26048  */
26049 #define CMP_C2_CH2F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
26050 
26051 #define CMP_C2_CH3F_MASK                         (0x80000U)
26052 #define CMP_C2_CH3F_SHIFT                        (19U)
26053 /*! CH3F - CH3F
26054  */
26055 #define CMP_C2_CH3F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
26056 
26057 #define CMP_C2_CH4F_MASK                         (0x100000U)
26058 #define CMP_C2_CH4F_SHIFT                        (20U)
26059 /*! CH4F - CH4F
26060  */
26061 #define CMP_C2_CH4F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
26062 
26063 #define CMP_C2_CH5F_MASK                         (0x200000U)
26064 #define CMP_C2_CH5F_SHIFT                        (21U)
26065 /*! CH5F - CH5F
26066  */
26067 #define CMP_C2_CH5F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
26068 
26069 #define CMP_C2_FXMXCH_MASK                       (0xE000000U)
26070 #define CMP_C2_FXMXCH_SHIFT                      (25U)
26071 /*! FXMXCH - Fixed channel selection
26072  *  0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
26073  *  0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
26074  *  0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
26075  *  0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
26076  *  0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
26077  *  0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
26078  *  0b110..Reserved.
26079  *  0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
26080  */
26081 #define CMP_C2_FXMXCH(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
26082 
26083 #define CMP_C2_FXMP_MASK                         (0x20000000U)
26084 #define CMP_C2_FXMP_SHIFT                        (29U)
26085 /*! FXMP - Fixed MUX Port
26086  *  0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
26087  *  0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
26088  */
26089 #define CMP_C2_FXMP(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
26090 
26091 #define CMP_C2_RRIE_MASK                         (0x40000000U)
26092 #define CMP_C2_RRIE_SHIFT                        (30U)
26093 /*! RRIE - Round-Robin interrupt enable
26094  *  0b0..The round-robin interrupt is disabled.
26095  *  0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
26096  */
26097 #define CMP_C2_RRIE(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
26098 /*! @} */
26099 
26100 /*! @name C3 - CMP Control Register 3 */
26101 /*! @{ */
26102 
26103 #define CMP_C3_ACPH2TC_MASK                      (0x70U)
26104 #define CMP_C3_ACPH2TC_SHIFT                     (4U)
26105 /*! ACPH2TC - Analog Comparator Phase2 Timing Control.
26106  *  0b000..Phase2 active time in one sampling period equals to T
26107  *  0b001..Phase2 active time in one sampling period equals to 2*T
26108  *  0b010..Phase2 active time in one sampling period equals to 4*T
26109  *  0b011..Phase2 active time in one sampling period equals to 8*T
26110  *  0b100..Phase2 active time in one sampling period equals to 16*T
26111  *  0b101..Phase2 active time in one sampling period equals to 32*T
26112  *  0b110..Phase2 active time in one sampling period equals to 64*T
26113  *  0b111..Phase2 active time in one sampling period equals to 16*T
26114  */
26115 #define CMP_C3_ACPH2TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
26116 
26117 #define CMP_C3_ACPH1TC_MASK                      (0x700U)
26118 #define CMP_C3_ACPH1TC_SHIFT                     (8U)
26119 /*! ACPH1TC - Analog Comparator Phase1 Timing Control.
26120  *  0b000..Phase1 active time in one sampling period equals to T
26121  *  0b001..Phase1 active time in one sampling period equals to 2*T
26122  *  0b010..Phase1 active time in one sampling period equals to 4*T
26123  *  0b011..Phase1 active time in one sampling period equals to 8*T
26124  *  0b100..Phase1 active time in one sampling period equals to T
26125  *  0b101..Phase1 active time in one sampling period equals to T
26126  *  0b110..Phase1 active time in one sampling period equals to T
26127  *  0b111..Phase1 active time in one sampling period equals to 0
26128  */
26129 #define CMP_C3_ACPH1TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
26130 
26131 #define CMP_C3_ACSAT_MASK                        (0x7000U)
26132 #define CMP_C3_ACSAT_SHIFT                       (12U)
26133 /*! ACSAT - Analog Comparator Sampling Time control.
26134  *  0b000..The sampling time equals to T
26135  *  0b001..The sampling time equasl to 2*T
26136  *  0b010..The sampling time equasl to 4*T
26137  *  0b011..The sampling time equasl to 8*T
26138  *  0b100..The sampling time equasl to 16*T
26139  *  0b101..The sampling time equasl to 32*T
26140  *  0b110..The sampling time equasl to 64*T
26141  *  0b111..The sampling time equasl to 256*T
26142  */
26143 #define CMP_C3_ACSAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
26144 
26145 #define CMP_C3_DMCS_MASK                         (0x10000U)
26146 #define CMP_C3_DMCS_SHIFT                        (16U)
26147 /*! DMCS - Discrete Mode Clock Selection
26148  *  0b0..Slow clock is selected for the timing generation.
26149  *  0b1..Fast clock is selected for the timing generation.
26150  */
26151 #define CMP_C3_DMCS(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
26152 
26153 #define CMP_C3_RDIVE_MASK                        (0x100000U)
26154 #define CMP_C3_RDIVE_SHIFT                       (20U)
26155 /*! RDIVE - Resistor Divider Enable
26156  *  0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
26157  *  0b1..The resistor is enabled because the inputs are above 1.8v.
26158  */
26159 #define CMP_C3_RDIVE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
26160 
26161 #define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
26162 #define CMP_C3_NCHCTEN_SHIFT                     (24U)
26163 /*! NCHCTEN - Negative Channel Continuous Mode Enable.
26164  *  0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
26165  *  0b1..Negative channel is in Continuous Mode and no special timing is requried.
26166  */
26167 #define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
26168 
26169 #define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
26170 #define CMP_C3_PCHCTEN_SHIFT                     (28U)
26171 /*! PCHCTEN - Positive Channel Continuous Mode Enable.
26172  *  0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
26173  *  0b1..Positive channel is in Continuous Mode and no special timing is requried.
26174  */
26175 #define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
26176 /*! @} */
26177 
26178 
26179 /*!
26180  * @}
26181  */ /* end of group CMP_Register_Masks */
26182 
26183 
26184 /* CMP - Peripheral instance base addresses */
26185 /** Peripheral CMP1 base address */
26186 #define CMP1_BASE                                (0x401A4000u)
26187 /** Peripheral CMP1 base pointer */
26188 #define CMP1                                     ((CMP_Type *)CMP1_BASE)
26189 /** Peripheral CMP2 base address */
26190 #define CMP2_BASE                                (0x401A8000u)
26191 /** Peripheral CMP2 base pointer */
26192 #define CMP2                                     ((CMP_Type *)CMP2_BASE)
26193 /** Peripheral CMP3 base address */
26194 #define CMP3_BASE                                (0x401AC000u)
26195 /** Peripheral CMP3 base pointer */
26196 #define CMP3                                     ((CMP_Type *)CMP3_BASE)
26197 /** Peripheral CMP4 base address */
26198 #define CMP4_BASE                                (0x401B0000u)
26199 /** Peripheral CMP4 base pointer */
26200 #define CMP4                                     ((CMP_Type *)CMP4_BASE)
26201 /** Array initializer of CMP peripheral base addresses */
26202 #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
26203 /** Array initializer of CMP peripheral base pointers */
26204 #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
26205 /** Interrupt vectors for the CMP peripheral type */
26206 #define CMP_IRQS                                 { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
26207 
26208 /*!
26209  * @}
26210  */ /* end of group CMP_Peripheral_Access_Layer */
26211 
26212 
26213 /* ----------------------------------------------------------------------------
26214    -- CSI Peripheral Access Layer
26215    ---------------------------------------------------------------------------- */
26216 
26217 /*!
26218  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
26219  * @{
26220  */
26221 
26222 /** CSI - Register Layout Typedef */
26223 typedef struct {
26224   __IO uint32_t CR1;                               /**< CSI Control Register 1, offset: 0x0 */
26225   __IO uint32_t CR2;                               /**< CSI Control Register 2, offset: 0x4 */
26226   __IO uint32_t CR3;                               /**< CSI Control Register 3, offset: 0x8 */
26227   __I  uint32_t STATFIFO;                          /**< CSI Statistic FIFO Register, offset: 0xC */
26228   __I  uint32_t RFIFO;                             /**< CSI RX FIFO Register, offset: 0x10 */
26229   __IO uint32_t RXCNT;                             /**< CSI RX Count Register, offset: 0x14 */
26230   __IO uint32_t SR;                                /**< CSI Status Register, offset: 0x18 */
26231        uint8_t RESERVED_0[4];
26232   __IO uint32_t DMASA_STATFIFO;                    /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
26233   __IO uint32_t DMATS_STATFIFO;                    /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
26234   __IO uint32_t DMASA_FB1;                         /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
26235   __IO uint32_t DMASA_FB2;                         /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
26236   __IO uint32_t FBUF_PARA;                         /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
26237   __IO uint32_t IMAG_PARA;                         /**< CSI Image Parameter Register, offset: 0x34 */
26238        uint8_t RESERVED_1[16];
26239   __IO uint32_t CR18;                              /**< CSI Control Register 18, offset: 0x48 */
26240   __IO uint32_t CR19;                              /**< CSI Control Register 19, offset: 0x4C */
26241   __IO uint32_t CR20;                              /**< CSI Control Register 20, offset: 0x50 */
26242   __IO uint32_t CR[256];                           /**< CSI Control Register, array offset: 0x54, array step: 0x4 */
26243 } CSI_Type;
26244 
26245 /* ----------------------------------------------------------------------------
26246    -- CSI Register Masks
26247    ---------------------------------------------------------------------------- */
26248 
26249 /*!
26250  * @addtogroup CSI_Register_Masks CSI Register Masks
26251  * @{
26252  */
26253 
26254 /*! @name CR1 - CSI Control Register 1 */
26255 /*! @{ */
26256 
26257 #define CSI_CR1_PIXEL_BIT_MASK                   (0x1U)
26258 #define CSI_CR1_PIXEL_BIT_SHIFT                  (0U)
26259 /*! PIXEL_BIT
26260  *  0b0..8-bit data for each pixel
26261  *  0b1..10-bit data for each pixel
26262  */
26263 #define CSI_CR1_PIXEL_BIT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
26264 
26265 #define CSI_CR1_REDGE_MASK                       (0x2U)
26266 #define CSI_CR1_REDGE_SHIFT                      (1U)
26267 /*! REDGE
26268  *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
26269  *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
26270  */
26271 #define CSI_CR1_REDGE(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
26272 
26273 #define CSI_CR1_INV_PCLK_MASK                    (0x4U)
26274 #define CSI_CR1_INV_PCLK_SHIFT                   (2U)
26275 /*! INV_PCLK
26276  *  0b0..CSI_PIXCLK is directly applied to internal circuitry
26277  *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
26278  */
26279 #define CSI_CR1_INV_PCLK(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
26280 
26281 #define CSI_CR1_INV_DATA_MASK                    (0x8U)
26282 #define CSI_CR1_INV_DATA_SHIFT                   (3U)
26283 /*! INV_DATA
26284  *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
26285  *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
26286  */
26287 #define CSI_CR1_INV_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
26288 
26289 #define CSI_CR1_GCLK_MODE_MASK                   (0x10U)
26290 #define CSI_CR1_GCLK_MODE_SHIFT                  (4U)
26291 /*! GCLK_MODE
26292  *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
26293  *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
26294  */
26295 #define CSI_CR1_GCLK_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
26296 
26297 #define CSI_CR1_CLR_RXFIFO_MASK                  (0x20U)
26298 #define CSI_CR1_CLR_RXFIFO_SHIFT                 (5U)
26299 #define CSI_CR1_CLR_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
26300 
26301 #define CSI_CR1_CLR_STATFIFO_MASK                (0x40U)
26302 #define CSI_CR1_CLR_STATFIFO_SHIFT               (6U)
26303 #define CSI_CR1_CLR_STATFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
26304 
26305 #define CSI_CR1_PACK_DIR_MASK                    (0x80U)
26306 #define CSI_CR1_PACK_DIR_SHIFT                   (7U)
26307 /*! PACK_DIR
26308  *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
26309  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
26310  *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
26311  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
26312  */
26313 #define CSI_CR1_PACK_DIR(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
26314 
26315 #define CSI_CR1_FCC_MASK                         (0x100U)
26316 #define CSI_CR1_FCC_SHIFT                        (8U)
26317 /*! FCC
26318  *  0b0..Asynchronous FIFO clear is selected.
26319  *  0b1..Synchronous FIFO clear is selected.
26320  */
26321 #define CSI_CR1_FCC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
26322 
26323 #define CSI_CR1_CCIR_EN_MASK                     (0x400U)
26324 #define CSI_CR1_CCIR_EN_SHIFT                    (10U)
26325 /*! CCIR_EN
26326  *  0b0..Traditional interface is selected.
26327  *  0b1..BT.656 interface is selected.
26328  */
26329 #define CSI_CR1_CCIR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
26330 
26331 #define CSI_CR1_HSYNC_POL_MASK                   (0x800U)
26332 #define CSI_CR1_HSYNC_POL_SHIFT                  (11U)
26333 /*! HSYNC_POL
26334  *  0b0..HSYNC is active low
26335  *  0b1..HSYNC is active high
26336  */
26337 #define CSI_CR1_HSYNC_POL(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
26338 
26339 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK      (0x1000U)
26340 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT     (12U)
26341 /*! HISTOGRAM_CALC_DONE_IE
26342  *  0b0..Histogram done interrupt disable
26343  *  0b1..Histogram done interrupt enable
26344  */
26345 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK)
26346 
26347 #define CSI_CR1_SOF_INTEN_MASK                   (0x10000U)
26348 #define CSI_CR1_SOF_INTEN_SHIFT                  (16U)
26349 /*! SOF_INTEN
26350  *  0b0..SOF interrupt disable
26351  *  0b1..SOF interrupt enable
26352  */
26353 #define CSI_CR1_SOF_INTEN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
26354 
26355 #define CSI_CR1_SOF_POL_MASK                     (0x20000U)
26356 #define CSI_CR1_SOF_POL_SHIFT                    (17U)
26357 /*! SOF_POL
26358  *  0b0..SOF interrupt is generated on SOF falling edge
26359  *  0b1..SOF interrupt is generated on SOF rising edge
26360  */
26361 #define CSI_CR1_SOF_POL(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
26362 
26363 #define CSI_CR1_RXFF_INTEN_MASK                  (0x40000U)
26364 #define CSI_CR1_RXFF_INTEN_SHIFT                 (18U)
26365 /*! RXFF_INTEN
26366  *  0b0..RxFIFO full interrupt disable
26367  *  0b1..RxFIFO full interrupt enable
26368  */
26369 #define CSI_CR1_RXFF_INTEN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
26370 
26371 #define CSI_CR1_FB1_DMA_DONE_INTEN_MASK          (0x80000U)
26372 #define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT         (19U)
26373 /*! FB1_DMA_DONE_INTEN
26374  *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
26375  *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
26376  */
26377 #define CSI_CR1_FB1_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
26378 
26379 #define CSI_CR1_FB2_DMA_DONE_INTEN_MASK          (0x100000U)
26380 #define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT         (20U)
26381 /*! FB2_DMA_DONE_INTEN
26382  *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
26383  *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
26384  */
26385 #define CSI_CR1_FB2_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
26386 
26387 #define CSI_CR1_STATFF_INTEN_MASK                (0x200000U)
26388 #define CSI_CR1_STATFF_INTEN_SHIFT               (21U)
26389 /*! STATFF_INTEN
26390  *  0b0..STATFIFO full interrupt disable
26391  *  0b1..STATFIFO full interrupt enable
26392  */
26393 #define CSI_CR1_STATFF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
26394 
26395 #define CSI_CR1_SFF_DMA_DONE_INTEN_MASK          (0x400000U)
26396 #define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT         (22U)
26397 /*! SFF_DMA_DONE_INTEN
26398  *  0b0..STATFIFO DMA Transfer Done interrupt disable
26399  *  0b1..STATFIFO DMA Transfer Done interrupt enable
26400  */
26401 #define CSI_CR1_SFF_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
26402 
26403 #define CSI_CR1_RF_OR_INTEN_MASK                 (0x1000000U)
26404 #define CSI_CR1_RF_OR_INTEN_SHIFT                (24U)
26405 /*! RF_OR_INTEN
26406  *  0b0..RxFIFO overrun interrupt is disabled
26407  *  0b1..RxFIFO overrun interrupt is enabled
26408  */
26409 #define CSI_CR1_RF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
26410 
26411 #define CSI_CR1_SF_OR_INTEN_MASK                 (0x2000000U)
26412 #define CSI_CR1_SF_OR_INTEN_SHIFT                (25U)
26413 /*! SF_OR_INTEN
26414  *  0b0..STATFIFO overrun interrupt is disabled
26415  *  0b1..STATFIFO overrun interrupt is enabled
26416  */
26417 #define CSI_CR1_SF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
26418 
26419 #define CSI_CR1_COF_INT_EN_MASK                  (0x4000000U)
26420 #define CSI_CR1_COF_INT_EN_SHIFT                 (26U)
26421 /*! COF_INT_EN
26422  *  0b0..COF interrupt is disabled
26423  *  0b1..COF interrupt is enabled
26424  */
26425 #define CSI_CR1_COF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
26426 
26427 #define CSI_CR1_VIDEO_MODE_MASK                  (0x8000000U)
26428 #define CSI_CR1_VIDEO_MODE_SHIFT                 (27U)
26429 /*! VIDEO_MODE
26430  *  0b0..Progressive mode is selected
26431  *  0b1..Interlace mode is selected
26432  */
26433 #define CSI_CR1_VIDEO_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK)
26434 
26435 #define CSI_CR1_EOF_INT_EN_MASK                  (0x20000000U)
26436 #define CSI_CR1_EOF_INT_EN_SHIFT                 (29U)
26437 /*! EOF_INT_EN
26438  *  0b0..EOF interrupt is disabled.
26439  *  0b1..EOF interrupt is generated when RX count value is reached.
26440  */
26441 #define CSI_CR1_EOF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
26442 
26443 #define CSI_CR1_EXT_VSYNC_MASK                   (0x40000000U)
26444 #define CSI_CR1_EXT_VSYNC_SHIFT                  (30U)
26445 /*! EXT_VSYNC
26446  *  0b0..Internal VSYNC mode
26447  *  0b1..External VSYNC mode
26448  */
26449 #define CSI_CR1_EXT_VSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
26450 
26451 #define CSI_CR1_SWAP16_EN_MASK                   (0x80000000U)
26452 #define CSI_CR1_SWAP16_EN_SHIFT                  (31U)
26453 /*! SWAP16_EN
26454  *  0b0..Disable swapping
26455  *  0b1..Enable swapping
26456  */
26457 #define CSI_CR1_SWAP16_EN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
26458 /*! @} */
26459 
26460 /*! @name CR2 - CSI Control Register 2 */
26461 /*! @{ */
26462 
26463 #define CSI_CR2_HSC_MASK                         (0xFFU)
26464 #define CSI_CR2_HSC_SHIFT                        (0U)
26465 /*! HSC
26466  *  0b00000000-0b11111111..Number of pixels to skip minus 1
26467  */
26468 #define CSI_CR2_HSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
26469 
26470 #define CSI_CR2_VSC_MASK                         (0xFF00U)
26471 #define CSI_CR2_VSC_SHIFT                        (8U)
26472 /*! VSC
26473  *  0b00000000-0b11111111..Number of rows to skip minus 1
26474  */
26475 #define CSI_CR2_VSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
26476 
26477 #define CSI_CR2_LVRM_MASK                        (0x70000U)
26478 #define CSI_CR2_LVRM_SHIFT                       (16U)
26479 /*! LVRM
26480  *  0b000..512 x 384
26481  *  0b001..448 x 336
26482  *  0b010..384 x 288
26483  *  0b011..384 x 256
26484  *  0b100..320 x 240
26485  *  0b101..288 x 216
26486  *  0b110..400 x 300
26487  */
26488 #define CSI_CR2_LVRM(x)                          (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
26489 
26490 #define CSI_CR2_BTS_MASK                         (0x180000U)
26491 #define CSI_CR2_BTS_SHIFT                        (19U)
26492 /*! BTS
26493  *  0b00..GR
26494  *  0b01..RG
26495  *  0b10..BG
26496  *  0b11..GB
26497  */
26498 #define CSI_CR2_BTS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
26499 
26500 #define CSI_CR2_SCE_MASK                         (0x800000U)
26501 #define CSI_CR2_SCE_SHIFT                        (23U)
26502 /*! SCE
26503  *  0b0..Skip count disable
26504  *  0b1..Skip count enable
26505  */
26506 #define CSI_CR2_SCE(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
26507 
26508 #define CSI_CR2_AFS_MASK                         (0x3000000U)
26509 #define CSI_CR2_AFS_SHIFT                        (24U)
26510 /*! AFS
26511  *  0b00..Abs Diff on consecutive green pixels
26512  *  0b01..Abs Diff on every third green pixels
26513  *  0b1x..Abs Diff on every four green pixels
26514  */
26515 #define CSI_CR2_AFS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
26516 
26517 #define CSI_CR2_DRM_MASK                         (0x4000000U)
26518 #define CSI_CR2_DRM_SHIFT                        (26U)
26519 /*! DRM
26520  *  0b0..Stats grid of 8 x 6
26521  *  0b1..Stats grid of 8 x 12
26522  */
26523 #define CSI_CR2_DRM(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
26524 
26525 #define CSI_CR2_DMA_BURST_TYPE_SFF_MASK          (0x30000000U)
26526 #define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT         (28U)
26527 /*! DMA_BURST_TYPE_SFF
26528  *  0bx0..INCR8
26529  *  0b01..INCR4
26530  *  0b11..INCR16
26531  */
26532 #define CSI_CR2_DMA_BURST_TYPE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
26533 
26534 #define CSI_CR2_DMA_BURST_TYPE_RFF_MASK          (0xC0000000U)
26535 #define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT         (30U)
26536 /*! DMA_BURST_TYPE_RFF
26537  *  0bx0..INCR8
26538  *  0b01..INCR4
26539  *  0b11..INCR16
26540  */
26541 #define CSI_CR2_DMA_BURST_TYPE_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
26542 /*! @} */
26543 
26544 /*! @name CR3 - CSI Control Register 3 */
26545 /*! @{ */
26546 
26547 #define CSI_CR3_ECC_AUTO_EN_MASK                 (0x1U)
26548 #define CSI_CR3_ECC_AUTO_EN_SHIFT                (0U)
26549 /*! ECC_AUTO_EN
26550  *  0b0..Auto Error correction is disabled.
26551  *  0b1..Auto Error correction is enabled.
26552  */
26553 #define CSI_CR3_ECC_AUTO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
26554 
26555 #define CSI_CR3_ECC_INT_EN_MASK                  (0x2U)
26556 #define CSI_CR3_ECC_INT_EN_SHIFT                 (1U)
26557 /*! ECC_INT_EN
26558  *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
26559  *  0b1..Interrupt is generated when error is detected.
26560  */
26561 #define CSI_CR3_ECC_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
26562 
26563 #define CSI_CR3_ZERO_PACK_EN_MASK                (0x4U)
26564 #define CSI_CR3_ZERO_PACK_EN_SHIFT               (2U)
26565 /*! ZERO_PACK_EN
26566  *  0b0..Zero packing disabled
26567  *  0b1..Zero packing enabled
26568  */
26569 #define CSI_CR3_ZERO_PACK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
26570 
26571 #define CSI_CR3_SENSOR_16BITS_MASK               (0x8U)
26572 #define CSI_CR3_SENSOR_16BITS_SHIFT              (3U)
26573 /*! SENSOR_16BITS
26574  *  0b0..Only one 8-bit sensor is connected.
26575  *  0b1..One 16-bit sensor is connected.
26576  */
26577 #define CSI_CR3_SENSOR_16BITS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
26578 
26579 #define CSI_CR3_RxFF_LEVEL_MASK                  (0x70U)
26580 #define CSI_CR3_RxFF_LEVEL_SHIFT                 (4U)
26581 /*! RxFF_LEVEL
26582  *  0b000..4 Double words
26583  *  0b001..8 Double words
26584  *  0b010..16 Double words
26585  *  0b011..24 Double words
26586  *  0b100..32 Double words
26587  *  0b101..48 Double words
26588  *  0b110..64 Double words
26589  *  0b111..96 Double words
26590  */
26591 #define CSI_CR3_RxFF_LEVEL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
26592 
26593 #define CSI_CR3_HRESP_ERR_EN_MASK                (0x80U)
26594 #define CSI_CR3_HRESP_ERR_EN_SHIFT               (7U)
26595 /*! HRESP_ERR_EN
26596  *  0b0..Disable hresponse error interrupt
26597  *  0b1..Enable hresponse error interrupt
26598  */
26599 #define CSI_CR3_HRESP_ERR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
26600 
26601 #define CSI_CR3_STATFF_LEVEL_MASK                (0x700U)
26602 #define CSI_CR3_STATFF_LEVEL_SHIFT               (8U)
26603 /*! STATFF_LEVEL
26604  *  0b000..4 Double words
26605  *  0b001..8 Double words
26606  *  0b010..12 Double words
26607  *  0b011..16 Double words
26608  *  0b100..24 Double words
26609  *  0b101..32 Double words
26610  *  0b110..48 Double words
26611  *  0b111..64 Double words
26612  */
26613 #define CSI_CR3_STATFF_LEVEL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
26614 
26615 #define CSI_CR3_DMA_REQ_EN_SFF_MASK              (0x800U)
26616 #define CSI_CR3_DMA_REQ_EN_SFF_SHIFT             (11U)
26617 /*! DMA_REQ_EN_SFF
26618  *  0b0..Disable the dma request
26619  *  0b1..Enable the dma request
26620  */
26621 #define CSI_CR3_DMA_REQ_EN_SFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
26622 
26623 #define CSI_CR3_DMA_REQ_EN_RFF_MASK              (0x1000U)
26624 #define CSI_CR3_DMA_REQ_EN_RFF_SHIFT             (12U)
26625 /*! DMA_REQ_EN_RFF
26626  *  0b0..Disable the dma request
26627  *  0b1..Enable the dma request
26628  */
26629 #define CSI_CR3_DMA_REQ_EN_RFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
26630 
26631 #define CSI_CR3_DMA_REFLASH_SFF_MASK             (0x2000U)
26632 #define CSI_CR3_DMA_REFLASH_SFF_SHIFT            (13U)
26633 /*! DMA_REFLASH_SFF
26634  *  0b0..No reflashing
26635  *  0b1..Reflash the embedded DMA controller
26636  */
26637 #define CSI_CR3_DMA_REFLASH_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
26638 
26639 #define CSI_CR3_DMA_REFLASH_RFF_MASK             (0x4000U)
26640 #define CSI_CR3_DMA_REFLASH_RFF_SHIFT            (14U)
26641 /*! DMA_REFLASH_RFF
26642  *  0b0..No reflashing
26643  *  0b1..Reflash the embedded DMA controller
26644  */
26645 #define CSI_CR3_DMA_REFLASH_RFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
26646 
26647 #define CSI_CR3_FRMCNT_RST_MASK                  (0x8000U)
26648 #define CSI_CR3_FRMCNT_RST_SHIFT                 (15U)
26649 /*! FRMCNT_RST
26650  *  0b0..Do not reset
26651  *  0b1..Reset frame counter immediately
26652  */
26653 #define CSI_CR3_FRMCNT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
26654 
26655 #define CSI_CR3_FRMCNT_MASK                      (0xFFFF0000U)
26656 #define CSI_CR3_FRMCNT_SHIFT                     (16U)
26657 #define CSI_CR3_FRMCNT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
26658 /*! @} */
26659 
26660 /*! @name STATFIFO - CSI Statistic FIFO Register */
26661 /*! @{ */
26662 
26663 #define CSI_STATFIFO_STAT_MASK                   (0xFFFFFFFFU)
26664 #define CSI_STATFIFO_STAT_SHIFT                  (0U)
26665 #define CSI_STATFIFO_STAT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
26666 /*! @} */
26667 
26668 /*! @name RFIFO - CSI RX FIFO Register */
26669 /*! @{ */
26670 
26671 #define CSI_RFIFO_IMAGE_MASK                     (0xFFFFFFFFU)
26672 #define CSI_RFIFO_IMAGE_SHIFT                    (0U)
26673 #define CSI_RFIFO_IMAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
26674 /*! @} */
26675 
26676 /*! @name RXCNT - CSI RX Count Register */
26677 /*! @{ */
26678 
26679 #define CSI_RXCNT_RXCNT_MASK                     (0x3FFFFFU)
26680 #define CSI_RXCNT_RXCNT_SHIFT                    (0U)
26681 #define CSI_RXCNT_RXCNT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
26682 /*! @} */
26683 
26684 /*! @name SR - CSI Status Register */
26685 /*! @{ */
26686 
26687 #define CSI_SR_DRDY_MASK                         (0x1U)
26688 #define CSI_SR_DRDY_SHIFT                        (0U)
26689 /*! DRDY
26690  *  0b0..No data (word) is ready
26691  *  0b1..At least 1 datum (word) is ready in RXFIFO.
26692  */
26693 #define CSI_SR_DRDY(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
26694 
26695 #define CSI_SR_ECC_INT_MASK                      (0x2U)
26696 #define CSI_SR_ECC_INT_SHIFT                     (1U)
26697 /*! ECC_INT
26698  *  0b0..No error detected
26699  *  0b1..Error is detected in BT.656 coding
26700  */
26701 #define CSI_SR_ECC_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
26702 
26703 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK      (0x4U)
26704 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT     (2U)
26705 /*! HISTOGRAM_CALC_DONE_INT
26706  *  0b0..Histogram calculation is not finished
26707  *  0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
26708  */
26709 #define CSI_SR_HISTOGRAM_CALC_DONE_INT(x)        (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK)
26710 
26711 #define CSI_SR_HRESP_ERR_INT_MASK                (0x80U)
26712 #define CSI_SR_HRESP_ERR_INT_SHIFT               (7U)
26713 /*! HRESP_ERR_INT
26714  *  0b0..No hresponse error.
26715  *  0b1..Hresponse error is detected.
26716  */
26717 #define CSI_SR_HRESP_ERR_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
26718 
26719 #define CSI_SR_COF_INT_MASK                      (0x2000U)
26720 #define CSI_SR_COF_INT_SHIFT                     (13U)
26721 /*! COF_INT
26722  *  0b0..Video field has no change.
26723  *  0b1..Change of video field is detected.
26724  */
26725 #define CSI_SR_COF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
26726 
26727 #define CSI_SR_F1_INT_MASK                       (0x4000U)
26728 #define CSI_SR_F1_INT_SHIFT                      (14U)
26729 /*! F1_INT
26730  *  0b0..Field 1 of video is not detected.
26731  *  0b1..Field 1 of video is about to start.
26732  */
26733 #define CSI_SR_F1_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
26734 
26735 #define CSI_SR_F2_INT_MASK                       (0x8000U)
26736 #define CSI_SR_F2_INT_SHIFT                      (15U)
26737 /*! F2_INT
26738  *  0b0..Field 2 of video is not detected
26739  *  0b1..Field 2 of video is about to start
26740  */
26741 #define CSI_SR_F2_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
26742 
26743 #define CSI_SR_SOF_INT_MASK                      (0x10000U)
26744 #define CSI_SR_SOF_INT_SHIFT                     (16U)
26745 /*! SOF_INT
26746  *  0b0..SOF is not detected.
26747  *  0b1..SOF is detected.
26748  */
26749 #define CSI_SR_SOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
26750 
26751 #define CSI_SR_EOF_INT_MASK                      (0x20000U)
26752 #define CSI_SR_EOF_INT_SHIFT                     (17U)
26753 /*! EOF_INT
26754  *  0b0..EOF is not detected.
26755  *  0b1..EOF is detected.
26756  */
26757 #define CSI_SR_EOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
26758 
26759 #define CSI_SR_RxFF_INT_MASK                     (0x40000U)
26760 #define CSI_SR_RxFF_INT_SHIFT                    (18U)
26761 /*! RxFF_INT
26762  *  0b0..RxFIFO is not full.
26763  *  0b1..RxFIFO is full.
26764  */
26765 #define CSI_SR_RxFF_INT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
26766 
26767 #define CSI_SR_DMA_TSF_DONE_FB1_MASK             (0x80000U)
26768 #define CSI_SR_DMA_TSF_DONE_FB1_SHIFT            (19U)
26769 /*! DMA_TSF_DONE_FB1
26770  *  0b0..DMA transfer is not completed.
26771  *  0b1..DMA transfer is completed.
26772  */
26773 #define CSI_SR_DMA_TSF_DONE_FB1(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
26774 
26775 #define CSI_SR_DMA_TSF_DONE_FB2_MASK             (0x100000U)
26776 #define CSI_SR_DMA_TSF_DONE_FB2_SHIFT            (20U)
26777 /*! DMA_TSF_DONE_FB2
26778  *  0b0..DMA transfer is not completed.
26779  *  0b1..DMA transfer is completed.
26780  */
26781 #define CSI_SR_DMA_TSF_DONE_FB2(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
26782 
26783 #define CSI_SR_STATFF_INT_MASK                   (0x200000U)
26784 #define CSI_SR_STATFF_INT_SHIFT                  (21U)
26785 /*! STATFF_INT
26786  *  0b0..STATFIFO is not full.
26787  *  0b1..STATFIFO is full.
26788  */
26789 #define CSI_SR_STATFF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
26790 
26791 #define CSI_SR_DMA_TSF_DONE_SFF_MASK             (0x400000U)
26792 #define CSI_SR_DMA_TSF_DONE_SFF_SHIFT            (22U)
26793 /*! DMA_TSF_DONE_SFF
26794  *  0b0..DMA transfer is not completed.
26795  *  0b1..DMA transfer is completed.
26796  */
26797 #define CSI_SR_DMA_TSF_DONE_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
26798 
26799 #define CSI_SR_RF_OR_INT_MASK                    (0x1000000U)
26800 #define CSI_SR_RF_OR_INT_SHIFT                   (24U)
26801 /*! RF_OR_INT
26802  *  0b0..RXFIFO has not overflowed.
26803  *  0b1..RXFIFO has overflowed.
26804  */
26805 #define CSI_SR_RF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
26806 
26807 #define CSI_SR_SF_OR_INT_MASK                    (0x2000000U)
26808 #define CSI_SR_SF_OR_INT_SHIFT                   (25U)
26809 /*! SF_OR_INT
26810  *  0b0..STATFIFO has not overflowed.
26811  *  0b1..STATFIFO has overflowed.
26812  */
26813 #define CSI_SR_SF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
26814 
26815 #define CSI_SR_DMA_FIELD1_DONE_MASK              (0x4000000U)
26816 #define CSI_SR_DMA_FIELD1_DONE_SHIFT             (26U)
26817 #define CSI_SR_DMA_FIELD1_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
26818 
26819 #define CSI_SR_DMA_FIELD0_DONE_MASK              (0x8000000U)
26820 #define CSI_SR_DMA_FIELD0_DONE_SHIFT             (27U)
26821 #define CSI_SR_DMA_FIELD0_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
26822 
26823 #define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK       (0x10000000U)
26824 #define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT      (28U)
26825 #define CSI_SR_BASEADDR_CHHANGE_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
26826 /*! @} */
26827 
26828 /*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
26829 /*! @{ */
26830 
26831 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
26832 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
26833 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
26834 /*! @} */
26835 
26836 /*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
26837 /*! @{ */
26838 
26839 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
26840 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
26841 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)   (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
26842 /*! @} */
26843 
26844 /*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
26845 /*! @{ */
26846 
26847 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK    (0xFFFFFFFCU)
26848 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT   (2U)
26849 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
26850 /*! @} */
26851 
26852 /*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
26853 /*! @{ */
26854 
26855 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK    (0xFFFFFFFCU)
26856 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT   (2U)
26857 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
26858 /*! @} */
26859 
26860 /*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */
26861 /*! @{ */
26862 
26863 #define CSI_FBUF_PARA_FBUF_STRIDE_MASK           (0xFFFFU)
26864 #define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT          (0U)
26865 #define CSI_FBUF_PARA_FBUF_STRIDE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
26866 
26867 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK    (0xFFFF0000U)
26868 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT   (16U)
26869 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)      (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
26870 /*! @} */
26871 
26872 /*! @name IMAG_PARA - CSI Image Parameter Register */
26873 /*! @{ */
26874 
26875 #define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK          (0xFFFFU)
26876 #define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT         (0U)
26877 #define CSI_IMAG_PARA_IMAGE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
26878 
26879 #define CSI_IMAG_PARA_IMAGE_WIDTH_MASK           (0xFFFF0000U)
26880 #define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT          (16U)
26881 #define CSI_IMAG_PARA_IMAGE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
26882 /*! @} */
26883 
26884 /*! @name CR18 - CSI Control Register 18 */
26885 /*! @{ */
26886 
26887 #define CSI_CR18_NTSC_EN_MASK                    (0x1U)
26888 #define CSI_CR18_NTSC_EN_SHIFT                   (0U)
26889 /*! NTSC_EN
26890  *  0b0..PAL
26891  *  0b1..NTSC
26892  */
26893 #define CSI_CR18_NTSC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK)
26894 
26895 #define CSI_CR18_TVDECODER_IN_EN_MASK            (0x2U)
26896 #define CSI_CR18_TVDECODER_IN_EN_SHIFT           (1U)
26897 #define CSI_CR18_TVDECODER_IN_EN(x)              (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK)
26898 
26899 #define CSI_CR18_DEINTERLACE_EN_MASK             (0x4U)
26900 #define CSI_CR18_DEINTERLACE_EN_SHIFT            (2U)
26901 /*! DEINTERLACE_EN
26902  *  0b0..Deinterlace disabled
26903  *  0b1..Deinterlace enabled
26904  */
26905 #define CSI_CR18_DEINTERLACE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
26906 
26907 #define CSI_CR18_PARALLEL24_EN_MASK              (0x8U)
26908 #define CSI_CR18_PARALLEL24_EN_SHIFT             (3U)
26909 /*! PARALLEL24_EN
26910  *  0b0..Input is disabled
26911  *  0b1..Input is enabled
26912  */
26913 #define CSI_CR18_PARALLEL24_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
26914 
26915 #define CSI_CR18_BASEADDR_SWITCH_EN_MASK         (0x10U)
26916 #define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT        (4U)
26917 #define CSI_CR18_BASEADDR_SWITCH_EN(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
26918 
26919 #define CSI_CR18_BASEADDR_SWITCH_SEL_MASK        (0x20U)
26920 #define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT       (5U)
26921 /*! BASEADDR_SWITCH_SEL
26922  *  0b0..Switching base address at the edge of the vsync
26923  *  0b1..Switching base address at the edge of the first data of each frame
26924  */
26925 #define CSI_CR18_BASEADDR_SWITCH_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
26926 
26927 #define CSI_CR18_FIELD0_DONE_IE_MASK             (0x40U)
26928 #define CSI_CR18_FIELD0_DONE_IE_SHIFT            (6U)
26929 /*! FIELD0_DONE_IE
26930  *  0b0..Interrupt disabled
26931  *  0b1..Interrupt enabled
26932  */
26933 #define CSI_CR18_FIELD0_DONE_IE(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
26934 
26935 #define CSI_CR18_DMA_FIELD1_DONE_IE_MASK         (0x80U)
26936 #define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT        (7U)
26937 /*! DMA_FIELD1_DONE_IE
26938  *  0b0..Interrupt disabled
26939  *  0b1..Interrupt enabled
26940  */
26941 #define CSI_CR18_DMA_FIELD1_DONE_IE(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
26942 
26943 #define CSI_CR18_LAST_DMA_REQ_SEL_MASK           (0x100U)
26944 #define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT          (8U)
26945 /*! LAST_DMA_REQ_SEL
26946  *  0b0..fifo_full_level
26947  *  0b1..hburst_length
26948  */
26949 #define CSI_CR18_LAST_DMA_REQ_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
26950 
26951 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK   (0x200U)
26952 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT  (9U)
26953 /*! BASEADDR_CHANGE_ERROR_IE
26954  *  0b0..Interrupt disabled
26955  *  0b1..Interrupt enabled
26956  */
26957 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)     (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
26958 
26959 #define CSI_CR18_RGB888A_FORMAT_SEL_MASK         (0x400U)
26960 #define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT        (10U)
26961 /*! RGB888A_FORMAT_SEL
26962  *  0b0..{8'h0, data[23:0]}
26963  *  0b1..{data[23:0], 8'h0}
26964  */
26965 #define CSI_CR18_RGB888A_FORMAT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
26966 
26967 #define CSI_CR18_AHB_HPROT_MASK                  (0xF000U)
26968 #define CSI_CR18_AHB_HPROT_SHIFT                 (12U)
26969 #define CSI_CR18_AHB_HPROT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
26970 
26971 #define CSI_CR18_MASK_OPTION_MASK                (0xC0000U)
26972 #define CSI_CR18_MASK_OPTION_SHIFT               (18U)
26973 /*! MASK_OPTION
26974  *  0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1.
26975  *  0b01..Writing to memory when CSI_ENABLE is 1.
26976  *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
26977  *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
26978  */
26979 #define CSI_CR18_MASK_OPTION(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
26980 
26981 #define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK          (0x100000U)
26982 #define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT         (20U)
26983 /*! MIPI_DOUBLE_CMPNT
26984  *  0b0..Single component per clock cycle (half pixel per clock cycle)
26985  *  0b1..Double component per clock cycle (a pixel per clock cycle)
26986  */
26987 #define CSI_CR18_MIPI_DOUBLE_CMPNT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK)
26988 
26989 #define CSI_CR18_MIPI_YU_SWAP_MASK               (0x200000U)
26990 #define CSI_CR18_MIPI_YU_SWAP_SHIFT              (21U)
26991 /*! MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode.
26992  */
26993 #define CSI_CR18_MIPI_YU_SWAP(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK)
26994 
26995 #define CSI_CR18_DATA_FROM_MIPI_MASK             (0x400000U)
26996 #define CSI_CR18_DATA_FROM_MIPI_SHIFT            (22U)
26997 /*! DATA_FROM_MIPI
26998  *  0b0..Data from parallel sensor
26999  *  0b1..Data from MIPI
27000  */
27001 #define CSI_CR18_DATA_FROM_MIPI(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK)
27002 
27003 #define CSI_CR18_LINE_STRIDE_EN_MASK             (0x1000000U)
27004 #define CSI_CR18_LINE_STRIDE_EN_SHIFT            (24U)
27005 #define CSI_CR18_LINE_STRIDE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK)
27006 
27007 #define CSI_CR18_MIPI_DATA_FORMAT_MASK           (0x7E000000U)
27008 #define CSI_CR18_MIPI_DATA_FORMAT_SHIFT          (25U)
27009 /*! MIPI_DATA_FORMAT - Image Data Format
27010  */
27011 #define CSI_CR18_MIPI_DATA_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK)
27012 
27013 #define CSI_CR18_CSI_ENABLE_MASK                 (0x80000000U)
27014 #define CSI_CR18_CSI_ENABLE_SHIFT                (31U)
27015 #define CSI_CR18_CSI_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
27016 /*! @} */
27017 
27018 /*! @name CR19 - CSI Control Register 19 */
27019 /*! @{ */
27020 
27021 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
27022 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
27023 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
27024 /*! @} */
27025 
27026 /*! @name CR20 - CSI Control Register 20 */
27027 /*! @{ */
27028 
27029 #define CSI_CR20_THRESHOLD_MASK                  (0xFFU)
27030 #define CSI_CR20_THRESHOLD_SHIFT                 (0U)
27031 #define CSI_CR20_THRESHOLD(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK)
27032 
27033 #define CSI_CR20_BINARY_EN_MASK                  (0x100U)
27034 #define CSI_CR20_BINARY_EN_SHIFT                 (8U)
27035 /*! BINARY_EN
27036  *  0b0..Output is Y8 format(8 bits each pixel)
27037  *  0b1..Output is Y1 format(1 bit each pixel)
27038  */
27039 #define CSI_CR20_BINARY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK)
27040 
27041 #define CSI_CR20_QR_DATA_FORMAT_MASK             (0xE00U)
27042 #define CSI_CR20_QR_DATA_FORMAT_SHIFT            (9U)
27043 /*! QR_DATA_FORMAT
27044  *  0b000..YU YV one cycle per 1 pixel input
27045  *  0b001..UY VY one cycle per1 pixel input
27046  *  0b010..Y U Y V two cycles per 1 pixel input
27047  *  0b011..U Y V Y two cycles per 1 pixel input
27048  *  0b100..YUV one cycle per 1 pixel input
27049  *  0b101..Y U V three cycles per 1 pixel input
27050  */
27051 #define CSI_CR20_QR_DATA_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK)
27052 
27053 #define CSI_CR20_BIG_END_MASK                    (0x1000U)
27054 #define CSI_CR20_BIG_END_SHIFT                   (12U)
27055 /*! BIG_END
27056  *  0b0..The newest (most recent) data will be assigned the lowest position when store to memory.
27057  *  0b1..The newest (most recent) data will be assigned the highest position when store to memory.
27058  */
27059 #define CSI_CR20_BIG_END(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK)
27060 
27061 #define CSI_CR20_10BIT_NEW_EN_MASK               (0x20000000U)
27062 #define CSI_CR20_10BIT_NEW_EN_SHIFT              (29U)
27063 /*! 10BIT_NEW_EN
27064  *  0b0..When input 8bits data, it will use the data[9:2]
27065  *  0b1..If input is 10bits data, it will use the data[7:0] (optional)
27066  */
27067 #define CSI_CR20_10BIT_NEW_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK)
27068 
27069 #define CSI_CR20_HISTOGRAM_EN_MASK               (0x40000000U)
27070 #define CSI_CR20_HISTOGRAM_EN_SHIFT              (30U)
27071 /*! HISTOGRAM_EN
27072  *  0b0..Histogram disable
27073  *  0b1..Histogram enable
27074  */
27075 #define CSI_CR20_HISTOGRAM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK)
27076 
27077 #define CSI_CR20_QRCODE_EN_MASK                  (0x80000000U)
27078 #define CSI_CR20_QRCODE_EN_SHIFT                 (31U)
27079 /*! QRCODE_EN
27080  *  0b0..Normal mode
27081  *  0b1..Gray scale mode
27082  */
27083 #define CSI_CR20_QRCODE_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK)
27084 /*! @} */
27085 
27086 /*! @name CR - CSI Control Register */
27087 /*! @{ */
27088 
27089 #define CSI_CR_PIXEL_COUNTERS_MASK               (0xFFFFFFU)
27090 #define CSI_CR_PIXEL_COUNTERS_SHIFT              (0U)
27091 #define CSI_CR_PIXEL_COUNTERS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK)
27092 /*! @} */
27093 
27094 /* The count of CSI_CR */
27095 #define CSI_CR_COUNT                             (256U)
27096 
27097 
27098 /*!
27099  * @}
27100  */ /* end of group CSI_Register_Masks */
27101 
27102 
27103 /* CSI - Peripheral instance base addresses */
27104 /** Peripheral CSI base address */
27105 #define CSI_BASE                                 (0x40800000u)
27106 /** Peripheral CSI base pointer */
27107 #define CSI                                      ((CSI_Type *)CSI_BASE)
27108 /** Array initializer of CSI peripheral base addresses */
27109 #define CSI_BASE_ADDRS                           { CSI_BASE }
27110 /** Array initializer of CSI peripheral base pointers */
27111 #define CSI_BASE_PTRS                            { CSI }
27112 /** Interrupt vectors for the CSI peripheral type */
27113 #define CSI_IRQS                                 { CSI_IRQn }
27114 /* Backward compatibility */
27115 #define CSI_CSICR1_PIXEL_BIT_MASK     CSI_CR1_PIXEL_BIT_MASK
27116 #define CSI_CSICR1_PIXEL_BIT_SHIFT     CSI_CR1_PIXEL_BIT_SHIFT
27117 #define CSI_CSICR1_PIXEL_BIT(x)     CSI_CR1_PIXEL_BIT(x)
27118 #define CSI_CSICR1_REDGE_MASK     CSI_CR1_REDGE_MASK
27119 #define CSI_CSICR1_REDGE_SHIFT     CSI_CR1_REDGE_SHIFT
27120 #define CSI_CSICR1_REDGE(x)     CSI_CR1_REDGE(x)
27121 #define CSI_CSICR1_INV_PCLK_MASK     CSI_CR1_INV_PCLK_MASK
27122 #define CSI_CSICR1_INV_PCLK_SHIFT     CSI_CR1_INV_PCLK_SHIFT
27123 #define CSI_CSICR1_INV_PCLK(x)     CSI_CR1_INV_PCLK(x)
27124 #define CSI_CSICR1_INV_DATA_MASK     CSI_CR1_INV_DATA_MASK
27125 #define CSI_CSICR1_INV_DATA_SHIFT     CSI_CR1_INV_DATA_SHIFT
27126 #define CSI_CSICR1_INV_DATA(x)     CSI_CR1_INV_DATA(x)
27127 #define CSI_CSICR1_GCLK_MODE_MASK     CSI_CR1_GCLK_MODE_MASK
27128 #define CSI_CSICR1_GCLK_MODE_SHIFT     CSI_CR1_GCLK_MODE_SHIFT
27129 #define CSI_CSICR1_GCLK_MODE(x)     CSI_CR1_GCLK_MODE(x)
27130 #define CSI_CSICR1_CLR_RXFIFO_MASK     CSI_CR1_CLR_RXFIFO_MASK
27131 #define CSI_CSICR1_CLR_RXFIFO_SHIFT     CSI_CR1_CLR_RXFIFO_SHIFT
27132 #define CSI_CSICR1_CLR_RXFIFO(x)     CSI_CR1_CLR_RXFIFO(x)
27133 #define CSI_CSICR1_CLR_STATFIFO_MASK     CSI_CR1_CLR_STATFIFO_MASK
27134 #define CSI_CSICR1_CLR_STATFIFO_SHIFT     CSI_CR1_CLR_STATFIFO_SHIFT
27135 #define CSI_CSICR1_CLR_STATFIFO(x)     CSI_CR1_CLR_STATFIFO(x)
27136 #define CSI_CSICR1_PACK_DIR_MASK     CSI_CR1_PACK_DIR_MASK
27137 #define CSI_CSICR1_PACK_DIR_SHIFT     CSI_CR1_PACK_DIR_SHIFT
27138 #define CSI_CSICR1_PACK_DIR(x)     CSI_CR1_PACK_DIR(x)
27139 #define CSI_CSICR1_FCC_MASK     CSI_CR1_FCC_MASK
27140 #define CSI_CSICR1_FCC_SHIFT     CSI_CR1_FCC_SHIFT
27141 #define CSI_CSICR1_FCC(x)     CSI_CR1_FCC(x)
27142 #define CSI_CSICR1_CCIR_EN_MASK     CSI_CR1_CCIR_EN_MASK
27143 #define CSI_CSICR1_CCIR_EN_SHIFT     CSI_CR1_CCIR_EN_SHIFT
27144 #define CSI_CSICR1_CCIR_EN(x)     CSI_CR1_CCIR_EN(x)
27145 #define CSI_CSICR1_HSYNC_POL_MASK     CSI_CR1_HSYNC_POL_MASK
27146 #define CSI_CSICR1_HSYNC_POL_SHIFT     CSI_CR1_HSYNC_POL_SHIFT
27147 #define CSI_CSICR1_HSYNC_POL(x)     CSI_CR1_HSYNC_POL(x)
27148 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK     CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
27149 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT     CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
27150 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x)     CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
27151 #define CSI_CSICR1_SOF_INTEN_MASK     CSI_CR1_SOF_INTEN_MASK
27152 #define CSI_CSICR1_SOF_INTEN_SHIFT     CSI_CR1_SOF_INTEN_SHIFT
27153 #define CSI_CSICR1_SOF_INTEN(x)     CSI_CR1_SOF_INTEN(x)
27154 #define CSI_CSICR1_SOF_POL_MASK     CSI_CR1_SOF_POL_MASK
27155 #define CSI_CSICR1_SOF_POL_SHIFT     CSI_CR1_SOF_POL_SHIFT
27156 #define CSI_CSICR1_SOF_POL(x)     CSI_CR1_SOF_POL(x)
27157 #define CSI_CSICR1_RXFF_INTEN_MASK     CSI_CR1_RXFF_INTEN_MASK
27158 #define CSI_CSICR1_RXFF_INTEN_SHIFT     CSI_CR1_RXFF_INTEN_SHIFT
27159 #define CSI_CSICR1_RXFF_INTEN(x)     CSI_CR1_RXFF_INTEN(x)
27160 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK     CSI_CR1_FB1_DMA_DONE_INTEN_MASK
27161 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
27162 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x)     CSI_CR1_FB1_DMA_DONE_INTEN(x)
27163 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK     CSI_CR1_FB2_DMA_DONE_INTEN_MASK
27164 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
27165 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x)     CSI_CR1_FB2_DMA_DONE_INTEN(x)
27166 #define CSI_CSICR1_STATFF_INTEN_MASK     CSI_CR1_STATFF_INTEN_MASK
27167 #define CSI_CSICR1_STATFF_INTEN_SHIFT     CSI_CR1_STATFF_INTEN_SHIFT
27168 #define CSI_CSICR1_STATFF_INTEN(x)     CSI_CR1_STATFF_INTEN(x)
27169 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK     CSI_CR1_SFF_DMA_DONE_INTEN_MASK
27170 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT     CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
27171 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x)     CSI_CR1_SFF_DMA_DONE_INTEN(x)
27172 #define CSI_CSICR1_RF_OR_INTEN_MASK     CSI_CR1_RF_OR_INTEN_MASK
27173 #define CSI_CSICR1_RF_OR_INTEN_SHIFT     CSI_CR1_RF_OR_INTEN_SHIFT
27174 #define CSI_CSICR1_RF_OR_INTEN(x)     CSI_CR1_RF_OR_INTEN(x)
27175 #define CSI_CSICR1_SF_OR_INTEN_MASK     CSI_CR1_SF_OR_INTEN_MASK
27176 #define CSI_CSICR1_SF_OR_INTEN_SHIFT     CSI_CR1_SF_OR_INTEN_SHIFT
27177 #define CSI_CSICR1_SF_OR_INTEN(x)     CSI_CR1_SF_OR_INTEN(x)
27178 #define CSI_CSICR1_COF_INT_EN_MASK     CSI_CR1_COF_INT_EN_MASK
27179 #define CSI_CSICR1_COF_INT_EN_SHIFT     CSI_CR1_COF_INT_EN_SHIFT
27180 #define CSI_CSICR1_COF_INT_EN(x)     CSI_CR1_COF_INT_EN(x)
27181 #define CSI_CSICR1_VIDEO_MODE_MASK     CSI_CR1_VIDEO_MODE_MASK
27182 #define CSI_CSICR1_VIDEO_MODE_SHIFT     CSI_CR1_VIDEO_MODE_SHIFT
27183 #define CSI_CSICR1_VIDEO_MODE(x)     CSI_CR1_VIDEO_MODE(x)
27184 #define CSI_CSICR1_EOF_INT_EN_MASK     CSI_CR1_EOF_INT_EN_MASK
27185 #define CSI_CSICR1_EOF_INT_EN_SHIFT     CSI_CR1_EOF_INT_EN_SHIFT
27186 #define CSI_CSICR1_EOF_INT_EN(x)     CSI_CR1_EOF_INT_EN(x)
27187 #define CSI_CSICR1_EXT_VSYNC_MASK     CSI_CR1_EXT_VSYNC_MASK
27188 #define CSI_CSICR1_EXT_VSYNC_SHIFT     CSI_CR1_EXT_VSYNC_SHIFT
27189 #define CSI_CSICR1_EXT_VSYNC(x)     CSI_CR1_EXT_VSYNC(x)
27190 #define CSI_CSICR1_SWAP16_EN_MASK     CSI_CR1_SWAP16_EN_MASK
27191 #define CSI_CSICR1_SWAP16_EN_SHIFT     CSI_CR1_SWAP16_EN_SHIFT
27192 #define CSI_CSICR1_SWAP16_EN(x)     CSI_CR1_SWAP16_EN(x)
27193 #define CSI_CSICR2_HSC_MASK     CSI_CR2_HSC_MASK
27194 #define CSI_CSICR2_HSC_SHIFT     CSI_CR2_HSC_SHIFT
27195 #define CSI_CSICR2_HSC(x)     CSI_CR2_HSC(x)
27196 #define CSI_CSICR2_VSC_MASK     CSI_CR2_VSC_MASK
27197 #define CSI_CSICR2_VSC_SHIFT     CSI_CR2_VSC_SHIFT
27198 #define CSI_CSICR2_VSC(x)     CSI_CR2_VSC(x)
27199 #define CSI_CSICR2_LVRM_MASK     CSI_CR2_LVRM_MASK
27200 #define CSI_CSICR2_LVRM_SHIFT     CSI_CR2_LVRM_SHIFT
27201 #define CSI_CSICR2_LVRM(x)     CSI_CR2_LVRM(x)
27202 #define CSI_CSICR2_BTS_MASK     CSI_CR2_BTS_MASK
27203 #define CSI_CSICR2_BTS_SHIFT     CSI_CR2_BTS_SHIFT
27204 #define CSI_CSICR2_BTS(x)     CSI_CR2_BTS(x)
27205 #define CSI_CSICR2_SCE_MASK     CSI_CR2_SCE_MASK
27206 #define CSI_CSICR2_SCE_SHIFT     CSI_CR2_SCE_SHIFT
27207 #define CSI_CSICR2_SCE(x)     CSI_CR2_SCE(x)
27208 #define CSI_CSICR2_AFS_MASK     CSI_CR2_AFS_MASK
27209 #define CSI_CSICR2_AFS_SHIFT     CSI_CR2_AFS_SHIFT
27210 #define CSI_CSICR2_AFS(x)     CSI_CR2_AFS(x)
27211 #define CSI_CSICR2_DRM_MASK     CSI_CR2_DRM_MASK
27212 #define CSI_CSICR2_DRM_SHIFT     CSI_CR2_DRM_SHIFT
27213 #define CSI_CSICR2_DRM(x)     CSI_CR2_DRM(x)
27214 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK     CSI_CR2_DMA_BURST_TYPE_SFF_MASK
27215 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
27216 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)     CSI_CR2_DMA_BURST_TYPE_SFF(x)
27217 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK     CSI_CR2_DMA_BURST_TYPE_RFF_MASK
27218 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
27219 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)     CSI_CR2_DMA_BURST_TYPE_RFF(x)
27220 #define CSI_CSICR3_ECC_AUTO_EN_MASK     CSI_CR3_ECC_AUTO_EN_MASK
27221 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT     CSI_CR3_ECC_AUTO_EN_SHIFT
27222 #define CSI_CSICR3_ECC_AUTO_EN(x)     CSI_CR3_ECC_AUTO_EN(x)
27223 #define CSI_CSICR3_ECC_INT_EN_MASK     CSI_CR3_ECC_INT_EN_MASK
27224 #define CSI_CSICR3_ECC_INT_EN_SHIFT     CSI_CR3_ECC_INT_EN_SHIFT
27225 #define CSI_CSICR3_ECC_INT_EN(x)     CSI_CR3_ECC_INT_EN(x)
27226 #define CSI_CSICR3_ZERO_PACK_EN_MASK     CSI_CR3_ZERO_PACK_EN_MASK
27227 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT     CSI_CR3_ZERO_PACK_EN_SHIFT
27228 #define CSI_CSICR3_ZERO_PACK_EN(x)     CSI_CR3_ZERO_PACK_EN(x)
27229 #define CSI_CSICR3_SENSOR_16BITS_MASK     CSI_CR3_SENSOR_16BITS_MASK
27230 #define CSI_CSICR3_SENSOR_16BITS_SHIFT     CSI_CR3_SENSOR_16BITS_SHIFT
27231 #define CSI_CSICR3_SENSOR_16BITS(x)     CSI_CR3_SENSOR_16BITS(x)
27232 #define CSI_CSICR3_RxFF_LEVEL_MASK     CSI_CR3_RxFF_LEVEL_MASK
27233 #define CSI_CSICR3_RxFF_LEVEL_SHIFT     CSI_CR3_RxFF_LEVEL_SHIFT
27234 #define CSI_CSICR3_RxFF_LEVEL(x)     CSI_CR3_RxFF_LEVEL(x)
27235 #define CSI_CSICR3_HRESP_ERR_EN_MASK     CSI_CR3_HRESP_ERR_EN_MASK
27236 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT     CSI_CR3_HRESP_ERR_EN_SHIFT
27237 #define CSI_CSICR3_HRESP_ERR_EN(x)     CSI_CR3_HRESP_ERR_EN(x)
27238 #define CSI_CSICR3_STATFF_LEVEL_MASK     CSI_CR3_STATFF_LEVEL_MASK
27239 #define CSI_CSICR3_STATFF_LEVEL_SHIFT     CSI_CR3_STATFF_LEVEL_SHIFT
27240 #define CSI_CSICR3_STATFF_LEVEL(x)     CSI_CR3_STATFF_LEVEL(x)
27241 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK     CSI_CR3_DMA_REQ_EN_SFF_MASK
27242 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT     CSI_CR3_DMA_REQ_EN_SFF_SHIFT
27243 #define CSI_CSICR3_DMA_REQ_EN_SFF(x)     CSI_CR3_DMA_REQ_EN_SFF(x)
27244 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK     CSI_CR3_DMA_REQ_EN_RFF_MASK
27245 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT     CSI_CR3_DMA_REQ_EN_RFF_SHIFT
27246 #define CSI_CSICR3_DMA_REQ_EN_RFF(x)     CSI_CR3_DMA_REQ_EN_RFF(x)
27247 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK     CSI_CR3_DMA_REFLASH_SFF_MASK
27248 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT     CSI_CR3_DMA_REFLASH_SFF_SHIFT
27249 #define CSI_CSICR3_DMA_REFLASH_SFF(x)     CSI_CR3_DMA_REFLASH_SFF(x)
27250 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK     CSI_CR3_DMA_REFLASH_RFF_MASK
27251 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT     CSI_CR3_DMA_REFLASH_RFF_SHIFT
27252 #define CSI_CSICR3_DMA_REFLASH_RFF(x)     CSI_CR3_DMA_REFLASH_RFF(x)
27253 #define CSI_CSICR3_FRMCNT_RST_MASK     CSI_CR3_FRMCNT_RST_MASK
27254 #define CSI_CSICR3_FRMCNT_RST_SHIFT     CSI_CR3_FRMCNT_RST_SHIFT
27255 #define CSI_CSICR3_FRMCNT_RST(x)     CSI_CR3_FRMCNT_RST(x)
27256 #define CSI_CSICR3_FRMCNT_MASK     CSI_CR3_FRMCNT_MASK
27257 #define CSI_CSICR3_FRMCNT_SHIFT     CSI_CR3_FRMCNT_SHIFT
27258 #define CSI_CSICR3_FRMCNT(x)     CSI_CR3_FRMCNT(x)
27259 #define CSI_CSISTATFIFO_STAT_MASK     CSI_STATFIFO_STAT_MASK
27260 #define CSI_CSISTATFIFO_STAT_SHIFT     CSI_STATFIFO_STAT_SHIFT
27261 #define CSI_CSISTATFIFO_STAT(x)     CSI_STATFIFO_STAT(x)
27262 #define CSI_CSIRFIFO_IMAGE_MASK     CSI_RFIFO_IMAGE_MASK
27263 #define CSI_CSIRFIFO_IMAGE_SHIFT     CSI_RFIFO_IMAGE_SHIFT
27264 #define CSI_CSIRFIFO_IMAGE(x)     CSI_RFIFO_IMAGE(x)
27265 #define CSI_CSIRXCNT_RXCNT_MASK     CSI_RXCNT_RXCNT_MASK
27266 #define CSI_CSIRXCNT_RXCNT_SHIFT     CSI_RXCNT_RXCNT_SHIFT
27267 #define CSI_CSIRXCNT_RXCNT(x)     CSI_RXCNT_RXCNT(x)
27268 #define CSI_CSISR_DRDY_MASK     CSI_SR_DRDY_MASK
27269 #define CSI_CSISR_DRDY_SHIFT     CSI_SR_DRDY_SHIFT
27270 #define CSI_CSISR_DRDY(x)     CSI_SR_DRDY(x)
27271 #define CSI_CSISR_ECC_INT_MASK     CSI_SR_ECC_INT_MASK
27272 #define CSI_CSISR_ECC_INT_SHIFT     CSI_SR_ECC_INT_SHIFT
27273 #define CSI_CSISR_ECC_INT(x)     CSI_SR_ECC_INT(x)
27274 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK     CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
27275 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT     CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
27276 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x)     CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
27277 #define CSI_CSISR_HRESP_ERR_INT_MASK     CSI_SR_HRESP_ERR_INT_MASK
27278 #define CSI_CSISR_HRESP_ERR_INT_SHIFT     CSI_SR_HRESP_ERR_INT_SHIFT
27279 #define CSI_CSISR_HRESP_ERR_INT(x)     CSI_SR_HRESP_ERR_INT(x)
27280 #define CSI_CSISR_COF_INT_MASK     CSI_SR_COF_INT_MASK
27281 #define CSI_CSISR_COF_INT_SHIFT     CSI_SR_COF_INT_SHIFT
27282 #define CSI_CSISR_COF_INT(x)     CSI_SR_COF_INT(x)
27283 #define CSI_CSISR_F1_INT_MASK     CSI_SR_F1_INT_MASK
27284 #define CSI_CSISR_F1_INT_SHIFT     CSI_SR_F1_INT_SHIFT
27285 #define CSI_CSISR_F1_INT(x)     CSI_SR_F1_INT(x)
27286 #define CSI_CSISR_F2_INT_MASK     CSI_SR_F2_INT_MASK
27287 #define CSI_CSISR_F2_INT_SHIFT     CSI_SR_F2_INT_SHIFT
27288 #define CSI_CSISR_F2_INT(x)     CSI_SR_F2_INT(x)
27289 #define CSI_CSISR_SOF_INT_MASK     CSI_SR_SOF_INT_MASK
27290 #define CSI_CSISR_SOF_INT_SHIFT     CSI_SR_SOF_INT_SHIFT
27291 #define CSI_CSISR_SOF_INT(x)     CSI_SR_SOF_INT(x)
27292 #define CSI_CSISR_EOF_INT_MASK     CSI_SR_EOF_INT_MASK
27293 #define CSI_CSISR_EOF_INT_SHIFT     CSI_SR_EOF_INT_SHIFT
27294 #define CSI_CSISR_EOF_INT(x)     CSI_SR_EOF_INT(x)
27295 #define CSI_CSISR_RxFF_INT_MASK     CSI_SR_RxFF_INT_MASK
27296 #define CSI_CSISR_RxFF_INT_SHIFT     CSI_SR_RxFF_INT_SHIFT
27297 #define CSI_CSISR_RxFF_INT(x)     CSI_SR_RxFF_INT(x)
27298 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK     CSI_SR_DMA_TSF_DONE_FB1_MASK
27299 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT     CSI_SR_DMA_TSF_DONE_FB1_SHIFT
27300 #define CSI_CSISR_DMA_TSF_DONE_FB1(x)     CSI_SR_DMA_TSF_DONE_FB1(x)
27301 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK     CSI_SR_DMA_TSF_DONE_FB2_MASK
27302 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT     CSI_SR_DMA_TSF_DONE_FB2_SHIFT
27303 #define CSI_CSISR_DMA_TSF_DONE_FB2(x)     CSI_SR_DMA_TSF_DONE_FB2(x)
27304 #define CSI_CSISR_STATFF_INT_MASK     CSI_SR_STATFF_INT_MASK
27305 #define CSI_CSISR_STATFF_INT_SHIFT     CSI_SR_STATFF_INT_SHIFT
27306 #define CSI_CSISR_STATFF_INT(x)     CSI_SR_STATFF_INT(x)
27307 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK     CSI_SR_DMA_TSF_DONE_SFF_MASK
27308 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT     CSI_SR_DMA_TSF_DONE_SFF_SHIFT
27309 #define CSI_CSISR_DMA_TSF_DONE_SFF(x)     CSI_SR_DMA_TSF_DONE_SFF(x)
27310 #define CSI_CSISR_RF_OR_INT_MASK     CSI_SR_RF_OR_INT_MASK
27311 #define CSI_CSISR_RF_OR_INT_SHIFT     CSI_SR_RF_OR_INT_SHIFT
27312 #define CSI_CSISR_RF_OR_INT(x)     CSI_SR_RF_OR_INT(x)
27313 #define CSI_CSISR_SF_OR_INT_MASK     CSI_SR_SF_OR_INT_MASK
27314 #define CSI_CSISR_SF_OR_INT_SHIFT     CSI_SR_SF_OR_INT_SHIFT
27315 #define CSI_CSISR_SF_OR_INT(x)     CSI_SR_SF_OR_INT(x)
27316 #define CSI_CSISR_DMA_FIELD1_DONE_MASK     CSI_SR_DMA_FIELD1_DONE_MASK
27317 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT     CSI_SR_DMA_FIELD1_DONE_SHIFT
27318 #define CSI_CSISR_DMA_FIELD1_DONE(x)     CSI_SR_DMA_FIELD1_DONE(x)
27319 #define CSI_CSISR_DMA_FIELD0_DONE_MASK     CSI_SR_DMA_FIELD0_DONE_MASK
27320 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT     CSI_SR_DMA_FIELD0_DONE_SHIFT
27321 #define CSI_CSISR_DMA_FIELD0_DONE(x)     CSI_SR_DMA_FIELD0_DONE(x)
27322 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK     CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
27323 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT     CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
27324 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x)     CSI_SR_BASEADDR_CHHANGE_ERROR(x)
27325 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
27326 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
27327 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x)     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
27328 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
27329 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
27330 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
27331 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK     CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
27332 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT     CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
27333 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)     CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
27334 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK     CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
27335 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT     CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
27336 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)     CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
27337 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK     CSI_FBUF_PARA_FBUF_STRIDE_MASK
27338 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT     CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
27339 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)     CSI_FBUF_PARA_FBUF_STRIDE(x)
27340 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK     CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
27341 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT     CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
27342 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)     CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
27343 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK     CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
27344 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT     CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
27345 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)     CSI_IMAG_PARA_IMAGE_HEIGHT(x)
27346 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK     CSI_IMAG_PARA_IMAGE_WIDTH_MASK
27347 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT     CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
27348 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)     CSI_IMAG_PARA_IMAGE_WIDTH(x)
27349 #define CSI_CSICR18_NTSC_EN_MASK     CSI_CR18_NTSC_EN_MASK
27350 #define CSI_CSICR18_NTSC_EN_SHIFT     CSI_CR18_NTSC_EN_SHIFT
27351 #define CSI_CSICR18_NTSC_EN(x)     CSI_CR18_NTSC_EN(x)
27352 #define CSI_CSICR18_TVDECODER_IN_EN_MASK     CSI_CR18_TVDECODER_IN_EN_MASK
27353 #define CSI_CSICR18_TVDECODER_IN_EN_SHIFT     CSI_CR18_TVDECODER_IN_EN_SHIFT
27354 #define CSI_CSICR18_TVDECODER_IN_EN(x)     CSI_CR18_TVDECODER_IN_EN(x)
27355 #define CSI_CSICR18_DEINTERLACE_EN_MASK     CSI_CR18_DEINTERLACE_EN_MASK
27356 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT     CSI_CR18_DEINTERLACE_EN_SHIFT
27357 #define CSI_CSICR18_DEINTERLACE_EN(x)     CSI_CR18_DEINTERLACE_EN(x)
27358 #define CSI_CSICR18_PARALLEL24_EN_MASK     CSI_CR18_PARALLEL24_EN_MASK
27359 #define CSI_CSICR18_PARALLEL24_EN_SHIFT     CSI_CR18_PARALLEL24_EN_SHIFT
27360 #define CSI_CSICR18_PARALLEL24_EN(x)     CSI_CR18_PARALLEL24_EN(x)
27361 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK     CSI_CR18_BASEADDR_SWITCH_EN_MASK
27362 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
27363 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x)     CSI_CR18_BASEADDR_SWITCH_EN(x)
27364 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     CSI_CR18_BASEADDR_SWITCH_SEL_MASK
27365 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT     CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
27366 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x)     CSI_CR18_BASEADDR_SWITCH_SEL(x)
27367 #define CSI_CSICR18_FIELD0_DONE_IE_MASK     CSI_CR18_FIELD0_DONE_IE_MASK
27368 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT     CSI_CR18_FIELD0_DONE_IE_SHIFT
27369 #define CSI_CSICR18_FIELD0_DONE_IE(x)     CSI_CR18_FIELD0_DONE_IE(x)
27370 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK     CSI_CR18_DMA_FIELD1_DONE_IE_MASK
27371 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
27372 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x)     CSI_CR18_DMA_FIELD1_DONE_IE(x)
27373 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK     CSI_CR18_LAST_DMA_REQ_SEL_MASK
27374 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT     CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
27375 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x)     CSI_CR18_LAST_DMA_REQ_SEL(x)
27376 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
27377 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
27378 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)     CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
27379 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK     CSI_CR18_RGB888A_FORMAT_SEL_MASK
27380 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
27381 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x)     CSI_CR18_RGB888A_FORMAT_SEL(x)
27382 #define CSI_CSICR18_AHB_HPROT_MASK     CSI_CR18_AHB_HPROT_MASK
27383 #define CSI_CSICR18_AHB_HPROT_SHIFT     CSI_CR18_AHB_HPROT_SHIFT
27384 #define CSI_CSICR18_AHB_HPROT(x)     CSI_CR18_AHB_HPROT(x)
27385 #define CSI_CSICR18_MASK_OPTION_MASK     CSI_CR18_MASK_OPTION_MASK
27386 #define CSI_CSICR18_MASK_OPTION_SHIFT     CSI_CR18_MASK_OPTION_SHIFT
27387 #define CSI_CSICR18_MASK_OPTION(x)     CSI_CR18_MASK_OPTION(x)
27388 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK     CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
27389 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT     CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
27390 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x)     CSI_CR18_MIPI_DOUBLE_CMPNT(x)
27391 #define CSI_CSICR18_MIPI_YU_SWAP_MASK     CSI_CR18_MIPI_YU_SWAP_MASK
27392 #define CSI_CSICR18_MIPI_YU_SWAP_SHIFT     CSI_CR18_MIPI_YU_SWAP_SHIFT
27393 #define CSI_CSICR18_MIPI_YU_SWAP(x)     CSI_CR18_MIPI_YU_SWAP(x)
27394 #define CSI_CSICR18_DATA_FROM_MIPI_MASK     CSI_CR18_DATA_FROM_MIPI_MASK
27395 #define CSI_CSICR18_DATA_FROM_MIPI_SHIFT     CSI_CR18_DATA_FROM_MIPI_SHIFT
27396 #define CSI_CSICR18_DATA_FROM_MIPI(x)     CSI_CR18_DATA_FROM_MIPI(x)
27397 #define CSI_CSICR18_LINE_STRIDE_EN_MASK     CSI_CR18_LINE_STRIDE_EN_MASK
27398 #define CSI_CSICR18_LINE_STRIDE_EN_SHIFT     CSI_CR18_LINE_STRIDE_EN_SHIFT
27399 #define CSI_CSICR18_LINE_STRIDE_EN(x)     CSI_CR18_LINE_STRIDE_EN(x)
27400 #define CSI_CSICR18_MIPI_DATA_FORMAT_MASK     CSI_CR18_MIPI_DATA_FORMAT_MASK
27401 #define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT     CSI_CR18_MIPI_DATA_FORMAT_SHIFT
27402 #define CSI_CSICR18_MIPI_DATA_FORMAT(x)     CSI_CR18_MIPI_DATA_FORMAT(x)
27403 #define CSI_CSICR18_CSI_ENABLE_MASK     CSI_CR18_CSI_ENABLE_MASK
27404 #define CSI_CSICR18_CSI_ENABLE_SHIFT     CSI_CR18_CSI_ENABLE_SHIFT
27405 #define CSI_CSICR18_CSI_ENABLE(x)     CSI_CR18_CSI_ENABLE(x)
27406 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
27407 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
27408 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
27409 #define CSI_CSICR20_THRESHOLD_MASK     CSI_CR20_THRESHOLD_MASK
27410 #define CSI_CSICR20_THRESHOLD_SHIFT     CSI_CR20_THRESHOLD_SHIFT
27411 #define CSI_CSICR20_THRESHOLD(x)     CSI_CR20_THRESHOLD(x)
27412 #define CSI_CSICR20_BINARY_EN_MASK     CSI_CR20_BINARY_EN_MASK
27413 #define CSI_CSICR20_BINARY_EN_SHIFT     CSI_CR20_BINARY_EN_SHIFT
27414 #define CSI_CSICR20_BINARY_EN(x)     CSI_CR20_BINARY_EN(x)
27415 #define CSI_CSICR20_QR_DATA_FORMAT_MASK     CSI_CR20_QR_DATA_FORMAT_MASK
27416 #define CSI_CSICR20_QR_DATA_FORMAT_SHIFT     CSI_CR20_QR_DATA_FORMAT_SHIFT
27417 #define CSI_CSICR20_QR_DATA_FORMAT(x)     CSI_CR20_QR_DATA_FORMAT(x)
27418 #define CSI_CSICR20_BIG_END_MASK     CSI_CR20_BIG_END_MASK
27419 #define CSI_CSICR20_BIG_END_SHIFT     CSI_CR20_BIG_END_SHIFT
27420 #define CSI_CSICR20_BIG_END(x)     CSI_CR20_BIG_END(x)
27421 #define CSI_CSICR20_10BIT_NEW_EN_MASK     CSI_CR20_10BIT_NEW_EN_MASK
27422 #define CSI_CSICR20_10BIT_NEW_EN_SHIFT     CSI_CR20_10BIT_NEW_EN_SHIFT
27423 #define CSI_CSICR20_10BIT_NEW_EN(x)     CSI_CR20_10BIT_NEW_EN(x)
27424 #define CSI_CSICR20_HISTOGRAM_EN_MASK     CSI_CR20_HISTOGRAM_EN_MASK
27425 #define CSI_CSICR20_HISTOGRAM_EN_SHIFT     CSI_CR20_HISTOGRAM_EN_SHIFT
27426 #define CSI_CSICR20_HISTOGRAM_EN(x)     CSI_CR20_HISTOGRAM_EN(x)
27427 #define CSI_CSICR20_QRCODE_EN_MASK     CSI_CR20_QRCODE_EN_MASK
27428 #define CSI_CSICR20_QRCODE_EN_SHIFT     CSI_CR20_QRCODE_EN_SHIFT
27429 #define CSI_CSICR20_QRCODE_EN(x)     CSI_CR20_QRCODE_EN(x)
27430 #define CSI_CSICR21_PIXEL_COUNTERS_MASK     CSI_CR21_PIXEL_COUNTERS_MASK
27431 #define CSI_CSICR21_PIXEL_COUNTERS_SHIFT     CSI_CR21_PIXEL_COUNTERS_SHIFT
27432 #define CSI_CSICR21_PIXEL_COUNTERS(x)     CSI_CR21_PIXEL_COUNTERS(x)
27433 #define CSI_CSICR22_PIXEL_COUNTERS_MASK     CSI_CR22_PIXEL_COUNTERS_MASK
27434 #define CSI_CSICR22_PIXEL_COUNTERS_SHIFT     CSI_CR22_PIXEL_COUNTERS_SHIFT
27435 #define CSI_CSICR22_PIXEL_COUNTERS(x)     CSI_CR22_PIXEL_COUNTERS(x)
27436 #define CSI_CSICR23_PIXEL_COUNTERS_MASK     CSI_CR23_PIXEL_COUNTERS_MASK
27437 #define CSI_CSICR23_PIXEL_COUNTERS_SHIFT     CSI_CR23_PIXEL_COUNTERS_SHIFT
27438 #define CSI_CSICR23_PIXEL_COUNTERS(x)     CSI_CR23_PIXEL_COUNTERS(x)
27439 #define CSI_CSICR24_PIXEL_COUNTERS_MASK     CSI_CR24_PIXEL_COUNTERS_MASK
27440 #define CSI_CSICR24_PIXEL_COUNTERS_SHIFT     CSI_CR24_PIXEL_COUNTERS_SHIFT
27441 #define CSI_CSICR24_PIXEL_COUNTERS(x)     CSI_CR24_PIXEL_COUNTERS(x)
27442 #define CSI_CSICR25_PIXEL_COUNTERS_MASK     CSI_CR25_PIXEL_COUNTERS_MASK
27443 #define CSI_CSICR25_PIXEL_COUNTERS_SHIFT     CSI_CR25_PIXEL_COUNTERS_SHIFT
27444 #define CSI_CSICR25_PIXEL_COUNTERS(x)     CSI_CR25_PIXEL_COUNTERS(x)
27445 #define CSI_CSICR26_PIXEL_COUNTERS_MASK     CSI_CR26_PIXEL_COUNTERS_MASK
27446 #define CSI_CSICR26_PIXEL_COUNTERS_SHIFT     CSI_CR26_PIXEL_COUNTERS_SHIFT
27447 #define CSI_CSICR26_PIXEL_COUNTERS(x)     CSI_CR26_PIXEL_COUNTERS(x)
27448 #define CSI_CSICR27_PIXEL_COUNTERS_MASK     CSI_CR27_PIXEL_COUNTERS_MASK
27449 #define CSI_CSICR27_PIXEL_COUNTERS_SHIFT     CSI_CR27_PIXEL_COUNTERS_SHIFT
27450 #define CSI_CSICR27_PIXEL_COUNTERS(x)     CSI_CR27_PIXEL_COUNTERS(x)
27451 #define CSI_CSICR28_PIXEL_COUNTERS_MASK     CSI_CR28_PIXEL_COUNTERS_MASK
27452 #define CSI_CSICR28_PIXEL_COUNTERS_SHIFT     CSI_CR28_PIXEL_COUNTERS_SHIFT
27453 #define CSI_CSICR28_PIXEL_COUNTERS(x)     CSI_CR28_PIXEL_COUNTERS(x)
27454 #define CSI_CSICR29_PIXEL_COUNTERS_MASK     CSI_CR29_PIXEL_COUNTERS_MASK
27455 #define CSI_CSICR29_PIXEL_COUNTERS_SHIFT     CSI_CR29_PIXEL_COUNTERS_SHIFT
27456 #define CSI_CSICR29_PIXEL_COUNTERS(x)     CSI_CR29_PIXEL_COUNTERS(x)
27457 #define CSI_CSICR30_PIXEL_COUNTERS_MASK     CSI_CR30_PIXEL_COUNTERS_MASK
27458 #define CSI_CSICR30_PIXEL_COUNTERS_SHIFT     CSI_CR30_PIXEL_COUNTERS_SHIFT
27459 #define CSI_CSICR30_PIXEL_COUNTERS(x)     CSI_CR30_PIXEL_COUNTERS(x)
27460 #define CSI_CSICR31_PIXEL_COUNTERS_MASK     CSI_CR31_PIXEL_COUNTERS_MASK
27461 #define CSI_CSICR31_PIXEL_COUNTERS_SHIFT     CSI_CR31_PIXEL_COUNTERS_SHIFT
27462 #define CSI_CSICR31_PIXEL_COUNTERS(x)     CSI_CR31_PIXEL_COUNTERS(x)
27463 #define CSI_CSICR32_PIXEL_COUNTERS_MASK     CSI_CR32_PIXEL_COUNTERS_MASK
27464 #define CSI_CSICR32_PIXEL_COUNTERS_SHIFT     CSI_CR32_PIXEL_COUNTERS_SHIFT
27465 #define CSI_CSICR32_PIXEL_COUNTERS(x)     CSI_CR32_PIXEL_COUNTERS(x)
27466 #define CSI_CSICR33_PIXEL_COUNTERS_MASK     CSI_CR33_PIXEL_COUNTERS_MASK
27467 #define CSI_CSICR33_PIXEL_COUNTERS_SHIFT     CSI_CR33_PIXEL_COUNTERS_SHIFT
27468 #define CSI_CSICR33_PIXEL_COUNTERS(x)     CSI_CR33_PIXEL_COUNTERS(x)
27469 #define CSI_CSICR34_PIXEL_COUNTERS_MASK     CSI_CR34_PIXEL_COUNTERS_MASK
27470 #define CSI_CSICR34_PIXEL_COUNTERS_SHIFT     CSI_CR34_PIXEL_COUNTERS_SHIFT
27471 #define CSI_CSICR34_PIXEL_COUNTERS(x)     CSI_CR34_PIXEL_COUNTERS(x)
27472 #define CSI_CSICR35_PIXEL_COUNTERS_MASK     CSI_CR35_PIXEL_COUNTERS_MASK
27473 #define CSI_CSICR35_PIXEL_COUNTERS_SHIFT     CSI_CR35_PIXEL_COUNTERS_SHIFT
27474 #define CSI_CSICR35_PIXEL_COUNTERS(x)     CSI_CR35_PIXEL_COUNTERS(x)
27475 #define CSI_CSICR36_PIXEL_COUNTERS_MASK     CSI_CR36_PIXEL_COUNTERS_MASK
27476 #define CSI_CSICR36_PIXEL_COUNTERS_SHIFT     CSI_CR36_PIXEL_COUNTERS_SHIFT
27477 #define CSI_CSICR36_PIXEL_COUNTERS(x)     CSI_CR36_PIXEL_COUNTERS(x)
27478 #define CSI_CSICR37_PIXEL_COUNTERS_MASK     CSI_CR37_PIXEL_COUNTERS_MASK
27479 #define CSI_CSICR37_PIXEL_COUNTERS_SHIFT     CSI_CR37_PIXEL_COUNTERS_SHIFT
27480 #define CSI_CSICR37_PIXEL_COUNTERS(x)     CSI_CR37_PIXEL_COUNTERS(x)
27481 #define CSI_CSICR38_PIXEL_COUNTERS_MASK     CSI_CR38_PIXEL_COUNTERS_MASK
27482 #define CSI_CSICR38_PIXEL_COUNTERS_SHIFT     CSI_CR38_PIXEL_COUNTERS_SHIFT
27483 #define CSI_CSICR38_PIXEL_COUNTERS(x)     CSI_CR38_PIXEL_COUNTERS(x)
27484 #define CSI_CSICR39_PIXEL_COUNTERS_MASK     CSI_CR39_PIXEL_COUNTERS_MASK
27485 #define CSI_CSICR39_PIXEL_COUNTERS_SHIFT     CSI_CR39_PIXEL_COUNTERS_SHIFT
27486 #define CSI_CSICR39_PIXEL_COUNTERS(x)     CSI_CR39_PIXEL_COUNTERS(x)
27487 #define CSI_CSICR40_PIXEL_COUNTERS_MASK     CSI_CR40_PIXEL_COUNTERS_MASK
27488 #define CSI_CSICR40_PIXEL_COUNTERS_SHIFT     CSI_CR40_PIXEL_COUNTERS_SHIFT
27489 #define CSI_CSICR40_PIXEL_COUNTERS(x)     CSI_CR40_PIXEL_COUNTERS(x)
27490 #define CSI_CSICR41_PIXEL_COUNTERS_MASK     CSI_CR41_PIXEL_COUNTERS_MASK
27491 #define CSI_CSICR41_PIXEL_COUNTERS_SHIFT     CSI_CR41_PIXEL_COUNTERS_SHIFT
27492 #define CSI_CSICR41_PIXEL_COUNTERS(x)     CSI_CR41_PIXEL_COUNTERS(x)
27493 #define CSI_CSICR42_PIXEL_COUNTERS_MASK     CSI_CR42_PIXEL_COUNTERS_MASK
27494 #define CSI_CSICR42_PIXEL_COUNTERS_SHIFT     CSI_CR42_PIXEL_COUNTERS_SHIFT
27495 #define CSI_CSICR42_PIXEL_COUNTERS(x)     CSI_CR42_PIXEL_COUNTERS(x)
27496 #define CSI_CSICR43_PIXEL_COUNTERS_MASK     CSI_CR43_PIXEL_COUNTERS_MASK
27497 #define CSI_CSICR43_PIXEL_COUNTERS_SHIFT     CSI_CR43_PIXEL_COUNTERS_SHIFT
27498 #define CSI_CSICR43_PIXEL_COUNTERS(x)     CSI_CR43_PIXEL_COUNTERS(x)
27499 #define CSI_CSICR44_PIXEL_COUNTERS_MASK     CSI_CR44_PIXEL_COUNTERS_MASK
27500 #define CSI_CSICR44_PIXEL_COUNTERS_SHIFT     CSI_CR44_PIXEL_COUNTERS_SHIFT
27501 #define CSI_CSICR44_PIXEL_COUNTERS(x)     CSI_CR44_PIXEL_COUNTERS(x)
27502 #define CSI_CSICR45_PIXEL_COUNTERS_MASK     CSI_CR45_PIXEL_COUNTERS_MASK
27503 #define CSI_CSICR45_PIXEL_COUNTERS_SHIFT     CSI_CR45_PIXEL_COUNTERS_SHIFT
27504 #define CSI_CSICR45_PIXEL_COUNTERS(x)     CSI_CR45_PIXEL_COUNTERS(x)
27505 #define CSI_CSICR46_PIXEL_COUNTERS_MASK     CSI_CR46_PIXEL_COUNTERS_MASK
27506 #define CSI_CSICR46_PIXEL_COUNTERS_SHIFT     CSI_CR46_PIXEL_COUNTERS_SHIFT
27507 #define CSI_CSICR46_PIXEL_COUNTERS(x)     CSI_CR46_PIXEL_COUNTERS(x)
27508 #define CSI_CSICR47_PIXEL_COUNTERS_MASK     CSI_CR47_PIXEL_COUNTERS_MASK
27509 #define CSI_CSICR47_PIXEL_COUNTERS_SHIFT     CSI_CR47_PIXEL_COUNTERS_SHIFT
27510 #define CSI_CSICR47_PIXEL_COUNTERS(x)     CSI_CR47_PIXEL_COUNTERS(x)
27511 #define CSI_CSICR48_PIXEL_COUNTERS_MASK     CSI_CR48_PIXEL_COUNTERS_MASK
27512 #define CSI_CSICR48_PIXEL_COUNTERS_SHIFT     CSI_CR48_PIXEL_COUNTERS_SHIFT
27513 #define CSI_CSICR48_PIXEL_COUNTERS(x)     CSI_CR48_PIXEL_COUNTERS(x)
27514 #define CSI_CSICR49_PIXEL_COUNTERS_MASK     CSI_CR49_PIXEL_COUNTERS_MASK
27515 #define CSI_CSICR49_PIXEL_COUNTERS_SHIFT     CSI_CR49_PIXEL_COUNTERS_SHIFT
27516 #define CSI_CSICR49_PIXEL_COUNTERS(x)     CSI_CR49_PIXEL_COUNTERS(x)
27517 #define CSI_CSICR50_PIXEL_COUNTERS_MASK     CSI_CR50_PIXEL_COUNTERS_MASK
27518 #define CSI_CSICR50_PIXEL_COUNTERS_SHIFT     CSI_CR50_PIXEL_COUNTERS_SHIFT
27519 #define CSI_CSICR50_PIXEL_COUNTERS(x)     CSI_CR50_PIXEL_COUNTERS(x)
27520 #define CSI_CSICR51_PIXEL_COUNTERS_MASK     CSI_CR51_PIXEL_COUNTERS_MASK
27521 #define CSI_CSICR51_PIXEL_COUNTERS_SHIFT     CSI_CR51_PIXEL_COUNTERS_SHIFT
27522 #define CSI_CSICR51_PIXEL_COUNTERS(x)     CSI_CR51_PIXEL_COUNTERS(x)
27523 #define CSI_CSICR52_PIXEL_COUNTERS_MASK     CSI_CR52_PIXEL_COUNTERS_MASK
27524 #define CSI_CSICR52_PIXEL_COUNTERS_SHIFT     CSI_CR52_PIXEL_COUNTERS_SHIFT
27525 #define CSI_CSICR52_PIXEL_COUNTERS(x)     CSI_CR52_PIXEL_COUNTERS(x)
27526 #define CSI_CSICR53_PIXEL_COUNTERS_MASK     CSI_CR53_PIXEL_COUNTERS_MASK
27527 #define CSI_CSICR53_PIXEL_COUNTERS_SHIFT     CSI_CR53_PIXEL_COUNTERS_SHIFT
27528 #define CSI_CSICR53_PIXEL_COUNTERS(x)     CSI_CR53_PIXEL_COUNTERS(x)
27529 #define CSI_CSICR54_PIXEL_COUNTERS_MASK     CSI_CR54_PIXEL_COUNTERS_MASK
27530 #define CSI_CSICR54_PIXEL_COUNTERS_SHIFT     CSI_CR54_PIXEL_COUNTERS_SHIFT
27531 #define CSI_CSICR54_PIXEL_COUNTERS(x)     CSI_CR54_PIXEL_COUNTERS(x)
27532 #define CSI_CSICR55_PIXEL_COUNTERS_MASK     CSI_CR55_PIXEL_COUNTERS_MASK
27533 #define CSI_CSICR55_PIXEL_COUNTERS_SHIFT     CSI_CR55_PIXEL_COUNTERS_SHIFT
27534 #define CSI_CSICR55_PIXEL_COUNTERS(x)     CSI_CR55_PIXEL_COUNTERS(x)
27535 #define CSI_CSICR56_PIXEL_COUNTERS_MASK     CSI_CR56_PIXEL_COUNTERS_MASK
27536 #define CSI_CSICR56_PIXEL_COUNTERS_SHIFT     CSI_CR56_PIXEL_COUNTERS_SHIFT
27537 #define CSI_CSICR56_PIXEL_COUNTERS(x)     CSI_CR56_PIXEL_COUNTERS(x)
27538 #define CSI_CSICR57_PIXEL_COUNTERS_MASK     CSI_CR57_PIXEL_COUNTERS_MASK
27539 #define CSI_CSICR57_PIXEL_COUNTERS_SHIFT     CSI_CR57_PIXEL_COUNTERS_SHIFT
27540 #define CSI_CSICR57_PIXEL_COUNTERS(x)     CSI_CR57_PIXEL_COUNTERS(x)
27541 #define CSI_CSICR58_PIXEL_COUNTERS_MASK     CSI_CR58_PIXEL_COUNTERS_MASK
27542 #define CSI_CSICR58_PIXEL_COUNTERS_SHIFT     CSI_CR58_PIXEL_COUNTERS_SHIFT
27543 #define CSI_CSICR58_PIXEL_COUNTERS(x)     CSI_CR58_PIXEL_COUNTERS(x)
27544 #define CSI_CSICR59_PIXEL_COUNTERS_MASK     CSI_CR59_PIXEL_COUNTERS_MASK
27545 #define CSI_CSICR59_PIXEL_COUNTERS_SHIFT     CSI_CR59_PIXEL_COUNTERS_SHIFT
27546 #define CSI_CSICR59_PIXEL_COUNTERS(x)     CSI_CR59_PIXEL_COUNTERS(x)
27547 #define CSI_CSICR60_PIXEL_COUNTERS_MASK     CSI_CR60_PIXEL_COUNTERS_MASK
27548 #define CSI_CSICR60_PIXEL_COUNTERS_SHIFT     CSI_CR60_PIXEL_COUNTERS_SHIFT
27549 #define CSI_CSICR60_PIXEL_COUNTERS(x)     CSI_CR60_PIXEL_COUNTERS(x)
27550 #define CSI_CSICR61_PIXEL_COUNTERS_MASK     CSI_CR61_PIXEL_COUNTERS_MASK
27551 #define CSI_CSICR61_PIXEL_COUNTERS_SHIFT     CSI_CR61_PIXEL_COUNTERS_SHIFT
27552 #define CSI_CSICR61_PIXEL_COUNTERS(x)     CSI_CR61_PIXEL_COUNTERS(x)
27553 #define CSI_CSICR62_PIXEL_COUNTERS_MASK     CSI_CR62_PIXEL_COUNTERS_MASK
27554 #define CSI_CSICR62_PIXEL_COUNTERS_SHIFT     CSI_CR62_PIXEL_COUNTERS_SHIFT
27555 #define CSI_CSICR62_PIXEL_COUNTERS(x)     CSI_CR62_PIXEL_COUNTERS(x)
27556 #define CSI_CSICR63_PIXEL_COUNTERS_MASK     CSI_CR63_PIXEL_COUNTERS_MASK
27557 #define CSI_CSICR63_PIXEL_COUNTERS_SHIFT     CSI_CR63_PIXEL_COUNTERS_SHIFT
27558 #define CSI_CSICR63_PIXEL_COUNTERS(x)     CSI_CR63_PIXEL_COUNTERS(x)
27559 #define CSI_CSICR64_PIXEL_COUNTERS_MASK     CSI_CR64_PIXEL_COUNTERS_MASK
27560 #define CSI_CSICR64_PIXEL_COUNTERS_SHIFT     CSI_CR64_PIXEL_COUNTERS_SHIFT
27561 #define CSI_CSICR64_PIXEL_COUNTERS(x)     CSI_CR64_PIXEL_COUNTERS(x)
27562 #define CSI_CSICR65_PIXEL_COUNTERS_MASK     CSI_CR65_PIXEL_COUNTERS_MASK
27563 #define CSI_CSICR65_PIXEL_COUNTERS_SHIFT     CSI_CR65_PIXEL_COUNTERS_SHIFT
27564 #define CSI_CSICR65_PIXEL_COUNTERS(x)     CSI_CR65_PIXEL_COUNTERS(x)
27565 #define CSI_CSICR66_PIXEL_COUNTERS_MASK     CSI_CR66_PIXEL_COUNTERS_MASK
27566 #define CSI_CSICR66_PIXEL_COUNTERS_SHIFT     CSI_CR66_PIXEL_COUNTERS_SHIFT
27567 #define CSI_CSICR66_PIXEL_COUNTERS(x)     CSI_CR66_PIXEL_COUNTERS(x)
27568 #define CSI_CSICR67_PIXEL_COUNTERS_MASK     CSI_CR67_PIXEL_COUNTERS_MASK
27569 #define CSI_CSICR67_PIXEL_COUNTERS_SHIFT     CSI_CR67_PIXEL_COUNTERS_SHIFT
27570 #define CSI_CSICR67_PIXEL_COUNTERS(x)     CSI_CR67_PIXEL_COUNTERS(x)
27571 #define CSI_CSICR68_PIXEL_COUNTERS_MASK     CSI_CR68_PIXEL_COUNTERS_MASK
27572 #define CSI_CSICR68_PIXEL_COUNTERS_SHIFT     CSI_CR68_PIXEL_COUNTERS_SHIFT
27573 #define CSI_CSICR68_PIXEL_COUNTERS(x)     CSI_CR68_PIXEL_COUNTERS(x)
27574 #define CSI_CSICR69_PIXEL_COUNTERS_MASK     CSI_CR69_PIXEL_COUNTERS_MASK
27575 #define CSI_CSICR69_PIXEL_COUNTERS_SHIFT     CSI_CR69_PIXEL_COUNTERS_SHIFT
27576 #define CSI_CSICR69_PIXEL_COUNTERS(x)     CSI_CR69_PIXEL_COUNTERS(x)
27577 #define CSI_CSICR70_PIXEL_COUNTERS_MASK     CSI_CR70_PIXEL_COUNTERS_MASK
27578 #define CSI_CSICR70_PIXEL_COUNTERS_SHIFT     CSI_CR70_PIXEL_COUNTERS_SHIFT
27579 #define CSI_CSICR70_PIXEL_COUNTERS(x)     CSI_CR70_PIXEL_COUNTERS(x)
27580 #define CSI_CSICR71_PIXEL_COUNTERS_MASK     CSI_CR71_PIXEL_COUNTERS_MASK
27581 #define CSI_CSICR71_PIXEL_COUNTERS_SHIFT     CSI_CR71_PIXEL_COUNTERS_SHIFT
27582 #define CSI_CSICR71_PIXEL_COUNTERS(x)     CSI_CR71_PIXEL_COUNTERS(x)
27583 #define CSI_CSICR72_PIXEL_COUNTERS_MASK     CSI_CR72_PIXEL_COUNTERS_MASK
27584 #define CSI_CSICR72_PIXEL_COUNTERS_SHIFT     CSI_CR72_PIXEL_COUNTERS_SHIFT
27585 #define CSI_CSICR72_PIXEL_COUNTERS(x)     CSI_CR72_PIXEL_COUNTERS(x)
27586 #define CSI_CSICR73_PIXEL_COUNTERS_MASK     CSI_CR73_PIXEL_COUNTERS_MASK
27587 #define CSI_CSICR73_PIXEL_COUNTERS_SHIFT     CSI_CR73_PIXEL_COUNTERS_SHIFT
27588 #define CSI_CSICR73_PIXEL_COUNTERS(x)     CSI_CR73_PIXEL_COUNTERS(x)
27589 #define CSI_CSICR74_PIXEL_COUNTERS_MASK     CSI_CR74_PIXEL_COUNTERS_MASK
27590 #define CSI_CSICR74_PIXEL_COUNTERS_SHIFT     CSI_CR74_PIXEL_COUNTERS_SHIFT
27591 #define CSI_CSICR74_PIXEL_COUNTERS(x)     CSI_CR74_PIXEL_COUNTERS(x)
27592 #define CSI_CSICR75_PIXEL_COUNTERS_MASK     CSI_CR75_PIXEL_COUNTERS_MASK
27593 #define CSI_CSICR75_PIXEL_COUNTERS_SHIFT     CSI_CR75_PIXEL_COUNTERS_SHIFT
27594 #define CSI_CSICR75_PIXEL_COUNTERS(x)     CSI_CR75_PIXEL_COUNTERS(x)
27595 #define CSI_CSICR76_PIXEL_COUNTERS_MASK     CSI_CR76_PIXEL_COUNTERS_MASK
27596 #define CSI_CSICR76_PIXEL_COUNTERS_SHIFT     CSI_CR76_PIXEL_COUNTERS_SHIFT
27597 #define CSI_CSICR76_PIXEL_COUNTERS(x)     CSI_CR76_PIXEL_COUNTERS(x)
27598 #define CSI_CSICR77_PIXEL_COUNTERS_MASK     CSI_CR77_PIXEL_COUNTERS_MASK
27599 #define CSI_CSICR77_PIXEL_COUNTERS_SHIFT     CSI_CR77_PIXEL_COUNTERS_SHIFT
27600 #define CSI_CSICR77_PIXEL_COUNTERS(x)     CSI_CR77_PIXEL_COUNTERS(x)
27601 #define CSI_CSICR78_PIXEL_COUNTERS_MASK     CSI_CR78_PIXEL_COUNTERS_MASK
27602 #define CSI_CSICR78_PIXEL_COUNTERS_SHIFT     CSI_CR78_PIXEL_COUNTERS_SHIFT
27603 #define CSI_CSICR78_PIXEL_COUNTERS(x)     CSI_CR78_PIXEL_COUNTERS(x)
27604 #define CSI_CSICR79_PIXEL_COUNTERS_MASK     CSI_CR79_PIXEL_COUNTERS_MASK
27605 #define CSI_CSICR79_PIXEL_COUNTERS_SHIFT     CSI_CR79_PIXEL_COUNTERS_SHIFT
27606 #define CSI_CSICR79_PIXEL_COUNTERS(x)     CSI_CR79_PIXEL_COUNTERS(x)
27607 #define CSI_CSICR80_PIXEL_COUNTERS_MASK     CSI_CR80_PIXEL_COUNTERS_MASK
27608 #define CSI_CSICR80_PIXEL_COUNTERS_SHIFT     CSI_CR80_PIXEL_COUNTERS_SHIFT
27609 #define CSI_CSICR80_PIXEL_COUNTERS(x)     CSI_CR80_PIXEL_COUNTERS(x)
27610 #define CSI_CSICR81_PIXEL_COUNTERS_MASK     CSI_CR81_PIXEL_COUNTERS_MASK
27611 #define CSI_CSICR81_PIXEL_COUNTERS_SHIFT     CSI_CR81_PIXEL_COUNTERS_SHIFT
27612 #define CSI_CSICR81_PIXEL_COUNTERS(x)     CSI_CR81_PIXEL_COUNTERS(x)
27613 #define CSI_CSICR82_PIXEL_COUNTERS_MASK     CSI_CR82_PIXEL_COUNTERS_MASK
27614 #define CSI_CSICR82_PIXEL_COUNTERS_SHIFT     CSI_CR82_PIXEL_COUNTERS_SHIFT
27615 #define CSI_CSICR82_PIXEL_COUNTERS(x)     CSI_CR82_PIXEL_COUNTERS(x)
27616 #define CSI_CSICR83_PIXEL_COUNTERS_MASK     CSI_CR83_PIXEL_COUNTERS_MASK
27617 #define CSI_CSICR83_PIXEL_COUNTERS_SHIFT     CSI_CR83_PIXEL_COUNTERS_SHIFT
27618 #define CSI_CSICR83_PIXEL_COUNTERS(x)     CSI_CR83_PIXEL_COUNTERS(x)
27619 #define CSI_CSICR84_PIXEL_COUNTERS_MASK     CSI_CR84_PIXEL_COUNTERS_MASK
27620 #define CSI_CSICR84_PIXEL_COUNTERS_SHIFT     CSI_CR84_PIXEL_COUNTERS_SHIFT
27621 #define CSI_CSICR84_PIXEL_COUNTERS(x)     CSI_CR84_PIXEL_COUNTERS(x)
27622 #define CSI_CSICR85_PIXEL_COUNTERS_MASK     CSI_CR85_PIXEL_COUNTERS_MASK
27623 #define CSI_CSICR85_PIXEL_COUNTERS_SHIFT     CSI_CR85_PIXEL_COUNTERS_SHIFT
27624 #define CSI_CSICR85_PIXEL_COUNTERS(x)     CSI_CR85_PIXEL_COUNTERS(x)
27625 #define CSI_CSICR86_PIXEL_COUNTERS_MASK     CSI_CR86_PIXEL_COUNTERS_MASK
27626 #define CSI_CSICR86_PIXEL_COUNTERS_SHIFT     CSI_CR86_PIXEL_COUNTERS_SHIFT
27627 #define CSI_CSICR86_PIXEL_COUNTERS(x)     CSI_CR86_PIXEL_COUNTERS(x)
27628 #define CSI_CSICR87_PIXEL_COUNTERS_MASK     CSI_CR87_PIXEL_COUNTERS_MASK
27629 #define CSI_CSICR87_PIXEL_COUNTERS_SHIFT     CSI_CR87_PIXEL_COUNTERS_SHIFT
27630 #define CSI_CSICR87_PIXEL_COUNTERS(x)     CSI_CR87_PIXEL_COUNTERS(x)
27631 #define CSI_CSICR88_PIXEL_COUNTERS_MASK     CSI_CR88_PIXEL_COUNTERS_MASK
27632 #define CSI_CSICR88_PIXEL_COUNTERS_SHIFT     CSI_CR88_PIXEL_COUNTERS_SHIFT
27633 #define CSI_CSICR88_PIXEL_COUNTERS(x)     CSI_CR88_PIXEL_COUNTERS(x)
27634 #define CSI_CSICR89_PIXEL_COUNTERS_MASK     CSI_CR89_PIXEL_COUNTERS_MASK
27635 #define CSI_CSICR89_PIXEL_COUNTERS_SHIFT     CSI_CR89_PIXEL_COUNTERS_SHIFT
27636 #define CSI_CSICR89_PIXEL_COUNTERS(x)     CSI_CR89_PIXEL_COUNTERS(x)
27637 #define CSI_CSICR90_PIXEL_COUNTERS_MASK     CSI_CR90_PIXEL_COUNTERS_MASK
27638 #define CSI_CSICR90_PIXEL_COUNTERS_SHIFT     CSI_CR90_PIXEL_COUNTERS_SHIFT
27639 #define CSI_CSICR90_PIXEL_COUNTERS(x)     CSI_CR90_PIXEL_COUNTERS(x)
27640 #define CSI_CSICR91_PIXEL_COUNTERS_MASK     CSI_CR91_PIXEL_COUNTERS_MASK
27641 #define CSI_CSICR91_PIXEL_COUNTERS_SHIFT     CSI_CR91_PIXEL_COUNTERS_SHIFT
27642 #define CSI_CSICR91_PIXEL_COUNTERS(x)     CSI_CR91_PIXEL_COUNTERS(x)
27643 #define CSI_CSICR92_PIXEL_COUNTERS_MASK     CSI_CR92_PIXEL_COUNTERS_MASK
27644 #define CSI_CSICR92_PIXEL_COUNTERS_SHIFT     CSI_CR92_PIXEL_COUNTERS_SHIFT
27645 #define CSI_CSICR92_PIXEL_COUNTERS(x)     CSI_CR92_PIXEL_COUNTERS(x)
27646 #define CSI_CSICR93_PIXEL_COUNTERS_MASK     CSI_CR93_PIXEL_COUNTERS_MASK
27647 #define CSI_CSICR93_PIXEL_COUNTERS_SHIFT     CSI_CR93_PIXEL_COUNTERS_SHIFT
27648 #define CSI_CSICR93_PIXEL_COUNTERS(x)     CSI_CR93_PIXEL_COUNTERS(x)
27649 #define CSI_CSICR94_PIXEL_COUNTERS_MASK     CSI_CR94_PIXEL_COUNTERS_MASK
27650 #define CSI_CSICR94_PIXEL_COUNTERS_SHIFT     CSI_CR94_PIXEL_COUNTERS_SHIFT
27651 #define CSI_CSICR94_PIXEL_COUNTERS(x)     CSI_CR94_PIXEL_COUNTERS(x)
27652 #define CSI_CSICR95_PIXEL_COUNTERS_MASK     CSI_CR95_PIXEL_COUNTERS_MASK
27653 #define CSI_CSICR95_PIXEL_COUNTERS_SHIFT     CSI_CR95_PIXEL_COUNTERS_SHIFT
27654 #define CSI_CSICR95_PIXEL_COUNTERS(x)     CSI_CR95_PIXEL_COUNTERS(x)
27655 #define CSI_CSICR96_PIXEL_COUNTERS_MASK     CSI_CR96_PIXEL_COUNTERS_MASK
27656 #define CSI_CSICR96_PIXEL_COUNTERS_SHIFT     CSI_CR96_PIXEL_COUNTERS_SHIFT
27657 #define CSI_CSICR96_PIXEL_COUNTERS(x)     CSI_CR96_PIXEL_COUNTERS(x)
27658 #define CSI_CSICR97_PIXEL_COUNTERS_MASK     CSI_CR97_PIXEL_COUNTERS_MASK
27659 #define CSI_CSICR97_PIXEL_COUNTERS_SHIFT     CSI_CR97_PIXEL_COUNTERS_SHIFT
27660 #define CSI_CSICR97_PIXEL_COUNTERS(x)     CSI_CR97_PIXEL_COUNTERS(x)
27661 #define CSI_CSICR98_PIXEL_COUNTERS_MASK     CSI_CR98_PIXEL_COUNTERS_MASK
27662 #define CSI_CSICR98_PIXEL_COUNTERS_SHIFT     CSI_CR98_PIXEL_COUNTERS_SHIFT
27663 #define CSI_CSICR98_PIXEL_COUNTERS(x)     CSI_CR98_PIXEL_COUNTERS(x)
27664 #define CSI_CSICR99_PIXEL_COUNTERS_MASK     CSI_CR99_PIXEL_COUNTERS_MASK
27665 #define CSI_CSICR99_PIXEL_COUNTERS_SHIFT     CSI_CR99_PIXEL_COUNTERS_SHIFT
27666 #define CSI_CSICR99_PIXEL_COUNTERS(x)     CSI_CR99_PIXEL_COUNTERS(x)
27667 #define CSI_CSICR100_PIXEL_COUNTERS_MASK     CSI_CR100_PIXEL_COUNTERS_MASK
27668 #define CSI_CSICR100_PIXEL_COUNTERS_SHIFT     CSI_CR100_PIXEL_COUNTERS_SHIFT
27669 #define CSI_CSICR100_PIXEL_COUNTERS(x)     CSI_CR100_PIXEL_COUNTERS(x)
27670 #define CSI_CSICR101_PIXEL_COUNTERS_MASK     CSI_CR101_PIXEL_COUNTERS_MASK
27671 #define CSI_CSICR101_PIXEL_COUNTERS_SHIFT     CSI_CR101_PIXEL_COUNTERS_SHIFT
27672 #define CSI_CSICR101_PIXEL_COUNTERS(x)     CSI_CR101_PIXEL_COUNTERS(x)
27673 #define CSI_CSICR102_PIXEL_COUNTERS_MASK     CSI_CR102_PIXEL_COUNTERS_MASK
27674 #define CSI_CSICR102_PIXEL_COUNTERS_SHIFT     CSI_CR102_PIXEL_COUNTERS_SHIFT
27675 #define CSI_CSICR102_PIXEL_COUNTERS(x)     CSI_CR102_PIXEL_COUNTERS(x)
27676 #define CSI_CSICR103_PIXEL_COUNTERS_MASK     CSI_CR103_PIXEL_COUNTERS_MASK
27677 #define CSI_CSICR103_PIXEL_COUNTERS_SHIFT     CSI_CR103_PIXEL_COUNTERS_SHIFT
27678 #define CSI_CSICR103_PIXEL_COUNTERS(x)     CSI_CR103_PIXEL_COUNTERS(x)
27679 #define CSI_CSICR104_PIXEL_COUNTERS_MASK     CSI_CR104_PIXEL_COUNTERS_MASK
27680 #define CSI_CSICR104_PIXEL_COUNTERS_SHIFT     CSI_CR104_PIXEL_COUNTERS_SHIFT
27681 #define CSI_CSICR104_PIXEL_COUNTERS(x)     CSI_CR104_PIXEL_COUNTERS(x)
27682 #define CSI_CSICR105_PIXEL_COUNTERS_MASK     CSI_CR105_PIXEL_COUNTERS_MASK
27683 #define CSI_CSICR105_PIXEL_COUNTERS_SHIFT     CSI_CR105_PIXEL_COUNTERS_SHIFT
27684 #define CSI_CSICR105_PIXEL_COUNTERS(x)     CSI_CR105_PIXEL_COUNTERS(x)
27685 #define CSI_CSICR106_PIXEL_COUNTERS_MASK     CSI_CR106_PIXEL_COUNTERS_MASK
27686 #define CSI_CSICR106_PIXEL_COUNTERS_SHIFT     CSI_CR106_PIXEL_COUNTERS_SHIFT
27687 #define CSI_CSICR106_PIXEL_COUNTERS(x)     CSI_CR106_PIXEL_COUNTERS(x)
27688 #define CSI_CSICR107_PIXEL_COUNTERS_MASK     CSI_CR107_PIXEL_COUNTERS_MASK
27689 #define CSI_CSICR107_PIXEL_COUNTERS_SHIFT     CSI_CR107_PIXEL_COUNTERS_SHIFT
27690 #define CSI_CSICR107_PIXEL_COUNTERS(x)     CSI_CR107_PIXEL_COUNTERS(x)
27691 #define CSI_CSICR108_PIXEL_COUNTERS_MASK     CSI_CR108_PIXEL_COUNTERS_MASK
27692 #define CSI_CSICR108_PIXEL_COUNTERS_SHIFT     CSI_CR108_PIXEL_COUNTERS_SHIFT
27693 #define CSI_CSICR108_PIXEL_COUNTERS(x)     CSI_CR108_PIXEL_COUNTERS(x)
27694 #define CSI_CSICR109_PIXEL_COUNTERS_MASK     CSI_CR109_PIXEL_COUNTERS_MASK
27695 #define CSI_CSICR109_PIXEL_COUNTERS_SHIFT     CSI_CR109_PIXEL_COUNTERS_SHIFT
27696 #define CSI_CSICR109_PIXEL_COUNTERS(x)     CSI_CR109_PIXEL_COUNTERS(x)
27697 #define CSI_CSICR110_PIXEL_COUNTERS_MASK     CSI_CR110_PIXEL_COUNTERS_MASK
27698 #define CSI_CSICR110_PIXEL_COUNTERS_SHIFT     CSI_CR110_PIXEL_COUNTERS_SHIFT
27699 #define CSI_CSICR110_PIXEL_COUNTERS(x)     CSI_CR110_PIXEL_COUNTERS(x)
27700 #define CSI_CSICR111_PIXEL_COUNTERS_MASK     CSI_CR111_PIXEL_COUNTERS_MASK
27701 #define CSI_CSICR111_PIXEL_COUNTERS_SHIFT     CSI_CR111_PIXEL_COUNTERS_SHIFT
27702 #define CSI_CSICR111_PIXEL_COUNTERS(x)     CSI_CR111_PIXEL_COUNTERS(x)
27703 #define CSI_CSICR112_PIXEL_COUNTERS_MASK     CSI_CR112_PIXEL_COUNTERS_MASK
27704 #define CSI_CSICR112_PIXEL_COUNTERS_SHIFT     CSI_CR112_PIXEL_COUNTERS_SHIFT
27705 #define CSI_CSICR112_PIXEL_COUNTERS(x)     CSI_CR112_PIXEL_COUNTERS(x)
27706 #define CSI_CSICR113_PIXEL_COUNTERS_MASK     CSI_CR113_PIXEL_COUNTERS_MASK
27707 #define CSI_CSICR113_PIXEL_COUNTERS_SHIFT     CSI_CR113_PIXEL_COUNTERS_SHIFT
27708 #define CSI_CSICR113_PIXEL_COUNTERS(x)     CSI_CR113_PIXEL_COUNTERS(x)
27709 #define CSI_CSICR114_PIXEL_COUNTERS_MASK     CSI_CR114_PIXEL_COUNTERS_MASK
27710 #define CSI_CSICR114_PIXEL_COUNTERS_SHIFT     CSI_CR114_PIXEL_COUNTERS_SHIFT
27711 #define CSI_CSICR114_PIXEL_COUNTERS(x)     CSI_CR114_PIXEL_COUNTERS(x)
27712 #define CSI_CSICR115_PIXEL_COUNTERS_MASK     CSI_CR115_PIXEL_COUNTERS_MASK
27713 #define CSI_CSICR115_PIXEL_COUNTERS_SHIFT     CSI_CR115_PIXEL_COUNTERS_SHIFT
27714 #define CSI_CSICR115_PIXEL_COUNTERS(x)     CSI_CR115_PIXEL_COUNTERS(x)
27715 #define CSI_CSICR116_PIXEL_COUNTERS_MASK     CSI_CR116_PIXEL_COUNTERS_MASK
27716 #define CSI_CSICR116_PIXEL_COUNTERS_SHIFT     CSI_CR116_PIXEL_COUNTERS_SHIFT
27717 #define CSI_CSICR116_PIXEL_COUNTERS(x)     CSI_CR116_PIXEL_COUNTERS(x)
27718 #define CSI_CSICR117_PIXEL_COUNTERS_MASK     CSI_CR117_PIXEL_COUNTERS_MASK
27719 #define CSI_CSICR117_PIXEL_COUNTERS_SHIFT     CSI_CR117_PIXEL_COUNTERS_SHIFT
27720 #define CSI_CSICR117_PIXEL_COUNTERS(x)     CSI_CR117_PIXEL_COUNTERS(x)
27721 #define CSI_CSICR118_PIXEL_COUNTERS_MASK     CSI_CR118_PIXEL_COUNTERS_MASK
27722 #define CSI_CSICR118_PIXEL_COUNTERS_SHIFT     CSI_CR118_PIXEL_COUNTERS_SHIFT
27723 #define CSI_CSICR118_PIXEL_COUNTERS(x)     CSI_CR118_PIXEL_COUNTERS(x)
27724 #define CSI_CSICR119_PIXEL_COUNTERS_MASK     CSI_CR119_PIXEL_COUNTERS_MASK
27725 #define CSI_CSICR119_PIXEL_COUNTERS_SHIFT     CSI_CR119_PIXEL_COUNTERS_SHIFT
27726 #define CSI_CSICR119_PIXEL_COUNTERS(x)     CSI_CR119_PIXEL_COUNTERS(x)
27727 #define CSI_CSICR120_PIXEL_COUNTERS_MASK     CSI_CR120_PIXEL_COUNTERS_MASK
27728 #define CSI_CSICR120_PIXEL_COUNTERS_SHIFT     CSI_CR120_PIXEL_COUNTERS_SHIFT
27729 #define CSI_CSICR120_PIXEL_COUNTERS(x)     CSI_CR120_PIXEL_COUNTERS(x)
27730 #define CSI_CSICR121_PIXEL_COUNTERS_MASK     CSI_CR121_PIXEL_COUNTERS_MASK
27731 #define CSI_CSICR121_PIXEL_COUNTERS_SHIFT     CSI_CR121_PIXEL_COUNTERS_SHIFT
27732 #define CSI_CSICR121_PIXEL_COUNTERS(x)     CSI_CR121_PIXEL_COUNTERS(x)
27733 #define CSI_CSICR122_PIXEL_COUNTERS_MASK     CSI_CR122_PIXEL_COUNTERS_MASK
27734 #define CSI_CSICR122_PIXEL_COUNTERS_SHIFT     CSI_CR122_PIXEL_COUNTERS_SHIFT
27735 #define CSI_CSICR122_PIXEL_COUNTERS(x)     CSI_CR122_PIXEL_COUNTERS(x)
27736 #define CSI_CSICR123_PIXEL_COUNTERS_MASK     CSI_CR123_PIXEL_COUNTERS_MASK
27737 #define CSI_CSICR123_PIXEL_COUNTERS_SHIFT     CSI_CR123_PIXEL_COUNTERS_SHIFT
27738 #define CSI_CSICR123_PIXEL_COUNTERS(x)     CSI_CR123_PIXEL_COUNTERS(x)
27739 #define CSI_CSICR124_PIXEL_COUNTERS_MASK     CSI_CR124_PIXEL_COUNTERS_MASK
27740 #define CSI_CSICR124_PIXEL_COUNTERS_SHIFT     CSI_CR124_PIXEL_COUNTERS_SHIFT
27741 #define CSI_CSICR124_PIXEL_COUNTERS(x)     CSI_CR124_PIXEL_COUNTERS(x)
27742 #define CSI_CSICR125_PIXEL_COUNTERS_MASK     CSI_CR125_PIXEL_COUNTERS_MASK
27743 #define CSI_CSICR125_PIXEL_COUNTERS_SHIFT     CSI_CR125_PIXEL_COUNTERS_SHIFT
27744 #define CSI_CSICR125_PIXEL_COUNTERS(x)     CSI_CR125_PIXEL_COUNTERS(x)
27745 #define CSI_CSICR126_PIXEL_COUNTERS_MASK     CSI_CR126_PIXEL_COUNTERS_MASK
27746 #define CSI_CSICR126_PIXEL_COUNTERS_SHIFT     CSI_CR126_PIXEL_COUNTERS_SHIFT
27747 #define CSI_CSICR126_PIXEL_COUNTERS(x)     CSI_CR126_PIXEL_COUNTERS(x)
27748 #define CSI_CSICR127_PIXEL_COUNTERS_MASK     CSI_CR127_PIXEL_COUNTERS_MASK
27749 #define CSI_CSICR127_PIXEL_COUNTERS_SHIFT     CSI_CR127_PIXEL_COUNTERS_SHIFT
27750 #define CSI_CSICR127_PIXEL_COUNTERS(x)     CSI_CR127_PIXEL_COUNTERS(x)
27751 #define CSI_CSICR128_PIXEL_COUNTERS_MASK     CSI_CR128_PIXEL_COUNTERS_MASK
27752 #define CSI_CSICR128_PIXEL_COUNTERS_SHIFT     CSI_CR128_PIXEL_COUNTERS_SHIFT
27753 #define CSI_CSICR128_PIXEL_COUNTERS(x)     CSI_CR128_PIXEL_COUNTERS(x)
27754 #define CSI_CSICR129_PIXEL_COUNTERS_MASK     CSI_CR129_PIXEL_COUNTERS_MASK
27755 #define CSI_CSICR129_PIXEL_COUNTERS_SHIFT     CSI_CR129_PIXEL_COUNTERS_SHIFT
27756 #define CSI_CSICR129_PIXEL_COUNTERS(x)     CSI_CR129_PIXEL_COUNTERS(x)
27757 #define CSI_CSICR130_PIXEL_COUNTERS_MASK     CSI_CR130_PIXEL_COUNTERS_MASK
27758 #define CSI_CSICR130_PIXEL_COUNTERS_SHIFT     CSI_CR130_PIXEL_COUNTERS_SHIFT
27759 #define CSI_CSICR130_PIXEL_COUNTERS(x)     CSI_CR130_PIXEL_COUNTERS(x)
27760 #define CSI_CSICR131_PIXEL_COUNTERS_MASK     CSI_CR131_PIXEL_COUNTERS_MASK
27761 #define CSI_CSICR131_PIXEL_COUNTERS_SHIFT     CSI_CR131_PIXEL_COUNTERS_SHIFT
27762 #define CSI_CSICR131_PIXEL_COUNTERS(x)     CSI_CR131_PIXEL_COUNTERS(x)
27763 #define CSI_CSICR132_PIXEL_COUNTERS_MASK     CSI_CR132_PIXEL_COUNTERS_MASK
27764 #define CSI_CSICR132_PIXEL_COUNTERS_SHIFT     CSI_CR132_PIXEL_COUNTERS_SHIFT
27765 #define CSI_CSICR132_PIXEL_COUNTERS(x)     CSI_CR132_PIXEL_COUNTERS(x)
27766 #define CSI_CSICR133_PIXEL_COUNTERS_MASK     CSI_CR133_PIXEL_COUNTERS_MASK
27767 #define CSI_CSICR133_PIXEL_COUNTERS_SHIFT     CSI_CR133_PIXEL_COUNTERS_SHIFT
27768 #define CSI_CSICR133_PIXEL_COUNTERS(x)     CSI_CR133_PIXEL_COUNTERS(x)
27769 #define CSI_CSICR134_PIXEL_COUNTERS_MASK     CSI_CR134_PIXEL_COUNTERS_MASK
27770 #define CSI_CSICR134_PIXEL_COUNTERS_SHIFT     CSI_CR134_PIXEL_COUNTERS_SHIFT
27771 #define CSI_CSICR134_PIXEL_COUNTERS(x)     CSI_CR134_PIXEL_COUNTERS(x)
27772 #define CSI_CSICR135_PIXEL_COUNTERS_MASK     CSI_CR135_PIXEL_COUNTERS_MASK
27773 #define CSI_CSICR135_PIXEL_COUNTERS_SHIFT     CSI_CR135_PIXEL_COUNTERS_SHIFT
27774 #define CSI_CSICR135_PIXEL_COUNTERS(x)     CSI_CR135_PIXEL_COUNTERS(x)
27775 #define CSI_CSICR136_PIXEL_COUNTERS_MASK     CSI_CR136_PIXEL_COUNTERS_MASK
27776 #define CSI_CSICR136_PIXEL_COUNTERS_SHIFT     CSI_CR136_PIXEL_COUNTERS_SHIFT
27777 #define CSI_CSICR136_PIXEL_COUNTERS(x)     CSI_CR136_PIXEL_COUNTERS(x)
27778 #define CSI_CSICR137_PIXEL_COUNTERS_MASK     CSI_CR137_PIXEL_COUNTERS_MASK
27779 #define CSI_CSICR137_PIXEL_COUNTERS_SHIFT     CSI_CR137_PIXEL_COUNTERS_SHIFT
27780 #define CSI_CSICR137_PIXEL_COUNTERS(x)     CSI_CR137_PIXEL_COUNTERS(x)
27781 #define CSI_CSICR138_PIXEL_COUNTERS_MASK     CSI_CR138_PIXEL_COUNTERS_MASK
27782 #define CSI_CSICR138_PIXEL_COUNTERS_SHIFT     CSI_CR138_PIXEL_COUNTERS_SHIFT
27783 #define CSI_CSICR138_PIXEL_COUNTERS(x)     CSI_CR138_PIXEL_COUNTERS(x)
27784 #define CSI_CSICR139_PIXEL_COUNTERS_MASK     CSI_CR139_PIXEL_COUNTERS_MASK
27785 #define CSI_CSICR139_PIXEL_COUNTERS_SHIFT     CSI_CR139_PIXEL_COUNTERS_SHIFT
27786 #define CSI_CSICR139_PIXEL_COUNTERS(x)     CSI_CR139_PIXEL_COUNTERS(x)
27787 #define CSI_CSICR140_PIXEL_COUNTERS_MASK     CSI_CR140_PIXEL_COUNTERS_MASK
27788 #define CSI_CSICR140_PIXEL_COUNTERS_SHIFT     CSI_CR140_PIXEL_COUNTERS_SHIFT
27789 #define CSI_CSICR140_PIXEL_COUNTERS(x)     CSI_CR140_PIXEL_COUNTERS(x)
27790 #define CSI_CSICR141_PIXEL_COUNTERS_MASK     CSI_CR141_PIXEL_COUNTERS_MASK
27791 #define CSI_CSICR141_PIXEL_COUNTERS_SHIFT     CSI_CR141_PIXEL_COUNTERS_SHIFT
27792 #define CSI_CSICR141_PIXEL_COUNTERS(x)     CSI_CR141_PIXEL_COUNTERS(x)
27793 #define CSI_CSICR142_PIXEL_COUNTERS_MASK     CSI_CR142_PIXEL_COUNTERS_MASK
27794 #define CSI_CSICR142_PIXEL_COUNTERS_SHIFT     CSI_CR142_PIXEL_COUNTERS_SHIFT
27795 #define CSI_CSICR142_PIXEL_COUNTERS(x)     CSI_CR142_PIXEL_COUNTERS(x)
27796 #define CSI_CSICR143_PIXEL_COUNTERS_MASK     CSI_CR143_PIXEL_COUNTERS_MASK
27797 #define CSI_CSICR143_PIXEL_COUNTERS_SHIFT     CSI_CR143_PIXEL_COUNTERS_SHIFT
27798 #define CSI_CSICR143_PIXEL_COUNTERS(x)     CSI_CR143_PIXEL_COUNTERS(x)
27799 #define CSI_CSICR144_PIXEL_COUNTERS_MASK     CSI_CR144_PIXEL_COUNTERS_MASK
27800 #define CSI_CSICR144_PIXEL_COUNTERS_SHIFT     CSI_CR144_PIXEL_COUNTERS_SHIFT
27801 #define CSI_CSICR144_PIXEL_COUNTERS(x)     CSI_CR144_PIXEL_COUNTERS(x)
27802 #define CSI_CSICR145_PIXEL_COUNTERS_MASK     CSI_CR145_PIXEL_COUNTERS_MASK
27803 #define CSI_CSICR145_PIXEL_COUNTERS_SHIFT     CSI_CR145_PIXEL_COUNTERS_SHIFT
27804 #define CSI_CSICR145_PIXEL_COUNTERS(x)     CSI_CR145_PIXEL_COUNTERS(x)
27805 #define CSI_CSICR146_PIXEL_COUNTERS_MASK     CSI_CR146_PIXEL_COUNTERS_MASK
27806 #define CSI_CSICR146_PIXEL_COUNTERS_SHIFT     CSI_CR146_PIXEL_COUNTERS_SHIFT
27807 #define CSI_CSICR146_PIXEL_COUNTERS(x)     CSI_CR146_PIXEL_COUNTERS(x)
27808 #define CSI_CSICR147_PIXEL_COUNTERS_MASK     CSI_CR147_PIXEL_COUNTERS_MASK
27809 #define CSI_CSICR147_PIXEL_COUNTERS_SHIFT     CSI_CR147_PIXEL_COUNTERS_SHIFT
27810 #define CSI_CSICR147_PIXEL_COUNTERS(x)     CSI_CR147_PIXEL_COUNTERS(x)
27811 #define CSI_CSICR148_PIXEL_COUNTERS_MASK     CSI_CR148_PIXEL_COUNTERS_MASK
27812 #define CSI_CSICR148_PIXEL_COUNTERS_SHIFT     CSI_CR148_PIXEL_COUNTERS_SHIFT
27813 #define CSI_CSICR148_PIXEL_COUNTERS(x)     CSI_CR148_PIXEL_COUNTERS(x)
27814 #define CSI_CSICR149_PIXEL_COUNTERS_MASK     CSI_CR149_PIXEL_COUNTERS_MASK
27815 #define CSI_CSICR149_PIXEL_COUNTERS_SHIFT     CSI_CR149_PIXEL_COUNTERS_SHIFT
27816 #define CSI_CSICR149_PIXEL_COUNTERS(x)     CSI_CR149_PIXEL_COUNTERS(x)
27817 #define CSI_CSICR150_PIXEL_COUNTERS_MASK     CSI_CR150_PIXEL_COUNTERS_MASK
27818 #define CSI_CSICR150_PIXEL_COUNTERS_SHIFT     CSI_CR150_PIXEL_COUNTERS_SHIFT
27819 #define CSI_CSICR150_PIXEL_COUNTERS(x)     CSI_CR150_PIXEL_COUNTERS(x)
27820 #define CSI_CSICR151_PIXEL_COUNTERS_MASK     CSI_CR151_PIXEL_COUNTERS_MASK
27821 #define CSI_CSICR151_PIXEL_COUNTERS_SHIFT     CSI_CR151_PIXEL_COUNTERS_SHIFT
27822 #define CSI_CSICR151_PIXEL_COUNTERS(x)     CSI_CR151_PIXEL_COUNTERS(x)
27823 #define CSI_CSICR152_PIXEL_COUNTERS_MASK     CSI_CR152_PIXEL_COUNTERS_MASK
27824 #define CSI_CSICR152_PIXEL_COUNTERS_SHIFT     CSI_CR152_PIXEL_COUNTERS_SHIFT
27825 #define CSI_CSICR152_PIXEL_COUNTERS(x)     CSI_CR152_PIXEL_COUNTERS(x)
27826 #define CSI_CSICR153_PIXEL_COUNTERS_MASK     CSI_CR153_PIXEL_COUNTERS_MASK
27827 #define CSI_CSICR153_PIXEL_COUNTERS_SHIFT     CSI_CR153_PIXEL_COUNTERS_SHIFT
27828 #define CSI_CSICR153_PIXEL_COUNTERS(x)     CSI_CR153_PIXEL_COUNTERS(x)
27829 #define CSI_CSICR154_PIXEL_COUNTERS_MASK     CSI_CR154_PIXEL_COUNTERS_MASK
27830 #define CSI_CSICR154_PIXEL_COUNTERS_SHIFT     CSI_CR154_PIXEL_COUNTERS_SHIFT
27831 #define CSI_CSICR154_PIXEL_COUNTERS(x)     CSI_CR154_PIXEL_COUNTERS(x)
27832 #define CSI_CSICR155_PIXEL_COUNTERS_MASK     CSI_CR155_PIXEL_COUNTERS_MASK
27833 #define CSI_CSICR155_PIXEL_COUNTERS_SHIFT     CSI_CR155_PIXEL_COUNTERS_SHIFT
27834 #define CSI_CSICR155_PIXEL_COUNTERS(x)     CSI_CR155_PIXEL_COUNTERS(x)
27835 #define CSI_CSICR156_PIXEL_COUNTERS_MASK     CSI_CR156_PIXEL_COUNTERS_MASK
27836 #define CSI_CSICR156_PIXEL_COUNTERS_SHIFT     CSI_CR156_PIXEL_COUNTERS_SHIFT
27837 #define CSI_CSICR156_PIXEL_COUNTERS(x)     CSI_CR156_PIXEL_COUNTERS(x)
27838 #define CSI_CSICR157_PIXEL_COUNTERS_MASK     CSI_CR157_PIXEL_COUNTERS_MASK
27839 #define CSI_CSICR157_PIXEL_COUNTERS_SHIFT     CSI_CR157_PIXEL_COUNTERS_SHIFT
27840 #define CSI_CSICR157_PIXEL_COUNTERS(x)     CSI_CR157_PIXEL_COUNTERS(x)
27841 #define CSI_CSICR158_PIXEL_COUNTERS_MASK     CSI_CR158_PIXEL_COUNTERS_MASK
27842 #define CSI_CSICR158_PIXEL_COUNTERS_SHIFT     CSI_CR158_PIXEL_COUNTERS_SHIFT
27843 #define CSI_CSICR158_PIXEL_COUNTERS(x)     CSI_CR158_PIXEL_COUNTERS(x)
27844 #define CSI_CSICR159_PIXEL_COUNTERS_MASK     CSI_CR159_PIXEL_COUNTERS_MASK
27845 #define CSI_CSICR159_PIXEL_COUNTERS_SHIFT     CSI_CR159_PIXEL_COUNTERS_SHIFT
27846 #define CSI_CSICR159_PIXEL_COUNTERS(x)     CSI_CR159_PIXEL_COUNTERS(x)
27847 #define CSI_CSICR160_PIXEL_COUNTERS_MASK     CSI_CR160_PIXEL_COUNTERS_MASK
27848 #define CSI_CSICR160_PIXEL_COUNTERS_SHIFT     CSI_CR160_PIXEL_COUNTERS_SHIFT
27849 #define CSI_CSICR160_PIXEL_COUNTERS(x)     CSI_CR160_PIXEL_COUNTERS(x)
27850 #define CSI_CSICR161_PIXEL_COUNTERS_MASK     CSI_CR161_PIXEL_COUNTERS_MASK
27851 #define CSI_CSICR161_PIXEL_COUNTERS_SHIFT     CSI_CR161_PIXEL_COUNTERS_SHIFT
27852 #define CSI_CSICR161_PIXEL_COUNTERS(x)     CSI_CR161_PIXEL_COUNTERS(x)
27853 #define CSI_CSICR162_PIXEL_COUNTERS_MASK     CSI_CR162_PIXEL_COUNTERS_MASK
27854 #define CSI_CSICR162_PIXEL_COUNTERS_SHIFT     CSI_CR162_PIXEL_COUNTERS_SHIFT
27855 #define CSI_CSICR162_PIXEL_COUNTERS(x)     CSI_CR162_PIXEL_COUNTERS(x)
27856 #define CSI_CSICR163_PIXEL_COUNTERS_MASK     CSI_CR163_PIXEL_COUNTERS_MASK
27857 #define CSI_CSICR163_PIXEL_COUNTERS_SHIFT     CSI_CR163_PIXEL_COUNTERS_SHIFT
27858 #define CSI_CSICR163_PIXEL_COUNTERS(x)     CSI_CR163_PIXEL_COUNTERS(x)
27859 #define CSI_CSICR164_PIXEL_COUNTERS_MASK     CSI_CR164_PIXEL_COUNTERS_MASK
27860 #define CSI_CSICR164_PIXEL_COUNTERS_SHIFT     CSI_CR164_PIXEL_COUNTERS_SHIFT
27861 #define CSI_CSICR164_PIXEL_COUNTERS(x)     CSI_CR164_PIXEL_COUNTERS(x)
27862 #define CSI_CSICR165_PIXEL_COUNTERS_MASK     CSI_CR165_PIXEL_COUNTERS_MASK
27863 #define CSI_CSICR165_PIXEL_COUNTERS_SHIFT     CSI_CR165_PIXEL_COUNTERS_SHIFT
27864 #define CSI_CSICR165_PIXEL_COUNTERS(x)     CSI_CR165_PIXEL_COUNTERS(x)
27865 #define CSI_CSICR166_PIXEL_COUNTERS_MASK     CSI_CR166_PIXEL_COUNTERS_MASK
27866 #define CSI_CSICR166_PIXEL_COUNTERS_SHIFT     CSI_CR166_PIXEL_COUNTERS_SHIFT
27867 #define CSI_CSICR166_PIXEL_COUNTERS(x)     CSI_CR166_PIXEL_COUNTERS(x)
27868 #define CSI_CSICR167_PIXEL_COUNTERS_MASK     CSI_CR167_PIXEL_COUNTERS_MASK
27869 #define CSI_CSICR167_PIXEL_COUNTERS_SHIFT     CSI_CR167_PIXEL_COUNTERS_SHIFT
27870 #define CSI_CSICR167_PIXEL_COUNTERS(x)     CSI_CR167_PIXEL_COUNTERS(x)
27871 #define CSI_CSICR168_PIXEL_COUNTERS_MASK     CSI_CR168_PIXEL_COUNTERS_MASK
27872 #define CSI_CSICR168_PIXEL_COUNTERS_SHIFT     CSI_CR168_PIXEL_COUNTERS_SHIFT
27873 #define CSI_CSICR168_PIXEL_COUNTERS(x)     CSI_CR168_PIXEL_COUNTERS(x)
27874 #define CSI_CSICR169_PIXEL_COUNTERS_MASK     CSI_CR169_PIXEL_COUNTERS_MASK
27875 #define CSI_CSICR169_PIXEL_COUNTERS_SHIFT     CSI_CR169_PIXEL_COUNTERS_SHIFT
27876 #define CSI_CSICR169_PIXEL_COUNTERS(x)     CSI_CR169_PIXEL_COUNTERS(x)
27877 #define CSI_CSICR170_PIXEL_COUNTERS_MASK     CSI_CR170_PIXEL_COUNTERS_MASK
27878 #define CSI_CSICR170_PIXEL_COUNTERS_SHIFT     CSI_CR170_PIXEL_COUNTERS_SHIFT
27879 #define CSI_CSICR170_PIXEL_COUNTERS(x)     CSI_CR170_PIXEL_COUNTERS(x)
27880 #define CSI_CSICR171_PIXEL_COUNTERS_MASK     CSI_CR171_PIXEL_COUNTERS_MASK
27881 #define CSI_CSICR171_PIXEL_COUNTERS_SHIFT     CSI_CR171_PIXEL_COUNTERS_SHIFT
27882 #define CSI_CSICR171_PIXEL_COUNTERS(x)     CSI_CR171_PIXEL_COUNTERS(x)
27883 #define CSI_CSICR172_PIXEL_COUNTERS_MASK     CSI_CR172_PIXEL_COUNTERS_MASK
27884 #define CSI_CSICR172_PIXEL_COUNTERS_SHIFT     CSI_CR172_PIXEL_COUNTERS_SHIFT
27885 #define CSI_CSICR172_PIXEL_COUNTERS(x)     CSI_CR172_PIXEL_COUNTERS(x)
27886 #define CSI_CSICR173_PIXEL_COUNTERS_MASK     CSI_CR173_PIXEL_COUNTERS_MASK
27887 #define CSI_CSICR173_PIXEL_COUNTERS_SHIFT     CSI_CR173_PIXEL_COUNTERS_SHIFT
27888 #define CSI_CSICR173_PIXEL_COUNTERS(x)     CSI_CR173_PIXEL_COUNTERS(x)
27889 #define CSI_CSICR174_PIXEL_COUNTERS_MASK     CSI_CR174_PIXEL_COUNTERS_MASK
27890 #define CSI_CSICR174_PIXEL_COUNTERS_SHIFT     CSI_CR174_PIXEL_COUNTERS_SHIFT
27891 #define CSI_CSICR174_PIXEL_COUNTERS(x)     CSI_CR174_PIXEL_COUNTERS(x)
27892 #define CSI_CSICR175_PIXEL_COUNTERS_MASK     CSI_CR175_PIXEL_COUNTERS_MASK
27893 #define CSI_CSICR175_PIXEL_COUNTERS_SHIFT     CSI_CR175_PIXEL_COUNTERS_SHIFT
27894 #define CSI_CSICR175_PIXEL_COUNTERS(x)     CSI_CR175_PIXEL_COUNTERS(x)
27895 #define CSI_CSICR176_PIXEL_COUNTERS_MASK     CSI_CR176_PIXEL_COUNTERS_MASK
27896 #define CSI_CSICR176_PIXEL_COUNTERS_SHIFT     CSI_CR176_PIXEL_COUNTERS_SHIFT
27897 #define CSI_CSICR176_PIXEL_COUNTERS(x)     CSI_CR176_PIXEL_COUNTERS(x)
27898 #define CSI_CSICR177_PIXEL_COUNTERS_MASK     CSI_CR177_PIXEL_COUNTERS_MASK
27899 #define CSI_CSICR177_PIXEL_COUNTERS_SHIFT     CSI_CR177_PIXEL_COUNTERS_SHIFT
27900 #define CSI_CSICR177_PIXEL_COUNTERS(x)     CSI_CR177_PIXEL_COUNTERS(x)
27901 #define CSI_CSICR178_PIXEL_COUNTERS_MASK     CSI_CR178_PIXEL_COUNTERS_MASK
27902 #define CSI_CSICR178_PIXEL_COUNTERS_SHIFT     CSI_CR178_PIXEL_COUNTERS_SHIFT
27903 #define CSI_CSICR178_PIXEL_COUNTERS(x)     CSI_CR178_PIXEL_COUNTERS(x)
27904 #define CSI_CSICR179_PIXEL_COUNTERS_MASK     CSI_CR179_PIXEL_COUNTERS_MASK
27905 #define CSI_CSICR179_PIXEL_COUNTERS_SHIFT     CSI_CR179_PIXEL_COUNTERS_SHIFT
27906 #define CSI_CSICR179_PIXEL_COUNTERS(x)     CSI_CR179_PIXEL_COUNTERS(x)
27907 #define CSI_CSICR180_PIXEL_COUNTERS_MASK     CSI_CR180_PIXEL_COUNTERS_MASK
27908 #define CSI_CSICR180_PIXEL_COUNTERS_SHIFT     CSI_CR180_PIXEL_COUNTERS_SHIFT
27909 #define CSI_CSICR180_PIXEL_COUNTERS(x)     CSI_CR180_PIXEL_COUNTERS(x)
27910 #define CSI_CSICR181_PIXEL_COUNTERS_MASK     CSI_CR181_PIXEL_COUNTERS_MASK
27911 #define CSI_CSICR181_PIXEL_COUNTERS_SHIFT     CSI_CR181_PIXEL_COUNTERS_SHIFT
27912 #define CSI_CSICR181_PIXEL_COUNTERS(x)     CSI_CR181_PIXEL_COUNTERS(x)
27913 #define CSI_CSICR182_PIXEL_COUNTERS_MASK     CSI_CR182_PIXEL_COUNTERS_MASK
27914 #define CSI_CSICR182_PIXEL_COUNTERS_SHIFT     CSI_CR182_PIXEL_COUNTERS_SHIFT
27915 #define CSI_CSICR182_PIXEL_COUNTERS(x)     CSI_CR182_PIXEL_COUNTERS(x)
27916 #define CSI_CSICR183_PIXEL_COUNTERS_MASK     CSI_CR183_PIXEL_COUNTERS_MASK
27917 #define CSI_CSICR183_PIXEL_COUNTERS_SHIFT     CSI_CR183_PIXEL_COUNTERS_SHIFT
27918 #define CSI_CSICR183_PIXEL_COUNTERS(x)     CSI_CR183_PIXEL_COUNTERS(x)
27919 #define CSI_CSICR184_PIXEL_COUNTERS_MASK     CSI_CR184_PIXEL_COUNTERS_MASK
27920 #define CSI_CSICR184_PIXEL_COUNTERS_SHIFT     CSI_CR184_PIXEL_COUNTERS_SHIFT
27921 #define CSI_CSICR184_PIXEL_COUNTERS(x)     CSI_CR184_PIXEL_COUNTERS(x)
27922 #define CSI_CSICR185_PIXEL_COUNTERS_MASK     CSI_CR185_PIXEL_COUNTERS_MASK
27923 #define CSI_CSICR185_PIXEL_COUNTERS_SHIFT     CSI_CR185_PIXEL_COUNTERS_SHIFT
27924 #define CSI_CSICR185_PIXEL_COUNTERS(x)     CSI_CR185_PIXEL_COUNTERS(x)
27925 #define CSI_CSICR186_PIXEL_COUNTERS_MASK     CSI_CR186_PIXEL_COUNTERS_MASK
27926 #define CSI_CSICR186_PIXEL_COUNTERS_SHIFT     CSI_CR186_PIXEL_COUNTERS_SHIFT
27927 #define CSI_CSICR186_PIXEL_COUNTERS(x)     CSI_CR186_PIXEL_COUNTERS(x)
27928 #define CSI_CSICR187_PIXEL_COUNTERS_MASK     CSI_CR187_PIXEL_COUNTERS_MASK
27929 #define CSI_CSICR187_PIXEL_COUNTERS_SHIFT     CSI_CR187_PIXEL_COUNTERS_SHIFT
27930 #define CSI_CSICR187_PIXEL_COUNTERS(x)     CSI_CR187_PIXEL_COUNTERS(x)
27931 #define CSI_CSICR188_PIXEL_COUNTERS_MASK     CSI_CR188_PIXEL_COUNTERS_MASK
27932 #define CSI_CSICR188_PIXEL_COUNTERS_SHIFT     CSI_CR188_PIXEL_COUNTERS_SHIFT
27933 #define CSI_CSICR188_PIXEL_COUNTERS(x)     CSI_CR188_PIXEL_COUNTERS(x)
27934 #define CSI_CSICR189_PIXEL_COUNTERS_MASK     CSI_CR189_PIXEL_COUNTERS_MASK
27935 #define CSI_CSICR189_PIXEL_COUNTERS_SHIFT     CSI_CR189_PIXEL_COUNTERS_SHIFT
27936 #define CSI_CSICR189_PIXEL_COUNTERS(x)     CSI_CR189_PIXEL_COUNTERS(x)
27937 #define CSI_CSICR190_PIXEL_COUNTERS_MASK     CSI_CR190_PIXEL_COUNTERS_MASK
27938 #define CSI_CSICR190_PIXEL_COUNTERS_SHIFT     CSI_CR190_PIXEL_COUNTERS_SHIFT
27939 #define CSI_CSICR190_PIXEL_COUNTERS(x)     CSI_CR190_PIXEL_COUNTERS(x)
27940 #define CSI_CSICR191_PIXEL_COUNTERS_MASK     CSI_CR191_PIXEL_COUNTERS_MASK
27941 #define CSI_CSICR191_PIXEL_COUNTERS_SHIFT     CSI_CR191_PIXEL_COUNTERS_SHIFT
27942 #define CSI_CSICR191_PIXEL_COUNTERS(x)     CSI_CR191_PIXEL_COUNTERS(x)
27943 #define CSI_CSICR192_PIXEL_COUNTERS_MASK     CSI_CR192_PIXEL_COUNTERS_MASK
27944 #define CSI_CSICR192_PIXEL_COUNTERS_SHIFT     CSI_CR192_PIXEL_COUNTERS_SHIFT
27945 #define CSI_CSICR192_PIXEL_COUNTERS(x)     CSI_CR192_PIXEL_COUNTERS(x)
27946 #define CSI_CSICR193_PIXEL_COUNTERS_MASK     CSI_CR193_PIXEL_COUNTERS_MASK
27947 #define CSI_CSICR193_PIXEL_COUNTERS_SHIFT     CSI_CR193_PIXEL_COUNTERS_SHIFT
27948 #define CSI_CSICR193_PIXEL_COUNTERS(x)     CSI_CR193_PIXEL_COUNTERS(x)
27949 #define CSI_CSICR194_PIXEL_COUNTERS_MASK     CSI_CR194_PIXEL_COUNTERS_MASK
27950 #define CSI_CSICR194_PIXEL_COUNTERS_SHIFT     CSI_CR194_PIXEL_COUNTERS_SHIFT
27951 #define CSI_CSICR194_PIXEL_COUNTERS(x)     CSI_CR194_PIXEL_COUNTERS(x)
27952 #define CSI_CSICR195_PIXEL_COUNTERS_MASK     CSI_CR195_PIXEL_COUNTERS_MASK
27953 #define CSI_CSICR195_PIXEL_COUNTERS_SHIFT     CSI_CR195_PIXEL_COUNTERS_SHIFT
27954 #define CSI_CSICR195_PIXEL_COUNTERS(x)     CSI_CR195_PIXEL_COUNTERS(x)
27955 #define CSI_CSICR196_PIXEL_COUNTERS_MASK     CSI_CR196_PIXEL_COUNTERS_MASK
27956 #define CSI_CSICR196_PIXEL_COUNTERS_SHIFT     CSI_CR196_PIXEL_COUNTERS_SHIFT
27957 #define CSI_CSICR196_PIXEL_COUNTERS(x)     CSI_CR196_PIXEL_COUNTERS(x)
27958 #define CSI_CSICR197_PIXEL_COUNTERS_MASK     CSI_CR197_PIXEL_COUNTERS_MASK
27959 #define CSI_CSICR197_PIXEL_COUNTERS_SHIFT     CSI_CR197_PIXEL_COUNTERS_SHIFT
27960 #define CSI_CSICR197_PIXEL_COUNTERS(x)     CSI_CR197_PIXEL_COUNTERS(x)
27961 #define CSI_CSICR198_PIXEL_COUNTERS_MASK     CSI_CR198_PIXEL_COUNTERS_MASK
27962 #define CSI_CSICR198_PIXEL_COUNTERS_SHIFT     CSI_CR198_PIXEL_COUNTERS_SHIFT
27963 #define CSI_CSICR198_PIXEL_COUNTERS(x)     CSI_CR198_PIXEL_COUNTERS(x)
27964 #define CSI_CSICR199_PIXEL_COUNTERS_MASK     CSI_CR199_PIXEL_COUNTERS_MASK
27965 #define CSI_CSICR199_PIXEL_COUNTERS_SHIFT     CSI_CR199_PIXEL_COUNTERS_SHIFT
27966 #define CSI_CSICR199_PIXEL_COUNTERS(x)     CSI_CR199_PIXEL_COUNTERS(x)
27967 #define CSI_CSICR200_PIXEL_COUNTERS_MASK     CSI_CR200_PIXEL_COUNTERS_MASK
27968 #define CSI_CSICR200_PIXEL_COUNTERS_SHIFT     CSI_CR200_PIXEL_COUNTERS_SHIFT
27969 #define CSI_CSICR200_PIXEL_COUNTERS(x)     CSI_CR200_PIXEL_COUNTERS(x)
27970 #define CSI_CSICR201_PIXEL_COUNTERS_MASK     CSI_CR201_PIXEL_COUNTERS_MASK
27971 #define CSI_CSICR201_PIXEL_COUNTERS_SHIFT     CSI_CR201_PIXEL_COUNTERS_SHIFT
27972 #define CSI_CSICR201_PIXEL_COUNTERS(x)     CSI_CR201_PIXEL_COUNTERS(x)
27973 #define CSI_CSICR202_PIXEL_COUNTERS_MASK     CSI_CR202_PIXEL_COUNTERS_MASK
27974 #define CSI_CSICR202_PIXEL_COUNTERS_SHIFT     CSI_CR202_PIXEL_COUNTERS_SHIFT
27975 #define CSI_CSICR202_PIXEL_COUNTERS(x)     CSI_CR202_PIXEL_COUNTERS(x)
27976 #define CSI_CSICR203_PIXEL_COUNTERS_MASK     CSI_CR203_PIXEL_COUNTERS_MASK
27977 #define CSI_CSICR203_PIXEL_COUNTERS_SHIFT     CSI_CR203_PIXEL_COUNTERS_SHIFT
27978 #define CSI_CSICR203_PIXEL_COUNTERS(x)     CSI_CR203_PIXEL_COUNTERS(x)
27979 #define CSI_CSICR204_PIXEL_COUNTERS_MASK     CSI_CR204_PIXEL_COUNTERS_MASK
27980 #define CSI_CSICR204_PIXEL_COUNTERS_SHIFT     CSI_CR204_PIXEL_COUNTERS_SHIFT
27981 #define CSI_CSICR204_PIXEL_COUNTERS(x)     CSI_CR204_PIXEL_COUNTERS(x)
27982 #define CSI_CSICR205_PIXEL_COUNTERS_MASK     CSI_CR205_PIXEL_COUNTERS_MASK
27983 #define CSI_CSICR205_PIXEL_COUNTERS_SHIFT     CSI_CR205_PIXEL_COUNTERS_SHIFT
27984 #define CSI_CSICR205_PIXEL_COUNTERS(x)     CSI_CR205_PIXEL_COUNTERS(x)
27985 #define CSI_CSICR206_PIXEL_COUNTERS_MASK     CSI_CR206_PIXEL_COUNTERS_MASK
27986 #define CSI_CSICR206_PIXEL_COUNTERS_SHIFT     CSI_CR206_PIXEL_COUNTERS_SHIFT
27987 #define CSI_CSICR206_PIXEL_COUNTERS(x)     CSI_CR206_PIXEL_COUNTERS(x)
27988 #define CSI_CSICR207_PIXEL_COUNTERS_MASK     CSI_CR207_PIXEL_COUNTERS_MASK
27989 #define CSI_CSICR207_PIXEL_COUNTERS_SHIFT     CSI_CR207_PIXEL_COUNTERS_SHIFT
27990 #define CSI_CSICR207_PIXEL_COUNTERS(x)     CSI_CR207_PIXEL_COUNTERS(x)
27991 #define CSI_CSICR208_PIXEL_COUNTERS_MASK     CSI_CR208_PIXEL_COUNTERS_MASK
27992 #define CSI_CSICR208_PIXEL_COUNTERS_SHIFT     CSI_CR208_PIXEL_COUNTERS_SHIFT
27993 #define CSI_CSICR208_PIXEL_COUNTERS(x)     CSI_CR208_PIXEL_COUNTERS(x)
27994 #define CSI_CSICR209_PIXEL_COUNTERS_MASK     CSI_CR209_PIXEL_COUNTERS_MASK
27995 #define CSI_CSICR209_PIXEL_COUNTERS_SHIFT     CSI_CR209_PIXEL_COUNTERS_SHIFT
27996 #define CSI_CSICR209_PIXEL_COUNTERS(x)     CSI_CR209_PIXEL_COUNTERS(x)
27997 #define CSI_CSICR210_PIXEL_COUNTERS_MASK     CSI_CR210_PIXEL_COUNTERS_MASK
27998 #define CSI_CSICR210_PIXEL_COUNTERS_SHIFT     CSI_CR210_PIXEL_COUNTERS_SHIFT
27999 #define CSI_CSICR210_PIXEL_COUNTERS(x)     CSI_CR210_PIXEL_COUNTERS(x)
28000 #define CSI_CSICR211_PIXEL_COUNTERS_MASK     CSI_CR211_PIXEL_COUNTERS_MASK
28001 #define CSI_CSICR211_PIXEL_COUNTERS_SHIFT     CSI_CR211_PIXEL_COUNTERS_SHIFT
28002 #define CSI_CSICR211_PIXEL_COUNTERS(x)     CSI_CR211_PIXEL_COUNTERS(x)
28003 #define CSI_CSICR212_PIXEL_COUNTERS_MASK     CSI_CR212_PIXEL_COUNTERS_MASK
28004 #define CSI_CSICR212_PIXEL_COUNTERS_SHIFT     CSI_CR212_PIXEL_COUNTERS_SHIFT
28005 #define CSI_CSICR212_PIXEL_COUNTERS(x)     CSI_CR212_PIXEL_COUNTERS(x)
28006 #define CSI_CSICR213_PIXEL_COUNTERS_MASK     CSI_CR213_PIXEL_COUNTERS_MASK
28007 #define CSI_CSICR213_PIXEL_COUNTERS_SHIFT     CSI_CR213_PIXEL_COUNTERS_SHIFT
28008 #define CSI_CSICR213_PIXEL_COUNTERS(x)     CSI_CR213_PIXEL_COUNTERS(x)
28009 #define CSI_CSICR214_PIXEL_COUNTERS_MASK     CSI_CR214_PIXEL_COUNTERS_MASK
28010 #define CSI_CSICR214_PIXEL_COUNTERS_SHIFT     CSI_CR214_PIXEL_COUNTERS_SHIFT
28011 #define CSI_CSICR214_PIXEL_COUNTERS(x)     CSI_CR214_PIXEL_COUNTERS(x)
28012 #define CSI_CSICR215_PIXEL_COUNTERS_MASK     CSI_CR215_PIXEL_COUNTERS_MASK
28013 #define CSI_CSICR215_PIXEL_COUNTERS_SHIFT     CSI_CR215_PIXEL_COUNTERS_SHIFT
28014 #define CSI_CSICR215_PIXEL_COUNTERS(x)     CSI_CR215_PIXEL_COUNTERS(x)
28015 #define CSI_CSICR216_PIXEL_COUNTERS_MASK     CSI_CR216_PIXEL_COUNTERS_MASK
28016 #define CSI_CSICR216_PIXEL_COUNTERS_SHIFT     CSI_CR216_PIXEL_COUNTERS_SHIFT
28017 #define CSI_CSICR216_PIXEL_COUNTERS(x)     CSI_CR216_PIXEL_COUNTERS(x)
28018 #define CSI_CSICR217_PIXEL_COUNTERS_MASK     CSI_CR217_PIXEL_COUNTERS_MASK
28019 #define CSI_CSICR217_PIXEL_COUNTERS_SHIFT     CSI_CR217_PIXEL_COUNTERS_SHIFT
28020 #define CSI_CSICR217_PIXEL_COUNTERS(x)     CSI_CR217_PIXEL_COUNTERS(x)
28021 #define CSI_CSICR218_PIXEL_COUNTERS_MASK     CSI_CR218_PIXEL_COUNTERS_MASK
28022 #define CSI_CSICR218_PIXEL_COUNTERS_SHIFT     CSI_CR218_PIXEL_COUNTERS_SHIFT
28023 #define CSI_CSICR218_PIXEL_COUNTERS(x)     CSI_CR218_PIXEL_COUNTERS(x)
28024 #define CSI_CSICR219_PIXEL_COUNTERS_MASK     CSI_CR219_PIXEL_COUNTERS_MASK
28025 #define CSI_CSICR219_PIXEL_COUNTERS_SHIFT     CSI_CR219_PIXEL_COUNTERS_SHIFT
28026 #define CSI_CSICR219_PIXEL_COUNTERS(x)     CSI_CR219_PIXEL_COUNTERS(x)
28027 #define CSI_CSICR220_PIXEL_COUNTERS_MASK     CSI_CR220_PIXEL_COUNTERS_MASK
28028 #define CSI_CSICR220_PIXEL_COUNTERS_SHIFT     CSI_CR220_PIXEL_COUNTERS_SHIFT
28029 #define CSI_CSICR220_PIXEL_COUNTERS(x)     CSI_CR220_PIXEL_COUNTERS(x)
28030 #define CSI_CSICR221_PIXEL_COUNTERS_MASK     CSI_CR221_PIXEL_COUNTERS_MASK
28031 #define CSI_CSICR221_PIXEL_COUNTERS_SHIFT     CSI_CR221_PIXEL_COUNTERS_SHIFT
28032 #define CSI_CSICR221_PIXEL_COUNTERS(x)     CSI_CR221_PIXEL_COUNTERS(x)
28033 #define CSI_CSICR222_PIXEL_COUNTERS_MASK     CSI_CR222_PIXEL_COUNTERS_MASK
28034 #define CSI_CSICR222_PIXEL_COUNTERS_SHIFT     CSI_CR222_PIXEL_COUNTERS_SHIFT
28035 #define CSI_CSICR222_PIXEL_COUNTERS(x)     CSI_CR222_PIXEL_COUNTERS(x)
28036 #define CSI_CSICR223_PIXEL_COUNTERS_MASK     CSI_CR223_PIXEL_COUNTERS_MASK
28037 #define CSI_CSICR223_PIXEL_COUNTERS_SHIFT     CSI_CR223_PIXEL_COUNTERS_SHIFT
28038 #define CSI_CSICR223_PIXEL_COUNTERS(x)     CSI_CR223_PIXEL_COUNTERS(x)
28039 #define CSI_CSICR224_PIXEL_COUNTERS_MASK     CSI_CR224_PIXEL_COUNTERS_MASK
28040 #define CSI_CSICR224_PIXEL_COUNTERS_SHIFT     CSI_CR224_PIXEL_COUNTERS_SHIFT
28041 #define CSI_CSICR224_PIXEL_COUNTERS(x)     CSI_CR224_PIXEL_COUNTERS(x)
28042 #define CSI_CSICR225_PIXEL_COUNTERS_MASK     CSI_CR225_PIXEL_COUNTERS_MASK
28043 #define CSI_CSICR225_PIXEL_COUNTERS_SHIFT     CSI_CR225_PIXEL_COUNTERS_SHIFT
28044 #define CSI_CSICR225_PIXEL_COUNTERS(x)     CSI_CR225_PIXEL_COUNTERS(x)
28045 #define CSI_CSICR226_PIXEL_COUNTERS_MASK     CSI_CR226_PIXEL_COUNTERS_MASK
28046 #define CSI_CSICR226_PIXEL_COUNTERS_SHIFT     CSI_CR226_PIXEL_COUNTERS_SHIFT
28047 #define CSI_CSICR226_PIXEL_COUNTERS(x)     CSI_CR226_PIXEL_COUNTERS(x)
28048 #define CSI_CSICR227_PIXEL_COUNTERS_MASK     CSI_CR227_PIXEL_COUNTERS_MASK
28049 #define CSI_CSICR227_PIXEL_COUNTERS_SHIFT     CSI_CR227_PIXEL_COUNTERS_SHIFT
28050 #define CSI_CSICR227_PIXEL_COUNTERS(x)     CSI_CR227_PIXEL_COUNTERS(x)
28051 #define CSI_CSICR228_PIXEL_COUNTERS_MASK     CSI_CR228_PIXEL_COUNTERS_MASK
28052 #define CSI_CSICR228_PIXEL_COUNTERS_SHIFT     CSI_CR228_PIXEL_COUNTERS_SHIFT
28053 #define CSI_CSICR228_PIXEL_COUNTERS(x)     CSI_CR228_PIXEL_COUNTERS(x)
28054 #define CSI_CSICR229_PIXEL_COUNTERS_MASK     CSI_CR229_PIXEL_COUNTERS_MASK
28055 #define CSI_CSICR229_PIXEL_COUNTERS_SHIFT     CSI_CR229_PIXEL_COUNTERS_SHIFT
28056 #define CSI_CSICR229_PIXEL_COUNTERS(x)     CSI_CR229_PIXEL_COUNTERS(x)
28057 #define CSI_CSICR230_PIXEL_COUNTERS_MASK     CSI_CR230_PIXEL_COUNTERS_MASK
28058 #define CSI_CSICR230_PIXEL_COUNTERS_SHIFT     CSI_CR230_PIXEL_COUNTERS_SHIFT
28059 #define CSI_CSICR230_PIXEL_COUNTERS(x)     CSI_CR230_PIXEL_COUNTERS(x)
28060 #define CSI_CSICR231_PIXEL_COUNTERS_MASK     CSI_CR231_PIXEL_COUNTERS_MASK
28061 #define CSI_CSICR231_PIXEL_COUNTERS_SHIFT     CSI_CR231_PIXEL_COUNTERS_SHIFT
28062 #define CSI_CSICR231_PIXEL_COUNTERS(x)     CSI_CR231_PIXEL_COUNTERS(x)
28063 #define CSI_CSICR232_PIXEL_COUNTERS_MASK     CSI_CR232_PIXEL_COUNTERS_MASK
28064 #define CSI_CSICR232_PIXEL_COUNTERS_SHIFT     CSI_CR232_PIXEL_COUNTERS_SHIFT
28065 #define CSI_CSICR232_PIXEL_COUNTERS(x)     CSI_CR232_PIXEL_COUNTERS(x)
28066 #define CSI_CSICR233_PIXEL_COUNTERS_MASK     CSI_CR233_PIXEL_COUNTERS_MASK
28067 #define CSI_CSICR233_PIXEL_COUNTERS_SHIFT     CSI_CR233_PIXEL_COUNTERS_SHIFT
28068 #define CSI_CSICR233_PIXEL_COUNTERS(x)     CSI_CR233_PIXEL_COUNTERS(x)
28069 #define CSI_CSICR234_PIXEL_COUNTERS_MASK     CSI_CR234_PIXEL_COUNTERS_MASK
28070 #define CSI_CSICR234_PIXEL_COUNTERS_SHIFT     CSI_CR234_PIXEL_COUNTERS_SHIFT
28071 #define CSI_CSICR234_PIXEL_COUNTERS(x)     CSI_CR234_PIXEL_COUNTERS(x)
28072 #define CSI_CSICR235_PIXEL_COUNTERS_MASK     CSI_CR235_PIXEL_COUNTERS_MASK
28073 #define CSI_CSICR235_PIXEL_COUNTERS_SHIFT     CSI_CR235_PIXEL_COUNTERS_SHIFT
28074 #define CSI_CSICR235_PIXEL_COUNTERS(x)     CSI_CR235_PIXEL_COUNTERS(x)
28075 #define CSI_CSICR236_PIXEL_COUNTERS_MASK     CSI_CR236_PIXEL_COUNTERS_MASK
28076 #define CSI_CSICR236_PIXEL_COUNTERS_SHIFT     CSI_CR236_PIXEL_COUNTERS_SHIFT
28077 #define CSI_CSICR236_PIXEL_COUNTERS(x)     CSI_CR236_PIXEL_COUNTERS(x)
28078 #define CSI_CSICR237_PIXEL_COUNTERS_MASK     CSI_CR237_PIXEL_COUNTERS_MASK
28079 #define CSI_CSICR237_PIXEL_COUNTERS_SHIFT     CSI_CR237_PIXEL_COUNTERS_SHIFT
28080 #define CSI_CSICR237_PIXEL_COUNTERS(x)     CSI_CR237_PIXEL_COUNTERS(x)
28081 #define CSI_CSICR238_PIXEL_COUNTERS_MASK     CSI_CR238_PIXEL_COUNTERS_MASK
28082 #define CSI_CSICR238_PIXEL_COUNTERS_SHIFT     CSI_CR238_PIXEL_COUNTERS_SHIFT
28083 #define CSI_CSICR238_PIXEL_COUNTERS(x)     CSI_CR238_PIXEL_COUNTERS(x)
28084 #define CSI_CSICR239_PIXEL_COUNTERS_MASK     CSI_CR239_PIXEL_COUNTERS_MASK
28085 #define CSI_CSICR239_PIXEL_COUNTERS_SHIFT     CSI_CR239_PIXEL_COUNTERS_SHIFT
28086 #define CSI_CSICR239_PIXEL_COUNTERS(x)     CSI_CR239_PIXEL_COUNTERS(x)
28087 #define CSI_CSICR240_PIXEL_COUNTERS_MASK     CSI_CR240_PIXEL_COUNTERS_MASK
28088 #define CSI_CSICR240_PIXEL_COUNTERS_SHIFT     CSI_CR240_PIXEL_COUNTERS_SHIFT
28089 #define CSI_CSICR240_PIXEL_COUNTERS(x)     CSI_CR240_PIXEL_COUNTERS(x)
28090 #define CSI_CSICR241_PIXEL_COUNTERS_MASK     CSI_CR241_PIXEL_COUNTERS_MASK
28091 #define CSI_CSICR241_PIXEL_COUNTERS_SHIFT     CSI_CR241_PIXEL_COUNTERS_SHIFT
28092 #define CSI_CSICR241_PIXEL_COUNTERS(x)     CSI_CR241_PIXEL_COUNTERS(x)
28093 #define CSI_CSICR242_PIXEL_COUNTERS_MASK     CSI_CR242_PIXEL_COUNTERS_MASK
28094 #define CSI_CSICR242_PIXEL_COUNTERS_SHIFT     CSI_CR242_PIXEL_COUNTERS_SHIFT
28095 #define CSI_CSICR242_PIXEL_COUNTERS(x)     CSI_CR242_PIXEL_COUNTERS(x)
28096 #define CSI_CSICR243_PIXEL_COUNTERS_MASK     CSI_CR243_PIXEL_COUNTERS_MASK
28097 #define CSI_CSICR243_PIXEL_COUNTERS_SHIFT     CSI_CR243_PIXEL_COUNTERS_SHIFT
28098 #define CSI_CSICR243_PIXEL_COUNTERS(x)     CSI_CR243_PIXEL_COUNTERS(x)
28099 #define CSI_CSICR244_PIXEL_COUNTERS_MASK     CSI_CR244_PIXEL_COUNTERS_MASK
28100 #define CSI_CSICR244_PIXEL_COUNTERS_SHIFT     CSI_CR244_PIXEL_COUNTERS_SHIFT
28101 #define CSI_CSICR244_PIXEL_COUNTERS(x)     CSI_CR244_PIXEL_COUNTERS(x)
28102 #define CSI_CSICR245_PIXEL_COUNTERS_MASK     CSI_CR245_PIXEL_COUNTERS_MASK
28103 #define CSI_CSICR245_PIXEL_COUNTERS_SHIFT     CSI_CR245_PIXEL_COUNTERS_SHIFT
28104 #define CSI_CSICR245_PIXEL_COUNTERS(x)     CSI_CR245_PIXEL_COUNTERS(x)
28105 #define CSI_CSICR246_PIXEL_COUNTERS_MASK     CSI_CR246_PIXEL_COUNTERS_MASK
28106 #define CSI_CSICR246_PIXEL_COUNTERS_SHIFT     CSI_CR246_PIXEL_COUNTERS_SHIFT
28107 #define CSI_CSICR246_PIXEL_COUNTERS(x)     CSI_CR246_PIXEL_COUNTERS(x)
28108 #define CSI_CSICR247_PIXEL_COUNTERS_MASK     CSI_CR247_PIXEL_COUNTERS_MASK
28109 #define CSI_CSICR247_PIXEL_COUNTERS_SHIFT     CSI_CR247_PIXEL_COUNTERS_SHIFT
28110 #define CSI_CSICR247_PIXEL_COUNTERS(x)     CSI_CR247_PIXEL_COUNTERS(x)
28111 #define CSI_CSICR248_PIXEL_COUNTERS_MASK     CSI_CR248_PIXEL_COUNTERS_MASK
28112 #define CSI_CSICR248_PIXEL_COUNTERS_SHIFT     CSI_CR248_PIXEL_COUNTERS_SHIFT
28113 #define CSI_CSICR248_PIXEL_COUNTERS(x)     CSI_CR248_PIXEL_COUNTERS(x)
28114 #define CSI_CSICR249_PIXEL_COUNTERS_MASK     CSI_CR249_PIXEL_COUNTERS_MASK
28115 #define CSI_CSICR249_PIXEL_COUNTERS_SHIFT     CSI_CR249_PIXEL_COUNTERS_SHIFT
28116 #define CSI_CSICR249_PIXEL_COUNTERS(x)     CSI_CR249_PIXEL_COUNTERS(x)
28117 #define CSI_CSICR250_PIXEL_COUNTERS_MASK     CSI_CR250_PIXEL_COUNTERS_MASK
28118 #define CSI_CSICR250_PIXEL_COUNTERS_SHIFT     CSI_CR250_PIXEL_COUNTERS_SHIFT
28119 #define CSI_CSICR250_PIXEL_COUNTERS(x)     CSI_CR250_PIXEL_COUNTERS(x)
28120 #define CSI_CSICR251_PIXEL_COUNTERS_MASK     CSI_CR251_PIXEL_COUNTERS_MASK
28121 #define CSI_CSICR251_PIXEL_COUNTERS_SHIFT     CSI_CR251_PIXEL_COUNTERS_SHIFT
28122 #define CSI_CSICR251_PIXEL_COUNTERS(x)     CSI_CR251_PIXEL_COUNTERS(x)
28123 #define CSI_CSICR252_PIXEL_COUNTERS_MASK     CSI_CR252_PIXEL_COUNTERS_MASK
28124 #define CSI_CSICR252_PIXEL_COUNTERS_SHIFT     CSI_CR252_PIXEL_COUNTERS_SHIFT
28125 #define CSI_CSICR252_PIXEL_COUNTERS(x)     CSI_CR252_PIXEL_COUNTERS(x)
28126 #define CSI_CSICR253_PIXEL_COUNTERS_MASK     CSI_CR253_PIXEL_COUNTERS_MASK
28127 #define CSI_CSICR253_PIXEL_COUNTERS_SHIFT     CSI_CR253_PIXEL_COUNTERS_SHIFT
28128 #define CSI_CSICR253_PIXEL_COUNTERS(x)     CSI_CR253_PIXEL_COUNTERS(x)
28129 #define CSI_CSICR254_PIXEL_COUNTERS_MASK     CSI_CR254_PIXEL_COUNTERS_MASK
28130 #define CSI_CSICR254_PIXEL_COUNTERS_SHIFT     CSI_CR254_PIXEL_COUNTERS_SHIFT
28131 #define CSI_CSICR254_PIXEL_COUNTERS(x)     CSI_CR254_PIXEL_COUNTERS(x)
28132 #define CSI_CSICR255_PIXEL_COUNTERS_MASK     CSI_CR255_PIXEL_COUNTERS_MASK
28133 #define CSI_CSICR255_PIXEL_COUNTERS_SHIFT     CSI_CR255_PIXEL_COUNTERS_SHIFT
28134 #define CSI_CSICR255_PIXEL_COUNTERS(x)     CSI_CR255_PIXEL_COUNTERS(x)
28135 #define CSI_CSICR256_PIXEL_COUNTERS_MASK     CSI_CR256_PIXEL_COUNTERS_MASK
28136 #define CSI_CSICR256_PIXEL_COUNTERS_SHIFT     CSI_CR256_PIXEL_COUNTERS_SHIFT
28137 #define CSI_CSICR256_PIXEL_COUNTERS(x)     CSI_CR256_PIXEL_COUNTERS(x)
28138 #define CSI_CSICR257_PIXEL_COUNTERS_MASK     CSI_CR257_PIXEL_COUNTERS_MASK
28139 #define CSI_CSICR257_PIXEL_COUNTERS_SHIFT     CSI_CR257_PIXEL_COUNTERS_SHIFT
28140 #define CSI_CSICR257_PIXEL_COUNTERS(x)     CSI_CR257_PIXEL_COUNTERS(x)
28141 #define CSI_CSICR258_PIXEL_COUNTERS_MASK     CSI_CR258_PIXEL_COUNTERS_MASK
28142 #define CSI_CSICR258_PIXEL_COUNTERS_SHIFT     CSI_CR258_PIXEL_COUNTERS_SHIFT
28143 #define CSI_CSICR258_PIXEL_COUNTERS(x)     CSI_CR258_PIXEL_COUNTERS(x)
28144 #define CSI_CSICR259_PIXEL_COUNTERS_MASK     CSI_CR259_PIXEL_COUNTERS_MASK
28145 #define CSI_CSICR259_PIXEL_COUNTERS_SHIFT     CSI_CR259_PIXEL_COUNTERS_SHIFT
28146 #define CSI_CSICR259_PIXEL_COUNTERS(x)     CSI_CR259_PIXEL_COUNTERS(x)
28147 #define CSI_CSICR260_PIXEL_COUNTERS_MASK     CSI_CR260_PIXEL_COUNTERS_MASK
28148 #define CSI_CSICR260_PIXEL_COUNTERS_SHIFT     CSI_CR260_PIXEL_COUNTERS_SHIFT
28149 #define CSI_CSICR260_PIXEL_COUNTERS(x)     CSI_CR260_PIXEL_COUNTERS(x)
28150 #define CSI_CSICR261_PIXEL_COUNTERS_MASK     CSI_CR261_PIXEL_COUNTERS_MASK
28151 #define CSI_CSICR261_PIXEL_COUNTERS_SHIFT     CSI_CR261_PIXEL_COUNTERS_SHIFT
28152 #define CSI_CSICR261_PIXEL_COUNTERS(x)     CSI_CR261_PIXEL_COUNTERS(x)
28153 #define CSI_CSICR262_PIXEL_COUNTERS_MASK     CSI_CR262_PIXEL_COUNTERS_MASK
28154 #define CSI_CSICR262_PIXEL_COUNTERS_SHIFT     CSI_CR262_PIXEL_COUNTERS_SHIFT
28155 #define CSI_CSICR262_PIXEL_COUNTERS(x)     CSI_CR262_PIXEL_COUNTERS(x)
28156 #define CSI_CSICR263_PIXEL_COUNTERS_MASK     CSI_CR263_PIXEL_COUNTERS_MASK
28157 #define CSI_CSICR263_PIXEL_COUNTERS_SHIFT     CSI_CR263_PIXEL_COUNTERS_SHIFT
28158 #define CSI_CSICR263_PIXEL_COUNTERS(x)     CSI_CR263_PIXEL_COUNTERS(x)
28159 #define CSI_CSICR264_PIXEL_COUNTERS_MASK     CSI_CR264_PIXEL_COUNTERS_MASK
28160 #define CSI_CSICR264_PIXEL_COUNTERS_SHIFT     CSI_CR264_PIXEL_COUNTERS_SHIFT
28161 #define CSI_CSICR264_PIXEL_COUNTERS(x)     CSI_CR264_PIXEL_COUNTERS(x)
28162 #define CSI_CSICR265_PIXEL_COUNTERS_MASK     CSI_CR265_PIXEL_COUNTERS_MASK
28163 #define CSI_CSICR265_PIXEL_COUNTERS_SHIFT     CSI_CR265_PIXEL_COUNTERS_SHIFT
28164 #define CSI_CSICR265_PIXEL_COUNTERS(x)     CSI_CR265_PIXEL_COUNTERS(x)
28165 #define CSI_CSICR266_PIXEL_COUNTERS_MASK     CSI_CR266_PIXEL_COUNTERS_MASK
28166 #define CSI_CSICR266_PIXEL_COUNTERS_SHIFT     CSI_CR266_PIXEL_COUNTERS_SHIFT
28167 #define CSI_CSICR266_PIXEL_COUNTERS(x)     CSI_CR266_PIXEL_COUNTERS(x)
28168 #define CSI_CSICR267_PIXEL_COUNTERS_MASK     CSI_CR267_PIXEL_COUNTERS_MASK
28169 #define CSI_CSICR267_PIXEL_COUNTERS_SHIFT     CSI_CR267_PIXEL_COUNTERS_SHIFT
28170 #define CSI_CSICR267_PIXEL_COUNTERS(x)     CSI_CR267_PIXEL_COUNTERS(x)
28171 #define CSI_CSICR268_PIXEL_COUNTERS_MASK     CSI_CR268_PIXEL_COUNTERS_MASK
28172 #define CSI_CSICR268_PIXEL_COUNTERS_SHIFT     CSI_CR268_PIXEL_COUNTERS_SHIFT
28173 #define CSI_CSICR268_PIXEL_COUNTERS(x)     CSI_CR268_PIXEL_COUNTERS(x)
28174 #define CSI_CSICR269_PIXEL_COUNTERS_MASK     CSI_CR269_PIXEL_COUNTERS_MASK
28175 #define CSI_CSICR269_PIXEL_COUNTERS_SHIFT     CSI_CR269_PIXEL_COUNTERS_SHIFT
28176 #define CSI_CSICR269_PIXEL_COUNTERS(x)     CSI_CR269_PIXEL_COUNTERS(x)
28177 #define CSI_CSICR270_PIXEL_COUNTERS_MASK     CSI_CR270_PIXEL_COUNTERS_MASK
28178 #define CSI_CSICR270_PIXEL_COUNTERS_SHIFT     CSI_CR270_PIXEL_COUNTERS_SHIFT
28179 #define CSI_CSICR270_PIXEL_COUNTERS(x)     CSI_CR270_PIXEL_COUNTERS(x)
28180 #define CSI_CSICR271_PIXEL_COUNTERS_MASK     CSI_CR271_PIXEL_COUNTERS_MASK
28181 #define CSI_CSICR271_PIXEL_COUNTERS_SHIFT     CSI_CR271_PIXEL_COUNTERS_SHIFT
28182 #define CSI_CSICR271_PIXEL_COUNTERS(x)     CSI_CR271_PIXEL_COUNTERS(x)
28183 #define CSI_CSICR272_PIXEL_COUNTERS_MASK     CSI_CR272_PIXEL_COUNTERS_MASK
28184 #define CSI_CSICR272_PIXEL_COUNTERS_SHIFT     CSI_CR272_PIXEL_COUNTERS_SHIFT
28185 #define CSI_CSICR272_PIXEL_COUNTERS(x)     CSI_CR272_PIXEL_COUNTERS(x)
28186 #define CSI_CSICR273_PIXEL_COUNTERS_MASK     CSI_CR273_PIXEL_COUNTERS_MASK
28187 #define CSI_CSICR273_PIXEL_COUNTERS_SHIFT     CSI_CR273_PIXEL_COUNTERS_SHIFT
28188 #define CSI_CSICR273_PIXEL_COUNTERS(x)     CSI_CR273_PIXEL_COUNTERS(x)
28189 #define CSI_CSICR274_PIXEL_COUNTERS_MASK     CSI_CR274_PIXEL_COUNTERS_MASK
28190 #define CSI_CSICR274_PIXEL_COUNTERS_SHIFT     CSI_CR274_PIXEL_COUNTERS_SHIFT
28191 #define CSI_CSICR274_PIXEL_COUNTERS(x)     CSI_CR274_PIXEL_COUNTERS(x)
28192 #define CSI_CSICR275_PIXEL_COUNTERS_MASK     CSI_CR275_PIXEL_COUNTERS_MASK
28193 #define CSI_CSICR275_PIXEL_COUNTERS_SHIFT     CSI_CR275_PIXEL_COUNTERS_SHIFT
28194 #define CSI_CSICR275_PIXEL_COUNTERS(x)     CSI_CR275_PIXEL_COUNTERS(x)
28195 #define CSI_CSICR276_PIXEL_COUNTERS_MASK     CSI_CR276_PIXEL_COUNTERS_MASK
28196 #define CSI_CSICR276_PIXEL_COUNTERS_SHIFT     CSI_CR276_PIXEL_COUNTERS_SHIFT
28197 #define CSI_CSICR276_PIXEL_COUNTERS(x)     CSI_CR276_PIXEL_COUNTERS(x)
28198 
28199 
28200 /*!
28201  * @}
28202  */ /* end of group CSI_Peripheral_Access_Layer */
28203 
28204 
28205 /* ----------------------------------------------------------------------------
28206    -- DAC Peripheral Access Layer
28207    ---------------------------------------------------------------------------- */
28208 
28209 /*!
28210  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
28211  * @{
28212  */
28213 
28214 /** DAC - Register Layout Typedef */
28215 typedef struct {
28216   __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
28217   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
28218   __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
28219   __IO uint32_t CR;                                /**< DAC Status and Control Register, offset: 0xC */
28220   __I  uint32_t PTR;                               /**< DAC FIFO Pointer Register, offset: 0x10 */
28221   __IO uint32_t CR2;                               /**< DAC Status and Control Register 2, offset: 0x14 */
28222 } DAC_Type;
28223 
28224 /* ----------------------------------------------------------------------------
28225    -- DAC Register Masks
28226    ---------------------------------------------------------------------------- */
28227 
28228 /*!
28229  * @addtogroup DAC_Register_Masks DAC Register Masks
28230  * @{
28231  */
28232 
28233 /*! @name VERID - Version Identifier Register */
28234 /*! @{ */
28235 
28236 #define DAC_VERID_FEATURE_MASK                   (0xFFFFU)
28237 #define DAC_VERID_FEATURE_SHIFT                  (0U)
28238 /*! FEATURE - Feature Identification Number
28239  *  0b0000000000000000..Standard feature set
28240  *  0b0000000000000001..C40 feature set
28241  *  0b0000000000000010..5V DAC feature set
28242  *  0b0000000000000100..ADC BIST feature set
28243  */
28244 #define DAC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
28245 
28246 #define DAC_VERID_MINOR_MASK                     (0xFF0000U)
28247 #define DAC_VERID_MINOR_SHIFT                    (16U)
28248 /*! MINOR - Minor version number
28249  */
28250 #define DAC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
28251 
28252 #define DAC_VERID_MAJOR_MASK                     (0xFF000000U)
28253 #define DAC_VERID_MAJOR_SHIFT                    (24U)
28254 /*! MAJOR - Major version number
28255  */
28256 #define DAC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
28257 /*! @} */
28258 
28259 /*! @name PARAM - Parameter Register */
28260 /*! @{ */
28261 
28262 #define DAC_PARAM_FIFOSZ_MASK                    (0x7U)
28263 #define DAC_PARAM_FIFOSZ_SHIFT                   (0U)
28264 /*! FIFOSZ - FIFO size
28265  *  0b000..FIFO depth is 2
28266  *  0b001..FIFO depth is 4
28267  *  0b010..FIFO depth is 8
28268  *  0b011..FIFO depth is 16
28269  *  0b100..FIFO depth is 32
28270  *  0b101..FIFO depth is 64
28271  *  0b110..FIFO depth is 128
28272  *  0b111..FIFO depth is 256
28273  */
28274 #define DAC_PARAM_FIFOSZ(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
28275 /*! @} */
28276 
28277 /*! @name DATA - DAC Data Register */
28278 /*! @{ */
28279 
28280 #define DAC_DATA_DATA0_MASK                      (0xFFFU)
28281 #define DAC_DATA_DATA0_SHIFT                     (0U)
28282 /*! DATA0 - FIFO DATA0
28283  */
28284 #define DAC_DATA_DATA0(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
28285 /*! @} */
28286 
28287 /*! @name CR - DAC Status and Control Register */
28288 /*! @{ */
28289 
28290 #define DAC_CR_FULLF_MASK                        (0x1U)
28291 #define DAC_CR_FULLF_SHIFT                       (0U)
28292 /*! FULLF - Full Flag
28293  *  0b0..FIFO is not full.
28294  *  0b1..FIFO is full.
28295  */
28296 #define DAC_CR_FULLF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
28297 
28298 #define DAC_CR_NEMPTF_MASK                       (0x2U)
28299 #define DAC_CR_NEMPTF_SHIFT                      (1U)
28300 /*! NEMPTF - Nearly Empty Flag
28301  *  0b0..More than one data is available in the FIFO.
28302  *  0b1..One data is available in the FIFO.
28303  */
28304 #define DAC_CR_NEMPTF(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
28305 
28306 #define DAC_CR_WMF_MASK                          (0x4U)
28307 #define DAC_CR_WMF_SHIFT                         (2U)
28308 /*! WMF - FIFO Watermark Status Flag
28309  *  0b0..The DAC buffer read pointer has not reached the watermark level.
28310  *  0b1..The DAC buffer read pointer has reached the watermark level.
28311  */
28312 #define DAC_CR_WMF(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
28313 
28314 #define DAC_CR_UDFF_MASK                         (0x8U)
28315 #define DAC_CR_UDFF_SHIFT                        (3U)
28316 /*! UDFF - Underflow Flag
28317  *  0b0..No underflow has occurred since the last time the flag was cleared.
28318  *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
28319  */
28320 #define DAC_CR_UDFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
28321 
28322 #define DAC_CR_OVFF_MASK                         (0x10U)
28323 #define DAC_CR_OVFF_SHIFT                        (4U)
28324 /*! OVFF - Overflow Flag
28325  *  0b0..No overflow has occurred since the last time the flag was cleared.
28326  *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
28327  */
28328 #define DAC_CR_OVFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
28329 
28330 #define DAC_CR_FULLIE_MASK                       (0x100U)
28331 #define DAC_CR_FULLIE_SHIFT                      (8U)
28332 /*! FULLIE - Full Interrupt Enable
28333  *  0b0..FIFO Full interrupt is disabled.
28334  *  0b1..FIFO Full interrupt is enabled.
28335  */
28336 #define DAC_CR_FULLIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
28337 
28338 #define DAC_CR_EMPTIE_MASK                       (0x200U)
28339 #define DAC_CR_EMPTIE_SHIFT                      (9U)
28340 /*! EMPTIE - Nearly Empty Interrupt Enable
28341  *  0b0..FIFO Nearly Empty interrupt is disabled.
28342  *  0b1..FIFO Nearly Empty interrupt is enabled.
28343  */
28344 #define DAC_CR_EMPTIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
28345 
28346 #define DAC_CR_WTMIE_MASK                        (0x400U)
28347 #define DAC_CR_WTMIE_SHIFT                       (10U)
28348 /*! WTMIE - Watermark Interrupt Enable
28349  *  0b0..Watermark interrupt is disabled.
28350  *  0b1..Watermark interrupt is enabled.
28351  */
28352 #define DAC_CR_WTMIE(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
28353 
28354 #define DAC_CR_SWTRG_MASK                        (0x1000U)
28355 #define DAC_CR_SWTRG_SHIFT                       (12U)
28356 /*! SWTRG - DAC Software Trigger
28357  *  0b0..The DAC soft trigger is not valid.
28358  *  0b1..The DAC soft trigger is valid.
28359  */
28360 #define DAC_CR_SWTRG(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
28361 
28362 #define DAC_CR_TRGSEL_MASK                       (0x2000U)
28363 #define DAC_CR_TRGSEL_SHIFT                      (13U)
28364 /*! TRGSEL - DAC Trigger Select
28365  *  0b0..The DAC hardware trigger is selected.
28366  *  0b1..The DAC software trigger is selected.
28367  */
28368 #define DAC_CR_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
28369 
28370 #define DAC_CR_DACRFS_MASK                       (0x4000U)
28371 #define DAC_CR_DACRFS_SHIFT                      (14U)
28372 /*! DACRFS - DAC Reference Select
28373  *  0b0..The DAC selects DACREF_1 as the reference voltage.
28374  *  0b1..The DAC selects DACREF_2 as the reference voltage.
28375  */
28376 #define DAC_CR_DACRFS(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
28377 
28378 #define DAC_CR_DACEN_MASK                        (0x8000U)
28379 #define DAC_CR_DACEN_SHIFT                       (15U)
28380 /*! DACEN - DAC Enable
28381  *  0b0..The DAC system is disabled.
28382  *  0b1..The DAC system is enabled.
28383  */
28384 #define DAC_CR_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
28385 
28386 #define DAC_CR_FIFOEN_MASK                       (0x10000U)
28387 #define DAC_CR_FIFOEN_SHIFT                      (16U)
28388 /*! FIFOEN - FIFO Enable
28389  *  0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
28390  *  0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
28391  */
28392 #define DAC_CR_FIFOEN(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
28393 
28394 #define DAC_CR_SWMD_MASK                         (0x20000U)
28395 #define DAC_CR_SWMD_SHIFT                        (17U)
28396 /*! SWMD - DAC FIFO Mode Select
28397  *  0b0..Normal mode
28398  *  0b1..Swing back mode
28399  */
28400 #define DAC_CR_SWMD(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
28401 
28402 #define DAC_CR_UVIE_MASK                         (0x40000U)
28403 #define DAC_CR_UVIE_SHIFT                        (18U)
28404 /*! UVIE - Underflow and overflow interrupt enable
28405  *  0b0..Underflow and overflow interrupt is disabled.
28406  *  0b1..Underflow and overflow interrupt is enabled.
28407  */
28408 #define DAC_CR_UVIE(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
28409 
28410 #define DAC_CR_FIFORST_MASK                      (0x200000U)
28411 #define DAC_CR_FIFORST_SHIFT                     (21U)
28412 /*! FIFORST - FIFO Reset
28413  *  0b0..No effect
28414  *  0b1..FIFO reset
28415  */
28416 #define DAC_CR_FIFORST(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
28417 
28418 #define DAC_CR_SWRST_MASK                        (0x400000U)
28419 #define DAC_CR_SWRST_SHIFT                       (22U)
28420 /*! SWRST - Software reset
28421  */
28422 #define DAC_CR_SWRST(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
28423 
28424 #define DAC_CR_DMAEN_MASK                        (0x800000U)
28425 #define DAC_CR_DMAEN_SHIFT                       (23U)
28426 /*! DMAEN - DMA Enable Select
28427  *  0b0..DMA is disabled.
28428  *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
28429  *       interrupts will not be presented on this module at the same time.
28430  */
28431 #define DAC_CR_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
28432 
28433 #define DAC_CR_WML_MASK                          (0xFF000000U)
28434 #define DAC_CR_WML_SHIFT                         (24U)
28435 /*! WML - Watermark Level Select
28436  */
28437 #define DAC_CR_WML(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
28438 /*! @} */
28439 
28440 /*! @name PTR - DAC FIFO Pointer Register */
28441 /*! @{ */
28442 
28443 #define DAC_PTR_DACWFP_MASK                      (0xFFU)
28444 #define DAC_PTR_DACWFP_SHIFT                     (0U)
28445 /*! DACWFP - DACWFP
28446  */
28447 #define DAC_PTR_DACWFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
28448 
28449 #define DAC_PTR_DACRFP_MASK                      (0xFF0000U)
28450 #define DAC_PTR_DACRFP_SHIFT                     (16U)
28451 /*! DACRFP - DACRFP
28452  */
28453 #define DAC_PTR_DACRFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
28454 /*! @} */
28455 
28456 /*! @name CR2 - DAC Status and Control Register 2 */
28457 /*! @{ */
28458 
28459 #define DAC_CR2_BFEN_MASK                        (0x1U)
28460 #define DAC_CR2_BFEN_SHIFT                       (0U)
28461 /*! BFEN - Buffer Enable
28462  *  0b0..Opamp is not used as buffer
28463  *  0b1..Opamp is used as buffer
28464  */
28465 #define DAC_CR2_BFEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
28466 
28467 #define DAC_CR2_OEN_MASK                         (0x2U)
28468 #define DAC_CR2_OEN_SHIFT                        (1U)
28469 /*! OEN - Optional Enable
28470  *  0b0..Output buffer is not bypassed
28471  *  0b1..Output buffer is bypassed
28472  */
28473 #define DAC_CR2_OEN(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
28474 
28475 #define DAC_CR2_BFMS_MASK                        (0x4U)
28476 #define DAC_CR2_BFMS_SHIFT                       (2U)
28477 /*! BFMS - Buffer Middle Speed Select
28478  *  0b0..Buffer middle speed not selected
28479  *  0b1..Buffer middle speed selected
28480  */
28481 #define DAC_CR2_BFMS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
28482 
28483 #define DAC_CR2_BFHS_MASK                        (0x8U)
28484 #define DAC_CR2_BFHS_SHIFT                       (3U)
28485 /*! BFHS - Buffer High Speed Select
28486  *  0b0..Buffer high speed not selected
28487  *  0b1..Buffer high speed selected
28488  */
28489 #define DAC_CR2_BFHS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
28490 
28491 #define DAC_CR2_IREF2_MASK                       (0x10U)
28492 #define DAC_CR2_IREF2_SHIFT                      (4U)
28493 /*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
28494  *  0b0..Internal PTAT Current Reference not selected
28495  *  0b1..Internal PTAT Current Reference selected
28496  */
28497 #define DAC_CR2_IREF2(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
28498 
28499 #define DAC_CR2_IREF1_MASK                       (0x20U)
28500 #define DAC_CR2_IREF1_SHIFT                      (5U)
28501 /*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
28502  *  0b0..Internal ZTC Current Reference not selected
28503  *  0b1..Internal ZTC Current Reference selected
28504  */
28505 #define DAC_CR2_IREF1(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
28506 
28507 #define DAC_CR2_IREF_MASK                        (0x40U)
28508 #define DAC_CR2_IREF_SHIFT                       (6U)
28509 /*! IREF - Internal Current Reference Select
28510  *  0b0..Internal Current Reference not selected
28511  *  0b1..Internal Current Reference selected
28512  */
28513 #define DAC_CR2_IREF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
28514 /*! @} */
28515 
28516 
28517 /*!
28518  * @}
28519  */ /* end of group DAC_Register_Masks */
28520 
28521 
28522 /* DAC - Peripheral instance base addresses */
28523 /** Peripheral DAC base address */
28524 #define DAC_BASE                                 (0x40064000u)
28525 /** Peripheral DAC base pointer */
28526 #define DAC                                      ((DAC_Type *)DAC_BASE)
28527 /** Array initializer of DAC peripheral base addresses */
28528 #define DAC_BASE_ADDRS                           { DAC_BASE }
28529 /** Array initializer of DAC peripheral base pointers */
28530 #define DAC_BASE_PTRS                            { DAC }
28531 /** Interrupt vectors for the DAC peripheral type */
28532 #define DAC_IRQS                                 { DAC_IRQn }
28533 
28534 /*!
28535  * @}
28536  */ /* end of group DAC_Peripheral_Access_Layer */
28537 
28538 
28539 /* ----------------------------------------------------------------------------
28540    -- DCDC Peripheral Access Layer
28541    ---------------------------------------------------------------------------- */
28542 
28543 /*!
28544  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
28545  * @{
28546  */
28547 
28548 /** DCDC - Register Layout Typedef */
28549 typedef struct {
28550   __IO uint32_t CTRL0;                             /**< DCDC Control Register 0, offset: 0x0 */
28551   __IO uint32_t CTRL1;                             /**< DCDC Control Register 1, offset: 0x4 */
28552   __IO uint32_t REG0;                              /**< DCDC Register 0, offset: 0x8 */
28553   __IO uint32_t REG1;                              /**< DCDC Register 1, offset: 0xC */
28554   __IO uint32_t REG2;                              /**< DCDC Register 2, offset: 0x10 */
28555   __IO uint32_t REG3;                              /**< DCDC Register 3, offset: 0x14 */
28556   __IO uint32_t REG4;                              /**< DCDC Register 4, offset: 0x18 */
28557   __IO uint32_t REG5;                              /**< DCDC Register 5, offset: 0x1C */
28558   __IO uint32_t REG6;                              /**< DCDC Register 6, offset: 0x20 */
28559   __IO uint32_t REG7;                              /**< DCDC Register 7, offset: 0x24 */
28560   __IO uint32_t REG7P;                             /**< DCDC Register 7 plus, offset: 0x28 */
28561   __IO uint32_t REG8;                              /**< DCDC Register 8, offset: 0x2C */
28562   __IO uint32_t REG9;                              /**< DCDC Register 9, offset: 0x30 */
28563   __IO uint32_t REG10;                             /**< DCDC Register 10, offset: 0x34 */
28564   __IO uint32_t REG11;                             /**< DCDC Register 11, offset: 0x38 */
28565   __IO uint32_t REG12;                             /**< DCDC Register 12, offset: 0x3C */
28566   __IO uint32_t REG13;                             /**< DCDC Register 13, offset: 0x40 */
28567   __IO uint32_t REG14;                             /**< DCDC Register 14, offset: 0x44 */
28568   __IO uint32_t REG15;                             /**< DCDC Register 15, offset: 0x48 */
28569   __IO uint32_t REG16;                             /**< DCDC Register 16, offset: 0x4C */
28570   __IO uint32_t REG17;                             /**< DCDC Register 17, offset: 0x50 */
28571   __IO uint32_t REG18;                             /**< DCDC Register 18, offset: 0x54 */
28572   __IO uint32_t REG19;                             /**< DCDC Register 19, offset: 0x58 */
28573   __IO uint32_t REG20;                             /**< DCDC Register 20, offset: 0x5C */
28574   __IO uint32_t REG21;                             /**< DCDC Register 21, offset: 0x60 */
28575   __IO uint32_t REG22;                             /**< DCDC Register 22, offset: 0x64 */
28576   __IO uint32_t REG23;                             /**< DCDC Register 23, offset: 0x68 */
28577   __IO uint32_t REG24;                             /**< DCDC Register 24, offset: 0x6C */
28578 } DCDC_Type;
28579 
28580 /* ----------------------------------------------------------------------------
28581    -- DCDC Register Masks
28582    ---------------------------------------------------------------------------- */
28583 
28584 /*!
28585  * @addtogroup DCDC_Register_Masks DCDC Register Masks
28586  * @{
28587  */
28588 
28589 /*! @name CTRL0 - DCDC Control Register 0 */
28590 /*! @{ */
28591 
28592 #define DCDC_CTRL0_ENABLE_MASK                   (0x1U)
28593 #define DCDC_CTRL0_ENABLE_SHIFT                  (0U)
28594 /*! ENABLE
28595  *  0b0..Disable (Bypass)
28596  *  0b1..Enable
28597  */
28598 #define DCDC_CTRL0_ENABLE(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
28599 
28600 #define DCDC_CTRL0_DIG_EN_MASK                   (0x2U)
28601 #define DCDC_CTRL0_DIG_EN_SHIFT                  (1U)
28602 /*! DIG_EN
28603  *  0b0..Reserved
28604  *  0b1..Enable
28605  */
28606 #define DCDC_CTRL0_DIG_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
28607 
28608 #define DCDC_CTRL0_STBY_EN_MASK                  (0x4U)
28609 #define DCDC_CTRL0_STBY_EN_SHIFT                 (2U)
28610 /*! STBY_EN
28611  *  0b1..Enter into standby mode
28612  */
28613 #define DCDC_CTRL0_STBY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
28614 
28615 #define DCDC_CTRL0_LP_MODE_EN_MASK               (0x8U)
28616 #define DCDC_CTRL0_LP_MODE_EN_SHIFT              (3U)
28617 /*! LP_MODE_EN
28618  *  0b1..Enter into low-power mode
28619  */
28620 #define DCDC_CTRL0_LP_MODE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
28621 
28622 #define DCDC_CTRL0_STBY_LP_MODE_EN_MASK          (0x10U)
28623 #define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT         (4U)
28624 /*! STBY_LP_MODE_EN
28625  *  0b0..Disable DCDC entry into low-power mode from a GPC standby request
28626  *  0b1..Enable DCDC to enter into low-power mode from a GPC standby request
28627  */
28628 #define DCDC_CTRL0_STBY_LP_MODE_EN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
28629 
28630 #define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK          (0x20U)
28631 #define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT         (5U)
28632 /*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout
28633  *  0b0..Wait DCDC_OK for ACK
28634  *  0b1..Enable internal count for DCDC_OK timeout
28635  */
28636 #define DCDC_CTRL0_ENABLE_DCDC_CNT(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
28637 
28638 #define DCDC_CTRL0_TRIM_HOLD_MASK                (0x40U)
28639 #define DCDC_CTRL0_TRIM_HOLD_SHIFT               (6U)
28640 /*! TRIM_HOLD - Hold trim input
28641  *  0b0..Sample trim input
28642  *  0b1..Hold trim input
28643  */
28644 #define DCDC_CTRL0_TRIM_HOLD(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
28645 
28646 #define DCDC_CTRL0_DEBUG_BITS_MASK               (0x7FF80000U)
28647 #define DCDC_CTRL0_DEBUG_BITS_SHIFT              (19U)
28648 /*! DEBUG_BITS - DEBUG_BITS[11:0]
28649  */
28650 #define DCDC_CTRL0_DEBUG_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
28651 
28652 #define DCDC_CTRL0_CONTROL_MODE_MASK             (0x80000000U)
28653 #define DCDC_CTRL0_CONTROL_MODE_SHIFT            (31U)
28654 /*! CONTROL_MODE - Control mode
28655  *  0b0..Software control mode
28656  *  0b1..Hardware control mode (controlled by GPC Setpoints)
28657  */
28658 #define DCDC_CTRL0_CONTROL_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
28659 /*! @} */
28660 
28661 /*! @name CTRL1 - DCDC Control Register 1 */
28662 /*! @{ */
28663 
28664 #define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK           (0x1FU)
28665 #define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT          (0U)
28666 /*! VDD1P8CTRL_TRG
28667  *  0b11111..2.275V
28668  *  0b01100..1.8V
28669  *  0b00000..1.5V
28670  */
28671 #define DCDC_CTRL1_VDD1P8CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
28672 
28673 #define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK           (0x1F00U)
28674 #define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT          (8U)
28675 /*! VDD1P0CTRL_TRG
28676  *  0b11111..1.375V
28677  *  0b10000..1.0V
28678  *  0b00000..0.6V
28679  */
28680 #define DCDC_CTRL1_VDD1P0CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
28681 
28682 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK      (0x1F0000U)
28683 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT     (16U)
28684 /*! VDD1P8CTRL_STBY_TRG
28685  *  0b11111..2.3V
28686  *  0b01011..1.8V
28687  *  0b00000..1.525V
28688  */
28689 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
28690 
28691 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK      (0x1F000000U)
28692 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT     (24U)
28693 /*! VDD1P0CTRL_STBY_TRG
28694  *  0b11111..1.4V
28695  *  0b01111..1.0V
28696  *  0b00000..0.625V
28697  */
28698 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)
28699 /*! @} */
28700 
28701 /*! @name REG0 - DCDC Register 0 */
28702 /*! @{ */
28703 
28704 #define DCDC_REG0_PWD_ZCD_MASK                   (0x1U)
28705 #define DCDC_REG0_PWD_ZCD_SHIFT                  (0U)
28706 /*! PWD_ZCD - Power Down Zero Cross Detection
28707  *  0b0..Zero cross detetion function powered up
28708  *  0b1..Zero cross detetion function powered down
28709  */
28710 #define DCDC_REG0_PWD_ZCD(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
28711 
28712 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
28713 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT  (1U)
28714 /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
28715  *  0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal
28716  *       ring oscillator to 24M xtal automatically
28717  *  0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
28718  */
28719 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
28720 
28721 #define DCDC_REG0_SEL_CLK_MASK                   (0x4U)
28722 #define DCDC_REG0_SEL_CLK_SHIFT                  (2U)
28723 /*! SEL_CLK - Select Clock
28724  *  0b0..DCDC uses internal ring oscillator
28725  *  0b1..DCDC uses 24M xtal
28726  */
28727 #define DCDC_REG0_SEL_CLK(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
28728 
28729 #define DCDC_REG0_PWD_OSC_INT_MASK               (0x8U)
28730 #define DCDC_REG0_PWD_OSC_INT_SHIFT              (3U)
28731 /*! PWD_OSC_INT - Power down internal ring oscillator
28732  *  0b0..Internal ring oscillator powered up
28733  *  0b1..Internal ring oscillator powered down
28734  */
28735 #define DCDC_REG0_PWD_OSC_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
28736 
28737 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK           (0x10U)
28738 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT          (4U)
28739 /*! PWD_CUR_SNS_CMP - Power down signal of the current detector
28740  *  0b0..Current Detector powered up
28741  *  0b1..Current Detector powered down
28742  */
28743 #define DCDC_REG0_PWD_CUR_SNS_CMP(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
28744 
28745 #define DCDC_REG0_CUR_SNS_THRSH_MASK             (0xE0U)
28746 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT            (5U)
28747 /*! CUR_SNS_THRSH - Current Sense (detector) Threshold
28748  */
28749 #define DCDC_REG0_CUR_SNS_THRSH(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
28750 
28751 #define DCDC_REG0_PWD_OVERCUR_DET_MASK           (0x100U)
28752 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT          (8U)
28753 /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
28754  *  0b0..Overcurrent detection comparator is enabled
28755  *  0b1..Overcurrent detection comparator is disabled
28756  */
28757 #define DCDC_REG0_PWD_OVERCUR_DET(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
28758 
28759 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK       (0x800U)
28760 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT      (11U)
28761 /*! PWD_CMP_DCDC_IN_DET
28762  *  0b0..Low voltage detection comparator is enabled
28763  *  0b1..Low voltage detection comparator is disabled
28764  */
28765 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
28766 
28767 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK       (0x10000U)
28768 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT      (16U)
28769 /*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8
28770  *  0b0..Overvoltage detection comparator for the VDD1P8 output is enabled
28771  *  0b1..Overvoltage detection comparator for the VDD1P8 output is disabled
28772  */
28773 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
28774 
28775 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK       (0x20000U)
28776 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT      (17U)
28777 /*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0
28778  *  0b0..Overvoltage detection comparator for the VDD1P0 output is enabled
28779  *  0b1..Overvoltage detection comparator for the VDD1P0 output is disabled
28780  */
28781 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
28782 
28783 #define DCDC_REG0_LP_HIGH_HYS_MASK               (0x200000U)
28784 #define DCDC_REG0_LP_HIGH_HYS_SHIFT              (21U)
28785 /*! LP_HIGH_HYS - Low Power High Hysteric Value
28786  *  0b0..Adjust hysteretic value in low power to 12.5mV
28787  *  0b1..Adjust hysteretic value in low power to 25mV
28788  */
28789 #define DCDC_REG0_LP_HIGH_HYS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
28790 
28791 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
28792 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
28793 /*! PWD_CMP_OFFSET - power down the out-of-range detection comparator
28794  *  0b0..Out-of-range comparator powered up
28795  *  0b1..Out-of-range comparator powered down
28796  */
28797 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
28798 
28799 #define DCDC_REG0_XTALOK_DISABLE_MASK            (0x8000000U)
28800 #define DCDC_REG0_XTALOK_DISABLE_SHIFT           (27U)
28801 /*! XTALOK_DISABLE - Disable xtalok detection circuit
28802  *  0b0..Enable xtalok detection circuit
28803  *  0b1..Disable xtalok detection circuit and always outputs OK signal "1"
28804  */
28805 #define DCDC_REG0_XTALOK_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
28806 
28807 #define DCDC_REG0_XTAL_24M_OK_MASK               (0x20000000U)
28808 #define DCDC_REG0_XTAL_24M_OK_SHIFT              (29U)
28809 /*! XTAL_24M_OK - 24M XTAL OK
28810  *  0b0..DCDC uses internal ring oscillator
28811  *  0b1..DCDC uses xtal 24M
28812  */
28813 #define DCDC_REG0_XTAL_24M_OK(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
28814 
28815 #define DCDC_REG0_STS_DC_OK_MASK                 (0x80000000U)
28816 #define DCDC_REG0_STS_DC_OK_SHIFT                (31U)
28817 /*! STS_DC_OK - DCDC Output OK
28818  *  0b0..DCDC is settling
28819  *  0b1..DCDC already settled
28820  */
28821 #define DCDC_REG0_STS_DC_OK(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
28822 /*! @} */
28823 
28824 /*! @name REG1 - DCDC Register 1 */
28825 /*! @{ */
28826 
28827 #define DCDC_REG1_DM_CTRL_MASK                   (0x8U)
28828 #define DCDC_REG1_DM_CTRL_SHIFT                  (3U)
28829 /*! DM_CTRL - DM Control
28830  *  0b0..No change to ripple when the discontinuous current is present in DCM.
28831  *  0b1..Improves ripple when the inductor current goes to zero in DCM.
28832  */
28833 #define DCDC_REG1_DM_CTRL(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
28834 
28835 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK         (0x10U)
28836 #define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT        (4U)
28837 /*! RLOAD_REG_EN_LPSR - Load Resistor Enable
28838  *  0b0..Disconnect load resistor
28839  *  0b1..Connect load resistor
28840  */
28841 #define DCDC_REG1_RLOAD_REG_EN_LPSR(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
28842 
28843 #define DCDC_REG1_VBG_TRIM_MASK                  (0x7C0U)
28844 #define DCDC_REG1_VBG_TRIM_SHIFT                 (6U)
28845 /*! VBG_TRIM - Trim Bandgap Voltage
28846  *  0b00000..0.452V
28847  *  0b10000..0.5V
28848  *  0b11111..0.545V
28849  */
28850 #define DCDC_REG1_VBG_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
28851 
28852 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK           (0x1800U)
28853 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT          (11U)
28854 /*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias
28855  *  0b00..50nA
28856  *  0b01..100nA
28857  *  0b10..200nA
28858  *  0b11..400nA
28859  */
28860 #define DCDC_REG1_LP_CMP_ISRC_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
28861 
28862 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK    (0x8000000U)
28863 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
28864 /*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection
28865  */
28866 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
28867 
28868 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK    (0x10000000U)
28869 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
28870 /*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection
28871  */
28872 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
28873 
28874 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK       (0x20000000U)
28875 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT      (29U)
28876 /*! LOOPCTRL_EN_CM_HYST
28877  *  0b0..Disable hysteresis in switching converter common mode analog comparators
28878  *  0b1..Enable hysteresis in switching converter common mode analog comparators
28879  */
28880 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
28881 
28882 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK       (0x40000000U)
28883 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT      (30U)
28884 /*! LOOPCTRL_EN_DF_HYST
28885  *  0b0..Disable hysteresis in switching converter differential mode analog comparators
28886  *  0b1..Enable hysteresis in switching converter differential mode analog comparators
28887  */
28888 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
28889 /*! @} */
28890 
28891 /*! @name REG2 - DCDC Register 2 */
28892 /*! @{ */
28893 
28894 #define DCDC_REG2_LOOPCTRL_DC_C_MASK             (0x3U)
28895 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT            (0U)
28896 #define DCDC_REG2_LOOPCTRL_DC_C(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
28897 
28898 #define DCDC_REG2_LOOPCTRL_DC_R_MASK             (0x3CU)
28899 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT            (2U)
28900 #define DCDC_REG2_LOOPCTRL_DC_R(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
28901 
28902 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK            (0x1C0U)
28903 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT           (6U)
28904 #define DCDC_REG2_LOOPCTRL_DC_FF(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
28905 
28906 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK       (0xE00U)
28907 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT      (9U)
28908 /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale
28909  */
28910 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
28911 
28912 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK    (0x1000U)
28913 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
28914 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
28915 
28916 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK        (0x2000U)
28917 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT       (13U)
28918 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
28919 
28920 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK     (0x8000U)
28921 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT    (15U)
28922 #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
28923 
28924 #define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK      (0x3FF0000U)
28925 #define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT     (16U)
28926 #define DCDC_REG2_BATTMONITOR_BATT_VAL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
28927 
28928 #define DCDC_REG2_DCM_SET_CTRL_MASK              (0x10000000U)
28929 #define DCDC_REG2_DCM_SET_CTRL_SHIFT             (28U)
28930 /*! DCM_SET_CTRL - DCM Set Control
28931  */
28932 #define DCDC_REG2_DCM_SET_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
28933 
28934 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK       (0x40000000U)
28935 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT      (30U)
28936 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
28937 /*! @} */
28938 
28939 /*! @name REG3 - DCDC Register 3 */
28940 /*! @{ */
28941 
28942 #define DCDC_REG3_IN_BROWNOUT_MASK               (0x4000U)
28943 #define DCDC_REG3_IN_BROWNOUT_SHIFT              (14U)
28944 /*! IN_BROWNOUT
28945  *  0b1..DCDC_IN is lower than 2.6V
28946  */
28947 #define DCDC_REG3_IN_BROWNOUT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
28948 
28949 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
28950 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT  (15U)
28951 /*! OVERVOLT_VDD1P8_DET_OUT
28952  *  0b1..VDD1P8 Overvoltage
28953  */
28954 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
28955 
28956 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
28957 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT  (16U)
28958 /*! OVERVOLT_VDD1P0_DET_OUT
28959  *  0b1..VDD1P0 Overvoltage
28960  */
28961 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
28962 
28963 #define DCDC_REG3_OVERCUR_DETECT_OUT_MASK        (0x20000U)
28964 #define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT       (17U)
28965 /*! OVERCUR_DETECT_OUT
28966  *  0b1..Overcurrent
28967  */
28968 #define DCDC_REG3_OVERCUR_DETECT_OUT(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
28969 
28970 #define DCDC_REG3_ENABLE_FF_MASK                 (0x40000U)
28971 #define DCDC_REG3_ENABLE_FF_SHIFT                (18U)
28972 /*! ENABLE_FF
28973  *  0b1..Enable feed-forward (FF) function that can speed up transient settling.
28974  */
28975 #define DCDC_REG3_ENABLE_FF(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
28976 
28977 #define DCDC_REG3_DISABLE_PULSE_SKIP_MASK        (0x80000U)
28978 #define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT       (19U)
28979 /*! DISABLE_PULSE_SKIP - Disable Pulse Skip
28980  *  0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN
28981  */
28982 #define DCDC_REG3_DISABLE_PULSE_SKIP(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
28983 
28984 #define DCDC_REG3_DISABLE_IDLE_SKIP_MASK         (0x100000U)
28985 #define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT        (20U)
28986 /*! DISABLE_IDLE_SKIP
28987  *  0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output
28988  *       voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled
28989  *       (PWD_CMP_OFFSET=0).
28990  */
28991 #define DCDC_REG3_DISABLE_IDLE_SKIP(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
28992 
28993 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK  (0x200000U)
28994 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U)
28995 /*! DOUBLE_IBIAS_CMP_LP_LPSR
28996  *  0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode
28997  */
28998 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
28999 
29000 #define DCDC_REG3_REG_FBK_SEL_MASK               (0xC00000U)
29001 #define DCDC_REG3_REG_FBK_SEL_SHIFT              (22U)
29002 #define DCDC_REG3_REG_FBK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
29003 
29004 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK         (0x1000000U)
29005 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT        (24U)
29006 /*! MINPWR_DC_HALFCLK
29007  *  0b0..DCDC clock remains at full frequency for continuous mode
29008  *  0b1..DCDC clock set to half frequency for continuous mode
29009  */
29010 #define DCDC_REG3_MINPWR_DC_HALFCLK(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
29011 
29012 #define DCDC_REG3_MINPWR_HALF_FETS_MASK          (0x4000000U)
29013 #define DCDC_REG3_MINPWR_HALF_FETS_SHIFT         (26U)
29014 #define DCDC_REG3_MINPWR_HALF_FETS(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
29015 
29016 #define DCDC_REG3_MISC_DELAY_TIMING_MASK         (0x8000000U)
29017 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT        (27U)
29018 /*! MISC_DELAY_TIMING - Miscellaneous Delay Timing
29019  */
29020 #define DCDC_REG3_MISC_DELAY_TIMING(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
29021 
29022 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
29023 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT  (29U)
29024 /*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0
29025  *  0b0..Enable stepping for VDD1P0
29026  *  0b1..Disable stepping for VDD1P0
29027  */
29028 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
29029 
29030 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
29031 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT  (30U)
29032 /*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8
29033  *  0b0..Enable stepping for VDD1P8
29034  *  0b1..Disable stepping for VDD1P8
29035  */
29036 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)
29037 /*! @} */
29038 
29039 /*! @name REG4 - DCDC Register 4 */
29040 /*! @{ */
29041 
29042 #define DCDC_REG4_ENABLE_SP_MASK                 (0xFFFFU)
29043 #define DCDC_REG4_ENABLE_SP_SHIFT                (0U)
29044 #define DCDC_REG4_ENABLE_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)
29045 /*! @} */
29046 
29047 /*! @name REG5 - DCDC Register 5 */
29048 /*! @{ */
29049 
29050 #define DCDC_REG5_DIG_EN_SP_MASK                 (0xFFFFU)
29051 #define DCDC_REG5_DIG_EN_SP_SHIFT                (0U)
29052 #define DCDC_REG5_DIG_EN_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)
29053 /*! @} */
29054 
29055 /*! @name REG6 - DCDC Register 6 */
29056 /*! @{ */
29057 
29058 #define DCDC_REG6_LP_MODE_SP_MASK                (0xFFFFU)
29059 #define DCDC_REG6_LP_MODE_SP_SHIFT               (0U)
29060 #define DCDC_REG6_LP_MODE_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)
29061 /*! @} */
29062 
29063 /*! @name REG7 - DCDC Register 7 */
29064 /*! @{ */
29065 
29066 #define DCDC_REG7_STBY_EN_SP_MASK                (0xFFFFU)
29067 #define DCDC_REG7_STBY_EN_SP_SHIFT               (0U)
29068 #define DCDC_REG7_STBY_EN_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)
29069 /*! @} */
29070 
29071 /*! @name REG7P - DCDC Register 7 plus */
29072 /*! @{ */
29073 
29074 #define DCDC_REG7P_STBY_LP_MODE_SP_MASK          (0xFFFFU)
29075 #define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT         (0U)
29076 #define DCDC_REG7P_STBY_LP_MODE_SP(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)
29077 /*! @} */
29078 
29079 /*! @name REG8 - DCDC Register 8 */
29080 /*! @{ */
29081 
29082 #define DCDC_REG8_ANA_TRG_SP0_MASK               (0xFFFFFFFFU)
29083 #define DCDC_REG8_ANA_TRG_SP0_SHIFT              (0U)
29084 #define DCDC_REG8_ANA_TRG_SP0(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)
29085 /*! @} */
29086 
29087 /*! @name REG9 - DCDC Register 9 */
29088 /*! @{ */
29089 
29090 #define DCDC_REG9_ANA_TRG_SP1_MASK               (0xFFFFFFFFU)
29091 #define DCDC_REG9_ANA_TRG_SP1_SHIFT              (0U)
29092 #define DCDC_REG9_ANA_TRG_SP1(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)
29093 /*! @} */
29094 
29095 /*! @name REG10 - DCDC Register 10 */
29096 /*! @{ */
29097 
29098 #define DCDC_REG10_ANA_TRG_SP2_MASK              (0xFFFFFFFFU)
29099 #define DCDC_REG10_ANA_TRG_SP2_SHIFT             (0U)
29100 #define DCDC_REG10_ANA_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)
29101 /*! @} */
29102 
29103 /*! @name REG11 - DCDC Register 11 */
29104 /*! @{ */
29105 
29106 #define DCDC_REG11_ANA_TRG_SP3_MASK              (0xFFFFFFFFU)
29107 #define DCDC_REG11_ANA_TRG_SP3_SHIFT             (0U)
29108 #define DCDC_REG11_ANA_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)
29109 /*! @} */
29110 
29111 /*! @name REG12 - DCDC Register 12 */
29112 /*! @{ */
29113 
29114 #define DCDC_REG12_DIG_TRG_SP0_MASK              (0xFFFFFFFFU)
29115 #define DCDC_REG12_DIG_TRG_SP0_SHIFT             (0U)
29116 #define DCDC_REG12_DIG_TRG_SP0(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)
29117 /*! @} */
29118 
29119 /*! @name REG13 - DCDC Register 13 */
29120 /*! @{ */
29121 
29122 #define DCDC_REG13_DIG_TRG_SP1_MASK              (0xFFFFFFFFU)
29123 #define DCDC_REG13_DIG_TRG_SP1_SHIFT             (0U)
29124 #define DCDC_REG13_DIG_TRG_SP1(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)
29125 /*! @} */
29126 
29127 /*! @name REG14 - DCDC Register 14 */
29128 /*! @{ */
29129 
29130 #define DCDC_REG14_DIG_TRG_SP2_MASK              (0xFFFFFFFFU)
29131 #define DCDC_REG14_DIG_TRG_SP2_SHIFT             (0U)
29132 #define DCDC_REG14_DIG_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)
29133 /*! @} */
29134 
29135 /*! @name REG15 - DCDC Register 15 */
29136 /*! @{ */
29137 
29138 #define DCDC_REG15_DIG_TRG_SP3_MASK              (0xFFFFFFFFU)
29139 #define DCDC_REG15_DIG_TRG_SP3_SHIFT             (0U)
29140 #define DCDC_REG15_DIG_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)
29141 /*! @} */
29142 
29143 /*! @name REG16 - DCDC Register 16 */
29144 /*! @{ */
29145 
29146 #define DCDC_REG16_ANA_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
29147 #define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT        (0U)
29148 #define DCDC_REG16_ANA_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)
29149 /*! @} */
29150 
29151 /*! @name REG17 - DCDC Register 17 */
29152 /*! @{ */
29153 
29154 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
29155 #define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT        (0U)
29156 #define DCDC_REG17_ANA_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
29157 /*! @} */
29158 
29159 /*! @name REG18 - DCDC Register 18 */
29160 /*! @{ */
29161 
29162 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
29163 #define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT        (0U)
29164 #define DCDC_REG18_ANA_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
29165 /*! @} */
29166 
29167 /*! @name REG19 - DCDC Register 19 */
29168 /*! @{ */
29169 
29170 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
29171 #define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT        (0U)
29172 #define DCDC_REG19_ANA_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
29173 /*! @} */
29174 
29175 /*! @name REG20 - DCDC Register 20 */
29176 /*! @{ */
29177 
29178 #define DCDC_REG20_DIG_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
29179 #define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT        (0U)
29180 #define DCDC_REG20_DIG_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)
29181 /*! @} */
29182 
29183 /*! @name REG21 - DCDC Register 21 */
29184 /*! @{ */
29185 
29186 #define DCDC_REG21_DIG_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
29187 #define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT        (0U)
29188 #define DCDC_REG21_DIG_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)
29189 /*! @} */
29190 
29191 /*! @name REG22 - DCDC Register 22 */
29192 /*! @{ */
29193 
29194 #define DCDC_REG22_DIG_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
29195 #define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT        (0U)
29196 #define DCDC_REG22_DIG_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)
29197 /*! @} */
29198 
29199 /*! @name REG23 - DCDC Register 23 */
29200 /*! @{ */
29201 
29202 #define DCDC_REG23_DIG_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
29203 #define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT        (0U)
29204 #define DCDC_REG23_DIG_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)
29205 /*! @} */
29206 
29207 /*! @name REG24 - DCDC Register 24 */
29208 /*! @{ */
29209 
29210 #define DCDC_REG24_OK_COUNT_MASK                 (0xFFFFFFFFU)
29211 #define DCDC_REG24_OK_COUNT_SHIFT                (0U)
29212 #define DCDC_REG24_OK_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
29213 /*! @} */
29214 
29215 
29216 /*!
29217  * @}
29218  */ /* end of group DCDC_Register_Masks */
29219 
29220 
29221 /* DCDC - Peripheral instance base addresses */
29222 /** Peripheral DCDC base address */
29223 #define DCDC_BASE                                (0x40CA8000u)
29224 /** Peripheral DCDC base pointer */
29225 #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
29226 /** Array initializer of DCDC peripheral base addresses */
29227 #define DCDC_BASE_ADDRS                          { DCDC_BASE }
29228 /** Array initializer of DCDC peripheral base pointers */
29229 #define DCDC_BASE_PTRS                           { DCDC }
29230 
29231 /*!
29232  * @}
29233  */ /* end of group DCDC_Peripheral_Access_Layer */
29234 
29235 
29236 /* ----------------------------------------------------------------------------
29237    -- DCIC Peripheral Access Layer
29238    ---------------------------------------------------------------------------- */
29239 
29240 /*!
29241  * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer
29242  * @{
29243  */
29244 
29245 /** DCIC - Register Layout Typedef */
29246 typedef struct {
29247   __IO uint32_t DCICC;                             /**< DCIC Control Register, offset: 0x0 */
29248   __IO uint32_t DCICIC;                            /**< DCIC Interrupt Control Register, offset: 0x4 */
29249   __IO uint32_t DCICS;                             /**< DCIC Status Register, offset: 0x8 */
29250        uint8_t RESERVED_0[4];
29251   struct {                                         /* offset: 0x10, array step: 0x10 */
29252     __IO uint32_t DCICRC;                            /**< DCIC ROI Config Register, array offset: 0x10, array step: 0x10 */
29253     __IO uint32_t DCICRS;                            /**< DCIC ROI Size Register, array offset: 0x14, array step: 0x10 */
29254     __IO uint32_t DCICRRS;                           /**< DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10 */
29255     __I  uint32_t DCICRCS;                           /**< DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10 */
29256   } REGION[16];
29257 } DCIC_Type;
29258 
29259 /* ----------------------------------------------------------------------------
29260    -- DCIC Register Masks
29261    ---------------------------------------------------------------------------- */
29262 
29263 /*!
29264  * @addtogroup DCIC_Register_Masks DCIC Register Masks
29265  * @{
29266  */
29267 
29268 /*! @name DCICC - DCIC Control Register */
29269 /*! @{ */
29270 
29271 #define DCIC_DCICC_IC_EN_MASK                    (0x1U)
29272 #define DCIC_DCICC_IC_EN_SHIFT                   (0U)
29273 /*! IC_EN
29274  *  0b0..Disabled
29275  *  0b1..Enabled
29276  */
29277 #define DCIC_DCICC_IC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK)
29278 
29279 #define DCIC_DCICC_DE_POL_MASK                   (0x10U)
29280 #define DCIC_DCICC_DE_POL_SHIFT                  (4U)
29281 /*! DE_POL
29282  *  0b0..Active High.
29283  *  0b1..Active Low.
29284  */
29285 #define DCIC_DCICC_DE_POL(x)                     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK)
29286 
29287 #define DCIC_DCICC_HSYNC_POL_MASK                (0x20U)
29288 #define DCIC_DCICC_HSYNC_POL_SHIFT               (5U)
29289 /*! HSYNC_POL
29290  *  0b0..Active High.
29291  *  0b1..Active Low.
29292  */
29293 #define DCIC_DCICC_HSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK)
29294 
29295 #define DCIC_DCICC_VSYNC_POL_MASK                (0x40U)
29296 #define DCIC_DCICC_VSYNC_POL_SHIFT               (6U)
29297 /*! VSYNC_POL
29298  *  0b0..Active High.
29299  *  0b1..Active Low.
29300  */
29301 #define DCIC_DCICC_VSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK)
29302 
29303 #define DCIC_DCICC_CLK_POL_MASK                  (0x80U)
29304 #define DCIC_DCICC_CLK_POL_SHIFT                 (7U)
29305 /*! CLK_POL
29306  *  0b0..Not inverted (default).
29307  *  0b1..Inverted.
29308  */
29309 #define DCIC_DCICC_CLK_POL(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK)
29310 /*! @} */
29311 
29312 /*! @name DCICIC - DCIC Interrupt Control Register */
29313 /*! @{ */
29314 
29315 #define DCIC_DCICIC_EI_MASK_MASK                 (0x1U)
29316 #define DCIC_DCICIC_EI_MASK_SHIFT                (0U)
29317 /*! EI_MASK
29318  *  0b0..Mask disabled - Interrupt assertion enabled
29319  *  0b1..Mask enabled - Interrupt assertion disabled
29320  */
29321 #define DCIC_DCICIC_EI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK)
29322 
29323 #define DCIC_DCICIC_FI_MASK_MASK                 (0x2U)
29324 #define DCIC_DCICIC_FI_MASK_SHIFT                (1U)
29325 /*! FI_MASK
29326  *  0b0..Mask disabled - Interrupt assertion enabled
29327  *  0b1..Mask enabled - Interrupt assertion disabled
29328  */
29329 #define DCIC_DCICIC_FI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK)
29330 
29331 #define DCIC_DCICIC_FREEZE_MASK_MASK             (0x8U)
29332 #define DCIC_DCICIC_FREEZE_MASK_SHIFT            (3U)
29333 /*! FREEZE_MASK
29334  *  0b0..Masks change allowed
29335  *  0b1..Masks are frozen
29336  */
29337 #define DCIC_DCICIC_FREEZE_MASK(x)               (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK)
29338 
29339 #define DCIC_DCICIC_EXT_SIG_EN_MASK              (0x10000U)
29340 #define DCIC_DCICIC_EXT_SIG_EN_SHIFT             (16U)
29341 /*! EXT_SIG_EN
29342  *  0b0..Disabled
29343  *  0b1..Enabled
29344  */
29345 #define DCIC_DCICIC_EXT_SIG_EN(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK)
29346 /*! @} */
29347 
29348 /*! @name DCICS - DCIC Status Register */
29349 /*! @{ */
29350 
29351 #define DCIC_DCICS_ROI_MATCH_STAT_MASK           (0xFFFFU)
29352 #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT          (0U)
29353 /*! ROI_MATCH_STAT
29354  *  0b0000000000000000..ROI calculated CRC matches expected signature
29355  *  0b0000000000000001..Mismatch at ROI calculated CRC
29356  */
29357 #define DCIC_DCICS_ROI_MATCH_STAT(x)             (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK)
29358 
29359 #define DCIC_DCICS_EI_STAT_MASK                  (0x10000U)
29360 #define DCIC_DCICS_EI_STAT_SHIFT                 (16U)
29361 /*! EI_STAT
29362  *  0b0..No pending Interrupt
29363  *  0b1..Pending Interrupt
29364  */
29365 #define DCIC_DCICS_EI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK)
29366 
29367 #define DCIC_DCICS_FI_STAT_MASK                  (0x20000U)
29368 #define DCIC_DCICS_FI_STAT_SHIFT                 (17U)
29369 /*! FI_STAT
29370  *  0b0..No pending Interrupt
29371  *  0b1..Pending Interrupt
29372  */
29373 #define DCIC_DCICS_FI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK)
29374 /*! @} */
29375 
29376 /*! @name DCICRC - DCIC ROI Config Register */
29377 /*! @{ */
29378 
29379 #define DCIC_DCICRC_START_OFFSET_X_MASK          (0x1FFFU)
29380 #define DCIC_DCICRC_START_OFFSET_X_SHIFT         (0U)
29381 #define DCIC_DCICRC_START_OFFSET_X(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK)
29382 
29383 #define DCIC_DCICRC_START_OFFSET_Y_MASK          (0xFFF0000U)
29384 #define DCIC_DCICRC_START_OFFSET_Y_SHIFT         (16U)
29385 #define DCIC_DCICRC_START_OFFSET_Y(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK)
29386 
29387 #define DCIC_DCICRC_ROI_FREEZE_MASK              (0x40000000U)
29388 #define DCIC_DCICRC_ROI_FREEZE_SHIFT             (30U)
29389 /*! ROI_FREEZE
29390  *  0b0..ROI configuration can be changed
29391  *  0b1..ROI configuration is frozen
29392  */
29393 #define DCIC_DCICRC_ROI_FREEZE(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK)
29394 
29395 #define DCIC_DCICRC_ROI_EN_MASK                  (0x80000000U)
29396 #define DCIC_DCICRC_ROI_EN_SHIFT                 (31U)
29397 /*! ROI_EN
29398  *  0b0..Disabled
29399  *  0b1..Enabled
29400  */
29401 #define DCIC_DCICRC_ROI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK)
29402 /*! @} */
29403 
29404 /* The count of DCIC_DCICRC */
29405 #define DCIC_DCICRC_COUNT                        (16U)
29406 
29407 /*! @name DCICRS - DCIC ROI Size Register */
29408 /*! @{ */
29409 
29410 #define DCIC_DCICRS_END_OFFSET_X_MASK            (0x1FFFU)
29411 #define DCIC_DCICRS_END_OFFSET_X_SHIFT           (0U)
29412 #define DCIC_DCICRS_END_OFFSET_X(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK)
29413 
29414 #define DCIC_DCICRS_END_OFFSET_Y_MASK            (0xFFF0000U)
29415 #define DCIC_DCICRS_END_OFFSET_Y_SHIFT           (16U)
29416 #define DCIC_DCICRS_END_OFFSET_Y(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK)
29417 /*! @} */
29418 
29419 /* The count of DCIC_DCICRS */
29420 #define DCIC_DCICRS_COUNT                        (16U)
29421 
29422 /*! @name DCICRRS - DCIC ROI Reference Signature Register */
29423 /*! @{ */
29424 
29425 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK    (0xFFFFFFFFU)
29426 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT   (0U)
29427 #define DCIC_DCICRRS_REFERENCE_SIGNATURE(x)      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
29428 /*! @} */
29429 
29430 /* The count of DCIC_DCICRRS */
29431 #define DCIC_DCICRRS_COUNT                       (16U)
29432 
29433 /*! @name DCICRCS - DCIC ROI Calculated Signature Register */
29434 /*! @{ */
29435 
29436 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK   (0xFFFFFFFFU)
29437 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT  (0U)
29438 #define DCIC_DCICRCS_CALCULATED_SIGNATURE(x)     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
29439 /*! @} */
29440 
29441 /* The count of DCIC_DCICRCS */
29442 #define DCIC_DCICRCS_COUNT                       (16U)
29443 
29444 
29445 /*!
29446  * @}
29447  */ /* end of group DCIC_Register_Masks */
29448 
29449 
29450 /* DCIC - Peripheral instance base addresses */
29451 /** Peripheral DCIC1 base address */
29452 #define DCIC1_BASE                               (0x40819000u)
29453 /** Peripheral DCIC1 base pointer */
29454 #define DCIC1                                    ((DCIC_Type *)DCIC1_BASE)
29455 /** Peripheral DCIC2 base address */
29456 #define DCIC2_BASE                               (0x4081A000u)
29457 /** Peripheral DCIC2 base pointer */
29458 #define DCIC2                                    ((DCIC_Type *)DCIC2_BASE)
29459 /** Array initializer of DCIC peripheral base addresses */
29460 #define DCIC_BASE_ADDRS                          { 0u, DCIC1_BASE, DCIC2_BASE }
29461 /** Array initializer of DCIC peripheral base pointers */
29462 #define DCIC_BASE_PTRS                           { (DCIC_Type *)0u, DCIC1, DCIC2 }
29463 
29464 /*!
29465  * @}
29466  */ /* end of group DCIC_Peripheral_Access_Layer */
29467 
29468 
29469 /* ----------------------------------------------------------------------------
29470    -- DMA Peripheral Access Layer
29471    ---------------------------------------------------------------------------- */
29472 
29473 /*!
29474  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
29475  * @{
29476  */
29477 
29478 /** DMA - Register Layout Typedef */
29479 typedef struct {
29480   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
29481   __I  uint32_t ES;                                /**< Error Status, offset: 0x4 */
29482        uint8_t RESERVED_0[4];
29483   __IO uint32_t ERQ;                               /**< Enable Request, offset: 0xC */
29484        uint8_t RESERVED_1[4];
29485   __IO uint32_t EEI;                               /**< Enable Error Interrupt, offset: 0x14 */
29486   __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt, offset: 0x18 */
29487   __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt, offset: 0x19 */
29488   __O  uint8_t CERQ;                               /**< Clear Enable Request, offset: 0x1A */
29489   __O  uint8_t SERQ;                               /**< Set Enable Request, offset: 0x1B */
29490   __O  uint8_t CDNE;                               /**< Clear DONE Status Bit, offset: 0x1C */
29491   __O  uint8_t SSRT;                               /**< Set START Bit, offset: 0x1D */
29492   __O  uint8_t CERR;                               /**< Clear Error, offset: 0x1E */
29493   __O  uint8_t CINT;                               /**< Clear Interrupt Request, offset: 0x1F */
29494        uint8_t RESERVED_2[4];
29495   __IO uint32_t INT;                               /**< Interrupt Request, offset: 0x24 */
29496        uint8_t RESERVED_3[4];
29497   __IO uint32_t ERR;                               /**< Error, offset: 0x2C */
29498        uint8_t RESERVED_4[4];
29499   __I  uint32_t HRS;                               /**< Hardware Request Status, offset: 0x34 */
29500        uint8_t RESERVED_5[12];
29501   __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop, offset: 0x44 */
29502        uint8_t RESERVED_6[184];
29503   __IO uint8_t DCHPRI3;                            /**< Channel Priority, offset: 0x100 */
29504   __IO uint8_t DCHPRI2;                            /**< Channel Priority, offset: 0x101 */
29505   __IO uint8_t DCHPRI1;                            /**< Channel Priority, offset: 0x102 */
29506   __IO uint8_t DCHPRI0;                            /**< Channel Priority, offset: 0x103 */
29507   __IO uint8_t DCHPRI7;                            /**< Channel Priority, offset: 0x104 */
29508   __IO uint8_t DCHPRI6;                            /**< Channel Priority, offset: 0x105 */
29509   __IO uint8_t DCHPRI5;                            /**< Channel Priority, offset: 0x106 */
29510   __IO uint8_t DCHPRI4;                            /**< Channel Priority, offset: 0x107 */
29511   __IO uint8_t DCHPRI11;                           /**< Channel Priority, offset: 0x108 */
29512   __IO uint8_t DCHPRI10;                           /**< Channel Priority, offset: 0x109 */
29513   __IO uint8_t DCHPRI9;                            /**< Channel Priority, offset: 0x10A */
29514   __IO uint8_t DCHPRI8;                            /**< Channel Priority, offset: 0x10B */
29515   __IO uint8_t DCHPRI15;                           /**< Channel Priority, offset: 0x10C */
29516   __IO uint8_t DCHPRI14;                           /**< Channel Priority, offset: 0x10D */
29517   __IO uint8_t DCHPRI13;                           /**< Channel Priority, offset: 0x10E */
29518   __IO uint8_t DCHPRI12;                           /**< Channel Priority, offset: 0x10F */
29519   __IO uint8_t DCHPRI19;                           /**< Channel Priority, offset: 0x110 */
29520   __IO uint8_t DCHPRI18;                           /**< Channel Priority, offset: 0x111 */
29521   __IO uint8_t DCHPRI17;                           /**< Channel Priority, offset: 0x112 */
29522   __IO uint8_t DCHPRI16;                           /**< Channel Priority, offset: 0x113 */
29523   __IO uint8_t DCHPRI23;                           /**< Channel Priority, offset: 0x114 */
29524   __IO uint8_t DCHPRI22;                           /**< Channel Priority, offset: 0x115 */
29525   __IO uint8_t DCHPRI21;                           /**< Channel Priority, offset: 0x116 */
29526   __IO uint8_t DCHPRI20;                           /**< Channel Priority, offset: 0x117 */
29527   __IO uint8_t DCHPRI27;                           /**< Channel Priority, offset: 0x118 */
29528   __IO uint8_t DCHPRI26;                           /**< Channel Priority, offset: 0x119 */
29529   __IO uint8_t DCHPRI25;                           /**< Channel Priority, offset: 0x11A */
29530   __IO uint8_t DCHPRI24;                           /**< Channel Priority, offset: 0x11B */
29531   __IO uint8_t DCHPRI31;                           /**< Channel Priority, offset: 0x11C */
29532   __IO uint8_t DCHPRI30;                           /**< Channel Priority, offset: 0x11D */
29533   __IO uint8_t DCHPRI29;                           /**< Channel Priority, offset: 0x11E */
29534   __IO uint8_t DCHPRI28;                           /**< Channel Priority, offset: 0x11F */
29535        uint8_t RESERVED_7[3808];
29536   struct {                                         /* offset: 0x1000, array step: 0x20 */
29537     __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
29538     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
29539     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
29540     union {                                          /* offset: 0x1008, array step: 0x20 */
29541       __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
29542       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
29543       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
29544     };
29545     __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
29546     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
29547     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
29548     union {                                          /* offset: 0x1016, array step: 0x20 */
29549       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
29550       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
29551     };
29552     __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
29553     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
29554     union {                                          /* offset: 0x101E, array step: 0x20 */
29555       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
29556       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
29557     };
29558   } TCD[32];
29559 } DMA_Type;
29560 
29561 /* ----------------------------------------------------------------------------
29562    -- DMA Register Masks
29563    ---------------------------------------------------------------------------- */
29564 
29565 /*!
29566  * @addtogroup DMA_Register_Masks DMA Register Masks
29567  * @{
29568  */
29569 
29570 /*! @name CR - Control */
29571 /*! @{ */
29572 
29573 #define DMA_CR_EDBG_MASK                         (0x2U)
29574 #define DMA_CR_EDBG_SHIFT                        (1U)
29575 /*! EDBG - Enable Debug
29576  *  0b0..When the chip is in Debug mode, the eDMA continues to operate.
29577  *  0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.
29578  */
29579 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
29580 
29581 #define DMA_CR_ERCA_MASK                         (0x4U)
29582 #define DMA_CR_ERCA_SHIFT                        (2U)
29583 /*! ERCA - Enable Round Robin Channel Arbitration
29584  *  0b0..Fixed priority arbitration within each group
29585  *  0b1..Round robin arbitration within each group
29586  */
29587 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
29588 
29589 #define DMA_CR_ERGA_MASK                         (0x8U)
29590 #define DMA_CR_ERGA_SHIFT                        (3U)
29591 /*! ERGA - Enable Round Robin Group Arbitration
29592  *  0b0..Fixed priority arbitration
29593  *  0b1..Round robin arbitration
29594  */
29595 #define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
29596 
29597 #define DMA_CR_HOE_MASK                          (0x10U)
29598 #define DMA_CR_HOE_SHIFT                         (4U)
29599 /*! HOE - Halt On Error
29600  *  0b0..Normal operation
29601  *  0b1..Error causes HALT field to be automatically set to 1
29602  */
29603 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
29604 
29605 #define DMA_CR_HALT_MASK                         (0x20U)
29606 #define DMA_CR_HALT_SHIFT                        (5U)
29607 /*! HALT - Halt eDMA Operations
29608  *  0b0..Normal operation
29609  *  0b1..eDMA operations halted
29610  */
29611 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
29612 
29613 #define DMA_CR_CLM_MASK                          (0x40U)
29614 #define DMA_CR_CLM_SHIFT                         (6U)
29615 /*! CLM - Continuous Link Mode
29616  *  0b0..Continuous link mode is off
29617  *  0b1..Continuous link mode is on
29618  */
29619 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
29620 
29621 #define DMA_CR_EMLM_MASK                         (0x80U)
29622 #define DMA_CR_EMLM_SHIFT                        (7U)
29623 /*! EMLM - Enable Minor Loop Mapping
29624  *  0b0..Disabled
29625  *  0b1..Enabled
29626  */
29627 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
29628 
29629 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
29630 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
29631 /*! GRP0PRI - Channel Group 0 Priority
29632  */
29633 #define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
29634 
29635 #define DMA_CR_GRP1PRI_MASK                      (0x400U)
29636 #define DMA_CR_GRP1PRI_SHIFT                     (10U)
29637 /*! GRP1PRI - Channel Group 1 Priority
29638  */
29639 #define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
29640 
29641 #define DMA_CR_ECX_MASK                          (0x10000U)
29642 #define DMA_CR_ECX_SHIFT                         (16U)
29643 /*! ECX - Error Cancel Transfer
29644  *  0b0..Normal operation
29645  *  0b1..Cancel the remaining data transfer
29646  */
29647 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
29648 
29649 #define DMA_CR_CX_MASK                           (0x20000U)
29650 #define DMA_CR_CX_SHIFT                          (17U)
29651 /*! CX - Cancel Transfer
29652  *  0b0..Normal operation
29653  *  0b1..Cancel the remaining data transfer
29654  */
29655 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
29656 
29657 #define DMA_CR_VERSION_MASK                      (0x7F000000U)
29658 #define DMA_CR_VERSION_SHIFT                     (24U)
29659 /*! VERSION - eDMA version number
29660  */
29661 #define DMA_CR_VERSION(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
29662 
29663 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
29664 #define DMA_CR_ACTIVE_SHIFT                      (31U)
29665 /*! ACTIVE - eDMA Active Status
29666  *  0b0..eDMA is idle
29667  *  0b1..eDMA is executing a channel
29668  */
29669 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
29670 /*! @} */
29671 
29672 /*! @name ES - Error Status */
29673 /*! @{ */
29674 
29675 #define DMA_ES_DBE_MASK                          (0x1U)
29676 #define DMA_ES_DBE_SHIFT                         (0U)
29677 /*! DBE - Destination Bus Error
29678  *  0b0..No destination bus error.
29679  *  0b1..The most-recently recorded error was a bus error on a destination write.
29680  */
29681 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
29682 
29683 #define DMA_ES_SBE_MASK                          (0x2U)
29684 #define DMA_ES_SBE_SHIFT                         (1U)
29685 /*! SBE - Source Bus Error
29686  *  0b0..No source bus error.
29687  *  0b1..The most-recently recorded error was a bus error on a source read.
29688  */
29689 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
29690 
29691 #define DMA_ES_SGE_MASK                          (0x4U)
29692 #define DMA_ES_SGE_SHIFT                         (2U)
29693 /*! SGE - Scatter/Gather Configuration Error
29694  *  0b0..No scatter/gather configuration error.
29695  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
29696  */
29697 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
29698 
29699 #define DMA_ES_NCE_MASK                          (0x8U)
29700 #define DMA_ES_NCE_SHIFT                         (3U)
29701 /*! NCE - NBYTES/CITER Configuration Error
29702  *  0b0..No NBYTES/CITER configuration error.
29703  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
29704  *       fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or
29705  *       TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
29706  */
29707 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
29708 
29709 #define DMA_ES_DOE_MASK                          (0x10U)
29710 #define DMA_ES_DOE_SHIFT                         (4U)
29711 /*! DOE - Destination Offset Error
29712  *  0b0..No destination offset configuration error.
29713  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
29714  */
29715 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
29716 
29717 #define DMA_ES_DAE_MASK                          (0x20U)
29718 #define DMA_ES_DAE_SHIFT                         (5U)
29719 /*! DAE - Destination Address Error
29720  *  0b0..No destination address configuration error.
29721  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
29722  *       is inconsistent with TCDn_ATTR[DSIZE].
29723  */
29724 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
29725 
29726 #define DMA_ES_SOE_MASK                          (0x40U)
29727 #define DMA_ES_SOE_SHIFT                         (6U)
29728 /*! SOE - Source Offset Error
29729  *  0b0..No source offset configuration error.
29730  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
29731  */
29732 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
29733 
29734 #define DMA_ES_SAE_MASK                          (0x80U)
29735 #define DMA_ES_SAE_SHIFT                         (7U)
29736 /*! SAE - Source Address Error
29737  *  0b0..No source address configuration error.
29738  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
29739  *       is inconsistent with TCDn_ATTR[SSIZE].
29740  */
29741 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
29742 
29743 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
29744 #define DMA_ES_ERRCHN_SHIFT                      (8U)
29745 /*! ERRCHN - Error Channel Number or Canceled Channel Number
29746  */
29747 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
29748 
29749 #define DMA_ES_CPE_MASK                          (0x4000U)
29750 #define DMA_ES_CPE_SHIFT                         (14U)
29751 /*! CPE - Channel Priority Error
29752  *  0b0..No channel priority error.
29753  *  0b1..The most-recently recorded error was a configuration error in the channel priorities within a group.
29754  *       Channel priorities within a group are not unique.
29755  */
29756 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
29757 
29758 #define DMA_ES_GPE_MASK                          (0x8000U)
29759 #define DMA_ES_GPE_SHIFT                         (15U)
29760 /*! GPE - Group Priority Error
29761  *  0b0..No group priority error.
29762  *  0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.
29763  */
29764 #define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
29765 
29766 #define DMA_ES_ECX_MASK                          (0x10000U)
29767 #define DMA_ES_ECX_SHIFT                         (16U)
29768 /*! ECX - Transfer Canceled
29769  *  0b0..No canceled transfers
29770  *  0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
29771  */
29772 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
29773 
29774 #define DMA_ES_VLD_MASK                          (0x80000000U)
29775 #define DMA_ES_VLD_SHIFT                         (31U)
29776 /*! VLD - Logical OR of all ERR status fields
29777  *  0b0..No ERR fields are 1
29778  *  0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
29779  */
29780 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
29781 /*! @} */
29782 
29783 /*! @name ERQ - Enable Request */
29784 /*! @{ */
29785 
29786 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
29787 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
29788 /*! ERQ0 - Enable DMA Request 0
29789  *  0b0..The DMA request signal for channel 0 is disabled
29790  *  0b1..The DMA request signal for channel 0 is enabled
29791  */
29792 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
29793 
29794 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
29795 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
29796 /*! ERQ1 - Enable DMA Request 1
29797  *  0b0..The DMA request signal for channel 1 is disabled
29798  *  0b1..The DMA request signal for channel 1 is enabled
29799  */
29800 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
29801 
29802 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
29803 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
29804 /*! ERQ2 - Enable DMA Request 2
29805  *  0b0..The DMA request signal for channel 2 is disabled
29806  *  0b1..The DMA request signal for channel 2 is enabled
29807  */
29808 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
29809 
29810 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
29811 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
29812 /*! ERQ3 - Enable DMA Request 3
29813  *  0b0..The DMA request signal for channel 3 is disabled
29814  *  0b1..The DMA request signal for channel 3 is enabled
29815  */
29816 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
29817 
29818 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
29819 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
29820 /*! ERQ4 - Enable DMA Request 4
29821  *  0b0..The DMA request signal for channel 4 is disabled
29822  *  0b1..The DMA request signal for channel 4 is enabled
29823  */
29824 #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
29825 
29826 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
29827 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
29828 /*! ERQ5 - Enable DMA Request 5
29829  *  0b0..The DMA request signal for channel 5 is disabled
29830  *  0b1..The DMA request signal for channel 5 is enabled
29831  */
29832 #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
29833 
29834 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
29835 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
29836 /*! ERQ6 - Enable DMA Request 6
29837  *  0b0..The DMA request signal for channel 6 is disabled
29838  *  0b1..The DMA request signal for channel 6 is enabled
29839  */
29840 #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
29841 
29842 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
29843 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
29844 /*! ERQ7 - Enable DMA Request 7
29845  *  0b0..The DMA request signal for channel 7 is disabled
29846  *  0b1..The DMA request signal for channel 7 is enabled
29847  */
29848 #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
29849 
29850 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
29851 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
29852 /*! ERQ8 - Enable DMA Request 8
29853  *  0b0..The DMA request signal for channel 8 is disabled
29854  *  0b1..The DMA request signal for channel 8 is enabled
29855  */
29856 #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
29857 
29858 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
29859 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
29860 /*! ERQ9 - Enable DMA Request 9
29861  *  0b0..The DMA request signal for channel 9 is disabled
29862  *  0b1..The DMA request signal for channel 9 is enabled
29863  */
29864 #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
29865 
29866 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
29867 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
29868 /*! ERQ10 - Enable DMA Request 10
29869  *  0b0..The DMA request signal for channel 10 is disabled
29870  *  0b1..The DMA request signal for channel 10 is enabled
29871  */
29872 #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
29873 
29874 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
29875 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
29876 /*! ERQ11 - Enable DMA Request 11
29877  *  0b0..The DMA request signal for channel 11 is disabled
29878  *  0b1..The DMA request signal for channel 11 is enabled
29879  */
29880 #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
29881 
29882 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
29883 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
29884 /*! ERQ12 - Enable DMA Request 12
29885  *  0b0..The DMA request signal for channel 12 is disabled
29886  *  0b1..The DMA request signal for channel 12 is enabled
29887  */
29888 #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
29889 
29890 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
29891 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
29892 /*! ERQ13 - Enable DMA Request 13
29893  *  0b0..The DMA request signal for channel 13 is disabled
29894  *  0b1..The DMA request signal for channel 13 is enabled
29895  */
29896 #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
29897 
29898 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
29899 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
29900 /*! ERQ14 - Enable DMA Request 14
29901  *  0b0..The DMA request signal for channel 14 is disabled
29902  *  0b1..The DMA request signal for channel 14 is enabled
29903  */
29904 #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
29905 
29906 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
29907 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
29908 /*! ERQ15 - Enable DMA Request 15
29909  *  0b0..The DMA request signal for channel 15 is disabled
29910  *  0b1..The DMA request signal for channel 15 is enabled
29911  */
29912 #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
29913 
29914 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
29915 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
29916 /*! ERQ16 - Enable DMA Request 16
29917  *  0b0..The DMA request signal for channel 16 is disabled
29918  *  0b1..The DMA request signal for channel 16 is enabled
29919  */
29920 #define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
29921 
29922 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
29923 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
29924 /*! ERQ17 - Enable DMA Request 17
29925  *  0b0..The DMA request signal for channel 17 is disabled
29926  *  0b1..The DMA request signal for channel 17 is enabled
29927  */
29928 #define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
29929 
29930 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
29931 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
29932 /*! ERQ18 - Enable DMA Request 18
29933  *  0b0..The DMA request signal for channel 18 is disabled
29934  *  0b1..The DMA request signal for channel 18 is enabled
29935  */
29936 #define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
29937 
29938 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
29939 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
29940 /*! ERQ19 - Enable DMA Request 19
29941  *  0b0..The DMA request signal for channel 19 is disabled
29942  *  0b1..The DMA request signal for channel 19 is enabled
29943  */
29944 #define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
29945 
29946 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
29947 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
29948 /*! ERQ20 - Enable DMA Request 20
29949  *  0b0..The DMA request signal for channel 20 is disabled
29950  *  0b1..The DMA request signal for channel 20 is enabled
29951  */
29952 #define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
29953 
29954 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
29955 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
29956 /*! ERQ21 - Enable DMA Request 21
29957  *  0b0..The DMA request signal for channel 21 is disabled
29958  *  0b1..The DMA request signal for channel 21 is enabled
29959  */
29960 #define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
29961 
29962 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
29963 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
29964 /*! ERQ22 - Enable DMA Request 22
29965  *  0b0..The DMA request signal for channel 22 is disabled
29966  *  0b1..The DMA request signal for channel 22 is enabled
29967  */
29968 #define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
29969 
29970 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
29971 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
29972 /*! ERQ23 - Enable DMA Request 23
29973  *  0b0..The DMA request signal for channel 23 is disabled
29974  *  0b1..The DMA request signal for channel 23 is enabled
29975  */
29976 #define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
29977 
29978 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
29979 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
29980 /*! ERQ24 - Enable DMA Request 24
29981  *  0b0..The DMA request signal for channel 24 is disabled
29982  *  0b1..The DMA request signal for channel 24 is enabled
29983  */
29984 #define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
29985 
29986 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
29987 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
29988 /*! ERQ25 - Enable DMA Request 25
29989  *  0b0..The DMA request signal for channel 25 is disabled
29990  *  0b1..The DMA request signal for channel 25 is enabled
29991  */
29992 #define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
29993 
29994 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
29995 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
29996 /*! ERQ26 - Enable DMA Request 26
29997  *  0b0..The DMA request signal for channel 26 is disabled
29998  *  0b1..The DMA request signal for channel 26 is enabled
29999  */
30000 #define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
30001 
30002 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
30003 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
30004 /*! ERQ27 - Enable DMA Request 27
30005  *  0b0..The DMA request signal for channel 27 is disabled
30006  *  0b1..The DMA request signal for channel 27 is enabled
30007  */
30008 #define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
30009 
30010 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
30011 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
30012 /*! ERQ28 - Enable DMA Request 28
30013  *  0b0..The DMA request signal for channel 28 is disabled
30014  *  0b1..The DMA request signal for channel 28 is enabled
30015  */
30016 #define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
30017 
30018 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
30019 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
30020 /*! ERQ29 - Enable DMA Request 29
30021  *  0b0..The DMA request signal for channel 29 is disabled
30022  *  0b1..The DMA request signal for channel 29 is enabled
30023  */
30024 #define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
30025 
30026 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
30027 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
30028 /*! ERQ30 - Enable DMA Request 30
30029  *  0b0..The DMA request signal for channel 30 is disabled
30030  *  0b1..The DMA request signal for channel 30 is enabled
30031  */
30032 #define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
30033 
30034 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
30035 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
30036 /*! ERQ31 - Enable DMA Request 31
30037  *  0b0..The DMA request signal for channel 31 is disabled
30038  *  0b1..The DMA request signal for channel 31 is enabled
30039  */
30040 #define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
30041 /*! @} */
30042 
30043 /*! @name EEI - Enable Error Interrupt */
30044 /*! @{ */
30045 
30046 #define DMA_EEI_EEI0_MASK                        (0x1U)
30047 #define DMA_EEI_EEI0_SHIFT                       (0U)
30048 /*! EEI0 - Enable Error Interrupt 0
30049  *  0b0..An error on channel 0 does not generate an error interrupt
30050  *  0b1..An error on channel 0 generates an error interrupt request
30051  */
30052 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
30053 
30054 #define DMA_EEI_EEI1_MASK                        (0x2U)
30055 #define DMA_EEI_EEI1_SHIFT                       (1U)
30056 /*! EEI1 - Enable Error Interrupt 1
30057  *  0b0..An error on channel 1 does not generate an error interrupt
30058  *  0b1..An error on channel 1 generates an error interrupt request
30059  */
30060 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
30061 
30062 #define DMA_EEI_EEI2_MASK                        (0x4U)
30063 #define DMA_EEI_EEI2_SHIFT                       (2U)
30064 /*! EEI2 - Enable Error Interrupt 2
30065  *  0b0..An error on channel 2 does not generate an error interrupt
30066  *  0b1..An error on channel 2 generates an error interrupt request
30067  */
30068 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
30069 
30070 #define DMA_EEI_EEI3_MASK                        (0x8U)
30071 #define DMA_EEI_EEI3_SHIFT                       (3U)
30072 /*! EEI3 - Enable Error Interrupt 3
30073  *  0b0..An error on channel 3 does not generate an error interrupt
30074  *  0b1..An error on channel 3 generates an error interrupt request
30075  */
30076 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
30077 
30078 #define DMA_EEI_EEI4_MASK                        (0x10U)
30079 #define DMA_EEI_EEI4_SHIFT                       (4U)
30080 /*! EEI4 - Enable Error Interrupt 4
30081  *  0b0..An error on channel 4 does not generate an error interrupt
30082  *  0b1..An error on channel 4 generates an error interrupt request
30083  */
30084 #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
30085 
30086 #define DMA_EEI_EEI5_MASK                        (0x20U)
30087 #define DMA_EEI_EEI5_SHIFT                       (5U)
30088 /*! EEI5 - Enable Error Interrupt 5
30089  *  0b0..An error on channel 5 does not generate an error interrupt
30090  *  0b1..An error on channel 5 generates an error interrupt request
30091  */
30092 #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
30093 
30094 #define DMA_EEI_EEI6_MASK                        (0x40U)
30095 #define DMA_EEI_EEI6_SHIFT                       (6U)
30096 /*! EEI6 - Enable Error Interrupt 6
30097  *  0b0..An error on channel 6 does not generate an error interrupt
30098  *  0b1..An error on channel 6 generates an error interrupt request
30099  */
30100 #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
30101 
30102 #define DMA_EEI_EEI7_MASK                        (0x80U)
30103 #define DMA_EEI_EEI7_SHIFT                       (7U)
30104 /*! EEI7 - Enable Error Interrupt 7
30105  *  0b0..An error on channel 7 does not generate an error interrupt
30106  *  0b1..An error on channel 7 generates an error interrupt request
30107  */
30108 #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
30109 
30110 #define DMA_EEI_EEI8_MASK                        (0x100U)
30111 #define DMA_EEI_EEI8_SHIFT                       (8U)
30112 /*! EEI8 - Enable Error Interrupt 8
30113  *  0b0..An error on channel 8 does not generate an error interrupt
30114  *  0b1..An error on channel 8 generates an error interrupt request
30115  */
30116 #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
30117 
30118 #define DMA_EEI_EEI9_MASK                        (0x200U)
30119 #define DMA_EEI_EEI9_SHIFT                       (9U)
30120 /*! EEI9 - Enable Error Interrupt 9
30121  *  0b0..An error on channel 9 does not generate an error interrupt
30122  *  0b1..An error on channel 9 generates an error interrupt request
30123  */
30124 #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
30125 
30126 #define DMA_EEI_EEI10_MASK                       (0x400U)
30127 #define DMA_EEI_EEI10_SHIFT                      (10U)
30128 /*! EEI10 - Enable Error Interrupt 10
30129  *  0b0..An error on channel 10 does not generate an error interrupt
30130  *  0b1..An error on channel 10 generates an error interrupt request
30131  */
30132 #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
30133 
30134 #define DMA_EEI_EEI11_MASK                       (0x800U)
30135 #define DMA_EEI_EEI11_SHIFT                      (11U)
30136 /*! EEI11 - Enable Error Interrupt 11
30137  *  0b0..An error on channel 11 does not generate an error interrupt
30138  *  0b1..An error on channel 11 generates an error interrupt request
30139  */
30140 #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
30141 
30142 #define DMA_EEI_EEI12_MASK                       (0x1000U)
30143 #define DMA_EEI_EEI12_SHIFT                      (12U)
30144 /*! EEI12 - Enable Error Interrupt 12
30145  *  0b0..An error on channel 12 does not generate an error interrupt
30146  *  0b1..An error on channel 12 generates an error interrupt request
30147  */
30148 #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
30149 
30150 #define DMA_EEI_EEI13_MASK                       (0x2000U)
30151 #define DMA_EEI_EEI13_SHIFT                      (13U)
30152 /*! EEI13 - Enable Error Interrupt 13
30153  *  0b0..An error on channel 13 does not generate an error interrupt
30154  *  0b1..An error on channel 13 generates an error interrupt request
30155  */
30156 #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
30157 
30158 #define DMA_EEI_EEI14_MASK                       (0x4000U)
30159 #define DMA_EEI_EEI14_SHIFT                      (14U)
30160 /*! EEI14 - Enable Error Interrupt 14
30161  *  0b0..An error on channel 14 does not generate an error interrupt
30162  *  0b1..An error on channel 14 generates an error interrupt request
30163  */
30164 #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
30165 
30166 #define DMA_EEI_EEI15_MASK                       (0x8000U)
30167 #define DMA_EEI_EEI15_SHIFT                      (15U)
30168 /*! EEI15 - Enable Error Interrupt 15
30169  *  0b0..An error on channel 15 does not generate an error interrupt
30170  *  0b1..An error on channel 15 generates an error interrupt request
30171  */
30172 #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
30173 
30174 #define DMA_EEI_EEI16_MASK                       (0x10000U)
30175 #define DMA_EEI_EEI16_SHIFT                      (16U)
30176 /*! EEI16 - Enable Error Interrupt 16
30177  *  0b0..An error on channel 16 does not generate an error interrupt
30178  *  0b1..An error on channel 16 generates an error interrupt request
30179  */
30180 #define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
30181 
30182 #define DMA_EEI_EEI17_MASK                       (0x20000U)
30183 #define DMA_EEI_EEI17_SHIFT                      (17U)
30184 /*! EEI17 - Enable Error Interrupt 17
30185  *  0b0..An error on channel 17 does not generate an error interrupt
30186  *  0b1..An error on channel 17 generates an error interrupt request
30187  */
30188 #define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
30189 
30190 #define DMA_EEI_EEI18_MASK                       (0x40000U)
30191 #define DMA_EEI_EEI18_SHIFT                      (18U)
30192 /*! EEI18 - Enable Error Interrupt 18
30193  *  0b0..An error on channel 18 does not generate an error interrupt
30194  *  0b1..An error on channel 18 generates an error interrupt request
30195  */
30196 #define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
30197 
30198 #define DMA_EEI_EEI19_MASK                       (0x80000U)
30199 #define DMA_EEI_EEI19_SHIFT                      (19U)
30200 /*! EEI19 - Enable Error Interrupt 19
30201  *  0b0..An error on channel 19 does not generate an error interrupt
30202  *  0b1..An error on channel 19 generates an error interrupt request
30203  */
30204 #define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
30205 
30206 #define DMA_EEI_EEI20_MASK                       (0x100000U)
30207 #define DMA_EEI_EEI20_SHIFT                      (20U)
30208 /*! EEI20 - Enable Error Interrupt 20
30209  *  0b0..An error on channel 20 does not generate an error interrupt
30210  *  0b1..An error on channel 20 generates an error interrupt request
30211  */
30212 #define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
30213 
30214 #define DMA_EEI_EEI21_MASK                       (0x200000U)
30215 #define DMA_EEI_EEI21_SHIFT                      (21U)
30216 /*! EEI21 - Enable Error Interrupt 21
30217  *  0b0..An error on channel 21 does not generate an error interrupt
30218  *  0b1..An error on channel 21 generates an error interrupt request
30219  */
30220 #define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
30221 
30222 #define DMA_EEI_EEI22_MASK                       (0x400000U)
30223 #define DMA_EEI_EEI22_SHIFT                      (22U)
30224 /*! EEI22 - Enable Error Interrupt 22
30225  *  0b0..An error on channel 22 does not generate an error interrupt
30226  *  0b1..An error on channel 22 generates an error interrupt request
30227  */
30228 #define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
30229 
30230 #define DMA_EEI_EEI23_MASK                       (0x800000U)
30231 #define DMA_EEI_EEI23_SHIFT                      (23U)
30232 /*! EEI23 - Enable Error Interrupt 23
30233  *  0b0..An error on channel 23 does not generate an error interrupt
30234  *  0b1..An error on channel 23 generates an error interrupt request
30235  */
30236 #define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
30237 
30238 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
30239 #define DMA_EEI_EEI24_SHIFT                      (24U)
30240 /*! EEI24 - Enable Error Interrupt 24
30241  *  0b0..An error on channel 24 does not generate an error interrupt
30242  *  0b1..An error on channel 24 generates an error interrupt request
30243  */
30244 #define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
30245 
30246 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
30247 #define DMA_EEI_EEI25_SHIFT                      (25U)
30248 /*! EEI25 - Enable Error Interrupt 25
30249  *  0b0..An error on channel 25 does not generate an error interrupt
30250  *  0b1..An error on channel 25 generates an error interrupt request
30251  */
30252 #define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
30253 
30254 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
30255 #define DMA_EEI_EEI26_SHIFT                      (26U)
30256 /*! EEI26 - Enable Error Interrupt 26
30257  *  0b0..An error on channel 26 does not generate an error interrupt
30258  *  0b1..An error on channel 26 generates an error interrupt request
30259  */
30260 #define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
30261 
30262 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
30263 #define DMA_EEI_EEI27_SHIFT                      (27U)
30264 /*! EEI27 - Enable Error Interrupt 27
30265  *  0b0..An error on channel 27 does not generate an error interrupt
30266  *  0b1..An error on channel 27 generates an error interrupt request
30267  */
30268 #define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
30269 
30270 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
30271 #define DMA_EEI_EEI28_SHIFT                      (28U)
30272 /*! EEI28 - Enable Error Interrupt 28
30273  *  0b0..An error on channel 28 does not generate an error interrupt
30274  *  0b1..An error on channel 28 generates an error interrupt request
30275  */
30276 #define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
30277 
30278 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
30279 #define DMA_EEI_EEI29_SHIFT                      (29U)
30280 /*! EEI29 - Enable Error Interrupt 29
30281  *  0b0..An error on channel 29 does not generate an error interrupt
30282  *  0b1..An error on channel 29 generates an error interrupt request
30283  */
30284 #define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
30285 
30286 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
30287 #define DMA_EEI_EEI30_SHIFT                      (30U)
30288 /*! EEI30 - Enable Error Interrupt 30
30289  *  0b0..An error on channel 30 does not generate an error interrupt
30290  *  0b1..An error on channel 30 generates an error interrupt request
30291  */
30292 #define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
30293 
30294 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
30295 #define DMA_EEI_EEI31_SHIFT                      (31U)
30296 /*! EEI31 - Enable Error Interrupt 31
30297  *  0b0..An error on channel 31 does not generate an error interrupt
30298  *  0b1..An error on channel 31 generates an error interrupt request
30299  */
30300 #define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
30301 /*! @} */
30302 
30303 /*! @name CEEI - Clear Enable Error Interrupt */
30304 /*! @{ */
30305 
30306 #define DMA_CEEI_CEEI_MASK                       (0x1FU)
30307 #define DMA_CEEI_CEEI_SHIFT                      (0U)
30308 /*! CEEI - Clear Enable Error Interrupt
30309  */
30310 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
30311 
30312 #define DMA_CEEI_CAEE_MASK                       (0x40U)
30313 #define DMA_CEEI_CAEE_SHIFT                      (6U)
30314 /*! CAEE - Clear All Enable Error Interrupts
30315  *  0b0..Write 0 only to the EEI field specified in the CEEI field
30316  *  0b1..Write 0 to all fields in EEI
30317  */
30318 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
30319 
30320 #define DMA_CEEI_NOP_MASK                        (0x80U)
30321 #define DMA_CEEI_NOP_SHIFT                       (7U)
30322 /*! NOP - No Op Enable
30323  *  0b0..Normal operation
30324  *  0b1..No operation, ignore the other fields in this register
30325  */
30326 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
30327 /*! @} */
30328 
30329 /*! @name SEEI - Set Enable Error Interrupt */
30330 /*! @{ */
30331 
30332 #define DMA_SEEI_SEEI_MASK                       (0x1FU)
30333 #define DMA_SEEI_SEEI_SHIFT                      (0U)
30334 /*! SEEI - Set Enable Error Interrupt
30335  */
30336 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
30337 
30338 #define DMA_SEEI_SAEE_MASK                       (0x40U)
30339 #define DMA_SEEI_SAEE_SHIFT                      (6U)
30340 /*! SAEE - Set All Enable Error Interrupts
30341  *  0b0..Write 1 only to the EEI field specified in the SEEI field
30342  *  0b1..Writes 1 to all fields in EEI
30343  */
30344 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
30345 
30346 #define DMA_SEEI_NOP_MASK                        (0x80U)
30347 #define DMA_SEEI_NOP_SHIFT                       (7U)
30348 /*! NOP - No Op Enable
30349  *  0b0..Normal operation
30350  *  0b1..No operation, ignore the other fields in this register
30351  */
30352 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
30353 /*! @} */
30354 
30355 /*! @name CERQ - Clear Enable Request */
30356 /*! @{ */
30357 
30358 #define DMA_CERQ_CERQ_MASK                       (0x1FU)
30359 #define DMA_CERQ_CERQ_SHIFT                      (0U)
30360 /*! CERQ - Clear Enable Request
30361  */
30362 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
30363 
30364 #define DMA_CERQ_CAER_MASK                       (0x40U)
30365 #define DMA_CERQ_CAER_SHIFT                      (6U)
30366 /*! CAER - Clear All Enable Requests
30367  *  0b0..Write 0 to only the ERQ field specified in the CERQ field
30368  *  0b1..Write 0 to all fields in ERQ
30369  */
30370 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
30371 
30372 #define DMA_CERQ_NOP_MASK                        (0x80U)
30373 #define DMA_CERQ_NOP_SHIFT                       (7U)
30374 /*! NOP - No Op Enable
30375  *  0b0..Normal operation
30376  *  0b1..No operation, ignore the other fields in this register
30377  */
30378 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
30379 /*! @} */
30380 
30381 /*! @name SERQ - Set Enable Request */
30382 /*! @{ */
30383 
30384 #define DMA_SERQ_SERQ_MASK                       (0x1FU)
30385 #define DMA_SERQ_SERQ_SHIFT                      (0U)
30386 /*! SERQ - Set Enable Request
30387  */
30388 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
30389 
30390 #define DMA_SERQ_SAER_MASK                       (0x40U)
30391 #define DMA_SERQ_SAER_SHIFT                      (6U)
30392 /*! SAER - Set All Enable Requests
30393  *  0b0..Write 1 to only the ERQ field specified in the SERQ field
30394  *  0b1..Write 1 to all fields in ERQ
30395  */
30396 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
30397 
30398 #define DMA_SERQ_NOP_MASK                        (0x80U)
30399 #define DMA_SERQ_NOP_SHIFT                       (7U)
30400 /*! NOP - No Op Enable
30401  *  0b0..Normal operation
30402  *  0b1..No operation, ignore the other fields in this register
30403  */
30404 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
30405 /*! @} */
30406 
30407 /*! @name CDNE - Clear DONE Status Bit */
30408 /*! @{ */
30409 
30410 #define DMA_CDNE_CDNE_MASK                       (0x1FU)
30411 #define DMA_CDNE_CDNE_SHIFT                      (0U)
30412 /*! CDNE - Clear DONE field
30413  */
30414 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
30415 
30416 #define DMA_CDNE_CADN_MASK                       (0x40U)
30417 #define DMA_CDNE_CADN_SHIFT                      (6U)
30418 /*! CADN - Clears All DONE fields
30419  *  0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
30420  *  0b1..Writes 0 to all bits in TCDn_CSR[DONE]
30421  */
30422 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
30423 
30424 #define DMA_CDNE_NOP_MASK                        (0x80U)
30425 #define DMA_CDNE_NOP_SHIFT                       (7U)
30426 /*! NOP - No Op Enable
30427  *  0b0..Normal operation
30428  *  0b1..No operation; all other fields in this register are ignored.
30429  */
30430 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
30431 /*! @} */
30432 
30433 /*! @name SSRT - Set START Bit */
30434 /*! @{ */
30435 
30436 #define DMA_SSRT_SSRT_MASK                       (0x1FU)
30437 #define DMA_SSRT_SSRT_SHIFT                      (0U)
30438 /*! SSRT - Set START field
30439  */
30440 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
30441 
30442 #define DMA_SSRT_SAST_MASK                       (0x40U)
30443 #define DMA_SSRT_SAST_SHIFT                      (6U)
30444 /*! SAST - Set All START fields (activates all channels)
30445  *  0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
30446  *  0b1..Write 1 to all bits in TCDn_CSR[START]
30447  */
30448 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
30449 
30450 #define DMA_SSRT_NOP_MASK                        (0x80U)
30451 #define DMA_SSRT_NOP_SHIFT                       (7U)
30452 /*! NOP - No Op Enable
30453  *  0b0..Normal operation
30454  *  0b1..No operation; all other fields in this register are ignored.
30455  */
30456 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
30457 /*! @} */
30458 
30459 /*! @name CERR - Clear Error */
30460 /*! @{ */
30461 
30462 #define DMA_CERR_CERR_MASK                       (0x1FU)
30463 #define DMA_CERR_CERR_SHIFT                      (0U)
30464 /*! CERR - Clear Error Indicator
30465  */
30466 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
30467 
30468 #define DMA_CERR_CAEI_MASK                       (0x40U)
30469 #define DMA_CERR_CAEI_SHIFT                      (6U)
30470 /*! CAEI - Clear All Error Indicators
30471  *  0b0..Write 0 to only the ERR field specified in the CERR field
30472  *  0b1..Write 0 to all fields in ERR
30473  */
30474 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
30475 
30476 #define DMA_CERR_NOP_MASK                        (0x80U)
30477 #define DMA_CERR_NOP_SHIFT                       (7U)
30478 /*! NOP - No Op Enable
30479  *  0b0..Normal operation
30480  *  0b1..No operation; all other fields in this register are ignored.
30481  */
30482 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
30483 /*! @} */
30484 
30485 /*! @name CINT - Clear Interrupt Request */
30486 /*! @{ */
30487 
30488 #define DMA_CINT_CINT_MASK                       (0x1FU)
30489 #define DMA_CINT_CINT_SHIFT                      (0U)
30490 /*! CINT - Clear Interrupt Request
30491  */
30492 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
30493 
30494 #define DMA_CINT_CAIR_MASK                       (0x40U)
30495 #define DMA_CINT_CAIR_SHIFT                      (6U)
30496 /*! CAIR - Clear All Interrupt Requests
30497  *  0b0..Clear only the INT field specified in the CINT field
30498  *  0b1..Clear all bits in INT
30499  */
30500 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
30501 
30502 #define DMA_CINT_NOP_MASK                        (0x80U)
30503 #define DMA_CINT_NOP_SHIFT                       (7U)
30504 /*! NOP - No Op Enable
30505  *  0b0..Normal operation
30506  *  0b1..No operation; all other fields in this register are ignored.
30507  */
30508 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
30509 /*! @} */
30510 
30511 /*! @name INT - Interrupt Request */
30512 /*! @{ */
30513 
30514 #define DMA_INT_INT0_MASK                        (0x1U)
30515 #define DMA_INT_INT0_SHIFT                       (0U)
30516 /*! INT0 - Interrupt Request 0
30517  *  0b0..The interrupt request for channel 0 is cleared
30518  *  0b1..The interrupt request for channel 0 is active
30519  */
30520 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
30521 
30522 #define DMA_INT_INT1_MASK                        (0x2U)
30523 #define DMA_INT_INT1_SHIFT                       (1U)
30524 /*! INT1 - Interrupt Request 1
30525  *  0b0..The interrupt request for channel 1 is cleared
30526  *  0b1..The interrupt request for channel 1 is active
30527  */
30528 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
30529 
30530 #define DMA_INT_INT2_MASK                        (0x4U)
30531 #define DMA_INT_INT2_SHIFT                       (2U)
30532 /*! INT2 - Interrupt Request 2
30533  *  0b0..The interrupt request for channel 2 is cleared
30534  *  0b1..The interrupt request for channel 2 is active
30535  */
30536 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
30537 
30538 #define DMA_INT_INT3_MASK                        (0x8U)
30539 #define DMA_INT_INT3_SHIFT                       (3U)
30540 /*! INT3 - Interrupt Request 3
30541  *  0b0..The interrupt request for channel 3 is cleared
30542  *  0b1..The interrupt request for channel 3 is active
30543  */
30544 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
30545 
30546 #define DMA_INT_INT4_MASK                        (0x10U)
30547 #define DMA_INT_INT4_SHIFT                       (4U)
30548 /*! INT4 - Interrupt Request 4
30549  *  0b0..The interrupt request for channel 4 is cleared
30550  *  0b1..The interrupt request for channel 4 is active
30551  */
30552 #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
30553 
30554 #define DMA_INT_INT5_MASK                        (0x20U)
30555 #define DMA_INT_INT5_SHIFT                       (5U)
30556 /*! INT5 - Interrupt Request 5
30557  *  0b0..The interrupt request for channel 5 is cleared
30558  *  0b1..The interrupt request for channel 5 is active
30559  */
30560 #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
30561 
30562 #define DMA_INT_INT6_MASK                        (0x40U)
30563 #define DMA_INT_INT6_SHIFT                       (6U)
30564 /*! INT6 - Interrupt Request 6
30565  *  0b0..The interrupt request for channel 6 is cleared
30566  *  0b1..The interrupt request for channel 6 is active
30567  */
30568 #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
30569 
30570 #define DMA_INT_INT7_MASK                        (0x80U)
30571 #define DMA_INT_INT7_SHIFT                       (7U)
30572 /*! INT7 - Interrupt Request 7
30573  *  0b0..The interrupt request for channel 7 is cleared
30574  *  0b1..The interrupt request for channel 7 is active
30575  */
30576 #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
30577 
30578 #define DMA_INT_INT8_MASK                        (0x100U)
30579 #define DMA_INT_INT8_SHIFT                       (8U)
30580 /*! INT8 - Interrupt Request 8
30581  *  0b0..The interrupt request for channel 8 is cleared
30582  *  0b1..The interrupt request for channel 8 is active
30583  */
30584 #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
30585 
30586 #define DMA_INT_INT9_MASK                        (0x200U)
30587 #define DMA_INT_INT9_SHIFT                       (9U)
30588 /*! INT9 - Interrupt Request 9
30589  *  0b0..The interrupt request for channel 9 is cleared
30590  *  0b1..The interrupt request for channel 9 is active
30591  */
30592 #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
30593 
30594 #define DMA_INT_INT10_MASK                       (0x400U)
30595 #define DMA_INT_INT10_SHIFT                      (10U)
30596 /*! INT10 - Interrupt Request 10
30597  *  0b0..The interrupt request for channel 10 is cleared
30598  *  0b1..The interrupt request for channel 10 is active
30599  */
30600 #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
30601 
30602 #define DMA_INT_INT11_MASK                       (0x800U)
30603 #define DMA_INT_INT11_SHIFT                      (11U)
30604 /*! INT11 - Interrupt Request 11
30605  *  0b0..The interrupt request for channel 11 is cleared
30606  *  0b1..The interrupt request for channel 11 is active
30607  */
30608 #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
30609 
30610 #define DMA_INT_INT12_MASK                       (0x1000U)
30611 #define DMA_INT_INT12_SHIFT                      (12U)
30612 /*! INT12 - Interrupt Request 12
30613  *  0b0..The interrupt request for channel 12 is cleared
30614  *  0b1..The interrupt request for channel 12 is active
30615  */
30616 #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
30617 
30618 #define DMA_INT_INT13_MASK                       (0x2000U)
30619 #define DMA_INT_INT13_SHIFT                      (13U)
30620 /*! INT13 - Interrupt Request 13
30621  *  0b0..The interrupt request for channel 13 is cleared
30622  *  0b1..The interrupt request for channel 13 is active
30623  */
30624 #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
30625 
30626 #define DMA_INT_INT14_MASK                       (0x4000U)
30627 #define DMA_INT_INT14_SHIFT                      (14U)
30628 /*! INT14 - Interrupt Request 14
30629  *  0b0..The interrupt request for channel 14 is cleared
30630  *  0b1..The interrupt request for channel 14 is active
30631  */
30632 #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
30633 
30634 #define DMA_INT_INT15_MASK                       (0x8000U)
30635 #define DMA_INT_INT15_SHIFT                      (15U)
30636 /*! INT15 - Interrupt Request 15
30637  *  0b0..The interrupt request for channel 15 is cleared
30638  *  0b1..The interrupt request for channel 15 is active
30639  */
30640 #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
30641 
30642 #define DMA_INT_INT16_MASK                       (0x10000U)
30643 #define DMA_INT_INT16_SHIFT                      (16U)
30644 /*! INT16 - Interrupt Request 16
30645  *  0b0..The interrupt request for channel 16 is cleared
30646  *  0b1..The interrupt request for channel 16 is active
30647  */
30648 #define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
30649 
30650 #define DMA_INT_INT17_MASK                       (0x20000U)
30651 #define DMA_INT_INT17_SHIFT                      (17U)
30652 /*! INT17 - Interrupt Request 17
30653  *  0b0..The interrupt request for channel 17 is cleared
30654  *  0b1..The interrupt request for channel 17 is active
30655  */
30656 #define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
30657 
30658 #define DMA_INT_INT18_MASK                       (0x40000U)
30659 #define DMA_INT_INT18_SHIFT                      (18U)
30660 /*! INT18 - Interrupt Request 18
30661  *  0b0..The interrupt request for channel 18 is cleared
30662  *  0b1..The interrupt request for channel 18 is active
30663  */
30664 #define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
30665 
30666 #define DMA_INT_INT19_MASK                       (0x80000U)
30667 #define DMA_INT_INT19_SHIFT                      (19U)
30668 /*! INT19 - Interrupt Request 19
30669  *  0b0..The interrupt request for channel 19 is cleared
30670  *  0b1..The interrupt request for channel 19 is active
30671  */
30672 #define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
30673 
30674 #define DMA_INT_INT20_MASK                       (0x100000U)
30675 #define DMA_INT_INT20_SHIFT                      (20U)
30676 /*! INT20 - Interrupt Request 20
30677  *  0b0..The interrupt request for channel 20 is cleared
30678  *  0b1..The interrupt request for channel 20 is active
30679  */
30680 #define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
30681 
30682 #define DMA_INT_INT21_MASK                       (0x200000U)
30683 #define DMA_INT_INT21_SHIFT                      (21U)
30684 /*! INT21 - Interrupt Request 21
30685  *  0b0..The interrupt request for channel 21 is cleared
30686  *  0b1..The interrupt request for channel 21 is active
30687  */
30688 #define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
30689 
30690 #define DMA_INT_INT22_MASK                       (0x400000U)
30691 #define DMA_INT_INT22_SHIFT                      (22U)
30692 /*! INT22 - Interrupt Request 22
30693  *  0b0..The interrupt request for channel 22 is cleared
30694  *  0b1..The interrupt request for channel 22 is active
30695  */
30696 #define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
30697 
30698 #define DMA_INT_INT23_MASK                       (0x800000U)
30699 #define DMA_INT_INT23_SHIFT                      (23U)
30700 /*! INT23 - Interrupt Request 23
30701  *  0b0..The interrupt request for channel 23 is cleared
30702  *  0b1..The interrupt request for channel 23 is active
30703  */
30704 #define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
30705 
30706 #define DMA_INT_INT24_MASK                       (0x1000000U)
30707 #define DMA_INT_INT24_SHIFT                      (24U)
30708 /*! INT24 - Interrupt Request 24
30709  *  0b0..The interrupt request for channel 24 is cleared
30710  *  0b1..The interrupt request for channel 24 is active
30711  */
30712 #define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
30713 
30714 #define DMA_INT_INT25_MASK                       (0x2000000U)
30715 #define DMA_INT_INT25_SHIFT                      (25U)
30716 /*! INT25 - Interrupt Request 25
30717  *  0b0..The interrupt request for channel 25 is cleared
30718  *  0b1..The interrupt request for channel 25 is active
30719  */
30720 #define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
30721 
30722 #define DMA_INT_INT26_MASK                       (0x4000000U)
30723 #define DMA_INT_INT26_SHIFT                      (26U)
30724 /*! INT26 - Interrupt Request 26
30725  *  0b0..The interrupt request for channel 26 is cleared
30726  *  0b1..The interrupt request for channel 26 is active
30727  */
30728 #define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
30729 
30730 #define DMA_INT_INT27_MASK                       (0x8000000U)
30731 #define DMA_INT_INT27_SHIFT                      (27U)
30732 /*! INT27 - Interrupt Request 27
30733  *  0b0..The interrupt request for channel 27 is cleared
30734  *  0b1..The interrupt request for channel 27 is active
30735  */
30736 #define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
30737 
30738 #define DMA_INT_INT28_MASK                       (0x10000000U)
30739 #define DMA_INT_INT28_SHIFT                      (28U)
30740 /*! INT28 - Interrupt Request 28
30741  *  0b0..The interrupt request for channel 28 is cleared
30742  *  0b1..The interrupt request for channel 28 is active
30743  */
30744 #define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
30745 
30746 #define DMA_INT_INT29_MASK                       (0x20000000U)
30747 #define DMA_INT_INT29_SHIFT                      (29U)
30748 /*! INT29 - Interrupt Request 29
30749  *  0b0..The interrupt request for channel 29 is cleared
30750  *  0b1..The interrupt request for channel 29 is active
30751  */
30752 #define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
30753 
30754 #define DMA_INT_INT30_MASK                       (0x40000000U)
30755 #define DMA_INT_INT30_SHIFT                      (30U)
30756 /*! INT30 - Interrupt Request 30
30757  *  0b0..The interrupt request for channel 30 is cleared
30758  *  0b1..The interrupt request for channel 30 is active
30759  */
30760 #define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
30761 
30762 #define DMA_INT_INT31_MASK                       (0x80000000U)
30763 #define DMA_INT_INT31_SHIFT                      (31U)
30764 /*! INT31 - Interrupt Request 31
30765  *  0b0..The interrupt request for channel 31 is cleared
30766  *  0b1..The interrupt request for channel 31 is active
30767  */
30768 #define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
30769 /*! @} */
30770 
30771 /*! @name ERR - Error */
30772 /*! @{ */
30773 
30774 #define DMA_ERR_ERR0_MASK                        (0x1U)
30775 #define DMA_ERR_ERR0_SHIFT                       (0U)
30776 /*! ERR0 - Error In Channel 0
30777  *  0b0..No error in this channel has occurred
30778  *  0b1..An error in this channel has occurred
30779  */
30780 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
30781 
30782 #define DMA_ERR_ERR1_MASK                        (0x2U)
30783 #define DMA_ERR_ERR1_SHIFT                       (1U)
30784 /*! ERR1 - Error In Channel 1
30785  *  0b0..No error in this channel has occurred
30786  *  0b1..An error in this channel has occurred
30787  */
30788 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
30789 
30790 #define DMA_ERR_ERR2_MASK                        (0x4U)
30791 #define DMA_ERR_ERR2_SHIFT                       (2U)
30792 /*! ERR2 - Error In Channel 2
30793  *  0b0..No error in this channel has occurred
30794  *  0b1..An error in this channel has occurred
30795  */
30796 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
30797 
30798 #define DMA_ERR_ERR3_MASK                        (0x8U)
30799 #define DMA_ERR_ERR3_SHIFT                       (3U)
30800 /*! ERR3 - Error In Channel 3
30801  *  0b0..No error in this channel has occurred
30802  *  0b1..An error in this channel has occurred
30803  */
30804 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
30805 
30806 #define DMA_ERR_ERR4_MASK                        (0x10U)
30807 #define DMA_ERR_ERR4_SHIFT                       (4U)
30808 /*! ERR4 - Error In Channel 4
30809  *  0b0..No error in this channel has occurred
30810  *  0b1..An error in this channel has occurred
30811  */
30812 #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
30813 
30814 #define DMA_ERR_ERR5_MASK                        (0x20U)
30815 #define DMA_ERR_ERR5_SHIFT                       (5U)
30816 /*! ERR5 - Error In Channel 5
30817  *  0b0..No error in this channel has occurred
30818  *  0b1..An error in this channel has occurred
30819  */
30820 #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
30821 
30822 #define DMA_ERR_ERR6_MASK                        (0x40U)
30823 #define DMA_ERR_ERR6_SHIFT                       (6U)
30824 /*! ERR6 - Error In Channel 6
30825  *  0b0..No error in this channel has occurred
30826  *  0b1..An error in this channel has occurred
30827  */
30828 #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
30829 
30830 #define DMA_ERR_ERR7_MASK                        (0x80U)
30831 #define DMA_ERR_ERR7_SHIFT                       (7U)
30832 /*! ERR7 - Error In Channel 7
30833  *  0b0..No error in this channel has occurred
30834  *  0b1..An error in this channel has occurred
30835  */
30836 #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
30837 
30838 #define DMA_ERR_ERR8_MASK                        (0x100U)
30839 #define DMA_ERR_ERR8_SHIFT                       (8U)
30840 /*! ERR8 - Error In Channel 8
30841  *  0b0..No error in this channel has occurred
30842  *  0b1..An error in this channel has occurred
30843  */
30844 #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
30845 
30846 #define DMA_ERR_ERR9_MASK                        (0x200U)
30847 #define DMA_ERR_ERR9_SHIFT                       (9U)
30848 /*! ERR9 - Error In Channel 9
30849  *  0b0..No error in this channel has occurred
30850  *  0b1..An error in this channel has occurred
30851  */
30852 #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
30853 
30854 #define DMA_ERR_ERR10_MASK                       (0x400U)
30855 #define DMA_ERR_ERR10_SHIFT                      (10U)
30856 /*! ERR10 - Error In Channel 10
30857  *  0b0..No error in this channel has occurred
30858  *  0b1..An error in this channel has occurred
30859  */
30860 #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
30861 
30862 #define DMA_ERR_ERR11_MASK                       (0x800U)
30863 #define DMA_ERR_ERR11_SHIFT                      (11U)
30864 /*! ERR11 - Error In Channel 11
30865  *  0b0..No error in this channel has occurred
30866  *  0b1..An error in this channel has occurred
30867  */
30868 #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
30869 
30870 #define DMA_ERR_ERR12_MASK                       (0x1000U)
30871 #define DMA_ERR_ERR12_SHIFT                      (12U)
30872 /*! ERR12 - Error In Channel 12
30873  *  0b0..No error in this channel has occurred
30874  *  0b1..An error in this channel has occurred
30875  */
30876 #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
30877 
30878 #define DMA_ERR_ERR13_MASK                       (0x2000U)
30879 #define DMA_ERR_ERR13_SHIFT                      (13U)
30880 /*! ERR13 - Error In Channel 13
30881  *  0b0..No error in this channel has occurred
30882  *  0b1..An error in this channel has occurred
30883  */
30884 #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
30885 
30886 #define DMA_ERR_ERR14_MASK                       (0x4000U)
30887 #define DMA_ERR_ERR14_SHIFT                      (14U)
30888 /*! ERR14 - Error In Channel 14
30889  *  0b0..No error in this channel has occurred
30890  *  0b1..An error in this channel has occurred
30891  */
30892 #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
30893 
30894 #define DMA_ERR_ERR15_MASK                       (0x8000U)
30895 #define DMA_ERR_ERR15_SHIFT                      (15U)
30896 /*! ERR15 - Error In Channel 15
30897  *  0b0..No error in this channel has occurred
30898  *  0b1..An error in this channel has occurred
30899  */
30900 #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
30901 
30902 #define DMA_ERR_ERR16_MASK                       (0x10000U)
30903 #define DMA_ERR_ERR16_SHIFT                      (16U)
30904 /*! ERR16 - Error In Channel 16
30905  *  0b0..No error in this channel has occurred
30906  *  0b1..An error in this channel has occurred
30907  */
30908 #define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
30909 
30910 #define DMA_ERR_ERR17_MASK                       (0x20000U)
30911 #define DMA_ERR_ERR17_SHIFT                      (17U)
30912 /*! ERR17 - Error In Channel 17
30913  *  0b0..No error in this channel has occurred
30914  *  0b1..An error in this channel has occurred
30915  */
30916 #define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
30917 
30918 #define DMA_ERR_ERR18_MASK                       (0x40000U)
30919 #define DMA_ERR_ERR18_SHIFT                      (18U)
30920 /*! ERR18 - Error In Channel 18
30921  *  0b0..No error in this channel has occurred
30922  *  0b1..An error in this channel has occurred
30923  */
30924 #define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
30925 
30926 #define DMA_ERR_ERR19_MASK                       (0x80000U)
30927 #define DMA_ERR_ERR19_SHIFT                      (19U)
30928 /*! ERR19 - Error In Channel 19
30929  *  0b0..No error in this channel has occurred
30930  *  0b1..An error in this channel has occurred
30931  */
30932 #define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
30933 
30934 #define DMA_ERR_ERR20_MASK                       (0x100000U)
30935 #define DMA_ERR_ERR20_SHIFT                      (20U)
30936 /*! ERR20 - Error In Channel 20
30937  *  0b0..No error in this channel has occurred
30938  *  0b1..An error in this channel has occurred
30939  */
30940 #define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
30941 
30942 #define DMA_ERR_ERR21_MASK                       (0x200000U)
30943 #define DMA_ERR_ERR21_SHIFT                      (21U)
30944 /*! ERR21 - Error In Channel 21
30945  *  0b0..No error in this channel has occurred
30946  *  0b1..An error in this channel has occurred
30947  */
30948 #define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
30949 
30950 #define DMA_ERR_ERR22_MASK                       (0x400000U)
30951 #define DMA_ERR_ERR22_SHIFT                      (22U)
30952 /*! ERR22 - Error In Channel 22
30953  *  0b0..No error in this channel has occurred
30954  *  0b1..An error in this channel has occurred
30955  */
30956 #define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
30957 
30958 #define DMA_ERR_ERR23_MASK                       (0x800000U)
30959 #define DMA_ERR_ERR23_SHIFT                      (23U)
30960 /*! ERR23 - Error In Channel 23
30961  *  0b0..No error in this channel has occurred
30962  *  0b1..An error in this channel has occurred
30963  */
30964 #define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
30965 
30966 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
30967 #define DMA_ERR_ERR24_SHIFT                      (24U)
30968 /*! ERR24 - Error In Channel 24
30969  *  0b0..No error in this channel has occurred
30970  *  0b1..An error in this channel has occurred
30971  */
30972 #define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
30973 
30974 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
30975 #define DMA_ERR_ERR25_SHIFT                      (25U)
30976 /*! ERR25 - Error In Channel 25
30977  *  0b0..No error in this channel has occurred
30978  *  0b1..An error in this channel has occurred
30979  */
30980 #define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
30981 
30982 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
30983 #define DMA_ERR_ERR26_SHIFT                      (26U)
30984 /*! ERR26 - Error In Channel 26
30985  *  0b0..No error in this channel has occurred
30986  *  0b1..An error in this channel has occurred
30987  */
30988 #define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
30989 
30990 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
30991 #define DMA_ERR_ERR27_SHIFT                      (27U)
30992 /*! ERR27 - Error In Channel 27
30993  *  0b0..No error in this channel has occurred
30994  *  0b1..An error in this channel has occurred
30995  */
30996 #define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
30997 
30998 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
30999 #define DMA_ERR_ERR28_SHIFT                      (28U)
31000 /*! ERR28 - Error In Channel 28
31001  *  0b0..No error in this channel has occurred
31002  *  0b1..An error in this channel has occurred
31003  */
31004 #define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
31005 
31006 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
31007 #define DMA_ERR_ERR29_SHIFT                      (29U)
31008 /*! ERR29 - Error In Channel 29
31009  *  0b0..No error in this channel has occurred
31010  *  0b1..An error in this channel has occurred
31011  */
31012 #define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
31013 
31014 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
31015 #define DMA_ERR_ERR30_SHIFT                      (30U)
31016 /*! ERR30 - Error In Channel 30
31017  *  0b0..No error in this channel has occurred
31018  *  0b1..An error in this channel has occurred
31019  */
31020 #define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
31021 
31022 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
31023 #define DMA_ERR_ERR31_SHIFT                      (31U)
31024 /*! ERR31 - Error In Channel 31
31025  *  0b0..No error in this channel has occurred
31026  *  0b1..An error in this channel has occurred
31027  */
31028 #define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
31029 /*! @} */
31030 
31031 /*! @name HRS - Hardware Request Status */
31032 /*! @{ */
31033 
31034 #define DMA_HRS_HRS0_MASK                        (0x1U)
31035 #define DMA_HRS_HRS0_SHIFT                       (0U)
31036 /*! HRS0 - Hardware Request Status Channel 0
31037  *  0b0..A hardware service request for channel 0 is not present
31038  *  0b1..A hardware service request for channel 0 is present
31039  */
31040 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
31041 
31042 #define DMA_HRS_HRS1_MASK                        (0x2U)
31043 #define DMA_HRS_HRS1_SHIFT                       (1U)
31044 /*! HRS1 - Hardware Request Status Channel 1
31045  *  0b0..A hardware service request for channel 1 is not present
31046  *  0b1..A hardware service request for channel 1 is present
31047  */
31048 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
31049 
31050 #define DMA_HRS_HRS2_MASK                        (0x4U)
31051 #define DMA_HRS_HRS2_SHIFT                       (2U)
31052 /*! HRS2 - Hardware Request Status Channel 2
31053  *  0b0..A hardware service request for channel 2 is not present
31054  *  0b1..A hardware service request for channel 2 is present
31055  */
31056 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
31057 
31058 #define DMA_HRS_HRS3_MASK                        (0x8U)
31059 #define DMA_HRS_HRS3_SHIFT                       (3U)
31060 /*! HRS3 - Hardware Request Status Channel 3
31061  *  0b0..A hardware service request for channel 3 is not present
31062  *  0b1..A hardware service request for channel 3 is present
31063  */
31064 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
31065 
31066 #define DMA_HRS_HRS4_MASK                        (0x10U)
31067 #define DMA_HRS_HRS4_SHIFT                       (4U)
31068 /*! HRS4 - Hardware Request Status Channel 4
31069  *  0b0..A hardware service request for channel 4 is not present
31070  *  0b1..A hardware service request for channel 4 is present
31071  */
31072 #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
31073 
31074 #define DMA_HRS_HRS5_MASK                        (0x20U)
31075 #define DMA_HRS_HRS5_SHIFT                       (5U)
31076 /*! HRS5 - Hardware Request Status Channel 5
31077  *  0b0..A hardware service request for channel 5 is not present
31078  *  0b1..A hardware service request for channel 5 is present
31079  */
31080 #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
31081 
31082 #define DMA_HRS_HRS6_MASK                        (0x40U)
31083 #define DMA_HRS_HRS6_SHIFT                       (6U)
31084 /*! HRS6 - Hardware Request Status Channel 6
31085  *  0b0..A hardware service request for channel 6 is not present
31086  *  0b1..A hardware service request for channel 6 is present
31087  */
31088 #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
31089 
31090 #define DMA_HRS_HRS7_MASK                        (0x80U)
31091 #define DMA_HRS_HRS7_SHIFT                       (7U)
31092 /*! HRS7 - Hardware Request Status Channel 7
31093  *  0b0..A hardware service request for channel 7 is not present
31094  *  0b1..A hardware service request for channel 7 is present
31095  */
31096 #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
31097 
31098 #define DMA_HRS_HRS8_MASK                        (0x100U)
31099 #define DMA_HRS_HRS8_SHIFT                       (8U)
31100 /*! HRS8 - Hardware Request Status Channel 8
31101  *  0b0..A hardware service request for channel 8 is not present
31102  *  0b1..A hardware service request for channel 8 is present
31103  */
31104 #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
31105 
31106 #define DMA_HRS_HRS9_MASK                        (0x200U)
31107 #define DMA_HRS_HRS9_SHIFT                       (9U)
31108 /*! HRS9 - Hardware Request Status Channel 9
31109  *  0b0..A hardware service request for channel 9 is not present
31110  *  0b1..A hardware service request for channel 9 is present
31111  */
31112 #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
31113 
31114 #define DMA_HRS_HRS10_MASK                       (0x400U)
31115 #define DMA_HRS_HRS10_SHIFT                      (10U)
31116 /*! HRS10 - Hardware Request Status Channel 10
31117  *  0b0..A hardware service request for channel 10 is not present
31118  *  0b1..A hardware service request for channel 10 is present
31119  */
31120 #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
31121 
31122 #define DMA_HRS_HRS11_MASK                       (0x800U)
31123 #define DMA_HRS_HRS11_SHIFT                      (11U)
31124 /*! HRS11 - Hardware Request Status Channel 11
31125  *  0b0..A hardware service request for channel 11 is not present
31126  *  0b1..A hardware service request for channel 11 is present
31127  */
31128 #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
31129 
31130 #define DMA_HRS_HRS12_MASK                       (0x1000U)
31131 #define DMA_HRS_HRS12_SHIFT                      (12U)
31132 /*! HRS12 - Hardware Request Status Channel 12
31133  *  0b0..A hardware service request for channel 12 is not present
31134  *  0b1..A hardware service request for channel 12 is present
31135  */
31136 #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
31137 
31138 #define DMA_HRS_HRS13_MASK                       (0x2000U)
31139 #define DMA_HRS_HRS13_SHIFT                      (13U)
31140 /*! HRS13 - Hardware Request Status Channel 13
31141  *  0b0..A hardware service request for channel 13 is not present
31142  *  0b1..A hardware service request for channel 13 is present
31143  */
31144 #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
31145 
31146 #define DMA_HRS_HRS14_MASK                       (0x4000U)
31147 #define DMA_HRS_HRS14_SHIFT                      (14U)
31148 /*! HRS14 - Hardware Request Status Channel 14
31149  *  0b0..A hardware service request for channel 14 is not present
31150  *  0b1..A hardware service request for channel 14 is present
31151  */
31152 #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
31153 
31154 #define DMA_HRS_HRS15_MASK                       (0x8000U)
31155 #define DMA_HRS_HRS15_SHIFT                      (15U)
31156 /*! HRS15 - Hardware Request Status Channel 15
31157  *  0b0..A hardware service request for channel 15 is not present
31158  *  0b1..A hardware service request for channel 15 is present
31159  */
31160 #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
31161 
31162 #define DMA_HRS_HRS16_MASK                       (0x10000U)
31163 #define DMA_HRS_HRS16_SHIFT                      (16U)
31164 /*! HRS16 - Hardware Request Status Channel 16
31165  *  0b0..A hardware service request for channel 16 is not present
31166  *  0b1..A hardware service request for channel 16 is present
31167  */
31168 #define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
31169 
31170 #define DMA_HRS_HRS17_MASK                       (0x20000U)
31171 #define DMA_HRS_HRS17_SHIFT                      (17U)
31172 /*! HRS17 - Hardware Request Status Channel 17
31173  *  0b0..A hardware service request for channel 17 is not present
31174  *  0b1..A hardware service request for channel 17 is present
31175  */
31176 #define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
31177 
31178 #define DMA_HRS_HRS18_MASK                       (0x40000U)
31179 #define DMA_HRS_HRS18_SHIFT                      (18U)
31180 /*! HRS18 - Hardware Request Status Channel 18
31181  *  0b0..A hardware service request for channel 18 is not present
31182  *  0b1..A hardware service request for channel 18 is present
31183  */
31184 #define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
31185 
31186 #define DMA_HRS_HRS19_MASK                       (0x80000U)
31187 #define DMA_HRS_HRS19_SHIFT                      (19U)
31188 /*! HRS19 - Hardware Request Status Channel 19
31189  *  0b0..A hardware service request for channel 19 is not present
31190  *  0b1..A hardware service request for channel 19 is present
31191  */
31192 #define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
31193 
31194 #define DMA_HRS_HRS20_MASK                       (0x100000U)
31195 #define DMA_HRS_HRS20_SHIFT                      (20U)
31196 /*! HRS20 - Hardware Request Status Channel 20
31197  *  0b0..A hardware service request for channel 20 is not present
31198  *  0b1..A hardware service request for channel 20 is present
31199  */
31200 #define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
31201 
31202 #define DMA_HRS_HRS21_MASK                       (0x200000U)
31203 #define DMA_HRS_HRS21_SHIFT                      (21U)
31204 /*! HRS21 - Hardware Request Status Channel 21
31205  *  0b0..A hardware service request for channel 21 is not present
31206  *  0b1..A hardware service request for channel 21 is present
31207  */
31208 #define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
31209 
31210 #define DMA_HRS_HRS22_MASK                       (0x400000U)
31211 #define DMA_HRS_HRS22_SHIFT                      (22U)
31212 /*! HRS22 - Hardware Request Status Channel 22
31213  *  0b0..A hardware service request for channel 22 is not present
31214  *  0b1..A hardware service request for channel 22 is present
31215  */
31216 #define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
31217 
31218 #define DMA_HRS_HRS23_MASK                       (0x800000U)
31219 #define DMA_HRS_HRS23_SHIFT                      (23U)
31220 /*! HRS23 - Hardware Request Status Channel 23
31221  *  0b0..A hardware service request for channel 23 is not present
31222  *  0b1..A hardware service request for channel 23 is present
31223  */
31224 #define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
31225 
31226 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
31227 #define DMA_HRS_HRS24_SHIFT                      (24U)
31228 /*! HRS24 - Hardware Request Status Channel 24
31229  *  0b0..A hardware service request for channel 24 is not present
31230  *  0b1..A hardware service request for channel 24 is present
31231  */
31232 #define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
31233 
31234 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
31235 #define DMA_HRS_HRS25_SHIFT                      (25U)
31236 /*! HRS25 - Hardware Request Status Channel 25
31237  *  0b0..A hardware service request for channel 25 is not present
31238  *  0b1..A hardware service request for channel 25 is present
31239  */
31240 #define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
31241 
31242 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
31243 #define DMA_HRS_HRS26_SHIFT                      (26U)
31244 /*! HRS26 - Hardware Request Status Channel 26
31245  *  0b0..A hardware service request for channel 26 is not present
31246  *  0b1..A hardware service request for channel 26 is present
31247  */
31248 #define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
31249 
31250 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
31251 #define DMA_HRS_HRS27_SHIFT                      (27U)
31252 /*! HRS27 - Hardware Request Status Channel 27
31253  *  0b0..A hardware service request for channel 27 is not present
31254  *  0b1..A hardware service request for channel 27 is present
31255  */
31256 #define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
31257 
31258 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
31259 #define DMA_HRS_HRS28_SHIFT                      (28U)
31260 /*! HRS28 - Hardware Request Status Channel 28
31261  *  0b0..A hardware service request for channel 28 is not present
31262  *  0b1..A hardware service request for channel 28 is present
31263  */
31264 #define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
31265 
31266 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
31267 #define DMA_HRS_HRS29_SHIFT                      (29U)
31268 /*! HRS29 - Hardware Request Status Channel 29
31269  *  0b0..A hardware service request for channel 29 is not preset
31270  *  0b1..A hardware service request for channel 29 is present
31271  */
31272 #define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
31273 
31274 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
31275 #define DMA_HRS_HRS30_SHIFT                      (30U)
31276 /*! HRS30 - Hardware Request Status Channel 30
31277  *  0b0..A hardware service request for channel 30 is not present
31278  *  0b1..A hardware service request for channel 30 is present
31279  */
31280 #define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
31281 
31282 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
31283 #define DMA_HRS_HRS31_SHIFT                      (31U)
31284 /*! HRS31 - Hardware Request Status Channel 31
31285  *  0b0..A hardware service request for channel 31 is not present
31286  *  0b1..A hardware service request for channel 31 is present
31287  */
31288 #define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
31289 /*! @} */
31290 
31291 /*! @name EARS - Enable Asynchronous Request in Stop */
31292 /*! @{ */
31293 
31294 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
31295 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
31296 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
31297  *  0b0..Disable asynchronous DMA request for channel 0
31298  *  0b1..Enable asynchronous DMA request for channel 0
31299  */
31300 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
31301 
31302 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
31303 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
31304 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
31305  *  0b0..Disable asynchronous DMA request for channel 1
31306  *  0b1..Enable asynchronous DMA request for channel 1
31307  */
31308 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
31309 
31310 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
31311 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
31312 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
31313  *  0b0..Disable asynchronous DMA request for channel 2
31314  *  0b1..Enable asynchronous DMA request for channel 2
31315  */
31316 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
31317 
31318 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
31319 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
31320 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
31321  *  0b0..Disable asynchronous DMA request for channel 3
31322  *  0b1..Enable asynchronous DMA request for channel 3
31323  */
31324 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
31325 
31326 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
31327 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
31328 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4.
31329  *  0b0..Disable asynchronous DMA request for channel 4
31330  *  0b1..Enable asynchronous DMA request for channel 4
31331  */
31332 #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
31333 
31334 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
31335 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
31336 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5.
31337  *  0b0..Disable asynchronous DMA request for channel 5
31338  *  0b1..Enable asynchronous DMA request for channel 5
31339  */
31340 #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
31341 
31342 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
31343 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
31344 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6.
31345  *  0b0..Disable asynchronous DMA request for channel 6
31346  *  0b1..Enable asynchronous DMA request for channel 6
31347  */
31348 #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
31349 
31350 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
31351 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
31352 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7.
31353  *  0b0..Disable asynchronous DMA request for channel 7
31354  *  0b1..Enable asynchronous DMA request for channel 7
31355  */
31356 #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
31357 
31358 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
31359 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
31360 /*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8.
31361  *  0b0..Disable asynchronous DMA request for channel 8
31362  *  0b1..Enable asynchronous DMA request for channel 8
31363  */
31364 #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
31365 
31366 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
31367 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
31368 /*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9.
31369  *  0b0..Disable asynchronous DMA request for channel 9
31370  *  0b1..Enable asynchronous DMA request for channel 9
31371  */
31372 #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
31373 
31374 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
31375 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
31376 /*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10.
31377  *  0b0..Disable asynchronous DMA request for channel 10
31378  *  0b1..Enable asynchronous DMA request for channel 10
31379  */
31380 #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
31381 
31382 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
31383 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
31384 /*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11.
31385  *  0b0..Disable asynchronous DMA request for channel 11
31386  *  0b1..Enable asynchronous DMA request for channel 11
31387  */
31388 #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
31389 
31390 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
31391 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
31392 /*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12.
31393  *  0b0..Disable asynchronous DMA request for channel 12
31394  *  0b1..Enable asynchronous DMA request for channel 12
31395  */
31396 #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
31397 
31398 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
31399 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
31400 /*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13.
31401  *  0b0..Disable asynchronous DMA request for channel 13
31402  *  0b1..Enable asynchronous DMA request for channel 13
31403  */
31404 #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
31405 
31406 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
31407 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
31408 /*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14.
31409  *  0b0..Disable asynchronous DMA request for channel 14
31410  *  0b1..Enable asynchronous DMA request for channel 14
31411  */
31412 #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
31413 
31414 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
31415 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
31416 /*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15.
31417  *  0b0..Disable asynchronous DMA request for channel 15
31418  *  0b1..Enable asynchronous DMA request for channel 15
31419  */
31420 #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
31421 
31422 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
31423 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
31424 /*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16.
31425  *  0b0..Disable asynchronous DMA request for channel 16
31426  *  0b1..Enable asynchronous DMA request for channel 16
31427  */
31428 #define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
31429 
31430 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
31431 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
31432 /*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17.
31433  *  0b0..Disable asynchronous DMA request for channel 17
31434  *  0b1..Enable asynchronous DMA request for channel 17
31435  */
31436 #define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
31437 
31438 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
31439 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
31440 /*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18.
31441  *  0b0..Disable asynchronous DMA request for channel 18
31442  *  0b1..Enable asynchronous DMA request for channel 18
31443  */
31444 #define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
31445 
31446 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
31447 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
31448 /*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19.
31449  *  0b0..Disable asynchronous DMA request for channel 19
31450  *  0b1..Enable asynchronous DMA request for channel 19
31451  */
31452 #define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
31453 
31454 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
31455 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
31456 /*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20.
31457  *  0b0..Disable asynchronous DMA request for channel 20
31458  *  0b1..Enable asynchronous DMA request for channel 20
31459  */
31460 #define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
31461 
31462 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
31463 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
31464 /*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21.
31465  *  0b0..Disable asynchronous DMA request for channel 21
31466  *  0b1..Enable asynchronous DMA request for channel 21
31467  */
31468 #define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
31469 
31470 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
31471 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
31472 /*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22.
31473  *  0b0..Disable asynchronous DMA request for channel 22
31474  *  0b1..Enable asynchronous DMA request for channel 22
31475  */
31476 #define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
31477 
31478 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
31479 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
31480 /*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23.
31481  *  0b0..Disable asynchronous DMA request for channel 23
31482  *  0b1..Enable asynchronous DMA request for channel 23
31483  */
31484 #define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
31485 
31486 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
31487 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
31488 /*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24.
31489  *  0b0..Disable asynchronous DMA request for channel 24
31490  *  0b1..Enable asynchronous DMA request for channel 24
31491  */
31492 #define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
31493 
31494 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
31495 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
31496 /*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25.
31497  *  0b0..Disable asynchronous DMA request for channel 25
31498  *  0b1..Enable asynchronous DMA request for channel 25
31499  */
31500 #define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
31501 
31502 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
31503 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
31504 /*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26.
31505  *  0b0..Disable asynchronous DMA request for channel 26
31506  *  0b1..Enable asynchronous DMA request for channel 26
31507  */
31508 #define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
31509 
31510 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
31511 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
31512 /*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27.
31513  *  0b0..Disable asynchronous DMA request for channel 27
31514  *  0b1..Enable asynchronous DMA request for channel 27
31515  */
31516 #define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
31517 
31518 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
31519 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
31520 /*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28.
31521  *  0b0..Disable asynchronous DMA request for channel 28
31522  *  0b1..Enable asynchronous DMA request for channel 28
31523  */
31524 #define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
31525 
31526 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
31527 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
31528 /*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29.
31529  *  0b0..Disable asynchronous DMA request for channel 29
31530  *  0b1..Enable asynchronous DMA request for channel 29
31531  */
31532 #define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
31533 
31534 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
31535 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
31536 /*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30.
31537  *  0b0..Disable asynchronous DMA request for channel 30
31538  *  0b1..Enable asynchronous DMA request for channel 30
31539  */
31540 #define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
31541 
31542 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
31543 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
31544 /*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31.
31545  *  0b0..Disable asynchronous DMA request for channel 31
31546  *  0b1..Enable asynchronous DMA request for channel 31
31547  */
31548 #define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
31549 /*! @} */
31550 
31551 /*! @name DCHPRI3 - Channel Priority */
31552 /*! @{ */
31553 
31554 #define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
31555 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
31556 /*! CHPRI - Channel n Arbitration Priority
31557  */
31558 #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
31559 
31560 #define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
31561 #define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
31562 /*! GRPPRI - Channel n Current Group Priority
31563  */
31564 #define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
31565 
31566 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
31567 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
31568 /*! DPA - Disable Preempt Ability. This field resets to 0.
31569  *  0b0..Channel n can suspend a lower priority channel
31570  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31571  */
31572 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
31573 
31574 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
31575 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
31576 /*! ECP - Enable Channel Preemption. This field resets to 0.
31577  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31578  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31579  */
31580 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
31581 /*! @} */
31582 
31583 /*! @name DCHPRI2 - Channel Priority */
31584 /*! @{ */
31585 
31586 #define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
31587 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
31588 /*! CHPRI - Channel n Arbitration Priority
31589  */
31590 #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
31591 
31592 #define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
31593 #define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
31594 /*! GRPPRI - Channel n Current Group Priority
31595  */
31596 #define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
31597 
31598 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
31599 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
31600 /*! DPA - Disable Preempt Ability. This field resets to 0.
31601  *  0b0..Channel n can suspend a lower priority channel
31602  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31603  */
31604 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
31605 
31606 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
31607 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
31608 /*! ECP - Enable Channel Preemption. This field resets to 0.
31609  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31610  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31611  */
31612 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
31613 /*! @} */
31614 
31615 /*! @name DCHPRI1 - Channel Priority */
31616 /*! @{ */
31617 
31618 #define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
31619 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
31620 /*! CHPRI - Channel n Arbitration Priority
31621  */
31622 #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
31623 
31624 #define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
31625 #define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
31626 /*! GRPPRI - Channel n Current Group Priority
31627  */
31628 #define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
31629 
31630 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
31631 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
31632 /*! DPA - Disable Preempt Ability. This field resets to 0.
31633  *  0b0..Channel n can suspend a lower priority channel
31634  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31635  */
31636 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
31637 
31638 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
31639 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
31640 /*! ECP - Enable Channel Preemption. This field resets to 0.
31641  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31642  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31643  */
31644 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
31645 /*! @} */
31646 
31647 /*! @name DCHPRI0 - Channel Priority */
31648 /*! @{ */
31649 
31650 #define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
31651 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
31652 /*! CHPRI - Channel n Arbitration Priority
31653  */
31654 #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
31655 
31656 #define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
31657 #define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
31658 /*! GRPPRI - Channel n Current Group Priority
31659  */
31660 #define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
31661 
31662 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
31663 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
31664 /*! DPA - Disable Preempt Ability. This field resets to 0.
31665  *  0b0..Channel n can suspend a lower priority channel
31666  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31667  */
31668 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
31669 
31670 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
31671 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
31672 /*! ECP - Enable Channel Preemption. This field resets to 0.
31673  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31674  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31675  */
31676 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
31677 /*! @} */
31678 
31679 /*! @name DCHPRI7 - Channel Priority */
31680 /*! @{ */
31681 
31682 #define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
31683 #define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
31684 /*! CHPRI - Channel n Arbitration Priority
31685  */
31686 #define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
31687 
31688 #define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
31689 #define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
31690 /*! GRPPRI - Channel n Current Group Priority
31691  */
31692 #define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
31693 
31694 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
31695 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
31696 /*! DPA - Disable Preempt Ability. This field resets to 0.
31697  *  0b0..Channel n can suspend a lower priority channel
31698  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31699  */
31700 #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
31701 
31702 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
31703 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
31704 /*! ECP - Enable Channel Preemption. This field resets to 0.
31705  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31706  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31707  */
31708 #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
31709 /*! @} */
31710 
31711 /*! @name DCHPRI6 - Channel Priority */
31712 /*! @{ */
31713 
31714 #define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
31715 #define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
31716 /*! CHPRI - Channel n Arbitration Priority
31717  */
31718 #define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
31719 
31720 #define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
31721 #define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
31722 /*! GRPPRI - Channel n Current Group Priority
31723  */
31724 #define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
31725 
31726 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
31727 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
31728 /*! DPA - Disable Preempt Ability. This field resets to 0.
31729  *  0b0..Channel n can suspend a lower priority channel
31730  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31731  */
31732 #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
31733 
31734 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
31735 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
31736 /*! ECP - Enable Channel Preemption. This field resets to 0.
31737  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31738  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31739  */
31740 #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
31741 /*! @} */
31742 
31743 /*! @name DCHPRI5 - Channel Priority */
31744 /*! @{ */
31745 
31746 #define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
31747 #define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
31748 /*! CHPRI - Channel n Arbitration Priority
31749  */
31750 #define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
31751 
31752 #define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
31753 #define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
31754 /*! GRPPRI - Channel n Current Group Priority
31755  */
31756 #define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
31757 
31758 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
31759 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
31760 /*! DPA - Disable Preempt Ability. This field resets to 0.
31761  *  0b0..Channel n can suspend a lower priority channel
31762  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31763  */
31764 #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
31765 
31766 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
31767 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
31768 /*! ECP - Enable Channel Preemption. This field resets to 0.
31769  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31770  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31771  */
31772 #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
31773 /*! @} */
31774 
31775 /*! @name DCHPRI4 - Channel Priority */
31776 /*! @{ */
31777 
31778 #define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
31779 #define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
31780 /*! CHPRI - Channel n Arbitration Priority
31781  */
31782 #define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
31783 
31784 #define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
31785 #define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
31786 /*! GRPPRI - Channel n Current Group Priority
31787  */
31788 #define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
31789 
31790 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
31791 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
31792 /*! DPA - Disable Preempt Ability. This field resets to 0.
31793  *  0b0..Channel n can suspend a lower priority channel
31794  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31795  */
31796 #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
31797 
31798 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
31799 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
31800 /*! ECP - Enable Channel Preemption. This field resets to 0.
31801  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31802  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31803  */
31804 #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
31805 /*! @} */
31806 
31807 /*! @name DCHPRI11 - Channel Priority */
31808 /*! @{ */
31809 
31810 #define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
31811 #define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
31812 /*! CHPRI - Channel n Arbitration Priority
31813  */
31814 #define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
31815 
31816 #define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
31817 #define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
31818 /*! GRPPRI - Channel n Current Group Priority
31819  */
31820 #define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
31821 
31822 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
31823 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
31824 /*! DPA - Disable Preempt Ability. This field resets to 0.
31825  *  0b0..Channel n can suspend a lower priority channel
31826  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31827  */
31828 #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
31829 
31830 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
31831 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
31832 /*! ECP - Enable Channel Preemption. This field resets to 0.
31833  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31834  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31835  */
31836 #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
31837 /*! @} */
31838 
31839 /*! @name DCHPRI10 - Channel Priority */
31840 /*! @{ */
31841 
31842 #define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
31843 #define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
31844 /*! CHPRI - Channel n Arbitration Priority
31845  */
31846 #define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
31847 
31848 #define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
31849 #define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
31850 /*! GRPPRI - Channel n Current Group Priority
31851  */
31852 #define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
31853 
31854 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
31855 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
31856 /*! DPA - Disable Preempt Ability. This field resets to 0.
31857  *  0b0..Channel n can suspend a lower priority channel
31858  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31859  */
31860 #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
31861 
31862 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
31863 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
31864 /*! ECP - Enable Channel Preemption. This field resets to 0.
31865  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31866  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31867  */
31868 #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
31869 /*! @} */
31870 
31871 /*! @name DCHPRI9 - Channel Priority */
31872 /*! @{ */
31873 
31874 #define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
31875 #define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
31876 /*! CHPRI - Channel n Arbitration Priority
31877  */
31878 #define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
31879 
31880 #define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
31881 #define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
31882 /*! GRPPRI - Channel n Current Group Priority
31883  */
31884 #define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
31885 
31886 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
31887 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
31888 /*! DPA - Disable Preempt Ability. This field resets to 0.
31889  *  0b0..Channel n can suspend a lower priority channel
31890  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31891  */
31892 #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
31893 
31894 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
31895 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
31896 /*! ECP - Enable Channel Preemption. This field resets to 0.
31897  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31898  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31899  */
31900 #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
31901 /*! @} */
31902 
31903 /*! @name DCHPRI8 - Channel Priority */
31904 /*! @{ */
31905 
31906 #define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
31907 #define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
31908 /*! CHPRI - Channel n Arbitration Priority
31909  */
31910 #define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
31911 
31912 #define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
31913 #define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
31914 /*! GRPPRI - Channel n Current Group Priority
31915  */
31916 #define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
31917 
31918 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
31919 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
31920 /*! DPA - Disable Preempt Ability. This field resets to 0.
31921  *  0b0..Channel n can suspend a lower priority channel
31922  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31923  */
31924 #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
31925 
31926 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
31927 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
31928 /*! ECP - Enable Channel Preemption. This field resets to 0.
31929  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31930  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31931  */
31932 #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
31933 /*! @} */
31934 
31935 /*! @name DCHPRI15 - Channel Priority */
31936 /*! @{ */
31937 
31938 #define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
31939 #define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
31940 /*! CHPRI - Channel n Arbitration Priority
31941  */
31942 #define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
31943 
31944 #define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
31945 #define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
31946 /*! GRPPRI - Channel n Current Group Priority
31947  */
31948 #define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
31949 
31950 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
31951 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
31952 /*! DPA - Disable Preempt Ability. This field resets to 0.
31953  *  0b0..Channel n can suspend a lower priority channel
31954  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31955  */
31956 #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
31957 
31958 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
31959 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
31960 /*! ECP - Enable Channel Preemption. This field resets to 0.
31961  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31962  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31963  */
31964 #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
31965 /*! @} */
31966 
31967 /*! @name DCHPRI14 - Channel Priority */
31968 /*! @{ */
31969 
31970 #define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
31971 #define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
31972 /*! CHPRI - Channel n Arbitration Priority
31973  */
31974 #define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
31975 
31976 #define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
31977 #define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
31978 /*! GRPPRI - Channel n Current Group Priority
31979  */
31980 #define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
31981 
31982 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
31983 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
31984 /*! DPA - Disable Preempt Ability. This field resets to 0.
31985  *  0b0..Channel n can suspend a lower priority channel
31986  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31987  */
31988 #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
31989 
31990 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
31991 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
31992 /*! ECP - Enable Channel Preemption. This field resets to 0.
31993  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31994  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31995  */
31996 #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
31997 /*! @} */
31998 
31999 /*! @name DCHPRI13 - Channel Priority */
32000 /*! @{ */
32001 
32002 #define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
32003 #define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
32004 /*! CHPRI - Channel n Arbitration Priority
32005  */
32006 #define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
32007 
32008 #define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
32009 #define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
32010 /*! GRPPRI - Channel n Current Group Priority
32011  */
32012 #define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
32013 
32014 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
32015 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
32016 /*! DPA - Disable Preempt Ability. This field resets to 0.
32017  *  0b0..Channel n can suspend a lower priority channel
32018  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32019  */
32020 #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
32021 
32022 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
32023 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
32024 /*! ECP - Enable Channel Preemption. This field resets to 0.
32025  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32026  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32027  */
32028 #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
32029 /*! @} */
32030 
32031 /*! @name DCHPRI12 - Channel Priority */
32032 /*! @{ */
32033 
32034 #define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
32035 #define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
32036 /*! CHPRI - Channel n Arbitration Priority
32037  */
32038 #define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
32039 
32040 #define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
32041 #define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
32042 /*! GRPPRI - Channel n Current Group Priority
32043  */
32044 #define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
32045 
32046 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
32047 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
32048 /*! DPA - Disable Preempt Ability. This field resets to 0.
32049  *  0b0..Channel n can suspend a lower priority channel
32050  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32051  */
32052 #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
32053 
32054 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
32055 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
32056 /*! ECP - Enable Channel Preemption. This field resets to 0.
32057  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32058  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32059  */
32060 #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
32061 /*! @} */
32062 
32063 /*! @name DCHPRI19 - Channel Priority */
32064 /*! @{ */
32065 
32066 #define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
32067 #define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
32068 /*! CHPRI - Channel n Arbitration Priority
32069  */
32070 #define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
32071 
32072 #define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
32073 #define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
32074 /*! GRPPRI - Channel n Current Group Priority
32075  */
32076 #define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
32077 
32078 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
32079 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
32080 /*! DPA - Disable Preempt Ability. This field resets to 0.
32081  *  0b0..Channel n can suspend a lower priority channel
32082  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32083  */
32084 #define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
32085 
32086 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
32087 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
32088 /*! ECP - Enable Channel Preemption. This field resets to 0.
32089  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32090  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32091  */
32092 #define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
32093 /*! @} */
32094 
32095 /*! @name DCHPRI18 - Channel Priority */
32096 /*! @{ */
32097 
32098 #define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
32099 #define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
32100 /*! CHPRI - Channel n Arbitration Priority
32101  */
32102 #define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
32103 
32104 #define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
32105 #define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
32106 /*! GRPPRI - Channel n Current Group Priority
32107  */
32108 #define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
32109 
32110 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
32111 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
32112 /*! DPA - Disable Preempt Ability. This field resets to 0.
32113  *  0b0..Channel n can suspend a lower priority channel
32114  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32115  */
32116 #define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
32117 
32118 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
32119 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
32120 /*! ECP - Enable Channel Preemption. This field resets to 0.
32121  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32122  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32123  */
32124 #define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
32125 /*! @} */
32126 
32127 /*! @name DCHPRI17 - Channel Priority */
32128 /*! @{ */
32129 
32130 #define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
32131 #define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
32132 /*! CHPRI - Channel n Arbitration Priority
32133  */
32134 #define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
32135 
32136 #define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
32137 #define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
32138 /*! GRPPRI - Channel n Current Group Priority
32139  */
32140 #define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
32141 
32142 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
32143 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
32144 /*! DPA - Disable Preempt Ability. This field resets to 0.
32145  *  0b0..Channel n can suspend a lower priority channel
32146  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32147  */
32148 #define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
32149 
32150 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
32151 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
32152 /*! ECP - Enable Channel Preemption. This field resets to 0.
32153  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32154  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32155  */
32156 #define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
32157 /*! @} */
32158 
32159 /*! @name DCHPRI16 - Channel Priority */
32160 /*! @{ */
32161 
32162 #define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
32163 #define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
32164 /*! CHPRI - Channel n Arbitration Priority
32165  */
32166 #define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
32167 
32168 #define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
32169 #define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
32170 /*! GRPPRI - Channel n Current Group Priority
32171  */
32172 #define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
32173 
32174 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
32175 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
32176 /*! DPA - Disable Preempt Ability. This field resets to 0.
32177  *  0b0..Channel n can suspend a lower priority channel
32178  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32179  */
32180 #define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
32181 
32182 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
32183 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
32184 /*! ECP - Enable Channel Preemption. This field resets to 0.
32185  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32186  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32187  */
32188 #define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
32189 /*! @} */
32190 
32191 /*! @name DCHPRI23 - Channel Priority */
32192 /*! @{ */
32193 
32194 #define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
32195 #define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
32196 /*! CHPRI - Channel n Arbitration Priority
32197  */
32198 #define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
32199 
32200 #define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
32201 #define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
32202 /*! GRPPRI - Channel n Current Group Priority
32203  */
32204 #define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
32205 
32206 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
32207 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
32208 /*! DPA - Disable Preempt Ability. This field resets to 0.
32209  *  0b0..Channel n can suspend a lower priority channel
32210  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32211  */
32212 #define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
32213 
32214 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
32215 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
32216 /*! ECP - Enable Channel Preemption. This field resets to 0.
32217  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32218  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32219  */
32220 #define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
32221 /*! @} */
32222 
32223 /*! @name DCHPRI22 - Channel Priority */
32224 /*! @{ */
32225 
32226 #define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
32227 #define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
32228 /*! CHPRI - Channel n Arbitration Priority
32229  */
32230 #define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
32231 
32232 #define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
32233 #define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
32234 /*! GRPPRI - Channel n Current Group Priority
32235  */
32236 #define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
32237 
32238 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
32239 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
32240 /*! DPA - Disable Preempt Ability. This field resets to 0.
32241  *  0b0..Channel n can suspend a lower priority channel
32242  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32243  */
32244 #define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
32245 
32246 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
32247 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
32248 /*! ECP - Enable Channel Preemption. This field resets to 0.
32249  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32250  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32251  */
32252 #define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
32253 /*! @} */
32254 
32255 /*! @name DCHPRI21 - Channel Priority */
32256 /*! @{ */
32257 
32258 #define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
32259 #define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
32260 /*! CHPRI - Channel n Arbitration Priority
32261  */
32262 #define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
32263 
32264 #define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
32265 #define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
32266 /*! GRPPRI - Channel n Current Group Priority
32267  */
32268 #define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
32269 
32270 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
32271 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
32272 /*! DPA - Disable Preempt Ability. This field resets to 0.
32273  *  0b0..Channel n can suspend a lower priority channel
32274  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32275  */
32276 #define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
32277 
32278 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
32279 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
32280 /*! ECP - Enable Channel Preemption. This field resets to 0.
32281  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32282  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32283  */
32284 #define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
32285 /*! @} */
32286 
32287 /*! @name DCHPRI20 - Channel Priority */
32288 /*! @{ */
32289 
32290 #define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
32291 #define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
32292 /*! CHPRI - Channel n Arbitration Priority
32293  */
32294 #define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
32295 
32296 #define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
32297 #define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
32298 /*! GRPPRI - Channel n Current Group Priority
32299  */
32300 #define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
32301 
32302 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
32303 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
32304 /*! DPA - Disable Preempt Ability. This field resets to 0.
32305  *  0b0..Channel n can suspend a lower priority channel
32306  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32307  */
32308 #define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
32309 
32310 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
32311 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
32312 /*! ECP - Enable Channel Preemption. This field resets to 0.
32313  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32314  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32315  */
32316 #define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
32317 /*! @} */
32318 
32319 /*! @name DCHPRI27 - Channel Priority */
32320 /*! @{ */
32321 
32322 #define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
32323 #define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
32324 /*! CHPRI - Channel n Arbitration Priority
32325  */
32326 #define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
32327 
32328 #define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
32329 #define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
32330 /*! GRPPRI - Channel n Current Group Priority
32331  */
32332 #define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
32333 
32334 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
32335 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
32336 /*! DPA - Disable Preempt Ability. This field resets to 0.
32337  *  0b0..Channel n can suspend a lower priority channel
32338  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32339  */
32340 #define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
32341 
32342 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
32343 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
32344 /*! ECP - Enable Channel Preemption. This field resets to 0.
32345  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32346  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32347  */
32348 #define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
32349 /*! @} */
32350 
32351 /*! @name DCHPRI26 - Channel Priority */
32352 /*! @{ */
32353 
32354 #define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
32355 #define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
32356 /*! CHPRI - Channel n Arbitration Priority
32357  */
32358 #define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
32359 
32360 #define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
32361 #define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
32362 /*! GRPPRI - Channel n Current Group Priority
32363  */
32364 #define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
32365 
32366 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
32367 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
32368 /*! DPA - Disable Preempt Ability. This field resets to 0.
32369  *  0b0..Channel n can suspend a lower priority channel
32370  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32371  */
32372 #define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
32373 
32374 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
32375 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
32376 /*! ECP - Enable Channel Preemption. This field resets to 0.
32377  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32378  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32379  */
32380 #define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
32381 /*! @} */
32382 
32383 /*! @name DCHPRI25 - Channel Priority */
32384 /*! @{ */
32385 
32386 #define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
32387 #define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
32388 /*! CHPRI - Channel n Arbitration Priority
32389  */
32390 #define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
32391 
32392 #define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
32393 #define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
32394 /*! GRPPRI - Channel n Current Group Priority
32395  */
32396 #define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
32397 
32398 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
32399 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
32400 /*! DPA - Disable Preempt Ability. This field resets to 0.
32401  *  0b0..Channel n can suspend a lower priority channel
32402  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32403  */
32404 #define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
32405 
32406 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
32407 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
32408 /*! ECP - Enable Channel Preemption. This field resets to 0.
32409  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32410  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32411  */
32412 #define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
32413 /*! @} */
32414 
32415 /*! @name DCHPRI24 - Channel Priority */
32416 /*! @{ */
32417 
32418 #define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
32419 #define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
32420 /*! CHPRI - Channel n Arbitration Priority
32421  */
32422 #define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
32423 
32424 #define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
32425 #define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
32426 /*! GRPPRI - Channel n Current Group Priority
32427  */
32428 #define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
32429 
32430 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
32431 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
32432 /*! DPA - Disable Preempt Ability. This field resets to 0.
32433  *  0b0..Channel n can suspend a lower priority channel
32434  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32435  */
32436 #define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
32437 
32438 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
32439 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
32440 /*! ECP - Enable Channel Preemption. This field resets to 0.
32441  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32442  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32443  */
32444 #define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
32445 /*! @} */
32446 
32447 /*! @name DCHPRI31 - Channel Priority */
32448 /*! @{ */
32449 
32450 #define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
32451 #define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
32452 /*! CHPRI - Channel n Arbitration Priority
32453  */
32454 #define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
32455 
32456 #define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
32457 #define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
32458 /*! GRPPRI - Channel n Current Group Priority
32459  */
32460 #define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
32461 
32462 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
32463 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
32464 /*! DPA - Disable Preempt Ability. This field resets to 0.
32465  *  0b0..Channel n can suspend a lower priority channel
32466  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32467  */
32468 #define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
32469 
32470 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
32471 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
32472 /*! ECP - Enable Channel Preemption. This field resets to 0.
32473  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32474  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32475  */
32476 #define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
32477 /*! @} */
32478 
32479 /*! @name DCHPRI30 - Channel Priority */
32480 /*! @{ */
32481 
32482 #define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
32483 #define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
32484 /*! CHPRI - Channel n Arbitration Priority
32485  */
32486 #define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
32487 
32488 #define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
32489 #define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
32490 /*! GRPPRI - Channel n Current Group Priority
32491  */
32492 #define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
32493 
32494 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
32495 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
32496 /*! DPA - Disable Preempt Ability. This field resets to 0.
32497  *  0b0..Channel n can suspend a lower priority channel
32498  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32499  */
32500 #define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
32501 
32502 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
32503 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
32504 /*! ECP - Enable Channel Preemption. This field resets to 0.
32505  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32506  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32507  */
32508 #define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
32509 /*! @} */
32510 
32511 /*! @name DCHPRI29 - Channel Priority */
32512 /*! @{ */
32513 
32514 #define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
32515 #define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
32516 /*! CHPRI - Channel n Arbitration Priority
32517  */
32518 #define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
32519 
32520 #define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
32521 #define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
32522 /*! GRPPRI - Channel n Current Group Priority
32523  */
32524 #define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
32525 
32526 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
32527 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
32528 /*! DPA - Disable Preempt Ability. This field resets to 0.
32529  *  0b0..Channel n can suspend a lower priority channel
32530  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32531  */
32532 #define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
32533 
32534 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
32535 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
32536 /*! ECP - Enable Channel Preemption. This field resets to 0.
32537  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32538  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32539  */
32540 #define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
32541 /*! @} */
32542 
32543 /*! @name DCHPRI28 - Channel Priority */
32544 /*! @{ */
32545 
32546 #define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
32547 #define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
32548 /*! CHPRI - Channel n Arbitration Priority
32549  */
32550 #define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
32551 
32552 #define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
32553 #define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
32554 /*! GRPPRI - Channel n Current Group Priority
32555  */
32556 #define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
32557 
32558 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
32559 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
32560 /*! DPA - Disable Preempt Ability. This field resets to 0.
32561  *  0b0..Channel n can suspend a lower priority channel
32562  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
32563  */
32564 #define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
32565 
32566 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
32567 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
32568 /*! ECP - Enable Channel Preemption. This field resets to 0.
32569  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
32570  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
32571  */
32572 #define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
32573 /*! @} */
32574 
32575 /*! @name SADDR - TCD Source Address */
32576 /*! @{ */
32577 
32578 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
32579 #define DMA_SADDR_SADDR_SHIFT                    (0U)
32580 /*! SADDR - Source Address
32581  */
32582 #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
32583 /*! @} */
32584 
32585 /* The count of DMA_SADDR */
32586 #define DMA_SADDR_COUNT                          (32U)
32587 
32588 /*! @name SOFF - TCD Signed Source Address Offset */
32589 /*! @{ */
32590 
32591 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
32592 #define DMA_SOFF_SOFF_SHIFT                      (0U)
32593 /*! SOFF - Source address signed offset
32594  */
32595 #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
32596 /*! @} */
32597 
32598 /* The count of DMA_SOFF */
32599 #define DMA_SOFF_COUNT                           (32U)
32600 
32601 /*! @name ATTR - TCD Transfer Attributes */
32602 /*! @{ */
32603 
32604 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
32605 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
32606 /*! DSIZE - Destination data transfer size
32607  */
32608 #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
32609 
32610 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
32611 #define DMA_ATTR_DMOD_SHIFT                      (3U)
32612 /*! DMOD - Destination Address Modulo
32613  */
32614 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
32615 
32616 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
32617 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
32618 /*! SSIZE - Source data transfer size
32619  *  0b000..8-bit
32620  *  0b001..16-bit
32621  *  0b010..32-bit
32622  *  0b011..64-bit
32623  *  0b100..Reserved
32624  *  0b101..32-byte burst (4 beats of 64 bits)
32625  *  0b110..Reserved
32626  *  0b111..Reserved
32627  */
32628 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
32629 
32630 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
32631 #define DMA_ATTR_SMOD_SHIFT                      (11U)
32632 /*! SMOD - Source Address Modulo
32633  *  0b00000..Source address modulo feature is disabled
32634  *  0b00001-0b11111..Value defines address range used to set up circular data queue
32635  */
32636 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
32637 /*! @} */
32638 
32639 /* The count of DMA_ATTR */
32640 #define DMA_ATTR_COUNT                           (32U)
32641 
32642 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
32643 /*! @{ */
32644 
32645 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
32646 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
32647 /*! NBYTES - Minor Byte Transfer Count
32648  */
32649 #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
32650 /*! @} */
32651 
32652 /* The count of DMA_NBYTES_MLNO */
32653 #define DMA_NBYTES_MLNO_COUNT                    (32U)
32654 
32655 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
32656 /*! @{ */
32657 
32658 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
32659 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
32660 /*! NBYTES - Minor Byte Transfer Count
32661  */
32662 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
32663 
32664 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
32665 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
32666 /*! DMLOE - Destination Minor Loop Offset Enable
32667  *  0b0..The minor loop offset is not applied to the DADDR
32668  *  0b1..The minor loop offset is applied to the DADDR
32669  */
32670 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
32671 
32672 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
32673 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
32674 /*! SMLOE - Source Minor Loop Offset Enable
32675  *  0b0..The minor loop offset is not applied to the SADDR
32676  *  0b1..The minor loop offset is applied to the SADDR
32677  */
32678 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
32679 /*! @} */
32680 
32681 /* The count of DMA_NBYTES_MLOFFNO */
32682 #define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
32683 
32684 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
32685 /*! @{ */
32686 
32687 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
32688 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
32689 /*! NBYTES - Minor Byte Transfer Count
32690  */
32691 #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
32692 
32693 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
32694 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
32695 /*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the
32696  *    source or destination address to form the next-state value after the minor loop completes.
32697  */
32698 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
32699 
32700 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
32701 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
32702 /*! DMLOE - Destination Minor Loop Offset Enable
32703  *  0b0..The minor loop offset is not applied to the DADDR
32704  *  0b1..The minor loop offset is applied to the DADDR
32705  */
32706 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
32707 
32708 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
32709 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
32710 /*! SMLOE - Source Minor Loop Offset Enable
32711  *  0b0..The minor loop offset is not applied to the SADDR
32712  *  0b1..The minor loop offset is applied to the SADDR
32713  */
32714 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
32715 /*! @} */
32716 
32717 /* The count of DMA_NBYTES_MLOFFYES */
32718 #define DMA_NBYTES_MLOFFYES_COUNT                (32U)
32719 
32720 /*! @name SLAST - TCD Last Source Address Adjustment */
32721 /*! @{ */
32722 
32723 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
32724 #define DMA_SLAST_SLAST_SHIFT                    (0U)
32725 /*! SLAST - Last Source Address Adjustment
32726  */
32727 #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
32728 /*! @} */
32729 
32730 /* The count of DMA_SLAST */
32731 #define DMA_SLAST_COUNT                          (32U)
32732 
32733 /*! @name DADDR - TCD Destination Address */
32734 /*! @{ */
32735 
32736 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
32737 #define DMA_DADDR_DADDR_SHIFT                    (0U)
32738 /*! DADDR - Destination Address
32739  */
32740 #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
32741 /*! @} */
32742 
32743 /* The count of DMA_DADDR */
32744 #define DMA_DADDR_COUNT                          (32U)
32745 
32746 /*! @name DOFF - TCD Signed Destination Address Offset */
32747 /*! @{ */
32748 
32749 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
32750 #define DMA_DOFF_DOFF_SHIFT                      (0U)
32751 /*! DOFF - Destination Address Signed Offset
32752  */
32753 #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
32754 /*! @} */
32755 
32756 /* The count of DMA_DOFF */
32757 #define DMA_DOFF_COUNT                           (32U)
32758 
32759 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
32760 /*! @{ */
32761 
32762 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
32763 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
32764 /*! CITER - Current Major Iteration Count
32765  */
32766 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
32767 
32768 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
32769 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
32770 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
32771  *  0b0..Channel-to-channel linking is disabled
32772  *  0b1..Channel-to-channel linking is enabled
32773  */
32774 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
32775 /*! @} */
32776 
32777 /* The count of DMA_CITER_ELINKNO */
32778 #define DMA_CITER_ELINKNO_COUNT                  (32U)
32779 
32780 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
32781 /*! @{ */
32782 
32783 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
32784 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
32785 /*! CITER - Current Major Iteration Count
32786  */
32787 #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
32788 
32789 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
32790 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
32791 /*! LINKCH - Minor Loop Link Channel Number
32792  */
32793 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
32794 
32795 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
32796 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
32797 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
32798  *  0b0..Channel-to-channel linking is disabled
32799  *  0b1..Channel-to-channel linking is enabled
32800  */
32801 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
32802 /*! @} */
32803 
32804 /* The count of DMA_CITER_ELINKYES */
32805 #define DMA_CITER_ELINKYES_COUNT                 (32U)
32806 
32807 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
32808 /*! @{ */
32809 
32810 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
32811 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
32812 /*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)
32813  */
32814 #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
32815 /*! @} */
32816 
32817 /* The count of DMA_DLAST_SGA */
32818 #define DMA_DLAST_SGA_COUNT                      (32U)
32819 
32820 /*! @name CSR - TCD Control and Status */
32821 /*! @{ */
32822 
32823 #define DMA_CSR_START_MASK                       (0x1U)
32824 #define DMA_CSR_START_SHIFT                      (0U)
32825 /*! START - Channel Start
32826  *  0b0..Channel is not explicitly started
32827  *  0b1..Channel is explicitly started via a software initiated service request
32828  */
32829 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
32830 
32831 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
32832 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
32833 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
32834  *  0b0..End of major loop interrupt is disabled
32835  *  0b1..End of major loop interrupt is enabled
32836  */
32837 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
32838 
32839 #define DMA_CSR_INTHALF_MASK                     (0x4U)
32840 #define DMA_CSR_INTHALF_SHIFT                    (2U)
32841 /*! INTHALF - Enable an interrupt when major counter is half complete.
32842  *  0b0..Half-point interrupt is disabled
32843  *  0b1..Half-point interrupt is enabled
32844  */
32845 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
32846 
32847 #define DMA_CSR_DREQ_MASK                        (0x8U)
32848 #define DMA_CSR_DREQ_SHIFT                       (3U)
32849 /*! DREQ - Disable Request
32850  *  0b0..The channel's ERQ field is not affected
32851  *  0b1..The channel's ERQ field value changes to 0 when the major loop is complete
32852  */
32853 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
32854 
32855 #define DMA_CSR_ESG_MASK                         (0x10U)
32856 #define DMA_CSR_ESG_SHIFT                        (4U)
32857 /*! ESG - Enable Scatter/Gather Processing
32858  *  0b0..The current channel's TCD is normal format
32859  *  0b1..The current channel's TCD specifies a scatter gather format
32860  */
32861 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
32862 
32863 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
32864 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
32865 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
32866  *  0b0..Channel-to-channel linking is disabled
32867  *  0b1..Channel-to-channel linking is enabled
32868  */
32869 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
32870 
32871 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
32872 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
32873 /*! ACTIVE - Channel Active
32874  */
32875 #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
32876 
32877 #define DMA_CSR_DONE_MASK                        (0x80U)
32878 #define DMA_CSR_DONE_SHIFT                       (7U)
32879 /*! DONE - Channel Done
32880  */
32881 #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
32882 
32883 #define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
32884 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
32885 /*! MAJORLINKCH - Major Loop Link Channel Number
32886  */
32887 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
32888 
32889 #define DMA_CSR_BWC_MASK                         (0xC000U)
32890 #define DMA_CSR_BWC_SHIFT                        (14U)
32891 /*! BWC - Bandwidth Control
32892  *  0b00..No eDMA engine stalls
32893  *  0b01..Reserved
32894  *  0b10..eDMA engine stalls for 4 cycles after each R/W
32895  *  0b11..eDMA engine stalls for 8 cycles after each R/W
32896  */
32897 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
32898 /*! @} */
32899 
32900 /* The count of DMA_CSR */
32901 #define DMA_CSR_COUNT                            (32U)
32902 
32903 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
32904 /*! @{ */
32905 
32906 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
32907 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
32908 /*! BITER - Starting Major Iteration Count
32909  */
32910 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
32911 
32912 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
32913 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
32914 /*! ELINK - Enables channel-to-channel linking on minor loop complete
32915  *  0b0..Channel-to-channel linking is disabled
32916  *  0b1..Channel-to-channel linking is enabled
32917  */
32918 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
32919 /*! @} */
32920 
32921 /* The count of DMA_BITER_ELINKNO */
32922 #define DMA_BITER_ELINKNO_COUNT                  (32U)
32923 
32924 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
32925 /*! @{ */
32926 
32927 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
32928 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
32929 /*! BITER - Starting major iteration count
32930  */
32931 #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
32932 
32933 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
32934 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
32935 /*! LINKCH - Link Channel Number
32936  */
32937 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
32938 
32939 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
32940 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
32941 /*! ELINK - Enables channel-to-channel linking on minor loop complete
32942  *  0b0..Channel-to-channel linking is disabled
32943  *  0b1..Channel-to-channel linking is enabled
32944  */
32945 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
32946 /*! @} */
32947 
32948 /* The count of DMA_BITER_ELINKYES */
32949 #define DMA_BITER_ELINKYES_COUNT                 (32U)
32950 
32951 
32952 /*!
32953  * @}
32954  */ /* end of group DMA_Register_Masks */
32955 
32956 
32957 /* DMA - Peripheral instance base addresses */
32958 /** Peripheral DMA0 base address */
32959 #define DMA0_BASE                                (0x40070000u)
32960 /** Peripheral DMA0 base pointer */
32961 #define DMA0                                     ((DMA_Type *)DMA0_BASE)
32962 /** Array initializer of DMA peripheral base addresses */
32963 #define DMA_BASE_ADDRS                           { DMA0_BASE }
32964 /** Array initializer of DMA peripheral base pointers */
32965 #define DMA_BASE_PTRS                            { DMA0 }
32966 /** Interrupt vectors for the DMA peripheral type */
32967 #define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
32968 #define DMA_ERROR_IRQS                           { DMA_ERROR_IRQn }
32969 
32970 /*!
32971  * @}
32972  */ /* end of group DMA_Peripheral_Access_Layer */
32973 
32974 
32975 /* ----------------------------------------------------------------------------
32976    -- DMAMUX Peripheral Access Layer
32977    ---------------------------------------------------------------------------- */
32978 
32979 /*!
32980  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
32981  * @{
32982  */
32983 
32984 /** DMAMUX - Register Layout Typedef */
32985 typedef struct {
32986   __IO uint32_t CHCFG[32];                         /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
32987 } DMAMUX_Type;
32988 
32989 /* ----------------------------------------------------------------------------
32990    -- DMAMUX Register Masks
32991    ---------------------------------------------------------------------------- */
32992 
32993 /*!
32994  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
32995  * @{
32996  */
32997 
32998 /*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
32999 /*! @{ */
33000 
33001 #define DMAMUX_CHCFG_SOURCE_MASK                 (0xFFU)
33002 #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
33003 /*! SOURCE - DMA Channel Source (Slot Number)
33004  */
33005 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
33006 
33007 #define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
33008 #define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
33009 /*! A_ON - DMA Channel Always Enable
33010  *  0b0..DMA Channel Always ON function is disabled
33011  *  0b1..DMA Channel Always ON function is enabled
33012  */
33013 #define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
33014 
33015 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
33016 #define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
33017 /*! TRIG - DMA Channel Trigger Enable
33018  *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
33019  *       specified source to the DMA channel. (Normal mode)
33020  *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
33021  */
33022 #define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
33023 
33024 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
33025 #define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
33026 /*! ENBL - DMA Mux Channel Enable
33027  *  0b0..DMA Mux channel is disabled
33028  *  0b1..DMA Mux channel is enabled
33029  */
33030 #define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
33031 /*! @} */
33032 
33033 /* The count of DMAMUX_CHCFG */
33034 #define DMAMUX_CHCFG_COUNT                       (32U)
33035 
33036 
33037 /*!
33038  * @}
33039  */ /* end of group DMAMUX_Register_Masks */
33040 
33041 
33042 /* DMAMUX - Peripheral instance base addresses */
33043 /** Peripheral DMAMUX0 base address */
33044 #define DMAMUX0_BASE                             (0x40074000u)
33045 /** Peripheral DMAMUX0 base pointer */
33046 #define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
33047 /** Array initializer of DMAMUX peripheral base addresses */
33048 #define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
33049 /** Array initializer of DMAMUX peripheral base pointers */
33050 #define DMAMUX_BASE_PTRS                         { DMAMUX0 }
33051 
33052 /*!
33053  * @}
33054  */ /* end of group DMAMUX_Peripheral_Access_Layer */
33055 
33056 
33057 /* ----------------------------------------------------------------------------
33058    -- DSI_HOST Peripheral Access Layer
33059    ---------------------------------------------------------------------------- */
33060 
33061 /*!
33062  * @addtogroup DSI_HOST_Peripheral_Access_Layer DSI_HOST Peripheral Access Layer
33063  * @{
33064  */
33065 
33066 /** DSI_HOST - Register Layout Typedef */
33067 typedef struct {
33068   __IO uint32_t CFG_NUM_LANES;                     /**< CFG_NUM_LANES, offset: 0x0 */
33069   __IO uint32_t CFG_NONCONTINUOUS_CLK;             /**< CFG_NONCONTINUOUS_CLK, offset: 0x4 */
33070   __IO uint32_t CFG_T_PRE;                         /**< CFG_T_PRE, offset: 0x8 */
33071   __IO uint32_t CFG_T_POST;                        /**< CFG_T_POST, offset: 0xC */
33072   __IO uint32_t CFG_TX_GAP;                        /**< CFG_TX_GAP, offset: 0x10 */
33073   __IO uint32_t CFG_AUTOINSERT_EOTP;               /**< CFG_AUTOINSERT_ETOP, offset: 0x14 */
33074   __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;         /**< CFG_EXTRA_CMDS_AFTER_ETOP, offset: 0x18 */
33075   __IO uint32_t CFG_HTX_TO_COUNT;                  /**< CFG_HTX_TO_COUNT, offset: 0x1C */
33076   __IO uint32_t CFG_LRX_H_TO_COUNT;                /**< CFG_LRX_H_TO_COUNT, offset: 0x20 */
33077   __IO uint32_t CFG_BTA_H_TO_COUNT;                /**< CFG_BTA_H_TO_COUNT, offset: 0x24 */
33078   __IO uint32_t CFG_TWAKEUP;                       /**< CFG_TWAKEUP, offset: 0x28 */
33079   __I  uint32_t CFG_STATUS_OUT;                    /**< CFG_STATUS_OUT, offset: 0x2C */
33080   __I  uint32_t RX_ERROR_STATUS;                   /**< RX_ERROR_STATUS, offset: 0x30 */
33081 } DSI_HOST_Type;
33082 
33083 /* ----------------------------------------------------------------------------
33084    -- DSI_HOST Register Masks
33085    ---------------------------------------------------------------------------- */
33086 
33087 /*!
33088  * @addtogroup DSI_HOST_Register_Masks DSI_HOST Register Masks
33089  * @{
33090  */
33091 
33092 /*! @name CFG_NUM_LANES - CFG_NUM_LANES */
33093 /*! @{ */
33094 
33095 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK    (0x3U)
33096 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT   (0U)
33097 /*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data.
33098  *  0b00..1 lane
33099  *  0b01..2 lanes
33100  */
33101 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
33102 /*! @} */
33103 
33104 /*! @name CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK */
33105 /*! @{ */
33106 
33107 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
33108 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
33109 /*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous
33110  *    clock mode, the high speed clock will transition into low power mode between transmissions.
33111  *  0b0..Continuous high speed clock
33112  *  0b1..Non-Continuous high speed clock
33113  */
33114 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
33115 /*! @} */
33116 
33117 /*! @name CFG_T_PRE - CFG_T_PRE */
33118 /*! @{ */
33119 
33120 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK      (0xFFU)
33121 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT     (0U)
33122 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
33123  *    wait after enabling the clock lane for HS operation before enabling the data lanes for HS
33124  *    operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this
33125  *    port is 1.
33126  */
33127 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
33128 /*! @} */
33129 
33130 /*! @name CFG_T_POST - CFG_T_POST */
33131 /*! @{ */
33132 
33133 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK     (0xFFU)
33134 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT    (0U)
33135 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting
33136  *    the clock lane into LP mode after the data lanes have been detected to be in Stop State. This
33137  *    setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE
33138  *    requirement for the clock lane before the data lane is allowed to change from LP11 to start a high
33139  *    speed transmission. The minimum value for this port is 1.
33140  */
33141 #define DSI_HOST_CFG_T_POST_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
33142 /*! @} */
33143 
33144 /*! @name CFG_TX_GAP - CFG_TX_GAP */
33145 /*! @{ */
33146 
33147 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK     (0xFFU)
33148 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT    (0U)
33149 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
33150  *    wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode
33151  *    again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this
33152  *    port is 1.
33153  */
33154 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
33155 /*! @} */
33156 
33157 /*! @name CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP */
33158 /*! @{ */
33159 
33160 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
33161 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
33162 /*! AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
33163  *  0b0..EoTp is not automatically inserted
33164  *  0b1..EoTp is automatically inserted
33165  */
33166 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
33167 /*! @} */
33168 
33169 /*! @name CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP */
33170 /*! @{ */
33171 
33172 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
33173 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
33174 /*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after
33175  *    the end of a packet. The value is the number of extra EOTP packets sent.
33176  */
33177 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
33178 /*! @} */
33179 
33180 /*! @name CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT */
33181 /*! @{ */
33182 
33183 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK     (0xFFFFFFU)
33184 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT    (0U)
33185 /*! COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods
33186  *    that once reached will initiate a timeout error and follow the recovery procedure documented in
33187  *    the DSI specification.
33188  */
33189 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
33190 /*! @} */
33191 
33192 /*! @name CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT */
33193 /*! @{ */
33194 
33195 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
33196 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT  (0U)
33197 /*! COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that
33198  *    once reached will initiate a timeout error and follow the recovery procedure documented in
33199  *    the DSI specification.
33200  */
33201 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
33202 /*! @} */
33203 
33204 /*! @name CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT */
33205 /*! @{ */
33206 
33207 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
33208 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT  (0U)
33209 /*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods
33210  *    that once reached will initiate a timeout error.
33211  */
33212 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
33213 /*! @} */
33214 
33215 /*! @name CFG_TWAKEUP - CFG_TWAKEUP */
33216 /*! @{ */
33217 
33218 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK    (0x7FFFFU)
33219 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT   (0U)
33220 /*! NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a
33221  *    clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum
33222  *    of 1ms in Mark-1 state after leaving ULPS.
33223  */
33224 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
33225 /*! @} */
33226 
33227 /*! @name CFG_STATUS_OUT - CFG_STATUS_OUT */
33228 /*! @{ */
33229 
33230 #define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK      (0xFFFFFFFFU)
33231 #define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT     (0U)
33232 /*! STATUS - Status Register
33233  */
33234 #define DSI_HOST_CFG_STATUS_OUT_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
33235 /*! @} */
33236 
33237 /*! @name RX_ERROR_STATUS - RX_ERROR_STATUS */
33238 /*! @{ */
33239 
33240 #define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK     (0x7FFU)
33241 #define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT    (0U)
33242 /*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators
33243  */
33244 #define DSI_HOST_RX_ERROR_STATUS_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)
33245 /*! @} */
33246 
33247 
33248 /*!
33249  * @}
33250  */ /* end of group DSI_HOST_Register_Masks */
33251 
33252 
33253 /* DSI_HOST - Peripheral instance base addresses */
33254 /** Peripheral DSI_HOST base address */
33255 #define DSI_HOST_BASE                            (0x4080C000u)
33256 /** Peripheral DSI_HOST base pointer */
33257 #define DSI_HOST                                 ((DSI_HOST_Type *)DSI_HOST_BASE)
33258 /** Array initializer of DSI_HOST peripheral base addresses */
33259 #define DSI_HOST_BASE_ADDRS                      { DSI_HOST_BASE }
33260 /** Array initializer of DSI_HOST peripheral base pointers */
33261 #define DSI_HOST_BASE_PTRS                       { DSI_HOST }
33262 /** Interrupt vectors for the DSI_HOST peripheral type */
33263 #define DSI_HOST_DSI_IRQS                        { MIPI_DSI_IRQn }
33264 
33265 /*!
33266  * @}
33267  */ /* end of group DSI_HOST_Peripheral_Access_Layer */
33268 
33269 
33270 /* ----------------------------------------------------------------------------
33271    -- DSI_HOST_APB_PKT_IF Peripheral Access Layer
33272    ---------------------------------------------------------------------------- */
33273 
33274 /*!
33275  * @addtogroup DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer DSI_HOST_APB_PKT_IF Peripheral Access Layer
33276  * @{
33277  */
33278 
33279 /** DSI_HOST_APB_PKT_IF - Register Layout Typedef */
33280 typedef struct {
33281   __IO uint32_t TX_PAYLOAD;                        /**< TX_PAYLOAD, offset: 0x0 */
33282   __IO uint32_t PKT_CONTROL;                       /**< PKT_CONTROL, offset: 0x4 */
33283   __IO uint32_t SEND_PACKET;                       /**< SEND_PACKET, offset: 0x8 */
33284   __I  uint32_t PKT_STATUS;                        /**< PKT_STATUS, offset: 0xC */
33285   __I  uint32_t PKT_FIFO_WR_LEVEL;                 /**< PKT_FIFO_WR_LEVEL, offset: 0x10 */
33286   __I  uint32_t PKT_FIFO_RD_LEVEL;                 /**< PKT_FIFO_RD_LEVEL, offset: 0x14 */
33287   __I  uint32_t PKT_RX_PAYLOAD;                    /**< PKT_RX_PAYLOAD, offset: 0x18 */
33288   __I  uint32_t PKT_RX_PKT_HEADER;                 /**< PKT_RX_PKT_HEADER, offset: 0x1C */
33289   __I  uint32_t IRQ_STATUS;                        /**< IRQ_STATUS, offset: 0x20 */
33290   __I  uint32_t IRQ_STATUS2;                       /**< IRQ_STATUS2, offset: 0x24 */
33291   __IO uint32_t IRQ_MASK;                          /**< IRQ_MASK, offset: 0x28 */
33292   __IO uint32_t IRQ_MASK2;                         /**< IRQ_MASK2, offset: 0x2C */
33293 } DSI_HOST_APB_PKT_IF_Type;
33294 
33295 /* ----------------------------------------------------------------------------
33296    -- DSI_HOST_APB_PKT_IF Register Masks
33297    ---------------------------------------------------------------------------- */
33298 
33299 /*!
33300  * @addtogroup DSI_HOST_APB_PKT_IF_Register_Masks DSI_HOST_APB_PKT_IF Register Masks
33301  * @{
33302  */
33303 
33304 /*! @name TX_PAYLOAD - TX_PAYLOAD */
33305 /*! @{ */
33306 
33307 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
33308 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U)
33309 /*! PAYLOAD - Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values.
33310  */
33311 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK)
33312 /*! @} */
33313 
33314 /*! @name PKT_CONTROL - PKT_CONTROL */
33315 /*! @{ */
33316 
33317 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU)
33318 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U)
33319 /*! CTRL - Tx packet control
33320  */
33321 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK)
33322 /*! @} */
33323 
33324 /*! @name SEND_PACKET - SEND_PACKET */
33325 /*! @{ */
33326 
33327 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U)
33328 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U)
33329 /*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
33330  *  0b0..Packet not sent
33331  *  0b1..Packet is sent
33332  */
33333 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK)
33334 /*! @} */
33335 
33336 /*! @name PKT_STATUS - PKT_STATUS */
33337 /*! @{ */
33338 
33339 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU)
33340 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U)
33341 /*! STATUS - Status of APB to packet interface.
33342  */
33343 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK)
33344 /*! @} */
33345 
33346 /*! @name PKT_FIFO_WR_LEVEL - PKT_FIFO_WR_LEVEL */
33347 /*! @{ */
33348 
33349 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU)
33350 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
33351 /*! WR - Write level of APB to pkt interface FIFO
33352  */
33353 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK)
33354 /*! @} */
33355 
33356 /*! @name PKT_FIFO_RD_LEVEL - PKT_FIFO_RD_LEVEL */
33357 /*! @{ */
33358 
33359 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU)
33360 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
33361 /*! RD - Read level of APB to pkt interface FIFO
33362  */
33363 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK)
33364 /*! @} */
33365 
33366 /*! @name PKT_RX_PAYLOAD - PKT_RX_PAYLOAD */
33367 /*! @{ */
33368 
33369 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
33370 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
33371 /*! PAYLOAD - APB to pkt interface Rx payload read
33372  */
33373 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK)
33374 /*! @} */
33375 
33376 /*! @name PKT_RX_PKT_HEADER - PKT_RX_PKT_HEADER */
33377 /*! @{ */
33378 
33379 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
33380 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
33381 /*! HEADER - APB to pkt interface Rx packet header
33382  */
33383 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK)
33384 /*! @} */
33385 
33386 /*! @name IRQ_STATUS - IRQ_STATUS */
33387 /*! @{ */
33388 
33389 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU)
33390 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U)
33391 /*! STATUS - Status of APB to packet interface.
33392  */
33393 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK)
33394 /*! @} */
33395 
33396 /*! @name IRQ_STATUS2 - IRQ_STATUS2 */
33397 /*! @{ */
33398 
33399 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U)
33400 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U)
33401 /*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
33402  *    Reading dsi_host_irq_status will clear both status and status2.
33403  */
33404 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK)
33405 /*! @} */
33406 
33407 /*! @name IRQ_MASK - IRQ_MASK */
33408 /*! @{ */
33409 
33410 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK   (0xFFFFFFFFU)
33411 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT  (0U)
33412 /*! MASK - IRQ Mask
33413  */
33414 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK)
33415 /*! @} */
33416 
33417 /*! @name IRQ_MASK2 - IRQ_MASK2 */
33418 /*! @{ */
33419 
33420 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U)
33421 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U)
33422 /*! MASK2 - IRQ mask 2
33423  */
33424 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK)
33425 /*! @} */
33426 
33427 
33428 /*!
33429  * @}
33430  */ /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */
33431 
33432 
33433 /* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
33434 /** Peripheral DSI_HOST_APB_PKT_IF base address */
33435 #define DSI_HOST_APB_PKT_IF_BASE                 (0x4080C280u)
33436 /** Peripheral DSI_HOST_APB_PKT_IF base pointer */
33437 #define DSI_HOST_APB_PKT_IF                      ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
33438 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base addresses */
33439 #define DSI_HOST_APB_PKT_IF_BASE_ADDRS           { DSI_HOST_APB_PKT_IF_BASE }
33440 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base pointers */
33441 #define DSI_HOST_APB_PKT_IF_BASE_PTRS            { DSI_HOST_APB_PKT_IF }
33442 
33443 /*!
33444  * @}
33445  */ /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
33446 
33447 
33448 /* ----------------------------------------------------------------------------
33449    -- DSI_HOST_DPI_INTFC Peripheral Access Layer
33450    ---------------------------------------------------------------------------- */
33451 
33452 /*!
33453  * @addtogroup DSI_HOST_DPI_INTFC_Peripheral_Access_Layer DSI_HOST_DPI_INTFC Peripheral Access Layer
33454  * @{
33455  */
33456 
33457 /** DSI_HOST_DPI_INTFC - Register Layout Typedef */
33458 typedef struct {
33459   __IO uint32_t PIXEL_PAYLOAD_SIZE;                /**< PEXEL_PAYLOAD_SIZE, offset: 0x0 */
33460   __IO uint32_t PIXEL_FIFO_SEND_LEVEL;             /**< PIXEL_FIFO_SEND_LEVEL, offset: 0x4 */
33461   __IO uint32_t INTERFACE_COLOR_CODING;            /**< INTERFACE_COLOR_CODING, offset: 0x8 */
33462   __IO uint32_t PIXEL_FORMAT;                      /**< PIXEL_FORMAT, offset: 0xC */
33463   __IO uint32_t VSYNC_POLARITY;                    /**< VSYNC_POLARITY, offset: 0x10 */
33464   __IO uint32_t HSYNC_POLARITY;                    /**< HSYNC_POLARITY, offset: 0x14 */
33465   __IO uint32_t VIDEO_MODE;                        /**< VIDEO_MODE, offset: 0x18 */
33466   __IO uint32_t HFP;                               /**< HFP, offset: 0x1C */
33467   __IO uint32_t HBP;                               /**< HBP, offset: 0x20 */
33468   __IO uint32_t HSA;                               /**< HSA, offset: 0x24 */
33469   __IO uint32_t ENABLE_MULT_PKTS;                  /**< ENABLE_MULT_PKTS, offset: 0x28 */
33470   __IO uint32_t VBP;                               /**< VBP, offset: 0x2C */
33471   __IO uint32_t VFP;                               /**< VFP, offset: 0x30 */
33472   __IO uint32_t BLLP_MODE;                         /**< BLLP_MODE, offset: 0x34 */
33473   __IO uint32_t USE_NULL_PKT_BLLP;                 /**< USE_NULL_PKT_BLLP, offset: 0x38 */
33474   __IO uint32_t VACTIVE;                           /**< VACTIVE, offset: 0x3C */
33475 } DSI_HOST_DPI_INTFC_Type;
33476 
33477 /* ----------------------------------------------------------------------------
33478    -- DSI_HOST_DPI_INTFC Register Masks
33479    ---------------------------------------------------------------------------- */
33480 
33481 /*!
33482  * @addtogroup DSI_HOST_DPI_INTFC_Register_Masks DSI_HOST_DPI_INTFC Register Masks
33483  * @{
33484  */
33485 
33486 /*! @name PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE */
33487 /*! @{ */
33488 
33489 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
33490 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
33491 /*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be
33492  *    evenly divisible by the line size (in pixels).
33493  */
33494 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
33495 /*! @} */
33496 
33497 /*! @name PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL */
33498 /*! @{ */
33499 
33500 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
33501 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
33502 /*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of
33503  *    DPI pixels before initiating a DSI packet. This configuration port controls the level at which
33504  *    the DPI Host bridge begins sending pixels.
33505  */
33506 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
33507 /*! @} */
33508 
33509 /*! @name INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING */
33510 /*! @{ */
33511 
33512 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
33513 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
33514 /*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
33515  *  0b000..16-bit Configuration 1
33516  *  0b001..16-bit Configuration 2
33517  *  0b010..16-bit Configuration 3
33518  *  0b011..18-bit Configuration 1
33519  *  0b100..18-bit Configuration 2
33520  *  0b101..24-bit
33521  *  0b110, 0b111..Reserved
33522  */
33523 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
33524 /*! @} */
33525 
33526 /*! @name PIXEL_FORMAT - PIXEL_FORMAT */
33527 /*! @{ */
33528 
33529 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
33530 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
33531 /*! PIXEL_FORMAT - Sets the DSI packet type of the pixels
33532  *  0b00..16 bit
33533  *  0b01..18 bit
33534  *  0b10..18 bit loosely packed
33535  *  0b11..24 bit
33536  */
33537 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
33538 /*! @} */
33539 
33540 /*! @name VSYNC_POLARITY - VSYNC_POLARITY */
33541 /*! @{ */
33542 
33543 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
33544 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
33545 /*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input
33546  *  0b0..active low
33547  *  0b1..active high
33548  */
33549 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
33550 /*! @} */
33551 
33552 /*! @name HSYNC_POLARITY - HSYNC_POLARITY */
33553 /*! @{ */
33554 
33555 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
33556 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
33557 /*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input
33558  *  0b0..active low
33559  *  0b1..active high
33560  */
33561 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
33562 /*! @} */
33563 
33564 /*! @name VIDEO_MODE - VIDEO_MODE */
33565 /*! @{ */
33566 
33567 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
33568 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
33569 /*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for.
33570  *  0b00..Non-Burst mode with Sync Pulses
33571  *  0b01..Non-Burst mode with Sync Events
33572  *  0b10..Burst mode
33573  *  0b11..Reserved, not valid
33574  */
33575 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
33576 /*! @} */
33577 
33578 /*! @name HFP - HFP */
33579 /*! @{ */
33580 
33581 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
33582 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U)
33583 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
33584  */
33585 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
33586 /*! @} */
33587 
33588 /*! @name HBP - HBP */
33589 /*! @{ */
33590 
33591 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
33592 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U)
33593 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
33594  */
33595 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
33596 /*! @} */
33597 
33598 /*! @name HSA - HSA */
33599 /*! @{ */
33600 
33601 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
33602 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U)
33603 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
33604  */
33605 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
33606 /*! @} */
33607 
33608 /*! @name ENABLE_MULT_PKTS - ENABLE_MULT_PKTS */
33609 /*! @{ */
33610 
33611 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
33612 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
33613 /*! ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled,
33614  *    PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line
33615  *  0b0..Video Line is sent in a single packet
33616  *  0b1..Video Line is sent in two packets
33617  */
33618 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
33619 /*! @} */
33620 
33621 /*! @name VBP - VBP */
33622 /*! @{ */
33623 
33624 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK    (0xFFU)
33625 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
33626 /*! NUM_LINES - Sets the number of lines in the vertical back porch.
33627  */
33628 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
33629 /*! @} */
33630 
33631 /*! @name VFP - VFP */
33632 /*! @{ */
33633 
33634 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK    (0xFFU)
33635 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
33636 /*! NUM_LINES - Sets the number of lines in the vertical front porch.
33637  */
33638 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
33639 /*! @} */
33640 
33641 /*! @name BLLP_MODE - BLLP_MODE */
33642 /*! @{ */
33643 
33644 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK     (0x1U)
33645 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT    (0U)
33646 /*! LP - Optimize bllp periods to Low Power mode when possible
33647  *  0b0..Blanking packets are sent during BLLP periods
33648  *  0b1..LP mode is used for BLLP periods
33649  */
33650 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
33651 /*! @} */
33652 
33653 /*! @name USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP */
33654 /*! @{ */
33655 
33656 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
33657 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
33658 /*! NULL - Selects type of blanking packet to be sent during bllp
33659  *  0b0..Blanking packet used in bllp region 1
33660  *  0b1..Null packet used in bllp region
33661  */
33662 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
33663 /*! @} */
33664 
33665 /*! @name VACTIVE - VACTIVE */
33666 /*! @{ */
33667 
33668 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU)
33669 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U)
33670 /*! NUM_LINES - Sets the number of lines in the vertical active aread.
33671  */
33672 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
33673 /*! @} */
33674 
33675 
33676 /*!
33677  * @}
33678  */ /* end of group DSI_HOST_DPI_INTFC_Register_Masks */
33679 
33680 
33681 /* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
33682 /** Peripheral DSI_HOST_DPI_INTFC base address */
33683 #define DSI_HOST_DPI_INTFC_BASE                  (0x4080C200u)
33684 /** Peripheral DSI_HOST_DPI_INTFC base pointer */
33685 #define DSI_HOST_DPI_INTFC                       ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
33686 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base addresses */
33687 #define DSI_HOST_DPI_INTFC_BASE_ADDRS            { DSI_HOST_DPI_INTFC_BASE }
33688 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base pointers */
33689 #define DSI_HOST_DPI_INTFC_BASE_PTRS             { DSI_HOST_DPI_INTFC }
33690 
33691 /*!
33692  * @}
33693  */ /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
33694 
33695 
33696 /* ----------------------------------------------------------------------------
33697    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
33698    ---------------------------------------------------------------------------- */
33699 
33700 /*!
33701  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
33702  * @{
33703  */
33704 
33705 /** DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Register Layout Typedef */
33706 typedef struct {
33707   __IO uint32_t PD_TX;                             /**< PD_TX, offset: 0x0 */
33708   __IO uint32_t M_PRG_HS_PREPARE;                  /**< M_PRG_HS_PREPARE, offset: 0x4 */
33709   __IO uint32_t MC_PRG_HS_PREPARE;                 /**< MC_PRG_HS_PREPARE, offset: 0x8 */
33710   __IO uint32_t M_PRG_HS_ZERO;                     /**< M_PRG_HS_ZERO, offset: 0xC */
33711   __IO uint32_t MC_PRG_HS_ZERO;                    /**< MC_PRG_HS_ZERO, offset: 0x10 */
33712   __IO uint32_t M_PRG_HS_TRAIL;                    /**< M_PRG_HS_TRAIL, offset: 0x14 */
33713   __IO uint32_t MC_PRG_HS_TRAIL;                   /**< MC_PRG_HS_TRAIL, offset: 0x18 */
33714   __IO uint32_t PD_PLL;                            /**< PD_PLL, offset: 0x1C */
33715   __IO uint32_t TST;                               /**< TST, offset: 0x20 */
33716   __IO uint32_t CN;                                /**< CN, offset: 0x24 */
33717   __IO uint32_t CM;                                /**< CM, offset: 0x28 */
33718   __IO uint32_t CO;                                /**< CO, offset: 0x2C */
33719   __I  uint32_t LOCK;                              /**< LOCK, offset: 0x30 */
33720   __IO uint32_t LOCK_BYP;                          /**< LOCK_BYP, offset: 0x34 */
33721   __IO uint32_t TX_RCAL;                           /**< TX_RCAL, offset: 0x38 */
33722   __IO uint32_t AUTO_PD_EN;                        /**< AUTO_PD_EN, offset: 0x3C */
33723   __IO uint32_t RXLPRP;                            /**< RXLPRP, offset: 0x40 */
33724   __IO uint32_t RXCDRP;                            /**< RXCDRP, offset: 0x44 */
33725 } DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type;
33726 
33727 /* ----------------------------------------------------------------------------
33728    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
33729    ---------------------------------------------------------------------------- */
33730 
33731 /*!
33732  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
33733  * @{
33734  */
33735 
33736 /*! @name PD_TX - PD_TX */
33737 /*! @{ */
33738 
33739 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U)
33740 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U)
33741 /*! PD_TX - Power Down input for D-PHY
33742  *  0b1..Power Down
33743  *  0b0..Power Up
33744  */
33745 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK)
33746 /*! @} */
33747 
33748 /*! @name M_PRG_HS_PREPARE - M_PRG_HS_PREPARE */
33749 /*! @{ */
33750 
33751 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
33752 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
33753 /*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE input
33754  */
33755 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
33756 /*! @} */
33757 
33758 /*! @name MC_PRG_HS_PREPARE - MC_PRG_HS_PREPARE */
33759 /*! @{ */
33760 
33761 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
33762 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
33763 /*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input
33764  */
33765 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
33766 /*! @} */
33767 
33768 /*! @name M_PRG_HS_ZERO - M_PRG_HS_ZERO */
33769 /*! @{ */
33770 
33771 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
33772 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
33773 /*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO input
33774  */
33775 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
33776 /*! @} */
33777 
33778 /*! @name MC_PRG_HS_ZERO - MC_PRG_HS_ZERO */
33779 /*! @{ */
33780 
33781 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
33782 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
33783 /*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO input
33784  */
33785 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
33786 /*! @} */
33787 
33788 /*! @name M_PRG_HS_TRAIL - M_PRG_HS_TRAIL */
33789 /*! @{ */
33790 
33791 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
33792 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
33793 /*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL input
33794  */
33795 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
33796 /*! @} */
33797 
33798 /*! @name MC_PRG_HS_TRAIL - MC_PRG_HS_TRAIL */
33799 /*! @{ */
33800 
33801 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
33802 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
33803 /*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input
33804  */
33805 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
33806 /*! @} */
33807 
33808 /*! @name PD_PLL - PD_PLL */
33809 /*! @{ */
33810 
33811 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U)
33812 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U)
33813 /*! PD_PLL - Power-down signal
33814  *  0b1..Power down PLL
33815  *  0b0..Power up PLL
33816  */
33817 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK)
33818 /*! @} */
33819 
33820 /*! @name TST - TST */
33821 /*! @{ */
33822 
33823 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU)
33824 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U)
33825 /*! TST - Test
33826  */
33827 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK)
33828 /*! @} */
33829 
33830 /*! @name CN - CN */
33831 /*! @{ */
33832 
33833 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU)
33834 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U)
33835 /*! CN - Control N divider
33836  */
33837 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK)
33838 /*! @} */
33839 
33840 /*! @name CM - CM */
33841 /*! @{ */
33842 
33843 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU)
33844 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U)
33845 /*! CM - Control M divider
33846  */
33847 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK)
33848 /*! @} */
33849 
33850 /*! @name CO - CO */
33851 /*! @{ */
33852 
33853 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U)
33854 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U)
33855 /*! CO - Control O divider
33856  *  0b00..Divide by 1
33857  *  0b01..Divide by 2
33858  *  0b10..Divide by 4
33859  *  0b11..Divide by 8
33860  */
33861 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK)
33862 /*! @} */
33863 
33864 /*! @name LOCK - LOCK */
33865 /*! @{ */
33866 
33867 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U)
33868 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U)
33869 /*! LOCK - Lock Detect output
33870  *  0b1..PLL has achieved frequency lock
33871  *  0b0..PLL not locked
33872  */
33873 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK)
33874 /*! @} */
33875 
33876 /*! @name LOCK_BYP - LOCK_BYP */
33877 /*! @{ */
33878 
33879 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U)
33880 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U)
33881 /*! LOCK_BYP - DPHY LOCK_BYP input
33882  *  0b0..PLL LOCK signal will gate TxByteClkHS clock
33883  *  0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS
33884  */
33885 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK)
33886 /*! @} */
33887 
33888 /*! @name TX_RCAL - TX_RCAL */
33889 /*! @{ */
33890 
33891 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U)
33892 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U)
33893 /*! TX_RCAL - On-chip termination control bits for manual calibration of HS-TX
33894  *  0b00..20% higher than mid-range. Highest impedance setting
33895  *  0b01..Mid-range impedance setting (default)
33896  *  0b10..15% lower than mid-range
33897  *  0b11..25% lower than mid-range. Lowest impedance setting
33898  */
33899 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK)
33900 /*! @} */
33901 
33902 /*! @name AUTO_PD_EN - AUTO_PD_EN */
33903 /*! @{ */
33904 
33905 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
33906 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
33907 /*! AUTO_PD_EN - DPHY AUTO_PD_EN input
33908  *  0b0..Inactive lanes are powered up and driving LP11
33909  *  0b1..inactive lanes are powered down
33910  */
33911 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK)
33912 /*! @} */
33913 
33914 /*! @name RXLPRP - RXLPRP */
33915 /*! @{ */
33916 
33917 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U)
33918 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U)
33919 /*! RXLPRP - DPHY RXLPRP input
33920  */
33921 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK)
33922 /*! @} */
33923 
33924 /*! @name RXCDRP - RXCDRP */
33925 /*! @{ */
33926 
33927 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U)
33928 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U)
33929 /*! RXCDRP - DPHY RXCDRP input
33930  *  0b00..344mV
33931  *  0b01..325mV (Default)
33932  *  0b10..307mV
33933  *  0b11..Invalid
33934  */
33935 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK)
33936 /*! @} */
33937 
33938 
33939 /*!
33940  * @}
33941  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */
33942 
33943 
33944 /* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */
33945 /** Peripheral DSI_HOST_DPHY_INTFC base address */
33946 #define DSI_HOST_DPHY_INTFC_BASE                 (0x4080C300u)
33947 /** Peripheral DSI_HOST_DPHY_INTFC base pointer */
33948 #define DSI_HOST_DPHY_INTFC                      ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
33949 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
33950  * addresses */
33951 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE }
33952 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
33953  * pointers */
33954 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC }
33955 
33956 /*!
33957  * @}
33958  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */
33959 
33960 
33961 /* ----------------------------------------------------------------------------
33962    -- EMVSIM Peripheral Access Layer
33963    ---------------------------------------------------------------------------- */
33964 
33965 /*!
33966  * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
33967  * @{
33968  */
33969 
33970 /** EMVSIM - Register Layout Typedef */
33971 typedef struct {
33972   __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
33973   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
33974   __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
33975   __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
33976   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
33977   __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
33978   __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
33979   __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
33980   __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
33981   __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
33982   __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
33983   __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
33984   __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
33985   __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
33986   __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
33987   __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
33988   __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
33989   __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
33990   __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
33991 } EMVSIM_Type;
33992 
33993 /* ----------------------------------------------------------------------------
33994    -- EMVSIM Register Masks
33995    ---------------------------------------------------------------------------- */
33996 
33997 /*!
33998  * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
33999  * @{
34000  */
34001 
34002 /*! @name VER_ID - Version ID Register */
34003 /*! @{ */
34004 
34005 #define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
34006 #define EMVSIM_VER_ID_VER_SHIFT                  (0U)
34007 /*! VER - Version ID of the module
34008  */
34009 #define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
34010 /*! @} */
34011 
34012 /*! @name PARAM - Parameter Register */
34013 /*! @{ */
34014 
34015 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
34016 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
34017 /*! RX_FIFO_DEPTH - Receive FIFO Depth
34018  */
34019 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
34020 
34021 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
34022 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
34023 /*! TX_FIFO_DEPTH - Transmit FIFO Depth
34024  */
34025 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
34026 /*! @} */
34027 
34028 /*! @name CLKCFG - Clock Configuration Register */
34029 /*! @{ */
34030 
34031 #define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
34032 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
34033 /*! CLK_PRSC - Clock Prescaler Value
34034  */
34035 #define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
34036 
34037 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
34038 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
34039 /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
34040  *  0b00..Disabled / Reset
34041  *  0b01..Card Clock
34042  *  0b10..Receive Clock
34043  *  0b11..ETU Clock (transmit clock)
34044  */
34045 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
34046 
34047 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
34048 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
34049 /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
34050  *  0b00..Disabled / Reset
34051  *  0b01..Card Clock
34052  *  0b10..Receive Clock
34053  *  0b11..ETU Clock (transmit clock)
34054  */
34055 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
34056 /*! @} */
34057 
34058 /*! @name DIVISOR - Baud Rate Divisor Register */
34059 /*! @{ */
34060 
34061 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
34062 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
34063 /*! DIVISOR_VALUE - Divisor (F/D) Value
34064  *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
34065  *  0b000000101-0b011111111..Divisor value F/D
34066  */
34067 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
34068 /*! @} */
34069 
34070 /*! @name CTRL - Control Register */
34071 /*! @{ */
34072 
34073 #define EMVSIM_CTRL_IC_MASK                      (0x1U)
34074 #define EMVSIM_CTRL_IC_SHIFT                     (0U)
34075 /*! IC - Inverse Convention
34076  *  0b0..Direction convention transfers enabled
34077  *  0b1..Inverse convention transfers enabled
34078  */
34079 #define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
34080 
34081 #define EMVSIM_CTRL_ICM_MASK                     (0x2U)
34082 #define EMVSIM_CTRL_ICM_SHIFT                    (1U)
34083 /*! ICM - Initial Character Mode
34084  *  0b0..Initial Character Mode disabled
34085  *  0b1..Initial Character Mode enabled
34086  */
34087 #define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
34088 
34089 #define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
34090 #define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
34091 /*! ANACK - Auto NACK Enable
34092  *  0b0..NACK generation on errors disabled
34093  *  0b1..NACK generation on errors enabled
34094  */
34095 #define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
34096 
34097 #define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
34098 #define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
34099 /*! ONACK - Overrun NACK Enable
34100  *  0b0..NACK generation on overrun is disabled
34101  *  0b1..NACK generation on overrun is enabled
34102  */
34103 #define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
34104 
34105 #define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
34106 #define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
34107 /*! FLSH_RX - Flush Receiver Bit
34108  *  0b0..EMVSIM Receiver normal operation
34109  *  0b1..EMVSIM Receiver held in Reset
34110  */
34111 #define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
34112 
34113 #define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
34114 #define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
34115 /*! FLSH_TX - Flush Transmitter Bit
34116  *  0b0..EMVSIM Transmitter normal operation
34117  *  0b1..EMVSIM Transmitter held in Reset
34118  */
34119 #define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
34120 
34121 #define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
34122 #define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
34123 /*! SW_RST - Software Reset Bit
34124  *  0b0..EMVSIM Normal operation
34125  *  0b1..EMVSIM held in Reset
34126  */
34127 #define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
34128 
34129 #define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
34130 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
34131 /*! KILL_CLOCKS - Kill all internal clocks
34132  *  0b0..EMVSIM input clock enabled
34133  *  0b1..EMVSIM input clock is disabled
34134  */
34135 #define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
34136 
34137 #define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
34138 #define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
34139 /*! DOZE_EN - Doze Enable
34140  *  0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty
34141  *  0b1..DOZE instruction has no effect on EMVSIM module
34142  */
34143 #define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
34144 
34145 #define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
34146 #define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
34147 /*! STOP_EN - STOP Enable
34148  *  0b0..STOP instruction shuts down all EMVSIM clocks
34149  *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
34150  */
34151 #define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
34152 
34153 #define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
34154 #define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
34155 /*! RCV_EN - Receiver Enable
34156  *  0b0..EMVSIM Receiver disabled
34157  *  0b1..EMVSIM Receiver enabled
34158  */
34159 #define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
34160 
34161 #define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
34162 #define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
34163 /*! XMT_EN - Transmitter Enable
34164  *  0b0..EMVSIM Transmitter disabled
34165  *  0b1..EMVSIM Transmitter enabled
34166  */
34167 #define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
34168 
34169 #define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
34170 #define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
34171 /*! RCVR_11 - Receiver 11 ETU Mode Enable
34172  *  0b0..Receiver configured for 12 ETU operation mode
34173  *  0b1..Receiver configured for 11 ETU operation mode
34174  */
34175 #define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
34176 
34177 #define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
34178 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
34179 /*! RX_DMA_EN - Receive DMA Enable
34180  *  0b0..No DMA Read Request asserted for Receiver
34181  *  0b1..DMA Read Request asserted for Receiver
34182  */
34183 #define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
34184 
34185 #define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
34186 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
34187 /*! TX_DMA_EN - Transmit DMA Enable
34188  *  0b0..No DMA Write Request asserted for Transmitter
34189  *  0b1..DMA Write Request asserted for Transmitter
34190  */
34191 #define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
34192 
34193 #define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
34194 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
34195 /*! INV_CRC_VAL - Invert bits in the CRC Output Value
34196  *  0b0..Bits in CRC Output value are not inverted.
34197  *  0b1..Bits in CRC Output value are inverted.
34198  */
34199 #define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
34200 
34201 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
34202 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
34203 /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
34204  *  0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0
34205  *  0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}
34206  */
34207 #define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
34208 
34209 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
34210 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
34211 /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
34212  *  0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation
34213  *  0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation
34214  */
34215 #define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
34216 
34217 #define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
34218 #define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
34219 /*! CWT_EN - Character Wait Time Counter Enable
34220  *  0b0..Character Wait time Counter is disabled
34221  *  0b1..Character Wait time counter is enabled
34222  */
34223 #define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
34224 
34225 #define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
34226 #define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
34227 /*! LRC_EN - LRC Enable
34228  *  0b0..8-bit Linear Redundancy Checking disabled
34229  *  0b1..8-bit Linear Redundancy Checking enabled
34230  */
34231 #define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
34232 
34233 #define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
34234 #define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
34235 /*! CRC_EN - CRC Enable
34236  *  0b0..16-bit Cyclic Redundancy Checking disabled
34237  *  0b1..16-bit Cyclic Redundancy Checking enabled
34238  */
34239 #define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
34240 
34241 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
34242 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
34243 /*! XMT_CRC_LRC - Transmit CRC or LRC Enable
34244  *  0b0..No CRC or LRC value is transmitted
34245  *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
34246  */
34247 #define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
34248 
34249 #define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
34250 #define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
34251 /*! BWT_EN - Block Wait Time Counter Enable
34252  *  0b0..Disable BWT, BGT Counters
34253  *  0b1..Enable BWT, BGT Counters
34254  */
34255 #define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
34256 /*! @} */
34257 
34258 /*! @name INT_MASK - Interrupt Mask Register */
34259 /*! @{ */
34260 
34261 #define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
34262 #define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
34263 /*! RDT_IM - Receive Data Threshold Interrupt Mask
34264  *  0b0..RDTF interrupt enabled
34265  *  0b1..RDTF interrupt masked
34266  */
34267 #define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
34268 
34269 #define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
34270 #define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
34271 /*! TC_IM - Transmit Complete Interrupt Mask
34272  *  0b0..TCF interrupt enabled
34273  *  0b1..TCF interrupt masked
34274  */
34275 #define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
34276 
34277 #define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
34278 #define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
34279 /*! RFO_IM - Receive FIFO Overflow Interrupt Mask
34280  *  0b0..RFO interrupt enabled
34281  *  0b1..RFO interrupt masked
34282  */
34283 #define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
34284 
34285 #define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
34286 #define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
34287 /*! ETC_IM - Early Transmit Complete Interrupt Mask
34288  *  0b0..ETC interrupt enabled
34289  *  0b1..ETC interrupt masked
34290  */
34291 #define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
34292 
34293 #define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
34294 #define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
34295 /*! TFE_IM - Transmit FIFO Empty Interrupt Mask
34296  *  0b0..TFE interrupt enabled
34297  *  0b1..TFE interrupt masked
34298  */
34299 #define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
34300 
34301 #define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
34302 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
34303 /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
34304  *  0b0..TNTE interrupt enabled
34305  *  0b1..TNTE interrupt masked
34306  */
34307 #define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
34308 
34309 #define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
34310 #define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
34311 /*! TFF_IM - Transmit FIFO Full Interrupt Mask
34312  *  0b0..TFF interrupt enabled
34313  *  0b1..TFF interrupt masked
34314  */
34315 #define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
34316 
34317 #define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
34318 #define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
34319 /*! TDT_IM - Transmit Data Threshold Interrupt Mask
34320  *  0b0..TDTF interrupt enabled
34321  *  0b1..TDTF interrupt masked
34322  */
34323 #define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
34324 
34325 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
34326 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
34327 /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
34328  *  0b0..GPCNT0_TO interrupt enabled
34329  *  0b1..GPCNT0_TO interrupt masked
34330  */
34331 #define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
34332 
34333 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
34334 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
34335 /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
34336  *  0b0..CWT_ERR interrupt enabled
34337  *  0b1..CWT_ERR interrupt masked
34338  */
34339 #define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
34340 
34341 #define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
34342 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
34343 /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
34344  *  0b0..RTE interrupt enabled
34345  *  0b1..RTE interrupt masked
34346  */
34347 #define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
34348 
34349 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
34350 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
34351 /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
34352  *  0b0..BWT_ERR interrupt enabled
34353  *  0b1..BWT_ERR interrupt masked
34354  */
34355 #define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
34356 
34357 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
34358 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
34359 /*! BGT_ERR_IM - Block Guard Time Error Interrupt
34360  *  0b0..BGT_ERR interrupt enabled
34361  *  0b1..BGT_ERR interrupt masked
34362  */
34363 #define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
34364 
34365 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
34366 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
34367 /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
34368  *  0b0..GPCNT1_TO interrupt enabled
34369  *  0b1..GPCNT1_TO interrupt masked
34370  */
34371 #define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
34372 
34373 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
34374 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
34375 /*! RX_DATA_IM - Receive Data Interrupt Mask
34376  *  0b0..RX_DATA interrupt enabled
34377  *  0b1..RX_DATA interrupt masked
34378  */
34379 #define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
34380 
34381 #define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
34382 #define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
34383 /*! PEF_IM - Parity Error Interrupt Mask
34384  *  0b0..PEF interrupt enabled
34385  *  0b1..PEF interrupt masked
34386  */
34387 #define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
34388 /*! @} */
34389 
34390 /*! @name RX_THD - Receiver Threshold Register */
34391 /*! @{ */
34392 
34393 #define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
34394 #define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
34395 /*! RDT - Receiver Data Threshold Value
34396  */
34397 #define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
34398 
34399 #define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
34400 #define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
34401 /*! RNCK_THD - Receiver NACK Threshold Value
34402  */
34403 #define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
34404 /*! @} */
34405 
34406 /*! @name TX_THD - Transmitter Threshold Register */
34407 /*! @{ */
34408 
34409 #define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
34410 #define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
34411 /*! TDT - Transmitter Data Threshold Value
34412  */
34413 #define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
34414 
34415 #define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
34416 #define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
34417 /*! TNCK_THD - Transmitter NACK Threshold Value
34418  */
34419 #define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
34420 /*! @} */
34421 
34422 /*! @name RX_STATUS - Receive Status Register */
34423 /*! @{ */
34424 
34425 #define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
34426 #define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
34427 /*! RFO - Receive FIFO Overflow Flag
34428  *  0b0..No overrun error has occurred
34429  *  0b1..A byte was received when the received FIFO was already full
34430  */
34431 #define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
34432 
34433 #define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
34434 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
34435 /*! RX_DATA - Receive Data Interrupt Flag
34436  *  0b0..No new byte is received
34437  *  0b1..New byte is received ans stored in Receive FIFO
34438  */
34439 #define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
34440 
34441 #define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
34442 #define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
34443 /*! RDTF - Receive Data Threshold Interrupt Flag
34444  *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT
34445  *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.
34446  */
34447 #define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
34448 
34449 #define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
34450 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
34451 /*! LRC_OK - LRC Check OK Flag
34452  *  0b0..Current LRC value does not match remainder.
34453  *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
34454  */
34455 #define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
34456 
34457 #define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
34458 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
34459 /*! CRC_OK - CRC Check OK Flag
34460  *  0b0..Current CRC value does not match remainder.
34461  *  0b1..Current calculated CRC value matches the expected result.
34462  */
34463 #define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
34464 
34465 #define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
34466 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
34467 /*! CWT_ERR - Character Wait Time Error Flag
34468  *  0b0..No CWT violation has occurred
34469  *  0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.
34470  */
34471 #define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
34472 
34473 #define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
34474 #define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
34475 /*! RTE - Received NACK Threshold Error Flag
34476  *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD
34477  *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD
34478  */
34479 #define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
34480 
34481 #define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
34482 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
34483 /*! BWT_ERR - Block Wait Time Error Flag
34484  *  0b0..Block wait time not exceeded
34485  *  0b1..Block wait time was exceeded
34486  */
34487 #define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
34488 
34489 #define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
34490 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
34491 /*! BGT_ERR - Block Guard Time Error Flag
34492  *  0b0..Block guard time was sufficient
34493  *  0b1..Block guard time was too small
34494  */
34495 #define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
34496 
34497 #define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
34498 #define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
34499 /*! PEF - Parity Error Flag
34500  *  0b0..No parity error detected
34501  *  0b1..Parity error detected
34502  */
34503 #define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
34504 
34505 #define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
34506 #define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
34507 /*! FEF - Frame Error Flag
34508  *  0b0..No frame error detected
34509  *  0b1..Frame error detected
34510  */
34511 #define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
34512 
34513 #define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
34514 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
34515 /*! RX_WPTR - Receive FIFO Write Pointer Value
34516  */
34517 #define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
34518 
34519 #define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
34520 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
34521 /*! RX_CNT - Receive FIFO Byte Count
34522  *  0b0000..FIFO is emtpy
34523  */
34524 #define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
34525 /*! @} */
34526 
34527 /*! @name TX_STATUS - Transmitter Status Register */
34528 /*! @{ */
34529 
34530 #define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
34531 #define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
34532 /*! TNTE - Transmit NACK Threshold Error Flag
34533  *  0b0..Transmit NACK threshold has not been reached
34534  *  0b1..Transmit NACK threshold reached; transmitter frozen
34535  */
34536 #define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
34537 
34538 #define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
34539 #define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
34540 /*! TFE - Transmit FIFO Empty Flag
34541  *  0b0..Transmit FIFO is not empty
34542  *  0b1..Transmit FIFO is empty
34543  */
34544 #define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
34545 
34546 #define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
34547 #define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
34548 /*! ETCF - Early Transmit Complete Flag
34549  *  0b0..Transmit pending or in progress
34550  *  0b1..Transmit complete
34551  */
34552 #define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
34553 
34554 #define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
34555 #define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
34556 /*! TCF - Transmit Complete Flag
34557  *  0b0..Transmit pending or in progress
34558  *  0b1..Transmit complete
34559  */
34560 #define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
34561 
34562 #define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
34563 #define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
34564 /*! TFF - Transmit FIFO Full Flag
34565  *  0b0..Transmit FIFO Full condition has not occurred
34566  *  0b1..A Transmit FIFO Full condition has occurred
34567  */
34568 #define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
34569 
34570 #define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
34571 #define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
34572 /*! TDTF - Transmit Data Threshold Flag
34573  *  0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared
34574  *  0b1..Number of bytes in FIFO is less than or equal to TDT
34575  */
34576 #define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
34577 
34578 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
34579 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
34580 /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
34581  *  0b0..GPCNT0 time not reached, or bit has been cleared.
34582  *  0b1..General Purpose counter has reached the GPCNT0 value
34583  */
34584 #define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
34585 
34586 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
34587 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
34588 /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
34589  *  0b0..GPCNT1 time not reached, or bit has been cleared.
34590  *  0b1..General Purpose counter has reached the GPCNT1 value
34591  */
34592 #define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
34593 
34594 #define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
34595 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
34596 /*! TX_RPTR - Transmit FIFO Read Pointer
34597  */
34598 #define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
34599 
34600 #define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
34601 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
34602 /*! TX_CNT - Transmit FIFO Byte Count
34603  *  0b0000..FIFO is emtpy
34604  */
34605 #define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
34606 /*! @} */
34607 
34608 /*! @name PCSR - Port Control and Status Register */
34609 /*! @{ */
34610 
34611 #define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
34612 #define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
34613 /*! SAPD - Auto Power Down Enable
34614  *  0b0..Auto power down disabled
34615  *  0b1..Auto power down enabled
34616  */
34617 #define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
34618 
34619 #define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
34620 #define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
34621 /*! SVCC_EN - Vcc Enable for Smart Card
34622  *  0b0..Smart Card Voltage disabled
34623  *  0b1..Smart Card Voltage enabled
34624  */
34625 #define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
34626 
34627 #define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
34628 #define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
34629 /*! VCCENP - VCC Enable Polarity Control
34630  *  0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged.
34631  *  0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.
34632  */
34633 #define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
34634 
34635 #define EMVSIM_PCSR_SRST_MASK                    (0x8U)
34636 #define EMVSIM_PCSR_SRST_SHIFT                   (3U)
34637 /*! SRST - Reset to Smart Card
34638  *  0b0..Smart Card Reset is asserted
34639  *  0b1..Smart Card Reset is de-asserted
34640  */
34641 #define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
34642 
34643 #define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
34644 #define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
34645 /*! SCEN - Clock Enable for Smart Card
34646  *  0b0..Smart Card Clock Disabled
34647  *  0b1..Smart Card Clock Enabled
34648  */
34649 #define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
34650 
34651 #define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
34652 #define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
34653 /*! SCSP - Smart Card Clock Stop Polarity
34654  *  0b0..Clock is logic 0 when stopped by SCEN
34655  *  0b1..Clock is logic 1 when stopped by SCEN
34656  */
34657 #define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
34658 
34659 #define EMVSIM_PCSR_SPD_MASK                     (0x80U)
34660 #define EMVSIM_PCSR_SPD_SHIFT                    (7U)
34661 /*! SPD - Auto Power Down Control
34662  *  0b0..No effect
34663  *  0b1..Start Auto Powerdown or Power Down is in progress
34664  */
34665 #define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
34666 
34667 #define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
34668 #define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
34669 /*! SPDIM - Smart Card Presence Detect Interrupt Mask
34670  *  0b0..SIM presence detect interrupt is enabled
34671  *  0b1..SIM presence detect interrupt is masked
34672  */
34673 #define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
34674 
34675 #define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
34676 #define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
34677 /*! SPDIF - Smart Card Presence Detect Interrupt Flag
34678  *  0b0..No insertion or removal of Smart Card detected on Port
34679  *  0b1..Insertion or removal of Smart Card detected on Port
34680  */
34681 #define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
34682 
34683 #define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
34684 #define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
34685 /*! SPDP - Smart Card Presence Detect Pin Status
34686  *  0b0..SIM Presence Detect pin is logic low
34687  *  0b1..SIM Presence Detectpin is logic high
34688  */
34689 #define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
34690 
34691 #define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
34692 #define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
34693 /*! SPDES - SIM Presence Detect Edge Select
34694  *  0b0..Falling edge on the pin
34695  *  0b1..Rising edge on the pin
34696  */
34697 #define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
34698 /*! @} */
34699 
34700 /*! @name RX_BUF - Receive Data Read Buffer */
34701 /*! @{ */
34702 
34703 #define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
34704 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
34705 /*! RX_BYTE - Receive Data Byte Read
34706  */
34707 #define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
34708 /*! @} */
34709 
34710 /*! @name TX_BUF - Transmit Data Buffer */
34711 /*! @{ */
34712 
34713 #define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
34714 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
34715 /*! TX_BYTE - Transmit Data Byte
34716  */
34717 #define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
34718 /*! @} */
34719 
34720 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
34721 /*! @{ */
34722 
34723 #define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
34724 #define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
34725 /*! GETU - Transmitter Guard Time Value in ETU
34726  */
34727 #define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
34728 /*! @} */
34729 
34730 /*! @name CWT_VAL - Character Wait Time Value Register */
34731 /*! @{ */
34732 
34733 #define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
34734 #define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
34735 /*! CWT - Character Wait Time Value
34736  */
34737 #define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
34738 /*! @} */
34739 
34740 /*! @name BWT_VAL - Block Wait Time Value Register */
34741 /*! @{ */
34742 
34743 #define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
34744 #define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
34745 /*! BWT - Block Wait Time Value
34746  */
34747 #define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
34748 /*! @} */
34749 
34750 /*! @name BGT_VAL - Block Guard Time Value Register */
34751 /*! @{ */
34752 
34753 #define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
34754 #define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
34755 /*! BGT - Block Guard Time Value
34756  */
34757 #define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
34758 /*! @} */
34759 
34760 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
34761 /*! @{ */
34762 
34763 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
34764 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
34765 /*! GPCNT0 - General Purpose Counter 0 Timeout Value
34766  */
34767 #define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
34768 /*! @} */
34769 
34770 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
34771 /*! @{ */
34772 
34773 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
34774 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
34775 /*! GPCNT1 - General Purpose Counter 1 Timeout Value
34776  */
34777 #define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
34778 /*! @} */
34779 
34780 
34781 /*!
34782  * @}
34783  */ /* end of group EMVSIM_Register_Masks */
34784 
34785 
34786 /* EMVSIM - Peripheral instance base addresses */
34787 /** Peripheral EMVSIM1 base address */
34788 #define EMVSIM1_BASE                             (0x40154000u)
34789 /** Peripheral EMVSIM1 base pointer */
34790 #define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
34791 /** Peripheral EMVSIM2 base address */
34792 #define EMVSIM2_BASE                             (0x40158000u)
34793 /** Peripheral EMVSIM2 base pointer */
34794 #define EMVSIM2                                  ((EMVSIM_Type *)EMVSIM2_BASE)
34795 /** Array initializer of EMVSIM peripheral base addresses */
34796 #define EMVSIM_BASE_ADDRS                        { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
34797 /** Array initializer of EMVSIM peripheral base pointers */
34798 #define EMVSIM_BASE_PTRS                         { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
34799 /** Interrupt vectors for the EMVSIM peripheral type */
34800 #define EMVSIM_IRQS                              { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
34801 
34802 /*!
34803  * @}
34804  */ /* end of group EMVSIM_Peripheral_Access_Layer */
34805 
34806 
34807 /* ----------------------------------------------------------------------------
34808    -- ENC Peripheral Access Layer
34809    ---------------------------------------------------------------------------- */
34810 
34811 /*!
34812  * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
34813  * @{
34814  */
34815 
34816 /** ENC - Register Layout Typedef */
34817 typedef struct {
34818   __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
34819   __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x2 */
34820   __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x4 */
34821   __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x6 */
34822   __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x8 */
34823   __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0xA */
34824   __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0xC */
34825   __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xE */
34826   __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0x10 */
34827   __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x12 */
34828   __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x14 */
34829   __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x16 */
34830   __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x18 */
34831   __I  uint16_t IMR;                               /**< Input Monitor Register, offset: 0x1A */
34832   __IO uint16_t TST;                               /**< Test Register, offset: 0x1C */
34833   __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x1E */
34834   __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x20 */
34835   __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x22 */
34836   __IO uint16_t UCOMP;                             /**< Upper Position Compare Register, offset: 0x24 */
34837   __IO uint16_t LCOMP;                             /**< Lower Position Compare Register, offset: 0x26 */
34838   __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x28 */
34839   __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x2A */
34840   __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x2C */
34841   __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0x2E */
34842   __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x30 */
34843   __IO uint16_t CTRL3;                             /**< Control 3 Register, offset: 0x32 */
34844 } ENC_Type;
34845 
34846 /* ----------------------------------------------------------------------------
34847    -- ENC Register Masks
34848    ---------------------------------------------------------------------------- */
34849 
34850 /*!
34851  * @addtogroup ENC_Register_Masks ENC Register Masks
34852  * @{
34853  */
34854 
34855 /*! @name CTRL - Control Register */
34856 /*! @{ */
34857 
34858 #define ENC_CTRL_CMPIE_MASK                      (0x1U)
34859 #define ENC_CTRL_CMPIE_SHIFT                     (0U)
34860 /*! CMPIE - Compare Interrupt Enable
34861  *  0b0..Disabled
34862  *  0b1..Enabled
34863  */
34864 #define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
34865 
34866 #define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
34867 #define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
34868 /*! CMPIRQ - Compare Interrupt Request
34869  *  0b0..No match has occurred (the counter does not match the COMP value)
34870  *  0b1..COMP match has occurred (the counter matches the COMP value)
34871  */
34872 #define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
34873 
34874 #define ENC_CTRL_WDE_MASK                        (0x4U)
34875 #define ENC_CTRL_WDE_SHIFT                       (2U)
34876 /*! WDE - Watchdog Enable
34877  *  0b0..Disabled
34878  *  0b1..Enabled
34879  */
34880 #define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
34881 
34882 #define ENC_CTRL_DIE_MASK                        (0x8U)
34883 #define ENC_CTRL_DIE_SHIFT                       (3U)
34884 /*! DIE - Watchdog Timeout Interrupt Enable
34885  *  0b0..Disabled
34886  *  0b1..Enabled
34887  */
34888 #define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
34889 
34890 #define ENC_CTRL_DIRQ_MASK                       (0x10U)
34891 #define ENC_CTRL_DIRQ_SHIFT                      (4U)
34892 /*! DIRQ - Watchdog Timeout Interrupt Request
34893  *  0b0..No Watchdog timeout interrupt has occurred
34894  *  0b1..Watchdog timeout interrupt has occurred
34895  */
34896 #define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
34897 
34898 #define ENC_CTRL_XNE_MASK                        (0x20U)
34899 #define ENC_CTRL_XNE_SHIFT                       (5U)
34900 /*! XNE - Use Negative Edge of INDEX Pulse
34901  *  0b0..Use positive edge of INDEX pulse
34902  *  0b1..Use negative edge of INDEX pulse
34903  */
34904 #define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
34905 
34906 #define ENC_CTRL_XIP_MASK                        (0x40U)
34907 #define ENC_CTRL_XIP_SHIFT                       (6U)
34908 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
34909  *  0b0..INDEX pulse does not initialize the position counter
34910  *  0b1..INDEX pulse initializes the position counter
34911  */
34912 #define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
34913 
34914 #define ENC_CTRL_XIE_MASK                        (0x80U)
34915 #define ENC_CTRL_XIE_SHIFT                       (7U)
34916 /*! XIE - INDEX Pulse Interrupt Enable
34917  *  0b0..Disabled
34918  *  0b1..Enabled
34919  */
34920 #define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
34921 
34922 #define ENC_CTRL_XIRQ_MASK                       (0x100U)
34923 #define ENC_CTRL_XIRQ_SHIFT                      (8U)
34924 /*! XIRQ - INDEX Pulse Interrupt Request
34925  *  0b0..INDEX pulse has not occurred
34926  *  0b1..INDEX pulse has occurred
34927  */
34928 #define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
34929 
34930 #define ENC_CTRL_PH1_MASK                        (0x200U)
34931 #define ENC_CTRL_PH1_SHIFT                       (9U)
34932 /*! PH1 - Enable Signal Phase Count Mode
34933  *  0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
34934  *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
34935  *       PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
34936  *       CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
34937  *       PHASEB = 0, then count down
34938  */
34939 #define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
34940 
34941 #define ENC_CTRL_REV_MASK                        (0x400U)
34942 #define ENC_CTRL_REV_SHIFT                       (10U)
34943 /*! REV - Enable Reverse Direction Counting
34944  *  0b0..Count normally
34945  *  0b1..Count in the reverse direction
34946  */
34947 #define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
34948 
34949 #define ENC_CTRL_SWIP_MASK                       (0x800U)
34950 #define ENC_CTRL_SWIP_SHIFT                      (11U)
34951 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
34952  *  0b0..No action
34953  *  0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
34954  */
34955 #define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
34956 
34957 #define ENC_CTRL_HNE_MASK                        (0x1000U)
34958 #define ENC_CTRL_HNE_SHIFT                       (12U)
34959 /*! HNE - Use Negative Edge of HOME Input
34960  *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
34961  *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
34962  */
34963 #define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
34964 
34965 #define ENC_CTRL_HIP_MASK                        (0x2000U)
34966 #define ENC_CTRL_HIP_SHIFT                       (13U)
34967 /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
34968  *  0b0..No action
34969  *  0b1..HOME signal initializes the position counter
34970  */
34971 #define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
34972 
34973 #define ENC_CTRL_HIE_MASK                        (0x4000U)
34974 #define ENC_CTRL_HIE_SHIFT                       (14U)
34975 /*! HIE - HOME Interrupt Enable
34976  *  0b0..Disabled
34977  *  0b1..Enabled
34978  */
34979 #define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
34980 
34981 #define ENC_CTRL_HIRQ_MASK                       (0x8000U)
34982 #define ENC_CTRL_HIRQ_SHIFT                      (15U)
34983 /*! HIRQ - HOME Signal Transition Interrupt Request
34984  *  0b0..No transition on the HOME signal has occurred
34985  *  0b1..A transition on the HOME signal has occurred
34986  */
34987 #define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
34988 /*! @} */
34989 
34990 /*! @name FILT - Input Filter Register */
34991 /*! @{ */
34992 
34993 #define ENC_FILT_FILT_PER_MASK                   (0xFFU)
34994 #define ENC_FILT_FILT_PER_SHIFT                  (0U)
34995 /*! FILT_PER - Input Filter Sample Period
34996  */
34997 #define ENC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
34998 
34999 #define ENC_FILT_FILT_CNT_MASK                   (0x700U)
35000 #define ENC_FILT_FILT_CNT_SHIFT                  (8U)
35001 /*! FILT_CNT - Input Filter Sample Count
35002  */
35003 #define ENC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
35004 
35005 #define ENC_FILT_FILT_PRSC_MASK                  (0xE000U)
35006 #define ENC_FILT_FILT_PRSC_SHIFT                 (13U)
35007 /*! FILT_PRSC - prescaler divide IPbus clock to FILT clk
35008  */
35009 #define ENC_FILT_FILT_PRSC(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)
35010 /*! @} */
35011 
35012 /*! @name WTR - Watchdog Timeout Register */
35013 /*! @{ */
35014 
35015 #define ENC_WTR_WDOG_MASK                        (0xFFFFU)
35016 #define ENC_WTR_WDOG_SHIFT                       (0U)
35017 /*! WDOG - WDOG
35018  */
35019 #define ENC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
35020 /*! @} */
35021 
35022 /*! @name POSD - Position Difference Counter Register */
35023 /*! @{ */
35024 
35025 #define ENC_POSD_POSD_MASK                       (0xFFFFU)
35026 #define ENC_POSD_POSD_SHIFT                      (0U)
35027 /*! POSD - POSD
35028  */
35029 #define ENC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
35030 /*! @} */
35031 
35032 /*! @name POSDH - Position Difference Hold Register */
35033 /*! @{ */
35034 
35035 #define ENC_POSDH_POSDH_MASK                     (0xFFFFU)
35036 #define ENC_POSDH_POSDH_SHIFT                    (0U)
35037 /*! POSDH - POSDH
35038  */
35039 #define ENC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
35040 /*! @} */
35041 
35042 /*! @name REV - Revolution Counter Register */
35043 /*! @{ */
35044 
35045 #define ENC_REV_REV_MASK                         (0xFFFFU)
35046 #define ENC_REV_REV_SHIFT                        (0U)
35047 /*! REV - REV
35048  */
35049 #define ENC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
35050 /*! @} */
35051 
35052 /*! @name REVH - Revolution Hold Register */
35053 /*! @{ */
35054 
35055 #define ENC_REVH_REVH_MASK                       (0xFFFFU)
35056 #define ENC_REVH_REVH_SHIFT                      (0U)
35057 /*! REVH - REVH
35058  */
35059 #define ENC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
35060 /*! @} */
35061 
35062 /*! @name UPOS - Upper Position Counter Register */
35063 /*! @{ */
35064 
35065 #define ENC_UPOS_POS_MASK                        (0xFFFFU)
35066 #define ENC_UPOS_POS_SHIFT                       (0U)
35067 /*! POS - POS
35068  */
35069 #define ENC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
35070 /*! @} */
35071 
35072 /*! @name LPOS - Lower Position Counter Register */
35073 /*! @{ */
35074 
35075 #define ENC_LPOS_POS_MASK                        (0xFFFFU)
35076 #define ENC_LPOS_POS_SHIFT                       (0U)
35077 /*! POS - POS
35078  */
35079 #define ENC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
35080 /*! @} */
35081 
35082 /*! @name UPOSH - Upper Position Hold Register */
35083 /*! @{ */
35084 
35085 #define ENC_UPOSH_POSH_MASK                      (0xFFFFU)
35086 #define ENC_UPOSH_POSH_SHIFT                     (0U)
35087 /*! POSH - POSH
35088  */
35089 #define ENC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
35090 /*! @} */
35091 
35092 /*! @name LPOSH - Lower Position Hold Register */
35093 /*! @{ */
35094 
35095 #define ENC_LPOSH_POSH_MASK                      (0xFFFFU)
35096 #define ENC_LPOSH_POSH_SHIFT                     (0U)
35097 /*! POSH - POSH
35098  */
35099 #define ENC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
35100 /*! @} */
35101 
35102 /*! @name UINIT - Upper Initialization Register */
35103 /*! @{ */
35104 
35105 #define ENC_UINIT_INIT_MASK                      (0xFFFFU)
35106 #define ENC_UINIT_INIT_SHIFT                     (0U)
35107 /*! INIT - INIT
35108  */
35109 #define ENC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
35110 /*! @} */
35111 
35112 /*! @name LINIT - Lower Initialization Register */
35113 /*! @{ */
35114 
35115 #define ENC_LINIT_INIT_MASK                      (0xFFFFU)
35116 #define ENC_LINIT_INIT_SHIFT                     (0U)
35117 /*! INIT - INIT
35118  */
35119 #define ENC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
35120 /*! @} */
35121 
35122 /*! @name IMR - Input Monitor Register */
35123 /*! @{ */
35124 
35125 #define ENC_IMR_HOME_MASK                        (0x1U)
35126 #define ENC_IMR_HOME_SHIFT                       (0U)
35127 /*! HOME - HOME
35128  */
35129 #define ENC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
35130 
35131 #define ENC_IMR_INDEX_MASK                       (0x2U)
35132 #define ENC_IMR_INDEX_SHIFT                      (1U)
35133 /*! INDEX - INDEX
35134  */
35135 #define ENC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
35136 
35137 #define ENC_IMR_PHB_MASK                         (0x4U)
35138 #define ENC_IMR_PHB_SHIFT                        (2U)
35139 /*! PHB - PHB
35140  */
35141 #define ENC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
35142 
35143 #define ENC_IMR_PHA_MASK                         (0x8U)
35144 #define ENC_IMR_PHA_SHIFT                        (3U)
35145 /*! PHA - PHA
35146  */
35147 #define ENC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
35148 
35149 #define ENC_IMR_FHOM_MASK                        (0x10U)
35150 #define ENC_IMR_FHOM_SHIFT                       (4U)
35151 /*! FHOM - FHOM
35152  */
35153 #define ENC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
35154 
35155 #define ENC_IMR_FIND_MASK                        (0x20U)
35156 #define ENC_IMR_FIND_SHIFT                       (5U)
35157 /*! FIND - FIND
35158  */
35159 #define ENC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
35160 
35161 #define ENC_IMR_FPHB_MASK                        (0x40U)
35162 #define ENC_IMR_FPHB_SHIFT                       (6U)
35163 /*! FPHB - FPHB
35164  */
35165 #define ENC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
35166 
35167 #define ENC_IMR_FPHA_MASK                        (0x80U)
35168 #define ENC_IMR_FPHA_SHIFT                       (7U)
35169 /*! FPHA - FPHA
35170  */
35171 #define ENC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
35172 /*! @} */
35173 
35174 /*! @name TST - Test Register */
35175 /*! @{ */
35176 
35177 #define ENC_TST_TEST_COUNT_MASK                  (0xFFU)
35178 #define ENC_TST_TEST_COUNT_SHIFT                 (0U)
35179 /*! TEST_COUNT - TEST_COUNT
35180  */
35181 #define ENC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
35182 
35183 #define ENC_TST_TEST_PERIOD_MASK                 (0x1F00U)
35184 #define ENC_TST_TEST_PERIOD_SHIFT                (8U)
35185 /*! TEST_PERIOD - TEST_PERIOD
35186  */
35187 #define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
35188 
35189 #define ENC_TST_QDN_MASK                         (0x2000U)
35190 #define ENC_TST_QDN_SHIFT                        (13U)
35191 /*! QDN - Quadrature Decoder Negative Signal
35192  *  0b0..Generates a positive quadrature decoder signal
35193  *  0b1..Generates a negative quadrature decoder signal
35194  */
35195 #define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
35196 
35197 #define ENC_TST_TCE_MASK                         (0x4000U)
35198 #define ENC_TST_TCE_SHIFT                        (14U)
35199 /*! TCE - Test Counter Enable
35200  *  0b0..Disabled
35201  *  0b1..Enabled
35202  */
35203 #define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
35204 
35205 #define ENC_TST_TEN_MASK                         (0x8000U)
35206 #define ENC_TST_TEN_SHIFT                        (15U)
35207 /*! TEN - Test Mode Enable
35208  *  0b0..Disabled
35209  *  0b1..Enabled
35210  */
35211 #define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
35212 /*! @} */
35213 
35214 /*! @name CTRL2 - Control 2 Register */
35215 /*! @{ */
35216 
35217 #define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
35218 #define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
35219 /*! UPDHLD - Update Hold Registers
35220  *  0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
35221  *  0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
35222  */
35223 #define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
35224 
35225 #define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
35226 #define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
35227 /*! UPDPOS - Update Position Registers
35228  *  0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
35229  *  0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
35230  */
35231 #define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
35232 
35233 #define ENC_CTRL2_MOD_MASK                       (0x4U)
35234 #define ENC_CTRL2_MOD_SHIFT                      (2U)
35235 /*! MOD - Enable Modulo Counting
35236  *  0b0..Disable modulo counting
35237  *  0b1..Enable modulo counting
35238  */
35239 #define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
35240 
35241 #define ENC_CTRL2_DIR_MASK                       (0x8U)
35242 #define ENC_CTRL2_DIR_SHIFT                      (3U)
35243 /*! DIR - Count Direction Flag
35244  *  0b0..Last count was in the down direction
35245  *  0b1..Last count was in the up direction
35246  */
35247 #define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
35248 
35249 #define ENC_CTRL2_RUIE_MASK                      (0x10U)
35250 #define ENC_CTRL2_RUIE_SHIFT                     (4U)
35251 /*! RUIE - Roll-under Interrupt Enable
35252  *  0b0..Disabled
35253  *  0b1..Enabled
35254  */
35255 #define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
35256 
35257 #define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
35258 #define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
35259 /*! RUIRQ - Roll-under Interrupt Request
35260  *  0b0..No roll-under has occurred
35261  *  0b1..Roll-under has occurred
35262  */
35263 #define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
35264 
35265 #define ENC_CTRL2_ROIE_MASK                      (0x40U)
35266 #define ENC_CTRL2_ROIE_SHIFT                     (6U)
35267 /*! ROIE - Roll-over Interrupt Enable
35268  *  0b0..Disabled
35269  *  0b1..Enabled
35270  */
35271 #define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
35272 
35273 #define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
35274 #define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
35275 /*! ROIRQ - Roll-over Interrupt Request
35276  *  0b0..No roll-over has occurred
35277  *  0b1..Roll-over has occurred
35278  */
35279 #define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
35280 
35281 #define ENC_CTRL2_REVMOD_MASK                    (0x100U)
35282 #define ENC_CTRL2_REVMOD_SHIFT                   (8U)
35283 /*! REVMOD - Revolution Counter Modulus Enable
35284  *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
35285  *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
35286  */
35287 #define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
35288 
35289 #define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
35290 #define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
35291 /*! OUTCTL - Output Control
35292  *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
35293  *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
35294  */
35295 #define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
35296 
35297 #define ENC_CTRL2_SABIE_MASK                     (0x400U)
35298 #define ENC_CTRL2_SABIE_SHIFT                    (10U)
35299 /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
35300  *  0b0..Disabled
35301  *  0b1..Enabled
35302  */
35303 #define ENC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
35304 
35305 #define ENC_CTRL2_SABIRQ_MASK                    (0x800U)
35306 #define ENC_CTRL2_SABIRQ_SHIFT                   (11U)
35307 /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
35308  *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
35309  *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
35310  */
35311 #define ENC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
35312 /*! @} */
35313 
35314 /*! @name UMOD - Upper Modulus Register */
35315 /*! @{ */
35316 
35317 #define ENC_UMOD_MOD_MASK                        (0xFFFFU)
35318 #define ENC_UMOD_MOD_SHIFT                       (0U)
35319 /*! MOD - MOD
35320  */
35321 #define ENC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
35322 /*! @} */
35323 
35324 /*! @name LMOD - Lower Modulus Register */
35325 /*! @{ */
35326 
35327 #define ENC_LMOD_MOD_MASK                        (0xFFFFU)
35328 #define ENC_LMOD_MOD_SHIFT                       (0U)
35329 /*! MOD - MOD
35330  */
35331 #define ENC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
35332 /*! @} */
35333 
35334 /*! @name UCOMP - Upper Position Compare Register */
35335 /*! @{ */
35336 
35337 #define ENC_UCOMP_COMP_MASK                      (0xFFFFU)
35338 #define ENC_UCOMP_COMP_SHIFT                     (0U)
35339 /*! COMP - COMP
35340  */
35341 #define ENC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
35342 /*! @} */
35343 
35344 /*! @name LCOMP - Lower Position Compare Register */
35345 /*! @{ */
35346 
35347 #define ENC_LCOMP_COMP_MASK                      (0xFFFFU)
35348 #define ENC_LCOMP_COMP_SHIFT                     (0U)
35349 /*! COMP - COMP
35350  */
35351 #define ENC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
35352 /*! @} */
35353 
35354 /*! @name LASTEDGE - Last Edge Time Register */
35355 /*! @{ */
35356 
35357 #define ENC_LASTEDGE_LASTEDGE_MASK               (0xFFFFU)
35358 #define ENC_LASTEDGE_LASTEDGE_SHIFT              (0U)
35359 /*! LASTEDGE - Last Edge Time Counter
35360  */
35361 #define ENC_LASTEDGE_LASTEDGE(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
35362 /*! @} */
35363 
35364 /*! @name LASTEDGEH - Last Edge Time Hold Register */
35365 /*! @{ */
35366 
35367 #define ENC_LASTEDGEH_LASTEDGEH_MASK             (0xFFFFU)
35368 #define ENC_LASTEDGEH_LASTEDGEH_SHIFT            (0U)
35369 /*! LASTEDGEH - Last Edge Time Hold
35370  */
35371 #define ENC_LASTEDGEH_LASTEDGEH(x)               (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
35372 /*! @} */
35373 
35374 /*! @name POSDPER - Position Difference Period Counter Register */
35375 /*! @{ */
35376 
35377 #define ENC_POSDPER_POSDPER_MASK                 (0xFFFFU)
35378 #define ENC_POSDPER_POSDPER_SHIFT                (0U)
35379 /*! POSDPER - Position difference period
35380  */
35381 #define ENC_POSDPER_POSDPER(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
35382 /*! @} */
35383 
35384 /*! @name POSDPERBFR - Position Difference Period Buffer Register */
35385 /*! @{ */
35386 
35387 #define ENC_POSDPERBFR_POSDPERBFR_MASK           (0xFFFFU)
35388 #define ENC_POSDPERBFR_POSDPERBFR_SHIFT          (0U)
35389 /*! POSDPERBFR - Position difference period buffer
35390  */
35391 #define ENC_POSDPERBFR_POSDPERBFR(x)             (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
35392 /*! @} */
35393 
35394 /*! @name POSDPERH - Position Difference Period Hold Register */
35395 /*! @{ */
35396 
35397 #define ENC_POSDPERH_POSDPERH_MASK               (0xFFFFU)
35398 #define ENC_POSDPERH_POSDPERH_SHIFT              (0U)
35399 /*! POSDPERH - Position difference period hold
35400  */
35401 #define ENC_POSDPERH_POSDPERH(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
35402 /*! @} */
35403 
35404 /*! @name CTRL3 - Control 3 Register */
35405 /*! @{ */
35406 
35407 #define ENC_CTRL3_PMEN_MASK                      (0x1U)
35408 #define ENC_CTRL3_PMEN_SHIFT                     (0U)
35409 /*! PMEN - Period measurement function enable
35410  *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read.
35411  *  0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.
35412  */
35413 #define ENC_CTRL3_PMEN(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)
35414 
35415 #define ENC_CTRL3_PRSC_MASK                      (0xF0U)
35416 #define ENC_CTRL3_PRSC_SHIFT                     (4U)
35417 /*! PRSC - Prescaler
35418  */
35419 #define ENC_CTRL3_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)
35420 /*! @} */
35421 
35422 
35423 /*!
35424  * @}
35425  */ /* end of group ENC_Register_Masks */
35426 
35427 
35428 /* ENC - Peripheral instance base addresses */
35429 /** Peripheral ENC1 base address */
35430 #define ENC1_BASE                                (0x40174000u)
35431 /** Peripheral ENC1 base pointer */
35432 #define ENC1                                     ((ENC_Type *)ENC1_BASE)
35433 /** Peripheral ENC2 base address */
35434 #define ENC2_BASE                                (0x40178000u)
35435 /** Peripheral ENC2 base pointer */
35436 #define ENC2                                     ((ENC_Type *)ENC2_BASE)
35437 /** Peripheral ENC3 base address */
35438 #define ENC3_BASE                                (0x4017C000u)
35439 /** Peripheral ENC3 base pointer */
35440 #define ENC3                                     ((ENC_Type *)ENC3_BASE)
35441 /** Peripheral ENC4 base address */
35442 #define ENC4_BASE                                (0x40180000u)
35443 /** Peripheral ENC4 base pointer */
35444 #define ENC4                                     ((ENC_Type *)ENC4_BASE)
35445 /** Array initializer of ENC peripheral base addresses */
35446 #define ENC_BASE_ADDRS                           { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
35447 /** Array initializer of ENC peripheral base pointers */
35448 #define ENC_BASE_PTRS                            { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
35449 /** Interrupt vectors for the ENC peripheral type */
35450 #define ENC_COMPARE_IRQS                         { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35451 #define ENC_HOME_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35452 #define ENC_WDOG_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35453 #define ENC_INDEX_IRQS                           { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35454 #define ENC_INPUT_SWITCH_IRQS                    { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
35455 
35456 /*!
35457  * @}
35458  */ /* end of group ENC_Peripheral_Access_Layer */
35459 
35460 
35461 /* ----------------------------------------------------------------------------
35462    -- ENET Peripheral Access Layer
35463    ---------------------------------------------------------------------------- */
35464 
35465 /*!
35466  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
35467  * @{
35468  */
35469 
35470 /** ENET - Register Layout Typedef */
35471 typedef struct {
35472        uint8_t RESERVED_0[4];
35473   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
35474   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
35475        uint8_t RESERVED_1[4];
35476   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
35477   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
35478        uint8_t RESERVED_2[12];
35479   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
35480        uint8_t RESERVED_3[24];
35481   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
35482   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
35483        uint8_t RESERVED_4[28];
35484   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
35485        uint8_t RESERVED_5[28];
35486   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
35487        uint8_t RESERVED_6[60];
35488   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
35489        uint8_t RESERVED_7[28];
35490   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
35491   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
35492   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
35493   __IO uint32_t TXIC[3];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
35494        uint8_t RESERVED_8[4];
35495   __IO uint32_t RXIC[3];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
35496        uint8_t RESERVED_9[12];
35497   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
35498   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
35499   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
35500   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
35501        uint8_t RESERVED_10[28];
35502   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
35503        uint8_t RESERVED_11[24];
35504   __IO uint32_t RDSR1;                             /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
35505   __IO uint32_t TDSR1;                             /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
35506   __IO uint32_t MRBR1;                             /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
35507   __IO uint32_t RDSR2;                             /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
35508   __IO uint32_t TDSR2;                             /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
35509   __IO uint32_t MRBR2;                             /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
35510        uint8_t RESERVED_12[8];
35511   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
35512   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
35513   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
35514        uint8_t RESERVED_13[4];
35515   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
35516   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
35517   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
35518   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
35519   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
35520   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
35521   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
35522   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
35523   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
35524        uint8_t RESERVED_14[12];
35525   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
35526   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
35527   __IO uint32_t RCMR[2];                           /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
35528        uint8_t RESERVED_15[8];
35529   __IO uint32_t DMACFG[2];                         /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
35530   __IO uint32_t RDAR1;                             /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
35531   __IO uint32_t TDAR1;                             /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
35532   __IO uint32_t RDAR2;                             /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
35533   __IO uint32_t TDAR2;                             /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
35534   __IO uint32_t QOS;                               /**< QOS Scheme, offset: 0x1F0 */
35535        uint8_t RESERVED_16[16];
35536   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
35537   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
35538   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
35539   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
35540   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
35541   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
35542   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
35543   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
35544   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
35545   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
35546   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
35547   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
35548   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
35549   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
35550   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
35551   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
35552   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
35553        uint32_t IEEE_T_DROP;                       /**< Reserved Statistic Register, offset: 0x248 */
35554   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
35555   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
35556   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
35557   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
35558   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
35559   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
35560   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
35561   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
35562   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
35563   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
35564   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
35565        uint8_t RESERVED_17[12];
35566   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
35567   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
35568   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
35569   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
35570   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
35571   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
35572   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
35573   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
35574        uint8_t RESERVED_18[4];
35575   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
35576   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
35577   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
35578   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
35579   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
35580   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
35581   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
35582   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
35583   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
35584   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
35585   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
35586   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
35587   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
35588   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
35589   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
35590        uint8_t RESERVED_19[284];
35591   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
35592   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
35593   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
35594   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
35595   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
35596   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
35597   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
35598        uint8_t RESERVED_20[488];
35599   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
35600   struct {                                         /* offset: 0x608, array step: 0x8 */
35601     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
35602     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
35603   } CHANNEL[4];
35604 } ENET_Type;
35605 
35606 /* ----------------------------------------------------------------------------
35607    -- ENET Register Masks
35608    ---------------------------------------------------------------------------- */
35609 
35610 /*!
35611  * @addtogroup ENET_Register_Masks ENET Register Masks
35612  * @{
35613  */
35614 
35615 /*! @name EIR - Interrupt Event Register */
35616 /*! @{ */
35617 
35618 #define ENET_EIR_RXB1_MASK                       (0x1U)
35619 #define ENET_EIR_RXB1_SHIFT                      (0U)
35620 /*! RXB1 - Receive buffer interrupt, class 1
35621  */
35622 #define ENET_EIR_RXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
35623 
35624 #define ENET_EIR_RXF1_MASK                       (0x2U)
35625 #define ENET_EIR_RXF1_SHIFT                      (1U)
35626 /*! RXF1 - Receive frame interrupt, class 1
35627  */
35628 #define ENET_EIR_RXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
35629 
35630 #define ENET_EIR_TXB1_MASK                       (0x4U)
35631 #define ENET_EIR_TXB1_SHIFT                      (2U)
35632 /*! TXB1 - Transmit buffer interrupt, class 1
35633  */
35634 #define ENET_EIR_TXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
35635 
35636 #define ENET_EIR_TXF1_MASK                       (0x8U)
35637 #define ENET_EIR_TXF1_SHIFT                      (3U)
35638 /*! TXF1 - Transmit frame interrupt, class 1
35639  */
35640 #define ENET_EIR_TXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
35641 
35642 #define ENET_EIR_RXB2_MASK                       (0x10U)
35643 #define ENET_EIR_RXB2_SHIFT                      (4U)
35644 /*! RXB2 - Receive buffer interrupt, class 2
35645  */
35646 #define ENET_EIR_RXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
35647 
35648 #define ENET_EIR_RXF2_MASK                       (0x20U)
35649 #define ENET_EIR_RXF2_SHIFT                      (5U)
35650 /*! RXF2 - Receive frame interrupt, class 2
35651  */
35652 #define ENET_EIR_RXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
35653 
35654 #define ENET_EIR_TXB2_MASK                       (0x40U)
35655 #define ENET_EIR_TXB2_SHIFT                      (6U)
35656 /*! TXB2 - Transmit buffer interrupt, class 2
35657  */
35658 #define ENET_EIR_TXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
35659 
35660 #define ENET_EIR_TXF2_MASK                       (0x80U)
35661 #define ENET_EIR_TXF2_SHIFT                      (7U)
35662 /*! TXF2 - Transmit frame interrupt, class 2
35663  */
35664 #define ENET_EIR_TXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
35665 
35666 #define ENET_EIR_RXFLUSH_0_MASK                  (0x1000U)
35667 #define ENET_EIR_RXFLUSH_0_SHIFT                 (12U)
35668 #define ENET_EIR_RXFLUSH_0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
35669 
35670 #define ENET_EIR_RXFLUSH_1_MASK                  (0x2000U)
35671 #define ENET_EIR_RXFLUSH_1_SHIFT                 (13U)
35672 #define ENET_EIR_RXFLUSH_1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
35673 
35674 #define ENET_EIR_RXFLUSH_2_MASK                  (0x4000U)
35675 #define ENET_EIR_RXFLUSH_2_SHIFT                 (14U)
35676 #define ENET_EIR_RXFLUSH_2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
35677 
35678 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
35679 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
35680 /*! TS_TIMER - Timestamp Timer
35681  */
35682 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
35683 
35684 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
35685 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
35686 /*! TS_AVAIL - Transmit Timestamp Available
35687  */
35688 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
35689 
35690 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
35691 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
35692 /*! WAKEUP - Node Wakeup Request Indication
35693  */
35694 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
35695 
35696 #define ENET_EIR_PLR_MASK                        (0x40000U)
35697 #define ENET_EIR_PLR_SHIFT                       (18U)
35698 /*! PLR - Payload Receive Error
35699  */
35700 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
35701 
35702 #define ENET_EIR_UN_MASK                         (0x80000U)
35703 #define ENET_EIR_UN_SHIFT                        (19U)
35704 /*! UN - Transmit FIFO Underrun
35705  */
35706 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
35707 
35708 #define ENET_EIR_RL_MASK                         (0x100000U)
35709 #define ENET_EIR_RL_SHIFT                        (20U)
35710 /*! RL - Collision Retry Limit
35711  */
35712 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
35713 
35714 #define ENET_EIR_LC_MASK                         (0x200000U)
35715 #define ENET_EIR_LC_SHIFT                        (21U)
35716 /*! LC - Late Collision
35717  */
35718 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
35719 
35720 #define ENET_EIR_EBERR_MASK                      (0x400000U)
35721 #define ENET_EIR_EBERR_SHIFT                     (22U)
35722 /*! EBERR - Ethernet Bus Error
35723  */
35724 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
35725 
35726 #define ENET_EIR_MII_MASK                        (0x800000U)
35727 #define ENET_EIR_MII_SHIFT                       (23U)
35728 /*! MII - MII Interrupt.
35729  */
35730 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
35731 
35732 #define ENET_EIR_RXB_MASK                        (0x1000000U)
35733 #define ENET_EIR_RXB_SHIFT                       (24U)
35734 /*! RXB - Receive Buffer Interrupt
35735  */
35736 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
35737 
35738 #define ENET_EIR_RXF_MASK                        (0x2000000U)
35739 #define ENET_EIR_RXF_SHIFT                       (25U)
35740 /*! RXF - Receive Frame Interrupt
35741  */
35742 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
35743 
35744 #define ENET_EIR_TXB_MASK                        (0x4000000U)
35745 #define ENET_EIR_TXB_SHIFT                       (26U)
35746 /*! TXB - Transmit Buffer Interrupt
35747  */
35748 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
35749 
35750 #define ENET_EIR_TXF_MASK                        (0x8000000U)
35751 #define ENET_EIR_TXF_SHIFT                       (27U)
35752 /*! TXF - Transmit Frame Interrupt
35753  */
35754 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
35755 
35756 #define ENET_EIR_GRA_MASK                        (0x10000000U)
35757 #define ENET_EIR_GRA_SHIFT                       (28U)
35758 /*! GRA - Graceful Stop Complete
35759  */
35760 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
35761 
35762 #define ENET_EIR_BABT_MASK                       (0x20000000U)
35763 #define ENET_EIR_BABT_SHIFT                      (29U)
35764 /*! BABT - Babbling Transmit Error
35765  */
35766 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
35767 
35768 #define ENET_EIR_BABR_MASK                       (0x40000000U)
35769 #define ENET_EIR_BABR_SHIFT                      (30U)
35770 /*! BABR - Babbling Receive Error
35771  */
35772 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
35773 /*! @} */
35774 
35775 /*! @name EIMR - Interrupt Mask Register */
35776 /*! @{ */
35777 
35778 #define ENET_EIMR_RXB1_MASK                      (0x1U)
35779 #define ENET_EIMR_RXB1_SHIFT                     (0U)
35780 /*! RXB1 - Receive buffer interrupt, class 1
35781  *  0b0..The corresponding interrupt source is masked.
35782  *  0b1..The corresponding interrupt source is not masked.
35783  */
35784 #define ENET_EIMR_RXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
35785 
35786 #define ENET_EIMR_RXF1_MASK                      (0x2U)
35787 #define ENET_EIMR_RXF1_SHIFT                     (1U)
35788 /*! RXF1 - Receive frame interrupt, class 1
35789  *  0b0..The corresponding interrupt source is masked.
35790  *  0b1..The corresponding interrupt source is not masked.
35791  */
35792 #define ENET_EIMR_RXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
35793 
35794 #define ENET_EIMR_TXB1_MASK                      (0x4U)
35795 #define ENET_EIMR_TXB1_SHIFT                     (2U)
35796 /*! TXB1 - Transmit buffer interrupt, class 1
35797  *  0b0..The corresponding interrupt source is masked.
35798  *  0b1..The corresponding interrupt source is not masked.
35799  */
35800 #define ENET_EIMR_TXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
35801 
35802 #define ENET_EIMR_TXF1_MASK                      (0x8U)
35803 #define ENET_EIMR_TXF1_SHIFT                     (3U)
35804 /*! TXF1 - Transmit frame interrupt, class 1
35805  *  0b0..The corresponding interrupt source is masked.
35806  *  0b1..The corresponding interrupt source is not masked.
35807  */
35808 #define ENET_EIMR_TXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
35809 
35810 #define ENET_EIMR_RXB2_MASK                      (0x10U)
35811 #define ENET_EIMR_RXB2_SHIFT                     (4U)
35812 /*! RXB2 - Receive buffer interrupt, class 2
35813  *  0b0..The corresponding interrupt source is masked.
35814  *  0b1..The corresponding interrupt source is not masked.
35815  */
35816 #define ENET_EIMR_RXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
35817 
35818 #define ENET_EIMR_RXF2_MASK                      (0x20U)
35819 #define ENET_EIMR_RXF2_SHIFT                     (5U)
35820 /*! RXF2 - Receive frame interrupt, class 2
35821  *  0b0..The corresponding interrupt source is masked.
35822  *  0b1..The corresponding interrupt source is not masked.
35823  */
35824 #define ENET_EIMR_RXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
35825 
35826 #define ENET_EIMR_TXB2_MASK                      (0x40U)
35827 #define ENET_EIMR_TXB2_SHIFT                     (6U)
35828 /*! TXB2 - Transmit buffer interrupt, class 2
35829  *  0b0..The corresponding interrupt source is masked.
35830  *  0b1..The corresponding interrupt source is not masked.
35831  */
35832 #define ENET_EIMR_TXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
35833 
35834 #define ENET_EIMR_TXF2_MASK                      (0x80U)
35835 #define ENET_EIMR_TXF2_SHIFT                     (7U)
35836 /*! TXF2 - Transmit frame interrupt, class 2
35837  *  0b0..The corresponding interrupt source is masked.
35838  *  0b1..The corresponding interrupt source is not masked.
35839  */
35840 #define ENET_EIMR_TXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
35841 
35842 #define ENET_EIMR_RXFLUSH_0_MASK                 (0x1000U)
35843 #define ENET_EIMR_RXFLUSH_0_SHIFT                (12U)
35844 /*! RXFLUSH_0
35845  *  0b0..The corresponding interrupt source is masked.
35846  *  0b1..The corresponding interrupt source is not masked.
35847  */
35848 #define ENET_EIMR_RXFLUSH_0(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
35849 
35850 #define ENET_EIMR_RXFLUSH_1_MASK                 (0x2000U)
35851 #define ENET_EIMR_RXFLUSH_1_SHIFT                (13U)
35852 /*! RXFLUSH_1
35853  *  0b0..The corresponding interrupt source is masked.
35854  *  0b1..The corresponding interrupt source is not masked.
35855  */
35856 #define ENET_EIMR_RXFLUSH_1(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
35857 
35858 #define ENET_EIMR_RXFLUSH_2_MASK                 (0x4000U)
35859 #define ENET_EIMR_RXFLUSH_2_SHIFT                (14U)
35860 /*! RXFLUSH_2
35861  *  0b0..The corresponding interrupt source is masked.
35862  *  0b1..The corresponding interrupt source is not masked.
35863  */
35864 #define ENET_EIMR_RXFLUSH_2(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
35865 
35866 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
35867 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
35868 /*! TS_TIMER - TS_TIMER Interrupt Mask
35869  *  0b0..The corresponding interrupt source is masked.
35870  *  0b1..The corresponding interrupt source is not masked.
35871  */
35872 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
35873 
35874 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
35875 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
35876 /*! TS_AVAIL - TS_AVAIL Interrupt Mask
35877  *  0b0..The corresponding interrupt source is masked.
35878  *  0b1..The corresponding interrupt source is not masked.
35879  */
35880 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
35881 
35882 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
35883 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
35884 /*! WAKEUP - WAKEUP Interrupt Mask
35885  *  0b0..The corresponding interrupt source is masked.
35886  *  0b1..The corresponding interrupt source is not masked.
35887  */
35888 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
35889 
35890 #define ENET_EIMR_PLR_MASK                       (0x40000U)
35891 #define ENET_EIMR_PLR_SHIFT                      (18U)
35892 /*! PLR - PLR Interrupt Mask
35893  *  0b0..The corresponding interrupt source is masked.
35894  *  0b1..The corresponding interrupt source is not masked.
35895  */
35896 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
35897 
35898 #define ENET_EIMR_UN_MASK                        (0x80000U)
35899 #define ENET_EIMR_UN_SHIFT                       (19U)
35900 /*! UN - UN Interrupt Mask
35901  *  0b0..The corresponding interrupt source is masked.
35902  *  0b1..The corresponding interrupt source is not masked.
35903  */
35904 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
35905 
35906 #define ENET_EIMR_RL_MASK                        (0x100000U)
35907 #define ENET_EIMR_RL_SHIFT                       (20U)
35908 /*! RL - RL Interrupt Mask
35909  *  0b0..The corresponding interrupt source is masked.
35910  *  0b1..The corresponding interrupt source is not masked.
35911  */
35912 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
35913 
35914 #define ENET_EIMR_LC_MASK                        (0x200000U)
35915 #define ENET_EIMR_LC_SHIFT                       (21U)
35916 /*! LC - LC Interrupt Mask
35917  *  0b0..The corresponding interrupt source is masked.
35918  *  0b1..The corresponding interrupt source is not masked.
35919  */
35920 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
35921 
35922 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
35923 #define ENET_EIMR_EBERR_SHIFT                    (22U)
35924 /*! EBERR - EBERR Interrupt Mask
35925  *  0b0..The corresponding interrupt source is masked.
35926  *  0b1..The corresponding interrupt source is not masked.
35927  */
35928 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
35929 
35930 #define ENET_EIMR_MII_MASK                       (0x800000U)
35931 #define ENET_EIMR_MII_SHIFT                      (23U)
35932 /*! MII - MII Interrupt Mask
35933  *  0b0..The corresponding interrupt source is masked.
35934  *  0b1..The corresponding interrupt source is not masked.
35935  */
35936 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
35937 
35938 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
35939 #define ENET_EIMR_RXB_SHIFT                      (24U)
35940 /*! RXB - RXB Interrupt Mask
35941  *  0b0..The corresponding interrupt source is masked.
35942  *  0b1..The corresponding interrupt source is not masked.
35943  */
35944 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
35945 
35946 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
35947 #define ENET_EIMR_RXF_SHIFT                      (25U)
35948 /*! RXF - RXF Interrupt Mask
35949  *  0b0..The corresponding interrupt source is masked.
35950  *  0b1..The corresponding interrupt source is not masked.
35951  */
35952 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
35953 
35954 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
35955 #define ENET_EIMR_TXB_SHIFT                      (26U)
35956 /*! TXB - TXB Interrupt Mask
35957  *  0b0..The corresponding interrupt source is masked.
35958  *  0b1..The corresponding interrupt source is not masked.
35959  */
35960 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
35961 
35962 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
35963 #define ENET_EIMR_TXF_SHIFT                      (27U)
35964 /*! TXF - TXF Interrupt Mask
35965  *  0b0..The corresponding interrupt source is masked.
35966  *  0b1..The corresponding interrupt source is not masked.
35967  */
35968 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
35969 
35970 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
35971 #define ENET_EIMR_GRA_SHIFT                      (28U)
35972 /*! GRA - GRA Interrupt Mask
35973  *  0b0..The corresponding interrupt source is masked.
35974  *  0b1..The corresponding interrupt source is not masked.
35975  */
35976 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
35977 
35978 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
35979 #define ENET_EIMR_BABT_SHIFT                     (29U)
35980 /*! BABT - BABT Interrupt Mask
35981  *  0b0..The corresponding interrupt source is masked.
35982  *  0b1..The corresponding interrupt source is not masked.
35983  */
35984 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
35985 
35986 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
35987 #define ENET_EIMR_BABR_SHIFT                     (30U)
35988 /*! BABR - BABR Interrupt Mask
35989  *  0b0..The corresponding interrupt source is masked.
35990  *  0b1..The corresponding interrupt source is not masked.
35991  */
35992 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
35993 /*! @} */
35994 
35995 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
35996 /*! @{ */
35997 
35998 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
35999 #define ENET_RDAR_RDAR_SHIFT                     (24U)
36000 /*! RDAR - Receive Descriptor Active
36001  */
36002 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
36003 /*! @} */
36004 
36005 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
36006 /*! @{ */
36007 
36008 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
36009 #define ENET_TDAR_TDAR_SHIFT                     (24U)
36010 /*! TDAR - Transmit Descriptor Active
36011  */
36012 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
36013 /*! @} */
36014 
36015 /*! @name ECR - Ethernet Control Register */
36016 /*! @{ */
36017 
36018 #define ENET_ECR_RESET_MASK                      (0x1U)
36019 #define ENET_ECR_RESET_SHIFT                     (0U)
36020 /*! RESET - Ethernet MAC Reset
36021  */
36022 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
36023 
36024 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
36025 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
36026 /*! ETHEREN - Ethernet Enable
36027  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
36028  *  0b1..MAC is enabled, and reception and transmission are possible.
36029  */
36030 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
36031 
36032 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
36033 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
36034 /*! MAGICEN - Magic Packet Detection Enable
36035  *  0b0..Magic detection logic disabled.
36036  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
36037  */
36038 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
36039 
36040 #define ENET_ECR_SLEEP_MASK                      (0x8U)
36041 #define ENET_ECR_SLEEP_SHIFT                     (3U)
36042 /*! SLEEP - Sleep Mode Enable
36043  *  0b0..Normal operating mode.
36044  *  0b1..Sleep mode.
36045  */
36046 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
36047 
36048 #define ENET_ECR_EN1588_MASK                     (0x10U)
36049 #define ENET_ECR_EN1588_SHIFT                    (4U)
36050 /*! EN1588 - EN1588 Enable
36051  *  0b0..Legacy FEC buffer descriptors and functions enabled.
36052  *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
36053  */
36054 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
36055 
36056 #define ENET_ECR_SPEED_MASK                      (0x20U)
36057 #define ENET_ECR_SPEED_SHIFT                     (5U)
36058 /*! SPEED
36059  *  0b0..10/100-Mbit/s mode
36060  *  0b1..1000-Mbit/s mode
36061  */
36062 #define ENET_ECR_SPEED(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
36063 
36064 #define ENET_ECR_DBGEN_MASK                      (0x40U)
36065 #define ENET_ECR_DBGEN_SHIFT                     (6U)
36066 /*! DBGEN - Debug Enable
36067  *  0b0..MAC continues operation in debug mode.
36068  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
36069  */
36070 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
36071 
36072 #define ENET_ECR_DBSWP_MASK                      (0x100U)
36073 #define ENET_ECR_DBSWP_SHIFT                     (8U)
36074 /*! DBSWP - Descriptor Byte Swapping Enable
36075  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
36076  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
36077  */
36078 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
36079 
36080 #define ENET_ECR_SVLANEN_MASK                    (0x200U)
36081 #define ENET_ECR_SVLANEN_SHIFT                   (9U)
36082 /*! SVLANEN - S-VLAN enable
36083  *  0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
36084  *  0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
36085  *       receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
36086  *       classification match comparators, RCMRn.
36087  */
36088 #define ENET_ECR_SVLANEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
36089 
36090 #define ENET_ECR_VLANUSE2ND_MASK                 (0x400U)
36091 #define ENET_ECR_VLANUSE2ND_SHIFT                (10U)
36092 /*! VLANUSE2ND - VLAN use second tag
36093  *  0b0..Always extract data from the first VLAN tag if it exists.
36094  *  0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
36095  *       double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
36096  *       second tag must be a C-VLAN
36097  */
36098 #define ENET_ECR_VLANUSE2ND(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
36099 
36100 #define ENET_ECR_SVLANDBL_MASK                   (0x800U)
36101 #define ENET_ECR_SVLANDBL_SHIFT                  (11U)
36102 /*! SVLANDBL - S-VLAN double tag
36103  *  0b0..Disable S-VLAN double tag
36104  *  0b1..Enable S-VLAN double tag
36105  */
36106 #define ENET_ECR_SVLANDBL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
36107 
36108 #define ENET_ECR_TXC_DLY_MASK                    (0x10000U)
36109 #define ENET_ECR_TXC_DLY_SHIFT                   (16U)
36110 /*! TXC_DLY - Transmit clock delay
36111  *  0b0..RGMII_TXC is not delayed.
36112  *  0b1..Generate delayed version of RGMII_TXC.
36113  */
36114 #define ENET_ECR_TXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
36115 /*! @} */
36116 
36117 /*! @name MMFR - MII Management Frame Register */
36118 /*! @{ */
36119 
36120 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
36121 #define ENET_MMFR_DATA_SHIFT                     (0U)
36122 /*! DATA - Management Frame Data
36123  */
36124 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
36125 
36126 #define ENET_MMFR_TA_MASK                        (0x30000U)
36127 #define ENET_MMFR_TA_SHIFT                       (16U)
36128 /*! TA - Turn Around
36129  */
36130 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
36131 
36132 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
36133 #define ENET_MMFR_RA_SHIFT                       (18U)
36134 /*! RA - Register Address
36135  */
36136 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
36137 
36138 #define ENET_MMFR_PA_MASK                        (0xF800000U)
36139 #define ENET_MMFR_PA_SHIFT                       (23U)
36140 /*! PA - PHY Address
36141  */
36142 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
36143 
36144 #define ENET_MMFR_OP_MASK                        (0x30000000U)
36145 #define ENET_MMFR_OP_SHIFT                       (28U)
36146 /*! OP - Operation Code
36147  */
36148 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
36149 
36150 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
36151 #define ENET_MMFR_ST_SHIFT                       (30U)
36152 /*! ST - Start Of Frame Delimiter
36153  */
36154 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
36155 /*! @} */
36156 
36157 /*! @name MSCR - MII Speed Control Register */
36158 /*! @{ */
36159 
36160 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
36161 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
36162 /*! MII_SPEED - MII Speed
36163  */
36164 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
36165 
36166 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
36167 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
36168 /*! DIS_PRE - Disable Preamble
36169  *  0b0..Preamble enabled.
36170  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
36171  */
36172 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
36173 
36174 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
36175 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
36176 /*! HOLDTIME - Hold time On MDIO Output
36177  *  0b000..1 internal module clock cycle
36178  *  0b001..2 internal module clock cycles
36179  *  0b010..3 internal module clock cycles
36180  *  0b111..8 internal module clock cycles
36181  */
36182 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
36183 /*! @} */
36184 
36185 /*! @name MIBC - MIB Control Register */
36186 /*! @{ */
36187 
36188 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
36189 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
36190 /*! MIB_CLEAR - MIB Clear
36191  *  0b0..See note above.
36192  *  0b1..All statistics counters are reset to 0.
36193  */
36194 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
36195 
36196 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
36197 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
36198 /*! MIB_IDLE - MIB Idle
36199  *  0b0..The MIB block is updating MIB counters.
36200  *  0b1..The MIB block is not currently updating any MIB counters.
36201  */
36202 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
36203 
36204 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
36205 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
36206 /*! MIB_DIS - Disable MIB Logic
36207  *  0b0..MIB logic is enabled.
36208  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
36209  */
36210 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
36211 /*! @} */
36212 
36213 /*! @name RCR - Receive Control Register */
36214 /*! @{ */
36215 
36216 #define ENET_RCR_LOOP_MASK                       (0x1U)
36217 #define ENET_RCR_LOOP_SHIFT                      (0U)
36218 /*! LOOP - Internal Loopback
36219  *  0b0..Loopback disabled.
36220  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
36221  */
36222 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
36223 
36224 #define ENET_RCR_DRT_MASK                        (0x2U)
36225 #define ENET_RCR_DRT_SHIFT                       (1U)
36226 /*! DRT - Disable Receive On Transmit
36227  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
36228  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
36229  */
36230 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
36231 
36232 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
36233 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
36234 /*! MII_MODE - Media Independent Interface Mode
36235  *  0b0..Reserved.
36236  *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
36237  */
36238 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
36239 
36240 #define ENET_RCR_PROM_MASK                       (0x8U)
36241 #define ENET_RCR_PROM_SHIFT                      (3U)
36242 /*! PROM - Promiscuous Mode
36243  *  0b0..Disabled.
36244  *  0b1..Enabled.
36245  */
36246 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
36247 
36248 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
36249 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
36250 /*! BC_REJ - Broadcast Frame Reject
36251  *  0b0..Will not reject frames as described above
36252  *  0b1..Will reject frames as described above
36253  */
36254 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
36255 
36256 #define ENET_RCR_FCE_MASK                        (0x20U)
36257 #define ENET_RCR_FCE_SHIFT                       (5U)
36258 /*! FCE - Flow Control Enable
36259  *  0b0..Disable flow control
36260  *  0b1..Enable flow control
36261  */
36262 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
36263 
36264 #define ENET_RCR_RGMII_EN_MASK                   (0x40U)
36265 #define ENET_RCR_RGMII_EN_SHIFT                  (6U)
36266 /*! RGMII_EN - RGMII Mode Enable
36267  *  0b0..MAC configured for non-RGMII operation
36268  *  0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
36269  *       ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
36270  */
36271 #define ENET_RCR_RGMII_EN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
36272 
36273 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
36274 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
36275 /*! RMII_MODE - RMII Mode Enable
36276  *  0b0..MAC configured for MII mode.
36277  *  0b1..MAC configured for RMII operation.
36278  */
36279 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
36280 
36281 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
36282 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
36283 /*! RMII_10T
36284  *  0b0..100-Mbit/s or 1-Gbit/s operation.
36285  *  0b1..10-Mbit/s operation.
36286  */
36287 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
36288 
36289 #define ENET_RCR_PADEN_MASK                      (0x1000U)
36290 #define ENET_RCR_PADEN_SHIFT                     (12U)
36291 /*! PADEN - Enable Frame Padding Remove On Receive
36292  *  0b0..No padding is removed on receive by the MAC.
36293  *  0b1..Padding is removed from received frames.
36294  */
36295 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
36296 
36297 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
36298 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
36299 /*! PAUFWD - Terminate/Forward Pause Frames
36300  *  0b0..Pause frames are terminated and discarded in the MAC.
36301  *  0b1..Pause frames are forwarded to the user application.
36302  */
36303 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
36304 
36305 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
36306 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
36307 /*! CRCFWD - Terminate/Forward Received CRC
36308  *  0b0..The CRC field of received frames is transmitted to the user application.
36309  *  0b1..The CRC field is stripped from the frame.
36310  */
36311 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
36312 
36313 #define ENET_RCR_CFEN_MASK                       (0x8000U)
36314 #define ENET_RCR_CFEN_SHIFT                      (15U)
36315 /*! CFEN - MAC Control Frame Enable
36316  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
36317  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
36318  */
36319 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
36320 
36321 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
36322 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
36323 /*! MAX_FL - Maximum Frame Length
36324  */
36325 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
36326 
36327 #define ENET_RCR_NLC_MASK                        (0x40000000U)
36328 #define ENET_RCR_NLC_SHIFT                       (30U)
36329 /*! NLC - Payload Length Check Disable
36330  *  0b0..The payload length check is disabled.
36331  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
36332  */
36333 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
36334 
36335 #define ENET_RCR_GRS_MASK                        (0x80000000U)
36336 #define ENET_RCR_GRS_SHIFT                       (31U)
36337 /*! GRS - Graceful Receive Stopped
36338  *  0b0..Receive not stopped
36339  *  0b1..Receive stopped
36340  */
36341 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
36342 /*! @} */
36343 
36344 /*! @name TCR - Transmit Control Register */
36345 /*! @{ */
36346 
36347 #define ENET_TCR_GTS_MASK                        (0x1U)
36348 #define ENET_TCR_GTS_SHIFT                       (0U)
36349 /*! GTS - Graceful Transmit Stop
36350  *  0b0..Disable graceful transmit stop
36351  *  0b1..Enable graceful transmit stop
36352  */
36353 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
36354 
36355 #define ENET_TCR_FDEN_MASK                       (0x4U)
36356 #define ENET_TCR_FDEN_SHIFT                      (2U)
36357 /*! FDEN - Full-Duplex Enable
36358  *  0b0..Disable full-duplex
36359  *  0b1..Enable full-duplex
36360  */
36361 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
36362 
36363 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
36364 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
36365 /*! TFC_PAUSE - Transmit Frame Control Pause
36366  *  0b0..No PAUSE frame transmitted.
36367  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
36368  */
36369 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
36370 
36371 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
36372 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
36373 /*! RFC_PAUSE - Receive Frame Control Pause
36374  */
36375 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
36376 
36377 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
36378 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
36379 /*! ADDSEL - Source MAC Address Select On Transmit
36380  *  0b000..Node MAC address programmed on PADDR1/2 registers.
36381  *  0b100..Reserved.
36382  *  0b101..Reserved.
36383  *  0b110..Reserved.
36384  */
36385 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
36386 
36387 #define ENET_TCR_ADDINS_MASK                     (0x100U)
36388 #define ENET_TCR_ADDINS_SHIFT                    (8U)
36389 /*! ADDINS - Set MAC Address On Transmit
36390  *  0b0..The source MAC address is not modified by the MAC.
36391  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
36392  */
36393 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
36394 
36395 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
36396 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
36397 /*! CRCFWD - Forward Frame From Application With CRC
36398  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
36399  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
36400  */
36401 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
36402 /*! @} */
36403 
36404 /*! @name PALR - Physical Address Lower Register */
36405 /*! @{ */
36406 
36407 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
36408 #define ENET_PALR_PADDR1_SHIFT                   (0U)
36409 /*! PADDR1 - Pause Address
36410  */
36411 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
36412 /*! @} */
36413 
36414 /*! @name PAUR - Physical Address Upper Register */
36415 /*! @{ */
36416 
36417 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
36418 #define ENET_PAUR_TYPE_SHIFT                     (0U)
36419 /*! TYPE - Type Field In PAUSE Frames
36420  */
36421 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
36422 
36423 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
36424 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
36425 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
36426 /*! @} */
36427 
36428 /*! @name OPD - Opcode/Pause Duration Register */
36429 /*! @{ */
36430 
36431 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
36432 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
36433 /*! PAUSE_DUR - Pause Duration
36434  */
36435 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
36436 
36437 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
36438 #define ENET_OPD_OPCODE_SHIFT                    (16U)
36439 /*! OPCODE - Opcode Field In PAUSE Frames
36440  */
36441 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
36442 /*! @} */
36443 
36444 /*! @name TXIC - Transmit Interrupt Coalescing Register */
36445 /*! @{ */
36446 
36447 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
36448 #define ENET_TXIC_ICTT_SHIFT                     (0U)
36449 /*! ICTT - Interrupt coalescing timer threshold
36450  */
36451 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
36452 
36453 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
36454 #define ENET_TXIC_ICFT_SHIFT                     (20U)
36455 /*! ICFT - Interrupt coalescing frame count threshold
36456  */
36457 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
36458 
36459 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
36460 #define ENET_TXIC_ICCS_SHIFT                     (30U)
36461 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
36462  *  0b0..Use MII/GMII TX clocks.
36463  *  0b1..Use ENET system clock.
36464  */
36465 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
36466 
36467 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
36468 #define ENET_TXIC_ICEN_SHIFT                     (31U)
36469 /*! ICEN - Interrupt Coalescing Enable
36470  *  0b0..Disable Interrupt coalescing.
36471  *  0b1..Enable Interrupt coalescing.
36472  */
36473 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
36474 /*! @} */
36475 
36476 /* The count of ENET_TXIC */
36477 #define ENET_TXIC_COUNT                          (3U)
36478 
36479 /*! @name RXIC - Receive Interrupt Coalescing Register */
36480 /*! @{ */
36481 
36482 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
36483 #define ENET_RXIC_ICTT_SHIFT                     (0U)
36484 /*! ICTT - Interrupt coalescing timer threshold
36485  */
36486 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
36487 
36488 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
36489 #define ENET_RXIC_ICFT_SHIFT                     (20U)
36490 /*! ICFT - Interrupt coalescing frame count threshold
36491  */
36492 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
36493 
36494 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
36495 #define ENET_RXIC_ICCS_SHIFT                     (30U)
36496 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
36497  *  0b0..Use MII/GMII TX clocks.
36498  *  0b1..Use ENET system clock.
36499  */
36500 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
36501 
36502 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
36503 #define ENET_RXIC_ICEN_SHIFT                     (31U)
36504 /*! ICEN - Interrupt Coalescing Enable
36505  *  0b0..Disable Interrupt coalescing.
36506  *  0b1..Enable Interrupt coalescing.
36507  */
36508 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
36509 /*! @} */
36510 
36511 /* The count of ENET_RXIC */
36512 #define ENET_RXIC_COUNT                          (3U)
36513 
36514 /*! @name IAUR - Descriptor Individual Upper Address Register */
36515 /*! @{ */
36516 
36517 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
36518 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
36519 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
36520 /*! @} */
36521 
36522 /*! @name IALR - Descriptor Individual Lower Address Register */
36523 /*! @{ */
36524 
36525 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
36526 #define ENET_IALR_IADDR2_SHIFT                   (0U)
36527 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
36528 /*! @} */
36529 
36530 /*! @name GAUR - Descriptor Group Upper Address Register */
36531 /*! @{ */
36532 
36533 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
36534 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
36535 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
36536 /*! @} */
36537 
36538 /*! @name GALR - Descriptor Group Lower Address Register */
36539 /*! @{ */
36540 
36541 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
36542 #define ENET_GALR_GADDR2_SHIFT                   (0U)
36543 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
36544 /*! @} */
36545 
36546 /*! @name TFWR - Transmit FIFO Watermark Register */
36547 /*! @{ */
36548 
36549 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
36550 #define ENET_TFWR_TFWR_SHIFT                     (0U)
36551 /*! TFWR - Transmit FIFO Write
36552  *  0b000000..64 bytes written.
36553  *  0b000001..64 bytes written.
36554  *  0b000010..128 bytes written.
36555  *  0b000011..192 bytes written.
36556  *  0b011111..1984 bytes written.
36557  */
36558 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
36559 
36560 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
36561 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
36562 /*! STRFWD - Store And Forward Enable
36563  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
36564  *  0b1..Enabled.
36565  */
36566 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
36567 /*! @} */
36568 
36569 /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
36570 /*! @{ */
36571 
36572 #define ENET_RDSR1_R_DES_START_MASK              (0xFFFFFFF8U)
36573 #define ENET_RDSR1_R_DES_START_SHIFT             (3U)
36574 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
36575 /*! @} */
36576 
36577 /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
36578 /*! @{ */
36579 
36580 #define ENET_TDSR1_X_DES_START_MASK              (0xFFFFFFF8U)
36581 #define ENET_TDSR1_X_DES_START_SHIFT             (3U)
36582 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
36583 /*! @} */
36584 
36585 /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
36586 /*! @{ */
36587 
36588 #define ENET_MRBR1_R_BUF_SIZE_MASK               (0x7F0U)
36589 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              (4U)
36590 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
36591 /*! @} */
36592 
36593 /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
36594 /*! @{ */
36595 
36596 #define ENET_RDSR2_R_DES_START_MASK              (0xFFFFFFF8U)
36597 #define ENET_RDSR2_R_DES_START_SHIFT             (3U)
36598 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
36599 /*! @} */
36600 
36601 /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
36602 /*! @{ */
36603 
36604 #define ENET_TDSR2_X_DES_START_MASK              (0xFFFFFFF8U)
36605 #define ENET_TDSR2_X_DES_START_SHIFT             (3U)
36606 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
36607 /*! @} */
36608 
36609 /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
36610 /*! @{ */
36611 
36612 #define ENET_MRBR2_R_BUF_SIZE_MASK               (0x7F0U)
36613 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              (4U)
36614 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
36615 /*! @} */
36616 
36617 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
36618 /*! @{ */
36619 
36620 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
36621 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
36622 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
36623 /*! @} */
36624 
36625 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
36626 /*! @{ */
36627 
36628 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
36629 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
36630 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
36631 /*! @} */
36632 
36633 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
36634 /*! @{ */
36635 
36636 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36637 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
36638 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
36639 /*! @} */
36640 
36641 /*! @name RSFL - Receive FIFO Section Full Threshold */
36642 /*! @{ */
36643 
36644 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36645 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
36646 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
36647  */
36648 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36649 /*! @} */
36650 
36651 /*! @name RSEM - Receive FIFO Section Empty Threshold */
36652 /*! @{ */
36653 
36654 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36655 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
36656 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
36657  */
36658 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36659 
36660 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
36661 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
36662 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
36663  */
36664 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
36665 /*! @} */
36666 
36667 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
36668 /*! @{ */
36669 
36670 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36671 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
36672 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
36673  */
36674 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36675 /*! @} */
36676 
36677 /*! @name RAFL - Receive FIFO Almost Full Threshold */
36678 /*! @{ */
36679 
36680 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36681 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
36682 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
36683  */
36684 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36685 /*! @} */
36686 
36687 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
36688 /*! @{ */
36689 
36690 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36691 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
36692 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
36693  */
36694 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36695 /*! @} */
36696 
36697 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
36698 /*! @{ */
36699 
36700 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36701 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
36702 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
36703  */
36704 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36705 /*! @} */
36706 
36707 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
36708 /*! @{ */
36709 
36710 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36711 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
36712 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
36713  */
36714 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
36715 /*! @} */
36716 
36717 /*! @name TIPG - Transmit Inter-Packet Gap */
36718 /*! @{ */
36719 
36720 #define ENET_TIPG_IPG_MASK                       (0x1FU)
36721 #define ENET_TIPG_IPG_SHIFT                      (0U)
36722 /*! IPG - Transmit Inter-Packet Gap
36723  */
36724 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
36725 /*! @} */
36726 
36727 /*! @name FTRL - Frame Truncation Length */
36728 /*! @{ */
36729 
36730 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
36731 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
36732 /*! TRUNC_FL - Frame Truncation Length
36733  */
36734 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
36735 /*! @} */
36736 
36737 /*! @name TACC - Transmit Accelerator Function Configuration */
36738 /*! @{ */
36739 
36740 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
36741 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
36742 /*! SHIFT16 - TX FIFO Shift-16
36743  *  0b0..Disabled.
36744  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
36745  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
36746  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
36747  *       extended to a 16-byte header.
36748  */
36749 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
36750 
36751 #define ENET_TACC_IPCHK_MASK                     (0x8U)
36752 #define ENET_TACC_IPCHK_SHIFT                    (3U)
36753 /*! IPCHK
36754  *  0b0..Checksum is not inserted.
36755  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
36756  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
36757  */
36758 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
36759 
36760 #define ENET_TACC_PROCHK_MASK                    (0x10U)
36761 #define ENET_TACC_PROCHK_SHIFT                   (4U)
36762 /*! PROCHK
36763  *  0b0..Checksum not inserted.
36764  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
36765  *       frame. The checksum field must be cleared. The other frames are not modified.
36766  */
36767 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
36768 /*! @} */
36769 
36770 /*! @name RACC - Receive Accelerator Function Configuration */
36771 /*! @{ */
36772 
36773 #define ENET_RACC_PADREM_MASK                    (0x1U)
36774 #define ENET_RACC_PADREM_SHIFT                   (0U)
36775 /*! PADREM - Enable Padding Removal For Short IP Frames
36776  *  0b0..Padding not removed.
36777  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
36778  */
36779 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
36780 
36781 #define ENET_RACC_IPDIS_MASK                     (0x2U)
36782 #define ENET_RACC_IPDIS_SHIFT                    (1U)
36783 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
36784  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
36785  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
36786  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
36787  *       store and forward mode (RSFL cleared).
36788  */
36789 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
36790 
36791 #define ENET_RACC_PRODIS_MASK                    (0x4U)
36792 #define ENET_RACC_PRODIS_SHIFT                   (2U)
36793 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
36794  *  0b0..Frames with wrong checksum are not discarded.
36795  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
36796  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
36797  *       cleared).
36798  */
36799 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
36800 
36801 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
36802 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
36803 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
36804  *  0b0..Frames with errors are not discarded.
36805  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
36806  */
36807 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
36808 
36809 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
36810 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
36811 /*! SHIFT16 - RX FIFO Shift-16
36812  *  0b0..Disabled.
36813  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
36814  */
36815 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
36816 /*! @} */
36817 
36818 /*! @name RCMR - Receive Classification Match Register for Class n */
36819 /*! @{ */
36820 
36821 #define ENET_RCMR_CMP0_MASK                      (0x7U)
36822 #define ENET_RCMR_CMP0_SHIFT                     (0U)
36823 /*! CMP0 - Compare 0
36824  */
36825 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
36826 
36827 #define ENET_RCMR_CMP1_MASK                      (0x70U)
36828 #define ENET_RCMR_CMP1_SHIFT                     (4U)
36829 /*! CMP1 - Compare 1
36830  */
36831 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
36832 
36833 #define ENET_RCMR_CMP2_MASK                      (0x700U)
36834 #define ENET_RCMR_CMP2_SHIFT                     (8U)
36835 /*! CMP2 - Compare 2
36836  */
36837 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
36838 
36839 #define ENET_RCMR_CMP3_MASK                      (0x7000U)
36840 #define ENET_RCMR_CMP3_SHIFT                     (12U)
36841 /*! CMP3 - Compare 3
36842  */
36843 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
36844 
36845 #define ENET_RCMR_MATCHEN_MASK                   (0x10000U)
36846 #define ENET_RCMR_MATCHEN_SHIFT                  (16U)
36847 /*! MATCHEN - Match Enable
36848  *  0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
36849  *  0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
36850  */
36851 #define ENET_RCMR_MATCHEN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
36852 /*! @} */
36853 
36854 /* The count of ENET_RCMR */
36855 #define ENET_RCMR_COUNT                          (2U)
36856 
36857 /*! @name DMACFG - DMA Class Based Configuration */
36858 /*! @{ */
36859 
36860 #define ENET_DMACFG_IDLE_SLOPE_MASK              (0xFFFFU)
36861 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             (0U)
36862 /*! IDLE_SLOPE - Idle slope
36863  */
36864 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
36865 
36866 #define ENET_DMACFG_DMA_CLASS_EN_MASK            (0x10000U)
36867 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           (16U)
36868 /*! DMA_CLASS_EN - DMA class enable
36869  *  0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
36870  *       requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
36871  *       queues are disabled then their frames will be placed in queue 0.
36872  *  0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
36873  */
36874 #define ENET_DMACFG_DMA_CLASS_EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
36875 
36876 #define ENET_DMACFG_CALC_NOIPG_MASK              (0x20000U)
36877 #define ENET_DMACFG_CALC_NOIPG_SHIFT             (17U)
36878 /*! CALC_NOIPG - Calculate no IPG
36879  *  0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
36880  *       for a frame when doing bandwidth calculations. This is the default.
36881  *  0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
36882  *       when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
36883  *       frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
36884  *       will become more bandwidth than large frames due to the relation of data to IPG overhead).
36885  */
36886 #define ENET_DMACFG_CALC_NOIPG(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
36887 /*! @} */
36888 
36889 /* The count of ENET_DMACFG */
36890 #define ENET_DMACFG_COUNT                        (2U)
36891 
36892 /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
36893 /*! @{ */
36894 
36895 #define ENET_RDAR1_RDAR_MASK                     (0x1000000U)
36896 #define ENET_RDAR1_RDAR_SHIFT                    (24U)
36897 /*! RDAR - Receive Descriptor Active
36898  */
36899 #define ENET_RDAR1_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
36900 /*! @} */
36901 
36902 /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
36903 /*! @{ */
36904 
36905 #define ENET_TDAR1_TDAR_MASK                     (0x1000000U)
36906 #define ENET_TDAR1_TDAR_SHIFT                    (24U)
36907 /*! TDAR - Transmit Descriptor Active
36908  */
36909 #define ENET_TDAR1_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
36910 /*! @} */
36911 
36912 /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
36913 /*! @{ */
36914 
36915 #define ENET_RDAR2_RDAR_MASK                     (0x1000000U)
36916 #define ENET_RDAR2_RDAR_SHIFT                    (24U)
36917 /*! RDAR - Receive Descriptor Active
36918  */
36919 #define ENET_RDAR2_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
36920 /*! @} */
36921 
36922 /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
36923 /*! @{ */
36924 
36925 #define ENET_TDAR2_TDAR_MASK                     (0x1000000U)
36926 #define ENET_TDAR2_TDAR_SHIFT                    (24U)
36927 /*! TDAR - Transmit Descriptor Active
36928  */
36929 #define ENET_TDAR2_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
36930 /*! @} */
36931 
36932 /*! @name QOS - QOS Scheme */
36933 /*! @{ */
36934 
36935 #define ENET_QOS_TX_SCHEME_MASK                  (0x7U)
36936 #define ENET_QOS_TX_SCHEME_SHIFT                 (0U)
36937 /*! TX_SCHEME - TX scheme configuration
36938  *  0b000..Credit-based scheme
36939  *  0b001..Round-robin scheme
36940  *  0b010-0b111..Reserved
36941  */
36942 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
36943 
36944 #define ENET_QOS_RX_FLUSH0_MASK                  (0x8U)
36945 #define ENET_QOS_RX_FLUSH0_SHIFT                 (3U)
36946 /*! RX_FLUSH0 - RX Flush Ring 0
36947  *  0b0..Disable
36948  *  0b1..Enable
36949  */
36950 #define ENET_QOS_RX_FLUSH0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
36951 
36952 #define ENET_QOS_RX_FLUSH1_MASK                  (0x10U)
36953 #define ENET_QOS_RX_FLUSH1_SHIFT                 (4U)
36954 /*! RX_FLUSH1 - RX Flush Ring 1
36955  *  0b0..Disable
36956  *  0b1..Enable
36957  */
36958 #define ENET_QOS_RX_FLUSH1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
36959 
36960 #define ENET_QOS_RX_FLUSH2_MASK                  (0x20U)
36961 #define ENET_QOS_RX_FLUSH2_SHIFT                 (5U)
36962 /*! RX_FLUSH2 - RX Flush Ring 2
36963  *  0b0..Disable
36964  *  0b1..Enable
36965  */
36966 #define ENET_QOS_RX_FLUSH2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
36967 /*! @} */
36968 
36969 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
36970 /*! @{ */
36971 
36972 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
36973 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
36974 /*! TXPKTS - Packet count
36975  */
36976 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
36977 /*! @} */
36978 
36979 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
36980 /*! @{ */
36981 
36982 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
36983 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
36984 /*! TXPKTS - Broadcast packets
36985  */
36986 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
36987 /*! @} */
36988 
36989 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
36990 /*! @{ */
36991 
36992 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
36993 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
36994 /*! TXPKTS - Multicast packets
36995  */
36996 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
36997 /*! @} */
36998 
36999 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
37000 /*! @{ */
37001 
37002 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
37003 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
37004 /*! TXPKTS - Packets with CRC/align error
37005  */
37006 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
37007 /*! @} */
37008 
37009 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
37010 /*! @{ */
37011 
37012 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
37013 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
37014 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
37015  */
37016 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
37017 /*! @} */
37018 
37019 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
37020 /*! @{ */
37021 
37022 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
37023 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
37024 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
37025  */
37026 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
37027 /*! @} */
37028 
37029 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
37030 /*! @{ */
37031 
37032 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
37033 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
37034 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC
37035  */
37036 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
37037 /*! @} */
37038 
37039 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
37040 /*! @{ */
37041 
37042 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
37043 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
37044 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
37045  */
37046 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
37047 /*! @} */
37048 
37049 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
37050 /*! @{ */
37051 
37052 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
37053 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
37054 /*! TXPKTS - Number of transmit collisions
37055  */
37056 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
37057 /*! @} */
37058 
37059 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
37060 /*! @{ */
37061 
37062 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
37063 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
37064 /*! TXPKTS - Number of 64-byte transmit packets
37065  */
37066 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
37067 /*! @} */
37068 
37069 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
37070 /*! @{ */
37071 
37072 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
37073 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
37074 /*! TXPKTS - Number of 65- to 127-byte transmit packets
37075  */
37076 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
37077 /*! @} */
37078 
37079 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
37080 /*! @{ */
37081 
37082 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
37083 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
37084 /*! TXPKTS - Number of 128- to 255-byte transmit packets
37085  */
37086 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
37087 /*! @} */
37088 
37089 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
37090 /*! @{ */
37091 
37092 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
37093 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
37094 /*! TXPKTS - Number of 256- to 511-byte transmit packets
37095  */
37096 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
37097 /*! @} */
37098 
37099 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
37100 /*! @{ */
37101 
37102 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
37103 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
37104 /*! TXPKTS - Number of 512- to 1023-byte transmit packets
37105  */
37106 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
37107 /*! @} */
37108 
37109 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
37110 /*! @{ */
37111 
37112 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
37113 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
37114 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets
37115  */
37116 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
37117 /*! @} */
37118 
37119 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
37120 /*! @{ */
37121 
37122 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
37123 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
37124 /*! TXPKTS - Number of transmit packets greater than 2048 bytes
37125  */
37126 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
37127 /*! @} */
37128 
37129 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
37130 /*! @{ */
37131 
37132 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
37133 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
37134 /*! TXOCTS - Number of transmit octets
37135  */
37136 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
37137 /*! @} */
37138 
37139 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
37140 /*! @{ */
37141 
37142 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
37143 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
37144 /*! COUNT - Number of frames transmitted OK
37145  */
37146 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
37147 /*! @} */
37148 
37149 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
37150 /*! @{ */
37151 
37152 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
37153 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
37154 /*! COUNT - Number of frames transmitted with one collision
37155  */
37156 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
37157 /*! @} */
37158 
37159 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
37160 /*! @{ */
37161 
37162 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
37163 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
37164 /*! COUNT - Number of frames transmitted with multiple collisions
37165  */
37166 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
37167 /*! @} */
37168 
37169 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
37170 /*! @{ */
37171 
37172 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
37173 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
37174 /*! COUNT - Number of frames transmitted with deferral delay
37175  */
37176 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
37177 /*! @} */
37178 
37179 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
37180 /*! @{ */
37181 
37182 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
37183 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
37184 /*! COUNT - Number of frames transmitted with late collision
37185  */
37186 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
37187 /*! @} */
37188 
37189 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
37190 /*! @{ */
37191 
37192 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
37193 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
37194 /*! COUNT - Number of frames transmitted with excessive collisions
37195  */
37196 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
37197 /*! @} */
37198 
37199 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
37200 /*! @{ */
37201 
37202 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
37203 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
37204 /*! COUNT - Number of frames transmitted with transmit FIFO underrun
37205  */
37206 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
37207 /*! @} */
37208 
37209 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
37210 /*! @{ */
37211 
37212 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
37213 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
37214 /*! COUNT - Number of frames transmitted with carrier sense error
37215  */
37216 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
37217 /*! @} */
37218 
37219 /*! @name IEEE_T_SQE - Reserved Statistic Register */
37220 /*! @{ */
37221 
37222 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
37223 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
37224 /*! COUNT - This read-only field is reserved and always has the value 0
37225  */
37226 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
37227 /*! @} */
37228 
37229 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
37230 /*! @{ */
37231 
37232 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
37233 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
37234 /*! COUNT - Number of flow-control pause frames transmitted
37235  */
37236 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
37237 /*! @} */
37238 
37239 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
37240 /*! @{ */
37241 
37242 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
37243 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
37244 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
37245  */
37246 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
37247 /*! @} */
37248 
37249 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
37250 /*! @{ */
37251 
37252 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
37253 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
37254 /*! COUNT - Number of packets received
37255  */
37256 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
37257 /*! @} */
37258 
37259 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
37260 /*! @{ */
37261 
37262 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
37263 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
37264 /*! COUNT - Number of receive broadcast packets
37265  */
37266 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
37267 /*! @} */
37268 
37269 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
37270 /*! @{ */
37271 
37272 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
37273 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
37274 /*! COUNT - Number of receive multicast packets
37275  */
37276 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
37277 /*! @} */
37278 
37279 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
37280 /*! @{ */
37281 
37282 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
37283 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
37284 /*! COUNT - Number of receive packets with CRC or align error
37285  */
37286 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
37287 /*! @} */
37288 
37289 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
37290 /*! @{ */
37291 
37292 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
37293 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
37294 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC
37295  */
37296 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
37297 /*! @} */
37298 
37299 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
37300 /*! @{ */
37301 
37302 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
37303 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
37304 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC
37305  */
37306 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
37307 /*! @} */
37308 
37309 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
37310 /*! @{ */
37311 
37312 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
37313 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
37314 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
37315  */
37316 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
37317 /*! @} */
37318 
37319 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
37320 /*! @{ */
37321 
37322 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
37323 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
37324 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
37325  */
37326 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
37327 /*! @} */
37328 
37329 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
37330 /*! @{ */
37331 
37332 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
37333 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
37334 /*! COUNT - Number of 64-byte receive packets
37335  */
37336 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
37337 /*! @} */
37338 
37339 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
37340 /*! @{ */
37341 
37342 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
37343 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
37344 /*! COUNT - Number of 65- to 127-byte recieve packets
37345  */
37346 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
37347 /*! @} */
37348 
37349 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
37350 /*! @{ */
37351 
37352 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
37353 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
37354 /*! COUNT - Number of 128- to 255-byte recieve packets
37355  */
37356 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
37357 /*! @} */
37358 
37359 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
37360 /*! @{ */
37361 
37362 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
37363 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
37364 /*! COUNT - Number of 256- to 511-byte recieve packets
37365  */
37366 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
37367 /*! @} */
37368 
37369 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
37370 /*! @{ */
37371 
37372 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
37373 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
37374 /*! COUNT - Number of 512- to 1023-byte recieve packets
37375  */
37376 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
37377 /*! @} */
37378 
37379 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
37380 /*! @{ */
37381 
37382 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
37383 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
37384 /*! COUNT - Number of 1024- to 2047-byte recieve packets
37385  */
37386 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
37387 /*! @} */
37388 
37389 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
37390 /*! @{ */
37391 
37392 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
37393 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
37394 /*! COUNT - Number of greater-than-2048-byte recieve packets
37395  */
37396 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
37397 /*! @} */
37398 
37399 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
37400 /*! @{ */
37401 
37402 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
37403 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
37404 /*! COUNT - Number of receive octets
37405  */
37406 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
37407 /*! @} */
37408 
37409 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
37410 /*! @{ */
37411 
37412 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
37413 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
37414 /*! COUNT - Frame count
37415  */
37416 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
37417 /*! @} */
37418 
37419 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
37420 /*! @{ */
37421 
37422 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
37423 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
37424 /*! COUNT - Number of frames received OK
37425  */
37426 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
37427 /*! @} */
37428 
37429 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
37430 /*! @{ */
37431 
37432 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
37433 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
37434 /*! COUNT - Number of frames received with CRC error
37435  */
37436 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
37437 /*! @} */
37438 
37439 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
37440 /*! @{ */
37441 
37442 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
37443 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
37444 /*! COUNT - Number of frames received with alignment error
37445  */
37446 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
37447 /*! @} */
37448 
37449 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
37450 /*! @{ */
37451 
37452 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
37453 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
37454 /*! COUNT - Receive FIFO overflow count
37455  */
37456 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
37457 /*! @} */
37458 
37459 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
37460 /*! @{ */
37461 
37462 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
37463 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
37464 /*! COUNT - Number of flow-control pause frames received
37465  */
37466 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
37467 /*! @} */
37468 
37469 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
37470 /*! @{ */
37471 
37472 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
37473 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
37474 /*! COUNT - Number of octets for frames received without error
37475  */
37476 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
37477 /*! @} */
37478 
37479 /*! @name ATCR - Adjustable Timer Control Register */
37480 /*! @{ */
37481 
37482 #define ENET_ATCR_EN_MASK                        (0x1U)
37483 #define ENET_ATCR_EN_SHIFT                       (0U)
37484 /*! EN - Enable Timer
37485  *  0b0..The timer stops at the current value.
37486  *  0b1..The timer starts incrementing.
37487  */
37488 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
37489 
37490 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
37491 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
37492 /*! OFFEN - Enable One-Shot Offset Event
37493  *  0b0..Disable.
37494  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
37495  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
37496  *       offset value must be set before setting this field.
37497  */
37498 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
37499 
37500 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
37501 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
37502 /*! OFFRST - Reset Timer On Offset Event
37503  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
37504  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
37505  */
37506 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
37507 
37508 #define ENET_ATCR_PEREN_MASK                     (0x10U)
37509 #define ENET_ATCR_PEREN_SHIFT                    (4U)
37510 /*! PEREN - Enable Periodical Event
37511  *  0b0..Disable.
37512  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
37513  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
37514  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
37515  */
37516 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
37517 
37518 #define ENET_ATCR_PINPER_MASK                    (0x80U)
37519 #define ENET_ATCR_PINPER_SHIFT                   (7U)
37520 /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
37521  *  0b0..Disable.
37522  *  0b1..Enable.
37523  */
37524 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
37525 
37526 #define ENET_ATCR_RESTART_MASK                   (0x200U)
37527 #define ENET_ATCR_RESTART_SHIFT                  (9U)
37528 /*! RESTART - Reset Timer
37529  */
37530 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
37531 
37532 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
37533 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
37534 /*! CAPTURE - Capture Timer Value
37535  *  0b0..No effect.
37536  *  0b1..The current time is captured and can be read from the ATVR register.
37537  */
37538 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
37539 
37540 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
37541 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
37542 /*! SLAVE - Enable Timer Slave Mode
37543  *  0b0..The timer is active and all configuration fields in this register are relevant.
37544  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
37545  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
37546  */
37547 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
37548 /*! @} */
37549 
37550 /*! @name ATVR - Timer Value Register */
37551 /*! @{ */
37552 
37553 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
37554 #define ENET_ATVR_ATIME_SHIFT                    (0U)
37555 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
37556 /*! @} */
37557 
37558 /*! @name ATOFF - Timer Offset Register */
37559 /*! @{ */
37560 
37561 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
37562 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
37563 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
37564 /*! @} */
37565 
37566 /*! @name ATPER - Timer Period Register */
37567 /*! @{ */
37568 
37569 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
37570 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
37571 /*! PERIOD - Value for generating periodic events
37572  */
37573 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
37574 /*! @} */
37575 
37576 /*! @name ATCOR - Timer Correction Register */
37577 /*! @{ */
37578 
37579 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
37580 #define ENET_ATCOR_COR_SHIFT                     (0U)
37581 /*! COR - Correction Counter Wrap-Around Value
37582  */
37583 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
37584 /*! @} */
37585 
37586 /*! @name ATINC - Time-Stamping Clock Period Register */
37587 /*! @{ */
37588 
37589 #define ENET_ATINC_INC_MASK                      (0x7FU)
37590 #define ENET_ATINC_INC_SHIFT                     (0U)
37591 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
37592  */
37593 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
37594 
37595 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
37596 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
37597 /*! INC_CORR - Correction Increment Value
37598  */
37599 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
37600 /*! @} */
37601 
37602 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
37603 /*! @{ */
37604 
37605 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
37606 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
37607 /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
37608  *    ff_tx_ts_frm signal asserted from the user application
37609  */
37610 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
37611 /*! @} */
37612 
37613 /*! @name TGSR - Timer Global Status Register */
37614 /*! @{ */
37615 
37616 #define ENET_TGSR_TF0_MASK                       (0x1U)
37617 #define ENET_TGSR_TF0_SHIFT                      (0U)
37618 /*! TF0 - Copy Of Timer Flag For Channel 0
37619  *  0b0..Timer Flag for Channel 0 is clear
37620  *  0b1..Timer Flag for Channel 0 is set
37621  */
37622 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
37623 
37624 #define ENET_TGSR_TF1_MASK                       (0x2U)
37625 #define ENET_TGSR_TF1_SHIFT                      (1U)
37626 /*! TF1 - Copy Of Timer Flag For Channel 1
37627  *  0b0..Timer Flag for Channel 1 is clear
37628  *  0b1..Timer Flag for Channel 1 is set
37629  */
37630 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
37631 
37632 #define ENET_TGSR_TF2_MASK                       (0x4U)
37633 #define ENET_TGSR_TF2_SHIFT                      (2U)
37634 /*! TF2 - Copy Of Timer Flag For Channel 2
37635  *  0b0..Timer Flag for Channel 2 is clear
37636  *  0b1..Timer Flag for Channel 2 is set
37637  */
37638 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
37639 
37640 #define ENET_TGSR_TF3_MASK                       (0x8U)
37641 #define ENET_TGSR_TF3_SHIFT                      (3U)
37642 /*! TF3 - Copy Of Timer Flag For Channel 3
37643  *  0b0..Timer Flag for Channel 3 is clear
37644  *  0b1..Timer Flag for Channel 3 is set
37645  */
37646 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
37647 /*! @} */
37648 
37649 /*! @name TCSR - Timer Control Status Register */
37650 /*! @{ */
37651 
37652 #define ENET_TCSR_TDRE_MASK                      (0x1U)
37653 #define ENET_TCSR_TDRE_SHIFT                     (0U)
37654 /*! TDRE - Timer DMA Request Enable
37655  *  0b0..DMA request is disabled
37656  *  0b1..DMA request is enabled
37657  */
37658 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
37659 
37660 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
37661 #define ENET_TCSR_TMODE_SHIFT                    (2U)
37662 /*! TMODE - Timer Mode
37663  *  0b0000..Timer Channel is disabled.
37664  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
37665  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
37666  *  0b0011..Timer Channel is configured for Input Capture on both edges.
37667  *  0b0100..Timer Channel is configured for Output Compare - software only.
37668  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
37669  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
37670  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
37671  *  0b1000..Reserved
37672  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
37673  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
37674  *  0b110x..Reserved
37675  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
37676  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
37677  */
37678 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
37679 
37680 #define ENET_TCSR_TIE_MASK                       (0x40U)
37681 #define ENET_TCSR_TIE_SHIFT                      (6U)
37682 /*! TIE - Timer Interrupt Enable
37683  *  0b0..Interrupt is disabled
37684  *  0b1..Interrupt is enabled
37685  */
37686 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
37687 
37688 #define ENET_TCSR_TF_MASK                        (0x80U)
37689 #define ENET_TCSR_TF_SHIFT                       (7U)
37690 /*! TF - Timer Flag
37691  *  0b0..Input Capture or Output Compare has not occurred.
37692  *  0b1..Input Capture or Output Compare has occurred.
37693  */
37694 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
37695 
37696 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
37697 #define ENET_TCSR_TPWC_SHIFT                     (11U)
37698 /*! TPWC - Timer PulseWidth Control
37699  *  0b00000..Pulse width is one 1588-clock cycle.
37700  *  0b00001..Pulse width is two 1588-clock cycles.
37701  *  0b00010..Pulse width is three 1588-clock cycles.
37702  *  0b00011..Pulse width is four 1588-clock cycles.
37703  *  0b11111..Pulse width is 32 1588-clock cycles.
37704  */
37705 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
37706 /*! @} */
37707 
37708 /* The count of ENET_TCSR */
37709 #define ENET_TCSR_COUNT                          (4U)
37710 
37711 /*! @name TCCR - Timer Compare Capture Register */
37712 /*! @{ */
37713 
37714 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
37715 #define ENET_TCCR_TCC_SHIFT                      (0U)
37716 /*! TCC - Timer Capture Compare
37717  */
37718 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
37719 /*! @} */
37720 
37721 /* The count of ENET_TCCR */
37722 #define ENET_TCCR_COUNT                          (4U)
37723 
37724 
37725 /*!
37726  * @}
37727  */ /* end of group ENET_Register_Masks */
37728 
37729 
37730 /* ENET - Peripheral instance base addresses */
37731 /** Peripheral ENET base address */
37732 #define ENET_BASE                                (0x40424000u)
37733 /** Peripheral ENET base pointer */
37734 #define ENET                                     ((ENET_Type *)ENET_BASE)
37735 /** Peripheral ENET_1G base address */
37736 #define ENET_1G_BASE                             (0x40420000u)
37737 /** Peripheral ENET_1G base pointer */
37738 #define ENET_1G                                  ((ENET_Type *)ENET_1G_BASE)
37739 /** Array initializer of ENET peripheral base addresses */
37740 #define ENET_BASE_ADDRS                          { ENET_BASE, ENET_1G_BASE }
37741 /** Array initializer of ENET peripheral base pointers */
37742 #define ENET_BASE_PTRS                           { ENET, ENET_1G }
37743 /** Interrupt vectors for the ENET peripheral type */
37744 #define ENET_Transmit_IRQS                       { ENET_IRQn, ENET_1G_IRQn }
37745 #define ENET_Receive_IRQS                        { ENET_IRQn, ENET_1G_IRQn }
37746 #define ENET_Error_IRQS                          { ENET_IRQn, ENET_1G_IRQn }
37747 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
37748 #define ENET_Ts_IRQS                             { ENET_IRQn, ENET_1G_IRQn }
37749 /* ENET Buffer Descriptor and Buffer Address Alignment. */
37750 #define ENET_BUFF_ALIGNMENT                      (64U)
37751 
37752 
37753 /*!
37754  * @}
37755  */ /* end of group ENET_Peripheral_Access_Layer */
37756 
37757 
37758 /* ----------------------------------------------------------------------------
37759    -- ENET_QOS Peripheral Access Layer
37760    ---------------------------------------------------------------------------- */
37761 
37762 /*!
37763  * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
37764  * @{
37765  */
37766 
37767 /** ENET_QOS - Register Layout Typedef */
37768 typedef struct {
37769   __IO uint32_t MAC_CONFIGURATION;                 /**< MAC Configuration Register, offset: 0x0 */
37770   __IO uint32_t MAC_EXT_CONFIGURATION;             /**< MAC Extended Configuration Register, offset: 0x4 */
37771   __IO uint32_t MAC_PACKET_FILTER;                 /**< MAC Packet Filter, offset: 0x8 */
37772   __IO uint32_t MAC_WATCHDOG_TIMEOUT;              /**< Watchdog Timeout, offset: 0xC */
37773   __IO uint32_t MAC_HASH_TABLE_REG0;               /**< MAC Hash Table Register 0, offset: 0x10 */
37774   __IO uint32_t MAC_HASH_TABLE_REG1;               /**< MAC Hash Table Register 1, offset: 0x14 */
37775        uint8_t RESERVED_0[56];
37776   __IO uint32_t MAC_VLAN_TAG_CTRL;                 /**< MAC VLAN Tag Control, offset: 0x50 */
37777   __IO uint32_t MAC_VLAN_TAG_DATA;                 /**< MAC VLAN Tag Data, offset: 0x54 */
37778   __IO uint32_t MAC_VLAN_HASH_TABLE;               /**< MAC VLAN Hash Table, offset: 0x58 */
37779        uint8_t RESERVED_1[4];
37780   __IO uint32_t MAC_VLAN_INCL;                     /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
37781   __IO uint32_t MAC_INNER_VLAN_INCL;               /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
37782        uint8_t RESERVED_2[8];
37783   __IO uint32_t MAC_TX_FLOW_CTRL_Q[5];             /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
37784        uint8_t RESERVED_3[12];
37785   __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< MAC Rx Flow Control, offset: 0x90 */
37786   __IO uint32_t MAC_RXQ_CTRL4;                     /**< Receive Queue Control 4, offset: 0x94 */
37787   __IO uint32_t MAC_TXQ_PRTY_MAP0;                 /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
37788   __IO uint32_t MAC_TXQ_PRTY_MAP1;                 /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
37789   __IO uint32_t MAC_RXQ_CTRL[4];                   /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
37790   __I  uint32_t MAC_INTERRUPT_STATUS;              /**< Interrupt Status, offset: 0xB0 */
37791   __IO uint32_t MAC_INTERRUPT_ENABLE;              /**< Interrupt Enable, offset: 0xB4 */
37792   __I  uint32_t MAC_RX_TX_STATUS;                  /**< Receive Transmit Status, offset: 0xB8 */
37793        uint8_t RESERVED_4[4];
37794   __IO uint32_t MAC_PMT_CONTROL_STATUS;            /**< PMT Control and Status, offset: 0xC0 */
37795   __IO uint32_t MAC_RWK_PACKET_FILTER;             /**< Remote Wakeup Filter, offset: 0xC4 */
37796        uint8_t RESERVED_5[8];
37797   __IO uint32_t MAC_LPI_CONTROL_STATUS;            /**< LPI Control and Status, offset: 0xD0 */
37798   __IO uint32_t MAC_LPI_TIMERS_CONTROL;            /**< LPI Timers Control, offset: 0xD4 */
37799   __IO uint32_t MAC_LPI_ENTRY_TIMER;               /**< Tx LPI Entry Timer Control, offset: 0xD8 */
37800   __IO uint32_t MAC_ONEUS_TIC_COUNTER;             /**< One-microsecond Reference Timer, offset: 0xDC */
37801        uint8_t RESERVED_6[24];
37802   __IO uint32_t MAC_PHYIF_CONTROL_STATUS;          /**< PHY Interface Control and Status, offset: 0xF8 */
37803        uint8_t RESERVED_7[20];
37804   __I  uint32_t MAC_VERSION;                       /**< MAC Version, offset: 0x110 */
37805   __I  uint32_t MAC_DEBUG;                         /**< MAC Debug, offset: 0x114 */
37806        uint8_t RESERVED_8[4];
37807   __I  uint32_t MAC_HW_FEAT[4];                    /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
37808        uint8_t RESERVED_9[212];
37809   __IO uint32_t MAC_MDIO_ADDRESS;                  /**< MDIO Address, offset: 0x200 */
37810   __IO uint32_t MAC_MDIO_DATA;                     /**< MAC MDIO Data, offset: 0x204 */
37811        uint8_t RESERVED_10[40];
37812   __IO uint32_t MAC_CSR_SW_CTRL;                   /**< CSR Software Control, offset: 0x230 */
37813   __IO uint32_t MAC_FPE_CTRL_STS;                  /**< Frame Preemption Control, offset: 0x234 */
37814        uint8_t RESERVED_11[8];
37815   __I  uint32_t MAC_PRESN_TIME_NS;                 /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
37816   __IO uint32_t MAC_PRESN_TIME_UPDT;               /**< MAC 1722 Presentation Time, offset: 0x244 */
37817        uint8_t RESERVED_12[184];
37818   struct {                                         /* offset: 0x300, array step: 0x8 */
37819     __IO uint32_t HIGH;                              /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
37820     __IO uint32_t LOW;                               /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
37821   } MAC_ADDRESS[64];
37822        uint8_t RESERVED_13[512];
37823   __IO uint32_t MAC_MMC_CONTROL;                   /**< MMC Control, offset: 0x700 */
37824   __I  uint32_t MAC_MMC_RX_INTERRUPT;              /**< MMC Rx Interrupt, offset: 0x704 */
37825   __I  uint32_t MAC_MMC_TX_INTERRUPT;              /**< MMC Tx Interrupt, offset: 0x708 */
37826   __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK;         /**< MMC Rx Interrupt Mask, offset: 0x70C */
37827   __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK;         /**< MMC Tx Interrupt Mask, offset: 0x710 */
37828   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD;       /**< Tx Octet Count Good and Bad, offset: 0x714 */
37829   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD;      /**< Tx Packet Count Good and Bad, offset: 0x718 */
37830   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD;     /**< Tx Broadcast Packets Good, offset: 0x71C */
37831   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD;     /**< Tx Multicast Packets Good, offset: 0x720 */
37832   __I  uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD;  /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
37833   __I  uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
37834   __I  uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
37835   __I  uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
37836   __I  uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
37837   __I  uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
37838   __I  uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD;   /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
37839   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
37840   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
37841   __I  uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS;    /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
37842   __I  uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
37843   __I  uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
37844   __I  uint32_t MAC_TX_DEFERRED_PACKETS;           /**< Deferred Packets Transmitted, offset: 0x754 */
37845   __I  uint32_t MAC_TX_LATE_COLLISION_PACKETS;     /**< Late Collision Packets Transmitted, offset: 0x758 */
37846   __I  uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
37847   __I  uint32_t MAC_TX_CARRIER_ERROR_PACKETS;      /**< Carrier Error Packets Transmitted, offset: 0x760 */
37848   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD;           /**< Bytes Transmitted in Good Packets, offset: 0x764 */
37849   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD;          /**< Good Packets Transmitted, offset: 0x768 */
37850   __I  uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR;   /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
37851   __I  uint32_t MAC_TX_PAUSE_PACKETS;              /**< Pause Packets Transmitted, offset: 0x770 */
37852   __I  uint32_t MAC_TX_VLAN_PACKETS_GOOD;          /**< Good VLAN Packets Transmitted, offset: 0x774 */
37853   __I  uint32_t MAC_TX_OSIZE_PACKETS_GOOD;         /**< Good Oversize Packets Transmitted, offset: 0x778 */
37854        uint8_t RESERVED_14[4];
37855   __I  uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD;     /**< Good and Bad Packets Received, offset: 0x780 */
37856   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD;       /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
37857   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD;           /**< Bytes in Good Packets Received, offset: 0x788 */
37858   __I  uint32_t MAC_RX_BROADCAST_PACKETS_GOOD;     /**< Good Broadcast Packets Received, offset: 0x78C */
37859   __I  uint32_t MAC_RX_MULTICAST_PACKETS_GOOD;     /**< Good Multicast Packets Received, offset: 0x790 */
37860   __I  uint32_t MAC_RX_CRC_ERROR_PACKETS;          /**< CRC Error Packets Received, offset: 0x794 */
37861   __I  uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS;    /**< Alignment Error Packets Received, offset: 0x798 */
37862   __I  uint32_t MAC_RX_RUNT_ERROR_PACKETS;         /**< Runt Error Packets Received, offset: 0x79C */
37863   __I  uint32_t MAC_RX_JABBER_ERROR_PACKETS;       /**< Jabber Error Packets Received, offset: 0x7A0 */
37864   __I  uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD;     /**< Good Undersize Packets Received, offset: 0x7A4 */
37865   __I  uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD;      /**< Good Oversize Packets Received, offset: 0x7A8 */
37866   __I  uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD;  /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
37867   __I  uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
37868   __I  uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
37869   __I  uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
37870   __I  uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
37871   __I  uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
37872   __I  uint32_t MAC_RX_UNICAST_PACKETS_GOOD;       /**< Good Unicast Packets Received, offset: 0x7C4 */
37873   __I  uint32_t MAC_RX_LENGTH_ERROR_PACKETS;       /**< Length Error Packets Received, offset: 0x7C8 */
37874   __I  uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS;  /**< Out-of-range Type Packets Received, offset: 0x7CC */
37875   __I  uint32_t MAC_RX_PAUSE_PACKETS;              /**< Pause Packets Received, offset: 0x7D0 */
37876   __I  uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS;      /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
37877   __I  uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD;      /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
37878   __I  uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS;     /**< Watchdog Error Packets Received, offset: 0x7DC */
37879   __I  uint32_t MAC_RX_RECEIVE_ERROR_PACKETS;      /**< Receive Error Packets Received, offset: 0x7E0 */
37880   __I  uint32_t MAC_RX_CONTROL_PACKETS_GOOD;       /**< Good Control Packets Received, offset: 0x7E4 */
37881        uint8_t RESERVED_15[4];
37882   __I  uint32_t MAC_TX_LPI_USEC_CNTR;              /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
37883   __I  uint32_t MAC_TX_LPI_TRAN_CNTR;              /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
37884   __I  uint32_t MAC_RX_LPI_USEC_CNTR;              /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
37885   __I  uint32_t MAC_RX_LPI_TRAN_CNTR;              /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
37886        uint8_t RESERVED_16[4];
37887   __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK;     /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
37888        uint8_t RESERVED_17[4];
37889   __I  uint32_t MAC_MMC_IPC_RX_INTERRUPT;          /**< MMC IPC Receive Interrupt, offset: 0x808 */
37890        uint8_t RESERVED_18[4];
37891   __I  uint32_t MAC_RXIPV4_GOOD_PACKETS;           /**< Good IPv4 Datagrams Received, offset: 0x810 */
37892   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS;   /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
37893   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS;     /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
37894   __I  uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS;     /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
37895   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
37896   __I  uint32_t MAC_RXIPV6_GOOD_PACKETS;           /**< Good IPv6 Datagrams Received, offset: 0x824 */
37897   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS;   /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
37898   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS;     /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
37899   __I  uint32_t MAC_RXUDP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
37900   __I  uint32_t MAC_RXUDP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
37901   __I  uint32_t MAC_RXTCP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
37902   __I  uint32_t MAC_RXTCP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
37903   __I  uint32_t MAC_RXICMP_GOOD_PACKETS;           /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
37904   __I  uint32_t MAC_RXICMP_ERROR_PACKETS;          /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
37905        uint8_t RESERVED_19[8];
37906   __I  uint32_t MAC_RXIPV4_GOOD_OCTETS;            /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
37907   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
37908   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
37909   __I  uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS;      /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
37910   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
37911   __I  uint32_t MAC_RXIPV6_GOOD_OCTETS;            /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
37912   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
37913   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
37914   __I  uint32_t MAC_RXUDP_GOOD_OCTETS;             /**< Bytes Received in Good UDP Segment, offset: 0x870 */
37915   __I  uint32_t MAC_RXUDP_ERROR_OCTETS;            /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
37916   __I  uint32_t MAC_RXTCP_GOOD_OCTETS;             /**< Bytes Received in Good TCP Segment, offset: 0x878 */
37917   __I  uint32_t MAC_RXTCP_ERROR_OCTETS;            /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
37918   __I  uint32_t MAC_RXICMP_GOOD_OCTETS;            /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
37919   __I  uint32_t MAC_RXICMP_ERROR_OCTETS;           /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
37920        uint8_t RESERVED_20[24];
37921   __I  uint32_t MAC_MMC_FPE_TX_INTERRUPT;          /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
37922   __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK;     /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
37923   __I  uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
37924   __I  uint32_t MAC_MMC_TX_HOLD_REQ_CNTR;          /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
37925        uint8_t RESERVED_21[16];
37926   __I  uint32_t MAC_MMC_FPE_RX_INTERRUPT;          /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
37927   __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK;     /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
37928   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
37929   __I  uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR;    /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
37930   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
37931   __I  uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
37932        uint8_t RESERVED_22[40];
37933   __IO uint32_t MAC_L3_L4_CONTROL0;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
37934   __IO uint32_t MAC_LAYER4_ADDRESS0;               /**< Layer 4 Address 0, offset: 0x904 */
37935        uint8_t RESERVED_23[8];
37936   __IO uint32_t MAC_LAYER3_ADDR0_REG0;             /**< Layer 3 Address 0 Register 0, offset: 0x910 */
37937   __IO uint32_t MAC_LAYER3_ADDR1_REG0;             /**< Layer 3 Address 1 Register 0, offset: 0x914 */
37938   __IO uint32_t MAC_LAYER3_ADDR2_REG0;             /**< Layer 3 Address 2 Register 0, offset: 0x918 */
37939   __IO uint32_t MAC_LAYER3_ADDR3_REG0;             /**< Layer 3 Address 3 Register 0, offset: 0x91C */
37940        uint8_t RESERVED_24[16];
37941   __IO uint32_t MAC_L3_L4_CONTROL1;                /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
37942   __IO uint32_t MAC_LAYER4_ADDRESS1;               /**< Layer 4 Address 0, offset: 0x934 */
37943        uint8_t RESERVED_25[8];
37944   __IO uint32_t MAC_LAYER3_ADDR0_REG1;             /**< Layer 3 Address 0 Register 1, offset: 0x940 */
37945   __IO uint32_t MAC_LAYER3_ADDR1_REG1;             /**< Layer 3 Address 1 Register 1, offset: 0x944 */
37946   __IO uint32_t MAC_LAYER3_ADDR2_REG1;             /**< Layer 3 Address 2 Register 1, offset: 0x948 */
37947   __IO uint32_t MAC_LAYER3_ADDR3_REG1;             /**< Layer 3 Address 3 Register 1, offset: 0x94C */
37948        uint8_t RESERVED_26[16];
37949   __IO uint32_t MAC_L3_L4_CONTROL2;                /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
37950   __IO uint32_t MAC_LAYER4_ADDRESS2;               /**< Layer 4 Address 2, offset: 0x964 */
37951        uint8_t RESERVED_27[8];
37952   __IO uint32_t MAC_LAYER3_ADDR0_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x970 */
37953   __IO uint32_t MAC_LAYER3_ADDR1_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x974 */
37954   __IO uint32_t MAC_LAYER3_ADDR2_REG2;             /**< Layer 3 Address 2 Register 2, offset: 0x978 */
37955   __IO uint32_t MAC_LAYER3_ADDR3_REG2;             /**< Layer 3 Address 3 Register 2, offset: 0x97C */
37956        uint8_t RESERVED_28[16];
37957   __IO uint32_t MAC_L3_L4_CONTROL3;                /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
37958   __IO uint32_t MAC_LAYER4_ADDRESS3;               /**< Layer 4 Address 3, offset: 0x994 */
37959        uint8_t RESERVED_29[8];
37960   __IO uint32_t MAC_LAYER3_ADDR0_REG3;             /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
37961   __IO uint32_t MAC_LAYER3_ADDR1_REG3;             /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
37962   __IO uint32_t MAC_LAYER3_ADDR2_REG3;             /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
37963   __IO uint32_t MAC_LAYER3_ADDR3_REG3;             /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
37964        uint8_t RESERVED_30[16];
37965   __IO uint32_t MAC_L3_L4_CONTROL4;                /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
37966   __IO uint32_t MAC_LAYER4_ADDRESS4;               /**< Layer 4 Address 4, offset: 0x9C4 */
37967        uint8_t RESERVED_31[8];
37968   __IO uint32_t MAC_LAYER3_ADDR0_REG4;             /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
37969   __IO uint32_t MAC_LAYER3_ADDR1_REG4;             /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
37970   __IO uint32_t MAC_LAYER3_ADDR2_REG4;             /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
37971   __IO uint32_t MAC_LAYER3_ADDR3_REG4;             /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
37972        uint8_t RESERVED_32[16];
37973   __IO uint32_t MAC_L3_L4_CONTROL5;                /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
37974   __IO uint32_t MAC_LAYER4_ADDRESS5;               /**< Layer 4 Address 5, offset: 0x9F4 */
37975        uint8_t RESERVED_33[8];
37976   __IO uint32_t MAC_LAYER3_ADDR0_REG5;             /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
37977   __IO uint32_t MAC_LAYER3_ADDR1_REG5;             /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
37978   __IO uint32_t MAC_LAYER3_ADDR2_REG5;             /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
37979   __IO uint32_t MAC_LAYER3_ADDR3_REG5;             /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
37980        uint8_t RESERVED_34[16];
37981   __IO uint32_t MAC_L3_L4_CONTROL6;                /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
37982   __IO uint32_t MAC_LAYER4_ADDRESS6;               /**< Layer 4 Address 6, offset: 0xA24 */
37983        uint8_t RESERVED_35[8];
37984   __IO uint32_t MAC_LAYER3_ADDR0_REG6;             /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
37985   __IO uint32_t MAC_LAYER3_ADDR1_REG6;             /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
37986   __IO uint32_t MAC_LAYER3_ADDR2_REG6;             /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
37987   __IO uint32_t MAC_LAYER3_ADDR3_REG6;             /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
37988        uint8_t RESERVED_36[16];
37989   __IO uint32_t MAC_L3_L4_CONTROL7;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
37990   __IO uint32_t MAC_LAYER4_ADDRESS7;               /**< Layer 4 Address 7, offset: 0xA54 */
37991        uint8_t RESERVED_37[8];
37992   __IO uint32_t MAC_LAYER3_ADDR0_REG7;             /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
37993   __IO uint32_t MAC_LAYER3_ADDR1_REG7;             /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
37994   __IO uint32_t MAC_LAYER3_ADDR2_REG7;             /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
37995   __IO uint32_t MAC_LAYER3_ADDR3_REG7;             /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
37996        uint8_t RESERVED_38[144];
37997   __IO uint32_t MAC_TIMESTAMP_CONTROL;             /**< Timestamp Control, offset: 0xB00 */
37998   __IO uint32_t MAC_SUB_SECOND_INCREMENT;          /**< Subsecond Increment, offset: 0xB04 */
37999   __I  uint32_t MAC_SYSTEM_TIME_SECONDS;           /**< System Time Seconds, offset: 0xB08 */
38000   __I  uint32_t MAC_SYSTEM_TIME_NANOSECONDS;       /**< System Time Nanoseconds, offset: 0xB0C */
38001   __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE;    /**< System Time Seconds Update, offset: 0xB10 */
38002   __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
38003   __IO uint32_t MAC_TIMESTAMP_ADDEND;              /**< Timestamp Addend, offset: 0xB18 */
38004   __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
38005   __I  uint32_t MAC_TIMESTAMP_STATUS;              /**< Timestamp Status, offset: 0xB20 */
38006        uint8_t RESERVED_39[12];
38007   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
38008   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
38009        uint8_t RESERVED_40[8];
38010   __IO uint32_t MAC_AUXILIARY_CONTROL;             /**< Auxiliary Timestamp Control, offset: 0xB40 */
38011        uint8_t RESERVED_41[4];
38012   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
38013   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS;   /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
38014   __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR;   /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
38015   __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR;    /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
38016   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
38017   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
38018   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
38019   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
38020   __I  uint32_t MAC_TIMESTAMP_INGRESS_LATENCY;     /**< Timestamp Ingress Latency, offset: 0xB68 */
38021   __I  uint32_t MAC_TIMESTAMP_EGRESS_LATENCY;      /**< Timestamp Egress Latency, offset: 0xB6C */
38022   __IO uint32_t MAC_PPS_CONTROL;                   /**< PPS Control, offset: 0xB70 */
38023        uint8_t RESERVED_42[12];
38024   __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS;      /**< PPS0 Target Time Seconds, offset: 0xB80 */
38025   __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS;  /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
38026   __IO uint32_t MAC_PPS0_INTERVAL;                 /**< PPS0 Interval, offset: 0xB88 */
38027   __IO uint32_t MAC_PPS0_WIDTH;                    /**< PPS0 Width, offset: 0xB8C */
38028   __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS;      /**< PPS1 Target Time Seconds, offset: 0xB90 */
38029   __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS;  /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
38030   __IO uint32_t MAC_PPS1_INTERVAL;                 /**< PPS1 Interval, offset: 0xB98 */
38031   __IO uint32_t MAC_PPS1_WIDTH;                    /**< PPS1 Width, offset: 0xB9C */
38032   __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS;      /**< PPS2 Target Time Seconds, offset: 0xBA0 */
38033   __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS;  /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
38034   __IO uint32_t MAC_PPS2_INTERVAL;                 /**< PPS2 Interval, offset: 0xBA8 */
38035   __IO uint32_t MAC_PPS2_WIDTH;                    /**< PPS2 Width, offset: 0xBAC */
38036   __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS;      /**< PPS3 Target Time Seconds, offset: 0xBB0 */
38037   __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS;  /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
38038   __IO uint32_t MAC_PPS3_INTERVAL;                 /**< PPS3 Interval, offset: 0xBB8 */
38039   __IO uint32_t MAC_PPS3_WIDTH;                    /**< PPS3 Width, offset: 0xBBC */
38040   __IO uint32_t MAC_PTO_CONTROL;                   /**< PTP Offload Engine Control, offset: 0xBC0 */
38041   __IO uint32_t MAC_SOURCE_PORT_IDENTITY0;         /**< Source Port Identity 0, offset: 0xBC4 */
38042   __IO uint32_t MAC_SOURCE_PORT_IDENTITY1;         /**< Source Port Identity 1, offset: 0xBC8 */
38043   __IO uint32_t MAC_SOURCE_PORT_IDENTITY2;         /**< Source Port Identity 2, offset: 0xBCC */
38044   __IO uint32_t MAC_LOG_MESSAGE_INTERVAL;          /**< Log Message Interval, offset: 0xBD0 */
38045        uint8_t RESERVED_43[44];
38046   __IO uint32_t MTL_OPERATION_MODE;                /**< MTL Operation Mode, offset: 0xC00 */
38047        uint8_t RESERVED_44[4];
38048   __IO uint32_t MTL_DBG_CTL;                       /**< FIFO Debug Access Control and Status, offset: 0xC08 */
38049   __IO uint32_t MTL_DBG_STS;                       /**< FIFO Debug Status, offset: 0xC0C */
38050   __IO uint32_t MTL_FIFO_DEBUG_DATA;               /**< FIFO Debug Data, offset: 0xC10 */
38051        uint8_t RESERVED_45[12];
38052   __I  uint32_t MTL_INTERRUPT_STATUS;              /**< MTL Interrupt Status, offset: 0xC20 */
38053        uint8_t RESERVED_46[12];
38054   __IO uint32_t MTL_RXQ_DMA_MAP0;                  /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
38055   __IO uint32_t MTL_RXQ_DMA_MAP1;                  /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
38056        uint8_t RESERVED_47[8];
38057   __IO uint32_t MTL_TBS_CTRL;                      /**< Time Based Scheduling Control, offset: 0xC40 */
38058        uint8_t RESERVED_48[12];
38059   __IO uint32_t MTL_EST_CONTROL;                   /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
38060        uint8_t RESERVED_49[4];
38061   __IO uint32_t MTL_EST_STATUS;                    /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
38062        uint8_t RESERVED_50[4];
38063   __IO uint32_t MTL_EST_SCH_ERROR;                 /**< EST Scheduling Error, offset: 0xC60 */
38064   __IO uint32_t MTL_EST_FRM_SIZE_ERROR;            /**< EST Frame Size Error, offset: 0xC64 */
38065   __I  uint32_t MTL_EST_FRM_SIZE_CAPTURE;          /**< EST Frame Size Capture, offset: 0xC68 */
38066        uint8_t RESERVED_51[4];
38067   __IO uint32_t MTL_EST_INTR_ENABLE;               /**< EST Interrupt Enable, offset: 0xC70 */
38068        uint8_t RESERVED_52[12];
38069   __IO uint32_t MTL_EST_GCL_CONTROL;               /**< EST GCL Control, offset: 0xC80 */
38070   __IO uint32_t MTL_EST_GCL_DATA;                  /**< EST GCL Data, offset: 0xC84 */
38071        uint8_t RESERVED_53[8];
38072   __IO uint32_t MTL_FPE_CTRL_STS;                  /**< Frame Preemption Control and Status, offset: 0xC90 */
38073   __IO uint32_t MTL_FPE_ADVANCE;                   /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
38074        uint8_t RESERVED_54[8];
38075   __IO uint32_t MTL_RXP_CONTROL_STATUS;            /**< RXP Control Status, offset: 0xCA0 */
38076   __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS;  /**< RXP Interrupt Control Status, offset: 0xCA4 */
38077   __I  uint32_t MTL_RXP_DROP_CNT;                  /**< RXP Drop Count, offset: 0xCA8 */
38078   __I  uint32_t MTL_RXP_ERROR_CNT;                 /**< RXP Error Count, offset: 0xCAC */
38079   __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
38080   __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA;         /**< RXP Indirect Access Data, offset: 0xCB4 */
38081        uint8_t RESERVED_55[72];
38082   struct {                                         /* offset: 0xD00, array step: 0x40 */
38083     __IO uint32_t MTL_TXQX_OP_MODE;                  /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
38084     __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
38085     __I  uint32_t MTL_TXQX_DBG;                      /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
38086          uint8_t RESERVED_0[4];
38087     __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40 */
38088     __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
38089     __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
38090     __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40 */
38091     __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40 */
38092     __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40 */
38093          uint8_t RESERVED_1[4];
38094     __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
38095     __IO uint32_t MTL_RXQX_OP_MODE;                  /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
38096     __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
38097     __I  uint32_t MTL_RXQX_DBG;                      /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
38098     __IO uint32_t MTL_RXQX_CTRL;                     /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
38099   } MTL_QUEUE[5];
38100        uint8_t RESERVED_56[448];
38101   __IO uint32_t DMA_MODE;                          /**< DMA Bus Mode, offset: 0x1000 */
38102   __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus Mode, offset: 0x1004 */
38103   __I  uint32_t DMA_INTERRUPT_STATUS;              /**< DMA Interrupt Status, offset: 0x1008 */
38104   __I  uint32_t DMA_DEBUG_STATUS0;                 /**< DMA Debug Status 0, offset: 0x100C */
38105   __I  uint32_t DMA_DEBUG_STATUS1;                 /**< DMA Debug Status 1, offset: 0x1010 */
38106        uint8_t RESERVED_57[44];
38107   __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL;        /**< AXI LPI Entry Interval Control, offset: 0x1040 */
38108        uint8_t RESERVED_58[12];
38109   __IO uint32_t DMA_TBS_CTRL;                      /**< TBS Control, offset: 0x1050 */
38110        uint8_t RESERVED_59[172];
38111   struct {                                         /* offset: 0x1100, array step: 0x80 */
38112     __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
38113     __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
38114     __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
38115          uint8_t RESERVED_0[8];
38116     __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
38117          uint8_t RESERVED_1[4];
38118     __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
38119     __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
38120          uint8_t RESERVED_2[4];
38121     __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
38122     __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
38123     __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
38124     __IO uint32_t DMA_CHX_INT_EN;                    /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
38125     __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
38126     __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
38127          uint8_t RESERVED_3[4];
38128     __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
38129          uint8_t RESERVED_4[4];
38130     __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
38131          uint8_t RESERVED_5[4];
38132     __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
38133          uint8_t RESERVED_6[4];
38134     __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
38135     __IO uint32_t DMA_CHX_STAT;                      /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
38136     __I  uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
38137     __I  uint32_t DMA_CHX_RXP_ACCEPT_CNT;            /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
38138     __I  uint32_t DMA_CHX_RX_ERI_CNT;                /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
38139          uint8_t RESERVED_7[16];
38140   } DMA_CH[5];
38141 } ENET_QOS_Type;
38142 
38143 /* ----------------------------------------------------------------------------
38144    -- ENET_QOS Register Masks
38145    ---------------------------------------------------------------------------- */
38146 
38147 /*!
38148  * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
38149  * @{
38150  */
38151 
38152 /*! @name MAC_CONFIGURATION - MAC Configuration Register */
38153 /*! @{ */
38154 
38155 #define ENET_QOS_MAC_CONFIGURATION_RE_MASK       (0x1U)
38156 #define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT      (0U)
38157 /*! RE - Receiver Enable
38158  *  0b0..Receiver is disabled
38159  *  0b1..Receiver is enabled
38160  */
38161 #define ENET_QOS_MAC_CONFIGURATION_RE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
38162 
38163 #define ENET_QOS_MAC_CONFIGURATION_TE_MASK       (0x2U)
38164 #define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT      (1U)
38165 /*! TE - Transmitter Enable
38166  *  0b0..Transmitter is disabled
38167  *  0b1..Transmitter is enabled
38168  */
38169 #define ENET_QOS_MAC_CONFIGURATION_TE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
38170 
38171 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK   (0xCU)
38172 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT  (2U)
38173 /*! PRELEN - Preamble Length for Transmit packets
38174  *  0b10..3 bytes of preamble
38175  *  0b01..5 bytes of preamble
38176  *  0b00..7 bytes of preamble
38177  *  0b11..Reserved
38178  */
38179 #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
38180 
38181 #define ENET_QOS_MAC_CONFIGURATION_DC_MASK       (0x10U)
38182 #define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT      (4U)
38183 /*! DC - Deferral Check
38184  *  0b0..Deferral check function is disabled
38185  *  0b1..Deferral check function is enabled
38186  */
38187 #define ENET_QOS_MAC_CONFIGURATION_DC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
38188 
38189 #define ENET_QOS_MAC_CONFIGURATION_BL_MASK       (0x60U)
38190 #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT      (5U)
38191 /*! BL - Back-Off Limit
38192  *  0b11..k = min(n,1)
38193  *  0b00..k = min(n,10)
38194  *  0b10..k = min(n,4)
38195  *  0b01..k = min(n,8)
38196  */
38197 #define ENET_QOS_MAC_CONFIGURATION_BL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
38198 
38199 #define ENET_QOS_MAC_CONFIGURATION_DR_MASK       (0x100U)
38200 #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT      (8U)
38201 /*! DR - Disable Retry
38202  *  0b1..Disable Retry
38203  *  0b0..Enable Retry
38204  */
38205 #define ENET_QOS_MAC_CONFIGURATION_DR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
38206 
38207 #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK     (0x200U)
38208 #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT    (9U)
38209 /*! DCRS - Disable Carrier Sense During Transmission
38210  *  0b1..Disable Carrier Sense During Transmission
38211  *  0b0..Enable Carrier Sense During Transmission
38212  */
38213 #define ENET_QOS_MAC_CONFIGURATION_DCRS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
38214 
38215 #define ENET_QOS_MAC_CONFIGURATION_DO_MASK       (0x400U)
38216 #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT      (10U)
38217 /*! DO - Disable Receive Own
38218  *  0b1..Disable Receive Own
38219  *  0b0..Enable Receive Own
38220  */
38221 #define ENET_QOS_MAC_CONFIGURATION_DO(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
38222 
38223 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK   (0x800U)
38224 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT  (11U)
38225 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
38226  *  0b0..ECRSFD is disabled
38227  *  0b1..ECRSFD is enabled
38228  */
38229 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
38230 
38231 #define ENET_QOS_MAC_CONFIGURATION_LM_MASK       (0x1000U)
38232 #define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT      (12U)
38233 /*! LM - Loopback Mode
38234  *  0b0..Loopback is disabled
38235  *  0b1..Loopback is enabled
38236  */
38237 #define ENET_QOS_MAC_CONFIGURATION_LM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
38238 
38239 #define ENET_QOS_MAC_CONFIGURATION_DM_MASK       (0x2000U)
38240 #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT      (13U)
38241 /*! DM - Duplex Mode
38242  *  0b1..Full-duplex mode
38243  *  0b0..Half-duplex mode
38244  */
38245 #define ENET_QOS_MAC_CONFIGURATION_DM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
38246 
38247 #define ENET_QOS_MAC_CONFIGURATION_FES_MASK      (0x4000U)
38248 #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT     (14U)
38249 /*! FES - Speed
38250  *  0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
38251  *  0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
38252  */
38253 #define ENET_QOS_MAC_CONFIGURATION_FES(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
38254 
38255 #define ENET_QOS_MAC_CONFIGURATION_PS_MASK       (0x8000U)
38256 #define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT      (15U)
38257 /*! PS - Port Select
38258  *  0b0..For 1000 or 2500 Mbps operations
38259  *  0b1..For 10 or 100 Mbps operations
38260  */
38261 #define ENET_QOS_MAC_CONFIGURATION_PS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
38262 
38263 #define ENET_QOS_MAC_CONFIGURATION_JE_MASK       (0x10000U)
38264 #define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT      (16U)
38265 /*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
38266  *    (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
38267  *    status.
38268  *  0b0..Jumbo packet is disabled
38269  *  0b1..Jumbo packet is enabled
38270  */
38271 #define ENET_QOS_MAC_CONFIGURATION_JE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
38272 
38273 #define ENET_QOS_MAC_CONFIGURATION_JD_MASK       (0x20000U)
38274 #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT      (17U)
38275 /*! JD - Jabber Disable
38276  *  0b1..Jabber is disabled
38277  *  0b0..Jabber is enabled
38278  */
38279 #define ENET_QOS_MAC_CONFIGURATION_JD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
38280 
38281 #define ENET_QOS_MAC_CONFIGURATION_BE_MASK       (0x40000U)
38282 #define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT      (18U)
38283 /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
38284  *    transmission in the GMII half-duplex mode.
38285  *  0b0..Packet Burst is disabled
38286  *  0b1..Packet Burst is enabled
38287  */
38288 #define ENET_QOS_MAC_CONFIGURATION_BE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
38289 
38290 #define ENET_QOS_MAC_CONFIGURATION_WD_MASK       (0x80000U)
38291 #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT      (19U)
38292 /*! WD - Watchdog Disable
38293  *  0b1..Watchdog is disabled
38294  *  0b0..Watchdog is enabled
38295  */
38296 #define ENET_QOS_MAC_CONFIGURATION_WD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
38297 
38298 #define ENET_QOS_MAC_CONFIGURATION_ACS_MASK      (0x100000U)
38299 #define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT     (20U)
38300 /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
38301  *    on the incoming packets only if the value of the length field is less than 1,536 bytes.
38302  *  0b0..Automatic Pad or CRC Stripping is disabled
38303  *  0b1..Automatic Pad or CRC Stripping is enabled
38304  */
38305 #define ENET_QOS_MAC_CONFIGURATION_ACS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
38306 
38307 #define ENET_QOS_MAC_CONFIGURATION_CST_MASK      (0x200000U)
38308 #define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT     (21U)
38309 /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
38310  *    packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
38311  *    the packet to the application.
38312  *  0b0..CRC stripping for Type packets is disabled
38313  *  0b1..CRC stripping for Type packets is enabled
38314  */
38315 #define ENET_QOS_MAC_CONFIGURATION_CST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
38316 
38317 #define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK     (0x400000U)
38318 #define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT    (22U)
38319 /*! S2KP - IEEE 802.
38320  *  0b0..Support upto 2K packet is disabled
38321  *  0b1..Support upto 2K packet is Enabled
38322  */
38323 #define ENET_QOS_MAC_CONFIGURATION_S2KP(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
38324 
38325 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK   (0x800000U)
38326 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT  (23U)
38327 /*! GPSLCE - Giant Packet Size Limit Control Enable
38328  *  0b0..Giant Packet Size Limit Control is disabled
38329  *  0b1..Giant Packet Size Limit Control is enabled
38330  */
38331 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
38332 
38333 #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK      (0x7000000U)
38334 #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT     (24U)
38335 /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
38336  *  0b111..40 bit times IPG
38337  *  0b110..48 bit times IPG
38338  *  0b101..56 bit times IPG
38339  *  0b100..64 bit times IPG
38340  *  0b011..72 bit times IPG
38341  *  0b010..80 bit times IPG
38342  *  0b001..88 bit times IPG
38343  *  0b000..96 bit times IPG
38344  */
38345 #define ENET_QOS_MAC_CONFIGURATION_IPG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
38346 
38347 #define ENET_QOS_MAC_CONFIGURATION_IPC_MASK      (0x8000000U)
38348 #define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT     (27U)
38349 /*! IPC - Checksum Offload
38350  *  0b0..IP header/payload checksum checking is disabled
38351  *  0b1..IP header/payload checksum checking is enabled
38352  */
38353 #define ENET_QOS_MAC_CONFIGURATION_IPC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
38354 
38355 #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK     (0x70000000U)
38356 #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT    (28U)
38357 /*! SARC - Source Address Insertion or Replacement Control
38358  *  0b010..Contents of MAC Addr-0 inserted in SA field
38359  *  0b011..Contents of MAC Addr-0 replaces SA field
38360  *  0b110..Contents of MAC Addr-1 inserted in SA field
38361  *  0b111..Contents of MAC Addr-1 replaces SA field
38362  *  0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
38363  */
38364 #define ENET_QOS_MAC_CONFIGURATION_SARC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
38365 /*! @} */
38366 
38367 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
38368 /*! @{ */
38369 
38370 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
38371 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
38372 /*! GPSL - Giant Packet Size Limit
38373  */
38374 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
38375 
38376 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
38377 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
38378 /*! DCRCC - Disable CRC Checking for Received Packets
38379  *  0b1..CRC Checking is disabled
38380  *  0b0..CRC Checking is enabled
38381  */
38382 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
38383 
38384 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
38385 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
38386 /*! SPEN - Slow Protocol Detection Enable
38387  *  0b0..Slow Protocol Detection is disabled
38388  *  0b1..Slow Protocol Detection is enabled
38389  */
38390 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
38391 
38392 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK  (0x40000U)
38393 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
38394 /*! USP - Unicast Slow Protocol Packet Detect
38395  *  0b0..Unicast Slow Protocol Packet Detection is disabled
38396  *  0b1..Unicast Slow Protocol Packet Detection is enabled
38397  */
38398 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
38399 
38400 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK  (0x80000U)
38401 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
38402 /*! PDC - Packet Duplication Control
38403  *  0b0..Packet Duplication Control is disabled
38404  *  0b1..Packet Duplication Control is enabled
38405  */
38406 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
38407 
38408 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
38409 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
38410 /*! EIPGEN - Extended Inter-Packet Gap Enable
38411  *  0b0..Extended Inter-Packet Gap is disabled
38412  *  0b1..Extended Inter-Packet Gap is enabled
38413  */
38414 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
38415 
38416 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
38417 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
38418 /*! EIPG - Extended Inter-Packet Gap
38419  */
38420 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
38421 /*! @} */
38422 
38423 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */
38424 /*! @{ */
38425 
38426 #define ENET_QOS_MAC_PACKET_FILTER_PR_MASK       (0x1U)
38427 #define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT      (0U)
38428 /*! PR - Promiscuous Mode
38429  *  0b0..Promiscuous Mode is disabled
38430  *  0b1..Promiscuous Mode is enabled
38431  */
38432 #define ENET_QOS_MAC_PACKET_FILTER_PR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
38433 
38434 #define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK      (0x2U)
38435 #define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT     (1U)
38436 /*! HUC - Hash Unicast
38437  *  0b0..Hash Unicast is disabled
38438  *  0b1..Hash Unicast is enabled
38439  */
38440 #define ENET_QOS_MAC_PACKET_FILTER_HUC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
38441 
38442 #define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK      (0x4U)
38443 #define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT     (2U)
38444 /*! HMC - Hash Multicast
38445  *  0b0..Hash Multicast is disabled
38446  *  0b1..Hash Multicast is enabled
38447  */
38448 #define ENET_QOS_MAC_PACKET_FILTER_HMC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
38449 
38450 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK     (0x8U)
38451 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT    (3U)
38452 /*! DAIF - DA Inverse Filtering
38453  *  0b0..DA Inverse Filtering is disabled
38454  *  0b1..DA Inverse Filtering is enabled
38455  */
38456 #define ENET_QOS_MAC_PACKET_FILTER_DAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
38457 
38458 #define ENET_QOS_MAC_PACKET_FILTER_PM_MASK       (0x10U)
38459 #define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT      (4U)
38460 /*! PM - Pass All Multicast
38461  *  0b0..Pass All Multicast is disabled
38462  *  0b1..Pass All Multicast is enabled
38463  */
38464 #define ENET_QOS_MAC_PACKET_FILTER_PM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
38465 
38466 #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK      (0x20U)
38467 #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT     (5U)
38468 /*! DBF - Disable Broadcast Packets
38469  *  0b1..Disable Broadcast Packets
38470  *  0b0..Enable Broadcast Packets
38471  */
38472 #define ENET_QOS_MAC_PACKET_FILTER_DBF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
38473 
38474 #define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK      (0xC0U)
38475 #define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT     (6U)
38476 /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
38477  *    unicast and multicast Pause packets).
38478  *  0b00..MAC filters all control packets from reaching the application
38479  *  0b10..MAC forwards all control packets to the application even if they fail the Address filter
38480  *  0b11..MAC forwards the control packets that pass the Address filter
38481  *  0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
38482  */
38483 #define ENET_QOS_MAC_PACKET_FILTER_PCF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
38484 
38485 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK     (0x100U)
38486 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT    (8U)
38487 /*! SAIF - SA Inverse Filtering
38488  *  0b0..SA Inverse Filtering is disabled
38489  *  0b1..SA Inverse Filtering is enabled
38490  */
38491 #define ENET_QOS_MAC_PACKET_FILTER_SAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
38492 
38493 #define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK      (0x200U)
38494 #define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT     (9U)
38495 /*! SAF - Source Address Filter Enable
38496  *  0b0..SA Filtering is disabled
38497  *  0b1..SA Filtering is enabled
38498  */
38499 #define ENET_QOS_MAC_PACKET_FILTER_SAF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
38500 
38501 #define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK      (0x400U)
38502 #define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT     (10U)
38503 /*! HPF - Hash or Perfect Filter
38504  *  0b0..Hash or Perfect Filter is disabled
38505  *  0b1..Hash or Perfect Filter is enabled
38506  */
38507 #define ENET_QOS_MAC_PACKET_FILTER_HPF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
38508 
38509 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK     (0x10000U)
38510 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT    (16U)
38511 /*! VTFE - VLAN Tag Filter Enable
38512  *  0b0..VLAN Tag Filter is disabled
38513  *  0b1..VLAN Tag Filter is enabled
38514  */
38515 #define ENET_QOS_MAC_PACKET_FILTER_VTFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
38516 
38517 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK     (0x100000U)
38518 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT    (20U)
38519 /*! IPFE - Layer 3 and Layer 4 Filter Enable
38520  *  0b0..Layer 3 and Layer 4 Filters are disabled
38521  *  0b1..Layer 3 and Layer 4 Filters are enabled
38522  */
38523 #define ENET_QOS_MAC_PACKET_FILTER_IPFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
38524 
38525 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK     (0x200000U)
38526 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT    (21U)
38527 /*! DNTU - Drop Non-TCP/UDP over IP Packets
38528  *  0b1..Drop Non-TCP/UDP over IP Packets
38529  *  0b0..Forward Non-TCP/UDP over IP Packets
38530  */
38531 #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
38532 
38533 #define ENET_QOS_MAC_PACKET_FILTER_RA_MASK       (0x80000000U)
38534 #define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT      (31U)
38535 /*! RA - Receive All
38536  *  0b0..Receive All is disabled
38537  *  0b1..Receive All is enabled
38538  */
38539 #define ENET_QOS_MAC_PACKET_FILTER_RA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
38540 /*! @} */
38541 
38542 /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
38543 /*! @{ */
38544 
38545 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK   (0xFU)
38546 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT  (0U)
38547 /*! WTO - Watchdog Timeout
38548  *  0b1000..10 KB
38549  *  0b1001..11 KB
38550  *  0b1010..12 KB
38551  *  0b1011..13 KB
38552  *  0b1100..14 KB
38553  *  0b1101..15 KB
38554  *  0b1110..16383 Bytes
38555  *  0b0000..2 KB
38556  *  0b0001..3 KB
38557  *  0b0010..4 KB
38558  *  0b0011..5 KB
38559  *  0b0100..6 KB
38560  *  0b0101..7 KB
38561  *  0b0110..8 KB
38562  *  0b0111..9 KB
38563  *  0b1111..Reserved
38564  */
38565 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
38566 
38567 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK   (0x100U)
38568 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT  (8U)
38569 /*! PWE - Programmable Watchdog Enable
38570  *  0b0..Programmable Watchdog is disabled
38571  *  0b1..Programmable Watchdog is enabled
38572  */
38573 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
38574 /*! @} */
38575 
38576 /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
38577 /*! @{ */
38578 
38579 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
38580 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
38581 /*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table.
38582  */
38583 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
38584 /*! @} */
38585 
38586 /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
38587 /*! @{ */
38588 
38589 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
38590 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
38591 /*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table.
38592  */
38593 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
38594 /*! @} */
38595 
38596 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
38597 /*! @{ */
38598 
38599 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK       (0x1U)
38600 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT      (0U)
38601 /*! OB - Operation Busy
38602  *  0b0..Operation Busy is disabled
38603  *  0b1..Operation Busy is enabled
38604  */
38605 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
38606 
38607 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK       (0x2U)
38608 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT      (1U)
38609 /*! CT - Command Type
38610  *  0b1..Read operation
38611  *  0b0..Write operation
38612  */
38613 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
38614 
38615 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK      (0x7CU)
38616 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT     (2U)
38617 /*! OFS - Offset
38618  */
38619 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
38620 
38621 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK     (0x20000U)
38622 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT    (17U)
38623 /*! VTIM - VLAN Tag Inverse Match Enable
38624  *  0b0..VLAN Tag Inverse Match is disabled
38625  *  0b1..VLAN Tag Inverse Match is enabled
38626  */
38627 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
38628 
38629 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK     (0x40000U)
38630 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT    (18U)
38631 /*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
38632  *    packets (Type = 0x88A8) as valid VLAN tagged packets.
38633  *  0b0..S-VLAN is disabled
38634  *  0b1..S-VLAN is enabled
38635  */
38636 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
38637 
38638 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK     (0x600000U)
38639 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT    (21U)
38640 /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
38641  *    outer VLAN Tag in received packet.
38642  *  0b11..Always strip
38643  *  0b00..Do not strip
38644  *  0b10..Strip if VLAN filter fails
38645  *  0b01..Strip if VLAN filter passes
38646  */
38647 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
38648 
38649 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK   (0x1000000U)
38650 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT  (24U)
38651 /*! EVLRXS - Enable VLAN Tag in Rx status
38652  *  0b0..VLAN Tag in Rx status is disabled
38653  *  0b1..VLAN Tag in Rx status is enabled
38654  */
38655 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
38656 
38657 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK     (0x2000000U)
38658 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT    (25U)
38659 /*! VTHM - VLAN Tag Hash Table Match Enable
38660  *  0b0..VLAN Tag Hash Table Match is disabled
38661  *  0b1..VLAN Tag Hash Table Match is enabled
38662  */
38663 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
38664 
38665 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK    (0x4000000U)
38666 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT   (26U)
38667 /*! EDVLP - Enable Double VLAN Processing
38668  *  0b0..Double VLAN Processing is disabled
38669  *  0b1..Double VLAN Processing is enabled
38670  */
38671 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
38672 
38673 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK   (0x8000000U)
38674 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT  (27U)
38675 /*! ERIVLT - ERIVLT
38676  *  0b0..Inner VLAN tag is disabled
38677  *  0b1..Inner VLAN tag is enabled
38678  */
38679 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
38680 
38681 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK    (0x30000000U)
38682 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT   (28U)
38683 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
38684  *    on inner VLAN Tag in received packet.
38685  *  0b11..Always strip
38686  *  0b00..Do not strip
38687  *  0b10..Strip if VLAN filter fails
38688  *  0b01..Strip if VLAN filter passes
38689  */
38690 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
38691 
38692 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK  (0x80000000U)
38693 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
38694 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
38695  *  0b0..Inner VLAN Tag in Rx status is disabled
38696  *  0b1..Inner VLAN Tag in Rx status is enabled
38697  */
38698 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
38699 /*! @} */
38700 
38701 /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
38702 /*! @{ */
38703 
38704 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK      (0xFFFFU)
38705 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT     (0U)
38706 /*! VID - VLAN Tag ID
38707  */
38708 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
38709 
38710 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK      (0x10000U)
38711 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT     (16U)
38712 /*! VEN - VLAN Tag Enable
38713  *  0b0..VLAN Tag is disabled
38714  *  0b1..VLAN Tag is enabled
38715  */
38716 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
38717 
38718 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK      (0x20000U)
38719 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT     (17U)
38720 /*! ETV - 12bits or 16bits VLAN comparison
38721  *  0b1..12 bit VLAN comparison
38722  *  0b0..16 bit VLAN comparison
38723  */
38724 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
38725 
38726 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK   (0x40000U)
38727 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT  (18U)
38728 /*! DOVLTC - Disable VLAN Type Comparison
38729  *  0b1..VLAN type comparison is disabled
38730  *  0b0..VLAN type comparison is enabled
38731  */
38732 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
38733 
38734 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK   (0x80000U)
38735 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT  (19U)
38736 /*! ERSVLM - Enable S-VLAN Match for received Frames
38737  *  0b0..Receive S-VLAN Match is disabled
38738  *  0b1..Receive S-VLAN Match is enabled
38739  */
38740 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
38741 
38742 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK   (0x100000U)
38743 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT  (20U)
38744 /*! ERIVLT - Enable Inner VLAN Tag Comparison
38745  *  0b0..Inner VLAN tag comparison is disabled
38746  *  0b1..Inner VLAN tag comparison is enabled
38747  */
38748 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
38749 
38750 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK  (0x1000000U)
38751 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
38752 /*! DMACHEN - DMA Channel Number Enable
38753  *  0b0..DMA Channel Number is disabled
38754  *  0b1..DMA Channel Number is enabled
38755  */
38756 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
38757 
38758 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK   (0xE000000U)
38759 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT  (25U)
38760 /*! DMACHN - DMA Channel Number
38761  */
38762 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
38763 /*! @} */
38764 
38765 /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
38766 /*! @{ */
38767 
38768 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK   (0xFFFFU)
38769 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT  (0U)
38770 /*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table.
38771  */
38772 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
38773 /*! @} */
38774 
38775 /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
38776 /*! @{ */
38777 
38778 #define ENET_QOS_MAC_VLAN_INCL_VLT_MASK          (0xFFFFU)
38779 #define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT         (0U)
38780 /*! VLT - VLAN Tag for Transmit Packets
38781  */
38782 #define ENET_QOS_MAC_VLAN_INCL_VLT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
38783 
38784 #define ENET_QOS_MAC_VLAN_INCL_VLC_MASK          (0x30000U)
38785 #define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT         (16U)
38786 /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
38787  *    replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
38788  *    (bytes 15 and 16) of all transmitted packets with VLAN tags.
38789  *  0b01..VLAN tag deletion
38790  *  0b10..VLAN tag insertion
38791  *  0b00..No VLAN tag deletion, insertion, or replacement
38792  *  0b11..VLAN tag replacement
38793  */
38794 #define ENET_QOS_MAC_VLAN_INCL_VLC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
38795 
38796 #define ENET_QOS_MAC_VLAN_INCL_VLP_MASK          (0x40000U)
38797 #define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT         (18U)
38798 /*! VLP - VLAN Priority Control
38799  *  0b0..VLAN Priority Control is disabled
38800  *  0b1..VLAN Priority Control is enabled
38801  */
38802 #define ENET_QOS_MAC_VLAN_INCL_VLP(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
38803 
38804 #define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK         (0x80000U)
38805 #define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT        (19U)
38806 /*! CSVL - C-VLAN or S-VLAN
38807  *  0b0..C-VLAN type (0x8100) is inserted or replaced
38808  *  0b1..S-VLAN type (0x88A8) is inserted or replaced
38809  */
38810 #define ENET_QOS_MAC_VLAN_INCL_CSVL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
38811 
38812 #define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK         (0x100000U)
38813 #define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT        (20U)
38814 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
38815  *    replaced in Tx packet should be taken from: - The Tx descriptor
38816  *  0b0..VLAN Tag Input is disabled
38817  *  0b1..VLAN Tag Input is enabled
38818  */
38819 #define ENET_QOS_MAC_VLAN_INCL_VLTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
38820 
38821 #define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK         (0x200000U)
38822 #define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT        (21U)
38823 /*! CBTI - Channel based tag insertion
38824  *  0b0..Channel based tag insertion is disabled
38825  *  0b1..Channel based tag insertion is enabled
38826  */
38827 #define ENET_QOS_MAC_VLAN_INCL_CBTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
38828 
38829 #define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK         (0x7000000U)
38830 #define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT        (24U)
38831 /*! ADDR - Address
38832  */
38833 #define ENET_QOS_MAC_VLAN_INCL_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
38834 
38835 #define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK         (0x40000000U)
38836 #define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT        (30U)
38837 /*! RDWR - Read write control
38838  *  0b0..Read operation of indirect access
38839  *  0b1..Write operation of indirect access
38840  */
38841 #define ENET_QOS_MAC_VLAN_INCL_RDWR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
38842 
38843 #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK         (0x80000000U)
38844 #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT        (31U)
38845 /*! BUSY - Busy
38846  *  0b1..Busy status detected
38847  *  0b0..Busy status not detected
38848  */
38849 #define ENET_QOS_MAC_VLAN_INCL_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
38850 /*! @} */
38851 
38852 /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
38853 /*! @{ */
38854 
38855 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK    (0xFFFFU)
38856 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT   (0U)
38857 /*! VLT - VLAN Tag for Transmit Packets
38858  */
38859 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
38860 
38861 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK    (0x30000U)
38862 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT   (16U)
38863 /*! VLC - VLAN Tag Control in Transmit Packets
38864  *  0b01..VLAN tag deletion
38865  *  0b10..VLAN tag insertion
38866  *  0b00..No VLAN tag deletion, insertion, or replacement
38867  *  0b11..VLAN tag replacement
38868  */
38869 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
38870 
38871 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK    (0x40000U)
38872 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT   (18U)
38873 /*! VLP - VLAN Priority Control
38874  *  0b0..VLAN Priority Control is disabled
38875  *  0b1..VLAN Priority Control is enabled
38876  */
38877 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
38878 
38879 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK   (0x80000U)
38880 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT  (19U)
38881 /*! CSVL - C-VLAN or S-VLAN
38882  *  0b0..C-VLAN type (0x8100) is inserted
38883  *  0b1..S-VLAN type (0x88A8) is inserted
38884  */
38885 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
38886 
38887 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK   (0x100000U)
38888 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT  (20U)
38889 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
38890  *    replaced in Tx packet should be taken from: - The Tx descriptor
38891  *  0b0..VLAN Tag Input is disabled
38892  *  0b1..VLAN Tag Input is enabled
38893  */
38894 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
38895 /*! @} */
38896 
38897 /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
38898 /*! @{ */
38899 
38900 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
38901 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
38902 /*! FCB_BPA - Flow Control Busy or Backpressure Activate
38903  *  0b0..Flow Control Busy or Backpressure Activate is disabled
38904  *  0b1..Flow Control Busy or Backpressure Activate is enabled
38905  */
38906 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
38907 
38908 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK     (0x2U)
38909 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT    (1U)
38910 /*! TFE - Transmit Flow Control Enable
38911  *  0b0..Transmit Flow Control is disabled
38912  *  0b1..Transmit Flow Control is enabled
38913  */
38914 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
38915 
38916 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK     (0x70U)
38917 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT    (4U)
38918 /*! PLT - Pause Low Threshold
38919  *  0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
38920  *  0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
38921  *  0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
38922  *  0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
38923  *  0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
38924  *  0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
38925  *  0b110..Reserved
38926  */
38927 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
38928 
38929 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK    (0x80U)
38930 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT   (7U)
38931 /*! DZPQ - Disable Zero-Quanta Pause
38932  *  0b1..Zero-Quanta Pause packet generation is disabled
38933  *  0b0..Zero-Quanta Pause packet generation is enabled
38934  */
38935 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
38936 
38937 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK      (0xFFFF0000U)
38938 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT     (16U)
38939 /*! PT - Pause Time
38940  */
38941 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
38942 /*! @} */
38943 
38944 /* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
38945 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT        (5U)
38946 
38947 /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
38948 /*! @{ */
38949 
38950 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK       (0x1U)
38951 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT      (0U)
38952 /*! RFE - Receive Flow Control Enable
38953  *  0b0..Receive Flow Control is disabled
38954  *  0b1..Receive Flow Control is enabled
38955  */
38956 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
38957 
38958 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK        (0x2U)
38959 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT       (1U)
38960 /*! UP - Unicast Pause Packet Detect
38961  *  0b0..Unicast Pause Packet Detect disabled
38962  *  0b1..Unicast Pause Packet Detect enabled
38963  */
38964 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
38965 
38966 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK      (0x100U)
38967 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT     (8U)
38968 /*! PFCE - Priority Based Flow Control Enable
38969  *  0b0..Priority Based Flow Control is disabled
38970  *  0b1..Priority Based Flow Control is enabled
38971  */
38972 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
38973 /*! @} */
38974 
38975 /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
38976 /*! @{ */
38977 
38978 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK        (0x1U)
38979 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT       (0U)
38980 /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
38981  *  0b0..Unicast Address Filter Fail Packets Queuing is disabled
38982  *  0b1..Unicast Address Filter Fail Packets Queuing is enabled
38983  */
38984 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
38985 
38986 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK         (0xEU)
38987 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT        (1U)
38988 /*! UFFQ - Unicast Address Filter Fail Packets Queue.
38989  */
38990 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
38991 
38992 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK        (0x100U)
38993 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT       (8U)
38994 /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
38995  *  0b0..Multicast Address Filter Fail Packets Queuing is disabled
38996  *  0b1..Multicast Address Filter Fail Packets Queuing is enabled
38997  */
38998 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
38999 
39000 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK         (0xE00U)
39001 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT        (9U)
39002 /*! MFFQ - Multicast Address Filter Fail Packets Queue.
39003  */
39004 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
39005 
39006 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK        (0x10000U)
39007 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT       (16U)
39008 /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
39009  *  0b0..VLAN tag Filter Fail Packets Queuing is disabled
39010  *  0b1..VLAN tag Filter Fail Packets Queuing is enabled
39011  */
39012 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
39013 
39014 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK         (0xE0000U)
39015 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT        (17U)
39016 /*! VFFQ - VLAN Tag Filter Fail Packets Queue
39017  */
39018 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
39019 /*! @} */
39020 
39021 /*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
39022 /*! @{ */
39023 
39024 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK    (0xFFU)
39025 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT   (0U)
39026 /*! PSTQ0 - Priorities Selected in Transmit Queue 0
39027  */
39028 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
39029 
39030 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK    (0xFF00U)
39031 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT   (8U)
39032 /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
39033  */
39034 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
39035 
39036 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK    (0xFF0000U)
39037 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT   (16U)
39038 /*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit.
39039  */
39040 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
39041 
39042 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK    (0xFF000000U)
39043 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT   (24U)
39044 /*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit.
39045  */
39046 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
39047 /*! @} */
39048 
39049 /*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
39050 /*! @{ */
39051 
39052 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK    (0xFFU)
39053 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT   (0U)
39054 /*! PSTQ4 - Priorities Selected in Transmit Queue 4
39055  */
39056 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
39057 /*! @} */
39058 
39059 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
39060 /*! @{ */
39061 
39062 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK         (0x7U)
39063 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT        (0U)
39064 /*! AVCPQ - AV Untagged Control Packets Queue
39065  *  0b000..Receive Queue 0
39066  *  0b001..Receive Queue 1
39067  *  0b010..Receive Queue 2
39068  *  0b011..Receive Queue 3
39069  *  0b100..Receive Queue 4
39070  *  0b101..Reserved
39071  *  0b110..Reserved
39072  *  0b111..Reserved
39073  */
39074 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
39075 
39076 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK         (0xFFU)
39077 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT        (0U)
39078 /*! PSRQ0 - Priorities Selected in the Receive Queue 0
39079  */
39080 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
39081 
39082 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK         (0xFFU)
39083 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT        (0U)
39084 /*! PSRQ4 - Priorities Selected in the Receive Queue 4
39085  */
39086 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
39087 
39088 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK        (0x3U)
39089 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT       (0U)
39090 /*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
39091  *  0b00..Queue not enabled
39092  *  0b01..Queue enabled for AV
39093  *  0b10..Queue enabled for DCB/Generic
39094  *  0b11..Reserved
39095  */
39096 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
39097 
39098 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK        (0xCU)
39099 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT       (2U)
39100 /*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
39101  *  0b00..Queue not enabled
39102  *  0b01..Queue enabled for AV
39103  *  0b10..Queue enabled for DCB/Generic
39104  *  0b11..Reserved
39105  */
39106 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
39107 
39108 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK          (0x70U)
39109 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT         (4U)
39110 /*! PTPQ - PTP Packets Queue
39111  *  0b000..Receive Queue 0
39112  *  0b001..Receive Queue 1
39113  *  0b010..Receive Queue 2
39114  *  0b011..Receive Queue 3
39115  *  0b100..Receive Queue 4
39116  *  0b101..Reserved
39117  *  0b110..Reserved
39118  *  0b111..Reserved
39119  */
39120 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
39121 
39122 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK        (0x30U)
39123 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT       (4U)
39124 /*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
39125  *  0b00..Queue not enabled
39126  *  0b01..Queue enabled for AV
39127  *  0b10..Queue enabled for DCB/Generic
39128  *  0b11..Reserved
39129  */
39130 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
39131 
39132 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK        (0xC0U)
39133 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT       (6U)
39134 /*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
39135  *  0b00..Queue not enabled
39136  *  0b01..Queue enabled for AV
39137  *  0b10..Queue enabled for DCB/Generic
39138  *  0b11..Reserved
39139  */
39140 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
39141 
39142 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK        (0x700U)
39143 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT       (8U)
39144 /*! DCBCPQ - DCB Control Packets Queue
39145  *  0b000..Receive Queue 0
39146  *  0b001..Receive Queue 1
39147  *  0b010..Receive Queue 2
39148  *  0b011..Receive Queue 3
39149  *  0b100..Receive Queue 4
39150  *  0b101..Reserved
39151  *  0b110..Reserved
39152  *  0b111..Reserved
39153  */
39154 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
39155 
39156 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK         (0xFF00U)
39157 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT        (8U)
39158 /*! PSRQ1 - Priorities Selected in the Receive Queue 1
39159  */
39160 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
39161 
39162 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK        (0x300U)
39163 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT       (8U)
39164 /*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
39165  *  0b00..Queue not enabled
39166  *  0b01..Queue enabled for AV
39167  *  0b10..Queue enabled for DCB/Generic
39168  *  0b11..Reserved
39169  */
39170 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
39171 
39172 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK           (0x7000U)
39173 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT          (12U)
39174 /*! UPQ - Untagged Packet Queue
39175  *  0b000..Receive Queue 0
39176  *  0b001..Receive Queue 1
39177  *  0b010..Receive Queue 2
39178  *  0b011..Receive Queue 3
39179  *  0b100..Receive Queue 4
39180  *  0b101..Reserved
39181  *  0b110..Reserved
39182  *  0b111..Reserved
39183  */
39184 #define ENET_QOS_MAC_RXQ_CTRL_UPQ(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
39185 
39186 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK         (0x70000U)
39187 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT        (16U)
39188 /*! MCBCQ - Multicast and Broadcast Queue
39189  *  0b000..Receive Queue 0
39190  *  0b001..Receive Queue 1
39191  *  0b010..Receive Queue 2
39192  *  0b011..Receive Queue 3
39193  *  0b100..Receive Queue 4
39194  *  0b101..Reserved
39195  *  0b110..Reserved
39196  *  0b111..Reserved
39197  */
39198 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
39199 
39200 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK         (0xFF0000U)
39201 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT        (16U)
39202 /*! PSRQ2 - Priorities Selected in the Receive Queue 2
39203  */
39204 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
39205 
39206 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK       (0x100000U)
39207 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT      (20U)
39208 /*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
39209  *    packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
39210  *    to Rx Queue specified in MCBCQ field.
39211  *  0b0..Multicast and Broadcast Queue is disabled
39212  *  0b1..Multicast and Broadcast Queue is enabled
39213  */
39214 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
39215 
39216 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK        (0x200000U)
39217 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT       (21U)
39218 /*! TACPQE - Tagged AV Control Packets Queuing Enable.
39219  *  0b0..Tagged AV Control Packets Queuing is disabled
39220  *  0b1..Tagged AV Control Packets Queuing is enabled
39221  */
39222 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
39223 
39224 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK          (0xC00000U)
39225 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT         (22U)
39226 /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control.
39227  */
39228 #define ENET_QOS_MAC_RXQ_CTRL_TPQC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
39229 
39230 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK          (0x7000000U)
39231 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT         (24U)
39232 /*! FPRQ - Frame Preemption Residue Queue
39233  */
39234 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
39235 
39236 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK         (0xFF000000U)
39237 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT        (24U)
39238 /*! PSRQ3 - Priorities Selected in the Receive Queue 3
39239  */
39240 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
39241 /*! @} */
39242 
39243 /* The count of ENET_QOS_MAC_RXQ_CTRL */
39244 #define ENET_QOS_MAC_RXQ_CTRL_COUNT              (4U)
39245 
39246 /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
39247 /*! @{ */
39248 
39249 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
39250 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
39251 /*! RGSMIIIS - RGMII or SMII Interrupt Status
39252  *  0b1..RGMII or SMII Interrupt Status is active
39253  *  0b0..RGMII or SMII Interrupt Status is not active
39254  */
39255 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
39256 
39257 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
39258 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
39259 /*! PHYIS - PHY Interrupt
39260  *  0b1..PHY Interrupt detected
39261  *  0b0..PHY Interrupt not detected
39262  */
39263 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
39264 
39265 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
39266 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
39267 /*! PMTIS - PMT Interrupt Status
39268  *  0b1..PMT Interrupt status active
39269  *  0b0..PMT Interrupt status not active
39270  */
39271 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
39272 
39273 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
39274 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
39275 /*! LPIIS - LPI Interrupt Status
39276  *  0b1..LPI Interrupt status active
39277  *  0b0..LPI Interrupt status not active
39278  */
39279 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
39280 
39281 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
39282 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
39283 /*! MMCIS - MMC Interrupt Status
39284  *  0b1..MMC Interrupt status active
39285  *  0b0..MMC Interrupt status not active
39286  */
39287 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
39288 
39289 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
39290 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
39291 /*! MMCRXIS - MMC Receive Interrupt Status
39292  *  0b1..MMC Receive Interrupt status active
39293  *  0b0..MMC Receive Interrupt status not active
39294  */
39295 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
39296 
39297 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
39298 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
39299 /*! MMCTXIS - MMC Transmit Interrupt Status
39300  *  0b1..MMC Transmit Interrupt status active
39301  *  0b0..MMC Transmit Interrupt status not active
39302  */
39303 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
39304 
39305 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
39306 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
39307 /*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
39308  *  0b1..MMC Receive Checksum Offload Interrupt status active
39309  *  0b0..MMC Receive Checksum Offload Interrupt status not active
39310  */
39311 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
39312 
39313 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK  (0x1000U)
39314 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
39315 /*! TSIS - Timestamp Interrupt Status
39316  *  0b1..Timestamp Interrupt status active
39317  *  0b0..Timestamp Interrupt status not active
39318  */
39319 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
39320 
39321 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
39322 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
39323 /*! TXSTSIS - Transmit Status Interrupt
39324  *  0b1..Transmit Interrupt status active
39325  *  0b0..Transmit Interrupt status not active
39326  */
39327 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
39328 
39329 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
39330 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
39331 /*! RXSTSIS - Receive Status Interrupt
39332  *  0b1..Receive Interrupt status active
39333  *  0b0..Receive Interrupt status not active
39334  */
39335 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
39336 
39337 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
39338 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
39339 /*! FPEIS - Frame Preemption Interrupt Status
39340  *  0b1..Frame Preemption Interrupt status active
39341  *  0b0..Frame Preemption Interrupt status not active
39342  */
39343 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
39344 
39345 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
39346 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
39347 /*! MDIOIS - MDIO Interrupt Status
39348  *  0b1..MDIO Interrupt status active
39349  *  0b0..MDIO Interrupt status not active
39350  */
39351 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
39352 
39353 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
39354 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
39355 /*! MFTIS - MMC FPE Transmit Interrupt Status
39356  *  0b1..MMC FPE Transmit Interrupt status active
39357  *  0b0..MMC FPE Transmit Interrupt status not active
39358  */
39359 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
39360 
39361 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
39362 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
39363 /*! MFRIS - MMC FPE Receive Interrupt Status
39364  *  0b1..MMC FPE Receive Interrupt status active
39365  *  0b0..MMC FPE Receive Interrupt status not active
39366  */
39367 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
39368 /*! @} */
39369 
39370 /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
39371 /*! @{ */
39372 
39373 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
39374 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
39375 /*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
39376  *    interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
39377  *  0b0..RGMII or SMII Interrupt is disabled
39378  *  0b1..RGMII or SMII Interrupt is enabled
39379  */
39380 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
39381 
39382 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
39383 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
39384 /*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
39385  *    signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
39386  *  0b0..PHY Interrupt is disabled
39387  *  0b1..PHY Interrupt is enabled
39388  */
39389 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
39390 
39391 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
39392 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
39393 /*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
39394  *    signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
39395  *  0b0..PMT Interrupt is disabled
39396  *  0b1..PMT Interrupt is enabled
39397  */
39398 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
39399 
39400 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
39401 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
39402 /*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
39403  *    signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
39404  *  0b0..LPI Interrupt is disabled
39405  *  0b1..LPI Interrupt is enabled
39406  */
39407 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
39408 
39409 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK  (0x1000U)
39410 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
39411 /*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
39412  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
39413  *  0b0..Timestamp Interrupt is disabled
39414  *  0b1..Timestamp Interrupt is enabled
39415  */
39416 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
39417 
39418 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
39419 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
39420 /*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
39421  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
39422  *  0b0..Timestamp Status Interrupt is disabled
39423  *  0b1..Timestamp Status Interrupt is enabled
39424  */
39425 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
39426 
39427 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
39428 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
39429 /*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
39430  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
39431  *  0b0..Receive Status Interrupt is disabled
39432  *  0b1..Receive Status Interrupt is enabled
39433  */
39434 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
39435 
39436 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
39437 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
39438 /*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
39439  *    interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
39440  *  0b0..Frame Preemption Interrupt is disabled
39441  *  0b1..Frame Preemption Interrupt is enabled
39442  */
39443 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
39444 
39445 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
39446 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
39447 /*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
39448  *    when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
39449  *  0b0..MDIO Interrupt is disabled
39450  *  0b1..MDIO Interrupt is enabled
39451  */
39452 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
39453 /*! @} */
39454 
39455 /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
39456 /*! @{ */
39457 
39458 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK       (0x1U)
39459 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT      (0U)
39460 /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
39461  *    happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
39462  *    and JD bit is reset in the MAC_CONFIGURATION register.
39463  *  0b1..Transmit Jabber Timeout occurred
39464  *  0b0..No Transmit Jabber Timeout
39465  */
39466 #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
39467 
39468 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK     (0x2U)
39469 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT    (1U)
39470 /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
39471  *    indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
39472  *  0b1..No carrier
39473  *  0b0..Carrier is present
39474  */
39475 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
39476 
39477 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK     (0x4U)
39478 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT    (2U)
39479 /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
39480  *    indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
39481  *    signal was inactive for one or more transmission clock periods during packet transmission.
39482  *  0b1..Loss of carrier
39483  *  0b0..Carrier is present
39484  */
39485 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
39486 
39487 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK     (0x8U)
39488 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT    (3U)
39489 /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
39490  *    DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
39491  *    ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
39492  *    when Jumbo packet is enabled).
39493  *  0b1..Excessive deferral
39494  *  0b0..No Excessive deferral
39495  */
39496 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
39497 
39498 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK      (0x10U)
39499 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT     (4U)
39500 /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
39501  *    indicates that the packet transmission aborted because a collision occurred after the collision
39502  *    window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
39503  *    Extension in GMII mode).
39504  *  0b1..Late collision is sensed
39505  *  0b0..No collision
39506  */
39507 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
39508 
39509 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK     (0x20U)
39510 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT    (5U)
39511 /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
39512  *    bit indicates that the transmission aborted after 16 successive collisions while attempting
39513  *    to transmit the current packet.
39514  *  0b1..Excessive collision is sensed
39515  *  0b0..No collision
39516  */
39517 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
39518 
39519 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK       (0x100U)
39520 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT      (8U)
39521 /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
39522  *    bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
39523  *    MAC_CONFIGURATION register.
39524  *  0b1..Receive watchdog timed out
39525  *  0b0..No receive watchdog timeout
39526  */
39527 #define ENET_QOS_MAC_RX_TX_STATUS_RWT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
39528 /*! @} */
39529 
39530 /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
39531 /*! @{ */
39532 
39533 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
39534 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
39535 /*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
39536  *    receives the expected magic packet or remote wake-up packet.
39537  *  0b0..Power down is disabled
39538  *  0b1..Power down is enabled
39539  */
39540 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
39541 
39542 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
39543 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
39544 /*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
39545  *  0b0..Magic Packet is disabled
39546  *  0b1..Magic Packet is enabled
39547  */
39548 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
39549 
39550 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
39551 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
39552 /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
39553  *    generated when the MAC receives a remote wake-up packet.
39554  *  0b0..Remote wake-up packet is disabled
39555  *  0b1..Remote wake-up packet is enabled
39556  */
39557 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
39558 
39559 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
39560 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
39561 /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
39562  *    event is generated because of the reception of a magic packet.
39563  *  0b1..Magic packet is received
39564  *  0b0..No Magic packet is received
39565  */
39566 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
39567 
39568 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
39569 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
39570 /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
39571  *    management event is generated because of the reception of a remote wake-up packet.
39572  *  0b1..Remote wake-up packet is received
39573  *  0b0..Remote wake-up packet is received
39574  */
39575 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
39576 
39577 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
39578 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
39579 /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
39580  *    address recognition is detected as a remote wake-up packet.
39581  *  0b0..Global unicast is disabled
39582  *  0b1..Global unicast is enabled
39583  */
39584 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
39585 
39586 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
39587 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
39588 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
39589  *    MAC receiver drops all received frames until it receives the expected Wake-up frame.
39590  *  0b0..Remote Wake-up Packet Forwarding is disabled
39591  *  0b1..Remote Wake-up Packet Forwarding is enabled
39592  */
39593 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
39594 
39595 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
39596 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
39597 /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
39598  *    4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
39599  *    register pointer.
39600  */
39601 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
39602 
39603 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
39604 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
39605 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
39606  *    remote wake-up packet filter register pointer is reset to 3'b000.
39607  *  0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
39608  *  0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
39609  */
39610 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
39611 /*! @} */
39612 
39613 /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
39614 /*! @{ */
39615 
39616 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
39617 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
39618 /*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter.
39619  */
39620 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
39621 /*! @} */
39622 
39623 /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
39624 /*! @{ */
39625 
39626 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
39627 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
39628 /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
39629  *    entered the LPI state because of the setting of the LPIEN bit.
39630  *  0b1..Transmit LPI entry detected
39631  *  0b0..Transmit LPI entry not detected
39632  */
39633 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
39634 
39635 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
39636 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
39637 /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
39638  *    the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
39639  *  0b1..Transmit LPI exit detected
39640  *  0b0..Transmit LPI exit not detected
39641  */
39642 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
39643 
39644 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
39645 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
39646 /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
39647  *    an LPI pattern and entered the LPI state.
39648  *  0b1..Receive LPI entry detected
39649  *  0b0..Receive LPI entry not detected
39650  */
39651 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
39652 
39653 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
39654 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
39655 /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
39656  *    receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
39657  *    normal reception.
39658  *  0b1..Receive LPI exit detected
39659  *  0b0..Receive LPI exit not detected
39660  */
39661 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
39662 
39663 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
39664 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
39665 /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
39666  *    LPI pattern on the GMII or MII interface.
39667  *  0b1..Transmit LPI state detected
39668  *  0b0..Transmit LPI state not detected
39669  */
39670 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
39671 
39672 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
39673 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
39674 /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
39675  *    pattern on the GMII or MII interface.
39676  *  0b1..Receive LPI state detected
39677  *  0b0..Receive LPI state not detected
39678  */
39679 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
39680 
39681 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
39682 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
39683 /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
39684  *  0b0..LPI state is disabled
39685  *  0b1..LPI state is enabled
39686  */
39687 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
39688 
39689 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
39690 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
39691 /*! PLS - PHY Link Status This bit indicates the link status of the PHY.
39692  *  0b0..link is down
39693  *  0b1..link is okay (UP)
39694  */
39695 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
39696 
39697 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
39698 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
39699 /*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
39700  *    SMII Receive paths to be used for activating the LPI LS TIMER.
39701  *  0b0..PHY Link Status is disabled
39702  *  0b1..PHY Link Status is enabled
39703  */
39704 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
39705 
39706 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
39707 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
39708 /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
39709  *    out of the LPI mode on the Transmit side.
39710  *  0b0..LPI Tx Automate is disabled
39711  *  0b1..LPI Tx Automate is enabled
39712  */
39713 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
39714 
39715 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
39716 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
39717 /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
39718  *  0b0..LPI Timer is disabled
39719  *  0b1..LPI Timer is enabled
39720  */
39721 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
39722 
39723 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
39724 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
39725 /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
39726  *    sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
39727  *  0b0..LPI Tx Clock Stop is disabled
39728  *  0b1..LPI Tx Clock Stop is enabled
39729  */
39730 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
39731 /*! @} */
39732 
39733 /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
39734 /*! @{ */
39735 
39736 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
39737 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
39738 /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
39739  *    waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
39740  *    transmission.
39741  */
39742 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
39743 
39744 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
39745 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
39746 /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
39747  *    status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
39748  */
39749 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
39750 /*! @} */
39751 
39752 /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
39753 /*! @{ */
39754 
39755 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK  (0xFFFF8U)
39756 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
39757 /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
39758  *    mode, after it has transmitted all the frames.
39759  */
39760 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
39761 /*! @} */
39762 
39763 /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
39764 /*! @{ */
39765 
39766 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
39767 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
39768 /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
39769  */
39770 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
39771 /*! @} */
39772 
39773 /*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
39774 /*! @{ */
39775 
39776 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
39777 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
39778 /*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
39779  *    of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
39780  *    SGMII port.
39781  *  0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
39782  *  0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
39783  */
39784 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
39785 
39786 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
39787 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
39788 /*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
39789  *    configuration in the RGMII, SGMII, or SMII interface.
39790  *  0b0..Link down
39791  *  0b1..Link up
39792  */
39793 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
39794 
39795 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
39796 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
39797 /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
39798  *  0b1..Full-duplex mode
39799  *  0b0..Half-duplex mode
39800  */
39801 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
39802 
39803 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
39804 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
39805 /*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
39806  *  0b10..125 MHz
39807  *  0b00..2.5 MHz
39808  *  0b01..25 MHz
39809  *  0b11..Reserved
39810  */
39811 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
39812 
39813 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
39814 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
39815 /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
39816  *  0b1..Link up
39817  *  0b0..Link down
39818  */
39819 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
39820 /*! @} */
39821 
39822 /*! @name MAC_VERSION - MAC Version */
39823 /*! @{ */
39824 
39825 #define ENET_QOS_MAC_VERSION_SNPSVER_MASK        (0xFFU)
39826 #define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT       (0U)
39827 /*! SNPSVER - Synopsys-defined Version
39828  */
39829 #define ENET_QOS_MAC_VERSION_SNPSVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
39830 
39831 #define ENET_QOS_MAC_VERSION_USERVER_MASK        (0xFF00U)
39832 #define ENET_QOS_MAC_VERSION_USERVER_SHIFT       (8U)
39833 /*! USERVER - User-defined Version (8'h10)
39834  */
39835 #define ENET_QOS_MAC_VERSION_USERVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
39836 /*! @} */
39837 
39838 /*! @name MAC_DEBUG - MAC Debug */
39839 /*! @{ */
39840 
39841 #define ENET_QOS_MAC_DEBUG_RPESTS_MASK           (0x1U)
39842 #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT          (0U)
39843 /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
39844  *    the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
39845  *    Idle state.
39846  *  0b1..MAC GMII or MII Receive Protocol Engine Status detected
39847  *  0b0..MAC GMII or MII Receive Protocol Engine Status not detected
39848  */
39849 #define ENET_QOS_MAC_DEBUG_RPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
39850 
39851 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK         (0x6U)
39852 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT        (1U)
39853 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
39854  *    the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
39855  *    Controller module.
39856  */
39857 #define ENET_QOS_MAC_DEBUG_RFCFCSTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
39858 
39859 #define ENET_QOS_MAC_DEBUG_TPESTS_MASK           (0x10000U)
39860 #define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT          (16U)
39861 /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
39862  *    the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
39863  *    the Idle state.
39864  *  0b1..MAC GMII or MII Transmit Protocol Engine Status detected
39865  *  0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
39866  */
39867 #define ENET_QOS_MAC_DEBUG_TPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
39868 
39869 #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK           (0x60000U)
39870 #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT          (17U)
39871 /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
39872  *  0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
39873  *  0b00..Idle state
39874  *  0b11..Transferring input packet for transmission
39875  *  0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
39876  */
39877 #define ENET_QOS_MAC_DEBUG_TFCSTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
39878 /*! @} */
39879 
39880 /*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
39881 /*! @{ */
39882 
39883 #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK         (0x1U)
39884 #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT        (0U)
39885 /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
39886  *  0b1..10 or 100 Mbps support
39887  *  0b0..No 10 or 100 Mbps support
39888  */
39889 #define ENET_QOS_MAC_HW_FEAT_MIISEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
39890 
39891 #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK           (0x7U)
39892 #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT          (0U)
39893 /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
39894  *  0b011..16 Extended Rx VLAN Filters
39895  *  0b100..24 Extended Rx VLAN Filters
39896  *  0b101..32 Extended Rx VLAN Filters
39897  *  0b001..4 Extended Rx VLAN Filters
39898  *  0b010..8 Extended Rx VLAN Filters
39899  *  0b000..No Extended Rx VLAN Filters
39900  *  0b110..Reserved
39901  */
39902 #define ENET_QOS_MAC_HW_FEAT_NRVF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
39903 
39904 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK     (0x1FU)
39905 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT    (0U)
39906 /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
39907  *    bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
39908  *  0b00011..1024 bytes
39909  *  0b00000..128 bytes
39910  *  0b01010..128 KB
39911  *  0b00111..16384 bytes
39912  *  0b00100..2048 bytes
39913  *  0b00001..256 bytes
39914  *  0b01011..256 KB
39915  *  0b01000..32 KB
39916  *  0b00101..4096 bytes
39917  *  0b00010..512 bytes
39918  *  0b01001..64 KB
39919  *  0b00110..8192 bytes
39920  *  0b01100..Reserved
39921  */
39922 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
39923 
39924 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK         (0xFU)
39925 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT        (0U)
39926 /*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
39927  *  0b0000..1 MTL Rx Queue
39928  *  0b0001..2 MTL Rx Queues
39929  *  0b0010..3 MTL Rx Queues
39930  *  0b0011..4 MTL Rx Queues
39931  *  0b0100..5 MTL Rx Queues
39932  *  0b0101..Reserved
39933  *  0b0110..Reserved
39934  *  0b0111..Reserved
39935  */
39936 #define ENET_QOS_MAC_HW_FEAT_RXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
39937 
39938 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK        (0x2U)
39939 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT       (1U)
39940 /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
39941  *  0b1..1000 Mbps support
39942  *  0b0..No 1000 Mbps support
39943  */
39944 #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
39945 
39946 #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK          (0x4U)
39947 #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT         (2U)
39948 /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
39949  *  0b1..Half-duplex support
39950  *  0b0..No Half-duplex support
39951  */
39952 #define ENET_QOS_MAC_HW_FEAT_HDSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
39953 
39954 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK         (0x8U)
39955 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT        (3U)
39956 /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
39957  *    SGMII, or RTBI PHY interface option is selected
39958  *  0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
39959  *  0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
39960  */
39961 #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
39962 
39963 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK        (0x10U)
39964 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT       (4U)
39965 /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
39966  *    Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
39967  *  0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
39968  *  0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
39969  */
39970 #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
39971 
39972 #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK         (0x10U)
39973 #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT        (4U)
39974 /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
39975  *  0b1..VLAN Hash Filter selected
39976  *  0b0..VLAN Hash Filter not selected
39977  */
39978 #define ENET_QOS_MAC_HW_FEAT_VLHASH(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
39979 
39980 #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK          (0x20U)
39981 #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT         (5U)
39982 /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
39983  *  0b1..Double VLAN option is selected
39984  *  0b0..Double VLAN option is not selected
39985  */
39986 #define ENET_QOS_MAC_HW_FEAT_DVLAN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
39987 
39988 #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK         (0x20U)
39989 #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT        (5U)
39990 /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
39991  *  0b1..SMA (MDIO) Interface selected
39992  *  0b0..SMA (MDIO) Interface not selected
39993  */
39994 #define ENET_QOS_MAC_HW_FEAT_SMASEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
39995 
39996 #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK          (0x20U)
39997 #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT         (5U)
39998 /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
39999  *  0b1..Single Port RAM feature is selected
40000  *  0b0..Single Port RAM feature is not selected
40001  */
40002 #define ENET_QOS_MAC_HW_FEAT_SPRAM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
40003 
40004 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK         (0x40U)
40005 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT        (6U)
40006 /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
40007  *  0b1..PMT Remote Wake-up Packet Enable option is selected
40008  *  0b0..PMT Remote Wake-up Packet Enable option is not selected
40009  */
40010 #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
40011 
40012 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK     (0x7C0U)
40013 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT    (6U)
40014 /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
40015  *    bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
40016  *  0b00011..1024 bytes
40017  *  0b00000..128 bytes
40018  *  0b01010..128 KB
40019  *  0b00111..16384 bytes
40020  *  0b00100..2048 bytes
40021  *  0b00001..256 bytes
40022  *  0b01000..32 KB
40023  *  0b00101..4096 bytes
40024  *  0b00010..512 bytes
40025  *  0b01001..64 KB
40026  *  0b00110..8192 bytes
40027  *  0b01011..Reserved
40028  */
40029 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
40030 
40031 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK         (0x3C0U)
40032 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT        (6U)
40033 /*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
40034  *  0b0000..1 MTL Tx Queue
40035  *  0b0001..2 MTL Tx Queues
40036  *  0b0010..3 MTL Tx Queues
40037  *  0b0011..4 MTL Tx Queues
40038  *  0b0100..5 MTL Tx Queues
40039  *  0b0101..Reserved
40040  *  0b0110..Reserved
40041  *  0b0111..Reserved
40042  */
40043 #define ENET_QOS_MAC_HW_FEAT_TXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
40044 
40045 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK         (0x80U)
40046 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT        (7U)
40047 /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
40048  *  0b1..PMT Magic Packet Enable option is selected
40049  *  0b0..PMT Magic Packet Enable option is not selected
40050  */
40051 #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
40052 
40053 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK         (0x100U)
40054 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT        (8U)
40055 /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
40056  *  0b1..RMON Module Enable option is selected
40057  *  0b0..RMON Module Enable option is not selected
40058  */
40059 #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
40060 
40061 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK      (0x200U)
40062 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT     (9U)
40063 /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
40064  *  0b1..ARP Offload Enable option is selected
40065  *  0b0..ARP Offload Enable option is not selected
40066  */
40067 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
40068 
40069 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK        (0x200U)
40070 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT       (9U)
40071 /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
40072  *    Broadcast/Multicast Packet Duplication feature is selected.
40073  *  0b1..Broadcast/Multicast Packet Duplication feature is selected
40074  *  0b0..Broadcast/Multicast Packet Duplication feature is not selected
40075  */
40076 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
40077 
40078 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK         (0x400U)
40079 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT        (10U)
40080 /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
40081  *    Programmable Receive Parser option is selected.
40082  *  0b1..Flexible Receive Parser feature is selected
40083  *  0b0..Flexible Receive Parser feature is not selected
40084  */
40085 #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
40086 
40087 #define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK          (0x1800U)
40088 #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT         (11U)
40089 /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
40090  *    bytes of the packet data to be Parsed by Flexible Receive Parser.
40091  *  0b01..128 Bytes
40092  *  0b10..256 Bytes
40093  *  0b00..64 Bytes
40094  *  0b11..Reserved
40095  */
40096 #define ENET_QOS_MAC_HW_FEAT_FRPBS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
40097 
40098 #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK          (0x800U)
40099 #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT         (11U)
40100 /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
40101  *  0b1..One-Step Timestamping feature is selected
40102  *  0b0..One-Step Timestamping feature is not selected
40103  */
40104 #define ENET_QOS_MAC_HW_FEAT_OSTEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
40105 
40106 #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK          (0x1000U)
40107 #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT         (12U)
40108 /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
40109  *  0b1..PTP Offload feature is selected
40110  *  0b0..PTP Offload feature is not selected
40111  */
40112 #define ENET_QOS_MAC_HW_FEAT_PTOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
40113 
40114 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK        (0xF000U)
40115 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT       (12U)
40116 /*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
40117  *  0b0000..1 MTL Rx Channel
40118  *  0b0001..2 MTL Rx Channels
40119  *  0b0010..3 MTL Rx Channels
40120  *  0b0011..4 MTL Rx Channels
40121  *  0b0100..5 MTL Rx Channels
40122  *  0b0101..Reserved
40123  *  0b0110..Reserved
40124  *  0b0111..Reserved
40125  */
40126 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
40127 
40128 #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK          (0x1000U)
40129 #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT         (12U)
40130 /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
40131  *  0b1..IEEE 1588-2008 Timestamp Enable option is selected
40132  *  0b0..IEEE 1588-2008 Timestamp Enable option is not selected
40133  */
40134 #define ENET_QOS_MAC_HW_FEAT_TSSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
40135 
40136 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK      (0x2000U)
40137 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT     (13U)
40138 /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
40139  *  0b1..IEEE 1588 High Word Register option is selected
40140  *  0b0..IEEE 1588 High Word Register option is not selected
40141  */
40142 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
40143 
40144 #define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK         (0x2000U)
40145 #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT        (13U)
40146 /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
40147  *    Ethernet (EEE) option is selected
40148  *  0b1..Energy Efficient Ethernet Enable option is selected
40149  *  0b0..Energy Efficient Ethernet Enable option is not selected
40150  */
40151 #define ENET_QOS_MAC_HW_FEAT_EEESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
40152 
40153 #define ENET_QOS_MAC_HW_FEAT_FRPES_MASK          (0x6000U)
40154 #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT         (13U)
40155 /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
40156  *    Entries supported by Flexible Receive Parser.
40157  *  0b01..128 Entries
40158  *  0b10..256 Entries
40159  *  0b00..64 Entries
40160  *  0b11..Reserved
40161  */
40162 #define ENET_QOS_MAC_HW_FEAT_FRPES(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
40163 
40164 #define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK         (0xC000U)
40165 #define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT        (14U)
40166 /*! ADDR64 - Address Width.
40167  *  0b00..32
40168  *  0b01..40
40169  *  0b10..48
40170  *  0b11..Reserved
40171  */
40172 #define ENET_QOS_MAC_HW_FEAT_ADDR64(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
40173 
40174 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK       (0x4000U)
40175 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT      (14U)
40176 /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
40177  *    TCP/IP Checksum Insertion option is selected
40178  *  0b1..Transmit Checksum Offload Enable option is selected
40179  *  0b0..Transmit Checksum Offload Enable option is not selected
40180  */
40181 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
40182 
40183 #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK          (0x10000U)
40184 #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT         (16U)
40185 /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
40186  *  0b1..DCB Feature is selected
40187  *  0b0..DCB Feature is not selected
40188  */
40189 #define ENET_QOS_MAC_HW_FEAT_DCBEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
40190 
40191 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK         (0x10000U)
40192 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT        (16U)
40193 /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
40194  *    Enhancements to Scheduling Traffic feature is selected.
40195  *  0b1..Enable Enhancements to Scheduling Traffic feature is selected
40196  *  0b0..Enable Enhancements to Scheduling Traffic feature is not selected
40197  */
40198 #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
40199 
40200 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK       (0x10000U)
40201 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT      (16U)
40202 /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
40203  *  0b1..Receive Checksum Offload Enable option is selected
40204  *  0b0..Receive Checksum Offload Enable option is not selected
40205  */
40206 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
40207 
40208 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK         (0xE0000U)
40209 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT        (17U)
40210 /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
40211  *  0b101..1024
40212  *  0b010..128
40213  *  0b011..256
40214  *  0b100..512
40215  *  0b001..64
40216  *  0b000..No Depth configured
40217  *  0b110..Reserved
40218  */
40219 #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
40220 
40221 #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK          (0x20000U)
40222 #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT         (17U)
40223 /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
40224  *  0b1..Split Header Feature is selected
40225  *  0b0..Split Header Feature is not selected
40226  */
40227 #define ENET_QOS_MAC_HW_FEAT_SPHEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
40228 
40229 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK   (0x7C0000U)
40230 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT  (18U)
40231 /*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
40232  *    selected for Enable Additional 1-31 MAC Address Registers option
40233  */
40234 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
40235 
40236 #define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK          (0x40000U)
40237 #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT         (18U)
40238 /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
40239  *    Offloading for TCP/IP Packets option is selected
40240  *  0b1..TCP Segmentation Offload Feature is selected
40241  *  0b0..TCP Segmentation Offload Feature is not selected
40242  */
40243 #define ENET_QOS_MAC_HW_FEAT_TSOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
40244 
40245 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK        (0x3C0000U)
40246 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT       (18U)
40247 /*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
40248  *  0b0000..1 MTL Tx Channel
40249  *  0b0001..2 MTL Tx Channels
40250  *  0b0010..3 MTL Tx Channels
40251  *  0b0011..4 MTL Tx Channels
40252  *  0b0100..5 MTL Tx Channels
40253  *  0b0101..Reserved
40254  *  0b0110..Reserved
40255  *  0b0111..Reserved
40256  */
40257 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
40258 
40259 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK        (0x80000U)
40260 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT       (19U)
40261 /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
40262  *  0b1..DMA Debug Registers option is selected
40263  *  0b0..DMA Debug Registers option is not selected
40264  */
40265 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
40266 
40267 #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK          (0x100000U)
40268 #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT         (20U)
40269 /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
40270  *  0b1..AV Feature is selected
40271  *  0b0..AV Feature is not selected
40272  */
40273 #define ENET_QOS_MAC_HW_FEAT_AVSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
40274 
40275 #define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK         (0x300000U)
40276 #define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT        (20U)
40277 /*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
40278  *    width of the Configured Time Interval Field
40279  *  0b00..Width not configured
40280  *  0b01..16
40281  *  0b10..20
40282  *  0b11..24
40283  */
40284 #define ENET_QOS_MAC_HW_FEAT_ESTWID(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
40285 
40286 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK         (0x200000U)
40287 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT        (21U)
40288 /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
40289  *    Bridging option on Rx Side Only is selected.
40290  *  0b1..Rx Side Only AV Feature is selected
40291  *  0b0..Rx Side Only AV Feature is not selected
40292  */
40293 #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
40294 
40295 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK    (0x800000U)
40296 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT   (23U)
40297 /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
40298  *    MAC Address Registers (32-63) option is selected
40299  *  0b1..MAC Addresses 32-63 Select option is selected
40300  *  0b0..MAC Addresses 32-63 Select option is not selected
40301  */
40302 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
40303 
40304 #define ENET_QOS_MAC_HW_FEAT_POUOST_MASK         (0x800000U)
40305 #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT        (23U)
40306 /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
40307  *    step timestamp for PTP over UDP/IP feature is selected.
40308  *  0b1..One Step for PTP over UDP/IP Feature is selected
40309  *  0b0..One Step for PTP over UDP/IP Feature is not selected
40310  */
40311 #define ENET_QOS_MAC_HW_FEAT_POUOST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
40312 
40313 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK      (0x3000000U)
40314 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT     (24U)
40315 /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
40316  *  0b10..128
40317  *  0b11..256
40318  *  0b01..64
40319  *  0b00..No hash table
40320  */
40321 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
40322 
40323 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK    (0x1000000U)
40324 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT   (24U)
40325 /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
40326  *    MAC Address Registers (64-127) option is selected
40327  *  0b1..MAC Addresses 64-127 Select option is selected
40328  *  0b0..MAC Addresses 64-127 Select option is not selected
40329  */
40330 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
40331 
40332 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK      (0x7000000U)
40333 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT     (24U)
40334 /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
40335  *  0b001..1 PPS output
40336  *  0b010..2 PPS output
40337  *  0b011..3 PPS output
40338  *  0b100..4 PPS output
40339  *  0b000..No PPS output
40340  *  0b101..Reserved
40341  */
40342 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
40343 
40344 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK       (0x6000000U)
40345 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT      (25U)
40346 /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
40347  *    time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
40348  *  0b10..Both
40349  *  0b01..External
40350  *  0b00..Internal
40351  *  0b11..Reserved
40352  */
40353 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
40354 
40355 #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK         (0x4000000U)
40356 #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT        (26U)
40357 /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
40358  *  0b1..Frame Preemption Enable feature is selected
40359  *  0b0..Frame Preemption Enable feature is not selected
40360  */
40361 #define ENET_QOS_MAC_HW_FEAT_FPESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
40362 
40363 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK       (0x78000000U)
40364 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT      (27U)
40365 /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
40366  *  0b0001..1 L3 or L4 Filter
40367  *  0b0010..2 L3 or L4 Filters
40368  *  0b0011..3 L3 or L4 Filters
40369  *  0b0100..4 L3 or L4 Filters
40370  *  0b0101..5 L3 or L4 Filters
40371  *  0b0110..6 L3 or L4 Filters
40372  *  0b0111..7 L3 or L4 Filters
40373  *  0b1000..8 L3 or L4 Filters
40374  *  0b0000..No L3 or L4 Filter
40375  */
40376 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
40377 
40378 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK      (0x8000000U)
40379 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT     (27U)
40380 /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
40381  *    VLAN Insertion on Tx option is selected
40382  *  0b1..Source Address or VLAN Insertion Enable option is selected
40383  *  0b0..Source Address or VLAN Insertion Enable option is not selected
40384  */
40385 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
40386 
40387 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK         (0x8000000U)
40388 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT        (27U)
40389 /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
40390  *  0b1..Time Based Scheduling Enable feature is selected
40391  *  0b0..Time Based Scheduling Enable feature is not selected
40392  */
40393 #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
40394 
40395 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK      (0x70000000U)
40396 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT     (28U)
40397 /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
40398  *    this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
40399  *  0b000..GMII or MII
40400  *  0b111..RevMII
40401  *  0b001..RGMII
40402  *  0b100..RMII
40403  *  0b101..RTBI
40404  *  0b010..SGMII
40405  *  0b110..SMII
40406  *  0b011..TBI
40407  */
40408 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
40409 
40410 #define ENET_QOS_MAC_HW_FEAT_ASP_MASK            (0x30000000U)
40411 #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT           (28U)
40412 /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
40413  *  0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
40414  *  0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
40415  *  0b01..Only "ECC protection for external memory" feature is selected
40416  *  0b00..No Safety features selected
40417  */
40418 #define ENET_QOS_MAC_HW_FEAT_ASP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
40419 
40420 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK     (0x70000000U)
40421 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT    (28U)
40422 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
40423  *  0b001..1 auxiliary input
40424  *  0b010..2 auxiliary input
40425  *  0b011..3 auxiliary input
40426  *  0b100..4 auxiliary input
40427  *  0b000..No auxiliary input
40428  *  0b101..Reserved
40429  */
40430 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
40431 /*! @} */
40432 
40433 /* The count of ENET_QOS_MAC_HW_FEAT */
40434 #define ENET_QOS_MAC_HW_FEAT_COUNT               (4U)
40435 
40436 /*! @name MAC_MDIO_ADDRESS - MDIO Address */
40437 /*! @{ */
40438 
40439 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK        (0x1U)
40440 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT       (0U)
40441 /*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
40442  *  0b0..GMII Busy is disabled
40443  *  0b1..GMII Busy is enabled
40444  */
40445 #define ENET_QOS_MAC_MDIO_ADDRESS_GB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
40446 
40447 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK      (0x2U)
40448 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT     (1U)
40449 /*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
40450  *  0b0..Clause 45 PHY is disabled
40451  *  0b1..Clause 45 PHY is enabled
40452  */
40453 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
40454 
40455 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK     (0x4U)
40456 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT    (2U)
40457 /*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
40458  *  0b0..GMII Operation Command 0 is disabled
40459  *  0b1..GMII Operation Command 0 is enabled
40460  */
40461 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
40462 
40463 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK     (0x8U)
40464 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT    (3U)
40465 /*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
40466  *    RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
40467  *    Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
40468  *    and Read commands are valid.
40469  *  0b0..GMII Operation Command 1 is disabled
40470  *  0b1..GMII Operation Command 1 is enabled
40471  */
40472 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
40473 
40474 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK      (0x10U)
40475 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT     (4U)
40476 /*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
40477  *    before read, write, or post-read increment address packets.
40478  *  0b0..Skip Address Packet is disabled
40479  *  0b1..Skip Address Packet is enabled
40480  */
40481 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
40482 
40483 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK        (0xF00U)
40484 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT       (8U)
40485 /*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
40486  *    according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
40487  *    clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
40488  *    = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
40489  *    - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
40490  *    MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
40491  *    clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
40492  *    applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
40493  */
40494 #define ENET_QOS_MAC_MDIO_ADDRESS_CR(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
40495 
40496 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK       (0x7000U)
40497 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT      (12U)
40498 /*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
40499  *    generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
40500  */
40501 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
40502 
40503 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK       (0x1F0000U)
40504 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT      (16U)
40505 /*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device.
40506  */
40507 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
40508 
40509 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK        (0x3E00000U)
40510 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT       (21U)
40511 /*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing.
40512  */
40513 #define ENET_QOS_MAC_MDIO_ADDRESS_PA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
40514 
40515 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK       (0x4000000U)
40516 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT      (26U)
40517 /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
40518  *    the MAC informs the completion of a read or write command at the end of frame transfer (before
40519  *    the trailing clocks are transmitted).
40520  *  0b0..Back to Back transactions disabled
40521  *  0b1..Back to Back transactions enabled
40522  */
40523 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
40524 
40525 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK       (0x8000000U)
40526 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT      (27U)
40527 /*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
40528  *    and transmits MDIO frames with only 1 preamble bit.
40529  *  0b0..Preamble Suppression disabled
40530  *  0b1..Preamble Suppression enabled
40531  */
40532 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
40533 /*! @} */
40534 
40535 /*! @name MAC_MDIO_DATA - MAC MDIO Data */
40536 /*! @{ */
40537 
40538 #define ENET_QOS_MAC_MDIO_DATA_GD_MASK           (0xFFFFU)
40539 #define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT          (0U)
40540 /*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
40541  *    Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
40542  *    Management Write operation.
40543  */
40544 #define ENET_QOS_MAC_MDIO_DATA_GD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
40545 
40546 #define ENET_QOS_MAC_MDIO_DATA_RA_MASK           (0xFFFF0000U)
40547 #define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT          (16U)
40548 /*! RA - Register Address This field is valid only when C45E is set.
40549  */
40550 #define ENET_QOS_MAC_MDIO_DATA_RA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
40551 /*! @} */
40552 
40553 /*! @name MAC_CSR_SW_CTRL - CSR Software Control */
40554 /*! @{ */
40555 
40556 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK       (0x1U)
40557 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT      (0U)
40558 /*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
40559  *    fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
40560  *    clear it.
40561  *  0b0..Register Clear on Write 1 is disabled
40562  *  0b1..Register Clear on Write 1 is enabled
40563  */
40564 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
40565 /*! @} */
40566 
40567 /*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
40568 /*! @{ */
40569 
40570 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK      (0x1U)
40571 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT     (0U)
40572 /*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
40573  *  0b0..Tx Frame Preemption is disabled
40574  *  0b1..Tx Frame Preemption is enabled
40575  */
40576 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
40577 
40578 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK      (0x2U)
40579 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT     (1U)
40580 /*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
40581  *  0b0..Send Verify mPacket is disabled
40582  *  0b1..Send Verify mPacket is enabled
40583  */
40584 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
40585 
40586 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK      (0x4U)
40587 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT     (2U)
40588 /*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
40589  *  0b0..Send Respond mPacket is disabled
40590  *  0b1..Send Respond mPacket is enabled
40591  */
40592 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
40593 
40594 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK  (0x8U)
40595 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
40596 /*! S1_SET_0 - Synopsys Reserved, Must be set to "0".
40597  */
40598 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
40599 
40600 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK      (0x10000U)
40601 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT     (16U)
40602 /*! RVER - Received Verify Frame Set when a Verify mPacket is received.
40603  *  0b1..Received Verify Frame
40604  *  0b0..Not received Verify Frame
40605  */
40606 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
40607 
40608 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK      (0x20000U)
40609 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT     (17U)
40610 /*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
40611  *  0b1..Received Respond Frame
40612  *  0b0..Not received Respond Frame
40613  */
40614 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
40615 
40616 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK      (0x40000U)
40617 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT     (18U)
40618 /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
40619  *  0b1..transmitted Verify Frame
40620  *  0b0..Not transmitted Verify Frame
40621  */
40622 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
40623 
40624 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK      (0x80000U)
40625 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT     (19U)
40626 /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
40627  *  0b1..transmitted Respond Frame
40628  *  0b0..Not transmitted Respond Frame
40629  */
40630 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
40631 /*! @} */
40632 
40633 /*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
40634 /*! @{ */
40635 
40636 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK     (0xFFFFFFFFU)
40637 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT    (0U)
40638 /*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
40639  *    rollover equivalent time of the PTP System Time in ns
40640  */
40641 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
40642 /*! @} */
40643 
40644 /*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
40645 /*! @{ */
40646 
40647 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK   (0xFFFFFFFFU)
40648 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT  (0U)
40649 /*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time.
40650  */
40651 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
40652 /*! @} */
40653 
40654 /*! @name HIGH - MAC Address0 High..MAC Address63 High */
40655 /*! @{ */
40656 
40657 #define ENET_QOS_HIGH_ADDRHI_MASK                (0xFFFFU)
40658 #define ENET_QOS_HIGH_ADDRHI_SHIFT               (0U)
40659 /*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address.
40660  */
40661 #define ENET_QOS_HIGH_ADDRHI(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
40662 
40663 #define ENET_QOS_HIGH_DCS_MASK                   (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
40664 #define ENET_QOS_HIGH_DCS_SHIFT                  (16U)
40665 /*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
40666  *    contains the binary representation of the DMA Channel number to which an Rx packet whose DA
40667  *    matches the MAC Address(#i) content is routed.
40668  */
40669 #define ENET_QOS_HIGH_DCS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
40670 
40671 #define ENET_QOS_HIGH_MBC_MASK                   (0x3F000000U)
40672 #define ENET_QOS_HIGH_MBC_SHIFT                  (24U)
40673 /*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes.
40674  */
40675 #define ENET_QOS_HIGH_MBC(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
40676 
40677 #define ENET_QOS_HIGH_SA_MASK                    (0x40000000U)
40678 #define ENET_QOS_HIGH_SA_SHIFT                   (30U)
40679 /*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
40680  *    fields of the received packet.
40681  *  0b0..Compare with Destination Address
40682  *  0b1..Compare with Source Address
40683  */
40684 #define ENET_QOS_HIGH_SA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
40685 
40686 #define ENET_QOS_HIGH_AE_MASK                    (0x80000000U)
40687 #define ENET_QOS_HIGH_AE_SHIFT                   (31U)
40688 /*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
40689  *  0b0..INVALID : This bit must be always set to 1
40690  *  0b1..This bit is always set to 1
40691  */
40692 #define ENET_QOS_HIGH_AE(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
40693 /*! @} */
40694 
40695 /* The count of ENET_QOS_HIGH */
40696 #define ENET_QOS_HIGH_COUNT                      (64U)
40697 
40698 /*! @name LOW - MAC Address0 Low..MAC Address63 Low */
40699 /*! @{ */
40700 
40701 #define ENET_QOS_LOW_ADDRLO_MASK                 (0xFFFFFFFFU)
40702 #define ENET_QOS_LOW_ADDRLO_SHIFT                (0U)
40703 /*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address.
40704  */
40705 #define ENET_QOS_LOW_ADDRLO(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
40706 /*! @} */
40707 
40708 /* The count of ENET_QOS_LOW */
40709 #define ENET_QOS_LOW_COUNT                       (64U)
40710 
40711 /*! @name MAC_MMC_CONTROL - MMC Control */
40712 /*! @{ */
40713 
40714 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK     (0x1U)
40715 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT    (0U)
40716 /*! CNTRST - Counters Reset When this bit is set, all counters are reset.
40717  *  0b0..Counters are not reset
40718  *  0b1..All counters are reset
40719  */
40720 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
40721 
40722 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK  (0x2U)
40723 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
40724 /*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
40725  *  0b0..Counter Stop Rollover is disabled
40726  *  0b1..Counter Stop Rollover is enabled
40727  */
40728 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
40729 
40730 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK    (0x4U)
40731 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT   (2U)
40732 /*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
40733  *  0b0..Reset on Read is disabled
40734  *  0b1..Reset on Read is enabled
40735  */
40736 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
40737 
40738 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK   (0x8U)
40739 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT  (3U)
40740 /*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
40741  *  0b0..MMC Counter Freeze is disabled
40742  *  0b1..MMC Counter Freeze is enabled
40743  */
40744 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
40745 
40746 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK    (0x10U)
40747 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT   (4U)
40748 /*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
40749  *    full or almost half according to the CNTPRSTLVL bit.
40750  *  0b0..Counters Preset is disabled
40751  *  0b1..Counters Preset is enabled
40752  */
40753 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
40754 
40755 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
40756 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
40757 /*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
40758  *  0b0..Full-Half Preset is disabled
40759  *  0b1..Full-Half Preset is enabled
40760  */
40761 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
40762 
40763 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK      (0x100U)
40764 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT     (8U)
40765 /*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
40766  *  0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
40767  *  0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
40768  */
40769 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
40770 /*! @} */
40771 
40772 /*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
40773 /*! @{ */
40774 
40775 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
40776 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
40777 /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
40778  *    rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
40779  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
40780  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
40781  */
40782 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
40783 
40784 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
40785 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
40786 /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
40787  *    rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
40788  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
40789  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
40790  */
40791 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
40792 
40793 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
40794 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
40795 /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
40796  *    rxoctetcount_g counter reaches half of the maximum value or the maximum value.
40797  *  0b1..MMC Receive Good Octet Counter Interrupt Status detected
40798  *  0b0..MMC Receive Good Octet Counter Interrupt Status not detected
40799  */
40800 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
40801 
40802 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
40803 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
40804 /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
40805  *    rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
40806  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
40807  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
40808  */
40809 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
40810 
40811 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
40812 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
40813 /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
40814  *    rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
40815  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
40816  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
40817  */
40818 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
40819 
40820 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
40821 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
40822 /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
40823  *    rxcrcerror counter reaches half of the maximum value or the maximum value.
40824  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
40825  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
40826  */
40827 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
40828 
40829 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
40830 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
40831 /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
40832  *    the rxalignmenterror counter reaches half of the maximum value or the maximum value.
40833  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
40834  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
40835  */
40836 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
40837 
40838 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
40839 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
40840 /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
40841  *    rxrunterror counter reaches half of the maximum value or the maximum value.
40842  *  0b1..MMC Receive Runt Packet Counter Interrupt Status detected
40843  *  0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
40844  */
40845 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
40846 
40847 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
40848 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
40849 /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
40850  *    rxjabbererror counter reaches half of the maximum value or the maximum value.
40851  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
40852  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
40853  */
40854 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
40855 
40856 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
40857 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
40858 /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
40859  *    the rxundersize_g counter reaches half of the maximum value or the maximum value.
40860  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
40861  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
40862  */
40863 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
40864 
40865 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
40866 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
40867 /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
40868  *    rxoversize_g counter reaches half of the maximum value or the maximum value.
40869  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
40870  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
40871  */
40872 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
40873 
40874 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
40875 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
40876 /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
40877  *    when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
40878  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
40879  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
40880  */
40881 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
40882 
40883 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
40884 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
40885 /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
40886  *    is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
40887  *    value.
40888  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
40889  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
40890  */
40891 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
40892 
40893 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
40894 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
40895 /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
40896  *    bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
40897  *    maximum value.
40898  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
40899  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
40900  */
40901 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
40902 
40903 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
40904 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
40905 /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
40906  *    bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
40907  *    maximum value.
40908  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
40909  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
40910  */
40911 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
40912 
40913 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
40914 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
40915 /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
40916  *    bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
40917  *    maximum value.
40918  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
40919  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
40920  */
40921 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
40922 
40923 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
40924 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
40925 /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
40926  *    This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
40927  *    maximum value.
40928  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
40929  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
40930  */
40931 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
40932 
40933 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
40934 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
40935 /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
40936  *    rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
40937  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
40938  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
40939  */
40940 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
40941 
40942 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
40943 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
40944 /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
40945  *    rxlengtherror counter reaches half of the maximum value or the maximum value.
40946  *  0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
40947  *  0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
40948  */
40949 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
40950 
40951 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
40952 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
40953 /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
40954  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
40955  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
40956  */
40957 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
40958 
40959 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
40960 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
40961 /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
40962  *    rxpausepackets counter reaches half of the maximum value or the maximum value.
40963  *  0b1..MMC Receive Pause Packet Counter Interrupt Status detected
40964  *  0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
40965  */
40966 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
40967 
40968 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
40969 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
40970 /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
40971  *    rxfifooverflow counter reaches half of the maximum value or the maximum value.
40972  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
40973  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
40974  */
40975 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
40976 
40977 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
40978 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
40979 /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
40980  *    rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
40981  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
40982  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
40983  */
40984 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
40985 
40986 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
40987 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
40988 /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
40989  *    rxwatchdog error counter reaches half of the maximum value or the maximum value.
40990  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
40991  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
40992  */
40993 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
40994 
40995 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
40996 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
40997 /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
40998  *    rxrcverror counter reaches half of the maximum value or the maximum value.
40999  *  0b1..MMC Receive Error Packet Counter Interrupt Status detected
41000  *  0b0..MMC Receive Error Packet Counter Interrupt Status not detected
41001  */
41002 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
41003 
41004 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
41005 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
41006 /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
41007  *    rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
41008  *  0b1..MMC Receive Control Packet Counter Interrupt Status detected
41009  *  0b0..MMC Receive Control Packet Counter Interrupt Status not detected
41010  */
41011 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
41012 
41013 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
41014 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
41015 /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
41016  *    Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
41017  *  0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
41018  *  0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
41019  */
41020 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
41021 
41022 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
41023 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
41024 /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
41025  *    Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
41026  *  0b1..MMC Receive LPI transition Counter Interrupt Status detected
41027  *  0b0..MMC Receive LPI transition Counter Interrupt Status not detected
41028  */
41029 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
41030 /*! @} */
41031 
41032 /*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
41033 /*! @{ */
41034 
41035 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
41036 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
41037 /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
41038  *    txoctetcount_gb counter reaches half of the maximum value or the maximum value.
41039  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
41040  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
41041  */
41042 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
41043 
41044 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
41045 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
41046 /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
41047  *    txpacketcount_gb counter reaches half of the maximum value or the maximum value.
41048  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
41049  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
41050  */
41051 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
41052 
41053 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
41054 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
41055 /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
41056  *    txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
41057  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
41058  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
41059  */
41060 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
41061 
41062 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
41063 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
41064 /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
41065  *    txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
41066  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
41067  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
41068  */
41069 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
41070 
41071 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
41072 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
41073 /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
41074  *    when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
41075  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
41076  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
41077  */
41078 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
41079 
41080 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
41081 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
41082 /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
41083  *    bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
41084  *    reaches the maximum value.
41085  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
41086  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
41087  */
41088 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
41089 
41090 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
41091 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
41092 /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
41093  *    bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
41094  *    maximum value.
41095  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
41096  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
41097  */
41098 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
41099 
41100 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
41101 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
41102 /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
41103  *    bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
41104  *    maximum value.
41105  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
41106  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
41107  */
41108 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
41109 
41110 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
41111 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
41112 /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
41113  *    This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
41114  *    maximum value.
41115  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
41116  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
41117  */
41118 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
41119 
41120 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
41121 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
41122 /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
41123  *    This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
41124  *    the maximum value.
41125  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
41126  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
41127  */
41128 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
41129 
41130 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
41131 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
41132 /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
41133  *    the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
41134  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
41135  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
41136  */
41137 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
41138 
41139 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
41140 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
41141 /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
41142  *    the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
41143  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
41144  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
41145  */
41146 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
41147 
41148 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
41149 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
41150 /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
41151  *    the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
41152  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
41153  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
41154  */
41155 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
41156 
41157 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
41158 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
41159 /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
41160  *    the txunderflowerror counter reaches half of the maximum value or the maximum value.
41161  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
41162  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
41163  */
41164 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
41165 
41166 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
41167 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
41168 /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
41169  *    when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
41170  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
41171  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
41172  */
41173 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
41174 
41175 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
41176 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
41177 /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
41178  *    set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
41179  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
41180  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
41181  */
41182 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
41183 
41184 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
41185 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
41186 /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
41187  *    txdeferred counter reaches half of the maximum value or the maximum value.
41188  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
41189  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
41190  */
41191 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
41192 
41193 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
41194 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
41195 /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
41196  *    the txlatecol counter reaches half of the maximum value or the maximum value.
41197  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
41198  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
41199  */
41200 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
41201 
41202 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
41203 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
41204 /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
41205  *    when the txexesscol counter reaches half of the maximum value or the maximum value.
41206  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
41207  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
41208  */
41209 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
41210 
41211 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
41212 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
41213 /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
41214  *    txcarriererror counter reaches half of the maximum value or the maximum value.
41215  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
41216  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
41217  */
41218 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
41219 
41220 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
41221 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
41222 /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
41223  *    txoctetcount_g counter reaches half of the maximum value or the maximum value.
41224  *  0b1..MMC Transmit Good Octet Counter Interrupt Status detected
41225  *  0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
41226  */
41227 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
41228 
41229 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
41230 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
41231 /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
41232  *    txpacketcount_g counter reaches half of the maximum value or the maximum value.
41233  *  0b1..MMC Transmit Good Packet Counter Interrupt Status detected
41234  *  0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
41235  */
41236 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
41237 
41238 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
41239 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
41240 /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
41241  *    when the txexcessdef counter reaches half of the maximum value or the maximum value.
41242  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
41243  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
41244  */
41245 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
41246 
41247 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
41248 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
41249 /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
41250  *    txpausepacketserror counter reaches half of the maximum value or the maximum value.
41251  *  0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
41252  *  0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
41253  */
41254 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
41255 
41256 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
41257 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
41258 /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
41259  *    txvlanpackets_g counter reaches half of the maximum value or the maximum value.
41260  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
41261  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
41262  */
41263 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
41264 
41265 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
41266 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
41267 /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
41268  *    the txoversize_g counter reaches half of the maximum value or the maximum value.
41269  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
41270  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
41271  */
41272 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
41273 
41274 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
41275 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
41276 /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
41277  *    Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
41278  *  0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
41279  *  0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
41280  */
41281 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
41282 
41283 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
41284 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
41285 /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
41286  *    Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
41287  *  0b1..MMC Transmit LPI transition Counter Interrupt Status detected
41288  *  0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
41289  */
41290 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
41291 /*! @} */
41292 
41293 /*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
41294 /*! @{ */
41295 
41296 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
41297 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
41298 /*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
41299  *    interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
41300  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
41301  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
41302  */
41303 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
41304 
41305 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
41306 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
41307 /*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
41308  *    interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
41309  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
41310  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
41311  */
41312 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
41313 
41314 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
41315 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
41316 /*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
41317  *    when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
41318  *  0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
41319  *  0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
41320  */
41321 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
41322 
41323 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
41324 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
41325 /*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
41326  *    interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
41327  *    maximum value.
41328  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
41329  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
41330  */
41331 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
41332 
41333 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
41334 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
41335 /*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
41336  *    interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
41337  *    maximum value.
41338  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
41339  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
41340  */
41341 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
41342 
41343 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
41344 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
41345 /*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
41346  *    interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
41347  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
41348  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
41349  */
41350 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
41351 
41352 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
41353 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
41354 /*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
41355  *    the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
41356  *    maximum value.
41357  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
41358  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
41359  */
41360 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
41361 
41362 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
41363 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
41364 /*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
41365  *    when the rxrunterror counter reaches half of the maximum value or the maximum value.
41366  *  0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
41367  *  0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
41368  */
41369 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
41370 
41371 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
41372 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
41373 /*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
41374  *    interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
41375  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
41376  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
41377  */
41378 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
41379 
41380 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
41381 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
41382 /*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
41383  *    the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
41384  *    value.
41385  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
41386  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
41387  */
41388 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
41389 
41390 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
41391 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
41392 /*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
41393  *    interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
41394  *    value.
41395  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
41396  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
41397  */
41398 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
41399 
41400 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
41401 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
41402 /*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
41403  *    masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
41404  *    maximum value.
41405  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
41406  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
41407  */
41408 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
41409 
41410 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
41411 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
41412 /*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
41413  *    this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
41414  *    value or the maximum value.
41415  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
41416  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
41417  */
41418 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
41419 
41420 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
41421 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
41422 /*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
41423  *    this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
41424  *    value or the maximum value.
41425  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
41426  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
41427  */
41428 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
41429 
41430 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
41431 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
41432 /*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
41433  *    this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
41434  *    value or the maximum value.
41435  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
41436  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
41437  */
41438 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
41439 
41440 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
41441 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
41442 /*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
41443  *    Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
41444  *    maximum value or the maximum value.
41445  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
41446  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
41447  */
41448 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
41449 
41450 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
41451 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
41452 /*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
41453  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
41454  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
41455  */
41456 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
41457 
41458 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
41459 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
41460 /*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
41461  *    interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
41462  *    value.
41463  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
41464  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
41465  */
41466 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
41467 
41468 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
41469 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
41470 /*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
41471  *    interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
41472  *  0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
41473  *  0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
41474  */
41475 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
41476 
41477 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
41478 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
41479 /*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
41480  *    masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
41481  *    maximum value.
41482  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
41483  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
41484  */
41485 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
41486 
41487 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
41488 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
41489 /*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
41490  *    when the rxpausepackets counter reaches half of the maximum value or the maximum value.
41491  *  0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
41492  *  0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
41493  */
41494 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
41495 
41496 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
41497 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
41498 /*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
41499  *    interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
41500  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
41501  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
41502  */
41503 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
41504 
41505 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
41506 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
41507 /*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
41508  *    interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
41509  *    value.
41510  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
41511  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
41512  */
41513 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
41514 
41515 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
41516 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
41517 /*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
41518  *    interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
41519  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
41520  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
41521  */
41522 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
41523 
41524 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
41525 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
41526 /*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
41527  *    interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
41528  *  0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
41529  *  0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
41530  */
41531 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
41532 
41533 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
41534 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
41535 /*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
41536  *    interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
41537  *  0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
41538  *  0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
41539  */
41540 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
41541 
41542 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
41543 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
41544 /*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
41545  *    interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
41546  *  0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
41547  *  0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
41548  */
41549 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
41550 
41551 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
41552 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
41553 /*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
41554  *    interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
41555  *  0b0..MMC Receive LPI transition counter interrupt Mask is disabled
41556  *  0b1..MMC Receive LPI transition counter interrupt Mask is enabled
41557  */
41558 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
41559 /*! @} */
41560 
41561 /*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
41562 /*! @{ */
41563 
41564 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
41565 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
41566 /*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
41567  *    interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
41568  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
41569  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
41570  */
41571 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
41572 
41573 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
41574 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
41575 /*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
41576  *    interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
41577  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
41578  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
41579  */
41580 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
41581 
41582 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
41583 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
41584 /*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
41585  *    interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
41586  *    maximum value.
41587  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
41588  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
41589  */
41590 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
41591 
41592 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
41593 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
41594 /*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
41595  *    interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
41596  *    maximum value.
41597  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
41598  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
41599  */
41600 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
41601 
41602 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
41603 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
41604 /*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
41605  *    masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
41606  *    maximum value.
41607  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
41608  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
41609  */
41610 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
41611 
41612 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
41613 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
41614 /*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
41615  *    this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
41616  *    value or the maximum value.
41617  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
41618  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
41619  */
41620 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
41621 
41622 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
41623 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
41624 /*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
41625  *    this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
41626  *    value or the maximum value.
41627  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
41628  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
41629  */
41630 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
41631 
41632 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
41633 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
41634 /*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
41635  *    this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
41636  *    value or the maximum value.
41637  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
41638  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
41639  */
41640 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
41641 
41642 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
41643 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
41644 /*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
41645  *    Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
41646  *    maximum value or the maximum value.
41647  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
41648  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
41649  */
41650 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
41651 
41652 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
41653 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
41654 /*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
41655  *    Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
41656  *    maximum value or the maximum value.
41657  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
41658  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
41659  */
41660 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
41661 
41662 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
41663 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
41664 /*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41665  *    the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
41666  *    maximum value.
41667  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
41668  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
41669  */
41670 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
41671 
41672 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
41673 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
41674 /*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41675  *    the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
41676  *    maximum value.
41677  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
41678  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
41679  */
41680 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
41681 
41682 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
41683 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
41684 /*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
41685  *    the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
41686  *    maximum value.
41687  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
41688  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
41689  */
41690 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
41691 
41692 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
41693 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
41694 /*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
41695  *    the interrupt when the txunderflowerror counter reaches half of the maximum value or the
41696  *    maximum value.
41697  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
41698  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
41699  */
41700 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
41701 
41702 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
41703 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
41704 /*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
41705  *    masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
41706  *    maximum value.
41707  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
41708  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
41709  */
41710 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
41711 
41712 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
41713 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
41714 /*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
41715  *    masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
41716  *    maximum value.
41717  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
41718  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
41719  */
41720 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
41721 
41722 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
41723 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
41724 /*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
41725  *    interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
41726  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
41727  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
41728  */
41729 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
41730 
41731 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
41732 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
41733 /*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
41734  *    the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
41735  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
41736  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
41737  */
41738 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
41739 
41740 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
41741 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
41742 /*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
41743  *    masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
41744  *    value.
41745  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
41746  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
41747  */
41748 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
41749 
41750 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
41751 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
41752 /*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
41753  *    interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
41754  *    value.
41755  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
41756  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
41757  */
41758 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
41759 
41760 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
41761 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
41762 /*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
41763  *    when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
41764  *  0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
41765  *  0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
41766  */
41767 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
41768 
41769 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
41770 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
41771 /*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
41772  *    when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
41773  *  0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
41774  *  0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
41775  */
41776 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
41777 
41778 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
41779 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
41780 /*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
41781  *    masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
41782  *    value.
41783  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
41784  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
41785  */
41786 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
41787 
41788 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
41789 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
41790 /*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
41791  *    interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
41792  *  0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
41793  *  0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
41794  */
41795 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
41796 
41797 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
41798 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
41799 /*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
41800  *    interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
41801  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
41802  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
41803  */
41804 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
41805 
41806 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
41807 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
41808 /*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
41809  *    the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
41810  *    value.
41811  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
41812  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
41813  */
41814 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
41815 
41816 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
41817 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
41818 /*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
41819  *    interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
41820  *  0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
41821  *  0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
41822  */
41823 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
41824 
41825 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
41826 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
41827 /*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
41828  *    interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
41829  *  0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
41830  *  0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
41831  */
41832 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
41833 /*! @} */
41834 
41835 /*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
41836 /*! @{ */
41837 
41838 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
41839 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
41840 /*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
41841  *    exclusive of preamble and retried bytes, in good and bad packets.
41842  */
41843 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
41844 /*! @} */
41845 
41846 /*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
41847 /*! @{ */
41848 
41849 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
41850 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
41851 /*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
41852  *    transmitted, exclusive of retried packets.
41853  */
41854 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
41855 /*! @} */
41856 
41857 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
41858 /*! @{ */
41859 
41860 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
41861 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
41862 /*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted.
41863  */
41864 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
41865 /*! @} */
41866 
41867 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
41868 /*! @{ */
41869 
41870 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
41871 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
41872 /*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted.
41873  */
41874 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
41875 /*! @} */
41876 
41877 /*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
41878 /*! @{ */
41879 
41880 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
41881 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
41882 /*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
41883  *    transmitted with length 64 bytes, exclusive of preamble and retried packets.
41884  */
41885 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
41886 /*! @} */
41887 
41888 /*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
41889 /*! @{ */
41890 
41891 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
41892 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
41893 /*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
41894  *    bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
41895  *    and retried packets.
41896  */
41897 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
41898 /*! @} */
41899 
41900 /*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
41901 /*! @{ */
41902 
41903 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
41904 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
41905 /*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
41906  *    bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
41907  *    preamble and retried packets.
41908  */
41909 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
41910 /*! @} */
41911 
41912 /*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
41913 /*! @{ */
41914 
41915 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
41916 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
41917 /*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
41918  *    bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
41919  *    preamble and retried packets.
41920  */
41921 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
41922 /*! @} */
41923 
41924 /*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
41925 /*! @{ */
41926 
41927 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
41928 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
41929 /*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
41930  *    and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
41931  *    preamble and retried packets.
41932  */
41933 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
41934 /*! @} */
41935 
41936 /*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
41937 /*! @{ */
41938 
41939 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
41940 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
41941 /*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
41942  *    and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
41943  *    preamble and retried packets.
41944  */
41945 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
41946 /*! @} */
41947 
41948 /*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
41949 /*! @{ */
41950 
41951 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
41952 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
41953 /*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted.
41954  */
41955 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
41956 /*! @} */
41957 
41958 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
41959 /*! @{ */
41960 
41961 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
41962 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
41963 /*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted.
41964  */
41965 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
41966 /*! @} */
41967 
41968 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
41969 /*! @{ */
41970 
41971 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
41972 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
41973 /*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted.
41974  */
41975 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
41976 /*! @} */
41977 
41978 /*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
41979 /*! @{ */
41980 
41981 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
41982 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
41983 /*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error.
41984  */
41985 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
41986 /*! @} */
41987 
41988 /*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
41989 /*! @{ */
41990 
41991 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
41992 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
41993 /*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
41994  *    transmitted packets after a single collision in the half-duplex mode.
41995  */
41996 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
41997 /*! @} */
41998 
41999 /*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
42000 /*! @{ */
42001 
42002 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
42003 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
42004 /*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
42005  *    transmitted packets after multiple collisions in the half-duplex mode.
42006  */
42007 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
42008 /*! @} */
42009 
42010 /*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
42011 /*! @{ */
42012 
42013 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
42014 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
42015 /*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
42016  *    a deferral in the half-duplex mode.
42017  */
42018 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
42019 /*! @} */
42020 
42021 /*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
42022 /*! @{ */
42023 
42024 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
42025 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
42026 /*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error.
42027  */
42028 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
42029 /*! @} */
42030 
42031 /*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
42032 /*! @{ */
42033 
42034 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
42035 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
42036 /*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
42037  *    because of excessive (16) collision errors.
42038  */
42039 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
42040 /*! @} */
42041 
42042 /*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
42043 /*! @{ */
42044 
42045 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
42046 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
42047 /*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
42048  *    carrier sense error (no carrier or loss of carrier).
42049  */
42050 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
42051 /*! @} */
42052 
42053 /*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
42054 /*! @{ */
42055 
42056 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
42057 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
42058 /*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets.
42059  */
42060 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
42061 /*! @} */
42062 
42063 /*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
42064 /*! @{ */
42065 
42066 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
42067 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
42068 /*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted.
42069  */
42070 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
42071 /*! @} */
42072 
42073 /*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
42074 /*! @{ */
42075 
42076 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
42077 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
42078 /*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
42079  *    because of excessive deferral error (deferred for more than two max-sized packet times).
42080  */
42081 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
42082 /*! @} */
42083 
42084 /*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
42085 /*! @{ */
42086 
42087 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
42088 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
42089 /*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted.
42090  */
42091 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
42092 /*! @} */
42093 
42094 /*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
42095 /*! @{ */
42096 
42097 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
42098 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
42099 /*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted.
42100  */
42101 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
42102 /*! @} */
42103 
42104 /*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
42105 /*! @{ */
42106 
42107 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
42108 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
42109 /*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
42110  *    errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
42111  *    2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
42112  */
42113 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
42114 /*! @} */
42115 
42116 /*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
42117 /*! @{ */
42118 
42119 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
42120 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
42121 /*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received.
42122  */
42123 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
42124 /*! @} */
42125 
42126 /*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
42127 /*! @{ */
42128 
42129 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
42130 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
42131 /*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
42132  *    of preamble, in good and bad packets.
42133  */
42134 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
42135 /*! @} */
42136 
42137 /*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
42138 /*! @{ */
42139 
42140 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
42141 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
42142 /*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets.
42143  */
42144 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
42145 /*! @} */
42146 
42147 /*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
42148 /*! @{ */
42149 
42150 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
42151 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
42152 /*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received.
42153  */
42154 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
42155 /*! @} */
42156 
42157 /*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
42158 /*! @{ */
42159 
42160 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
42161 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
42162 /*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received.
42163  */
42164 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
42165 /*! @} */
42166 
42167 /*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
42168 /*! @{ */
42169 
42170 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
42171 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
42172 /*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error.
42173  */
42174 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
42175 /*! @} */
42176 
42177 /*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
42178 /*! @{ */
42179 
42180 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
42181 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
42182 /*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error.
42183  */
42184 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
42185 /*! @} */
42186 
42187 /*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
42188 /*! @{ */
42189 
42190 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
42191 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
42192 /*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
42193  *    (length less than 64 bytes and CRC error) error.
42194  */
42195 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
42196 /*! @} */
42197 
42198 /*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
42199 /*! @{ */
42200 
42201 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
42202 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
42203 /*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
42204  *    with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
42205  *    error.
42206  */
42207 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
42208 /*! @} */
42209 
42210 /*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
42211 /*! @{ */
42212 
42213 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
42214 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
42215 /*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
42216  *    length less than 64 bytes, without any errors.
42217  */
42218 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
42219 /*! @} */
42220 
42221 /*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
42222 /*! @{ */
42223 
42224 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
42225 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
42226 /*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
42227  *    errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
42228  *    packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
42229  */
42230 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
42231 /*! @} */
42232 
42233 /*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
42234 /*! @{ */
42235 
42236 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
42237 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
42238 /*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
42239  *    packets received with length 64 bytes, exclusive of the preamble.
42240  */
42241 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
42242 /*! @} */
42243 
42244 /*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
42245 /*! @{ */
42246 
42247 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
42248 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
42249 /*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
42250  *    bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
42251  */
42252 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
42253 /*! @} */
42254 
42255 /*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
42256 /*! @{ */
42257 
42258 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
42259 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
42260 /*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
42261  *    bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
42262  *    preamble.
42263  */
42264 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
42265 /*! @} */
42266 
42267 /*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
42268 /*! @{ */
42269 
42270 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
42271 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
42272 /*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
42273  *    bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
42274  *    preamble.
42275  */
42276 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
42277 /*! @} */
42278 
42279 /*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
42280 /*! @{ */
42281 
42282 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
42283 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
42284 /*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
42285  *    and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
42286  *    preamble.
42287  */
42288 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
42289 /*! @} */
42290 
42291 /*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
42292 /*! @{ */
42293 
42294 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
42295 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
42296 /*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
42297  *    packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
42298  *    preamble.
42299  */
42300 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
42301 /*! @} */
42302 
42303 /*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
42304 /*! @{ */
42305 
42306 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
42307 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
42308 /*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received.
42309  */
42310 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
42311 /*! @} */
42312 
42313 /*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
42314 /*! @{ */
42315 
42316 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
42317 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
42318 /*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
42319  *    length error (Length Type field not equal to packet size), for all packets with valid length field.
42320  */
42321 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
42322 /*! @} */
42323 
42324 /*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
42325 /*! @{ */
42326 
42327 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
42328 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
42329 /*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
42330  *    with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
42331  */
42332 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
42333 /*! @} */
42334 
42335 /*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
42336 /*! @{ */
42337 
42338 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
42339 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
42340 /*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received.
42341  */
42342 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
42343 /*! @} */
42344 
42345 /*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
42346 /*! @{ */
42347 
42348 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
42349 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
42350 /*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow.
42351  */
42352 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
42353 /*! @} */
42354 
42355 /*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
42356 /*! @{ */
42357 
42358 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
42359 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
42360 /*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received.
42361  */
42362 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
42363 /*! @} */
42364 
42365 /*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
42366 /*! @{ */
42367 
42368 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
42369 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
42370 /*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
42371  *    error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
42372  *    JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
42373  *    WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
42374  *    MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
42375  */
42376 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
42377 /*! @} */
42378 
42379 /*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
42380 /*! @{ */
42381 
42382 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
42383 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
42384 /*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
42385  *    Receive error or Packet Extension error on the GMII or MII interface.
42386  */
42387 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
42388 /*! @} */
42389 
42390 /*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
42391 /*! @{ */
42392 
42393 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
42394 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
42395 /*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received.
42396  */
42397 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
42398 /*! @} */
42399 
42400 /*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
42401 /*! @{ */
42402 
42403 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
42404 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
42405 /*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted.
42406  */
42407 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
42408 /*! @} */
42409 
42410 /*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
42411 /*! @{ */
42412 
42413 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
42414 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
42415 /*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred.
42416  */
42417 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
42418 /*! @} */
42419 
42420 /*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
42421 /*! @{ */
42422 
42423 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
42424 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
42425 /*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted.
42426  */
42427 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
42428 /*! @} */
42429 
42430 /*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
42431 /*! @{ */
42432 
42433 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
42434 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
42435 /*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred.
42436  */
42437 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
42438 /*! @} */
42439 
42440 /*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
42441 /*! @{ */
42442 
42443 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
42444 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
42445 /*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
42446  *    interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
42447  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
42448  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
42449  */
42450 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
42451 
42452 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
42453 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
42454 /*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
42455  *    masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
42456  *    maximum value.
42457  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
42458  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
42459  */
42460 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
42461 
42462 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
42463 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
42464 /*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
42465  *    masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
42466  *    maximum value.
42467  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
42468  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
42469  */
42470 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
42471 
42472 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
42473 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
42474 /*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
42475  *    the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
42476  *    maximum value.
42477  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
42478  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
42479  */
42480 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
42481 
42482 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
42483 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
42484 /*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
42485  *    this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
42486  *    value or the maximum value.
42487  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
42488  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
42489  */
42490 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
42491 
42492 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
42493 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
42494 /*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
42495  *    interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
42496  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
42497  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
42498  */
42499 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
42500 
42501 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
42502 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
42503 /*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
42504  *    masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
42505  *    maximum value.
42506  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
42507  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
42508  */
42509 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
42510 
42511 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
42512 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
42513 /*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
42514  *    masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
42515  *    maximum value.
42516  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
42517  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
42518  */
42519 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
42520 
42521 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
42522 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
42523 /*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
42524  *    interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
42525  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
42526  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
42527  */
42528 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
42529 
42530 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
42531 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
42532 /*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
42533  *    interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
42534  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
42535  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
42536  */
42537 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
42538 
42539 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
42540 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
42541 /*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
42542  *    interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
42543  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
42544  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
42545  */
42546 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
42547 
42548 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
42549 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
42550 /*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
42551  *    interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
42552  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
42553  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
42554  */
42555 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
42556 
42557 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
42558 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
42559 /*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
42560  *    interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
42561  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
42562  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
42563  */
42564 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
42565 
42566 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
42567 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
42568 /*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
42569  *    interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
42570  *    value.
42571  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
42572  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
42573  */
42574 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
42575 
42576 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
42577 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
42578 /*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
42579  *    interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
42580  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
42581  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
42582  */
42583 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
42584 
42585 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
42586 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
42587 /*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
42588  *    the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
42589  *    maximum value.
42590  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
42591  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
42592  */
42593 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
42594 
42595 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
42596 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
42597 /*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
42598  *    the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
42599  *    maximum value.
42600  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
42601  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
42602  */
42603 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
42604 
42605 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
42606 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
42607 /*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
42608  *    the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
42609  *    maximum value.
42610  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
42611  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
42612  */
42613 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
42614 
42615 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
42616 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
42617 /*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
42618  *    this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
42619  *    value or the maximum value.
42620  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
42621  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
42622  */
42623 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
42624 
42625 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
42626 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
42627 /*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
42628  *    interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
42629  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
42630  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
42631  */
42632 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
42633 
42634 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
42635 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
42636 /*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
42637  *    interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
42638  *    value.
42639  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
42640  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
42641  */
42642 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
42643 
42644 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
42645 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
42646 /*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
42647  *    masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
42648  *    maximum value.
42649  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
42650  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
42651  */
42652 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
42653 
42654 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
42655 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
42656 /*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
42657  *    interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
42658  *    value.
42659  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
42660  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
42661  */
42662 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
42663 
42664 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
42665 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
42666 /*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
42667  *    interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
42668  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
42669  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
42670  */
42671 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
42672 
42673 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
42674 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
42675 /*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
42676  *    interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
42677  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
42678  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
42679  */
42680 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
42681 
42682 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
42683 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
42684 /*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
42685  *    interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
42686  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
42687  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
42688  */
42689 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
42690 
42691 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
42692 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
42693 /*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
42694  *    interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
42695  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
42696  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
42697  */
42698 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
42699 
42700 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
42701 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
42702 /*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
42703  *    interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
42704  *    value.
42705  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
42706  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
42707  */
42708 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
42709 /*! @} */
42710 
42711 /*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
42712 /*! @{ */
42713 
42714 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
42715 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
42716 /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
42717  *    rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
42718  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
42719  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
42720  */
42721 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
42722 
42723 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
42724 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
42725 /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
42726  *    when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
42727  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
42728  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
42729  */
42730 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
42731 
42732 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
42733 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
42734 /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
42735  *    when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
42736  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
42737  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
42738  */
42739 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
42740 
42741 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
42742 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
42743 /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
42744  *    the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
42745  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
42746  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
42747  */
42748 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
42749 
42750 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
42751 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
42752 /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
42753  *    is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
42754  *    value.
42755  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
42756  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
42757  */
42758 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
42759 
42760 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
42761 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
42762 /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
42763  *    rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
42764  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
42765  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
42766  */
42767 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
42768 
42769 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
42770 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
42771 /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
42772  *    when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
42773  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
42774  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
42775  */
42776 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
42777 
42778 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
42779 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
42780 /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
42781  *    when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
42782  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
42783  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
42784  */
42785 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
42786 
42787 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
42788 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
42789 /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
42790  *    rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
42791  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
42792  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
42793  */
42794 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
42795 
42796 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
42797 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
42798 /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
42799  *    rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
42800  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
42801  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
42802  */
42803 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
42804 
42805 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
42806 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
42807 /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
42808  *    rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
42809  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
42810  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
42811  */
42812 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
42813 
42814 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
42815 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
42816 /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
42817  *    rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
42818  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
42819  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
42820  */
42821 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
42822 
42823 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
42824 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
42825 /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
42826  *    rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
42827  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
42828  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
42829  */
42830 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
42831 
42832 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
42833 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
42834 /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
42835  *    rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
42836  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
42837  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
42838  */
42839 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
42840 
42841 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
42842 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
42843 /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
42844  *    rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
42845  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
42846  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
42847  */
42848 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
42849 
42850 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
42851 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
42852 /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
42853  *    the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
42854  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
42855  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
42856  */
42857 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
42858 
42859 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
42860 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
42861 /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
42862  *    the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
42863  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
42864  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
42865  */
42866 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
42867 
42868 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
42869 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
42870 /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
42871  *    the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
42872  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
42873  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
42874  */
42875 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
42876 
42877 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
42878 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
42879 /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
42880  *    is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
42881  *    value.
42882  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
42883  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
42884  */
42885 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
42886 
42887 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
42888 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
42889 /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
42890  *    rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
42891  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
42892  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
42893  */
42894 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
42895 
42896 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
42897 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
42898 /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
42899  *    the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
42900  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
42901  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
42902  */
42903 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
42904 
42905 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
42906 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
42907 /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
42908  *    the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
42909  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
42910  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
42911  */
42912 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
42913 
42914 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
42915 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
42916 /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
42917  *    rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
42918  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
42919  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
42920  */
42921 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
42922 
42923 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
42924 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
42925 /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
42926  *    rxudp_err_octets counter reaches half of the maximum value or the maximum value.
42927  *  0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
42928  *  0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
42929  */
42930 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
42931 
42932 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
42933 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
42934 /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
42935  *    rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
42936  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
42937  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
42938  */
42939 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
42940 
42941 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
42942 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
42943 /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
42944  *    rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
42945  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
42946  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
42947  */
42948 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
42949 
42950 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
42951 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
42952 /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
42953  *    rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
42954  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
42955  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
42956  */
42957 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
42958 
42959 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
42960 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
42961 /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
42962  *    rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
42963  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
42964  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
42965  */
42966 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
42967 /*! @} */
42968 
42969 /*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
42970 /*! @{ */
42971 
42972 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
42973 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
42974 /*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
42975  */
42976 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
42977 /*! @} */
42978 
42979 /*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
42980 /*! @{ */
42981 
42982 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
42983 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
42984 /*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
42985  *    received with header (checksum, length, or version mismatch) errors.
42986  */
42987 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
42988 /*! @} */
42989 
42990 /*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
42991 /*! @{ */
42992 
42993 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
42994 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
42995 /*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
42996  *    received that did not have a TCP, UDP, or ICMP payload.
42997  */
42998 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
42999 /*! @} */
43000 
43001 /*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
43002 /*! @{ */
43003 
43004 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
43005 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
43006 /*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation.
43007  */
43008 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
43009 /*! @} */
43010 
43011 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
43012 /*! @{ */
43013 
43014 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
43015 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
43016 /*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
43017  *    IPv4 datagrams received that had a UDP payload with checksum disabled.
43018  */
43019 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
43020 /*! @} */
43021 
43022 /*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
43023 /*! @{ */
43024 
43025 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
43026 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
43027 /*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload.
43028  */
43029 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
43030 /*! @} */
43031 
43032 /*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
43033 /*! @{ */
43034 
43035 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
43036 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
43037 /*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
43038  *    received with header (length or version mismatch) errors.
43039  */
43040 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
43041 /*! @} */
43042 
43043 /*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
43044 /*! @{ */
43045 
43046 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
43047 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
43048 /*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
43049  *    received that did not have a TCP, UDP, or ICMP payload.
43050  */
43051 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
43052 /*! @} */
43053 
43054 /*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
43055 /*! @{ */
43056 
43057 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
43058 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
43059 /*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload.
43060  */
43061 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
43062 /*! @} */
43063 
43064 /*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
43065 /*! @{ */
43066 
43067 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
43068 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
43069 /*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
43070  *    whose UDP payload has a checksum error.
43071  */
43072 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
43073 /*! @} */
43074 
43075 /*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
43076 /*! @{ */
43077 
43078 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
43079 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
43080 /*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload.
43081  */
43082 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
43083 /*! @} */
43084 
43085 /*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
43086 /*! @{ */
43087 
43088 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
43089 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
43090 /*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
43091  *    whose TCP payload has a checksum error.
43092  */
43093 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
43094 /*! @} */
43095 
43096 /*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
43097 /*! @{ */
43098 
43099 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
43100 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
43101 /*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload.
43102  */
43103 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
43104 /*! @} */
43105 
43106 /*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
43107 /*! @{ */
43108 
43109 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
43110 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
43111 /*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
43112  *    received whose ICMP payload has a checksum error.
43113  */
43114 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
43115 /*! @} */
43116 
43117 /*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
43118 /*! @{ */
43119 
43120 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
43121 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
43122 /*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
43123  *    datagrams encapsulating TCP, UDP, or ICMP data.
43124  */
43125 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
43126 /*! @} */
43127 
43128 /*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
43129 /*! @{ */
43130 
43131 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
43132 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
43133 /*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
43134  *    in IPv4 datagrams with header errors (checksum, length, version mismatch).
43135  */
43136 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
43137 /*! @} */
43138 
43139 /*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
43140 /*! @{ */
43141 
43142 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
43143 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
43144 /*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
43145  *    datagrams that did not have a TCP, UDP, or ICMP payload.
43146  */
43147 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
43148 /*! @} */
43149 
43150 /*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
43151 /*! @{ */
43152 
43153 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
43154 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
43155 /*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams.
43156  */
43157 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
43158 /*! @} */
43159 
43160 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
43161 /*! @{ */
43162 
43163 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
43164 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
43165 /*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
43166  *    received in a UDP segment that had the UDP checksum disabled.
43167  */
43168 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
43169 /*! @} */
43170 
43171 /*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
43172 /*! @{ */
43173 
43174 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
43175 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
43176 /*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
43177  *    datagrams encapsulating TCP, UDP, or ICMP data.
43178  */
43179 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
43180 /*! @} */
43181 
43182 /*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
43183 /*! @{ */
43184 
43185 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
43186 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
43187 /*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
43188  *    in IPv6 datagrams with header errors (length, version mismatch).
43189  */
43190 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
43191 /*! @} */
43192 
43193 /*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
43194 /*! @{ */
43195 
43196 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
43197 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
43198 /*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
43199  *    datagrams that did not have a TCP, UDP, or ICMP payload.
43200  */
43201 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
43202 /*! @} */
43203 
43204 /*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
43205 /*! @{ */
43206 
43207 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
43208 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
43209 /*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment.
43210  */
43211 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
43212 /*! @} */
43213 
43214 /*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
43215 /*! @{ */
43216 
43217 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
43218 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
43219 /*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors.
43220  */
43221 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
43222 /*! @} */
43223 
43224 /*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
43225 /*! @{ */
43226 
43227 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
43228 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
43229 /*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment.
43230  */
43231 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
43232 /*! @} */
43233 
43234 /*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
43235 /*! @{ */
43236 
43237 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
43238 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
43239 /*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors.
43240  */
43241 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
43242 /*! @} */
43243 
43244 /*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
43245 /*! @{ */
43246 
43247 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
43248 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
43249 /*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment.
43250  */
43251 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
43252 /*! @} */
43253 
43254 /*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
43255 /*! @{ */
43256 
43257 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
43258 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
43259 /*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors.
43260  */
43261 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
43262 /*! @} */
43263 
43264 /*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
43265 /*! @{ */
43266 
43267 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
43268 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
43269 /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
43270  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
43271  *  0b1..MMC Tx FPE Fragment Counter Interrupt status detected
43272  *  0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
43273  */
43274 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
43275 
43276 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
43277 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
43278 /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
43279  *    counter reaches half of the maximum value or the maximum value.
43280  *  0b1..MMC Tx Hold Request Counter Interrupt Status detected
43281  *  0b0..MMC Tx Hold Request Counter Interrupt Status not detected
43282  */
43283 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
43284 /*! @} */
43285 
43286 /*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
43287 /*! @{ */
43288 
43289 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
43290 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
43291 /*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
43292  *    the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
43293  *  0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
43294  *  0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
43295  */
43296 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
43297 
43298 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
43299 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
43300 /*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
43301  *    when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
43302  *  0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
43303  *  0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
43304  */
43305 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
43306 /*! @} */
43307 
43308 /*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
43309 /*! @{ */
43310 
43311 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
43312 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
43313 /*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
43314  *    been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
43315  *    during FPE Enabled configuration.
43316  */
43317 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
43318 /*! @} */
43319 
43320 /*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
43321 /*! @{ */
43322 
43323 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
43324 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
43325 /*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC.
43326  */
43327 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
43328 /*! @} */
43329 
43330 /*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
43331 /*! @{ */
43332 
43333 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
43334 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
43335 /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
43336  *    Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
43337  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
43338  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
43339  */
43340 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
43341 
43342 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
43343 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
43344 /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
43345  *    Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
43346  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
43347  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
43348  */
43349 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
43350 
43351 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
43352 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
43353 /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
43354  *    Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
43355  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
43356  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
43357  */
43358 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
43359 
43360 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
43361 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
43362 /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
43363  *    Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
43364  *  0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
43365  *  0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
43366  */
43367 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
43368 /*! @} */
43369 
43370 /*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
43371 /*! @{ */
43372 
43373 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
43374 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
43375 /*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
43376  *    interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
43377  *    maximum value.
43378  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
43379  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
43380  */
43381 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
43382 
43383 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
43384 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
43385 /*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
43386  *    when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
43387  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
43388  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
43389  */
43390 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
43391 
43392 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
43393 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
43394 /*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
43395  *    when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
43396  *    value.
43397  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
43398  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
43399  */
43400 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
43401 
43402 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
43403 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
43404 /*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
43405  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
43406  *  0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
43407  *  0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
43408  */
43409 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
43410 /*! @} */
43411 
43412 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
43413 /*! @{ */
43414 
43415 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
43416 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
43417 /*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
43418  *    reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
43419  */
43420 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
43421 /*! @} */
43422 
43423 /*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
43424 /*! @{ */
43425 
43426 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
43427 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
43428 /*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
43429  *    unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
43430  *    was no preceding preempted frame.
43431  */
43432 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
43433 /*! @} */
43434 
43435 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
43436 /*! @{ */
43437 
43438 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
43439 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
43440 /*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
43441  *    successfully reassembled and delivered to MAC.
43442  */
43443 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
43444 /*! @} */
43445 
43446 /*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
43447 /*! @{ */
43448 
43449 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
43450 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
43451 /*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
43452  *    due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
43453  *    Enabled configuration.
43454  */
43455 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
43456 /*! @} */
43457 
43458 /*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
43459 /*! @{ */
43460 
43461 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK  (0x1U)
43462 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
43463 /*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43464  *    Address matching is enabled for IPv6 packets.
43465  *  0b0..Layer 3 Protocol is disabled
43466  *  0b1..Layer 3 Protocol is enabled
43467  */
43468 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
43469 
43470 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK  (0x4U)
43471 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
43472 /*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43473  *  0b0..Layer 3 IP SA Match is disabled
43474  *  0b1..Layer 3 IP SA Match is enabled
43475  */
43476 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
43477 
43478 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
43479 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
43480 /*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43481  *    field is enabled for inverse matching.
43482  *  0b0..Layer 3 IP SA Inverse Match is disabled
43483  *  0b1..Layer 3 IP SA Inverse Match is enabled
43484  */
43485 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
43486 
43487 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK  (0x10U)
43488 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
43489 /*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43490  *  0b0..Layer 3 IP DA Match is disabled
43491  *  0b1..Layer 3 IP DA Match is enabled
43492  */
43493 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
43494 
43495 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
43496 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
43497 /*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43498  *    Address field is enabled for inverse matching.
43499  *  0b0..Layer 3 IP DA Inverse Match is disabled
43500  *  0b1..Layer 3 IP DA Inverse Match is enabled
43501  */
43502 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
43503 
43504 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
43505 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
43506 /*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43507  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43508  */
43509 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
43510 
43511 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
43512 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
43513 /*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43514  *    bits of IP Destination Address that are matched in the IPv4 packets.
43515  */
43516 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
43517 
43518 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK  (0x10000U)
43519 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
43520 /*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43521  *    fields of UDP packets are used for matching.
43522  *  0b0..Layer 4 Protocol is disabled
43523  *  0b1..Layer 4 Protocol is enabled
43524  */
43525 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
43526 
43527 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK  (0x40000U)
43528 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
43529 /*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43530  *  0b0..Layer 4 Source Port Match is disabled
43531  *  0b1..Layer 4 Source Port Match is enabled
43532  */
43533 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
43534 
43535 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
43536 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
43537 /*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43538  *    number field is enabled for inverse matching.
43539  *  0b0..Layer 4 Source Port Inverse Match is disabled
43540  *  0b1..Layer 4 Source Port Inverse Match is enabled
43541  */
43542 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
43543 
43544 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK  (0x100000U)
43545 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
43546 /*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43547  *    Port number field is enabled for matching.
43548  *  0b0..Layer 4 Destination Port Match is disabled
43549  *  0b1..Layer 4 Destination Port Match is enabled
43550  */
43551 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
43552 
43553 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
43554 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
43555 /*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43556  *    Destination Port number field is enabled for inverse matching.
43557  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43558  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43559  */
43560 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
43561 
43562 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK  (0x7000000U)
43563 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
43564 /*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43565  *    to which the packet passed by this filter is routed.
43566  */
43567 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
43568 
43569 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
43570 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
43571 /*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43572  *    number for the packet that is passed by this L3_L4 filter.
43573  *  0b0..DMA Channel Select is disabled
43574  *  0b1..DMA Channel Select is enabled
43575  */
43576 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
43577 /*! @} */
43578 
43579 /*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
43580 /*! @{ */
43581 
43582 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK  (0xFFFFU)
43583 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
43584 /*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43585  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43586  *    Source Port Number field in the IPv4 or IPv6 packets.
43587  */
43588 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
43589 
43590 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK  (0xFFFF0000U)
43591 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
43592 /*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43593  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43594  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43595  */
43596 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
43597 /*! @} */
43598 
43599 /*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
43600 /*! @{ */
43601 
43602 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
43603 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
43604 /*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43605  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43606  *    Address field in the IPv6 packets.
43607  */
43608 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
43609 /*! @} */
43610 
43611 /*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
43612 /*! @{ */
43613 
43614 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
43615 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
43616 /*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43617  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43618  *    Address field in the IPv6 packets.
43619  */
43620 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
43621 /*! @} */
43622 
43623 /*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
43624 /*! @{ */
43625 
43626 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
43627 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
43628 /*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43629  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43630  *    Address field in the IPv6 packets.
43631  */
43632 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
43633 /*! @} */
43634 
43635 /*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
43636 /*! @{ */
43637 
43638 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
43639 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
43640 /*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43641  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43642  *    Address field in the IPv6 packets.
43643  */
43644 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
43645 /*! @} */
43646 
43647 /*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
43648 /*! @{ */
43649 
43650 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK  (0x1U)
43651 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
43652 /*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43653  *    Address matching is enabled for IPv6 packets.
43654  *  0b0..Layer 3 Protocol is disabled
43655  *  0b1..Layer 3 Protocol is enabled
43656  */
43657 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
43658 
43659 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK  (0x4U)
43660 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
43661 /*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43662  *  0b0..Layer 3 IP SA Match is disabled
43663  *  0b1..Layer 3 IP SA Match is enabled
43664  */
43665 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
43666 
43667 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
43668 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
43669 /*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43670  *    field is enabled for inverse matching.
43671  *  0b0..Layer 3 IP SA Inverse Match is disabled
43672  *  0b1..Layer 3 IP SA Inverse Match is enabled
43673  */
43674 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
43675 
43676 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK  (0x10U)
43677 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
43678 /*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43679  *  0b0..Layer 3 IP DA Match is disabled
43680  *  0b1..Layer 3 IP DA Match is enabled
43681  */
43682 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
43683 
43684 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
43685 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
43686 /*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43687  *    Address field is enabled for inverse matching.
43688  *  0b0..Layer 3 IP DA Inverse Match is disabled
43689  *  0b1..Layer 3 IP DA Inverse Match is enabled
43690  */
43691 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
43692 
43693 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
43694 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
43695 /*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43696  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43697  */
43698 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
43699 
43700 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
43701 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
43702 /*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43703  *    bits of IP Destination Address that are matched in the IPv4 packets.
43704  */
43705 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
43706 
43707 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK  (0x10000U)
43708 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
43709 /*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43710  *    fields of UDP packets are used for matching.
43711  *  0b0..Layer 4 Protocol is disabled
43712  *  0b1..Layer 4 Protocol is enabled
43713  */
43714 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
43715 
43716 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK  (0x40000U)
43717 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
43718 /*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43719  *  0b0..Layer 4 Source Port Match is disabled
43720  *  0b1..Layer 4 Source Port Match is enabled
43721  */
43722 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
43723 
43724 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
43725 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
43726 /*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43727  *    number field is enabled for inverse matching.
43728  *  0b0..Layer 4 Source Port Inverse Match is disabled
43729  *  0b1..Layer 4 Source Port Inverse Match is enabled
43730  */
43731 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
43732 
43733 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK  (0x100000U)
43734 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
43735 /*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43736  *    Port number field is enabled for matching.
43737  *  0b0..Layer 4 Destination Port Match is disabled
43738  *  0b1..Layer 4 Destination Port Match is enabled
43739  */
43740 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
43741 
43742 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
43743 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
43744 /*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43745  *    Destination Port number field is enabled for inverse matching.
43746  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43747  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43748  */
43749 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
43750 
43751 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK  (0x7000000U)
43752 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
43753 /*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43754  *    to which the packet passed by this filter is routed.
43755  */
43756 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
43757 
43758 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
43759 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
43760 /*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43761  *    number for the packet that is passed by this L3_L4 filter.
43762  *  0b0..DMA Channel Select is disabled
43763  *  0b1..DMA Channel Select is enabled
43764  */
43765 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
43766 /*! @} */
43767 
43768 /*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
43769 /*! @{ */
43770 
43771 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK  (0xFFFFU)
43772 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
43773 /*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43774  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43775  *    Source Port Number field in the IPv4 or IPv6 packets.
43776  */
43777 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
43778 
43779 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK  (0xFFFF0000U)
43780 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
43781 /*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43782  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43783  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43784  */
43785 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
43786 /*! @} */
43787 
43788 /*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
43789 /*! @{ */
43790 
43791 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
43792 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
43793 /*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43794  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43795  *    Address field in the IPv6 packets.
43796  */
43797 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
43798 /*! @} */
43799 
43800 /*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
43801 /*! @{ */
43802 
43803 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
43804 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
43805 /*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43806  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43807  *    Address field in the IPv6 packets.
43808  */
43809 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
43810 /*! @} */
43811 
43812 /*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
43813 /*! @{ */
43814 
43815 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
43816 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
43817 /*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43818  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43819  *    Address field in the IPv6 packets.
43820  */
43821 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
43822 /*! @} */
43823 
43824 /*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
43825 /*! @{ */
43826 
43827 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
43828 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
43829 /*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43830  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43831  *    Address field in the IPv6 packets.
43832  */
43833 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
43834 /*! @} */
43835 
43836 /*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
43837 /*! @{ */
43838 
43839 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK  (0x1U)
43840 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
43841 /*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43842  *    Address matching is enabled for IPv6 packets.
43843  *  0b0..Layer 3 Protocol is disabled
43844  *  0b1..Layer 3 Protocol is enabled
43845  */
43846 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
43847 
43848 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK  (0x4U)
43849 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
43850 /*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43851  *  0b0..Layer 3 IP SA Match is disabled
43852  *  0b1..Layer 3 IP SA Match is enabled
43853  */
43854 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
43855 
43856 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
43857 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
43858 /*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43859  *    field is enabled for inverse matching.
43860  *  0b0..Layer 3 IP SA Inverse Match is disabled
43861  *  0b1..Layer 3 IP SA Inverse Match is enabled
43862  */
43863 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
43864 
43865 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK  (0x10U)
43866 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
43867 /*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43868  *  0b0..Layer 3 IP DA Match is disabled
43869  *  0b1..Layer 3 IP DA Match is enabled
43870  */
43871 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
43872 
43873 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
43874 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
43875 /*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43876  *    Address field is enabled for inverse matching.
43877  *  0b0..Layer 3 IP DA Inverse Match is disabled
43878  *  0b1..Layer 3 IP DA Inverse Match is enabled
43879  */
43880 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
43881 
43882 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
43883 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
43884 /*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43885  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43886  */
43887 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
43888 
43889 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
43890 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
43891 /*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43892  *    bits of IP Destination Address that are matched in the IPv4 packets.
43893  */
43894 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
43895 
43896 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK  (0x10000U)
43897 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
43898 /*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43899  *    fields of UDP packets are used for matching.
43900  *  0b0..Layer 4 Protocol is disabled
43901  *  0b1..Layer 4 Protocol is enabled
43902  */
43903 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
43904 
43905 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK  (0x40000U)
43906 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
43907 /*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43908  *  0b0..Layer 4 Source Port Match is disabled
43909  *  0b1..Layer 4 Source Port Match is enabled
43910  */
43911 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
43912 
43913 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
43914 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
43915 /*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43916  *    number field is enabled for inverse matching.
43917  *  0b0..Layer 4 Source Port Inverse Match is disabled
43918  *  0b1..Layer 4 Source Port Inverse Match is enabled
43919  */
43920 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
43921 
43922 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK  (0x100000U)
43923 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
43924 /*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43925  *    Port number field is enabled for matching.
43926  *  0b0..Layer 4 Destination Port Match is disabled
43927  *  0b1..Layer 4 Destination Port Match is enabled
43928  */
43929 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
43930 
43931 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
43932 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
43933 /*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43934  *    Destination Port number field is enabled for inverse matching.
43935  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43936  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43937  */
43938 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
43939 
43940 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK  (0x7000000U)
43941 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
43942 /*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43943  *    to which the packet passed by this filter is routed.
43944  */
43945 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
43946 
43947 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
43948 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
43949 /*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43950  *    number for the packet that is passed by this L3_L4 filter.
43951  *  0b0..DMA Channel Select is disabled
43952  *  0b1..DMA Channel Select is enabled
43953  */
43954 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
43955 /*! @} */
43956 
43957 /*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
43958 /*! @{ */
43959 
43960 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK  (0xFFFFU)
43961 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
43962 /*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43963  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43964  *    Source Port Number field in the IPv4 or IPv6 packets.
43965  */
43966 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
43967 
43968 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK  (0xFFFF0000U)
43969 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
43970 /*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43971  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43972  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43973  */
43974 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
43975 /*! @} */
43976 
43977 /*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
43978 /*! @{ */
43979 
43980 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
43981 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
43982 /*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43983  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43984  *    Address field in the IPv6 packets.
43985  */
43986 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
43987 /*! @} */
43988 
43989 /*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
43990 /*! @{ */
43991 
43992 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
43993 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
43994 /*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43995  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43996  *    Address field in the IPv6 packets.
43997  */
43998 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
43999 /*! @} */
44000 
44001 /*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
44002 /*! @{ */
44003 
44004 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
44005 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
44006 /*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44007  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44008  *    Address field in the IPv6 packets.
44009  */
44010 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
44011 /*! @} */
44012 
44013 /*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
44014 /*! @{ */
44015 
44016 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
44017 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
44018 /*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44019  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44020  *    Address field in the IPv6 packets.
44021  */
44022 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
44023 /*! @} */
44024 
44025 /*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
44026 /*! @{ */
44027 
44028 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK  (0x1U)
44029 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
44030 /*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44031  *    Address matching is enabled for IPv6 packets.
44032  *  0b0..Layer 3 Protocol is disabled
44033  *  0b1..Layer 3 Protocol is enabled
44034  */
44035 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
44036 
44037 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK  (0x4U)
44038 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
44039 /*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44040  *  0b0..Layer 3 IP SA Match is disabled
44041  *  0b1..Layer 3 IP SA Match is enabled
44042  */
44043 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
44044 
44045 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
44046 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
44047 /*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44048  *    field is enabled for inverse matching.
44049  *  0b0..Layer 3 IP SA Inverse Match is disabled
44050  *  0b1..Layer 3 IP SA Inverse Match is enabled
44051  */
44052 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
44053 
44054 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK  (0x10U)
44055 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
44056 /*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44057  *  0b0..Layer 3 IP DA Match is disabled
44058  *  0b1..Layer 3 IP DA Match is enabled
44059  */
44060 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
44061 
44062 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
44063 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
44064 /*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44065  *    Address field is enabled for inverse matching.
44066  *  0b0..Layer 3 IP DA Inverse Match is disabled
44067  *  0b1..Layer 3 IP DA Inverse Match is enabled
44068  */
44069 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
44070 
44071 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
44072 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
44073 /*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44074  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44075  */
44076 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
44077 
44078 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
44079 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
44080 /*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44081  *    bits of IP Destination Address that are matched in the IPv4 packets.
44082  */
44083 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
44084 
44085 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK  (0x10000U)
44086 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
44087 /*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44088  *    fields of UDP packets are used for matching.
44089  *  0b0..Layer 4 Protocol is disabled
44090  *  0b1..Layer 4 Protocol is enabled
44091  */
44092 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
44093 
44094 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK  (0x40000U)
44095 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
44096 /*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44097  *  0b0..Layer 4 Source Port Match is disabled
44098  *  0b1..Layer 4 Source Port Match is enabled
44099  */
44100 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
44101 
44102 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
44103 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
44104 /*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44105  *    number field is enabled for inverse matching.
44106  *  0b0..Layer 4 Source Port Inverse Match is disabled
44107  *  0b1..Layer 4 Source Port Inverse Match is enabled
44108  */
44109 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
44110 
44111 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK  (0x100000U)
44112 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
44113 /*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44114  *    Port number field is enabled for matching.
44115  *  0b0..Layer 4 Destination Port Match is disabled
44116  *  0b1..Layer 4 Destination Port Match is enabled
44117  */
44118 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
44119 
44120 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
44121 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
44122 /*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44123  *    Destination Port number field is enabled for inverse matching.
44124  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44125  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44126  */
44127 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
44128 
44129 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK  (0x7000000U)
44130 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
44131 /*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44132  *    to which the packet passed by this filter is routed.
44133  */
44134 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
44135 
44136 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
44137 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
44138 /*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44139  *    number for the packet that is passed by this L3_L4 filter.
44140  *  0b0..DMA Channel Select is disabled
44141  *  0b1..DMA Channel Select is enabled
44142  */
44143 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
44144 /*! @} */
44145 
44146 /*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
44147 /*! @{ */
44148 
44149 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK  (0xFFFFU)
44150 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
44151 /*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44152  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44153  *    Source Port Number field in the IPv4 or IPv6 packets.
44154  */
44155 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
44156 
44157 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK  (0xFFFF0000U)
44158 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
44159 /*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44160  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44161  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44162  */
44163 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
44164 /*! @} */
44165 
44166 /*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
44167 /*! @{ */
44168 
44169 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
44170 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
44171 /*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44172  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44173  *    Address field in the IPv6 packets.
44174  */
44175 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
44176 /*! @} */
44177 
44178 /*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
44179 /*! @{ */
44180 
44181 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
44182 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
44183 /*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44184  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44185  *    Address field in the IPv6 packets.
44186  */
44187 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
44188 /*! @} */
44189 
44190 /*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
44191 /*! @{ */
44192 
44193 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
44194 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
44195 /*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44196  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44197  *    Address field in the IPv6 packets.
44198  */
44199 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
44200 /*! @} */
44201 
44202 /*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
44203 /*! @{ */
44204 
44205 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
44206 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
44207 /*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44208  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44209  *    Address field in the IPv6 packets.
44210  */
44211 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
44212 /*! @} */
44213 
44214 /*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
44215 /*! @{ */
44216 
44217 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK  (0x1U)
44218 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
44219 /*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44220  *    Address matching is enabled for IPv6 packets.
44221  *  0b0..Layer 3 Protocol is disabled
44222  *  0b1..Layer 3 Protocol is enabled
44223  */
44224 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
44225 
44226 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK  (0x4U)
44227 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
44228 /*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44229  *  0b0..Layer 3 IP SA Match is disabled
44230  *  0b1..Layer 3 IP SA Match is enabled
44231  */
44232 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
44233 
44234 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
44235 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
44236 /*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44237  *    field is enabled for inverse matching.
44238  *  0b0..Layer 3 IP SA Inverse Match is disabled
44239  *  0b1..Layer 3 IP SA Inverse Match is enabled
44240  */
44241 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
44242 
44243 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK  (0x10U)
44244 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
44245 /*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44246  *  0b0..Layer 3 IP DA Match is disabled
44247  *  0b1..Layer 3 IP DA Match is enabled
44248  */
44249 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
44250 
44251 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
44252 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
44253 /*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44254  *    Address field is enabled for inverse matching.
44255  *  0b0..Layer 3 IP DA Inverse Match is disabled
44256  *  0b1..Layer 3 IP DA Inverse Match is enabled
44257  */
44258 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
44259 
44260 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
44261 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
44262 /*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44263  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44264  */
44265 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
44266 
44267 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
44268 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
44269 /*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44270  *    bits of IP Destination Address that are matched in the IPv4 packets.
44271  */
44272 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
44273 
44274 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK  (0x10000U)
44275 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
44276 /*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44277  *    fields of UDP packets are used for matching.
44278  *  0b0..Layer 4 Protocol is disabled
44279  *  0b1..Layer 4 Protocol is enabled
44280  */
44281 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
44282 
44283 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK  (0x40000U)
44284 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
44285 /*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44286  *  0b0..Layer 4 Source Port Match is disabled
44287  *  0b1..Layer 4 Source Port Match is enabled
44288  */
44289 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
44290 
44291 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
44292 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
44293 /*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44294  *    number field is enabled for inverse matching.
44295  *  0b0..Layer 4 Source Port Inverse Match is disabled
44296  *  0b1..Layer 4 Source Port Inverse Match is enabled
44297  */
44298 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
44299 
44300 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK  (0x100000U)
44301 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
44302 /*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44303  *    Port number field is enabled for matching.
44304  *  0b0..Layer 4 Destination Port Match is disabled
44305  *  0b1..Layer 4 Destination Port Match is enabled
44306  */
44307 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
44308 
44309 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
44310 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
44311 /*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44312  *    Destination Port number field is enabled for inverse matching.
44313  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44314  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44315  */
44316 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
44317 
44318 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK  (0x7000000U)
44319 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
44320 /*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44321  *    to which the packet passed by this filter is routed.
44322  */
44323 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
44324 
44325 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
44326 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
44327 /*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44328  *    number for the packet that is passed by this L3_L4 filter.
44329  *  0b0..DMA Channel Select is disabled
44330  *  0b1..DMA Channel Select is enabled
44331  */
44332 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
44333 /*! @} */
44334 
44335 /*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
44336 /*! @{ */
44337 
44338 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK  (0xFFFFU)
44339 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
44340 /*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44341  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44342  *    Source Port Number field in the IPv4 or IPv6 packets.
44343  */
44344 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
44345 
44346 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK  (0xFFFF0000U)
44347 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
44348 /*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44349  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44350  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44351  */
44352 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
44353 /*! @} */
44354 
44355 /*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
44356 /*! @{ */
44357 
44358 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
44359 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
44360 /*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44361  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44362  *    Address field in the IPv6 packets.
44363  */
44364 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
44365 /*! @} */
44366 
44367 /*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
44368 /*! @{ */
44369 
44370 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
44371 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
44372 /*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44373  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44374  *    Address field in the IPv6 packets.
44375  */
44376 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
44377 /*! @} */
44378 
44379 /*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
44380 /*! @{ */
44381 
44382 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
44383 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
44384 /*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44385  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44386  *    Address field in the IPv6 packets.
44387  */
44388 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
44389 /*! @} */
44390 
44391 /*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
44392 /*! @{ */
44393 
44394 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
44395 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
44396 /*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44397  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44398  *    Address field in the IPv6 packets.
44399  */
44400 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
44401 /*! @} */
44402 
44403 /*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
44404 /*! @{ */
44405 
44406 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK  (0x1U)
44407 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
44408 /*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44409  *    Address matching is enabled for IPv6 packets.
44410  *  0b0..Layer 3 Protocol is disabled
44411  *  0b1..Layer 3 Protocol is enabled
44412  */
44413 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
44414 
44415 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK  (0x4U)
44416 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
44417 /*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44418  *  0b0..Layer 3 IP SA Match is disabled
44419  *  0b1..Layer 3 IP SA Match is enabled
44420  */
44421 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
44422 
44423 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
44424 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
44425 /*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44426  *    field is enabled for inverse matching.
44427  *  0b0..Layer 3 IP SA Inverse Match is disabled
44428  *  0b1..Layer 3 IP SA Inverse Match is enabled
44429  */
44430 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
44431 
44432 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK  (0x10U)
44433 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
44434 /*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44435  *  0b0..Layer 3 IP DA Match is disabled
44436  *  0b1..Layer 3 IP DA Match is enabled
44437  */
44438 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
44439 
44440 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
44441 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
44442 /*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44443  *    Address field is enabled for inverse matching.
44444  *  0b0..Layer 3 IP DA Inverse Match is disabled
44445  *  0b1..Layer 3 IP DA Inverse Match is enabled
44446  */
44447 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
44448 
44449 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
44450 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
44451 /*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44452  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44453  */
44454 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
44455 
44456 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
44457 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
44458 /*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44459  *    bits of IP Destination Address that are matched in the IPv4 packets.
44460  */
44461 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
44462 
44463 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK  (0x10000U)
44464 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
44465 /*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44466  *    fields of UDP packets are used for matching.
44467  *  0b0..Layer 4 Protocol is disabled
44468  *  0b1..Layer 4 Protocol is enabled
44469  */
44470 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
44471 
44472 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK  (0x40000U)
44473 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
44474 /*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44475  *  0b0..Layer 4 Source Port Match is disabled
44476  *  0b1..Layer 4 Source Port Match is enabled
44477  */
44478 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
44479 
44480 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
44481 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
44482 /*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44483  *    number field is enabled for inverse matching.
44484  *  0b0..Layer 4 Source Port Inverse Match is disabled
44485  *  0b1..Layer 4 Source Port Inverse Match is enabled
44486  */
44487 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
44488 
44489 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK  (0x100000U)
44490 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
44491 /*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44492  *    Port number field is enabled for matching.
44493  *  0b0..Layer 4 Destination Port Match is disabled
44494  *  0b1..Layer 4 Destination Port Match is enabled
44495  */
44496 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
44497 
44498 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
44499 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
44500 /*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44501  *    Destination Port number field is enabled for inverse matching.
44502  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44503  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44504  */
44505 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
44506 
44507 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK  (0x7000000U)
44508 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
44509 /*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44510  *    to which the packet passed by this filter is routed.
44511  */
44512 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
44513 
44514 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
44515 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
44516 /*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44517  *    number for the packet that is passed by this L3_L4 filter.
44518  *  0b0..DMA Channel Select is disabled
44519  *  0b1..DMA Channel Select is enabled
44520  */
44521 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
44522 /*! @} */
44523 
44524 /*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
44525 /*! @{ */
44526 
44527 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK  (0xFFFFU)
44528 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
44529 /*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44530  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44531  *    Source Port Number field in the IPv4 or IPv6 packets.
44532  */
44533 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
44534 
44535 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK  (0xFFFF0000U)
44536 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
44537 /*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44538  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44539  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44540  */
44541 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
44542 /*! @} */
44543 
44544 /*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
44545 /*! @{ */
44546 
44547 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
44548 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
44549 /*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44550  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44551  *    Address field in the IPv6 packets.
44552  */
44553 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
44554 /*! @} */
44555 
44556 /*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
44557 /*! @{ */
44558 
44559 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
44560 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
44561 /*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44562  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44563  *    Address field in the IPv6 packets.
44564  */
44565 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
44566 /*! @} */
44567 
44568 /*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
44569 /*! @{ */
44570 
44571 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
44572 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
44573 /*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44574  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44575  *    Address field in the IPv6 packets.
44576  */
44577 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
44578 /*! @} */
44579 
44580 /*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
44581 /*! @{ */
44582 
44583 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
44584 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
44585 /*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44586  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44587  *    Address field in the IPv6 packets.
44588  */
44589 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
44590 /*! @} */
44591 
44592 /*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
44593 /*! @{ */
44594 
44595 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK  (0x1U)
44596 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
44597 /*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44598  *    Address matching is enabled for IPv6 packets.
44599  *  0b0..Layer 3 Protocol is disabled
44600  *  0b1..Layer 3 Protocol is enabled
44601  */
44602 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
44603 
44604 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK  (0x4U)
44605 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
44606 /*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44607  *  0b0..Layer 3 IP SA Match is disabled
44608  *  0b1..Layer 3 IP SA Match is enabled
44609  */
44610 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
44611 
44612 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
44613 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
44614 /*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44615  *    field is enabled for inverse matching.
44616  *  0b0..Layer 3 IP SA Inverse Match is disabled
44617  *  0b1..Layer 3 IP SA Inverse Match is enabled
44618  */
44619 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
44620 
44621 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK  (0x10U)
44622 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
44623 /*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44624  *  0b0..Layer 3 IP DA Match is disabled
44625  *  0b1..Layer 3 IP DA Match is enabled
44626  */
44627 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
44628 
44629 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
44630 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
44631 /*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44632  *    Address field is enabled for inverse matching.
44633  *  0b0..Layer 3 IP DA Inverse Match is disabled
44634  *  0b1..Layer 3 IP DA Inverse Match is enabled
44635  */
44636 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
44637 
44638 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
44639 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
44640 /*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44641  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44642  */
44643 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
44644 
44645 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
44646 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
44647 /*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44648  *    bits of IP Destination Address that are matched in the IPv4 packets.
44649  */
44650 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
44651 
44652 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK  (0x10000U)
44653 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
44654 /*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44655  *    fields of UDP packets are used for matching.
44656  *  0b0..Layer 4 Protocol is disabled
44657  *  0b1..Layer 4 Protocol is enabled
44658  */
44659 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
44660 
44661 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK  (0x40000U)
44662 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
44663 /*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44664  *  0b0..Layer 4 Source Port Match is disabled
44665  *  0b1..Layer 4 Source Port Match is enabled
44666  */
44667 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
44668 
44669 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
44670 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
44671 /*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44672  *    number field is enabled for inverse matching.
44673  *  0b0..Layer 4 Source Port Inverse Match is disabled
44674  *  0b1..Layer 4 Source Port Inverse Match is enabled
44675  */
44676 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
44677 
44678 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK  (0x100000U)
44679 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
44680 /*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44681  *    Port number field is enabled for matching.
44682  *  0b0..Layer 4 Destination Port Match is disabled
44683  *  0b1..Layer 4 Destination Port Match is enabled
44684  */
44685 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
44686 
44687 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
44688 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
44689 /*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44690  *    Destination Port number field is enabled for inverse matching.
44691  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44692  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44693  */
44694 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
44695 
44696 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK  (0x7000000U)
44697 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
44698 /*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44699  *    to which the packet passed by this filter is routed.
44700  */
44701 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
44702 
44703 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
44704 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
44705 /*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44706  *    number for the packet that is passed by this L3_L4 filter.
44707  *  0b0..DMA Channel Select is disabled
44708  *  0b1..DMA Channel Select is enabled
44709  */
44710 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
44711 /*! @} */
44712 
44713 /*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
44714 /*! @{ */
44715 
44716 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK  (0xFFFFU)
44717 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
44718 /*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44719  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44720  *    Source Port Number field in the IPv4 or IPv6 packets.
44721  */
44722 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
44723 
44724 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK  (0xFFFF0000U)
44725 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
44726 /*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44727  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44728  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44729  */
44730 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
44731 /*! @} */
44732 
44733 /*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
44734 /*! @{ */
44735 
44736 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
44737 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
44738 /*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44739  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44740  *    Address field in the IPv6 packets.
44741  */
44742 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
44743 /*! @} */
44744 
44745 /*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
44746 /*! @{ */
44747 
44748 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
44749 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
44750 /*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44751  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44752  *    Address field in the IPv6 packets.
44753  */
44754 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
44755 /*! @} */
44756 
44757 /*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
44758 /*! @{ */
44759 
44760 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
44761 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
44762 /*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44763  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44764  *    Address field in the IPv6 packets.
44765  */
44766 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
44767 /*! @} */
44768 
44769 /*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
44770 /*! @{ */
44771 
44772 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
44773 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
44774 /*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44775  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44776  *    Address field in the IPv6 packets.
44777  */
44778 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
44779 /*! @} */
44780 
44781 /*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
44782 /*! @{ */
44783 
44784 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK  (0x1U)
44785 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
44786 /*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
44787  *    Address matching is enabled for IPv6 packets.
44788  *  0b0..Layer 3 Protocol is disabled
44789  *  0b1..Layer 3 Protocol is enabled
44790  */
44791 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
44792 
44793 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK  (0x4U)
44794 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
44795 /*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
44796  *  0b0..Layer 3 IP SA Match is disabled
44797  *  0b1..Layer 3 IP SA Match is enabled
44798  */
44799 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
44800 
44801 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
44802 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
44803 /*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
44804  *    field is enabled for inverse matching.
44805  *  0b0..Layer 3 IP SA Inverse Match is disabled
44806  *  0b1..Layer 3 IP SA Inverse Match is enabled
44807  */
44808 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
44809 
44810 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK  (0x10U)
44811 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
44812 /*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
44813  *  0b0..Layer 3 IP DA Match is disabled
44814  *  0b1..Layer 3 IP DA Match is enabled
44815  */
44816 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
44817 
44818 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
44819 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
44820 /*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
44821  *    Address field is enabled for inverse matching.
44822  *  0b0..Layer 3 IP DA Inverse Match is disabled
44823  *  0b1..Layer 3 IP DA Inverse Match is enabled
44824  */
44825 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
44826 
44827 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
44828 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
44829 /*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
44830  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
44831  */
44832 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
44833 
44834 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
44835 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
44836 /*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
44837  *    bits of IP Destination Address that are matched in the IPv4 packets.
44838  */
44839 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
44840 
44841 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK  (0x10000U)
44842 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
44843 /*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
44844  *    fields of UDP packets are used for matching.
44845  *  0b0..Layer 4 Protocol is disabled
44846  *  0b1..Layer 4 Protocol is enabled
44847  */
44848 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
44849 
44850 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK  (0x40000U)
44851 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
44852 /*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
44853  *  0b0..Layer 4 Source Port Match is disabled
44854  *  0b1..Layer 4 Source Port Match is enabled
44855  */
44856 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
44857 
44858 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
44859 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
44860 /*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
44861  *    number field is enabled for inverse matching.
44862  *  0b0..Layer 4 Source Port Inverse Match is disabled
44863  *  0b1..Layer 4 Source Port Inverse Match is enabled
44864  */
44865 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
44866 
44867 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK  (0x100000U)
44868 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
44869 /*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
44870  *    Port number field is enabled for matching.
44871  *  0b0..Layer 4 Destination Port Match is disabled
44872  *  0b1..Layer 4 Destination Port Match is enabled
44873  */
44874 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
44875 
44876 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
44877 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
44878 /*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
44879  *    Destination Port number field is enabled for inverse matching.
44880  *  0b0..Layer 4 Destination Port Inverse Match is disabled
44881  *  0b1..Layer 4 Destination Port Inverse Match is enabled
44882  */
44883 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
44884 
44885 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK  (0x7000000U)
44886 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
44887 /*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
44888  *    to which the packet passed by this filter is routed.
44889  */
44890 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
44891 
44892 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
44893 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
44894 /*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
44895  *    number for the packet that is passed by this L3_L4 filter.
44896  *  0b0..DMA Channel Select is disabled
44897  *  0b1..DMA Channel Select is enabled
44898  */
44899 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
44900 /*! @} */
44901 
44902 /*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
44903 /*! @{ */
44904 
44905 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK  (0xFFFFU)
44906 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
44907 /*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
44908  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
44909  *    Source Port Number field in the IPv4 or IPv6 packets.
44910  */
44911 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
44912 
44913 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK  (0xFFFF0000U)
44914 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
44915 /*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
44916  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
44917  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
44918  */
44919 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
44920 /*! @} */
44921 
44922 /*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
44923 /*! @{ */
44924 
44925 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
44926 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
44927 /*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
44928  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
44929  *    Address field in the IPv6 packets.
44930  */
44931 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
44932 /*! @} */
44933 
44934 /*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
44935 /*! @{ */
44936 
44937 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
44938 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
44939 /*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
44940  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
44941  *    Address field in the IPv6 packets.
44942  */
44943 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
44944 /*! @} */
44945 
44946 /*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
44947 /*! @{ */
44948 
44949 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
44950 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
44951 /*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
44952  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
44953  *    Address field in the IPv6 packets.
44954  */
44955 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
44956 /*! @} */
44957 
44958 /*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
44959 /*! @{ */
44960 
44961 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
44962 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
44963 /*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
44964  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
44965  *    Address field in the IPv6 packets.
44966  */
44967 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
44968 /*! @} */
44969 
44970 /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
44971 /*! @{ */
44972 
44973 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
44974 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
44975 /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
44976  *  0b0..Timestamp is disabled
44977  *  0b1..Timestamp is enabled
44978  */
44979 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
44980 
44981 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
44982 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
44983 /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
44984  *  0b0..Coarse method is used to update system timestamp
44985  *  0b1..Fine method is used to update system timestamp
44986  */
44987 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
44988 
44989 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
44990 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
44991 /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
44992  *    with the value specified in the MAC_System_Time_Seconds_Update and
44993  *    MAC_System_Time_Nanoseconds_Update registers.
44994  *  0b0..Timestamp is not initialized
44995  *  0b1..Timestamp is initialized
44996  */
44997 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
44998 
44999 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
45000 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
45001 /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
45002  *    with the value specified in MAC_System_Time_Seconds_Update and
45003  *    MAC_System_Time_Nanoseconds_Update registers.
45004  *  0b0..Timestamp is not updated
45005  *  0b1..Timestamp is updated
45006  */
45007 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
45008 
45009 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
45010 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
45011 /*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
45012  *    register is updated in the PTP block for fine correction.
45013  *  0b0..Addend Register is not updated
45014  *  0b1..Addend Register is updated
45015  */
45016 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
45017 
45018 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
45019 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
45020 /*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
45021  *  0b0..Presentation Time Generation is disabled
45022  *  0b1..Presentation Time Generation is enabled
45023  */
45024 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
45025 
45026 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
45027 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
45028 /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
45029  *    enabled for all packets received by the MAC.
45030  *  0b0..Timestamp for All Packets disabled
45031  *  0b1..Timestamp for All Packets enabled
45032  */
45033 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
45034 
45035 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
45036 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
45037 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
45038  *    register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
45039  *    the timestamp (High) seconds.
45040  *  0b0..Timestamp Digital or Binary Rollover Control is disabled
45041  *  0b1..Timestamp Digital or Binary Rollover Control is enabled
45042  */
45043 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
45044 
45045 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
45046 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
45047 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
45048  *    1588 version 2 format is used to process the PTP packets.
45049  *  0b0..PTP Packet Processing for Version 2 Format is disabled
45050  *  0b1..PTP Packet Processing for Version 2 Format is enabled
45051  */
45052 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
45053 
45054 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
45055 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
45056 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
45057  *    processes the PTP packets encapsulated directly in the Ethernet packets.
45058  *  0b0..Processing of PTP over Ethernet Packets is disabled
45059  *  0b1..Processing of PTP over Ethernet Packets is enabled
45060  */
45061 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
45062 
45063 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
45064 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
45065 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
45066  *    receiver processes the PTP packets encapsulated in IPv6-UDP packets.
45067  *  0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
45068  *  0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
45069  */
45070 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
45071 
45072 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
45073 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
45074 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
45075  *    receiver processes the PTP packets encapsulated in IPv4-UDP packets.
45076  *  0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
45077  *  0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
45078  */
45079 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
45080 
45081 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
45082 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
45083 /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
45084  *    snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
45085  *  0b0..Timestamp Snapshot for Event Messages is disabled
45086  *  0b1..Timestamp Snapshot for Event Messages is enabled
45087  */
45088 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
45089 
45090 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
45091 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
45092 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
45093  *    is taken only for the messages that are relevant to the master node.
45094  *  0b0..Snapshot for Messages Relevant to Master is disabled
45095  *  0b1..Snapshot for Messages Relevant to Master is enabled
45096  */
45097 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
45098 
45099 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
45100 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
45101 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
45102  *    decide the set of PTP packet types for which snapshot needs to be taken.
45103  */
45104 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
45105 
45106 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
45107 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
45108 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
45109  *    address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
45110  *    directly sent over Ethernet.
45111  *  0b0..MAC Address for PTP Packet Filtering is disabled
45112  *  0b1..MAC Address for PTP Packet Filtering is enabled
45113  */
45114 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
45115 
45116 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK  (0x80000U)
45117 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
45118 /*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
45119  *    the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
45120  *    correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
45121  *    operation.
45122  *  0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
45123  *  0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
45124  */
45125 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
45126 
45127 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
45128 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
45129 /*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
45130  *    reference System Time input for the following: - To take the timestamp provided as status - To insert
45131  *    the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
45132  *    enabled.
45133  *  0b0..External System Time Input is disabled
45134  *  0b1..External System Time Input is enabled
45135  */
45136 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
45137 
45138 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
45139 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
45140 /*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
45141  *    transmit timestamp status even if it is not read by the software.
45142  *  0b0..Transmit Timestamp Status Mode is disabled
45143  *  0b1..Transmit Timestamp Status Mode is enabled
45144  */
45145 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
45146 
45147 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
45148 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
45149 /*! AV8021ASMEN - AV 802.
45150  *  0b0..AV 802.1AS Mode is disabled
45151  *  0b1..AV 802.1AS Mode is enabled
45152  */
45153 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
45154 /*! @} */
45155 
45156 /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
45157 /*! @{ */
45158 
45159 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
45160 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
45161 /*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
45162  *    represented in nanoseconds multiplied by 2^8.
45163  */
45164 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
45165 
45166 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
45167 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
45168 /*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
45169  *    cycle (of clk_ptp_i) with the contents of the sub-second register.
45170  */
45171 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
45172 /*! @} */
45173 
45174 /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
45175 /*! @{ */
45176 
45177 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
45178 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
45179 /*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
45180  *    System Time maintained by the MAC.
45181  */
45182 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
45183 /*! @} */
45184 
45185 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
45186 /*! @{ */
45187 
45188 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
45189 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
45190 /*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0.
45191  */
45192 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
45193 /*! @} */
45194 
45195 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
45196 /*! @{ */
45197 
45198 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
45199 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
45200 /*! TSS - Timestamp Seconds The value in this field is the seconds part of the update.
45201  */
45202 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
45203 /*! @} */
45204 
45205 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
45206 /*! @{ */
45207 
45208 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
45209 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
45210 /*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update.
45211  */
45212 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
45213 
45214 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
45215 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
45216 /*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
45217  *  0b0..Add time
45218  *  0b1..Subtract time
45219  */
45220 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
45221 /*! @} */
45222 
45223 /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
45224 /*! @{ */
45225 
45226 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK  (0xFFFFFFFFU)
45227 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
45228 /*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
45229  *    Accumulator register to achieve time synchronization.
45230  */
45231 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
45232 /*! @} */
45233 
45234 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
45235 /*! @{ */
45236 
45237 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
45238 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
45239 /*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value.
45240  */
45241 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
45242 /*! @} */
45243 
45244 /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
45245 /*! @{ */
45246 
45247 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
45248 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
45249 /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
45250  *    the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
45251  *  0b1..Timestamp Seconds Overflow status detected
45252  *  0b0..Timestamp Seconds Overflow status not detected
45253  */
45254 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
45255 
45256 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
45257 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
45258 /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
45259  *    time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
45260  *    MAC_PPS0_Target_Time_Nanoseconds registers.
45261  *  0b1..Timestamp Target Time Reached status detected
45262  *  0b0..Timestamp Target Time Reached status not detected
45263  */
45264 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
45265 
45266 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
45267 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
45268 /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
45269  *  0b1..Auxiliary Timestamp Trigger Snapshot status detected
45270  *  0b0..Auxiliary Timestamp Trigger Snapshot status not detected
45271  */
45272 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
45273 
45274 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
45275 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
45276 /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
45277  *    in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
45278  *  0b1..Timestamp Target Time Error status detected
45279  *  0b0..Timestamp Target Time Error status not detected
45280  */
45281 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
45282 
45283 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
45284 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
45285 /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
45286  *    the value of system time is greater than or equal to the value specified in the
45287  *    MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
45288  *  0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
45289  *  0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
45290  */
45291 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
45292 
45293 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
45294 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
45295 /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
45296  *    in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
45297  *  0b1..Timestamp Target Time Error status detected
45298  *  0b0..Timestamp Target Time Error status not detected
45299  */
45300 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
45301 
45302 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
45303 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
45304 /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
45305  *    the value of system time is greater than or equal to the value specified in the
45306  *    MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
45307  *  0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
45308  *  0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
45309  */
45310 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
45311 
45312 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
45313 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
45314 /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
45315  *    in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
45316  *  0b1..Timestamp Target Time Error status detected
45317  *  0b0..Timestamp Target Time Error status not detected
45318  */
45319 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
45320 
45321 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
45322 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
45323 /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
45324  *    that the value of system time is greater than or equal to the value specified in the
45325  *    MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
45326  *  0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
45327  *  0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
45328  */
45329 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
45330 
45331 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
45332 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
45333 /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
45334  *    in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
45335  *  0b1..Timestamp Target Time Error status detected
45336  *  0b0..Timestamp Target Time Error status not detected
45337  */
45338 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
45339 
45340 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
45341 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
45342 /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
45343  *    transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
45344  *    the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
45345  *  0b1..Tx Timestamp Status Interrupt status detected
45346  *  0b0..Tx Timestamp Status Interrupt status not detected
45347  */
45348 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
45349 
45350 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
45351 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
45352 /*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
45353  *    trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
45354  */
45355 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
45356 
45357 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
45358 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
45359 /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
45360  *    timestamp snapshot FIFO is full and external trigger was set.
45361  *  0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
45362  *  0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
45363  */
45364 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
45365 
45366 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
45367 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
45368 /*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO.
45369  */
45370 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
45371 /*! @} */
45372 
45373 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
45374 /*! @{ */
45375 
45376 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
45377 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
45378 /*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
45379  *    of the Transmit packet's captured timestamp.
45380  */
45381 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
45382 
45383 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
45384 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
45385 /*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
45386  *    following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
45387  *    register is reset - The timestamp of the previous packet is overwritten with timestamp of the
45388  *    current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
45389  *  0b1..Transmit Timestamp Status Missed status detected
45390  *  0b0..Transmit Timestamp Status Missed status not detected
45391  */
45392 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
45393 /*! @} */
45394 
45395 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
45396 /*! @{ */
45397 
45398 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
45399 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
45400 /*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
45401  *    field of Transmit packet's captured timestamp.
45402  */
45403 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
45404 /*! @} */
45405 
45406 /*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
45407 /*! @{ */
45408 
45409 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
45410 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
45411 /*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
45412  *  0b0..Auxiliary Snapshot FIFO Clear is disabled
45413  *  0b1..Auxiliary Snapshot FIFO Clear is enabled
45414  */
45415 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
45416 
45417 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
45418 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
45419 /*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
45420  *  0b0..Auxiliary Snapshot $i is disabled
45421  *  0b1..Auxiliary Snapshot $i is enabled
45422  */
45423 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
45424 
45425 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
45426 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
45427 /*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
45428  *  0b0..Auxiliary Snapshot $i is disabled
45429  *  0b1..Auxiliary Snapshot $i is enabled
45430  */
45431 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
45432 
45433 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
45434 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
45435 /*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
45436  *  0b0..Auxiliary Snapshot $i is disabled
45437  *  0b1..Auxiliary Snapshot $i is enabled
45438  */
45439 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
45440 
45441 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
45442 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
45443 /*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
45444  *  0b0..Auxiliary Snapshot $i is disabled
45445  *  0b1..Auxiliary Snapshot $i is enabled
45446  */
45447 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
45448 /*! @} */
45449 
45450 /*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
45451 /*! @{ */
45452 
45453 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
45454 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
45455 /*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp.
45456  */
45457 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
45458 /*! @} */
45459 
45460 /*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
45461 /*! @{ */
45462 
45463 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
45464 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
45465 /*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp.
45466  */
45467 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
45468 /*! @} */
45469 
45470 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
45471 /*! @{ */
45472 
45473 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
45474 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
45475 /*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
45476  *    asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
45477  */
45478 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
45479 /*! @} */
45480 
45481 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
45482 /*! @{ */
45483 
45484 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
45485 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
45486 /*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
45487  *    asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
45488  */
45489 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
45490 /*! @} */
45491 
45492 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
45493 /*! @{ */
45494 
45495 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
45496 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
45497 /*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
45498  *    defined by the Ingress Correction expression.
45499  */
45500 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
45501 /*! @} */
45502 
45503 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
45504 /*! @{ */
45505 
45506 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
45507 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
45508 /*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
45509  *    correction value as defined by the Egress Correction expression.
45510  */
45511 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
45512 /*! @} */
45513 
45514 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
45515 /*! @{ */
45516 
45517 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
45518 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
45519 /*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
45520  *    part of the ingress path correction value as defined by the "Ingress Correction" expression.
45521  */
45522 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
45523 /*! @} */
45524 
45525 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
45526 /*! @{ */
45527 
45528 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
45529 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
45530 /*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
45531  *    part of the egress path correction value as defined by the "Egress Correction" expression.
45532  */
45533 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
45534 /*! @} */
45535 
45536 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
45537 /*! @{ */
45538 
45539 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
45540 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
45541 /*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
45542  *    nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
45543  *    ingress timestamp is taken.
45544  */
45545 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
45546 
45547 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
45548 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
45549 /*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
45550  *    sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
45551  *    where the ingress timestamp is taken.
45552  */
45553 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
45554 /*! @} */
45555 
45556 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
45557 /*! @{ */
45558 
45559 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
45560 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
45561 /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
45562  *    sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
45563  *    the output ports (phy_txd_o) of the MAC.
45564  */
45565 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
45566 
45567 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
45568 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
45569 /*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
45570  *    nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
45571  *    ports (phy_txd_o) of the MAC.
45572  */
45573 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
45574 /*! @} */
45575 
45576 /*! @name MAC_PPS_CONTROL - PPS Control */
45577 /*! @{ */
45578 
45579 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
45580 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
45581 /*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal.
45582  */
45583 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
45584 
45585 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK     (0x10U)
45586 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT    (4U)
45587 /*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
45588  *  0b0..Flexible PPS Output Mode is disabled
45589  *  0b1..Flexible PPS Output Mode is enabled
45590  */
45591 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
45592 
45593 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
45594 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
45595 /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
45596  *    registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
45597  *    output signal:
45598  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45599  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45600  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45601  *        ptp_pps_o output port
45602  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45603  *  0b01..Reserved
45604  */
45605 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
45606 
45607 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK    (0x80U)
45608 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT   (7U)
45609 /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
45610  *  0b1..0th PPS instance is enabled to operate in MCGR mode
45611  *  0b0..0th PPS instance is enabled to operate in PPS mode
45612  */
45613 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
45614 
45615 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK    (0xF00U)
45616 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT   (8U)
45617 /*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal.
45618  */
45619 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
45620 
45621 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
45622 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
45623 /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
45624  *    registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
45625  *    output signal.
45626  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45627  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45628  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45629  *        ptp_pps_o output port
45630  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45631  *  0b01..Reserved
45632  */
45633 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
45634 
45635 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK    (0x8000U)
45636 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT   (15U)
45637 /*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
45638  *  0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
45639  *  0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
45640  */
45641 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
45642 
45643 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK    (0xF0000U)
45644 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT   (16U)
45645 /*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal.
45646  */
45647 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
45648 
45649 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
45650 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
45651 /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
45652  *    registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
45653  *    output signal.
45654  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45655  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45656  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45657  *        ptp_pps_o output port
45658  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45659  *  0b01..Reserved
45660  */
45661 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
45662 
45663 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK    (0x800000U)
45664 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT   (23U)
45665 /*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
45666  *  0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
45667  *  0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
45668  */
45669 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
45670 
45671 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK    (0xF000000U)
45672 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT   (24U)
45673 /*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal.
45674  */
45675 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
45676 
45677 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
45678 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
45679 /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
45680  *    registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
45681  *    output signal.
45682  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
45683  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
45684  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
45685  *        ptp_pps_o output port
45686  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
45687  *  0b01..Reserved
45688  */
45689 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
45690 
45691 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK    (0x80000000U)
45692 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT   (31U)
45693 /*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode.
45694  */
45695 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
45696 /*! @} */
45697 
45698 /*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
45699 /*! @{ */
45700 
45701 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
45702 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
45703 /*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds.
45704  */
45705 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
45706 /*! @} */
45707 
45708 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
45709 /*! @{ */
45710 
45711 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
45712 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
45713 /*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45714  */
45715 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
45716 
45717 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
45718 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
45719 /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45720  *    PPS_CONTROL register is programmed to 010 or 011.
45721  *  0b1..PPS Target Time Register Busy is detected
45722  *  0b0..PPS Target Time Register Busy status is not detected
45723  */
45724 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
45725 /*! @} */
45726 
45727 /*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
45728 /*! @{ */
45729 
45730 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK  (0xFFFFFFFFU)
45731 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
45732 /*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45733  */
45734 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
45735 /*! @} */
45736 
45737 /*! @name MAC_PPS0_WIDTH - PPS0 Width */
45738 /*! @{ */
45739 
45740 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK   (0xFFFFFFFFU)
45741 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT  (0U)
45742 /*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
45743  *    corresponding falling edge of PPS0 signal output.
45744  */
45745 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
45746 /*! @} */
45747 
45748 /*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
45749 /*! @{ */
45750 
45751 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
45752 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
45753 /*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds.
45754  */
45755 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
45756 /*! @} */
45757 
45758 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
45759 /*! @{ */
45760 
45761 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
45762 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
45763 /*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45764  */
45765 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
45766 
45767 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
45768 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
45769 /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45770  *    PPS_CONTROL register is programmed to 010 or 011.
45771  *  0b1..PPS Target Time Register Busy is detected
45772  *  0b0..PPS Target Time Register Busy status is not detected
45773  */
45774 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
45775 /*! @} */
45776 
45777 /*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
45778 /*! @{ */
45779 
45780 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK  (0xFFFFFFFFU)
45781 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
45782 /*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45783  */
45784 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
45785 /*! @} */
45786 
45787 /*! @name MAC_PPS1_WIDTH - PPS1 Width */
45788 /*! @{ */
45789 
45790 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK   (0xFFFFFFFFU)
45791 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT  (0U)
45792 /*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
45793  *    corresponding falling edge of PPS0 signal output.
45794  */
45795 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
45796 /*! @} */
45797 
45798 /*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
45799 /*! @{ */
45800 
45801 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
45802 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
45803 /*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds.
45804  */
45805 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
45806 /*! @} */
45807 
45808 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
45809 /*! @{ */
45810 
45811 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
45812 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
45813 /*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45814  */
45815 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
45816 
45817 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
45818 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
45819 /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45820  *    PPS_CONTROL register is programmed to 010 or 011.
45821  *  0b1..PPS Target Time Register Busy is detected
45822  *  0b0..PPS Target Time Register Busy status is not detected
45823  */
45824 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
45825 /*! @} */
45826 
45827 /*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
45828 /*! @{ */
45829 
45830 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK  (0xFFFFFFFFU)
45831 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
45832 /*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45833  */
45834 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
45835 /*! @} */
45836 
45837 /*! @name MAC_PPS2_WIDTH - PPS2 Width */
45838 /*! @{ */
45839 
45840 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK   (0xFFFFFFFFU)
45841 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT  (0U)
45842 /*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
45843  *    corresponding falling edge of PPS0 signal output.
45844  */
45845 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
45846 /*! @} */
45847 
45848 /*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
45849 /*! @{ */
45850 
45851 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
45852 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
45853 /*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds.
45854  */
45855 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
45856 /*! @} */
45857 
45858 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
45859 /*! @{ */
45860 
45861 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
45862 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
45863 /*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
45864  */
45865 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
45866 
45867 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
45868 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
45869 /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
45870  *    PPS_CONTROL register is programmed to 010 or 011.
45871  *  0b1..PPS Target Time Register Busy is detected
45872  *  0b0..PPS Target Time Register Busy status is not detected
45873  */
45874 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
45875 /*! @} */
45876 
45877 /*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
45878 /*! @{ */
45879 
45880 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK  (0xFFFFFFFFU)
45881 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
45882 /*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
45883  */
45884 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
45885 /*! @} */
45886 
45887 /*! @name MAC_PPS3_WIDTH - PPS3 Width */
45888 /*! @{ */
45889 
45890 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK   (0xFFFFFFFFU)
45891 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT  (0U)
45892 /*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
45893  *    corresponding falling edge of PPS0 signal output.
45894  */
45895 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
45896 /*! @} */
45897 
45898 /*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
45899 /*! @{ */
45900 
45901 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK      (0x1U)
45902 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT     (0U)
45903 /*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
45904  *  0b0..PTP Offload feature is disabled
45905  *  0b1..PTP Offload feature is enabled
45906  */
45907 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
45908 
45909 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK    (0x2U)
45910 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT   (1U)
45911 /*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
45912  *    periodically based on interval programmed or trigger from application, when the MAC is
45913  *    programmed to be in Clock Master mode.
45914  *  0b0..Automatic PTP SYNC message is disabled
45915  *  0b1..Automatic PTP SYNC message is enabled
45916  */
45917 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
45918 
45919 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK   (0x4U)
45920 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT  (2U)
45921 /*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
45922  *    is generated periodically based on interval programmed or trigger from application, when the
45923  *    MAC is programmed to be in Peer-to-Peer Transparent mode.
45924  *  0b0..Automatic PTP Pdelay_Req message is disabled
45925  *  0b1..Automatic PTP Pdelay_Req message is enabled
45926  */
45927 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
45928 
45929 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK  (0x10U)
45930 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
45931 /*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
45932  *  0b0..Automatic PTP SYNC message Trigger is disabled
45933  *  0b1..Automatic PTP SYNC message Trigger is enabled
45934  */
45935 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
45936 
45937 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
45938 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
45939 /*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
45940  *  0b0..Automatic PTP Pdelay_Req message Trigger is disabled
45941  *  0b1..Automatic PTP Pdelay_Req message Trigger is enabled
45942  */
45943 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
45944 
45945 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK     (0x40U)
45946 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT    (6U)
45947 /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
45948  *    Request and Delay response is not generated for received SYNC and Delay request packet
45949  *    respectively, as required by the programmed mode.
45950  *  0b1..PTO Delay Request/Response response generation is disabled
45951  *  0b0..PTO Delay Request/Response response generation is enabled
45952  */
45953 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
45954 
45955 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK     (0x80U)
45956 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT    (7U)
45957 /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
45958  *    Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
45959  *    request packet, as required by the programmed mode.
45960  *  0b1..Peer Delay Response response generation is disabled
45961  *  0b0..Peer Delay Response response generation is enabled
45962  */
45963 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
45964 
45965 #define ENET_QOS_MAC_PTO_CONTROL_DN_MASK         (0xFF00U)
45966 #define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT        (8U)
45967 /*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating.
45968  */
45969 #define ENET_QOS_MAC_PTO_CONTROL_DN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
45970 /*! @} */
45971 
45972 /*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
45973 /*! @{ */
45974 
45975 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
45976 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
45977 /*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node.
45978  */
45979 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
45980 /*! @} */
45981 
45982 /*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
45983 /*! @{ */
45984 
45985 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
45986 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
45987 /*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node.
45988  */
45989 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
45990 /*! @} */
45991 
45992 /*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
45993 /*! @{ */
45994 
45995 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
45996 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
45997 /*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node.
45998  */
45999 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
46000 /*! @} */
46001 
46002 /*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
46003 /*! @{ */
46004 
46005 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
46006 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
46007 /*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
46008  *    message when the PTP node is Master.
46009  */
46010 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
46011 
46012 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
46013 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
46014 /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
46015  *  0b110..Reserved
46016  *  0b000..DelayReq generated for every received SYNC
46017  *  0b100..for every 16 SYNC messages
46018  *  0b001..DelayReq generated every alternate reception of SYNC
46019  *  0b101..for every 32 SYNC messages
46020  *  0b010..for every 4 SYNC messages
46021  *  0b011..for every 8 SYNC messages
46022  */
46023 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
46024 
46025 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
46026 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
46027 /*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node.
46028  */
46029 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
46030 /*! @} */
46031 
46032 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */
46033 /*! @{ */
46034 
46035 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK  (0x2U)
46036 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
46037 /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
46038  *  0b0..Drop Transmit Status is disabled
46039  *  0b1..Drop Transmit Status is enabled
46040  */
46041 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
46042 
46043 #define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK     (0x4U)
46044 #define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT    (2U)
46045 /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
46046  *  0b0..Strict priority (SP)
46047  *  0b1..Weighted Strict Priority (WSP)
46048  */
46049 #define ENET_QOS_MTL_OPERATION_MODE_RAA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
46050 
46051 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK  (0x60U)
46052 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
46053 /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
46054  *  0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
46055  *  0b11..Strict priority algorithm
46056  *  0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
46057  *  0b00..WRR algorithm
46058  */
46059 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
46060 
46061 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
46062 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
46063 /*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
46064  *  0b0..Counters Preset is disabled
46065  *  0b1..Counters Preset is enabled
46066  */
46067 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
46068 
46069 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK  (0x200U)
46070 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
46071 /*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
46072  *  0b0..Counters are not reset
46073  *  0b1..All counters are reset
46074  */
46075 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
46076 
46077 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK    (0x8000U)
46078 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT   (15U)
46079 /*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
46080  *  0b0..Flexible Rx parser is disabled
46081  *  0b1..Flexible Rx parser is enabled
46082  */
46083 #define ENET_QOS_MTL_OPERATION_MODE_FRPE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
46084 /*! @} */
46085 
46086 /*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
46087 /*! @{ */
46088 
46089 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK         (0x1U)
46090 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT        (0U)
46091 /*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
46092  *  0b0..FIFO Debug Access is disabled
46093  *  0b1..FIFO Debug Access is enabled
46094  */
46095 #define ENET_QOS_MTL_DBG_CTL_FDBGEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
46096 
46097 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK         (0x2U)
46098 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT        (1U)
46099 /*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
46100  *    the FIFO is read, write, and debug access.
46101  *  0b0..Debug Mode Access to FIFO is disabled
46102  *  0b1..Debug Mode Access to FIFO is enabled
46103  */
46104 #define ENET_QOS_MTL_DBG_CTL_DBGMOD(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
46105 
46106 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK         (0xCU)
46107 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT        (2U)
46108 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
46109  *  0b11..All four bytes are valid
46110  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
46111  *  0b01..Byte 0 and Byte 1 are valid
46112  *  0b00..Byte 0 valid
46113  */
46114 #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
46115 
46116 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK       (0x60U)
46117 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT      (5U)
46118 /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
46119  *  0b01..Control Word/Normal Status
46120  *  0b11..EOP Data/EOP
46121  *  0b00..Packet Data
46122  *  0b10..SOP Data/Last Status
46123  */
46124 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
46125 
46126 #define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK         (0x100U)
46127 #define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT        (8U)
46128 /*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
46129  *  0b0..Reset All Pointers is disabled
46130  *  0b1..Reset All Pointers is enabled
46131  */
46132 #define ENET_QOS_MTL_DBG_CTL_RSTALL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
46133 
46134 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK         (0x200U)
46135 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT        (9U)
46136 /*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
46137  *    currently-selected FIFO are reset when FIFO Debug Access is enabled.
46138  *  0b0..Reset Pointers of Selected FIFO is disabled
46139  *  0b1..Reset Pointers of Selected FIFO is enabled
46140  */
46141 #define ENET_QOS_MTL_DBG_CTL_RSTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
46142 
46143 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK       (0x400U)
46144 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT      (10U)
46145 /*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
46146  *  0b0..FIFO Read is disabled
46147  *  0b1..FIFO Read is enabled
46148  */
46149 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
46150 
46151 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK       (0x800U)
46152 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT      (11U)
46153 /*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
46154  *    FIFO when FIFO Debug Access is enabled.
46155  *  0b0..FIFO Write is disabled
46156  *  0b1..FIFO Write is enabled
46157  */
46158 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
46159 
46160 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK        (0x3000U)
46161 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT       (12U)
46162 /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
46163  *  0b11..Rx FIFO
46164  *  0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
46165  *  0b00..Tx FIFO
46166  *  0b01..Tx Status FIFO (only read access when SLVMOD is set)
46167  */
46168 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
46169 
46170 #define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK          (0x4000U)
46171 #define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT         (14U)
46172 /*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
46173  *    generated when EOP of received packet is written to the Rx FIFO.
46174  *  0b0..Receive Packet Available Interrupt Status is disabled
46175  *  0b1..Receive Packet Available Interrupt Status is enabled
46176  */
46177 #define ENET_QOS_MTL_DBG_CTL_PKTIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
46178 
46179 #define ENET_QOS_MTL_DBG_CTL_STSIE_MASK          (0x8000U)
46180 #define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT         (15U)
46181 /*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
46182  *    generated when Transmit status is available in slave mode.
46183  *  0b0..Transmit Packet Available Interrupt Status is disabled
46184  *  0b1..Transmit Packet Available Interrupt Status is enabled
46185  */
46186 #define ENET_QOS_MTL_DBG_CTL_STSIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
46187 /*! @} */
46188 
46189 /*! @name MTL_DBG_STS - FIFO Debug Status */
46190 /*! @{ */
46191 
46192 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK       (0x1U)
46193 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT      (0U)
46194 /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
46195  *    MAC and content of the following fields is not valid: - All other fields of this register - All
46196  *    fields of the MTL_FIFO_DEBUG_DATA register
46197  *  0b1..FIFO Busy detected
46198  *  0b0..FIFO Busy not detected
46199  */
46200 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
46201 
46202 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK       (0x6U)
46203 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT      (1U)
46204 /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
46205  *  0b01..Control Word/Normal Status
46206  *  0b11..EOP Data/EOP
46207  *  0b00..Packet Data
46208  *  0b10..SOP Data/Last Status
46209  */
46210 #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
46211 
46212 #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK         (0x18U)
46213 #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT        (3U)
46214 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
46215  *  0b11..All four bytes are valid
46216  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
46217  *  0b01..Byte 0 and Byte 1 are valid
46218  *  0b00..Byte 0 valid
46219  */
46220 #define ENET_QOS_MTL_DBG_STS_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
46221 
46222 #define ENET_QOS_MTL_DBG_STS_PKTI_MASK           (0x100U)
46223 #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT          (8U)
46224 /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
46225  *    written the EOP of received packet to the Rx FIFO.
46226  *  0b1..Receive Packet Available Interrupt Status detected
46227  *  0b0..Receive Packet Available Interrupt Status not detected
46228  */
46229 #define ENET_QOS_MTL_DBG_STS_PKTI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
46230 
46231 #define ENET_QOS_MTL_DBG_STS_STSI_MASK           (0x200U)
46232 #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT          (9U)
46233 /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
46234  *    mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
46235  *  0b1..Transmit Status Available Interrupt Status detected
46236  *  0b0..Transmit Status Available Interrupt Status not detected
46237  */
46238 #define ENET_QOS_MTL_DBG_STS_STSI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
46239 
46240 #define ENET_QOS_MTL_DBG_STS_LOCR_MASK           (0xFFFF8000U)
46241 #define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT          (15U)
46242 /*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO.
46243  */
46244 #define ENET_QOS_MTL_DBG_STS_LOCR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
46245 /*! @} */
46246 
46247 /*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
46248 /*! @{ */
46249 
46250 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
46251 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
46252 /*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
46253  *    data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
46254  */
46255 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
46256 /*! @} */
46257 
46258 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
46259 /*! @{ */
46260 
46261 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK  (0x1U)
46262 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
46263 /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
46264  *  0b1..Queue 0 Interrupt status detected
46265  *  0b0..Queue 0 Interrupt status not detected
46266  */
46267 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
46268 
46269 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK  (0x2U)
46270 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
46271 /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
46272  *  0b1..Queue 1 Interrupt status detected
46273  *  0b0..Queue 1 Interrupt status not detected
46274  */
46275 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
46276 
46277 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK  (0x4U)
46278 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
46279 /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
46280  *  0b1..Queue 2 Interrupt status detected
46281  *  0b0..Queue 2 Interrupt status not detected
46282  */
46283 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
46284 
46285 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK  (0x8U)
46286 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
46287 /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
46288  *  0b1..Queue 3 Interrupt status detected
46289  *  0b0..Queue 3 Interrupt status not detected
46290  */
46291 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
46292 
46293 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK  (0x10U)
46294 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
46295 /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
46296  *  0b1..Queue 4 Interrupt status detected
46297  *  0b0..Queue 4 Interrupt status not detected
46298  */
46299 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
46300 
46301 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
46302 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
46303 /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
46304  *  0b1..Debug Interrupt status detected
46305  *  0b0..Debug Interrupt status not detected
46306  */
46307 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
46308 
46309 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
46310 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
46311 /*! ESTIS - EST (TAS- 802.
46312  *  0b1..EST (TAS- 802.1Qbv) Interrupt status detected
46313  *  0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
46314  */
46315 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
46316 
46317 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
46318 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
46319 /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
46320  *  0b1..MTL Rx Parser Interrupt status detected
46321  *  0b0..MTL Rx Parser Interrupt status not detected
46322  */
46323 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
46324 /*! @} */
46325 
46326 /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
46327 /*! @{ */
46328 
46329 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK  (0x7U)
46330 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
46331 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
46332  *    in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
46333  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
46334  *    field is valid when the Q0DDMACH field is reset.
46335  */
46336 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
46337 
46338 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK  (0x10U)
46339 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
46340 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
46341  *    the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
46342  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
46343  *    Ethernet DA address.
46344  *  0b0..Queue 0 disabled for DA-based DMA Channel Selection
46345  *  0b1..Queue 0 enabled for DA-based DMA Channel Selection
46346  */
46347 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
46348 
46349 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK  (0x700U)
46350 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
46351 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
46352  *    in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
46353  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
46354  *    field is valid when the Q1DDMACH field is reset.
46355  */
46356 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
46357 
46358 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK  (0x1000U)
46359 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
46360 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
46361  *    the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
46362  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
46363  *    Ethernet DA address.
46364  *  0b0..Queue 1 disabled for DA-based DMA Channel Selection
46365  *  0b1..Queue 1 enabled for DA-based DMA Channel Selection
46366  */
46367 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
46368 
46369 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK  (0x70000U)
46370 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
46371 /*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
46372  *    in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
46373  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
46374  *    field is valid when the Q2DDMACH field is reset.
46375  */
46376 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
46377 
46378 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK  (0x100000U)
46379 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
46380 /*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
46381  *    the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
46382  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
46383  *    Ethernet DA address.
46384  *  0b0..Queue 2 disabled for DA-based DMA Channel Selection
46385  *  0b1..Queue 2 enabled for DA-based DMA Channel Selection
46386  */
46387 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
46388 
46389 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK  (0x7000000U)
46390 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
46391 /*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
46392  *    in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
46393  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
46394  *    field is valid when the Q3DDMACH field is reset.
46395  */
46396 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
46397 
46398 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK  (0x10000000U)
46399 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
46400 /*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
46401  *    indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
46402  *    in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
46403  *    or the Ethernet DA address.
46404  *  0b0..Queue 3 disabled for DA-based DMA Channel Selection
46405  *  0b1..Queue 3 enabled for DA-based DMA Channel Selection
46406  */
46407 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
46408 /*! @} */
46409 
46410 /*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
46411 /*! @{ */
46412 
46413 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK  (0x7U)
46414 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
46415 /*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
46416  *    in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
46417  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
46418  *    field is valid when the Q4DDMACH field is reset.
46419  */
46420 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
46421 
46422 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK  (0x10U)
46423 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
46424 /*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
46425  *    the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
46426  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
46427  *    Ethernet DA address.
46428  *  0b0..Queue 4 disabled for DA-based DMA Channel Selection
46429  *  0b1..Queue 4 enabled for DA-based DMA Channel Selection
46430  */
46431 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
46432 /*! @} */
46433 
46434 /*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
46435 /*! @{ */
46436 
46437 #define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK          (0x1U)
46438 #define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT         (0U)
46439 /*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
46440  *    is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
46441  *    current list.
46442  *  0b0..EST offset Mode is disabled
46443  *  0b1..EST offset Mode is enabled
46444  */
46445 #define ENET_QOS_MTL_TBS_CTRL_ESTM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
46446 
46447 #define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK          (0x2U)
46448 #define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT         (1U)
46449 /*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
46450  *  0b0..LEOS field is invalid
46451  *  0b1..LEOS field is valid
46452  */
46453 #define ENET_QOS_MTL_TBS_CTRL_LEOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
46454 
46455 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK         (0x70U)
46456 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT        (4U)
46457 /*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time.
46458  */
46459 #define ENET_QOS_MTL_TBS_CTRL_LEGOS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
46460 
46461 #define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK          (0xFFFFFF00U)
46462 #define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT         (8U)
46463 /*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
46464  *    Launch time to compute the Launch Expiry time.
46465  */
46466 #define ENET_QOS_MTL_TBS_CTRL_LEOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
46467 /*! @} */
46468 
46469 /*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
46470 /*! @{ */
46471 
46472 #define ENET_QOS_MTL_EST_CONTROL_EEST_MASK       (0x1U)
46473 #define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT      (0U)
46474 /*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
46475  *  0b0..EST is disabled
46476  *  0b1..EST is enabled
46477  */
46478 #define ENET_QOS_MTL_EST_CONTROL_EEST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
46479 
46480 #define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK       (0x2U)
46481 #define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT      (1U)
46482 /*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
46483  *    that it currently owns (SWOL) and the hardware should switch to the new list based on the new
46484  *    BTR.
46485  *  0b0..Switch to S/W owned list is disabled
46486  *  0b1..Switch to S/W owned list is enabled
46487  */
46488 #define ENET_QOS_MTL_EST_CONTROL_SSWL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
46489 
46490 #define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK       (0x10U)
46491 #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT      (4U)
46492 /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
46493  *    Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
46494  *  0b1..Do not Drop frames during Frame Size Error
46495  *  0b0..Drop frames during Frame Size Error
46496  */
46497 #define ENET_QOS_MTL_EST_CONTROL_DDBF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
46498 
46499 #define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK       (0x20U)
46500 #define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT      (5U)
46501 /*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
46502  *    to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
46503  *    field of this register) GCL iterations are dropped.
46504  *  0b0..Do not Drop Frames causing Scheduling Error
46505  *  0b1..Drop Frames causing Scheduling Error
46506  */
46507 #define ENET_QOS_MTL_EST_CONTROL_DFBS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
46508 
46509 #define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK       (0xC0U)
46510 #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT      (6U)
46511 /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
46512  *    reporting an HLBS error defined in EST_STATUS register.
46513  *  0b10..16 iterations
46514  *  0b11..32 iterations
46515  *  0b00..4 iterations
46516  *  0b01..8 iterations
46517  */
46518 #define ENET_QOS_MTL_EST_CONTROL_LCSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
46519 
46520 #define ENET_QOS_MTL_EST_CONTROL_TILS_MASK       (0x700U)
46521 #define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT      (8U)
46522 /*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
46523  *    programmed Time Interval values used in the Gate Control Lists.
46524  */
46525 #define ENET_QOS_MTL_EST_CONTROL_TILS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
46526 
46527 #define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK       (0xFFF000U)
46528 #define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT      (12U)
46529 /*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
46530  *    added to the current time to compensate for all the implementation pipeline delays such as the CDC
46531  *    sync delay, buffering delays, data path delays etc.
46532  */
46533 #define ENET_QOS_MTL_EST_CONTROL_CTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
46534 
46535 #define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK       (0xFF000000U)
46536 #define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT      (24U)
46537 /*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds.
46538  */
46539 #define ENET_QOS_MTL_EST_CONTROL_PTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
46540 /*! @} */
46541 
46542 /*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
46543 /*! @{ */
46544 
46545 #define ENET_QOS_MTL_EST_STATUS_SWLC_MASK        (0x1U)
46546 #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT       (0U)
46547 /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
46548  *    switched to the SWOL, and the SWOL bit has been updated to that effect.
46549  *  0b1..Switch to S/W owned list Complete detected
46550  *  0b0..Switch to S/W owned list Complete not detected
46551  */
46552 #define ENET_QOS_MTL_EST_STATUS_SWLC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
46553 
46554 #define ENET_QOS_MTL_EST_STATUS_BTRE_MASK        (0x2U)
46555 #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT       (1U)
46556 /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
46557  *    value is less than current time.
46558  *  0b1..BTR Error detected
46559  *  0b0..BTR Error not detected
46560  */
46561 #define ENET_QOS_MTL_EST_STATUS_BTRE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
46562 
46563 #define ENET_QOS_MTL_EST_STATUS_HLBF_MASK        (0x4U)
46564 #define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT       (2U)
46565 /*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
46566  *    Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
46567  *    equal to the duration needed for frame size (or frame fragment size when preemption is
46568  *    enabled) transmission.
46569  *  0b1..Head-Of-Line Blocking due to Frame Size detected
46570  *  0b0..Head-Of-Line Blocking due to Frame Size not detected
46571  */
46572 #define ENET_QOS_MTL_EST_STATUS_HLBF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
46573 
46574 #define ENET_QOS_MTL_EST_STATUS_HLBS_MASK        (0x8U)
46575 #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT       (3U)
46576 /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
46577  *    and get scheduled even after 4 iterations of the GCL.
46578  *  0b1..Head-Of-Line Blocking due to Scheduling detected
46579  *  0b0..Head-Of-Line Blocking due to Scheduling not detected
46580  */
46581 #define ENET_QOS_MTL_EST_STATUS_HLBS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
46582 
46583 #define ENET_QOS_MTL_EST_STATUS_CGCE_MASK        (0x10U)
46584 #define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT       (4U)
46585 /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
46586  *    programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
46587  *    Cycle Time (CTR).
46588  *  0b1..Constant Gate Control Error detected
46589  *  0b0..Constant Gate Control Error not detected
46590  */
46591 #define ENET_QOS_MTL_EST_STATUS_CGCE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
46592 
46593 #define ENET_QOS_MTL_EST_STATUS_SWOL_MASK        (0x80U)
46594 #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT       (7U)
46595 /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
46596  *    when "1" indicates the Gate Control list "1" is owned by the software.
46597  *  0b1..Gate control list number "1" is owned by software
46598  *  0b0..Gate control list number "0" is owned by software
46599  */
46600 #define ENET_QOS_MTL_EST_STATUS_SWOL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
46601 
46602 #define ENET_QOS_MTL_EST_STATUS_BTRL_MASK        (0xF00U)
46603 #define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT       (8U)
46604 /*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
46605  *    =< New BTR + (N * New Cycle Time) becomes true.
46606  */
46607 #define ENET_QOS_MTL_EST_STATUS_BTRL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
46608 
46609 #define ENET_QOS_MTL_EST_STATUS_CGSN_MASK        (0xF0000U)
46610 #define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT       (16U)
46611 /*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list.
46612  */
46613 #define ENET_QOS_MTL_EST_STATUS_CGSN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
46614 /*! @} */
46615 
46616 /*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
46617 /*! @{ */
46618 
46619 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK     (0x1FU)
46620 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT    (0U)
46621 /*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
46622  *    error/timeout described in HLBS field of status register.
46623  */
46624 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
46625 /*! @} */
46626 
46627 /*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
46628 /*! @{ */
46629 
46630 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
46631 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
46632 /*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
46633  *    error described in HLBF field of status register.
46634  */
46635 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
46636 /*! @} */
46637 
46638 /*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
46639 /*! @{ */
46640 
46641 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
46642 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
46643 /*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
46644  *    indicated in HBFQ field of this register.
46645  */
46646 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
46647 
46648 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
46649 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
46650 /*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
46651  *    experiencing HLBF error (see HLBF field of status register).
46652  */
46653 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
46654 /*! @} */
46655 
46656 /*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
46657 /*! @{ */
46658 
46659 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK   (0x1U)
46660 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT  (0U)
46661 /*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
46662  *    change is successful and the hardware has switched to the new list.
46663  *  0b0..Interrupt for Switch List is disabled
46664  *  0b1..Interrupt for Switch List is enabled
46665  */
46666 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
46667 
46668 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK   (0x2U)
46669 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT  (1U)
46670 /*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
46671  *  0b0..Interrupt for BTR Error is disabled
46672  *  0b1..Interrupt for BTR Error is enabled
46673  */
46674 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
46675 
46676 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK   (0x4U)
46677 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT  (2U)
46678 /*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
46679  *    due to Frame Size error occurs and is indicated in the status.
46680  *  0b0..Interrupt for HLBF is disabled
46681  *  0b1..Interrupt for HLBF is enabled
46682  */
46683 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
46684 
46685 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK   (0x8U)
46686 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT  (3U)
46687 /*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
46688  *    due to Scheduling issue and is indicated in the status.
46689  *  0b0..Interrupt for HLBS is disabled
46690  *  0b1..Interrupt for HLBS is enabled
46691  */
46692 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
46693 
46694 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK   (0x10U)
46695 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT  (4U)
46696 /*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
46697  *    Error occurs and is indicated in the status.
46698  *  0b0..Interrupt for CGCE is disabled
46699  *  0b1..Interrupt for CGCE is enabled
46700  */
46701 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
46702 /*! @} */
46703 
46704 /*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
46705 /*! @{ */
46706 
46707 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK   (0x1U)
46708 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT  (0U)
46709 /*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
46710  *  0b0..Start Read/Write Op disabled
46711  *  0b1..Start Read/Write Op enabled
46712  */
46713 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
46714 
46715 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK   (0x2U)
46716 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT  (1U)
46717 /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
46718  *  0b1..Read Operation
46719  *  0b0..Write Operation
46720  */
46721 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
46722 
46723 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK   (0x4U)
46724 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT  (2U)
46725 /*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
46726  *    related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
46727  *  0b0..Gate Control Related Registers are disabled
46728  *  0b1..Gate Control Related Registers are enabled
46729  */
46730 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
46731 
46732 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK   (0x10U)
46733 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT  (4U)
46734 /*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
46735  *    Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
46736  *    used to determine which bank to use.
46737  *  0b0..Debug Mode is disabled
46738  *  0b1..Debug Mode is enabled
46739  */
46740 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
46741 
46742 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK   (0x20U)
46743 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT  (5U)
46744 /*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
46745  *    Bank 0 (GCL0 and corresponding Time related registers).
46746  *  0b0..R/W in debug mode should be directed to Bank 0
46747  *  0b1..R/W in debug mode should be directed to Bank 1
46748  */
46749 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
46750 
46751 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK   (0x1FF00U)
46752 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT  (8U)
46753 /*! ADDR - Gate Control List Address: (GCLA when GCRR is "0").
46754  */
46755 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
46756 
46757 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK   (0x100000U)
46758 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT  (20U)
46759 /*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
46760  *    registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
46761  *  0b0..ERR0 is disabled
46762  *  0b1..ERR1 is enabled
46763  */
46764 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
46765 
46766 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
46767 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
46768 /*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
46769  *    enables the ECC error injection feature.
46770  *  0b0..EST ECC Inject Error is disabled
46771  *  0b1..EST ECC Inject Error is enabled
46772  */
46773 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
46774 
46775 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
46776 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
46777 /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
46778  *    following are the errors inserted based on the value encoded in this field.
46779  *  0b00..Insert 1 bit error
46780  *  0b11..Insert 1 bit error in address field
46781  *  0b01..Insert 2 bit errors
46782  *  0b10..Insert 3 bit errors
46783  */
46784 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
46785 /*! @} */
46786 
46787 /*! @name MTL_EST_GCL_DATA - EST GCL Data */
46788 /*! @{ */
46789 
46790 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK       (0xFFFFFFFFU)
46791 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT      (0U)
46792 /*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register.
46793  */
46794 #define ENET_QOS_MTL_EST_GCL_DATA_GCD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
46795 /*! @} */
46796 
46797 /*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
46798 /*! @{ */
46799 
46800 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK      (0x3U)
46801 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT     (0U)
46802 /*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
46803  *    bytes over 64 bytes required in non-final fragments of preempted frames.
46804  */
46805 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
46806 
46807 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK       (0x1F00U)
46808 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT      (8U)
46809 /*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
46810  *    preemptable, when '0' Queue is classified as express.
46811  */
46812 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
46813 
46814 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK       (0x10000000U)
46815 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT      (28U)
46816 /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
46817  *  0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
46818  *  0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
46819  */
46820 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
46821 /*! @} */
46822 
46823 /*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
46824 /*! @{ */
46825 
46826 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK       (0xFFFFU)
46827 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT      (0U)
46828 /*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
46829  *    the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
46830  *    transmission or any preemptable frames that are queued for transmission.
46831  */
46832 #define ENET_QOS_MTL_FPE_ADVANCE_HADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
46833 
46834 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK       (0xFFFF0000U)
46835 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT      (16U)
46836 /*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
46837  *    to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
46838  *    absence of there being any express frames available for transmission.
46839  */
46840 #define ENET_QOS_MTL_FPE_ADVANCE_RADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
46841 /*! @} */
46842 
46843 /*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
46844 /*! @{ */
46845 
46846 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
46847 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
46848 /*! NVE - Number of valid entries in the Instruction table This control indicates the number of
46849  *    valid entries in the Instruction Memory.
46850  */
46851 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
46852 
46853 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
46854 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
46855 /*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
46856  *    parsable entries in the Instruction Memory.
46857  */
46858 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
46859 
46860 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
46861 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
46862 /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
46863  *    and waiting for a new packet for processing.
46864  *  0b1..RX Parser in Idle state
46865  *  0b0..RX Parser not in Idle state
46866  */
46867 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
46868 /*! @} */
46869 
46870 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
46871 /*! @{ */
46872 
46873 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
46874 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
46875 /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
46876  *    address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
46877  *    this bit is set to 1.
46878  *  0b1..Number of Valid Entries Overflow Interrupt Status detected
46879  *  0b0..Number of Valid Entries Overflow Interrupt Status not detected
46880  */
46881 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
46882 
46883 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
46884 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
46885 /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
46886  *    number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
46887  *    MTL_RXP_CONTROL register),then this bit is set to 1.
46888  *  0b1..Number of Parsable Entries Overflow Interrupt Status detected
46889  *  0b0..Number of Parsable Entries Overflow Interrupt Status not detected
46890  */
46891 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
46892 
46893 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
46894 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
46895 /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
46896  *    'Frame Offset' found to be more than EOF offset, then then this bit is set.
46897  *  0b1..Frame Offset Overflow Interrupt Status detected
46898  *  0b0..Frame Offset Overflow Interrupt Status not detected
46899  */
46900 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
46901 
46902 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
46903 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
46904 /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
46905  *    packet by setting RF=1 in the instruction memory, then this bit is set to 1.
46906  *  0b1..Packet Dropped due to RF Interrupt Status detected
46907  *  0b0..Packet Dropped due to RF Interrupt Status not detected
46908  */
46909 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
46910 
46911 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
46912 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
46913 /*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
46914  *  0b0..Number of Valid Entries Overflow Interrupt is disabled
46915  *  0b1..Number of Valid Entries Overflow Interrupt is enabled
46916  */
46917 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
46918 
46919 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
46920 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
46921 /*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
46922  *  0b0..Number of Parsable Entries Overflow Interrupt is disabled
46923  *  0b1..Number of Parsable Entries Overflow Interrupt is enabled
46924  */
46925 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
46926 
46927 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
46928 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
46929 /*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
46930  *  0b0..Frame Offset Overflow Interrupt is disabled
46931  *  0b1..Frame Offset Overflow Interrupt is enabled
46932  */
46933 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
46934 
46935 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
46936 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
46937 /*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
46938  *  0b0..Packet Drop due to RF Interrupt is disabled
46939  *  0b1..Packet Drop due to RF Interrupt is enabled
46940  */
46941 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
46942 /*! @} */
46943 
46944 /*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
46945 /*! @{ */
46946 
46947 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK     (0x7FFFFFFFU)
46948 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT    (0U)
46949 /*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1.
46950  */
46951 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
46952 
46953 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK  (0x80000000U)
46954 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
46955 /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
46956  *    MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
46957  *  0b1..Rx Parser Drop count overflow occurred
46958  *  0b0..Rx Parser Drop count overflow not occurred
46959  */
46960 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
46961 /*! @} */
46962 
46963 /*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
46964 /*! @{ */
46965 
46966 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK    (0x7FFFFFFFU)
46967 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT   (0U)
46968 /*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
46969  *    following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
46970  *    address > EOF data entry address The counter is cleared when the register is read.
46971  */
46972 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
46973 
46974 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
46975 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
46976 /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
46977  *    MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
46978  *  0b1..Rx Parser Error count overflow occurred
46979  *  0b0..Rx Parser Error count overflow not occurred
46980  */
46981 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
46982 /*! @} */
46983 
46984 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
46985 /*! @{ */
46986 
46987 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
46988 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
46989 /*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table.
46990  */
46991 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
46992 
46993 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
46994 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
46995 /*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
46996  *  0b0..Read operation to the Rx Parser Memory
46997  *  0b1..Write operation to the Rx Parser Memory
46998  */
46999 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
47000 
47001 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
47002 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
47003 /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
47004  *    indicates to start the Read/Write operation from/to the Rx Parser Memory.
47005  *  0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
47006  *  0b0..hardware not busy
47007  */
47008 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
47009 /*! @} */
47010 
47011 /*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
47012 /*! @{ */
47013 
47014 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
47015 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
47016 /*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command.
47017  */
47018 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
47019 /*! @} */
47020 
47021 /*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
47022 /*! @{ */
47023 
47024 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK       (0x1U)
47025 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT      (0U)
47026 /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
47027  *  0b0..Flush Transmit Queue is disabled
47028  *  0b1..Flush Transmit Queue is enabled
47029  */
47030 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
47031 
47032 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK       (0x2U)
47033 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT      (1U)
47034 /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
47035  *  0b0..Transmit Store and Forward is disabled
47036  *  0b1..Transmit Store and Forward is enabled
47037  */
47038 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
47039 
47040 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK     (0xCU)
47041 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT    (2U)
47042 /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
47043  *  0b00..Not enabled
47044  *  0b10..Enabled
47045  *  0b01..Enable in AV mode (Reserved in non-AV)
47046  *  0b11..Reserved
47047  */
47048 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
47049 
47050 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK       (0x70U)
47051 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT      (4U)
47052 /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
47053  *  0b011..128
47054  *  0b100..192
47055  *  0b101..256
47056  *  0b000..32
47057  *  0b110..384
47058  *  0b111..512
47059  *  0b001..64
47060  *  0b010..96
47061  */
47062 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
47063 
47064 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK       (0x1F0000U)
47065 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT      (16U)
47066 /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
47067  */
47068 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
47069 /*! @} */
47070 
47071 /* The count of ENET_QOS_MTL_TXQX_OP_MODE */
47072 #define ENET_QOS_MTL_TXQX_OP_MODE_COUNT          (5U)
47073 
47074 /*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
47075 /*! @{ */
47076 
47077 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK  (0x7FFU)
47078 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
47079 /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
47080  *    controller because of Tx Queue Underflow.
47081  */
47082 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
47083 
47084 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK  (0x800U)
47085 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
47086 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
47087  *    Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
47088  *  0b1..Overflow detected for Underflow Packet Counter
47089  *  0b0..Overflow not detected for Underflow Packet Counter
47090  */
47091 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
47092 /*! @} */
47093 
47094 /* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
47095 #define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT          (5U)
47096 
47097 /*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
47098 /*! @{ */
47099 
47100 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK     (0x1U)
47101 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT    (0U)
47102 /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
47103  *    indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
47104  *    of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
47105  *    when PFC is enabled - Reception of 802.
47106  *  0b1..Transmit Queue in Pause status is detected
47107  *  0b0..Transmit Queue in Pause status is not detected
47108  */
47109 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
47110 
47111 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK        (0x6U)
47112 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT       (1U)
47113 /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
47114  *  0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
47115  *  0b00..Idle state
47116  *  0b01..Read state (transferring data to the MAC transmitter)
47117  *  0b10..Waiting for pending Tx Status from the MAC transmitter
47118  */
47119 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
47120 
47121 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK        (0x8U)
47122 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT       (3U)
47123 /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
47124  *    Queue Write Controller is active, and it is transferring the data to the Tx Queue.
47125  *  0b1..MTL Tx Queue Write Controller status is detected
47126  *  0b0..MTL Tx Queue Write Controller status is not detected
47127  */
47128 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
47129 
47130 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK        (0x10U)
47131 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT       (4U)
47132 /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
47133  *    is not empty and some data is left for transmission.
47134  *  0b1..MTL Tx Queue Not Empty status is detected
47135  *  0b0..MTL Tx Queue Not Empty status is not detected
47136  */
47137 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
47138 
47139 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK     (0x20U)
47140 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT    (5U)
47141 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
47142  *  0b1..MTL Tx Status FIFO Full status is detected
47143  *  0b0..MTL Tx Status FIFO Full status is not detected
47144  */
47145 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
47146 
47147 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK          (0x70000U)
47148 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT         (16U)
47149 /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
47150  */
47151 #define ENET_QOS_MTL_TXQX_DBG_PTXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
47152 
47153 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK       (0x700000U)
47154 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT      (20U)
47155 /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
47156  *    number of status in the Tx Status FIFO of this queue.
47157  */
47158 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
47159 /*! @} */
47160 
47161 /* The count of ENET_QOS_MTL_TXQX_DBG */
47162 #define ENET_QOS_MTL_TXQX_DBG_COUNT              (5U)
47163 
47164 /*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
47165 /*! @{ */
47166 
47167 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK    (0x4U)
47168 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT   (2U)
47169 /*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
47170  *    algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
47171  *    selected for Queue 1 traffic.
47172  *  0b0..CBS Algorithm is disabled
47173  *  0b1..CBS Algorithm is enabled
47174  */
47175 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
47176 
47177 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK       (0x8U)
47178 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT      (3U)
47179 /*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
47180  *    shaper algorithm logic is not reset to zero when there is positive credit and no packet to
47181  *    transmit in Channel 1.
47182  *  0b0..Credit Control is disabled
47183  *  0b1..Credit Control is enabled
47184  */
47185 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
47186 
47187 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK      (0x70U)
47188 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT     (4U)
47189 /*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
47190  *    number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
47191  *    average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
47192  *    computed for Queue.
47193  *  0b100..16 slots
47194  *  0b000..1 slot
47195  *  0b001..2 slots
47196  *  0b010..4 slots
47197  *  0b011..8 slots
47198  *  0b101..Reserved
47199  */
47200 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
47201 /*! @} */
47202 
47203 /* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
47204 #define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT         (5U)
47205 
47206 /*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
47207 /*! @{ */
47208 
47209 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK      (0xFFFFFFU)
47210 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT     (0U)
47211 /*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot.
47212  */
47213 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
47214 /*! @} */
47215 
47216 /* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
47217 #define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT         (5U)
47218 
47219 /*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
47220 /*! @{ */
47221 
47222 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK   (0x1FFFFFU)
47223 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT  (0U)
47224 /*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
47225  *    traffic, this field contains the quantum value in bytes to be added to credit during every queue
47226  *    scanning cycle.
47227  */
47228 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
47229 /*! @} */
47230 
47231 /* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
47232 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT        (5U)
47233 
47234 /*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
47235 /*! @{ */
47236 
47237 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK   (0x3FFFU)
47238 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT  (0U)
47239 /*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
47240  *    sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
47241  */
47242 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
47243 /*! @} */
47244 
47245 /* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
47246 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT      (5U)
47247 
47248 /*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
47249 /*! @{ */
47250 
47251 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK        (0x1FFFFFFFU)
47252 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT       (0U)
47253 /*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
47254  *    required for the credit-based shaper algorithm.
47255  */
47256 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
47257 /*! @} */
47258 
47259 /* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
47260 #define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT          (5U)
47261 
47262 /*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
47263 /*! @{ */
47264 
47265 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK        (0x1FFFFFFFU)
47266 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT       (0U)
47267 /*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
47268  *    required for the credit-based shaper algorithm.
47269  */
47270 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
47271 /*! @} */
47272 
47273 /* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
47274 #define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT          (5U)
47275 
47276 /*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
47277 /*! @{ */
47278 
47279 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
47280 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
47281 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
47282  *    had an underflow while transmitting the packet.
47283  *  0b1..Transmit Queue Underflow Interrupt Status detected
47284  *  0b0..Transmit Queue Underflow Interrupt Status not detected
47285  */
47286 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
47287 
47288 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
47289 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
47290 /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
47291  *  0b1..Average Bits Per Slot Interrupt Status detected
47292  *  0b0..Average Bits Per Slot Interrupt Status not detected
47293  */
47294 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
47295 
47296 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
47297 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
47298 /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
47299  *  0b0..Transmit Queue Underflow Interrupt Status is disabled
47300  *  0b1..Transmit Queue Underflow Interrupt Status is enabled
47301  */
47302 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
47303 
47304 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
47305 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
47306 /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
47307  *    sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
47308  *  0b0..Average Bits Per Slot Interrupt is disabled
47309  *  0b1..Average Bits Per Slot Interrupt is enabled
47310  */
47311 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
47312 
47313 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
47314 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
47315 /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
47316  *    an overflow while receiving the packet.
47317  *  0b1..Receive Queue Overflow Interrupt Status detected
47318  *  0b0..Receive Queue Overflow Interrupt Status not detected
47319  */
47320 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
47321 
47322 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
47323 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
47324 /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
47325  *  0b0..Receive Queue Overflow Interrupt is disabled
47326  *  0b1..Receive Queue Overflow Interrupt is enabled
47327  */
47328 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
47329 /*! @} */
47330 
47331 /* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
47332 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT     (5U)
47333 
47334 /*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
47335 /*! @{ */
47336 
47337 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK       (0x3U)
47338 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT      (0U)
47339 /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
47340  *    (in bytes): The received packet is transferred to the application or DMA when the packet size
47341  *    within the MTL Rx queue is larger than the threshold.
47342  *  0b11..128
47343  *  0b01..32
47344  *  0b00..64
47345  *  0b10..96
47346  */
47347 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
47348 
47349 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK       (0x8U)
47350 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT      (3U)
47351 /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
47352  *    good packets (packets with no error and length less than 64 bytes), including pad-bytes and
47353  *    CRC.
47354  *  0b0..Forward Undersized Good Packets is disabled
47355  *  0b1..Forward Undersized Good Packets is enabled
47356  */
47357 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
47358 
47359 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK       (0x10U)
47360 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT      (4U)
47361 /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
47362  *    (CRC error, GMII_ER, watchdog timeout, or overflow).
47363  *  0b0..Forward Error Packets is disabled
47364  *  0b1..Forward Error Packets is enabled
47365  */
47366 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
47367 
47368 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK       (0x20U)
47369 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT      (5U)
47370 /*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
47371  *    from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
47372  *    of this register.
47373  *  0b0..Receive Queue Store and Forward is disabled
47374  *  0b1..Receive Queue Store and Forward is enabled
47375  */
47376 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
47377 
47378 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
47379 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
47380 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
47381  *    does not drop the packets which only have the errors detected by the Receive Checksum Offload
47382  *    engine.
47383  *  0b1..Dropping of TCP/IP Checksum Error Packets is disabled
47384  *  0b0..Dropping of TCP/IP Checksum Error Packets is enabled
47385  */
47386 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
47387 
47388 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK      (0x80U)
47389 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT     (7U)
47390 /*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
47391  *    based on the fill-level of Rx queue, is enabled.
47392  *  0b0..Hardware Flow Control is disabled
47393  *  0b1..Hardware Flow Control is enabled
47394  */
47395 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
47396 
47397 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK       (0xF00U)
47398 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT      (8U)
47399 /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
47400  *    the threshold (fill-level of Rx queue) at which the flow control is activated: For more
47401  *    information on encoding for this field, see RFD.
47402  */
47403 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
47404 
47405 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK       (0x3C000U)
47406 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT      (14U)
47407 /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
47408  *    control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
47409  *    activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
47410  */
47411 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
47412 
47413 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK       (0x1F00000U)
47414 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT      (20U)
47415 /*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
47416  */
47417 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
47418 /*! @} */
47419 
47420 /* The count of ENET_QOS_MTL_RXQX_OP_MODE */
47421 #define ENET_QOS_MTL_RXQX_OP_MODE_COUNT          (5U)
47422 
47423 /*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
47424 /*! @{ */
47425 
47426 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
47427 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
47428 /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
47429  *    DWC_ether_qos because of Receive queue overflow.
47430  */
47431 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
47432 
47433 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
47434 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
47435 /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
47436  *    Overflow Packet Counter field crossed the maximum limit.
47437  *  0b1..Overflow Counter overflow detected
47438  *  0b0..Overflow Counter overflow not detected
47439  */
47440 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
47441 
47442 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
47443 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
47444 /*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
47445  *    DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
47446  */
47447 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
47448 
47449 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
47450 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
47451 /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
47452  *    Missed Packet Counter crossed the maximum limit.
47453  *  0b1..Missed Packet Counter overflow detected
47454  *  0b0..Missed Packet Counter overflow not detected
47455  */
47456 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
47457 /*! @} */
47458 
47459 /* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
47460 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
47461 
47462 /*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
47463 /*! @{ */
47464 
47465 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK        (0x1U)
47466 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT       (0U)
47467 /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
47468  *    Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
47469  *  0b1..MTL Rx Queue Write Controller Active Status detected
47470  *  0b0..MTL Rx Queue Write Controller Active Status not detected
47471  */
47472 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
47473 
47474 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK        (0x6U)
47475 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT       (1U)
47476 /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
47477  *  0b11..Flushing the packet data and status
47478  *  0b00..Idle state
47479  *  0b01..Reading packet data
47480  *  0b10..Reading packet status (or timestamp)
47481  */
47482 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
47483 
47484 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK        (0x30U)
47485 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT       (4U)
47486 /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
47487  *  0b10..Rx Queue fill-level above flow-control activate threshold
47488  *  0b01..Rx Queue fill-level below flow-control deactivate threshold
47489  *  0b00..Rx Queue empty
47490  *  0b11..Rx Queue full
47491  */
47492 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
47493 
47494 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK          (0x3FFF0000U)
47495 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT         (16U)
47496 /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
47497  */
47498 #define ENET_QOS_MTL_RXQX_DBG_PRXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
47499 /*! @} */
47500 
47501 /* The count of ENET_QOS_MTL_RXQX_DBG */
47502 #define ENET_QOS_MTL_RXQX_DBG_COUNT              (5U)
47503 
47504 /*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
47505 /*! @{ */
47506 
47507 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK     (0x7U)
47508 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT    (0U)
47509 /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
47510  */
47511 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
47512 
47513 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
47514 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
47515 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
47516  *    the packet data to the ARI interface such that the entire packet data of currently-selected
47517  *    queue is transmitted before switching to other queue.
47518  *  0b0..Receive Queue Packet Arbitration is disabled
47519  *  0b1..Receive Queue Packet Arbitration is enabled
47520  */
47521 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
47522 /*! @} */
47523 
47524 /* The count of ENET_QOS_MTL_RXQX_CTRL */
47525 #define ENET_QOS_MTL_RXQX_CTRL_COUNT             (5U)
47526 
47527 /*! @name DMA_MODE - DMA Bus Mode */
47528 /*! @{ */
47529 
47530 #define ENET_QOS_DMA_MODE_SWR_MASK               (0x1U)
47531 #define ENET_QOS_DMA_MODE_SWR_SHIFT              (0U)
47532 /*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
47533  *    all internal registers of the DMA, MTL, and MAC.
47534  *  0b0..Software Reset is disabled
47535  *  0b1..Software Reset is enabled
47536  */
47537 #define ENET_QOS_DMA_MODE_SWR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
47538 
47539 #define ENET_QOS_DMA_MODE_DSPW_MASK              (0x100U)
47540 #define ENET_QOS_DMA_MODE_DSPW_SHIFT             (8U)
47541 /*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
47542  *  0b0..Descriptor Posted Write is disabled
47543  *  0b1..Descriptor Posted Write is enabled
47544  */
47545 #define ENET_QOS_DMA_MODE_DSPW(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
47546 
47547 #define ENET_QOS_DMA_MODE_INTM_MASK              (0x30000U)
47548 #define ENET_QOS_DMA_MODE_INTM_SHIFT             (16U)
47549 /*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
47550  *  0b00..See above description
47551  *  0b01..See above description
47552  *  0b10..See above description
47553  *  0b11..Reserved
47554  */
47555 #define ENET_QOS_DMA_MODE_INTM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
47556 /*! @} */
47557 
47558 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
47559 /*! @{ */
47560 
47561 #define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK         (0x1U)
47562 #define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT        (0U)
47563 /*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
47564  *    of specified lengths as given below.
47565  *  0b0..Fixed Burst Length is disabled
47566  *  0b1..Fixed Burst Length is enabled
47567  */
47568 #define ENET_QOS_DMA_SYSBUS_MODE_FB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
47569 
47570 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK      (0x2U)
47571 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT     (1U)
47572 /*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
47573  *    master can select a burst length of 4 on the AXI interface.
47574  *  0b0..No effect
47575  *  0b1..AXI Burst Length 4
47576  */
47577 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
47578 
47579 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK      (0x4U)
47580 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT     (2U)
47581 /*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
47582  *    master can select a burst length of 8 on the AXI interface.
47583  *  0b0..No effect
47584  *  0b1..AXI Burst Length 8
47585  */
47586 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
47587 
47588 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK     (0x8U)
47589 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT    (3U)
47590 /*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
47591  *    master can select a burst length of 16 on the AXI interface.
47592  *  0b0..No effect
47593  *  0b1..AXI Burst Length 16
47594  */
47595 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
47596 
47597 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK       (0x400U)
47598 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT      (10U)
47599 /*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
47600  *    when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
47601  *    the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
47602  *  0b0..Automatic AXI LPI is disabled
47603  *  0b1..Automatic AXI LPI is enabled
47604  */
47605 #define ENET_QOS_DMA_SYSBUS_MODE_AALE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
47606 
47607 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK        (0x1000U)
47608 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT       (12U)
47609 /*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
47610  *    address-aligned burst transfers on Read and Write channels.
47611  *  0b0..Address-Aligned Beats is disabled
47612  *  0b1..Address-Aligned Beats is enabled
47613  */
47614 #define ENET_QOS_DMA_SYSBUS_MODE_AAL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
47615 
47616 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK    (0x2000U)
47617 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT   (13U)
47618 /*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
47619  *    performed by the EQOS-AXI master do not cross 1 KB boundary.
47620  *  0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
47621  *  0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
47622  */
47623 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
47624 
47625 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
47626 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
47627 /*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface.
47628  */
47629 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
47630 
47631 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
47632 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
47633 /*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
47634  *    outstanding request on the AXI write interface.
47635  */
47636 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
47637 
47638 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
47639 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
47640 /*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
47641  *    the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
47642  *    is received.
47643  *  0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
47644  *  0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
47645  */
47646 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
47647 
47648 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK     (0x80000000U)
47649 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT    (31U)
47650 /*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
47651  *    by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
47652  *    controller.
47653  *  0b0..Low Power Interface (LPI) is disabled
47654  *  0b1..Low Power Interface (LPI) is enabled
47655  */
47656 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
47657 /*! @} */
47658 
47659 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
47660 /*! @{ */
47661 
47662 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
47663 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
47664 /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
47665  *  0b1..DMA Channel 0 Interrupt Status detected
47666  *  0b0..DMA Channel 0 Interrupt Status not detected
47667  */
47668 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
47669 
47670 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
47671 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
47672 /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
47673  *  0b1..DMA Channel 1 Interrupt Status detected
47674  *  0b0..DMA Channel 1 Interrupt Status not detected
47675  */
47676 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
47677 
47678 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
47679 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
47680 /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
47681  *  0b1..DMA Channel 2 Interrupt Status detected
47682  *  0b0..DMA Channel 2 Interrupt Status not detected
47683  */
47684 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
47685 
47686 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
47687 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
47688 /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
47689  *  0b1..DMA Channel 3 Interrupt Status detected
47690  *  0b0..DMA Channel 3 Interrupt Status not detected
47691  */
47692 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
47693 
47694 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
47695 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
47696 /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
47697  *  0b1..DMA Channel 4 Interrupt Status detected
47698  *  0b0..DMA Channel 4 Interrupt Status not detected
47699  */
47700 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
47701 
47702 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
47703 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
47704 /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
47705  *  0b1..MTL Interrupt Status detected
47706  *  0b0..MTL Interrupt Status not detected
47707  */
47708 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
47709 
47710 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
47711 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
47712 /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
47713  *  0b1..MAC Interrupt Status detected
47714  *  0b0..MAC Interrupt Status not detected
47715  */
47716 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
47717 /*! @} */
47718 
47719 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
47720 /*! @{ */
47721 
47722 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK  (0x1U)
47723 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
47724 /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
47725  *    AXI master is active, and it is transferring data.
47726  *  0b1..AXI Master Write Channel or AHB Master Status detected
47727  *  0b0..AXI Master Write Channel or AHB Master Status not detected
47728  */
47729 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
47730 
47731 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK  (0x2U)
47732 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
47733 /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
47734  *    the AXI master is active, and it is transferring the data.
47735  *  0b1..AXI Master Read Channel Status detected
47736  *  0b0..AXI Master Read Channel Status not detected
47737  */
47738 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
47739 
47740 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK     (0xF00U)
47741 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT    (8U)
47742 /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
47743  *  0b0010..Reserved for future use
47744  *  0b0101..Running (Closing the Rx Descriptor)
47745  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47746  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47747  *  0b0011..Running (Waiting for Rx packet)
47748  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47749  *  0b0100..Suspended (Rx Descriptor Unavailable)
47750  *  0b0110..Timestamp write state
47751  */
47752 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
47753 
47754 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK     (0xF000U)
47755 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT    (12U)
47756 /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
47757  *  0b0101..Reserved for future use
47758  *  0b0111..Running (Closing Tx Descriptor)
47759  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47760  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47761  *  0b0010..Running (Waiting for status)
47762  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47763  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47764  *  0b0100..Timestamp write state
47765  */
47766 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
47767 
47768 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK     (0xF0000U)
47769 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT    (16U)
47770 /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
47771  *  0b0010..Reserved for future use
47772  *  0b0101..Running (Closing the Rx Descriptor)
47773  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47774  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47775  *  0b0011..Running (Waiting for Rx packet)
47776  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47777  *  0b0100..Suspended (Rx Descriptor Unavailable)
47778  *  0b0110..Timestamp write state
47779  */
47780 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
47781 
47782 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK     (0xF00000U)
47783 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT    (20U)
47784 /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
47785  *  0b0101..Reserved for future use
47786  *  0b0111..Running (Closing Tx Descriptor)
47787  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47788  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47789  *  0b0010..Running (Waiting for status)
47790  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47791  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47792  *  0b0100..Timestamp write state
47793  */
47794 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
47795 
47796 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK     (0xF000000U)
47797 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT    (24U)
47798 /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
47799  *  0b0010..Reserved for future use
47800  *  0b0101..Running (Closing the Rx Descriptor)
47801  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47802  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47803  *  0b0011..Running (Waiting for Rx packet)
47804  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47805  *  0b0100..Suspended (Rx Descriptor Unavailable)
47806  *  0b0110..Timestamp write state
47807  */
47808 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
47809 
47810 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK     (0xF0000000U)
47811 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT    (28U)
47812 /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
47813  *  0b0101..Reserved for future use
47814  *  0b0111..Running (Closing Tx Descriptor)
47815  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47816  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47817  *  0b0010..Running (Waiting for status)
47818  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47819  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47820  *  0b0100..Timestamp write state
47821  */
47822 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
47823 /*! @} */
47824 
47825 /*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
47826 /*! @{ */
47827 
47828 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK     (0xFU)
47829 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT    (0U)
47830 /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
47831  *  0b0010..Reserved for future use
47832  *  0b0101..Running (Closing the Rx Descriptor)
47833  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47834  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47835  *  0b0011..Running (Waiting for Rx packet)
47836  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47837  *  0b0100..Suspended (Rx Descriptor Unavailable)
47838  *  0b0110..Timestamp write state
47839  */
47840 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
47841 
47842 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK     (0xF0U)
47843 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT    (4U)
47844 /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
47845  *  0b0101..Reserved for future use
47846  *  0b0111..Running (Closing Tx Descriptor)
47847  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47848  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47849  *  0b0010..Running (Waiting for status)
47850  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47851  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47852  *  0b0100..Timestamp write state
47853  */
47854 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
47855 
47856 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK     (0xF00U)
47857 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT    (8U)
47858 /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
47859  *  0b0010..Reserved for future use
47860  *  0b0101..Running (Closing the Rx Descriptor)
47861  *  0b0001..Running (Fetching Rx Transfer Descriptor)
47862  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
47863  *  0b0011..Running (Waiting for Rx packet)
47864  *  0b0000..Stopped (Reset or Stop Receive Command issued)
47865  *  0b0100..Suspended (Rx Descriptor Unavailable)
47866  *  0b0110..Timestamp write state
47867  */
47868 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
47869 
47870 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK     (0xF000U)
47871 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT    (12U)
47872 /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
47873  *  0b0101..Reserved for future use
47874  *  0b0111..Running (Closing Tx Descriptor)
47875  *  0b0001..Running (Fetching Tx Transfer Descriptor)
47876  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
47877  *  0b0010..Running (Waiting for status)
47878  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
47879  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
47880  *  0b0100..Timestamp write state
47881  */
47882 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
47883 /*! @} */
47884 
47885 /*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
47886 /*! @{ */
47887 
47888 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
47889 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
47890 /*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
47891  *    for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
47892  *    clock cycles
47893  */
47894 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
47895 /*! @} */
47896 
47897 /*! @name DMA_TBS_CTRL - TBS Control */
47898 /*! @{ */
47899 
47900 #define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK          (0x1U)
47901 #define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT         (0U)
47902 /*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
47903  *  0b0..Fetch Time Offset is invalid
47904  *  0b1..Fetch Time Offset is valid
47905  */
47906 #define ENET_QOS_DMA_TBS_CTRL_FTOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
47907 
47908 #define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK          (0x70U)
47909 #define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT         (4U)
47910 /*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN.
47911  */
47912 #define ENET_QOS_DMA_TBS_CTRL_FGOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
47913 
47914 #define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK          (0xFFFFFF00U)
47915 #define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT         (8U)
47916 /*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
47917  *    Launch time to compute the Fetch Time.
47918  */
47919 #define ENET_QOS_DMA_TBS_CTRL_FTOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
47920 /*! @} */
47921 
47922 /*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
47923 /*! @{ */
47924 
47925 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK         (0x10000U)
47926 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT        (16U)
47927 /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
47928  *    DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
47929  *  0b0..8xPBL mode is disabled
47930  *  0b1..8xPBL mode is enabled
47931  */
47932 #define ENET_QOS_DMA_CHX_CTRL_PBLx8(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
47933 
47934 #define ENET_QOS_DMA_CHX_CTRL_DSL_MASK           (0x1C0000U)
47935 #define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT          (18U)
47936 /*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
47937  *    the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
47938  */
47939 #define ENET_QOS_DMA_CHX_CTRL_DSL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
47940 /*! @} */
47941 
47942 /* The count of ENET_QOS_DMA_CHX_CTRL */
47943 #define ENET_QOS_DMA_CHX_CTRL_COUNT              (5U)
47944 
47945 /*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
47946 /*! @{ */
47947 
47948 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK         (0x1U)
47949 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT        (0U)
47950 /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
47951  *  0b1..Start Transmission Command
47952  *  0b0..Stop Transmission Command
47953  */
47954 #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
47955 
47956 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK        (0x10U)
47957 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT       (4U)
47958 /*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
47959  *    packet of the Transmit data even before the status for the first packet is obtained.
47960  *  0b0..Operate on Second Packet disabled
47961  *  0b1..Operate on Second Packet enabled
47962  */
47963 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
47964 
47965 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK       (0x8000U)
47966 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT      (15U)
47967 /*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
47968  *    locations in the MTL before initiating a transfer.
47969  *  0b0..Ignore PBL Requirement is disabled
47970  *  0b1..Ignore PBL Requirement is enabled
47971  */
47972 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
47973 
47974 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK      (0x3F0000U)
47975 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT     (16U)
47976 /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
47977  *    transferred in one DMA block data transfer.
47978  */
47979 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
47980 
47981 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK       (0x10000000U)
47982 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT      (28U)
47983 /*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
47984  *    Descriptors that are 32 Bytes for both Normal and Context Descriptors.
47985  *  0b0..Enhanced Descriptor is disabled
47986  *  0b1..Enhanced Descriptor is enabled
47987  */
47988 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
47989 /*! @} */
47990 
47991 /* The count of ENET_QOS_DMA_CHX_TX_CTRL */
47992 #define ENET_QOS_DMA_CHX_TX_CTRL_COUNT           (5U)
47993 
47994 /*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
47995 /*! @{ */
47996 
47997 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK         (0x1U)
47998 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT        (0U)
47999 /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
48000  *    the Receive list and processes the incoming packets.
48001  *  0b1..Start Receive
48002  *  0b0..Stop Receive
48003  */
48004 #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
48005 
48006 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK   (0xEU)
48007 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT  (1U)
48008 /*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0.
48009  */
48010 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
48011 
48012 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK  (0x7FF0U)
48013 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
48014 /*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0.
48015  */
48016 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
48017 
48018 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK      (0x3F0000U)
48019 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT     (16U)
48020 /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
48021  *    transferred in one DMA block data transfer.
48022  */
48023 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
48024 
48025 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK        (0x80000000U)
48026 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT       (31U)
48027 /*! RPF - Rx Packet Flush.
48028  *  0b0..Rx Packet Flush is disabled
48029  *  0b1..Rx Packet Flush is enabled
48030  */
48031 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
48032 /*! @} */
48033 
48034 /* The count of ENET_QOS_DMA_CHX_RX_CTRL */
48035 #define ENET_QOS_DMA_CHX_RX_CTRL_COUNT           (5U)
48036 
48037 /*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
48038 /*! @{ */
48039 
48040 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
48041 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
48042 /*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list.
48043  */
48044 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
48045 /*! @} */
48046 
48047 /* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
48048 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT  (5U)
48049 
48050 /*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
48051 /*! @{ */
48052 
48053 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
48054 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
48055 /*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list.
48056  */
48057 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
48058 /*! @} */
48059 
48060 /* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
48061 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT  (5U)
48062 
48063 /*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
48064 /*! @{ */
48065 
48066 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
48067 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
48068 /*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring.
48069  */
48070 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
48071 /*! @} */
48072 
48073 /* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
48074 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT   (5U)
48075 
48076 /*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
48077 /*! @{ */
48078 
48079 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
48080 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
48081 /*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring.
48082  */
48083 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
48084 /*! @} */
48085 
48086 /* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
48087 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT   (5U)
48088 
48089 /*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
48090 /*! @{ */
48091 
48092 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
48093 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
48094 /*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring.
48095  */
48096 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
48097 /*! @} */
48098 
48099 /* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
48100 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
48101 
48102 /*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
48103 /*! @{ */
48104 
48105 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
48106 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
48107 /*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring.
48108  */
48109 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
48110 /*! @} */
48111 
48112 /* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
48113 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
48114 
48115 /*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
48116 /*! @{ */
48117 
48118 #define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK         (0x1U)
48119 #define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT        (0U)
48120 /*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
48121  *  0b0..Transmit Interrupt is disabled
48122  *  0b1..Transmit Interrupt is enabled
48123  */
48124 #define ENET_QOS_DMA_CHX_INT_EN_TIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
48125 
48126 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK        (0x2U)
48127 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT       (1U)
48128 /*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
48129  *  0b0..Transmit Stopped is disabled
48130  *  0b1..Transmit Stopped is enabled
48131  */
48132 #define ENET_QOS_DMA_CHX_INT_EN_TXSE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
48133 
48134 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK        (0x4U)
48135 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT       (2U)
48136 /*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
48137  *    Transmit Buffer Unavailable interrupt is enabled.
48138  *  0b0..Transmit Buffer Unavailable is disabled
48139  *  0b1..Transmit Buffer Unavailable is enabled
48140  */
48141 #define ENET_QOS_DMA_CHX_INT_EN_TBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
48142 
48143 #define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK         (0x40U)
48144 #define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT        (6U)
48145 /*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
48146  *  0b0..Receive Interrupt is disabled
48147  *  0b1..Receive Interrupt is enabled
48148  */
48149 #define ENET_QOS_DMA_CHX_INT_EN_RIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
48150 
48151 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK        (0x80U)
48152 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT       (7U)
48153 /*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
48154  *    Receive Buffer Unavailable interrupt is enabled.
48155  *  0b0..Receive Buffer Unavailable is disabled
48156  *  0b1..Receive Buffer Unavailable is enabled
48157  */
48158 #define ENET_QOS_DMA_CHX_INT_EN_RBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
48159 
48160 #define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK         (0x100U)
48161 #define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT        (8U)
48162 /*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
48163  *  0b0..Receive Stopped is disabled
48164  *  0b1..Receive Stopped is enabled
48165  */
48166 #define ENET_QOS_DMA_CHX_INT_EN_RSE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
48167 
48168 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK        (0x200U)
48169 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT       (9U)
48170 /*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
48171  *    Watchdog Timeout interrupt is enabled.
48172  *  0b0..Receive Watchdog Timeout is disabled
48173  *  0b1..Receive Watchdog Timeout is enabled
48174  */
48175 #define ENET_QOS_DMA_CHX_INT_EN_RWTE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
48176 
48177 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK        (0x400U)
48178 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT       (10U)
48179 /*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
48180  *  0b0..Early Transmit Interrupt is disabled
48181  *  0b1..Early Transmit Interrupt is enabled
48182  */
48183 #define ENET_QOS_DMA_CHX_INT_EN_ETIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
48184 
48185 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK        (0x800U)
48186 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT       (11U)
48187 /*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
48188  *  0b0..Early Receive Interrupt is disabled
48189  *  0b1..Early Receive Interrupt is enabled
48190  */
48191 #define ENET_QOS_DMA_CHX_INT_EN_ERIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
48192 
48193 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK        (0x1000U)
48194 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT       (12U)
48195 /*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
48196  *  0b0..Fatal Bus Error is disabled
48197  *  0b1..Fatal Bus Error is enabled
48198  */
48199 #define ENET_QOS_DMA_CHX_INT_EN_FBEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
48200 
48201 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK        (0x2000U)
48202 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT       (13U)
48203 /*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
48204  *  0b0..Context Descriptor Error is disabled
48205  *  0b1..Context Descriptor Error is enabled
48206  */
48207 #define ENET_QOS_DMA_CHX_INT_EN_CDEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
48208 
48209 #define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK         (0x4000U)
48210 #define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT        (14U)
48211 /*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
48212  *  0b0..Abnormal Interrupt Summary is disabled
48213  *  0b1..Abnormal Interrupt Summary is enabled
48214  */
48215 #define ENET_QOS_DMA_CHX_INT_EN_AIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
48216 
48217 #define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK         (0x8000U)
48218 #define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT        (15U)
48219 /*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
48220  *  0b0..Normal Interrupt Summary is disabled
48221  *  0b1..Normal Interrupt Summary is enabled
48222  */
48223 #define ENET_QOS_DMA_CHX_INT_EN_NIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
48224 /*! @} */
48225 
48226 /* The count of ENET_QOS_DMA_CHX_INT_EN */
48227 #define ENET_QOS_DMA_CHX_INT_EN_COUNT            (5U)
48228 
48229 /*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
48230 /*! @{ */
48231 
48232 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
48233 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
48234 /*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
48235  *    cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
48236  */
48237 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
48238 
48239 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
48240 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
48241 /*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
48242  *    clock cycles corresponding to one unit in RWT field.
48243  */
48244 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
48245 /*! @} */
48246 
48247 /* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
48248 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT    (5U)
48249 
48250 /*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
48251 /*! @{ */
48252 
48253 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
48254 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
48255 /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
48256  *    programmed in the Tx descriptor with the current reference given in the RSN field.
48257  *  0b0..Slot Comparison is disabled
48258  *  0b1..Slot Comparison is enabled
48259  */
48260 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
48261 
48262 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
48263 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
48264 /*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
48265  *    when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
48266  *    number given in the RSN field or - ahead of the reference slot number by up to two slots This
48267  *    bit is applicable only when the ESC bit is set.
48268  *  0b0..Advance Slot Check is disabled
48269  *  0b1..Advance Slot Check is enabled
48270  */
48271 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
48272 
48273 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
48274 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
48275 /*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
48276  *    fetches the scheduled packets.
48277  */
48278 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
48279 
48280 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
48281 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
48282 /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
48283  */
48284 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
48285 /*! @} */
48286 
48287 /* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
48288 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
48289 
48290 /*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
48291 /*! @{ */
48292 
48293 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
48294 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
48295 /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation.
48296  */
48297 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
48298 /*! @} */
48299 
48300 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
48301 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT    (5U)
48302 
48303 /*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
48304 /*! @{ */
48305 
48306 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
48307 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
48308 /*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation.
48309  */
48310 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
48311 /*! @} */
48312 
48313 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
48314 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT    (5U)
48315 
48316 /*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
48317 /*! @{ */
48318 
48319 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
48320 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
48321 /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation.
48322  */
48323 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
48324 /*! @} */
48325 
48326 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
48327 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT     (5U)
48328 
48329 /*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
48330 /*! @{ */
48331 
48332 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
48333 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
48334 /*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation.
48335  */
48336 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
48337 /*! @} */
48338 
48339 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
48340 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT     (5U)
48341 
48342 /*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
48343 /*! @{ */
48344 
48345 #define ENET_QOS_DMA_CHX_STAT_TI_MASK            (0x1U)
48346 #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT           (0U)
48347 /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
48348  *  0b1..Transmit Interrupt status detected
48349  *  0b0..Transmit Interrupt status not detected
48350  */
48351 #define ENET_QOS_DMA_CHX_STAT_TI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
48352 
48353 #define ENET_QOS_DMA_CHX_STAT_TPS_MASK           (0x2U)
48354 #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT          (1U)
48355 /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
48356  *  0b1..Transmit Process Stopped status detected
48357  *  0b0..Transmit Process Stopped status not detected
48358  */
48359 #define ENET_QOS_DMA_CHX_STAT_TPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
48360 
48361 #define ENET_QOS_DMA_CHX_STAT_TBU_MASK           (0x4U)
48362 #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT          (2U)
48363 /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
48364  *    descriptor in the Transmit list, and the DMA cannot acquire it.
48365  *  0b1..Transmit Buffer Unavailable status detected
48366  *  0b0..Transmit Buffer Unavailable status not detected
48367  */
48368 #define ENET_QOS_DMA_CHX_STAT_TBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
48369 
48370 #define ENET_QOS_DMA_CHX_STAT_RI_MASK            (0x40U)
48371 #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT           (6U)
48372 /*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
48373  *  0b1..Receive Interrupt status detected
48374  *  0b0..Receive Interrupt status not detected
48375  */
48376 #define ENET_QOS_DMA_CHX_STAT_RI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
48377 
48378 #define ENET_QOS_DMA_CHX_STAT_RBU_MASK           (0x80U)
48379 #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT          (7U)
48380 /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
48381  *    descriptor in the Receive list, and the DMA cannot acquire it.
48382  *  0b1..Receive Buffer Unavailable status detected
48383  *  0b0..Receive Buffer Unavailable status not detected
48384  */
48385 #define ENET_QOS_DMA_CHX_STAT_RBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
48386 
48387 #define ENET_QOS_DMA_CHX_STAT_RPS_MASK           (0x100U)
48388 #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT          (8U)
48389 /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
48390  *  0b1..Receive Process Stopped status detected
48391  *  0b0..Receive Process Stopped status not detected
48392  */
48393 #define ENET_QOS_DMA_CHX_STAT_RPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
48394 
48395 #define ENET_QOS_DMA_CHX_STAT_RWT_MASK           (0x200U)
48396 #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT          (9U)
48397 /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
48398  *    bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
48399  *  0b1..Receive Watchdog Timeout status detected
48400  *  0b0..Receive Watchdog Timeout status not detected
48401  */
48402 #define ENET_QOS_DMA_CHX_STAT_RWT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
48403 
48404 #define ENET_QOS_DMA_CHX_STAT_ETI_MASK           (0x400U)
48405 #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT          (10U)
48406 /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
48407  *    transfer of packet data to the MTL TXFIFO memory.
48408  *  0b1..Early Transmit Interrupt status detected
48409  *  0b0..Early Transmit Interrupt status not detected
48410  */
48411 #define ENET_QOS_DMA_CHX_STAT_ETI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
48412 
48413 #define ENET_QOS_DMA_CHX_STAT_ERI_MASK           (0x800U)
48414 #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT          (11U)
48415 /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
48416  *    transfer of packet data to the memory.
48417  *  0b1..Early Receive Interrupt status detected
48418  *  0b0..Early Receive Interrupt status not detected
48419  */
48420 #define ENET_QOS_DMA_CHX_STAT_ERI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
48421 
48422 #define ENET_QOS_DMA_CHX_STAT_FBE_MASK           (0x1000U)
48423 #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT          (12U)
48424 /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
48425  *  0b1..Fatal Bus Error status detected
48426  *  0b0..Fatal Bus Error status not detected
48427  */
48428 #define ENET_QOS_DMA_CHX_STAT_FBE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
48429 
48430 #define ENET_QOS_DMA_CHX_STAT_CDE_MASK           (0x2000U)
48431 #define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT          (13U)
48432 /*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
48433  *    descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
48434  *    descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
48435  *    with either of the buffer address as ones which is considered to be invalid.
48436  *  0b1..Context Descriptor Error status detected
48437  *  0b0..Context Descriptor Error status not detected
48438  */
48439 #define ENET_QOS_DMA_CHX_STAT_CDE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
48440 
48441 #define ENET_QOS_DMA_CHX_STAT_AIS_MASK           (0x4000U)
48442 #define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT          (14U)
48443 /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
48444  *    following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
48445  *    register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
48446  *    Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
48447  *    Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
48448  *  0b1..Abnormal Interrupt Summary status detected
48449  *  0b0..Abnormal Interrupt Summary status not detected
48450  */
48451 #define ENET_QOS_DMA_CHX_STAT_AIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
48452 
48453 #define ENET_QOS_DMA_CHX_STAT_NIS_MASK           (0x8000U)
48454 #define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT          (15U)
48455 /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
48456  *    following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
48457  *    register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
48458  *    Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
48459  *    enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
48460  *  0b1..Normal Interrupt Summary status detected
48461  *  0b0..Normal Interrupt Summary status not detected
48462  */
48463 #define ENET_QOS_DMA_CHX_STAT_NIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
48464 
48465 #define ENET_QOS_DMA_CHX_STAT_TEB_MASK           (0x70000U)
48466 #define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT          (16U)
48467 /*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error.
48468  */
48469 #define ENET_QOS_DMA_CHX_STAT_TEB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
48470 
48471 #define ENET_QOS_DMA_CHX_STAT_REB_MASK           (0x380000U)
48472 #define ENET_QOS_DMA_CHX_STAT_REB_SHIFT          (19U)
48473 /*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error.
48474  */
48475 #define ENET_QOS_DMA_CHX_STAT_REB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
48476 /*! @} */
48477 
48478 /* The count of ENET_QOS_DMA_CHX_STAT */
48479 #define ENET_QOS_DMA_CHX_STAT_COUNT              (5U)
48480 
48481 /*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
48482 /*! @{ */
48483 
48484 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
48485 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
48486 /*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
48487  *    dropped by the DMA either because of bus error or because of programming RPF field in
48488  *    DMA_CH2_RX_CONTROL register.
48489  */
48490 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
48491 
48492 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
48493 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
48494 /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
48495  *  0b1..Miss Frame Counter overflow occurred
48496  *  0b0..Miss Frame Counter overflow not occurred
48497  */
48498 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
48499 /*! @} */
48500 
48501 /* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
48502 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT    (5U)
48503 
48504 /*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
48505 /*! @{ */
48506 
48507 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
48508 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
48509 /*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1.
48510  */
48511 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
48512 
48513 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
48514 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
48515 /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
48516  *    Counter field crossed the maximum limit.
48517  *  0b1..Rx Parser Accept Counter overflow occurred
48518  *  0b0..Rx Parser Accept Counter overflow not occurred
48519  */
48520 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
48521 /*! @} */
48522 
48523 /* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
48524 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT    (5U)
48525 
48526 /*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
48527 /*! @{ */
48528 
48529 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK    (0xFFFU)
48530 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT   (0U)
48531 /*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
48532  *    for burst transfer completed by the Rx DMA from the start of packet transfer.
48533  */
48534 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
48535 /*! @} */
48536 
48537 /* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
48538 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT        (5U)
48539 
48540 
48541 /*!
48542  * @}
48543  */ /* end of group ENET_QOS_Register_Masks */
48544 
48545 
48546 /* ENET_QOS - Peripheral instance base addresses */
48547 /** Peripheral ENET_QOS base address */
48548 #define ENET_QOS_BASE                            (0x4043C000u)
48549 /** Peripheral ENET_QOS base pointer */
48550 #define ENET_QOS                                 ((ENET_QOS_Type *)ENET_QOS_BASE)
48551 /** Array initializer of ENET_QOS peripheral base addresses */
48552 #define ENET_QOS_BASE_ADDRS                      { ENET_QOS_BASE }
48553 /** Array initializer of ENET_QOS peripheral base pointers */
48554 #define ENET_QOS_BASE_PTRS                       { ENET_QOS }
48555 /** Interrupt vectors for the ENET_QOS peripheral type */
48556 #define ENET_QOS_IRQS                            { ENET_QOS_IRQn }
48557 #define ENET_QOS_PMT_IRQS                        { ENET_QOS_PMT_IRQn }
48558 
48559 /*!
48560  * @}
48561  */ /* end of group ENET_QOS_Peripheral_Access_Layer */
48562 
48563 
48564 /* ----------------------------------------------------------------------------
48565    -- ETHERNET_PLL Peripheral Access Layer
48566    ---------------------------------------------------------------------------- */
48567 
48568 /*!
48569  * @addtogroup ETHERNET_PLL_Peripheral_Access_Layer ETHERNET_PLL Peripheral Access Layer
48570  * @{
48571  */
48572 
48573 /** ETHERNET_PLL - Register Layout Typedef */
48574 typedef struct {
48575   struct {                                         /* offset: 0x0 */
48576     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
48577     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
48578     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
48579     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
48580   } CTRL0;
48581   struct {                                         /* offset: 0x10 */
48582     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
48583     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
48584     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
48585     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
48586   } SPREAD_SPECTRUM;
48587   struct {                                         /* offset: 0x20 */
48588     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
48589     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
48590     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
48591     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
48592   } NUMERATOR;
48593   struct {                                         /* offset: 0x30 */
48594     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
48595     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
48596     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
48597     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
48598   } DENOMINATOR;
48599 } ETHERNET_PLL_Type;
48600 
48601 /* ----------------------------------------------------------------------------
48602    -- ETHERNET_PLL Register Masks
48603    ---------------------------------------------------------------------------- */
48604 
48605 /*!
48606  * @addtogroup ETHERNET_PLL_Register_Masks ETHERNET_PLL Register Masks
48607  * @{
48608  */
48609 
48610 /*! @name CTRL0 - Fractional PLL Control Register */
48611 /*! @{ */
48612 
48613 #define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK       (0x7FU)
48614 #define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT      (0U)
48615 /*! DIV_SELECT - DIV_SELECT
48616  */
48617 #define ETHERNET_PLL_CTRL0_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK)
48618 
48619 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK       (0x100U)
48620 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT      (8U)
48621 /*! ENABLE_ALT - ENABLE_ALT
48622  *  0b0..Disable the alternate clock output
48623  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
48624  */
48625 #define ETHERNET_PLL_CTRL0_ENABLE_ALT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK)
48626 
48627 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK    (0x2000U)
48628 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
48629 /*! HOLD_RING_OFF - PLL Start up initialization
48630  *  0b0..Normal operation
48631  *  0b1..Initialize PLL start up
48632  */
48633 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x)      (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK)
48634 
48635 #define ETHERNET_PLL_CTRL0_POWERUP_MASK          (0x4000U)
48636 #define ETHERNET_PLL_CTRL0_POWERUP_SHIFT         (14U)
48637 /*! POWERUP - POWERUP
48638  *  0b1..Power Up the PLL
48639  *  0b0..Power down the PLL
48640  */
48641 #define ETHERNET_PLL_CTRL0_POWERUP(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK)
48642 
48643 #define ETHERNET_PLL_CTRL0_ENABLE_MASK           (0x8000U)
48644 #define ETHERNET_PLL_CTRL0_ENABLE_SHIFT          (15U)
48645 /*! ENABLE - ENABLE
48646  *  0b1..Enable the clock output
48647  *  0b0..Disable the clock output
48648  */
48649 #define ETHERNET_PLL_CTRL0_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK)
48650 
48651 #define ETHERNET_PLL_CTRL0_BYPASS_MASK           (0x10000U)
48652 #define ETHERNET_PLL_CTRL0_BYPASS_SHIFT          (16U)
48653 /*! BYPASS - BYPASS
48654  *  0b1..Bypass the PLL
48655  *  0b0..No Bypass
48656  */
48657 #define ETHERNET_PLL_CTRL0_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK)
48658 
48659 #define ETHERNET_PLL_CTRL0_DITHER_EN_MASK        (0x20000U)
48660 #define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT       (17U)
48661 /*! DITHER_EN - DITHER_EN
48662  *  0b0..Disable Dither
48663  *  0b1..Enable Dither
48664  */
48665 #define ETHERNET_PLL_CTRL0_DITHER_EN(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK)
48666 
48667 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK        (0x380000U)
48668 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT       (19U)
48669 /*! BIAS_TRIM - BIAS_TRIM
48670  */
48671 #define ETHERNET_PLL_CTRL0_BIAS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK)
48672 
48673 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK       (0x400000U)
48674 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT      (22U)
48675 /*! PLL_REG_EN - PLL_REG_EN
48676  */
48677 #define ETHERNET_PLL_CTRL0_PLL_REG_EN(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK)
48678 
48679 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK     (0xE000000U)
48680 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT    (25U)
48681 /*! POST_DIV_SEL - Post Divide Select
48682  *  0b000..Divide by 1
48683  *  0b001..Divide by 2
48684  *  0b010..Divide by 4
48685  *  0b011..Divide by 8
48686  *  0b100..Divide by 16
48687  *  0b101..Divide by 32
48688  */
48689 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK)
48690 
48691 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK      (0x20000000U)
48692 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT     (29U)
48693 /*! BIAS_SELECT - BIAS_SELECT
48694  *  0b0..Used in SoCs with a bias current of 10uA
48695  *  0b1..Used in SoCs with a bias current of 2uA
48696  */
48697 #define ETHERNET_PLL_CTRL0_BIAS_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK)
48698 /*! @} */
48699 
48700 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
48701 /*! @{ */
48702 
48703 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
48704 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT  (0U)
48705 /*! STEP - Step
48706  */
48707 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK)
48708 
48709 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
48710 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
48711 /*! ENABLE - Enable
48712  */
48713 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
48714 
48715 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
48716 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT  (16U)
48717 /*! STOP - Stop
48718  */
48719 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK)
48720 /*! @} */
48721 
48722 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
48723 /*! @{ */
48724 
48725 #define ETHERNET_PLL_NUMERATOR_NUM_MASK          (0x3FFFFFFFU)
48726 #define ETHERNET_PLL_NUMERATOR_NUM_SHIFT         (0U)
48727 /*! NUM - Numerator
48728  */
48729 #define ETHERNET_PLL_NUMERATOR_NUM(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK)
48730 /*! @} */
48731 
48732 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
48733 /*! @{ */
48734 
48735 #define ETHERNET_PLL_DENOMINATOR_DENOM_MASK      (0x3FFFFFFFU)
48736 #define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT     (0U)
48737 /*! DENOM - Denominator
48738  */
48739 #define ETHERNET_PLL_DENOMINATOR_DENOM(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK)
48740 /*! @} */
48741 
48742 
48743 /*!
48744  * @}
48745  */ /* end of group ETHERNET_PLL_Register_Masks */
48746 
48747 
48748 /* ETHERNET_PLL - Peripheral instance base addresses */
48749 /** Peripheral ETHERNET_PLL base address */
48750 #define ETHERNET_PLL_BASE                        (0u)
48751 /** Peripheral ETHERNET_PLL base pointer */
48752 #define ETHERNET_PLL                             ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
48753 /** Array initializer of ETHERNET_PLL peripheral base addresses */
48754 #define ETHERNET_PLL_BASE_ADDRS                  { ETHERNET_PLL_BASE }
48755 /** Array initializer of ETHERNET_PLL peripheral base pointers */
48756 #define ETHERNET_PLL_BASE_PTRS                   { ETHERNET_PLL }
48757 
48758 /*!
48759  * @}
48760  */ /* end of group ETHERNET_PLL_Peripheral_Access_Layer */
48761 
48762 
48763 /* ----------------------------------------------------------------------------
48764    -- EWM Peripheral Access Layer
48765    ---------------------------------------------------------------------------- */
48766 
48767 /*!
48768  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
48769  * @{
48770  */
48771 
48772 /** EWM - Register Layout Typedef */
48773 typedef struct {
48774   __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
48775   __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
48776   __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
48777   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
48778   __IO uint8_t CLKCTRL;                            /**< Clock Control Register, offset: 0x4 */
48779   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
48780 } EWM_Type;
48781 
48782 /* ----------------------------------------------------------------------------
48783    -- EWM Register Masks
48784    ---------------------------------------------------------------------------- */
48785 
48786 /*!
48787  * @addtogroup EWM_Register_Masks EWM Register Masks
48788  * @{
48789  */
48790 
48791 /*! @name CTRL - Control Register */
48792 /*! @{ */
48793 
48794 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
48795 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
48796 /*! EWMEN - EWM enable.
48797  *  0b0..EWM module is disabled.
48798  *  0b1..EWM module is enabled.
48799  */
48800 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
48801 
48802 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
48803 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
48804 /*! ASSIN - EWM_in's Assertion State Select.
48805  *  0b0..Default assert state of the EWM_in signal.
48806  *  0b1..Inverts the assert state of EWM_in signal.
48807  */
48808 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
48809 
48810 #define EWM_CTRL_INEN_MASK                       (0x4U)
48811 #define EWM_CTRL_INEN_SHIFT                      (2U)
48812 /*! INEN - Input Enable.
48813  *  0b0..EWM_in port is disabled.
48814  *  0b1..EWM_in port is enabled.
48815  */
48816 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
48817 
48818 #define EWM_CTRL_INTEN_MASK                      (0x8U)
48819 #define EWM_CTRL_INTEN_SHIFT                     (3U)
48820 /*! INTEN - Interrupt Enable.
48821  *  0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
48822  *  0b0..Deasserts the interrupt request.
48823  */
48824 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
48825 /*! @} */
48826 
48827 /*! @name SERV - Service Register */
48828 /*! @{ */
48829 
48830 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
48831 #define EWM_SERV_SERVICE_SHIFT                   (0U)
48832 /*! SERVICE - SERVICE
48833  */
48834 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
48835 /*! @} */
48836 
48837 /*! @name CMPL - Compare Low Register */
48838 /*! @{ */
48839 
48840 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
48841 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
48842 /*! COMPAREL - COMPAREL
48843  */
48844 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
48845 /*! @} */
48846 
48847 /*! @name CMPH - Compare High Register */
48848 /*! @{ */
48849 
48850 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
48851 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
48852 /*! COMPAREH - COMPAREH
48853  */
48854 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
48855 /*! @} */
48856 
48857 /*! @name CLKCTRL - Clock Control Register */
48858 /*! @{ */
48859 
48860 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
48861 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
48862 /*! CLKSEL - CLKSEL
48863  */
48864 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
48865 /*! @} */
48866 
48867 /*! @name CLKPRESCALER - Clock Prescaler Register */
48868 /*! @{ */
48869 
48870 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
48871 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
48872 /*! CLK_DIV - CLK_DIV
48873  */
48874 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
48875 /*! @} */
48876 
48877 
48878 /*!
48879  * @}
48880  */ /* end of group EWM_Register_Masks */
48881 
48882 
48883 /* EWM - Peripheral instance base addresses */
48884 /** Peripheral EWM base address */
48885 #define EWM_BASE                                 (0x4002C000u)
48886 /** Peripheral EWM base pointer */
48887 #define EWM                                      ((EWM_Type *)EWM_BASE)
48888 /** Array initializer of EWM peripheral base addresses */
48889 #define EWM_BASE_ADDRS                           { EWM_BASE }
48890 /** Array initializer of EWM peripheral base pointers */
48891 #define EWM_BASE_PTRS                            { EWM }
48892 /** Interrupt vectors for the EWM peripheral type */
48893 #define EWM_IRQS                                 { EWM_IRQn }
48894 
48895 /*!
48896  * @}
48897  */ /* end of group EWM_Peripheral_Access_Layer */
48898 
48899 
48900 /* ----------------------------------------------------------------------------
48901    -- FLEXIO Peripheral Access Layer
48902    ---------------------------------------------------------------------------- */
48903 
48904 /*!
48905  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
48906  * @{
48907  */
48908 
48909 /** FLEXIO - Register Layout Typedef */
48910 typedef struct {
48911   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
48912   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
48913   __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
48914   __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
48915   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
48916   __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
48917   __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
48918        uint8_t RESERVED_0[4];
48919   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
48920   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
48921   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
48922        uint8_t RESERVED_1[4];
48923   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
48924        uint8_t RESERVED_2[4];
48925   __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
48926        uint8_t RESERVED_3[4];
48927   __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
48928        uint8_t RESERVED_4[60];
48929   __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
48930        uint8_t RESERVED_5[96];
48931   __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
48932        uint8_t RESERVED_6[224];
48933   __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
48934        uint8_t RESERVED_7[96];
48935   __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
48936        uint8_t RESERVED_8[96];
48937   __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
48938        uint8_t RESERVED_9[96];
48939   __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
48940        uint8_t RESERVED_10[96];
48941   __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
48942        uint8_t RESERVED_11[96];
48943   __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
48944        uint8_t RESERVED_12[96];
48945   __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
48946        uint8_t RESERVED_13[352];
48947   __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
48948        uint8_t RESERVED_14[96];
48949   __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
48950        uint8_t RESERVED_15[96];
48951   __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
48952        uint8_t RESERVED_16[96];
48953   __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
48954        uint8_t RESERVED_17[96];
48955   __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
48956 } FLEXIO_Type;
48957 
48958 /* ----------------------------------------------------------------------------
48959    -- FLEXIO Register Masks
48960    ---------------------------------------------------------------------------- */
48961 
48962 /*!
48963  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
48964  * @{
48965  */
48966 
48967 /*! @name VERID - Version ID Register */
48968 /*! @{ */
48969 
48970 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
48971 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
48972 /*! FEATURE - Feature Specification Number
48973  *  0b0000000000000000..Standard features implemented.
48974  *  0b0000000000000001..Supports state, logic and parallel modes.
48975  *  0b0000000000000010..Supports pin control registers.
48976  *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
48977  */
48978 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
48979 
48980 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
48981 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
48982 /*! MINOR - Minor Version Number
48983  */
48984 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
48985 
48986 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
48987 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
48988 /*! MAJOR - Major Version Number
48989  */
48990 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
48991 /*! @} */
48992 
48993 /*! @name PARAM - Parameter Register */
48994 /*! @{ */
48995 
48996 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
48997 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
48998 /*! SHIFTER - Shifter Number
48999  */
49000 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
49001 
49002 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
49003 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
49004 /*! TIMER - Timer Number
49005  */
49006 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
49007 
49008 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
49009 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
49010 /*! PIN - Pin Number
49011  */
49012 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
49013 
49014 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
49015 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
49016 /*! TRIGGER - Trigger Number
49017  */
49018 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
49019 /*! @} */
49020 
49021 /*! @name CTRL - FlexIO Control Register */
49022 /*! @{ */
49023 
49024 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
49025 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
49026 /*! FLEXEN - FlexIO Enable
49027  *  0b0..FlexIO module is disabled.
49028  *  0b1..FlexIO module is enabled.
49029  */
49030 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
49031 
49032 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
49033 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
49034 /*! SWRST - Software Reset
49035  *  0b0..Software reset is disabled
49036  *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
49037  */
49038 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
49039 
49040 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
49041 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
49042 /*! FASTACC - Fast Access
49043  *  0b0..Configures for normal register accesses to FlexIO
49044  *  0b1..Configures for fast register accesses to FlexIO
49045  */
49046 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
49047 
49048 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
49049 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
49050 /*! DBGE - Debug Enable
49051  *  0b0..FlexIO is disabled in debug modes.
49052  *  0b1..FlexIO is enabled in debug modes
49053  */
49054 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
49055 
49056 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
49057 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
49058 /*! DOZEN - Doze Enable
49059  *  0b0..FlexIO enabled in Doze modes.
49060  *  0b1..FlexIO disabled in Doze modes.
49061  */
49062 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
49063 /*! @} */
49064 
49065 /*! @name PIN - Pin State Register */
49066 /*! @{ */
49067 
49068 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
49069 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
49070 /*! PDI - Pin Data Input
49071  */
49072 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
49073 /*! @} */
49074 
49075 /*! @name SHIFTSTAT - Shifter Status Register */
49076 /*! @{ */
49077 
49078 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
49079 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
49080 /*! SSF - Shifter Status Flag
49081  */
49082 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
49083 /*! @} */
49084 
49085 /*! @name SHIFTERR - Shifter Error Register */
49086 /*! @{ */
49087 
49088 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
49089 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
49090 /*! SEF - Shifter Error Flags
49091  */
49092 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
49093 /*! @} */
49094 
49095 /*! @name TIMSTAT - Timer Status Register */
49096 /*! @{ */
49097 
49098 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
49099 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
49100 /*! TSF - Timer Status Flags
49101  */
49102 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
49103 /*! @} */
49104 
49105 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
49106 /*! @{ */
49107 
49108 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
49109 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
49110 /*! SSIE - Shifter Status Interrupt Enable
49111  */
49112 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
49113 /*! @} */
49114 
49115 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
49116 /*! @{ */
49117 
49118 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
49119 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
49120 /*! SEIE - Shifter Error Interrupt Enable
49121  */
49122 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
49123 /*! @} */
49124 
49125 /*! @name TIMIEN - Timer Interrupt Enable Register */
49126 /*! @{ */
49127 
49128 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
49129 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
49130 /*! TEIE - Timer Status Interrupt Enable
49131  */
49132 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
49133 /*! @} */
49134 
49135 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
49136 /*! @{ */
49137 
49138 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
49139 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
49140 /*! SSDE - Shifter Status DMA Enable
49141  */
49142 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
49143 /*! @} */
49144 
49145 /*! @name TIMERSDEN - Timer Status DMA Enable */
49146 /*! @{ */
49147 
49148 #define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
49149 #define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
49150 /*! TSDE - Timer Status DMA Enable
49151  */
49152 #define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
49153 /*! @} */
49154 
49155 /*! @name SHIFTSTATE - Shifter State Register */
49156 /*! @{ */
49157 
49158 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
49159 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
49160 /*! STATE - Current State Pointer
49161  */
49162 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
49163 /*! @} */
49164 
49165 /*! @name SHIFTCTL - Shifter Control N Register */
49166 /*! @{ */
49167 
49168 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
49169 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
49170 /*! SMOD - Shifter Mode
49171  *  0b000..Disabled.
49172  *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
49173  *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
49174  *  0b011..Reserved.
49175  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
49176  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
49177  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
49178  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
49179  */
49180 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
49181 
49182 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
49183 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
49184 /*! PINPOL - Shifter Pin Polarity
49185  *  0b0..Pin is active high
49186  *  0b1..Pin is active low
49187  */
49188 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
49189 
49190 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
49191 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
49192 /*! PINSEL - Shifter Pin Select
49193  */
49194 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
49195 
49196 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
49197 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
49198 /*! PINCFG - Shifter Pin Configuration
49199  *  0b00..Shifter pin output disabled
49200  *  0b01..Shifter pin open drain or bidirectional output enable
49201  *  0b10..Shifter pin bidirectional output data
49202  *  0b11..Shifter pin output
49203  */
49204 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
49205 
49206 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
49207 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
49208 /*! TIMPOL - Timer Polarity
49209  *  0b0..Shift on posedge of Shift clock
49210  *  0b1..Shift on negedge of Shift clock
49211  */
49212 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
49213 
49214 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
49215 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
49216 /*! TIMSEL - Timer Select
49217  */
49218 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
49219 /*! @} */
49220 
49221 /* The count of FLEXIO_SHIFTCTL */
49222 #define FLEXIO_SHIFTCTL_COUNT                    (8U)
49223 
49224 /*! @name SHIFTCFG - Shifter Configuration N Register */
49225 /*! @{ */
49226 
49227 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
49228 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
49229 /*! SSTART - Shifter Start bit
49230  *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
49231  *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
49232  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
49233  *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
49234  */
49235 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
49236 
49237 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
49238 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
49239 /*! SSTOP - Shifter Stop bit
49240  *  0b00..Stop bit disabled for transmitter/receiver/match store
49241  *  0b01..Reserved for transmitter/receiver/match store
49242  *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
49243  *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
49244  */
49245 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
49246 
49247 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
49248 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
49249 /*! INSRC - Input Source
49250  *  0b0..Pin
49251  *  0b1..Shifter N+1 Output
49252  */
49253 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
49254 
49255 #define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
49256 #define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
49257 /*! LATST - Late Store
49258  *  0b0..Shift register stores the pre-shift register state.
49259  *  0b1..Shift register stores the post-shift register state.
49260  */
49261 #define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
49262 
49263 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
49264 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
49265 /*! PWIDTH - Parallel Width
49266  */
49267 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
49268 /*! @} */
49269 
49270 /* The count of FLEXIO_SHIFTCFG */
49271 #define FLEXIO_SHIFTCFG_COUNT                    (8U)
49272 
49273 /*! @name SHIFTBUF - Shifter Buffer N Register */
49274 /*! @{ */
49275 
49276 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
49277 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
49278 /*! SHIFTBUF - Shift Buffer
49279  */
49280 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
49281 /*! @} */
49282 
49283 /* The count of FLEXIO_SHIFTBUF */
49284 #define FLEXIO_SHIFTBUF_COUNT                    (8U)
49285 
49286 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
49287 /*! @{ */
49288 
49289 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
49290 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
49291 /*! SHIFTBUFBIS - Shift Buffer
49292  */
49293 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
49294 /*! @} */
49295 
49296 /* The count of FLEXIO_SHIFTBUFBIS */
49297 #define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
49298 
49299 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
49300 /*! @{ */
49301 
49302 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
49303 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
49304 /*! SHIFTBUFBYS - Shift Buffer
49305  */
49306 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
49307 /*! @} */
49308 
49309 /* The count of FLEXIO_SHIFTBUFBYS */
49310 #define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
49311 
49312 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
49313 /*! @{ */
49314 
49315 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
49316 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
49317 /*! SHIFTBUFBBS - Shift Buffer
49318  */
49319 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
49320 /*! @} */
49321 
49322 /* The count of FLEXIO_SHIFTBUFBBS */
49323 #define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
49324 
49325 /*! @name TIMCTL - Timer Control N Register */
49326 /*! @{ */
49327 
49328 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
49329 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
49330 /*! TIMOD - Timer Mode
49331  *  0b000..Timer Disabled.
49332  *  0b001..Dual 8-bit counters baud mode.
49333  *  0b010..Dual 8-bit counters PWM high mode.
49334  *  0b011..Single 16-bit counter mode.
49335  *  0b100..Single 16-bit counter disable mode.
49336  *  0b101..Dual 8-bit counters word mode.
49337  *  0b110..Dual 8-bit counters PWM low mode.
49338  *  0b111..Single 16-bit input capture mode.
49339  */
49340 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
49341 
49342 #define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
49343 #define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
49344 /*! ONETIM - Timer One Time Operation
49345  *  0b0..The timer enable event is generated as normal.
49346  *  0b1..The timer enable event is blocked unless timer status flag is clear.
49347  */
49348 #define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
49349 
49350 #define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
49351 #define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
49352 /*! PININS - Timer Pin Input Select
49353  *  0b0..Timer pin input and output are selected by PINSEL.
49354  *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
49355  */
49356 #define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
49357 
49358 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
49359 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
49360 /*! PINPOL - Timer Pin Polarity
49361  *  0b0..Pin is active high
49362  *  0b1..Pin is active low
49363  */
49364 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
49365 
49366 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
49367 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
49368 /*! PINSEL - Timer Pin Select
49369  */
49370 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
49371 
49372 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
49373 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
49374 /*! PINCFG - Timer Pin Configuration
49375  *  0b00..Timer pin output disabled
49376  *  0b01..Timer pin open drain or bidirectional output enable
49377  *  0b10..Timer pin bidirectional output data
49378  *  0b11..Timer pin output
49379  */
49380 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
49381 
49382 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
49383 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
49384 /*! TRGSRC - Trigger Source
49385  *  0b0..External trigger selected
49386  *  0b1..Internal trigger selected
49387  */
49388 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
49389 
49390 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
49391 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
49392 /*! TRGPOL - Trigger Polarity
49393  *  0b0..Trigger active high
49394  *  0b1..Trigger active low
49395  */
49396 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
49397 
49398 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
49399 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
49400 /*! TRGSEL - Trigger Select
49401  */
49402 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
49403 /*! @} */
49404 
49405 /* The count of FLEXIO_TIMCTL */
49406 #define FLEXIO_TIMCTL_COUNT                      (8U)
49407 
49408 /*! @name TIMCFG - Timer Configuration N Register */
49409 /*! @{ */
49410 
49411 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
49412 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
49413 /*! TSTART - Timer Start Bit
49414  *  0b0..Start bit disabled
49415  *  0b1..Start bit enabled
49416  */
49417 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
49418 
49419 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
49420 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
49421 /*! TSTOP - Timer Stop Bit
49422  *  0b00..Stop bit disabled
49423  *  0b01..Stop bit is enabled on timer compare
49424  *  0b10..Stop bit is enabled on timer disable
49425  *  0b11..Stop bit is enabled on timer compare and timer disable
49426  */
49427 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
49428 
49429 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
49430 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
49431 /*! TIMENA - Timer Enable
49432  *  0b000..Timer always enabled
49433  *  0b001..Timer enabled on Timer N-1 enable
49434  *  0b010..Timer enabled on Trigger high
49435  *  0b011..Timer enabled on Trigger high and Pin high
49436  *  0b100..Timer enabled on Pin rising edge
49437  *  0b101..Timer enabled on Pin rising edge and Trigger high
49438  *  0b110..Timer enabled on Trigger rising edge
49439  *  0b111..Timer enabled on Trigger rising or falling edge
49440  */
49441 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
49442 
49443 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
49444 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
49445 /*! TIMDIS - Timer Disable
49446  *  0b000..Timer never disabled
49447  *  0b001..Timer disabled on Timer N-1 disable
49448  *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
49449  *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
49450  *  0b100..Timer disabled on Pin rising or falling edge
49451  *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
49452  *  0b110..Timer disabled on Trigger falling edge
49453  *  0b111..Reserved
49454  */
49455 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
49456 
49457 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
49458 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
49459 /*! TIMRST - Timer Reset
49460  *  0b000..Timer never reset
49461  *  0b001..Timer reset on Timer Output high.
49462  *  0b010..Timer reset on Timer Pin equal to Timer Output
49463  *  0b011..Timer reset on Timer Trigger equal to Timer Output
49464  *  0b100..Timer reset on Timer Pin rising edge
49465  *  0b101..Reserved
49466  *  0b110..Timer reset on Trigger rising edge
49467  *  0b111..Timer reset on Trigger rising or falling edge
49468  */
49469 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
49470 
49471 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
49472 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
49473 /*! TIMDEC - Timer Decrement
49474  *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
49475  *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
49476  *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
49477  *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
49478  *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
49479  *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
49480  *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
49481  *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
49482  */
49483 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
49484 
49485 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
49486 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
49487 /*! TIMOUT - Timer Output
49488  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
49489  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
49490  *  0b10..Timer output is logic one when enabled and on timer reset
49491  *  0b11..Timer output is logic zero when enabled and on timer reset
49492  */
49493 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
49494 /*! @} */
49495 
49496 /* The count of FLEXIO_TIMCFG */
49497 #define FLEXIO_TIMCFG_COUNT                      (8U)
49498 
49499 /*! @name TIMCMP - Timer Compare N Register */
49500 /*! @{ */
49501 
49502 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
49503 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
49504 /*! CMP - Timer Compare Value
49505  */
49506 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
49507 /*! @} */
49508 
49509 /* The count of FLEXIO_TIMCMP */
49510 #define FLEXIO_TIMCMP_COUNT                      (8U)
49511 
49512 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
49513 /*! @{ */
49514 
49515 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
49516 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
49517 /*! SHIFTBUFNBS - Shift Buffer
49518  */
49519 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
49520 /*! @} */
49521 
49522 /* The count of FLEXIO_SHIFTBUFNBS */
49523 #define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
49524 
49525 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
49526 /*! @{ */
49527 
49528 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
49529 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
49530 /*! SHIFTBUFHWS - Shift Buffer
49531  */
49532 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
49533 /*! @} */
49534 
49535 /* The count of FLEXIO_SHIFTBUFHWS */
49536 #define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
49537 
49538 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
49539 /*! @{ */
49540 
49541 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
49542 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
49543 /*! SHIFTBUFNIS - Shift Buffer
49544  */
49545 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
49546 /*! @} */
49547 
49548 /* The count of FLEXIO_SHIFTBUFNIS */
49549 #define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
49550 
49551 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
49552 /*! @{ */
49553 
49554 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
49555 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
49556 /*! SHIFTBUFOES - Shift Buffer
49557  */
49558 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
49559 /*! @} */
49560 
49561 /* The count of FLEXIO_SHIFTBUFOES */
49562 #define FLEXIO_SHIFTBUFOES_COUNT                 (8U)
49563 
49564 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
49565 /*! @{ */
49566 
49567 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
49568 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
49569 /*! SHIFTBUFEOS - Shift Buffer
49570  */
49571 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
49572 /*! @} */
49573 
49574 /* The count of FLEXIO_SHIFTBUFEOS */
49575 #define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)
49576 
49577 
49578 /*!
49579  * @}
49580  */ /* end of group FLEXIO_Register_Masks */
49581 
49582 
49583 /* FLEXIO - Peripheral instance base addresses */
49584 /** Peripheral FLEXIO1 base address */
49585 #define FLEXIO1_BASE                             (0x400AC000u)
49586 /** Peripheral FLEXIO1 base pointer */
49587 #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
49588 /** Peripheral FLEXIO2 base address */
49589 #define FLEXIO2_BASE                             (0x400B0000u)
49590 /** Peripheral FLEXIO2 base pointer */
49591 #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
49592 /** Array initializer of FLEXIO peripheral base addresses */
49593 #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
49594 /** Array initializer of FLEXIO peripheral base pointers */
49595 #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
49596 /** Interrupt vectors for the FLEXIO peripheral type */
49597 #define FLEXIO_IRQS                              { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
49598 
49599 /*!
49600  * @}
49601  */ /* end of group FLEXIO_Peripheral_Access_Layer */
49602 
49603 
49604 /* ----------------------------------------------------------------------------
49605    -- FLEXRAM Peripheral Access Layer
49606    ---------------------------------------------------------------------------- */
49607 
49608 /*!
49609  * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
49610  * @{
49611  */
49612 
49613 /** FLEXRAM - Register Layout Typedef */
49614 typedef struct {
49615   __IO uint32_t TCM_CTRL;                          /**< TCM CRTL Register, offset: 0x0 */
49616   __IO uint32_t OCRAM_MAGIC_ADDR;                  /**< OCRAM Magic Address Register, offset: 0x4 */
49617   __IO uint32_t DTCM_MAGIC_ADDR;                   /**< DTCM Magic Address Register, offset: 0x8 */
49618   __IO uint32_t ITCM_MAGIC_ADDR;                   /**< ITCM Magic Address Register, offset: 0xC */
49619   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x10 */
49620   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable Register, offset: 0x14 */
49621   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable Register, offset: 0x18 */
49622   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_INFO;       /**< OCRAM single-bit ECC Error Information Register, offset: 0x1C */
49623   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR;       /**< OCRAM single-bit ECC Error Address Register, offset: 0x20 */
49624   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x24 */
49625   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x28 */
49626   __I  uint32_t OCRAM_ECC_MULTI_ERROR_INFO;        /**< OCRAM multi-bit ECC Error Information Register, offset: 0x2C */
49627   __I  uint32_t OCRAM_ECC_MULTI_ERROR_ADDR;        /**< OCRAM multi-bit ECC Error Address Register, offset: 0x30 */
49628   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_LSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x34 */
49629   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_MSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x38 */
49630   __I  uint32_t ITCM_ECC_SINGLE_ERROR_INFO;        /**< ITCM single-bit ECC Error Information Register, offset: 0x3C */
49631   __I  uint32_t ITCM_ECC_SINGLE_ERROR_ADDR;        /**< ITCM single-bit ECC Error Address Register, offset: 0x40 */
49632   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x44 */
49633   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x48 */
49634   __I  uint32_t ITCM_ECC_MULTI_ERROR_INFO;         /**< ITCM multi-bit ECC Error Information Register, offset: 0x4C */
49635   __I  uint32_t ITCM_ECC_MULTI_ERROR_ADDR;         /**< ITCM multi-bit ECC Error Address Register, offset: 0x50 */
49636   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x54 */
49637   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x58 */
49638   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_INFO;       /**< D0TCM single-bit ECC Error Information Register, offset: 0x5C */
49639   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR;       /**< D0TCM single-bit ECC Error Address Register, offset: 0x60 */
49640   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_DATA;       /**< D0TCM single-bit ECC Error Data Register, offset: 0x64 */
49641   __I  uint32_t D0TCM_ECC_MULTI_ERROR_INFO;        /**< D0TCM multi-bit ECC Error Information Register, offset: 0x68 */
49642   __I  uint32_t D0TCM_ECC_MULTI_ERROR_ADDR;        /**< D0TCM multi-bit ECC Error Address Register, offset: 0x6C */
49643   __I  uint32_t D0TCM_ECC_MULTI_ERROR_DATA;        /**< D0TCM multi-bit ECC Error Data Register, offset: 0x70 */
49644   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_INFO;       /**< D1TCM single-bit ECC Error Information Register, offset: 0x74 */
49645   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR;       /**< D1TCM single-bit ECC Error Address Register, offset: 0x78 */
49646   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_DATA;       /**< D1TCM single-bit ECC Error Data Register, offset: 0x7C */
49647   __I  uint32_t D1TCM_ECC_MULTI_ERROR_INFO;        /**< D1TCM multi-bit ECC Error Information Register, offset: 0x80 */
49648   __I  uint32_t D1TCM_ECC_MULTI_ERROR_ADDR;        /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */
49649   __I  uint32_t D1TCM_ECC_MULTI_ERROR_DATA;        /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */
49650        uint8_t RESERVED_0[124];
49651   __IO uint32_t FLEXRAM_CTRL;                      /**< FlexRAM feature Control register, offset: 0x108 */
49652   __I  uint32_t OCRAM_PIPELINE_STATUS;             /**< OCRAM Pipeline Status register, offset: 0x10C */
49653 } FLEXRAM_Type;
49654 
49655 /* ----------------------------------------------------------------------------
49656    -- FLEXRAM Register Masks
49657    ---------------------------------------------------------------------------- */
49658 
49659 /*!
49660  * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
49661  * @{
49662  */
49663 
49664 /*! @name TCM_CTRL - TCM CRTL Register */
49665 /*! @{ */
49666 
49667 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK       (0x1U)
49668 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT      (0U)
49669 /*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
49670  *  0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
49671  *  0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
49672  */
49673 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
49674 
49675 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK       (0x2U)
49676 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT      (1U)
49677 /*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
49678  *  0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
49679  *  0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
49680  */
49681 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
49682 
49683 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK       (0x4U)
49684 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT      (2U)
49685 /*! FORCE_CLK_ON - Force RAM Clock Always On
49686  */
49687 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
49688 
49689 #define FLEXRAM_TCM_CTRL_Reserved_MASK           (0xFFFFFFF8U)
49690 #define FLEXRAM_TCM_CTRL_Reserved_SHIFT          (3U)
49691 /*! Reserved - Reserved
49692  */
49693 #define FLEXRAM_TCM_CTRL_Reserved(x)             (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
49694 /*! @} */
49695 
49696 /*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
49697 /*! @{ */
49698 
49699 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
49700 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
49701 /*! OCRAM_WR_RD_SEL - OCRAM Write Read Select
49702  *  0b0..When OCRAM read access hits magic address, it will generate interrupt.
49703  *  0b1..When OCRAM write access hits magic address, it will generate interrupt.
49704  */
49705 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
49706 
49707 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU)
49708 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
49709 /*! OCRAM_MAGIC_ADDR - OCRAM Magic Address
49710  */
49711 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
49712 
49713 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK   (0xFFFC0000U)
49714 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT  (18U)
49715 /*! Reserved - Reserved
49716  */
49717 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
49718 /*! @} */
49719 
49720 /*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
49721 /*! @{ */
49722 
49723 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
49724 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
49725 /*! DTCM_WR_RD_SEL - DTCM Write Read Select
49726  *  0b0..When DTCM read access hits magic address, it will generate interrupt.
49727  *  0b1..When DTCM write access hits magic address, it will generate interrupt.
49728  */
49729 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
49730 
49731 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
49732 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
49733 /*! DTCM_MAGIC_ADDR - DTCM Magic Address
49734  */
49735 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
49736 
49737 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
49738 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
49739 /*! Reserved - Reserved
49740  */
49741 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
49742 /*! @} */
49743 
49744 /*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
49745 /*! @{ */
49746 
49747 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
49748 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
49749 /*! ITCM_WR_RD_SEL - ITCM Write Read Select
49750  *  0b0..When ITCM read access hits magic address, it will generate interrupt.
49751  *  0b1..When ITCM write access hits magic address, it will generate interrupt.
49752  */
49753 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
49754 
49755 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
49756 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
49757 /*! ITCM_MAGIC_ADDR - ITCM Magic Address
49758  */
49759 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
49760 
49761 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
49762 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
49763 /*! Reserved - Reserved
49764  */
49765 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
49766 /*! @} */
49767 
49768 /*! @name INT_STATUS - Interrupt Status Register */
49769 /*! @{ */
49770 
49771 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK  (0x1U)
49772 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
49773 /*! ITCM_MAM_STATUS - ITCM Magic Address Match Status
49774  *  0b0..ITCM did not access magic address.
49775  *  0b1..ITCM accessed magic address.
49776  */
49777 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
49778 
49779 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK  (0x2U)
49780 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
49781 /*! DTCM_MAM_STATUS - DTCM Magic Address Match Status
49782  *  0b0..DTCM did not access magic address.
49783  *  0b1..DTCM accessed magic address.
49784  */
49785 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
49786 
49787 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
49788 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
49789 /*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status
49790  *  0b0..OCRAM did not access magic address.
49791  *  0b1..OCRAM accessed magic address.
49792  */
49793 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
49794 
49795 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK  (0x8U)
49796 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
49797 /*! ITCM_ERR_STATUS - ITCM Access Error Status
49798  *  0b0..ITCM access error does not happen
49799  *  0b1..ITCM access error happens.
49800  */
49801 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
49802 
49803 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK  (0x10U)
49804 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
49805 /*! DTCM_ERR_STATUS - DTCM Access Error Status
49806  *  0b0..DTCM access error does not happen
49807  *  0b1..DTCM access error happens.
49808  */
49809 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
49810 
49811 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
49812 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
49813 /*! OCRAM_ERR_STATUS - OCRAM Access Error Status
49814  *  0b0..OCRAM access error does not happen
49815  *  0b1..OCRAM access error happens.
49816  */
49817 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
49818 
49819 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U)
49820 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U)
49821 /*! OCRAM_ECC_ERRM_INT - OCRAM access multi-bit ECC Error Interrupt Status
49822  *  0b0..OCRAM multi-bit ECC error does not happen
49823  *  0b1..OCRAM multi-bit ECC error happens.
49824  */
49825 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK)
49826 
49827 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U)
49828 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U)
49829 /*! OCRAM_ECC_ERRS_INT - OCRAM access single-bit ECC Error Interrupt Status
49830  *  0b0..OCRAM single-bit ECC error does not happen
49831  *  0b1..OCRAM single-bit ECC error happens.
49832  */
49833 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK)
49834 
49835 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U)
49836 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U)
49837 /*! ITCM_ECC_ERRM_INT - ITCM Access multi-bit ECC Error Interrupt Status
49838  *  0b0..ITCM multi-bit ECC error does not happen
49839  *  0b1..ITCM multi-bit ECC error happens.
49840  */
49841 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK)
49842 
49843 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U)
49844 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U)
49845 /*! ITCM_ECC_ERRS_INT - ITCM access single-bit ECC Error Interrupt Status
49846  *  0b0..ITCM single-bit ECC error does not happen
49847  *  0b1..ITCM single-bit ECC error happens.
49848  */
49849 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK)
49850 
49851 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U)
49852 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U)
49853 /*! D0TCM_ECC_ERRM_INT - D0TCM access multi-bit ECC Error Interrupt Status
49854  *  0b0..D0TCM multi-bit ECC error does not happen
49855  *  0b1..D0TCM multi-bit ECC error happens.
49856  */
49857 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK)
49858 
49859 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U)
49860 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U)
49861 /*! D0TCM_ECC_ERRS_INT - D0TCM access single-bit ECC Error Interrupt Status
49862  *  0b0..D0TCM single-bit ECC error does not happen
49863  *  0b1..D0TCM single-bit ECC error happens.
49864  */
49865 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK)
49866 
49867 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U)
49868 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U)
49869 /*! D1TCM_ECC_ERRM_INT - D1TCM access multi-bit ECC Error Interrupt Status
49870  *  0b0..D1TCM multi-bit ECC error does not happen
49871  *  0b1..D1TCM multi-bit ECC error happens.
49872  */
49873 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK)
49874 
49875 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U)
49876 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U)
49877 /*! D1TCM_ECC_ERRS_INT - D1TCM access single-bit ECC Error Interrupt Status
49878  *  0b0..D1TCM single-bit ECC error does not happen
49879  *  0b1..D1TCM single-bit ECC error happens.
49880  */
49881 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK)
49882 
49883 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U)
49884 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U)
49885 /*! ITCM_PARTIAL_WR_INT_S - ITCM Partial Write Interrupt Status
49886  *  0b0..ITCM Partial Write does not happen
49887  *  0b1..ITCM Partial Write happens.
49888  */
49889 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK)
49890 
49891 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U)
49892 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U)
49893 /*! D0TCM_PARTIAL_WR_INT_S - D0TCM Partial Write Interrupt Status
49894  *  0b0..D0TCM Partial Write does not happen
49895  *  0b1..D0TCM Partial Write happens.
49896  */
49897 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK)
49898 
49899 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U)
49900 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U)
49901 /*! D1TCM_PARTIAL_WR_INT_S - D1TCM Partial Write Interrupt Status
49902  *  0b0..D1TCM Partial Write does not happen
49903  *  0b1..D1TCM Partial Write happens.
49904  */
49905 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK)
49906 
49907 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U)
49908 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U)
49909 /*! OCRAM_PARTIAL_WR_INT_S - OCRAM Partial Write Interrupt Status
49910  *  0b0..OCRAM Partial Write does not happen
49911  *  0b1..OCRAM Partial Write happens.
49912  */
49913 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK)
49914 
49915 #define FLEXRAM_INT_STATUS_Reserved_MASK         (0xFFFC0000U)
49916 #define FLEXRAM_INT_STATUS_Reserved_SHIFT        (18U)
49917 /*! Reserved - Reserved
49918  */
49919 #define FLEXRAM_INT_STATUS_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
49920 /*! @} */
49921 
49922 /*! @name INT_STAT_EN - Interrupt Status Enable Register */
49923 /*! @{ */
49924 
49925 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
49926 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
49927 /*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable
49928  *  0b0..Masked
49929  *  0b1..Enabled
49930  */
49931 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
49932 
49933 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
49934 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
49935 /*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable
49936  *  0b0..Masked
49937  *  0b1..Enabled
49938  */
49939 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
49940 
49941 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
49942 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
49943 /*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable
49944  *  0b0..Masked
49945  *  0b1..Enabled
49946  */
49947 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
49948 
49949 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
49950 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
49951 /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
49952  *  0b0..Masked
49953  *  0b1..Enabled
49954  */
49955 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
49956 
49957 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
49958 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
49959 /*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
49960  *  0b0..Masked
49961  *  0b1..Enabled
49962  */
49963 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
49964 
49965 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
49966 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
49967 /*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
49968  *  0b0..Masked
49969  *  0b1..Enabled
49970  */
49971 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
49972 
49973 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U)
49974 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U)
49975 /*! OCRAM_ERRM_INT_EN - OCRAM Access multi-bit ECC Error Interrupt Status Enable
49976  *  0b0..Masked
49977  *  0b1..Enabled
49978  */
49979 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK)
49980 
49981 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U)
49982 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U)
49983 /*! OCRAM_ERRS_INT_EN - OCRAM Access single-bit ECC Error Interrupt Status Enable
49984  *  0b0..Masked
49985  *  0b1..Enabled
49986  */
49987 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK)
49988 
49989 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U)
49990 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U)
49991 /*! ITCM_ERRM_INT_EN - ITCM Access multi-bit ECC Error Interrupt Status Enable
49992  *  0b0..Masked
49993  *  0b1..Enabled
49994  */
49995 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK)
49996 
49997 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U)
49998 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U)
49999 /*! ITCM_ERRS_INT_EN - ITCM Access single-bit ECC Error Interrupt Status Enable
50000  *  0b0..Masked
50001  *  0b1..Enabled
50002  */
50003 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK)
50004 
50005 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U)
50006 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U)
50007 /*! D0TCM_ERRM_INT_EN - D0TCM Access multi-bit ECC Error Interrupt Status Enable
50008  *  0b0..Masked
50009  *  0b1..Enabled
50010  */
50011 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK)
50012 
50013 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U)
50014 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U)
50015 /*! D0TCM_ERRS_INT_EN - D0TCM Access single-bit ECC Error Interrupt Status Enable
50016  *  0b0..Masked
50017  *  0b1..Enabled
50018  */
50019 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK)
50020 
50021 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U)
50022 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U)
50023 /*! D1TCM_ERRM_INT_EN - D1TCM Access multi-bit ECC Error Interrupt Status Enable
50024  *  0b0..Masked
50025  *  0b1..Enabled
50026  */
50027 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK)
50028 
50029 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U)
50030 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U)
50031 /*! D1TCM_ERRS_INT_EN - D1TCM Access single-bit ECC Error Interrupt Status Enable
50032  *  0b0..Masked
50033  *  0b1..Enabled
50034  */
50035 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK)
50036 
50037 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U)
50038 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U)
50039 /*! ITCM_PARTIAL_WR_INT_S_EN - ITCM Partial Write Interrupt Status Enable
50040  *  0b0..Masked
50041  *  0b1..Enabled
50042  */
50043 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK)
50044 
50045 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U)
50046 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U)
50047 /*! D0TCM_PARTIAL_WR_INT_S_EN - D0TCM Partial Write Interrupt Status Enable
50048  *  0b0..Masked
50049  *  0b1..Enabled
50050  */
50051 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK)
50052 
50053 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U)
50054 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U)
50055 /*! D1TCM_PARTIAL_WR_INT_S_EN - D1TCM Partial Write Interrupt Status EN
50056  *  0b0..Masked
50057  *  0b1..Enbaled
50058  */
50059 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK)
50060 
50061 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U)
50062 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U)
50063 /*! OCRAM_PARTIAL_WR_INT_S_EN - OCRAM Partial Write Interrupt Status
50064  *  0b0..Masked
50065  *  0b1..Enabled
50066  */
50067 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK)
50068 
50069 #define FLEXRAM_INT_STAT_EN_Reserved_MASK        (0xFFFC0000U)
50070 #define FLEXRAM_INT_STAT_EN_Reserved_SHIFT       (18U)
50071 /*! Reserved - Reserved
50072  */
50073 #define FLEXRAM_INT_STAT_EN_Reserved(x)          (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
50074 /*! @} */
50075 
50076 /*! @name INT_SIG_EN - Interrupt Enable Register */
50077 /*! @{ */
50078 
50079 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK  (0x1U)
50080 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
50081 /*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable
50082  *  0b0..Masked
50083  *  0b1..Enabled
50084  */
50085 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
50086 
50087 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK  (0x2U)
50088 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
50089 /*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable
50090  *  0b0..Masked
50091  *  0b1..Enabled
50092  */
50093 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
50094 
50095 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
50096 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
50097 /*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable
50098  *  0b0..Masked
50099  *  0b1..Enabled
50100  */
50101 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
50102 
50103 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK  (0x8U)
50104 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
50105 /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
50106  *  0b0..Masked
50107  *  0b1..Enabled
50108  */
50109 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
50110 
50111 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK  (0x10U)
50112 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
50113 /*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
50114  *  0b0..Masked
50115  *  0b1..Enabled
50116  */
50117 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
50118 
50119 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
50120 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
50121 /*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
50122  *  0b0..Masked
50123  *  0b1..Enabled
50124  */
50125 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
50126 
50127 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U)
50128 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U)
50129 /*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi-bit ECC Error Interrupt Signal Enable
50130  *  0b0..Masked
50131  *  0b1..Enabled
50132  */
50133 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK)
50134 
50135 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U)
50136 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U)
50137 /*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single-bit ECC Error Interrupt Signal Enable
50138  *  0b0..Masked
50139  *  0b1..Enabled
50140  */
50141 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK)
50142 
50143 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U)
50144 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U)
50145 /*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi-bit ECC Error Interrupt Signal Enable
50146  *  0b0..Masked
50147  *  0b1..Enabled
50148  */
50149 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK)
50150 
50151 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U)
50152 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U)
50153 /*! ITCM_ERRS_INT_SIG_EN - ITCM Access single-bit ECC Error Interrupt Signal Enable
50154  *  0b0..Masked
50155  *  0b1..Enabled
50156  */
50157 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK)
50158 
50159 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U)
50160 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U)
50161 /*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi-bit ECC Error Interrupt Signal Enable
50162  *  0b0..Masked
50163  *  0b1..Enabled
50164  */
50165 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK)
50166 
50167 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U)
50168 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U)
50169 /*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single-bit ECC Error Interrupt Signal Enable
50170  *  0b0..Masked
50171  *  0b1..Enabled
50172  */
50173 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK)
50174 
50175 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
50176 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U)
50177 /*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi-bit ECC Error Interrupt Signal Enable
50178  *  0b0..Masked
50179  *  0b1..Enabled
50180  */
50181 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK)
50182 
50183 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
50184 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U)
50185 /*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single-bit ECC Error Interrupt Signal Enable
50186  *  0b0..Masked
50187  *  0b1..Enabled
50188  */
50189 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK)
50190 
50191 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U)
50192 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U)
50193 /*! ITCM_PARTIAL_WR_INT_SIG_EN - ITCM Partial Write Interrupt Signal Enable Enable
50194  *  0b0..Masked
50195  *  0b1..Enabled
50196  */
50197 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK)
50198 
50199 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U)
50200 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U)
50201 /*! D0TCM_PARTIAL_WR_INT_SIG_EN - D0TCM Partial Write Interrupt Signal Enable Enable
50202  *  0b0..Masked
50203  *  0b1..Enabled
50204  */
50205 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK)
50206 
50207 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U)
50208 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U)
50209 /*! D1TCM_PARTIAL_WR_INT_SIG_EN - D1TCM Partial Write Interrupt Signal Enable EN
50210  *  0b0..Masked
50211  *  0b1..Enbaled
50212  */
50213 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK)
50214 
50215 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U)
50216 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U)
50217 /*! OCRAM_PARTIAL_WR_INT_SIG_EN - OCRAM Partial Write Interrupt Signal Enable
50218  *  0b0..Masked
50219  *  0b1..Enabled
50220  */
50221 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK)
50222 
50223 #define FLEXRAM_INT_SIG_EN_Reserved_MASK         (0xFFFC0000U)
50224 #define FLEXRAM_INT_SIG_EN_Reserved_SHIFT        (18U)
50225 /*! Reserved - Reserved
50226  */
50227 #define FLEXRAM_INT_SIG_EN_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
50228 /*! @} */
50229 
50230 /*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register */
50231 /*! @{ */
50232 
50233 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU)
50234 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U)
50235 /*! OCRAM_ECCS_ERRED_ECC - corresponding ECC cipher of OCRAM single-bit ECC error
50236  */
50237 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK)
50238 
50239 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U)
50240 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U)
50241 /*! OCRAM_ECCS_ERRED_SYN - corresponding ECC syndrome of OCRAM single-bit ECC error
50242  */
50243 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK)
50244 
50245 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U)
50246 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U)
50247 /*! Reserved - Reserved
50248  */
50249 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
50250 /*! @} */
50251 
50252 /*! @name OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register */
50253 /*! @{ */
50254 
50255 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
50256 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U)
50257 /*! OCRAM_ECCS_ERRED_ADDR - OCRAM single-bit ECC error address
50258  */
50259 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK)
50260 /*! @} */
50261 
50262 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register */
50263 /*! @{ */
50264 
50265 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
50266 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
50267 /*! OCRAM_ECCS_ERRED_DATA_LSB - OCRAM single-bit ECC error data [31:0]
50268  */
50269 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK)
50270 /*! @} */
50271 
50272 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register */
50273 /*! @{ */
50274 
50275 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
50276 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
50277 /*! OCRAM_ECCS_ERRED_DATA_MSB - OCRAM single-bit ECC error data [63:32]
50278  */
50279 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK)
50280 /*! @} */
50281 
50282 /*! @name OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register */
50283 /*! @{ */
50284 
50285 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU)
50286 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U)
50287 /*! OCRAM_ECCM_ERRED_ECC - OCRAM multi-bit ECC error corresponding ECC value
50288  */
50289 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK)
50290 
50291 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U)
50292 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U)
50293 /*! Reserved - Reserved
50294  */
50295 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
50296 /*! @} */
50297 
50298 /*! @name OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register */
50299 /*! @{ */
50300 
50301 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
50302 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U)
50303 /*! OCRAM_ECCM_ERRED_ADDR - OCRAM multi-bit ECC error address
50304  */
50305 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK)
50306 /*! @} */
50307 
50308 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register */
50309 /*! @{ */
50310 
50311 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
50312 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
50313 /*! OCRAM_ECCM_ERRED_DATA_LSB - OCRAM multi-bit ECC error data [31:0]
50314  */
50315 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK)
50316 /*! @} */
50317 
50318 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register */
50319 /*! @{ */
50320 
50321 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
50322 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
50323 /*! OCRAM_ECCM_ERRED_DATA_MSB - OCRAM multi-bit ECC error data [63:32]
50324  */
50325 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK)
50326 /*! @} */
50327 
50328 /*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register */
50329 /*! @{ */
50330 
50331 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U)
50332 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U)
50333 /*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding TCM_WR value.
50334  */
50335 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK)
50336 
50337 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU)
50338 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U)
50339 /*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding TCM size
50340  */
50341 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK)
50342 
50343 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U)
50344 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U)
50345 /*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding TCM_MASTER.
50346  */
50347 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK)
50348 
50349 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U)
50350 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U)
50351 /*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding TCM_PRIV.
50352  */
50353 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK)
50354 
50355 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U)
50356 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U)
50357 /*! ITCM_ECCS_EFSYN - ITCM single-bit ECC error corresponding syndrome
50358  */
50359 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK)
50360 
50361 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U)
50362 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U)
50363 /*! Reserved - Reserved
50364  */
50365 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
50366 /*! @} */
50367 
50368 /*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */
50369 /*! @{ */
50370 
50371 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
50372 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U)
50373 /*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address
50374  */
50375 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK)
50376 /*! @} */
50377 
50378 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */
50379 /*! @{ */
50380 
50381 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
50382 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
50383 /*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0]
50384  */
50385 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK)
50386 /*! @} */
50387 
50388 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */
50389 /*! @{ */
50390 
50391 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
50392 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
50393 /*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32]
50394  */
50395 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK)
50396 /*! @} */
50397 
50398 /*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */
50399 /*! @{ */
50400 
50401 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U)
50402 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U)
50403 /*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding TCM_WR value
50404  */
50405 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK)
50406 
50407 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU)
50408 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U)
50409 /*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size
50410  */
50411 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK)
50412 
50413 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U)
50414 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U)
50415 /*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding TCM_MASTER
50416  */
50417 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK)
50418 
50419 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U)
50420 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U)
50421 /*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding TCM_PRIV
50422  */
50423 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK)
50424 
50425 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U)
50426 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U)
50427 /*! ITCM_ECCM_EFSYN - ITCM multi-bit ECC error corresponding syndrome
50428  */
50429 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK)
50430 
50431 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U)
50432 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U)
50433 /*! Reserved - Reserved
50434  */
50435 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
50436 /*! @} */
50437 
50438 /*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */
50439 /*! @{ */
50440 
50441 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
50442 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U)
50443 /*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address
50444  */
50445 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK)
50446 /*! @} */
50447 
50448 /*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */
50449 /*! @{ */
50450 
50451 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
50452 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
50453 /*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0]
50454  */
50455 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK)
50456 /*! @} */
50457 
50458 /*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */
50459 /*! @{ */
50460 
50461 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
50462 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
50463 /*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32]
50464  */
50465 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK)
50466 /*! @} */
50467 
50468 /*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */
50469 /*! @{ */
50470 
50471 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U)
50472 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U)
50473 /*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding TCM_WR value
50474  */
50475 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK)
50476 
50477 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU)
50478 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U)
50479 /*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size
50480  */
50481 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK)
50482 
50483 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U)
50484 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U)
50485 /*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding TCM_MASTER
50486  */
50487 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK)
50488 
50489 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U)
50490 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U)
50491 /*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding TCM_PRIV
50492  */
50493 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK)
50494 
50495 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U)
50496 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U)
50497 /*! D0TCM_ECCS_EFSYN - D0TCM single-bit ECC error corresponding syndrome
50498  */
50499 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK)
50500 
50501 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50502 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
50503 /*! Reserved - Reserved
50504  */
50505 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
50506 /*! @} */
50507 
50508 /*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */
50509 /*! @{ */
50510 
50511 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
50512 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U)
50513 /*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address
50514  */
50515 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK)
50516 /*! @} */
50517 
50518 /*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */
50519 /*! @{ */
50520 
50521 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
50522 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U)
50523 /*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data
50524  */
50525 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK)
50526 /*! @} */
50527 
50528 /*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */
50529 /*! @{ */
50530 
50531 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U)
50532 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U)
50533 /*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding TCM_WR value
50534  */
50535 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK)
50536 
50537 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU)
50538 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U)
50539 /*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size
50540  */
50541 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK)
50542 
50543 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U)
50544 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U)
50545 /*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding TCM_MASTER
50546  */
50547 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK)
50548 
50549 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U)
50550 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U)
50551 /*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding TCM_PRIV
50552  */
50553 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK)
50554 
50555 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U)
50556 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U)
50557 /*! D0TCM_ECCM_EFSYN - D0TCM multi-bit ECC error corresponding syndrome
50558  */
50559 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK)
50560 
50561 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50562 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
50563 /*! Reserved - Reserved
50564  */
50565 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
50566 /*! @} */
50567 
50568 /*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */
50569 /*! @{ */
50570 
50571 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
50572 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U)
50573 /*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address
50574  */
50575 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK)
50576 /*! @} */
50577 
50578 /*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */
50579 /*! @{ */
50580 
50581 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
50582 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U)
50583 /*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data
50584  */
50585 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK)
50586 /*! @} */
50587 
50588 /*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */
50589 /*! @{ */
50590 
50591 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U)
50592 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U)
50593 /*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding TCM_WR value
50594  */
50595 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK)
50596 
50597 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU)
50598 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U)
50599 /*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size
50600  */
50601 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK)
50602 
50603 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U)
50604 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U)
50605 /*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding TCM_MASTER
50606  */
50607 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK)
50608 
50609 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U)
50610 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U)
50611 /*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding TCM_PRIV
50612  */
50613 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK)
50614 
50615 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U)
50616 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U)
50617 /*! D1TCM_ECCS_EFSYN - D1TCM single-bit ECC error corresponding syndrome
50618  */
50619 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK)
50620 
50621 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50622 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
50623 /*! Reserved - Reserved
50624  */
50625 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
50626 /*! @} */
50627 
50628 /*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */
50629 /*! @{ */
50630 
50631 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
50632 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U)
50633 /*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address
50634  */
50635 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK)
50636 /*! @} */
50637 
50638 /*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */
50639 /*! @{ */
50640 
50641 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
50642 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U)
50643 /*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data
50644  */
50645 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK)
50646 /*! @} */
50647 
50648 /*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */
50649 /*! @{ */
50650 
50651 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U)
50652 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U)
50653 /*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding TCM_WR value
50654  */
50655 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK)
50656 
50657 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU)
50658 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U)
50659 /*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size
50660  */
50661 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK)
50662 
50663 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U)
50664 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U)
50665 /*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding TCM_MASTER
50666  */
50667 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK)
50668 
50669 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U)
50670 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U)
50671 /*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding TCM_PRIV
50672  */
50673 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK)
50674 
50675 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U)
50676 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U)
50677 /*! D1TCM_ECCM_EFSYN - D1TCM multi-bit ECC error corresponding syndrome
50678  */
50679 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK)
50680 
50681 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
50682 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
50683 /*! Reserved - Reserved
50684  */
50685 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
50686 /*! @} */
50687 
50688 /*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */
50689 /*! @{ */
50690 
50691 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
50692 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U)
50693 /*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address
50694  */
50695 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK)
50696 /*! @} */
50697 
50698 /*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */
50699 /*! @{ */
50700 
50701 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
50702 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U)
50703 /*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data
50704  */
50705 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK)
50706 /*! @} */
50707 
50708 /*! @name FLEXRAM_CTRL - FlexRAM feature Control register */
50709 /*! @{ */
50710 
50711 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U)
50712 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U)
50713 /*! OCRAM_RDATA_WAIT_EN - Read Data Wait Enable
50714  */
50715 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK)
50716 
50717 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U)
50718 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U)
50719 /*! OCRAM_RADDR_PIPELINE_EN - Read Address Pipeline Enable
50720  */
50721 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK)
50722 
50723 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U)
50724 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U)
50725 /*! OCRAM_WRDATA_PIPELINE_EN - Write Data Pipeline Enable
50726  */
50727 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK)
50728 
50729 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U)
50730 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U)
50731 /*! OCRAM_WRADDR_PIPELINE_EN - Write Address Pipeline Enable
50732  */
50733 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK)
50734 
50735 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK   (0x10U)
50736 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT  (4U)
50737 /*! OCRAM_ECC_EN - OCRAM ECC enable
50738  */
50739 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK)
50740 
50741 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK     (0x20U)
50742 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT    (5U)
50743 /*! TCM_ECC_EN - TCM ECC enable
50744  */
50745 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x)       (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK)
50746 
50747 #define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK       (0xFFFFFFC0U)
50748 #define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT      (6U)
50749 /*! Reserved - Reserved
50750  */
50751 #define FLEXRAM_FLEXRAM_CTRL_Reserved(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK)
50752 /*! @} */
50753 
50754 /*! @name OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register */
50755 /*! @{ */
50756 
50757 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U)
50758 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U)
50759 /*! OCRAM_RDATA_WAIT_EN_UPDATA_PENDING - Read Data Wait Enable Pending
50760  */
50761 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK)
50762 
50763 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U)
50764 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U)
50765 /*! OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING - Read Address Pipeline Enable Pending
50766  */
50767 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
50768 
50769 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U)
50770 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U)
50771 /*! OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING - Write Data Pipeline Enable Pending
50772  */
50773 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK)
50774 
50775 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U)
50776 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U)
50777 /*! OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING - Write Address Pipeline Enable Pending
50778  */
50779 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
50780 
50781 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U)
50782 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U)
50783 /*! Reserved - Reserved
50784  */
50785 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK)
50786 /*! @} */
50787 
50788 
50789 /*!
50790  * @}
50791  */ /* end of group FLEXRAM_Register_Masks */
50792 
50793 
50794 /* FLEXRAM - Peripheral instance base addresses */
50795 /** Peripheral FLEXRAM base address */
50796 #define FLEXRAM_BASE                             (0x40028000u)
50797 /** Peripheral FLEXRAM base pointer */
50798 #define FLEXRAM                                  ((FLEXRAM_Type *)FLEXRAM_BASE)
50799 /** Array initializer of FLEXRAM peripheral base addresses */
50800 #define FLEXRAM_BASE_ADDRS                       { FLEXRAM_BASE }
50801 /** Array initializer of FLEXRAM peripheral base pointers */
50802 #define FLEXRAM_BASE_PTRS                        { FLEXRAM }
50803 /** Interrupt vectors for the FLEXRAM peripheral type */
50804 #define FLEXRAM_IRQS                             { FLEXRAM_IRQn }
50805 #define FLEXRAM_ECC_IRQS                         { FLEXRAM_ECC_IRQn }
50806 
50807 /*!
50808  * @}
50809  */ /* end of group FLEXRAM_Peripheral_Access_Layer */
50810 
50811 
50812 /* ----------------------------------------------------------------------------
50813    -- FLEXSPI Peripheral Access Layer
50814    ---------------------------------------------------------------------------- */
50815 
50816 /*!
50817  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
50818  * @{
50819  */
50820 
50821 /** FLEXSPI - Register Layout Typedef */
50822 typedef struct {
50823   __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
50824   __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
50825   __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
50826   __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
50827   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
50828   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
50829   __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
50830   __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
50831   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
50832        uint8_t RESERVED_0[32];
50833   __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
50834   __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
50835   __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
50836        uint8_t RESERVED_1[4];
50837   __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
50838        uint8_t RESERVED_2[8];
50839   __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
50840   __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
50841        uint8_t RESERVED_3[8];
50842   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
50843        uint8_t RESERVED_4[4];
50844   __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
50845   __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
50846   __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
50847        uint8_t RESERVED_5[8];
50848   __I  uint32_t MISCCR4;                           /**< Misc Control Register 4, offset: 0xD0 */
50849   __I  uint32_t MISCCR5;                           /**< Misc Control Register 5, offset: 0xD4 */
50850   __I  uint32_t MISCCR6;                           /**< Misc Control Register 6, offset: 0xD8 */
50851   __I  uint32_t MISCCR7;                           /**< Misc Control Register 7, offset: 0xDC */
50852   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
50853   __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
50854   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
50855   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
50856   __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
50857   __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
50858        uint8_t RESERVED_6[8];
50859   __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
50860   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
50861   __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
50862        uint8_t RESERVED_7[256];
50863   __IO uint32_t HMSTRCR[8];                        /**< AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4 */
50864   __IO uint32_t HADDRSTART;                        /**< HADDR REMAP START ADDR, offset: 0x420 */
50865   __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
50866   __IO uint32_t HADDROFFSET;                       /**< HADDR REMAP OFFSET, offset: 0x428 */
50867        uint8_t RESERVED_8[4];
50868   __IO uint32_t IPSNSZSTART0;                      /**< IPS nonsecure region Start address of region 0, offset: 0x430 */
50869   __IO uint32_t IPSNSZEND0;                        /**< IPS nonsecure region End address of region 0, offset: 0x434 */
50870   __IO uint32_t IPSNSZSTART1;                      /**< IPS nonsecure region Start address of region 1, offset: 0x438 */
50871   __IO uint32_t IPSNSZEND1;                        /**< IPS nonsecure region End address of region 1, offset: 0x43C */
50872   __IO uint32_t AHBBUFREGIONSTART0;                /**< RX BUF Start address of region 0, offset: 0x440 */
50873   __IO uint32_t AHBBUFREGIONEND0;                  /**< RX BUF region End address of region 0, offset: 0x444 */
50874   __IO uint32_t AHBBUFREGIONSTART1;                /**< RX BUF Start address of region 1, offset: 0x448 */
50875   __IO uint32_t AHBBUFREGIONEND1;                  /**< RX BUF region End address of region 1, offset: 0x44C */
50876   __IO uint32_t AHBBUFREGIONSTART2;                /**< RX BUF Start address of region 2, offset: 0x450 */
50877   __IO uint32_t AHBBUFREGIONEND2;                  /**< RX BUF region End address of region 2, offset: 0x454 */
50878   __IO uint32_t AHBBUFREGIONSTART3;                /**< RX BUF Start address of region 3, offset: 0x458 */
50879   __IO uint32_t AHBBUFREGIONEND3;                  /**< RX BUF region End address of region 3, offset: 0x45C */
50880 } FLEXSPI_Type;
50881 
50882 /* ----------------------------------------------------------------------------
50883    -- FLEXSPI Register Masks
50884    ---------------------------------------------------------------------------- */
50885 
50886 /*!
50887  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
50888  * @{
50889  */
50890 
50891 /*! @name MCR0 - Module Control Register 0 */
50892 /*! @{ */
50893 
50894 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
50895 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
50896 /*! SWRESET - Software Reset
50897  */
50898 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
50899 
50900 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
50901 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
50902 /*! MDIS - Module Disable
50903  */
50904 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
50905 
50906 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
50907 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
50908 /*! RXCLKSRC - Sample Clock source selection for Flash Reading
50909  *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
50910  *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
50911  *  0b10..Reserved
50912  *  0b11..Flash provided Read strobe and input from DQS pad
50913  */
50914 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
50915 
50916 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
50917 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
50918 /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
50919  *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
50920  *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
50921  */
50922 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
50923 
50924 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
50925 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
50926 /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
50927  *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
50928  *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
50929  */
50930 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
50931 
50932 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
50933 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
50934 /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
50935  *  0b000..Divided by 1
50936  *  0b001..Divided by 2
50937  *  0b010..Divided by 3
50938  *  0b011..Divided by 4
50939  *  0b100..Divided by 5
50940  *  0b101..Divided by 6
50941  *  0b110..Divided by 7
50942  *  0b111..Divided by 8
50943  */
50944 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
50945 
50946 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
50947 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
50948 /*! HSEN - Half Speed Serial Flash access Enable.
50949  *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
50950  *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
50951  */
50952 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
50953 
50954 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
50955 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
50956 /*! DOZEEN - Doze mode enable bit
50957  *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
50958  *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
50959  */
50960 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
50961 
50962 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
50963 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
50964 /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data
50965  *    pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.
50966  *  0b0..Disable.
50967  *  0b1..Enable.
50968  */
50969 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
50970 
50971 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
50972 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
50973 /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
50974  *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
50975  *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
50976  *  0b0..Disable.
50977  *  0b1..Enable.
50978  */
50979 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
50980 
50981 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
50982 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
50983 /*! IPGRANTWAIT - Time out wait cycle for IP command grant.
50984  */
50985 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
50986 
50987 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
50988 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
50989 /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
50990  */
50991 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
50992 /*! @} */
50993 
50994 /*! @name MCR1 - Module Control Register 1 */
50995 /*! @{ */
50996 
50997 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
50998 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
50999 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
51000 
51001 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
51002 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
51003 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
51004 /*! @} */
51005 
51006 /*! @name MCR2 - Module Control Register 2 */
51007 /*! @{ */
51008 
51009 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
51010 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
51011 /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
51012  *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
51013  *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
51014  *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
51015  *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
51016  *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
51017  */
51018 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
51019 
51020 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
51021 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
51022 /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
51023  *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
51024  *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
51025  *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
51026  *       ignored.
51027  *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
51028  */
51029 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
51030 
51031 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
51032 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
51033 /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
51034  *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
51035  *    field, MCR0[SWRESET] should be set.
51036  *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
51037  *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
51038  */
51039 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
51040 
51041 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
51042 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
51043 /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
51044  */
51045 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
51046 /*! @} */
51047 
51048 /*! @name AHBCR - AHB Bus Control Register */
51049 /*! @{ */
51050 
51051 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
51052 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
51053 /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
51054  *  0b0..Flash will be accessed in Individual mode.
51055  *  0b1..Flash will be accessed in Parallel mode.
51056  */
51057 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
51058 
51059 #define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
51060 #define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
51061 /*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
51062  */
51063 #define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
51064 
51065 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
51066 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
51067 /*! CACHABLEEN - Enable AHB bus cachable read access support.
51068  *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
51069  *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
51070  */
51071 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
51072 
51073 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
51074 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
51075 /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
51076  *    of AHB write access, refer for more details about AHB bufferable write.
51077  *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
51078  *       ready after all data is transmitted to External device and AHB command finished.
51079  *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
51080  *       granted by arbitrator and will not wait for AHB command finished.
51081  */
51082 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
51083 
51084 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
51085 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
51086 /*! PREFETCHEN - AHB Read Prefetch Enable.
51087  */
51088 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
51089 
51090 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
51091 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
51092 /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
51093  *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.
51094  *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
51095  *       burst required to meet the alignment requirement.
51096  */
51097 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
51098 
51099 #define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
51100 #define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
51101 /*! READSZALIGN - AHB Read Size Alignment
51102  *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
51103  *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
51104  */
51105 #define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
51106 
51107 #define FLEXSPI_AHBCR_ECCEN_MASK                 (0x800U)
51108 #define FLEXSPI_AHBCR_ECCEN_SHIFT                (11U)
51109 /*! ECCEN - AHB Read ECC Enable
51110  *  0b0..AHB read ECC check disabled
51111  *  0b1..AHB read ECC check enabled
51112  */
51113 #define FLEXSPI_AHBCR_ECCEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK)
51114 
51115 #define FLEXSPI_AHBCR_SPLITEN_MASK               (0x1000U)
51116 #define FLEXSPI_AHBCR_SPLITEN_SHIFT              (12U)
51117 /*! SPLITEN - AHB transaction SPLIT
51118  *  0b0..AHB Split disabled
51119  *  0b1..AHB Split enabled
51120  */
51121 #define FLEXSPI_AHBCR_SPLITEN(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK)
51122 
51123 #define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK           (0x6000U)
51124 #define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT          (13U)
51125 /*! SPLIT_LIMIT - AHB SPLIT SIZE
51126  *  0b00..AHB Split Size=8bytes
51127  *  0b01..AHB Split Size=16bytes
51128  *  0b10..AHB Split Size=32bytes
51129  *  0b11..AHB Split Size=64bytes
51130  */
51131 #define FLEXSPI_AHBCR_SPLIT_LIMIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK)
51132 
51133 #define FLEXSPI_AHBCR_KEYECCEN_MASK              (0x8000U)
51134 #define FLEXSPI_AHBCR_KEYECCEN_SHIFT             (15U)
51135 /*! KEYECCEN - OTFAD KEY BLOC ECC Enable
51136  *  0b0..AHB KEY ECC check disabled
51137  *  0b1..AHB KEY ECC check enabled
51138  */
51139 #define FLEXSPI_AHBCR_KEYECCEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK)
51140 
51141 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK       (0x10000U)
51142 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT      (16U)
51143 /*! ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR
51144  */
51145 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK)
51146 
51147 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK        (0x20000U)
51148 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT       (17U)
51149 /*! ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR
51150  */
51151 #define FLEXSPI_AHBCR_ECCMULTIERRCLR(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK)
51152 
51153 #define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK          (0x40000U)
51154 #define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT         (18U)
51155 /*! HMSTRIDREMAP - AHB Master ID Remapping enable
51156  */
51157 #define FLEXSPI_AHBCR_HMSTRIDREMAP(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK)
51158 
51159 #define FLEXSPI_AHBCR_ECCSWAPEN_MASK             (0x80000U)
51160 #define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT            (19U)
51161 /*! ECCSWAPEN - ECC Read data swap function
51162  *  0b0..rdata send to ecc check without swap.
51163  *  0b1..rdata send to ecc ehck with swap.
51164  */
51165 #define FLEXSPI_AHBCR_ECCSWAPEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK)
51166 
51167 #define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
51168 #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
51169 /*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses.
51170  *  0b00..No limit
51171  *  0b01..1 KBytes
51172  *  0b10..512 Bytes
51173  *  0b11..256 Bytes
51174  */
51175 #define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
51176 /*! @} */
51177 
51178 /*! @name INTEN - Interrupt Enable Register */
51179 /*! @{ */
51180 
51181 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
51182 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
51183 /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
51184  */
51185 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
51186 
51187 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
51188 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
51189 /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
51190  */
51191 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
51192 
51193 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
51194 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
51195 /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
51196  */
51197 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
51198 
51199 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
51200 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
51201 /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
51202  */
51203 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
51204 
51205 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
51206 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
51207 /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
51208  */
51209 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
51210 
51211 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
51212 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
51213 /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
51214  */
51215 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
51216 
51217 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
51218 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
51219 /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
51220  */
51221 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
51222 
51223 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
51224 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
51225 /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
51226  */
51227 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
51228 
51229 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
51230 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
51231 /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
51232  */
51233 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
51234 
51235 #define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
51236 #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
51237 /*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
51238  */
51239 #define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
51240 
51241 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
51242 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
51243 /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
51244  */
51245 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
51246 
51247 #define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
51248 #define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
51249 /*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
51250  */
51251 #define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
51252 
51253 #define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
51254 #define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
51255 /*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
51256  */
51257 #define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
51258 
51259 #define FLEXSPI_INTEN_ECCMULTIERREN_MASK         (0x4000U)
51260 #define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT        (14U)
51261 /*! ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details.
51262  */
51263 #define FLEXSPI_INTEN_ECCMULTIERREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK)
51264 
51265 #define FLEXSPI_INTEN_ECCSINGLEERREN_MASK        (0x8000U)
51266 #define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT       (15U)
51267 /*! ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details.
51268  */
51269 #define FLEXSPI_INTEN_ECCSINGLEERREN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK)
51270 
51271 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK      (0x10000U)
51272 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT     (16U)
51273 /*! IPCMDSECUREVIOEN - IP command security violation interrupt enable.
51274  */
51275 #define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
51276 /*! @} */
51277 
51278 /*! @name INTR - Interrupt Register */
51279 /*! @{ */
51280 
51281 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
51282 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
51283 /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
51284  *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
51285  */
51286 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
51287 
51288 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
51289 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
51290 /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
51291  */
51292 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
51293 
51294 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
51295 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
51296 /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
51297  */
51298 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
51299 
51300 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
51301 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
51302 /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
51303  *    IP command, this command will be ignored and not executed at all.
51304  */
51305 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
51306 
51307 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
51308 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
51309 /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
51310  *    AHB command, this command will be ignored and not executed at all.
51311  */
51312 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
51313 
51314 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
51315 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
51316 /*! IPRXWA - IP RX FIFO watermark available interrupt.
51317  */
51318 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
51319 
51320 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
51321 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
51322 /*! IPTXWE - IP TX FIFO watermark empty interrupt.
51323  */
51324 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
51325 
51326 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
51327 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
51328 /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
51329  */
51330 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
51331 
51332 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
51333 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
51334 /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
51335  */
51336 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
51337 
51338 #define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
51339 #define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
51340 /*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
51341  */
51342 #define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
51343 
51344 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
51345 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
51346 /*! SEQTIMEOUT - Sequence execution timeout interrupt.
51347  */
51348 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
51349 
51350 #define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
51351 #define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
51352 /*! KEYDONE - OTFAD key blob processing done interrupt.
51353  */
51354 #define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
51355 
51356 #define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
51357 #define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
51358 /*! KEYERROR - OTFAD key blob processing error interrupt.
51359  */
51360 #define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
51361 
51362 #define FLEXSPI_INTR_ECCMULTIERR_MASK            (0x4000U)
51363 #define FLEXSPI_INTR_ECCMULTIERR_SHIFT           (14U)
51364 /*! ECCMULTIERR - ECC multi bits error interrupt.
51365  */
51366 #define FLEXSPI_INTR_ECCMULTIERR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK)
51367 
51368 #define FLEXSPI_INTR_ECCSINGLEERR_MASK           (0x8000U)
51369 #define FLEXSPI_INTR_ECCSINGLEERR_SHIFT          (15U)
51370 /*! ECCSINGLEERR - ECC single bit error interrupt.
51371  */
51372 #define FLEXSPI_INTR_ECCSINGLEERR(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK)
51373 
51374 #define FLEXSPI_INTR_IPCMDSECUREVIO_MASK         (0x10000U)
51375 #define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT        (16U)
51376 /*! IPCMDSECUREVIO - IP command security violation interrupt.
51377  */
51378 #define FLEXSPI_INTR_IPCMDSECUREVIO(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
51379 /*! @} */
51380 
51381 /*! @name LUTKEY - LUT Key Register */
51382 /*! @{ */
51383 
51384 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
51385 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
51386 /*! KEY - The Key to lock or unlock LUT.
51387  */
51388 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
51389 /*! @} */
51390 
51391 /*! @name LUTCR - LUT Control Register */
51392 /*! @{ */
51393 
51394 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
51395 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
51396 /*! LOCK - Lock LUT
51397  */
51398 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
51399 
51400 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
51401 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
51402 /*! UNLOCK - Unlock LUT
51403  */
51404 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
51405 
51406 #define FLEXSPI_LUTCR_PROTECT_MASK               (0x4U)
51407 #define FLEXSPI_LUTCR_PROTECT_SHIFT              (2U)
51408 /*! PROTECT - LUT protection
51409  */
51410 #define FLEXSPI_LUTCR_PROTECT(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
51411 /*! @} */
51412 
51413 /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
51414 /*! @{ */
51415 
51416 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x3FFU)
51417 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
51418 /*! BUFSZ - AHB RX Buffer Size in 64 bits.
51419  */
51420 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
51421 
51422 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
51423 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
51424 /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
51425  */
51426 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
51427 
51428 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
51429 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
51430 /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
51431  */
51432 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
51433 
51434 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK        (0x40000000U)
51435 #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT       (30U)
51436 /*! REGIONEN - AHB RX Buffer address region funciton enable
51437  */
51438 #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
51439 
51440 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
51441 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
51442 /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
51443  */
51444 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
51445 /*! @} */
51446 
51447 /* The count of FLEXSPI_AHBRXBUFCR0 */
51448 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
51449 
51450 /*! @name FLSHCR0 - Flash Control Register 0 */
51451 /*! @{ */
51452 
51453 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
51454 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
51455 /*! FLSHSZ - Flash Size in KByte.
51456  */
51457 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
51458 
51459 #define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
51460 #define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
51461 /*! SPLITWREN - AHB write access split function control.
51462  */
51463 #define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
51464 
51465 #define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
51466 #define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
51467 /*! SPLITRDEN - AHB read access split function control.
51468  */
51469 #define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
51470 /*! @} */
51471 
51472 /* The count of FLEXSPI_FLSHCR0 */
51473 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
51474 
51475 /*! @name FLSHCR1 - Flash Control Register 1 */
51476 /*! @{ */
51477 
51478 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
51479 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
51480 /*! TCSS - Serial Flash CS setup time.
51481  */
51482 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
51483 
51484 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
51485 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
51486 /*! TCSH - Serial Flash CS Hold time.
51487  */
51488 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
51489 
51490 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
51491 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
51492 /*! WA - Word Addressable.
51493  */
51494 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
51495 
51496 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
51497 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
51498 /*! CAS - Column Address Size.
51499  */
51500 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
51501 
51502 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
51503 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
51504 /*! CSINTERVALUNIT - CS interval unit
51505  *  0b0..The CS interval unit is 1 serial clock cycle
51506  *  0b1..The CS interval unit is 256 serial clock cycle
51507  */
51508 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
51509 
51510 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
51511 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
51512 /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
51513  *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
51514  *    the interval between command sequences, this field should be set accordingly. If there is no
51515  *    limitation, set this field with value 0x0.
51516  */
51517 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
51518 /*! @} */
51519 
51520 /* The count of FLEXSPI_FLSHCR1 */
51521 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
51522 
51523 /*! @name FLSHCR2 - Flash Control Register 2 */
51524 /*! @{ */
51525 
51526 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
51527 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
51528 /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
51529  */
51530 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
51531 
51532 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
51533 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
51534 /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
51535  */
51536 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
51537 
51538 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
51539 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
51540 /*! AWRSEQID - Sequence Index for AHB Write triggered Command.
51541  */
51542 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
51543 
51544 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
51545 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
51546 /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
51547  */
51548 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
51549 
51550 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
51551 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
51552 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
51553 
51554 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
51555 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
51556 /*! AWRWAITUNIT - AWRWAIT unit
51557  *  0b000..The AWRWAIT unit is 2 ahb clock cycle
51558  *  0b001..The AWRWAIT unit is 8 ahb clock cycle
51559  *  0b010..The AWRWAIT unit is 32 ahb clock cycle
51560  *  0b011..The AWRWAIT unit is 128 ahb clock cycle
51561  *  0b100..The AWRWAIT unit is 512 ahb clock cycle
51562  *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
51563  *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
51564  *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
51565  */
51566 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
51567 
51568 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
51569 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
51570 /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
51571  *    Refer Programmable Sequence Engine for details.
51572  */
51573 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
51574 /*! @} */
51575 
51576 /* The count of FLEXSPI_FLSHCR2 */
51577 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
51578 
51579 /*! @name FLSHCR4 - Flash Control Register 4 */
51580 /*! @{ */
51581 
51582 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
51583 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
51584 /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
51585  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
51586  *       burst start address alignment when flash is accessed in individual mode.
51587  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
51588  *       burst start address alignment when flash is accessed in individual mode.
51589  */
51590 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
51591 
51592 #define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
51593 #define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
51594 /*! WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove
51595  *    AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set.
51596  *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
51597  *       burst length when flash is accessed in individual mode.
51598  *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
51599  *       burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
51600  */
51601 #define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
51602 
51603 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
51604 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
51605 /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
51606  *    memory device on port A, this bit must be set.
51607  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
51608  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
51609  */
51610 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
51611 
51612 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
51613 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
51614 /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
51615  *    memory device on port B, this bit must be set.
51616  *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
51617  *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
51618  */
51619 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
51620 
51621 #define FLEXSPI_FLSHCR4_PAR_WM_MASK              (0x600U)
51622 #define FLEXSPI_FLSHCR4_PAR_WM_SHIFT             (9U)
51623 /*! PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.
51624  */
51625 #define FLEXSPI_FLSHCR4_PAR_WM(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK)
51626 
51627 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK    (0x800U)
51628 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT   (11U)
51629 /*! PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM.
51630  */
51631 #define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK)
51632 /*! @} */
51633 
51634 /*! @name IPCR0 - IP Control Register 0 */
51635 /*! @{ */
51636 
51637 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
51638 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
51639 /*! SFAR - Serial Flash Address for IP command.
51640  */
51641 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
51642 /*! @} */
51643 
51644 /*! @name IPCR1 - IP Control Register 1 */
51645 /*! @{ */
51646 
51647 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
51648 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
51649 /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
51650  */
51651 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
51652 
51653 #define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
51654 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
51655 /*! ISEQID - Sequence Index in LUT for IP command.
51656  */
51657 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
51658 
51659 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
51660 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
51661 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
51662  */
51663 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
51664 
51665 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
51666 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
51667 /*! IPAREN - Parallel mode Enabled for IP command.
51668  *  0b0..Flash will be accessed in Individual mode.
51669  *  0b1..Flash will be accessed in Parallel mode.
51670  */
51671 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
51672 /*! @} */
51673 
51674 /*! @name IPCMD - IP Command Register */
51675 /*! @{ */
51676 
51677 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
51678 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
51679 /*! TRG - Setting this bit will trigger an IP Command.
51680  */
51681 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
51682 /*! @} */
51683 
51684 /*! @name IPRXFCR - IP RX FIFO Control Register */
51685 /*! @{ */
51686 
51687 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
51688 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
51689 /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
51690  */
51691 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
51692 
51693 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
51694 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
51695 /*! RXDMAEN - IP RX FIFO reading by DMA enabled.
51696  *  0b0..IP RX FIFO would be read by processor.
51697  *  0b1..IP RX FIFO would be read by DMA.
51698  */
51699 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
51700 
51701 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x7CU)
51702 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
51703 /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
51704  */
51705 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
51706 /*! @} */
51707 
51708 /*! @name IPTXFCR - IP TX FIFO Control Register */
51709 /*! @{ */
51710 
51711 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
51712 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
51713 /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
51714  */
51715 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
51716 
51717 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
51718 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
51719 /*! TXDMAEN - IP TX FIFO filling by DMA enabled.
51720  *  0b0..IP TX FIFO would be filled by processor.
51721  *  0b1..IP TX FIFO would be filled by DMA.
51722  */
51723 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
51724 
51725 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x7CU)
51726 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
51727 /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
51728  */
51729 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
51730 /*! @} */
51731 
51732 /*! @name DLLCR - DLL Control Register 0 */
51733 /*! @{ */
51734 
51735 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
51736 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
51737 /*! DLLEN - DLL calibration enable.
51738  */
51739 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
51740 
51741 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
51742 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
51743 /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
51744  *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
51745  *    action is edge triggered, so software need to clear this bit after set this bit (no delay
51746  *    limitation).
51747  */
51748 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
51749 
51750 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
51751 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
51752 /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
51753  *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
51754  *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
51755  */
51756 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
51757 
51758 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
51759 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
51760 /*! OVRDEN - Slave clock delay line delay cell number selection override enable.
51761  */
51762 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
51763 
51764 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
51765 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
51766 /*! OVRDVAL - Slave clock delay line delay cell number selection override value.
51767  */
51768 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
51769 /*! @} */
51770 
51771 /* The count of FLEXSPI_DLLCR */
51772 #define FLEXSPI_DLLCR_COUNT                      (2U)
51773 
51774 /*! @name MISCCR4 - Misc Control Register 4 */
51775 /*! @{ */
51776 
51777 #define FLEXSPI_MISCCR4_AHBADDRESS_MASK          (0xFFFFFFFFU)
51778 #define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT         (0U)
51779 /*! AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt.
51780  */
51781 #define FLEXSPI_MISCCR4_AHBADDRESS(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK)
51782 /*! @} */
51783 
51784 /*! @name MISCCR5 - Misc Control Register 5 */
51785 /*! @{ */
51786 
51787 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK  (0xFFFFFFFFU)
51788 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U)
51789 /*! ECCSINGLEERRORCORR - ECC single bit error correction indication.
51790  */
51791 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK)
51792 /*! @} */
51793 
51794 /*! @name MISCCR6 - Misc Control Register 6 */
51795 /*! @{ */
51796 
51797 #define FLEXSPI_MISCCR6_VALID_MASK               (0x1U)
51798 #define FLEXSPI_MISCCR6_VALID_SHIFT              (0U)
51799 /*! VALID - ECC single error information Valid
51800  */
51801 #define FLEXSPI_MISCCR6_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK)
51802 
51803 #define FLEXSPI_MISCCR6_HIT_MASK                 (0x2U)
51804 #define FLEXSPI_MISCCR6_HIT_SHIFT                (1U)
51805 /*! HIT - ECC single error information Hit
51806  */
51807 #define FLEXSPI_MISCCR6_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK)
51808 
51809 #define FLEXSPI_MISCCR6_ADDRESS_MASK             (0xFFFFFFFCU)
51810 #define FLEXSPI_MISCCR6_ADDRESS_SHIFT            (2U)
51811 /*! ADDRESS - ECC single error address
51812  */
51813 #define FLEXSPI_MISCCR6_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK)
51814 /*! @} */
51815 
51816 /*! @name MISCCR7 - Misc Control Register 7 */
51817 /*! @{ */
51818 
51819 #define FLEXSPI_MISCCR7_VALID_MASK               (0x1U)
51820 #define FLEXSPI_MISCCR7_VALID_SHIFT              (0U)
51821 /*! VALID - ECC multi error information Valid
51822  */
51823 #define FLEXSPI_MISCCR7_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK)
51824 
51825 #define FLEXSPI_MISCCR7_HIT_MASK                 (0x2U)
51826 #define FLEXSPI_MISCCR7_HIT_SHIFT                (1U)
51827 /*! HIT - ECC multi error information Hit
51828  */
51829 #define FLEXSPI_MISCCR7_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK)
51830 
51831 #define FLEXSPI_MISCCR7_ADDRESS_MASK             (0xFFFFFFFCU)
51832 #define FLEXSPI_MISCCR7_ADDRESS_SHIFT            (2U)
51833 /*! ADDRESS - ECC multi error address
51834  */
51835 #define FLEXSPI_MISCCR7_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK)
51836 /*! @} */
51837 
51838 /*! @name STS0 - Status Register 0 */
51839 /*! @{ */
51840 
51841 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
51842 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
51843 /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
51844  *    sequence executing on FlexSPI interface.
51845  */
51846 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
51847 
51848 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
51849 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
51850 /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
51851  *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
51852  *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
51853  *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
51854  */
51855 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
51856 
51857 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
51858 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
51859 /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
51860  *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
51861  *  0b00..Triggered by AHB read command (triggered by AHB read).
51862  *  0b01..Triggered by AHB write command (triggered by AHB Write).
51863  *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
51864  *  0b11..Triggered by suspended command (resumed).
51865  */
51866 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
51867 /*! @} */
51868 
51869 /*! @name STS1 - Status Register 1 */
51870 /*! @{ */
51871 
51872 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
51873 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
51874 /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
51875  *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
51876  */
51877 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
51878 
51879 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
51880 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
51881 /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
51882  *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
51883  *  0b0000..No error.
51884  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
51885  *  0b0011..There is unknown instruction opcode in the sequence.
51886  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
51887  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
51888  *  0b1110..Sequence execution timeout.
51889  */
51890 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
51891 
51892 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
51893 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
51894 /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
51895  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
51896  */
51897 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
51898 
51899 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
51900 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
51901 /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
51902  *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
51903  *  0b0000..No error.
51904  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
51905  *  0b0011..There is unknown instruction opcode in the sequence.
51906  *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
51907  *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
51908  *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
51909  *  0b1110..Sequence execution timeout.
51910  *  0b1111..Flash boundary crossed.
51911  */
51912 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
51913 /*! @} */
51914 
51915 /*! @name STS2 - Status Register 2 */
51916 /*! @{ */
51917 
51918 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
51919 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
51920 /*! ASLVLOCK - Flash A sample clock slave delay line locked.
51921  */
51922 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
51923 
51924 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
51925 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
51926 /*! AREFLOCK - Flash A sample clock reference delay line locked.
51927  */
51928 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
51929 
51930 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
51931 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
51932 /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
51933  */
51934 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
51935 
51936 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
51937 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
51938 /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
51939  */
51940 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
51941 
51942 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
51943 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
51944 /*! BSLVLOCK - Flash B sample clock slave delay line locked.
51945  */
51946 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
51947 
51948 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
51949 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
51950 /*! BREFLOCK - Flash B sample clock reference delay line locked.
51951  */
51952 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
51953 
51954 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
51955 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
51956 /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
51957  */
51958 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
51959 
51960 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
51961 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
51962 /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
51963  */
51964 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
51965 /*! @} */
51966 
51967 /*! @name AHBSPNDSTS - AHB Suspend Status Register */
51968 /*! @{ */
51969 
51970 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
51971 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
51972 /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
51973  */
51974 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
51975 
51976 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
51977 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
51978 /*! BUFID - AHB RX BUF ID for suspended command sequence.
51979  */
51980 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
51981 
51982 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
51983 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
51984 /*! DATLFT - Left Data size for suspended command sequence (in byte).
51985  */
51986 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
51987 /*! @} */
51988 
51989 /*! @name IPRXFSTS - IP RX FIFO Status Register */
51990 /*! @{ */
51991 
51992 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
51993 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
51994 /*! FILL - Fill level of IP RX FIFO.
51995  */
51996 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
51997 
51998 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
51999 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
52000 /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
52001  */
52002 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
52003 /*! @} */
52004 
52005 /*! @name IPTXFSTS - IP TX FIFO Status Register */
52006 /*! @{ */
52007 
52008 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
52009 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
52010 /*! FILL - Fill level of IP TX FIFO.
52011  */
52012 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
52013 
52014 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
52015 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
52016 /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
52017  */
52018 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
52019 /*! @} */
52020 
52021 /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
52022 /*! @{ */
52023 
52024 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
52025 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
52026 /*! RXDATA - RX Data
52027  */
52028 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
52029 /*! @} */
52030 
52031 /* The count of FLEXSPI_RFDR */
52032 #define FLEXSPI_RFDR_COUNT                       (32U)
52033 
52034 /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
52035 /*! @{ */
52036 
52037 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
52038 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
52039 /*! TXDATA - TX Data
52040  */
52041 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
52042 /*! @} */
52043 
52044 /* The count of FLEXSPI_TFDR */
52045 #define FLEXSPI_TFDR_COUNT                       (32U)
52046 
52047 /*! @name LUT - LUT 0..LUT 63 */
52048 /*! @{ */
52049 
52050 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
52051 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
52052 /*! OPERAND0 - OPERAND0
52053  */
52054 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
52055 
52056 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
52057 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
52058 /*! NUM_PADS0 - NUM_PADS0
52059  */
52060 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
52061 
52062 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
52063 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
52064 /*! OPCODE0 - OPCODE
52065  */
52066 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
52067 
52068 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
52069 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
52070 /*! OPERAND1 - OPERAND1
52071  */
52072 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
52073 
52074 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
52075 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
52076 /*! NUM_PADS1 - NUM_PADS1
52077  */
52078 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
52079 
52080 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
52081 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
52082 /*! OPCODE1 - OPCODE1
52083  */
52084 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
52085 /*! @} */
52086 
52087 /* The count of FLEXSPI_LUT */
52088 #define FLEXSPI_LUT_COUNT                        (64U)
52089 
52090 /*! @name HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register */
52091 /*! @{ */
52092 
52093 #define FLEXSPI_HMSTRCR_MASK_MASK                (0xFFFFU)
52094 #define FLEXSPI_HMSTRCR_MASK_SHIFT               (0U)
52095 /*! MASK - Mask bits for AHB master ID.
52096  *  0b0000000000000000..Mask
52097  *  0b0000000000000001..Unmask
52098  */
52099 #define FLEXSPI_HMSTRCR_MASK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK)
52100 
52101 #define FLEXSPI_HMSTRCR_MSTRID_MASK              (0xFFFF0000U)
52102 #define FLEXSPI_HMSTRCR_MSTRID_SHIFT             (16U)
52103 /*! MSTRID - This is expected Master ID.
52104  */
52105 #define FLEXSPI_HMSTRCR_MSTRID(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK)
52106 /*! @} */
52107 
52108 /* The count of FLEXSPI_HMSTRCR */
52109 #define FLEXSPI_HMSTRCR_COUNT                    (8U)
52110 
52111 /*! @name HADDRSTART - HADDR REMAP START ADDR */
52112 /*! @{ */
52113 
52114 #define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
52115 #define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
52116 /*! REMAPEN
52117  *  0b0..HADDR REMAP Disabled
52118  *  0b1..HADDR REMAP Enabled
52119  */
52120 #define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
52121 
52122 #define FLEXSPI_HADDRSTART_KBINECC_MASK          (0x2U)
52123 #define FLEXSPI_HADDRSTART_KBINECC_SHIFT         (1U)
52124 /*! KBINECC
52125  *  0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset
52126  *  0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2
52127  */
52128 #define FLEXSPI_HADDRSTART_KBINECC(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK)
52129 
52130 #define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
52131 #define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
52132 #define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
52133 /*! @} */
52134 
52135 /*! @name HADDREND - HADDR REMAP END ADDR */
52136 /*! @{ */
52137 
52138 #define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
52139 #define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
52140 #define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
52141 /*! @} */
52142 
52143 /*! @name HADDROFFSET - HADDR REMAP OFFSET */
52144 /*! @{ */
52145 
52146 #define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
52147 #define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
52148 #define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
52149 /*! @} */
52150 
52151 /*! @name IPSNSZSTART0 - IPS nonsecure region Start address of region 0 */
52152 /*! @{ */
52153 
52154 #define FLEXSPI_IPSNSZSTART0_start_address_MASK  (0xFFFFF000U)
52155 #define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U)
52156 /*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address.
52157  */
52158 #define FLEXSPI_IPSNSZSTART0_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK)
52159 /*! @} */
52160 
52161 /*! @name IPSNSZEND0 - IPS nonsecure region End address of region 0 */
52162 /*! @{ */
52163 
52164 #define FLEXSPI_IPSNSZEND0_end_address_MASK      (0xFFFFF000U)
52165 #define FLEXSPI_IPSNSZEND0_end_address_SHIFT     (12U)
52166 /*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address.
52167  */
52168 #define FLEXSPI_IPSNSZEND0_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK)
52169 /*! @} */
52170 
52171 /*! @name IPSNSZSTART1 - IPS nonsecure region Start address of region 1 */
52172 /*! @{ */
52173 
52174 #define FLEXSPI_IPSNSZSTART1_start_address_MASK  (0xFFFFF000U)
52175 #define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U)
52176 /*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address.
52177  */
52178 #define FLEXSPI_IPSNSZSTART1_start_address(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK)
52179 /*! @} */
52180 
52181 /*! @name IPSNSZEND1 - IPS nonsecure region End address of region 1 */
52182 /*! @{ */
52183 
52184 #define FLEXSPI_IPSNSZEND1_end_address_MASK      (0xFFFFF000U)
52185 #define FLEXSPI_IPSNSZEND1_end_address_SHIFT     (12U)
52186 /*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address.
52187  */
52188 #define FLEXSPI_IPSNSZEND1_end_address(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK)
52189 /*! @} */
52190 
52191 /*! @name AHBBUFREGIONSTART0 - RX BUF Start address of region 0 */
52192 /*! @{ */
52193 
52194 #define FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U)
52195 #define FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U)
52196 /*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address.
52197  */
52198 #define FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK)
52199 /*! @} */
52200 
52201 /*! @name AHBBUFREGIONEND0 - RX BUF region End address of region 0 */
52202 /*! @{ */
52203 
52204 #define FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U)
52205 #define FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U)
52206 /*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address.
52207  */
52208 #define FLEXSPI_AHBBUFREGIONEND0_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK)
52209 /*! @} */
52210 
52211 /*! @name AHBBUFREGIONSTART1 - RX BUF Start address of region 1 */
52212 /*! @{ */
52213 
52214 #define FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U)
52215 #define FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U)
52216 /*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address.
52217  */
52218 #define FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK)
52219 /*! @} */
52220 
52221 /*! @name AHBBUFREGIONEND1 - RX BUF region End address of region 1 */
52222 /*! @{ */
52223 
52224 #define FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U)
52225 #define FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U)
52226 /*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address.
52227  */
52228 #define FLEXSPI_AHBBUFREGIONEND1_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK)
52229 /*! @} */
52230 
52231 /*! @name AHBBUFREGIONSTART2 - RX BUF Start address of region 2 */
52232 /*! @{ */
52233 
52234 #define FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U)
52235 #define FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U)
52236 /*! start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address.
52237  */
52238 #define FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK)
52239 /*! @} */
52240 
52241 /*! @name AHBBUFREGIONEND2 - RX BUF region End address of region 2 */
52242 /*! @{ */
52243 
52244 #define FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U)
52245 #define FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U)
52246 /*! end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address.
52247  */
52248 #define FLEXSPI_AHBBUFREGIONEND2_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK)
52249 /*! @} */
52250 
52251 /*! @name AHBBUFREGIONSTART3 - RX BUF Start address of region 3 */
52252 /*! @{ */
52253 
52254 #define FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U)
52255 #define FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U)
52256 /*! start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address.
52257  */
52258 #define FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK)
52259 /*! @} */
52260 
52261 /*! @name AHBBUFREGIONEND3 - RX BUF region End address of region 3 */
52262 /*! @{ */
52263 
52264 #define FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U)
52265 #define FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U)
52266 /*! end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address.
52267  */
52268 #define FLEXSPI_AHBBUFREGIONEND3_end_address(x)  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK)
52269 /*! @} */
52270 
52271 
52272 /*!
52273  * @}
52274  */ /* end of group FLEXSPI_Register_Masks */
52275 
52276 
52277 /* FLEXSPI - Peripheral instance base addresses */
52278 /** Peripheral FLEXSPI1 base address */
52279 #define FLEXSPI1_BASE                            (0x400CC000u)
52280 /** Peripheral FLEXSPI1 base pointer */
52281 #define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
52282 /** Peripheral FLEXSPI2 base address */
52283 #define FLEXSPI2_BASE                            (0x400D0000u)
52284 /** Peripheral FLEXSPI2 base pointer */
52285 #define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
52286 /** Array initializer of FLEXSPI peripheral base addresses */
52287 #define FLEXSPI_BASE_ADDRS                       { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
52288 /** Array initializer of FLEXSPI peripheral base pointers */
52289 #define FLEXSPI_BASE_PTRS                        { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
52290 /** Interrupt vectors for the FLEXSPI peripheral type */
52291 #define FLEXSPI_IRQS                             { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
52292 /* FlexSPI1 AMBA address. */
52293 #define FlexSPI1_AMBA_BASE                       (0x30000000U)
52294 /* FlexSPI1 ASFM address. */
52295 #define FlexSPI1_ASFM_BASE                       (0x30000000U)
52296 /* Base Address of AHB address space mapped to IP RX FIFO. */
52297 #define FlexSPI1_ARDF_BASE                       (0x2FC00000U)
52298 /* Base Address of AHB address space mapped to IP TX FIFO. */
52299 #define FlexSPI1_ATDF_BASE                       (0x2F800000U)
52300 /* FlexSPI1 alias base address. */
52301 #define FlexSPI1_ALIAS_BASE                      (0x8000000U)
52302 /* FlexSPI2 AMBA address. */
52303 #define FlexSPI2_AMBA_BASE                       (0x60000000U)
52304 /* FlexSPI ASFM address. */
52305 #define FlexSPI2_ASFM_BASE                       (0x60000000U)
52306 /* Base Address of AHB address space mapped to IP RX FIFO. */
52307 #define FlexSPI2_ARDF_BASE                       (0x7FC00000U)
52308 /* Base Address of AHB address space mapped to IP TX FIFO. */
52309 #define FlexSPI2_ATDF_BASE                       (0x7F800000U)
52310 
52311 
52312 /*!
52313  * @}
52314  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
52315 
52316 
52317 /* ----------------------------------------------------------------------------
52318    -- GPC_CPU_MODE_CTRL Peripheral Access Layer
52319    ---------------------------------------------------------------------------- */
52320 
52321 /*!
52322  * @addtogroup GPC_CPU_MODE_CTRL_Peripheral_Access_Layer GPC_CPU_MODE_CTRL Peripheral Access Layer
52323  * @{
52324  */
52325 
52326 /** GPC_CPU_MODE_CTRL - Register Layout Typedef */
52327 typedef struct {
52328        uint8_t RESERVED_0[4];
52329   __IO uint32_t CM_AUTHEN_CTRL;                    /**< CM Authentication Control, offset: 0x4 */
52330   __IO uint32_t CM_INT_CTRL;                       /**< CM Interrupt Control, offset: 0x8 */
52331   __IO uint32_t CM_MISC;                           /**< Miscellaneous, offset: 0xC */
52332   __IO uint32_t CM_MODE_CTRL;                      /**< CPU mode control, offset: 0x10 */
52333   __I  uint32_t CM_MODE_STAT;                      /**< CM CPU mode Status, offset: 0x14 */
52334        uint8_t RESERVED_1[232];
52335   __IO uint32_t CM_IRQ_WAKEUP_MASK[8];             /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4 */
52336        uint8_t RESERVED_2[32];
52337   __IO uint32_t CM_NON_IRQ_WAKEUP_MASK;            /**< CM non-irq wakeup mask, offset: 0x140 */
52338        uint8_t RESERVED_3[12];
52339   __I  uint32_t CM_IRQ_WAKEUP_STAT[8];             /**< CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4 */
52340        uint8_t RESERVED_4[32];
52341   __I  uint32_t CM_NON_IRQ_WAKEUP_STAT;            /**< CM non-irq wakeup status, offset: 0x190 */
52342        uint8_t RESERVED_5[108];
52343   __IO uint32_t CM_SLEEP_SSAR_CTRL;                /**< CM sleep SSAR control, offset: 0x200 */
52344        uint8_t RESERVED_6[4];
52345   __IO uint32_t CM_SLEEP_LPCG_CTRL;                /**< CM sleep LPCG control, offset: 0x208 */
52346        uint8_t RESERVED_7[4];
52347   __IO uint32_t CM_SLEEP_PLL_CTRL;                 /**< CM sleep PLL control, offset: 0x210 */
52348        uint8_t RESERVED_8[4];
52349   __IO uint32_t CM_SLEEP_ISO_CTRL;                 /**< CM sleep isolation control, offset: 0x218 */
52350        uint8_t RESERVED_9[4];
52351   __IO uint32_t CM_SLEEP_RESET_CTRL;               /**< CM sleep reset control, offset: 0x220 */
52352        uint8_t RESERVED_10[4];
52353   __IO uint32_t CM_SLEEP_POWER_CTRL;               /**< CM sleep power control, offset: 0x228 */
52354        uint8_t RESERVED_11[100];
52355   __IO uint32_t CM_WAKEUP_POWER_CTRL;              /**< CM wakeup power control, offset: 0x290 */
52356        uint8_t RESERVED_12[4];
52357   __IO uint32_t CM_WAKEUP_RESET_CTRL;              /**< CM wakeup reset control, offset: 0x298 */
52358        uint8_t RESERVED_13[4];
52359   __IO uint32_t CM_WAKEUP_ISO_CTRL;                /**< CM wakeup isolation control, offset: 0x2A0 */
52360        uint8_t RESERVED_14[4];
52361   __IO uint32_t CM_WAKEUP_PLL_CTRL;                /**< CM wakeup PLL control, offset: 0x2A8 */
52362        uint8_t RESERVED_15[4];
52363   __IO uint32_t CM_WAKEUP_LPCG_CTRL;               /**< CM wakeup LPCG control, offset: 0x2B0 */
52364        uint8_t RESERVED_16[4];
52365   __IO uint32_t CM_WAKEUP_SSAR_CTRL;               /**< CM wakeup SSAR control, offset: 0x2B8 */
52366        uint8_t RESERVED_17[68];
52367   __IO uint32_t CM_SP_CTRL;                        /**< CM Setpoint Control, offset: 0x300 */
52368   __I  uint32_t CM_SP_STAT;                        /**< CM Setpoint Status, offset: 0x304 */
52369        uint8_t RESERVED_18[8];
52370   __IO uint32_t CM_RUN_MODE_MAPPING;               /**< CM Run Mode Setpoint Allowed, offset: 0x310 */
52371   __IO uint32_t CM_WAIT_MODE_MAPPING;              /**< CM Wait Mode Setpoint Allowed, offset: 0x314 */
52372   __IO uint32_t CM_STOP_MODE_MAPPING;              /**< CM Stop Mode Setpoint Allowed, offset: 0x318 */
52373   __IO uint32_t CM_SUSPEND_MODE_MAPPING;           /**< CM Suspend Mode Setpoint Allowed, offset: 0x31C */
52374   __IO uint32_t CM_SP_MAPPING[16];                 /**< CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4 */
52375        uint8_t RESERVED_19[32];
52376   __IO uint32_t CM_STBY_CTRL;                      /**< CM standby control, offset: 0x380 */
52377 } GPC_CPU_MODE_CTRL_Type;
52378 
52379 /* ----------------------------------------------------------------------------
52380    -- GPC_CPU_MODE_CTRL Register Masks
52381    ---------------------------------------------------------------------------- */
52382 
52383 /*!
52384  * @addtogroup GPC_CPU_MODE_CTRL_Register_Masks GPC_CPU_MODE_CTRL Register Masks
52385  * @{
52386  */
52387 
52388 /*! @name CM_AUTHEN_CTRL - CM Authentication Control */
52389 /*! @{ */
52390 
52391 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U)
52392 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U)
52393 /*! USER - Allow user mode access
52394  *  0b0..Allow only privilege mode to access CPU mode control registers
52395  *  0b1..Allow both privilege and user mode to access CPU mode control registers
52396  */
52397 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK)
52398 
52399 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
52400 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
52401 /*! NONSECURE - Allow non-secure mode access
52402  *  0b0..Allow only secure mode to access CPU mode control registers
52403  *  0b1..Allow both secure and non-secure mode to access CPU mode control registers
52404  */
52405 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
52406 
52407 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
52408 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
52409 /*! LOCK_SETTING - Lock NONSECURE and USER
52410  */
52411 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
52412 
52413 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
52414 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
52415 /*! WHITE_LIST - Domain ID white list
52416  */
52417 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
52418 
52419 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
52420 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
52421 /*! LOCK_LIST - White list lock
52422  */
52423 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
52424 
52425 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
52426 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
52427 /*! LOCK_CFG - Configuration lock
52428  */
52429 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
52430 /*! @} */
52431 
52432 /*! @name CM_INT_CTRL - CM Interrupt Control */
52433 /*! @{ */
52434 
52435 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U)
52436 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U)
52437 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT_EN - sp_req_not_allowed_for_sleep interrupt enable
52438  *  0b0..Interrupt disable
52439  *  0b1..Interrupt enable
52440  */
52441 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK)
52442 
52443 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U)
52444 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U)
52445 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN - sp_req_not_allowed_for_wakeup interrupt enable
52446  *  0b0..Interrupt disable
52447  *  0b1..Interrupt enable
52448  */
52449 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK)
52450 
52451 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U)
52452 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U)
52453 /*! SP_REQ_NOT_ALLOWED_SOFT_INT_EN - sp_req_not_allowed_for_soft interrupt enable
52454  *  0b0..Interrupt disable
52455  *  0b1..Interrupt enable
52456  */
52457 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK)
52458 
52459 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U)
52460 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U)
52461 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT - sp_req_not_allowed_for_sleep interrupt status and clear register
52462  */
52463 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK)
52464 
52465 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U)
52466 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U)
52467 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT - sp_req_not_allowed_for_wakeup interrupt status and clear register
52468  */
52469 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK)
52470 
52471 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U)
52472 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U)
52473 /*! SP_REQ_NOT_ALLOWED_SOFT_INT - sp_req_not_allowed_for_soft interrupt status and clear register
52474  */
52475 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
52476 /*! @} */
52477 
52478 /*! @name CM_MISC - Miscellaneous */
52479 /*! @{ */
52480 
52481 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK  (0x1U)
52482 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U)
52483 /*! NMI_STAT - Non-masked interrupt status
52484  *  0b0..NMI is not asserting
52485  *  0b1..NMI is asserting
52486  */
52487 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x)    (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK)
52488 
52489 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U)
52490 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
52491 /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status
52492  *  0b0..Disable cpu_sleep_hold_req
52493  *  0b1..Allow cpu_sleep_hold_req assert during CPU low power status
52494  */
52495 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
52496 
52497 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
52498 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
52499 /*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b
52500  */
52501 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
52502 
52503 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U)
52504 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U)
52505 /*! MASTER_CPU - Master CPU
52506  */
52507 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x)  (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK)
52508 /*! @} */
52509 
52510 /*! @name CM_MODE_CTRL - CPU mode control */
52511 /*! @{ */
52512 
52513 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
52514 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
52515 /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event
52516  *  0b00..Stay in RUN mode
52517  *  0b01..Transit to WAIT mode
52518  *  0b10..Transit to STOP mode
52519  *  0b11..Transit to SUSPEND mode
52520  */
52521 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
52522 
52523 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U)
52524 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U)
52525 /*! WFE_EN - WFE assertion can be sleep event
52526  *  0b0..WFE assertion can not trigger low power
52527  *  0b1..WFE assertion can trigger low power
52528  */
52529 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
52530 /*! @} */
52531 
52532 /*! @name CM_MODE_STAT - CM CPU mode Status */
52533 /*! @{ */
52534 
52535 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
52536 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
52537 /*! CPU_MODE_CURRENT - Current CPU mode
52538  *  0b00..CPU is currently in RUN mode
52539  *  0b01..CPU is currently in WAIT mode
52540  *  0b10..CPU is currently in STOP mode
52541  *  0b11..CPU is currently in SUSPEND mode
52542  */
52543 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
52544 
52545 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
52546 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
52547 /*! CPU_MODE_PREVIOUS - Previous CPU mode
52548  *  0b00..CPU was previously in RUN mode
52549  *  0b01..CPU was previously in WAIT mode
52550  *  0b10..CPU was previously in STOP mode
52551  *  0b11..CPU was previously in SUSPEND mode
52552  */
52553 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
52554 /*! @} */
52555 
52556 /*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */
52557 /*! @{ */
52558 
52559 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU)
52560 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U)
52561 /*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform
52562  */
52563 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK)
52564 
52565 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU)
52566 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U)
52567 /*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform
52568  */
52569 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK)
52570 
52571 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU)
52572 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U)
52573 /*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform
52574  */
52575 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK)
52576 
52577 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU)
52578 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U)
52579 /*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform
52580  */
52581 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK)
52582 
52583 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU)
52584 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U)
52585 /*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform
52586  */
52587 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK)
52588 
52589 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU)
52590 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U)
52591 /*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform
52592  */
52593 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK)
52594 
52595 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU)
52596 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U)
52597 /*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform
52598  */
52599 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK)
52600 
52601 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
52602 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
52603 /*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform
52604  */
52605 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK)
52606 /*! @} */
52607 
52608 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK */
52609 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U)
52610 
52611 /*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask */
52612 /*! @{ */
52613 
52614 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U)
52615 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U)
52616 /*! EVENT_WAKEUP_MASK - There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source.
52617  *  0b1..The event cannot wakeup CPU platform
52618  */
52619 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK)
52620 
52621 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
52622 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
52623 /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform
52624  */
52625 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
52626 /*! @} */
52627 
52628 /*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */
52629 /*! @{ */
52630 
52631 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
52632 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
52633 /*! IRQ_WAKEUP_MASK_224_255 - IRQ status
52634  *  0b00000000000000000000000000000000..None
52635  *  0b00000000000000000000000000000001..Valid
52636  */
52637 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK)
52638 
52639 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU)
52640 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U)
52641 /*! IRQ_WAKEUP_STAT_0_31 - IRQ status
52642  *  0b00000000000000000000000000000000..None
52643  *  0b00000000000000000000000000000001..Valid
52644  */
52645 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK)
52646 
52647 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU)
52648 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U)
52649 /*! IRQ_WAKEUP_STAT_32_63 - IRQ status
52650  *  0b00000000000000000000000000000000..None
52651  *  0b00000000000000000000000000000001..Valid
52652  */
52653 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK)
52654 
52655 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU)
52656 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U)
52657 /*! IRQ_WAKEUP_STAT_64_95 - IRQ status
52658  *  0b00000000000000000000000000000000..None
52659  *  0b00000000000000000000000000000001..Valid
52660  */
52661 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK)
52662 
52663 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU)
52664 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U)
52665 /*! IRQ_WAKEUP_STAT_96_127 - IRQ status
52666  *  0b00000000000000000000000000000000..None
52667  *  0b00000000000000000000000000000001..Valid
52668  */
52669 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK)
52670 
52671 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU)
52672 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U)
52673 /*! IRQ_WAKEUP_STAT_128_159 - IRQ status
52674  *  0b00000000000000000000000000000000..None
52675  *  0b00000000000000000000000000000001..Valid
52676  */
52677 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK)
52678 
52679 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU)
52680 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U)
52681 /*! IRQ_WAKEUP_STAT_160_191 - IRQ status
52682  *  0b00000000000000000000000000000000..None
52683  *  0b00000000000000000000000000000001..Valid
52684  */
52685 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK)
52686 
52687 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU)
52688 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U)
52689 /*! IRQ_WAKEUP_STAT_192_223 - IRQ status
52690  *  0b00000000000000000000000000000000..None
52691  *  0b00000000000000000000000000000001..Valid
52692  */
52693 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK)
52694 /*! @} */
52695 
52696 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT */
52697 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U)
52698 
52699 /*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */
52700 /*! @{ */
52701 
52702 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U)
52703 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U)
52704 /*! EVENT_WAKEUP_STAT - Event wakeup status
52705  *  0b1..Interrupt is asserting (pending)
52706  */
52707 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK)
52708 
52709 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
52710 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
52711 /*! DEBUG_WAKEUP_STAT - Debug wakeup status
52712  */
52713 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
52714 /*! @} */
52715 
52716 /*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */
52717 /*! @{ */
52718 
52719 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
52720 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
52721 /*! STEP_CNT - Step count, useage is depending on CNT_MODE.
52722  */
52723 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK)
52724 
52725 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
52726 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
52727 /*! CNT_MODE - Count mode
52728  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52729  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52730  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52731  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52732  */
52733 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK)
52734 
52735 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
52736 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
52737 /*! DISABLE - Disable this step
52738  */
52739 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
52740 /*! @} */
52741 
52742 /*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */
52743 /*! @{ */
52744 
52745 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
52746 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
52747 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52748  */
52749 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK)
52750 
52751 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
52752 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
52753 /*! CNT_MODE - Count mode
52754  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52755  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52756  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52757  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52758  */
52759 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK)
52760 
52761 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
52762 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
52763 /*! DISABLE - Disable this step
52764  */
52765 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
52766 /*! @} */
52767 
52768 /*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */
52769 /*! @{ */
52770 
52771 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
52772 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U)
52773 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52774  */
52775 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK)
52776 
52777 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
52778 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U)
52779 /*! CNT_MODE - Count mode
52780  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52781  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52782  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52783  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52784  */
52785 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK)
52786 
52787 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
52788 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
52789 /*! DISABLE - Disable this step
52790  */
52791 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
52792 /*! @} */
52793 
52794 /*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */
52795 /*! @{ */
52796 
52797 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
52798 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U)
52799 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52800  */
52801 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK)
52802 
52803 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
52804 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U)
52805 /*! CNT_MODE - Count mode
52806  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52807  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52808  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52809  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52810  */
52811 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK)
52812 
52813 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
52814 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
52815 /*! DISABLE - Disable this step
52816  */
52817 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
52818 /*! @} */
52819 
52820 /*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */
52821 /*! @{ */
52822 
52823 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
52824 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U)
52825 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52826  */
52827 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK)
52828 
52829 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
52830 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U)
52831 /*! CNT_MODE - Count mode
52832  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52833  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52834  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52835  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52836  */
52837 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK)
52838 
52839 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
52840 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
52841 /*! DISABLE - Disable this step
52842  */
52843 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
52844 /*! @} */
52845 
52846 /*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */
52847 /*! @{ */
52848 
52849 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
52850 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U)
52851 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52852  */
52853 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK)
52854 
52855 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
52856 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U)
52857 /*! CNT_MODE - Count mode
52858  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52859  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52860  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52861  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52862  */
52863 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK)
52864 
52865 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
52866 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
52867 /*! DISABLE - Disable this step
52868  */
52869 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
52870 /*! @} */
52871 
52872 /*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */
52873 /*! @{ */
52874 
52875 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
52876 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U)
52877 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52878  */
52879 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK)
52880 
52881 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
52882 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U)
52883 /*! CNT_MODE - Count mode
52884  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52885  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52886  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52887  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52888  */
52889 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK)
52890 
52891 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
52892 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
52893 /*! DISABLE - Disable this step
52894  */
52895 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
52896 /*! @} */
52897 
52898 /*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */
52899 /*! @{ */
52900 
52901 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
52902 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U)
52903 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52904  */
52905 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK)
52906 
52907 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
52908 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U)
52909 /*! CNT_MODE - Count mode
52910  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52911  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52912  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52913  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52914  */
52915 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK)
52916 
52917 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
52918 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
52919 /*! DISABLE - Disable this step
52920  */
52921 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
52922 /*! @} */
52923 
52924 /*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */
52925 /*! @{ */
52926 
52927 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
52928 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U)
52929 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52930  */
52931 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK)
52932 
52933 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
52934 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U)
52935 /*! CNT_MODE - Count mode
52936  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52937  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52938  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52939  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52940  */
52941 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK)
52942 
52943 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
52944 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
52945 /*! DISABLE - Disable this step
52946  */
52947 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
52948 /*! @} */
52949 
52950 /*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */
52951 /*! @{ */
52952 
52953 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
52954 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U)
52955 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52956  */
52957 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK)
52958 
52959 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
52960 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U)
52961 /*! CNT_MODE - Count mode
52962  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52963  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52964  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52965  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52966  */
52967 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK)
52968 
52969 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
52970 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
52971 /*! DISABLE - Disable this step
52972  */
52973 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
52974 /*! @} */
52975 
52976 /*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */
52977 /*! @{ */
52978 
52979 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
52980 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
52981 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
52982  */
52983 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK)
52984 
52985 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
52986 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
52987 /*! CNT_MODE - Count mode
52988  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52989  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52990  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52991  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52992  */
52993 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK)
52994 
52995 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
52996 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
52997 /*! DISABLE - Disable this step
52998  */
52999 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
53000 /*! @} */
53001 
53002 /*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */
53003 /*! @{ */
53004 
53005 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
53006 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
53007 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53008  */
53009 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK)
53010 
53011 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
53012 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
53013 /*! CNT_MODE - Count mode
53014  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53015  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53016  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53017  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53018  */
53019 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK)
53020 
53021 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
53022 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
53023 /*! DISABLE - Disable this step
53024  */
53025 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
53026 /*! @} */
53027 
53028 /*! @name CM_SP_CTRL - CM Setpoint Control */
53029 /*! @{ */
53030 
53031 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U)
53032 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U)
53033 /*! CPU_SP_RUN_EN - Request a Setpoint transition when this bit is set
53034  */
53035 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK)
53036 
53037 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU)
53038 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U)
53039 /*! CPU_SP_RUN - The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set
53040  */
53041 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK)
53042 
53043 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U)
53044 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U)
53045 /*! CPU_SP_SLEEP_EN - 1 means enable Setpoint transition on next CPU platform sleep sequence
53046  */
53047 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK)
53048 
53049 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U)
53050 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U)
53051 /*! CPU_SP_SLEEP - The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence
53052  */
53053 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK)
53054 
53055 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U)
53056 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U)
53057 /*! CPU_SP_WAKEUP_EN - 1 means enable Setpoint transition on next CPU platform wakeup sequence
53058  */
53059 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK)
53060 
53061 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U)
53062 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U)
53063 /*! CPU_SP_WAKEUP - The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence
53064  */
53065 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK)
53066 
53067 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U)
53068 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U)
53069 /*! CPU_SP_WAKEUP_SEL - Select the Setpoint transiton on the next CPU platform wakeup sequence
53070  *  0b0..Request SP transition to CPU_SP_WAKEUP
53071  *  0b1..Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS
53072  */
53073 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK)
53074 /*! @} */
53075 
53076 /*! @name CM_SP_STAT - CM Setpoint Status */
53077 /*! @{ */
53078 
53079 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU)
53080 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U)
53081 /*! CPU_SP_CURRENT - The current Setpoint of the system
53082  */
53083 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK)
53084 
53085 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U)
53086 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U)
53087 /*! CPU_SP_PREVIOUS - The previous Setpoint of the system
53088  */
53089 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK)
53090 
53091 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U)
53092 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U)
53093 /*! CPU_SP_TARGET - The requested Setpoint from the CPU platform
53094  */
53095 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK)
53096 /*! @} */
53097 
53098 /*! @name CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed */
53099 /*! @{ */
53100 
53101 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU)
53102 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U)
53103 /*! CPU_RUN_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field
53104  */
53105 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK)
53106 /*! @} */
53107 
53108 /*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed */
53109 /*! @{ */
53110 
53111 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU)
53112 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U)
53113 /*! CPU_WAIT_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
53114  */
53115 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK)
53116 /*! @} */
53117 
53118 /*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed */
53119 /*! @{ */
53120 
53121 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU)
53122 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U)
53123 /*! CPU_STOP_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
53124  */
53125 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK)
53126 /*! @} */
53127 
53128 /*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed */
53129 /*! @{ */
53130 
53131 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU)
53132 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U)
53133 /*! CPU_SUSPEND_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
53134  */
53135 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK)
53136 /*! @} */
53137 
53138 /*! @name CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping */
53139 /*! @{ */
53140 
53141 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU)
53142 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U)
53143 /*! CPU_SP0_MAPPING - Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53144  */
53145 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK)
53146 
53147 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU)
53148 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U)
53149 /*! CPU_SP1_MAPPING - Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53150  */
53151 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK)
53152 
53153 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU)
53154 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U)
53155 /*! CPU_SP2_MAPPING - Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53156  */
53157 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK)
53158 
53159 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU)
53160 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U)
53161 /*! CPU_SP3_MAPPING - Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53162  */
53163 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK)
53164 
53165 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU)
53166 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U)
53167 /*! CPU_SP4_MAPPING - Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53168  */
53169 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK)
53170 
53171 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU)
53172 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U)
53173 /*! CPU_SP5_MAPPING - Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53174  */
53175 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK)
53176 
53177 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU)
53178 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U)
53179 /*! CPU_SP6_MAPPING - Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53180  */
53181 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK)
53182 
53183 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU)
53184 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U)
53185 /*! CPU_SP7_MAPPING - Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53186  */
53187 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK)
53188 
53189 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU)
53190 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U)
53191 /*! CPU_SP8_MAPPING - Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53192  */
53193 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK)
53194 
53195 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU)
53196 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U)
53197 /*! CPU_SP9_MAPPING - Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53198  */
53199 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK)
53200 
53201 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU)
53202 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U)
53203 /*! CPU_SP10_MAPPING - Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53204  */
53205 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK)
53206 
53207 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU)
53208 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U)
53209 /*! CPU_SP11_MAPPING - Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53210  */
53211 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK)
53212 
53213 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU)
53214 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U)
53215 /*! CPU_SP12_MAPPING - Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53216  */
53217 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK)
53218 
53219 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU)
53220 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U)
53221 /*! CPU_SP13_MAPPING - Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53222  */
53223 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK)
53224 
53225 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU)
53226 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U)
53227 /*! CPU_SP14_MAPPING - Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53228  */
53229 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK)
53230 
53231 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU)
53232 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U)
53233 /*! CPU_SP15_MAPPING - Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
53234  */
53235 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK)
53236 /*! @} */
53237 
53238 /* The count of GPC_CPU_MODE_CTRL_CM_SP_MAPPING */
53239 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT    (16U)
53240 
53241 /*! @name CM_STBY_CTRL - CM standby control */
53242 /*! @{ */
53243 
53244 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U)
53245 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U)
53246 /*! STBY_WAIT - 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field.
53247  */
53248 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK)
53249 
53250 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U)
53251 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U)
53252 /*! STBY_STOP - 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field.
53253  */
53254 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK)
53255 
53256 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U)
53257 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U)
53258 /*! STBY_SUSPEND - 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field.
53259  */
53260 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK)
53261 
53262 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U)
53263 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U)
53264 /*! STBY_SLEEP_BUSY - Indicate the CPU is busy entering standby mode.
53265  */
53266 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK)
53267 
53268 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U)
53269 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U)
53270 /*! STBY_WAKEUP_BUSY - Indicate the CPU is busy exiting standby mode.
53271  */
53272 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK)
53273 /*! @} */
53274 
53275 
53276 /*!
53277  * @}
53278  */ /* end of group GPC_CPU_MODE_CTRL_Register_Masks */
53279 
53280 
53281 /* GPC_CPU_MODE_CTRL - Peripheral instance base addresses */
53282 /** Peripheral GPC_CPU_MODE_CTRL_0 base address */
53283 #define GPC_CPU_MODE_CTRL_0_BASE                 (0x40C00000u)
53284 /** Peripheral GPC_CPU_MODE_CTRL_0 base pointer */
53285 #define GPC_CPU_MODE_CTRL_0                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
53286 /** Peripheral GPC_CPU_MODE_CTRL_1 base address */
53287 #define GPC_CPU_MODE_CTRL_1_BASE                 (0x40C00800u)
53288 /** Peripheral GPC_CPU_MODE_CTRL_1 base pointer */
53289 #define GPC_CPU_MODE_CTRL_1                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
53290 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses */
53291 #define GPC_CPU_MODE_CTRL_BASE_ADDRS             { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
53292 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers */
53293 #define GPC_CPU_MODE_CTRL_BASE_PTRS              { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
53294 
53295 /*!
53296  * @}
53297  */ /* end of group GPC_CPU_MODE_CTRL_Peripheral_Access_Layer */
53298 
53299 
53300 /* ----------------------------------------------------------------------------
53301    -- GPC_SET_POINT_CTRL Peripheral Access Layer
53302    ---------------------------------------------------------------------------- */
53303 
53304 /*!
53305  * @addtogroup GPC_SET_POINT_CTRL_Peripheral_Access_Layer GPC_SET_POINT_CTRL Peripheral Access Layer
53306  * @{
53307  */
53308 
53309 /** GPC_SET_POINT_CTRL - Register Layout Typedef */
53310 typedef struct {
53311        uint8_t RESERVED_0[4];
53312   __IO uint32_t SP_AUTHEN_CTRL;                    /**< SP Authentication Control, offset: 0x4 */
53313   __IO uint32_t SP_INT_CTRL;                       /**< SP Interrupt Control, offset: 0x8 */
53314        uint8_t RESERVED_1[4];
53315   __I  uint32_t SP_CPU_REQ;                        /**< CPU SP Request, offset: 0x10 */
53316   __I  uint32_t SP_SYS_STAT;                       /**< SP System Status, offset: 0x14 */
53317        uint8_t RESERVED_2[4];
53318   __IO uint32_t SP_ROSC_CTRL;                      /**< SP ROSC Control, offset: 0x1C */
53319        uint8_t RESERVED_3[32];
53320   __IO uint32_t SP_PRIORITY_0_7;                   /**< SP0~7 Priority, offset: 0x40 */
53321   __IO uint32_t SP_PRIORITY_8_15;                  /**< SP8~15 Priority, offset: 0x44 */
53322        uint8_t RESERVED_4[184];
53323   __IO uint32_t SP_SSAR_SAVE_CTRL;                 /**< SP SSAR save control, offset: 0x100 */
53324        uint8_t RESERVED_5[12];
53325   __IO uint32_t SP_LPCG_OFF_CTRL;                  /**< SP LPCG off control, offset: 0x110 */
53326        uint8_t RESERVED_6[12];
53327   __IO uint32_t SP_GROUP_DOWN_CTRL;                /**< SP group down control, offset: 0x120 */
53328        uint8_t RESERVED_7[12];
53329   __IO uint32_t SP_ROOT_DOWN_CTRL;                 /**< SP root down control, offset: 0x130 */
53330        uint8_t RESERVED_8[12];
53331   __IO uint32_t SP_PLL_OFF_CTRL;                   /**< SP PLL off control, offset: 0x140 */
53332        uint8_t RESERVED_9[12];
53333   __IO uint32_t SP_ISO_ON_CTRL;                    /**< SP ISO on control, offset: 0x150 */
53334        uint8_t RESERVED_10[12];
53335   __IO uint32_t SP_RESET_EARLY_CTRL;               /**< SP reset early control, offset: 0x160 */
53336        uint8_t RESERVED_11[12];
53337   __IO uint32_t SP_POWER_OFF_CTRL;                 /**< SP power off control, offset: 0x170 */
53338        uint8_t RESERVED_12[12];
53339   __IO uint32_t SP_BIAS_OFF_CTRL;                  /**< SP bias off control, offset: 0x180 */
53340        uint8_t RESERVED_13[12];
53341   __IO uint32_t SP_BG_PLDO_OFF_CTRL;               /**< SP bandgap and PLL_LDO off control, offset: 0x190 */
53342        uint8_t RESERVED_14[12];
53343   __IO uint32_t SP_LDO_PRE_CTRL;                   /**< SP LDO pre control, offset: 0x1A0 */
53344        uint8_t RESERVED_15[12];
53345   __IO uint32_t SP_DCDC_DOWN_CTRL;                 /**< SP DCDC down control, offset: 0x1B0 */
53346        uint8_t RESERVED_16[76];
53347   __IO uint32_t SP_DCDC_UP_CTRL;                   /**< SP DCDC up control, offset: 0x200 */
53348        uint8_t RESERVED_17[12];
53349   __IO uint32_t SP_LDO_POST_CTRL;                  /**< SP LDO post control, offset: 0x210 */
53350        uint8_t RESERVED_18[12];
53351   __IO uint32_t SP_BG_PLDO_ON_CTRL;                /**< SP bandgap and PLL_LDO on control, offset: 0x220 */
53352        uint8_t RESERVED_19[12];
53353   __IO uint32_t SP_BIAS_ON_CTRL;                   /**< SP bias on control, offset: 0x230 */
53354        uint8_t RESERVED_20[12];
53355   __IO uint32_t SP_POWER_ON_CTRL;                  /**< SP power on control, offset: 0x240 */
53356        uint8_t RESERVED_21[12];
53357   __IO uint32_t SP_RESET_LATE_CTRL;                /**< SP reset late control, offset: 0x250 */
53358        uint8_t RESERVED_22[12];
53359   __IO uint32_t SP_ISO_OFF_CTRL;                   /**< SP ISO off control, offset: 0x260 */
53360        uint8_t RESERVED_23[12];
53361   __IO uint32_t SP_PLL_ON_CTRL;                    /**< SP PLL on control, offset: 0x270 */
53362        uint8_t RESERVED_24[12];
53363   __IO uint32_t SP_ROOT_UP_CTRL;                   /**< SP root up control, offset: 0x280 */
53364        uint8_t RESERVED_25[12];
53365   __IO uint32_t SP_GROUP_UP_CTRL;                  /**< SP group up control, offset: 0x290 */
53366        uint8_t RESERVED_26[12];
53367   __IO uint32_t SP_LPCG_ON_CTRL;                   /**< SP LPCG on control, offset: 0x2A0 */
53368        uint8_t RESERVED_27[12];
53369   __IO uint32_t SP_SSAR_RESTORE_CTRL;              /**< SP SSAR restore control, offset: 0x2B0 */
53370 } GPC_SET_POINT_CTRL_Type;
53371 
53372 /* ----------------------------------------------------------------------------
53373    -- GPC_SET_POINT_CTRL Register Masks
53374    ---------------------------------------------------------------------------- */
53375 
53376 /*!
53377  * @addtogroup GPC_SET_POINT_CTRL_Register_Masks GPC_SET_POINT_CTRL Register Masks
53378  * @{
53379  */
53380 
53381 /*! @name SP_AUTHEN_CTRL - SP Authentication Control */
53382 /*! @{ */
53383 
53384 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U)
53385 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U)
53386 /*! USER - Allow user mode access
53387  *  0b0..Allow only privilege mode to access setpoint control registers
53388  *  0b1..Allow both privilege and user mode to access setpoint control registers
53389  */
53390 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK)
53391 
53392 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
53393 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
53394 /*! NONSECURE - Allow non-secure mode access
53395  *  0b0..Allow only secure mode to access setpoint control registers
53396  *  0b1..Allow both secure and non-secure mode to access setpoint control registers
53397  */
53398 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK)
53399 
53400 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
53401 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
53402 /*! LOCK_SETTING - Lock NONSECURE and USER
53403  */
53404 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK)
53405 
53406 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
53407 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
53408 /*! WHITE_LIST - Domain ID white list
53409  */
53410 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK)
53411 
53412 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
53413 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
53414 /*! LOCK_LIST - White list lock
53415  */
53416 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK)
53417 
53418 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
53419 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
53420 /*! LOCK_CFG - Configuration lock
53421  */
53422 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK)
53423 /*! @} */
53424 
53425 /*! @name SP_INT_CTRL - SP Interrupt Control */
53426 /*! @{ */
53427 
53428 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U)
53429 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U)
53430 /*! NO_ALLOWED_SP_INT_EN - no_allowed_set_point interrupt enable
53431  */
53432 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK)
53433 
53434 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U)
53435 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U)
53436 /*! NO_ALLOWED_SP_INT - no_allowed_set_point interrupt
53437  */
53438 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK)
53439 /*! @} */
53440 
53441 /*! @name SP_CPU_REQ - CPU SP Request */
53442 /*! @{ */
53443 
53444 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU)
53445 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U)
53446 /*! SP_REQ_CPU0 - Setpoint requested by CPU0
53447  */
53448 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK)
53449 
53450 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U)
53451 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U)
53452 /*! SP_REQ_CPU1 - Setpoint requested by CPU1
53453  */
53454 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK)
53455 
53456 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U)
53457 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U)
53458 /*! SP_REQ_CPU2 - Setpoint requested by CPU2
53459  */
53460 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK)
53461 
53462 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U)
53463 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U)
53464 /*! SP_REQ_CPU3 - Setpoint requested by CPU3
53465  */
53466 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK)
53467 
53468 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U)
53469 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U)
53470 /*! SP_ACCEPTED_CPU0 - CPU0 Setpoint accepted by SP controller
53471  */
53472 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK)
53473 
53474 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U)
53475 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U)
53476 /*! SP_ACCEPTED_CPU1 - CPU1 Setpoint accepted by SP controller
53477  */
53478 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK)
53479 
53480 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U)
53481 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U)
53482 /*! SP_ACCEPTED_CPU2 - CPU2 Setpoint accepted by SP controller
53483  */
53484 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK)
53485 
53486 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U)
53487 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U)
53488 /*! SP_ACCEPTED_CPU3 - CPU3 Setpoint accepted by SP controller
53489  */
53490 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK)
53491 /*! @} */
53492 
53493 /*! @name SP_SYS_STAT - SP System Status */
53494 /*! @{ */
53495 
53496 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU)
53497 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U)
53498 /*! SYS_SP_ALLOWED - Allowed Setpoints by all current CPU Setpoint requests
53499  */
53500 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK)
53501 
53502 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U)
53503 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U)
53504 /*! SYS_SP_TARGET - The Setpoint chosen as the target setpoint
53505  */
53506 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK)
53507 
53508 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U)
53509 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U)
53510 /*! SYS_SP_CURRENT - Current Setpoint, only valid when not SP trans busy
53511  */
53512 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK)
53513 
53514 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U)
53515 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U)
53516 /*! SYS_SP_PREVIOUS - Previous Setpoint, only valid when not SP trans busy
53517  */
53518 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK)
53519 /*! @} */
53520 
53521 /*! @name SP_ROSC_CTRL - SP ROSC Control */
53522 /*! @{ */
53523 
53524 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU)
53525 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U)
53526 /*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC
53527  */
53528 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK)
53529 /*! @} */
53530 
53531 /*! @name SP_PRIORITY_0_7 - SP0~7 Priority */
53532 /*! @{ */
53533 
53534 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU)
53535 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U)
53536 /*! SYS_SP0_PRIORITY - priority of Setpoint 0
53537  */
53538 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK)
53539 
53540 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U)
53541 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U)
53542 /*! SYS_SP1_PRIORITY - priority of Setpoint 1
53543  */
53544 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK)
53545 
53546 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U)
53547 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U)
53548 /*! SYS_SP2_PRIORITY - priority of Setpoint 2
53549  */
53550 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK)
53551 
53552 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U)
53553 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U)
53554 /*! SYS_SP3_PRIORITY - priority of Setpoint 3
53555  */
53556 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK)
53557 
53558 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U)
53559 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U)
53560 /*! SYS_SP4_PRIORITY - priority of Setpoint 4
53561  */
53562 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK)
53563 
53564 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U)
53565 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U)
53566 /*! SYS_SP5_PRIORITY - priority of Setpoint 5
53567  */
53568 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK)
53569 
53570 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U)
53571 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U)
53572 /*! SYS_SP6_PRIORITY - priority of Setpoint 6
53573  */
53574 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK)
53575 
53576 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U)
53577 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U)
53578 /*! SYS_SP7_PRIORITY - priority of Setpoint 7
53579  */
53580 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK)
53581 /*! @} */
53582 
53583 /*! @name SP_PRIORITY_8_15 - SP8~15 Priority */
53584 /*! @{ */
53585 
53586 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU)
53587 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U)
53588 /*! SYS_SP8_PRIORITY - priority of Setpoint 8
53589  */
53590 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK)
53591 
53592 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U)
53593 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U)
53594 /*! SYS_SP9_PRIORITY - priority of Setpoint 9
53595  */
53596 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK)
53597 
53598 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U)
53599 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U)
53600 /*! SYS_SP10_PRIORITY - priority of Setpoint 10
53601  */
53602 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK)
53603 
53604 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U)
53605 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U)
53606 /*! SYS_SP11_PRIORITY - priority of Setpoint 11
53607  */
53608 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK)
53609 
53610 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U)
53611 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U)
53612 /*! SYS_SP12_PRIORITY - priority of Setpoint 12
53613  */
53614 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK)
53615 
53616 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U)
53617 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U)
53618 /*! SYS_SP13_PRIORITY - priority of Setpoint 13
53619  */
53620 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK)
53621 
53622 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U)
53623 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U)
53624 /*! SYS_SP14_PRIORITY - priority of Setpoint 14
53625  */
53626 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK)
53627 
53628 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U)
53629 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U)
53630 /*! SYS_SP15_PRIORITY - priority of Setpoint 15
53631  */
53632 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK)
53633 /*! @} */
53634 
53635 /*! @name SP_SSAR_SAVE_CTRL - SP SSAR save control */
53636 /*! @{ */
53637 
53638 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU)
53639 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U)
53640 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53641  */
53642 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK)
53643 
53644 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U)
53645 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U)
53646 /*! CNT_MODE - Count mode
53647  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53648  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53649  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53650  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53651  */
53652 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK)
53653 
53654 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U)
53655 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U)
53656 /*! DISABLE - Disable this step
53657  */
53658 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK)
53659 /*! @} */
53660 
53661 /*! @name SP_LPCG_OFF_CTRL - SP LPCG off control */
53662 /*! @{ */
53663 
53664 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53665 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U)
53666 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53667  */
53668 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK)
53669 
53670 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53671 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U)
53672 /*! CNT_MODE - Count mode
53673  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53674  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53675  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53676  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53677  */
53678 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK)
53679 
53680 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U)
53681 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U)
53682 /*! DISABLE - Disable this step
53683  */
53684 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK)
53685 /*! @} */
53686 
53687 /*! @name SP_GROUP_DOWN_CTRL - SP group down control */
53688 /*! @{ */
53689 
53690 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53691 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53692 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53693  */
53694 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK)
53695 
53696 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53697 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53698 /*! CNT_MODE - Count mode
53699  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53700  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53701  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53702  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53703  */
53704 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK)
53705 
53706 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53707 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U)
53708 /*! DISABLE - Disable this step
53709  */
53710 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK)
53711 /*! @} */
53712 
53713 /*! @name SP_ROOT_DOWN_CTRL - SP root down control */
53714 /*! @{ */
53715 
53716 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53717 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53718 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53719  */
53720 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK)
53721 
53722 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53723 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53724 /*! CNT_MODE - Count mode
53725  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53726  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53727  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53728  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53729  */
53730 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK)
53731 
53732 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53733 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U)
53734 /*! DISABLE - Disable this step
53735  */
53736 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK)
53737 /*! @} */
53738 
53739 /*! @name SP_PLL_OFF_CTRL - SP PLL off control */
53740 /*! @{ */
53741 
53742 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53743 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U)
53744 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53745  */
53746 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK)
53747 
53748 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53749 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U)
53750 /*! CNT_MODE - Count mode
53751  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53752  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53753  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53754  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53755  */
53756 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK)
53757 
53758 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U)
53759 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U)
53760 /*! DISABLE - Disable this step
53761  */
53762 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK)
53763 /*! @} */
53764 
53765 /*! @name SP_ISO_ON_CTRL - SP ISO on control */
53766 /*! @{ */
53767 
53768 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
53769 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U)
53770 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53771  */
53772 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK)
53773 
53774 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
53775 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U)
53776 /*! CNT_MODE - Count mode
53777  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53778  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53779  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53780  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53781  */
53782 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK)
53783 
53784 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U)
53785 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U)
53786 /*! DISABLE - Disable this step
53787  */
53788 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK)
53789 /*! @} */
53790 
53791 /*! @name SP_RESET_EARLY_CTRL - SP reset early control */
53792 /*! @{ */
53793 
53794 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU)
53795 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U)
53796 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53797  */
53798 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK)
53799 
53800 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U)
53801 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U)
53802 /*! CNT_MODE - Count mode
53803  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53804  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53805  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53806  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53807  */
53808 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK)
53809 
53810 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U)
53811 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U)
53812 /*! DISABLE - Disable this step
53813  */
53814 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK)
53815 /*! @} */
53816 
53817 /*! @name SP_POWER_OFF_CTRL - SP power off control */
53818 /*! @{ */
53819 
53820 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53821 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U)
53822 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53823  */
53824 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK)
53825 
53826 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53827 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U)
53828 /*! CNT_MODE - Count mode
53829  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53830  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53831  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53832  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53833  */
53834 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK)
53835 
53836 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U)
53837 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U)
53838 /*! DISABLE - Disable this step
53839  */
53840 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK)
53841 /*! @} */
53842 
53843 /*! @name SP_BIAS_OFF_CTRL - SP bias off control */
53844 /*! @{ */
53845 
53846 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53847 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U)
53848 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53849  */
53850 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK)
53851 
53852 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53853 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U)
53854 /*! CNT_MODE - Count mode
53855  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53856  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53857  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53858  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53859  */
53860 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK)
53861 
53862 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U)
53863 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U)
53864 /*! DISABLE - Disable this step
53865  */
53866 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK)
53867 /*! @} */
53868 
53869 /*! @name SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control */
53870 /*! @{ */
53871 
53872 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
53873 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U)
53874 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53875  */
53876 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK)
53877 
53878 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
53879 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U)
53880 /*! CNT_MODE - Count mode
53881  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53882  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53883  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53884  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53885  */
53886 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK)
53887 
53888 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U)
53889 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U)
53890 /*! DISABLE - Disable this step
53891  */
53892 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK)
53893 /*! @} */
53894 
53895 /*! @name SP_LDO_PRE_CTRL - SP LDO pre control */
53896 /*! @{ */
53897 
53898 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU)
53899 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U)
53900 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53901  */
53902 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK)
53903 
53904 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U)
53905 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U)
53906 /*! CNT_MODE - Count mode
53907  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53908  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53909  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53910  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53911  */
53912 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK)
53913 
53914 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U)
53915 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U)
53916 /*! DISABLE - Disable this step
53917  */
53918 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK)
53919 /*! @} */
53920 
53921 /*! @name SP_DCDC_DOWN_CTRL - SP DCDC down control */
53922 /*! @{ */
53923 
53924 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
53925 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U)
53926 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53927  */
53928 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK)
53929 
53930 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
53931 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U)
53932 /*! CNT_MODE - Count mode
53933  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53934  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53935  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53936  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53937  */
53938 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK)
53939 
53940 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U)
53941 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U)
53942 /*! DISABLE - Disable this step
53943  */
53944 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK)
53945 /*! @} */
53946 
53947 /*! @name SP_DCDC_UP_CTRL - SP DCDC up control */
53948 /*! @{ */
53949 
53950 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
53951 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U)
53952 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53953  */
53954 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK)
53955 
53956 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U)
53957 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U)
53958 /*! CNT_MODE - Count mode
53959  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53960  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53961  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53962  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53963  */
53964 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK)
53965 
53966 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U)
53967 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U)
53968 /*! DISABLE - Disable this step
53969  */
53970 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK)
53971 /*! @} */
53972 
53973 /*! @name SP_LDO_POST_CTRL - SP LDO post control */
53974 /*! @{ */
53975 
53976 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU)
53977 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U)
53978 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
53979  */
53980 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK)
53981 
53982 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U)
53983 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U)
53984 /*! CNT_MODE - Count mode
53985  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53986  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53987  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53988  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53989  */
53990 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK)
53991 
53992 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U)
53993 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U)
53994 /*! DISABLE - Disable this step
53995  */
53996 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK)
53997 /*! @} */
53998 
53999 /*! @name SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control */
54000 /*! @{ */
54001 
54002 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
54003 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U)
54004 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54005  */
54006 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK)
54007 
54008 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
54009 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U)
54010 /*! CNT_MODE - Count mode
54011  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54012  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54013  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54014  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54015  */
54016 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK)
54017 
54018 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U)
54019 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U)
54020 /*! DISABLE - Disable this step
54021  */
54022 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK)
54023 /*! @} */
54024 
54025 /*! @name SP_BIAS_ON_CTRL - SP bias on control */
54026 /*! @{ */
54027 
54028 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
54029 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U)
54030 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54031  */
54032 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK)
54033 
54034 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U)
54035 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U)
54036 /*! CNT_MODE - Count mode
54037  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54038  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54039  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54040  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54041  */
54042 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK)
54043 
54044 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U)
54045 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U)
54046 /*! DISABLE - Disable this step
54047  */
54048 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK)
54049 /*! @} */
54050 
54051 /*! @name SP_POWER_ON_CTRL - SP power on control */
54052 /*! @{ */
54053 
54054 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
54055 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U)
54056 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54057  */
54058 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK)
54059 
54060 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U)
54061 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U)
54062 /*! CNT_MODE - Count mode
54063  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54064  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54065  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54066  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54067  */
54068 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK)
54069 
54070 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U)
54071 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U)
54072 /*! DISABLE - Disable this step
54073  */
54074 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK)
54075 /*! @} */
54076 
54077 /*! @name SP_RESET_LATE_CTRL - SP reset late control */
54078 /*! @{ */
54079 
54080 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU)
54081 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U)
54082 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54083  */
54084 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK)
54085 
54086 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U)
54087 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U)
54088 /*! CNT_MODE - Count mode
54089  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54090  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54091  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54092  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54093  */
54094 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK)
54095 
54096 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U)
54097 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U)
54098 /*! DISABLE - Disable this step
54099  */
54100 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK)
54101 /*! @} */
54102 
54103 /*! @name SP_ISO_OFF_CTRL - SP ISO off control */
54104 /*! @{ */
54105 
54106 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
54107 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U)
54108 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54109  */
54110 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK)
54111 
54112 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
54113 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U)
54114 /*! CNT_MODE - Count mode
54115  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54116  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54117  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54118  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54119  */
54120 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK)
54121 
54122 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U)
54123 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U)
54124 /*! DISABLE - Disable this step
54125  */
54126 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK)
54127 /*! @} */
54128 
54129 /*! @name SP_PLL_ON_CTRL - SP PLL on control */
54130 /*! @{ */
54131 
54132 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
54133 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U)
54134 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54135  */
54136 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK)
54137 
54138 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U)
54139 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U)
54140 /*! CNT_MODE - Count mode
54141  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54142  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54143  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54144  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54145  */
54146 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK)
54147 
54148 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U)
54149 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U)
54150 /*! DISABLE - Disable this step
54151  */
54152 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK)
54153 /*! @} */
54154 
54155 /*! @name SP_ROOT_UP_CTRL - SP root up control */
54156 /*! @{ */
54157 
54158 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
54159 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U)
54160 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54161  */
54162 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK)
54163 
54164 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U)
54165 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U)
54166 /*! CNT_MODE - Count mode
54167  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54168  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54169  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54170  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54171  */
54172 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK)
54173 
54174 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U)
54175 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U)
54176 /*! DISABLE - Disable this step
54177  */
54178 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK)
54179 /*! @} */
54180 
54181 /*! @name SP_GROUP_UP_CTRL - SP group up control */
54182 /*! @{ */
54183 
54184 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
54185 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U)
54186 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54187  */
54188 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK)
54189 
54190 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U)
54191 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U)
54192 /*! CNT_MODE - Count mode
54193  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54194  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54195  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54196  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54197  */
54198 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK)
54199 
54200 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U)
54201 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U)
54202 /*! DISABLE - Disable this step
54203  */
54204 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK)
54205 /*! @} */
54206 
54207 /*! @name SP_LPCG_ON_CTRL - SP LPCG on control */
54208 /*! @{ */
54209 
54210 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
54211 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U)
54212 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54213  */
54214 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK)
54215 
54216 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U)
54217 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U)
54218 /*! CNT_MODE - Count mode
54219  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54220  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54221  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54222  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54223  */
54224 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK)
54225 
54226 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U)
54227 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U)
54228 /*! DISABLE - Disable this step
54229  */
54230 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK)
54231 /*! @} */
54232 
54233 /*! @name SP_SSAR_RESTORE_CTRL - SP SSAR restore control */
54234 /*! @{ */
54235 
54236 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU)
54237 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U)
54238 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54239  */
54240 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK)
54241 
54242 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U)
54243 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U)
54244 /*! CNT_MODE - Count mode
54245  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54246  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54247  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54248  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54249  */
54250 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK)
54251 
54252 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U)
54253 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U)
54254 /*! DISABLE - Disable this step
54255  */
54256 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK)
54257 /*! @} */
54258 
54259 
54260 /*!
54261  * @}
54262  */ /* end of group GPC_SET_POINT_CTRL_Register_Masks */
54263 
54264 
54265 /* GPC_SET_POINT_CTRL - Peripheral instance base addresses */
54266 /** Peripheral GPC_SET_POINT_CTRL base address */
54267 #define GPC_SET_POINT_CTRL_BASE                  (0x40C02000u)
54268 /** Peripheral GPC_SET_POINT_CTRL base pointer */
54269 #define GPC_SET_POINT_CTRL                       ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
54270 /** Array initializer of GPC_SET_POINT_CTRL peripheral base addresses */
54271 #define GPC_SET_POINT_CTRL_BASE_ADDRS            { GPC_SET_POINT_CTRL_BASE }
54272 /** Array initializer of GPC_SET_POINT_CTRL peripheral base pointers */
54273 #define GPC_SET_POINT_CTRL_BASE_PTRS             { GPC_SET_POINT_CTRL }
54274 
54275 /*!
54276  * @}
54277  */ /* end of group GPC_SET_POINT_CTRL_Peripheral_Access_Layer */
54278 
54279 
54280 /* ----------------------------------------------------------------------------
54281    -- GPC_STBY_CTRL Peripheral Access Layer
54282    ---------------------------------------------------------------------------- */
54283 
54284 /*!
54285  * @addtogroup GPC_STBY_CTRL_Peripheral_Access_Layer GPC_STBY_CTRL Peripheral Access Layer
54286  * @{
54287  */
54288 
54289 /** GPC_STBY_CTRL - Register Layout Typedef */
54290 typedef struct {
54291        uint8_t RESERVED_0[4];
54292   __IO uint32_t STBY_AUTHEN_CTRL;                  /**< Standby Authentication Control, offset: 0x4 */
54293        uint8_t RESERVED_1[4];
54294   __IO uint32_t STBY_MISC;                         /**< STBY Misc, offset: 0xC */
54295        uint8_t RESERVED_2[224];
54296   __IO uint32_t STBY_LPCG_IN_CTRL;                 /**< STBY lpcg_in control, offset: 0xF0 */
54297        uint8_t RESERVED_3[12];
54298   __IO uint32_t STBY_PLL_IN_CTRL;                  /**< STBY pll_in control, offset: 0x100 */
54299        uint8_t RESERVED_4[12];
54300   __IO uint32_t STBY_BIAS_IN_CTRL;                 /**< STBY bias_in control, offset: 0x110 */
54301        uint8_t RESERVED_5[12];
54302   __IO uint32_t STBY_PLDO_IN_CTRL;                 /**< STBY pldo_in control, offset: 0x120 */
54303        uint8_t RESERVED_6[4];
54304   __IO uint32_t STBY_BANDGAP_IN_CTRL;              /**< STBY bandgap_in control, offset: 0x128 */
54305        uint8_t RESERVED_7[4];
54306   __IO uint32_t STBY_LDO_IN_CTRL;                  /**< STBY ldo_in control, offset: 0x130 */
54307        uint8_t RESERVED_8[12];
54308   __IO uint32_t STBY_DCDC_IN_CTRL;                 /**< STBY dcdc_in control, offset: 0x140 */
54309        uint8_t RESERVED_9[12];
54310   __IO uint32_t STBY_PMIC_IN_CTRL;                 /**< STBY PMIC in control, offset: 0x150 */
54311        uint8_t RESERVED_10[172];
54312   __IO uint32_t STBY_PMIC_OUT_CTRL;                /**< STBY PMIC out control, offset: 0x200 */
54313        uint8_t RESERVED_11[12];
54314   __IO uint32_t STBY_DCDC_OUT_CTRL;                /**< STBY DCDC out control, offset: 0x210 */
54315        uint8_t RESERVED_12[12];
54316   __IO uint32_t STBY_LDO_OUT_CTRL;                 /**< STBY LDO out control, offset: 0x220 */
54317        uint8_t RESERVED_13[12];
54318   __IO uint32_t STBY_BANDGAP_OUT_CTRL;             /**< STBY bandgap out control, offset: 0x230 */
54319        uint8_t RESERVED_14[4];
54320   __IO uint32_t STBY_PLDO_OUT_CTRL;                /**< STBY pldo out control, offset: 0x238 */
54321        uint8_t RESERVED_15[4];
54322   __IO uint32_t STBY_BIAS_OUT_CTRL;                /**< STBY bias out control, offset: 0x240 */
54323        uint8_t RESERVED_16[12];
54324   __IO uint32_t STBY_PLL_OUT_CTRL;                 /**< STBY PLL out control, offset: 0x250 */
54325        uint8_t RESERVED_17[12];
54326   __IO uint32_t STBY_LPCG_OUT_CTRL;                /**< STBY LPCG out control, offset: 0x260 */
54327 } GPC_STBY_CTRL_Type;
54328 
54329 /* ----------------------------------------------------------------------------
54330    -- GPC_STBY_CTRL Register Masks
54331    ---------------------------------------------------------------------------- */
54332 
54333 /*!
54334  * @addtogroup GPC_STBY_CTRL_Register_Masks GPC_STBY_CTRL Register Masks
54335  * @{
54336  */
54337 
54338 /*! @name STBY_AUTHEN_CTRL - Standby Authentication Control */
54339 /*! @{ */
54340 
54341 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
54342 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
54343 /*! LOCK_CFG - Configuration lock
54344  */
54345 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK)
54346 /*! @} */
54347 
54348 /*! @name STBY_MISC - STBY Misc */
54349 /*! @{ */
54350 
54351 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U)
54352 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U)
54353 /*! FORCE_CPU0_STBY - Force CPU0 requesting standby mode
54354  */
54355 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK)
54356 
54357 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U)
54358 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U)
54359 /*! FORCE_CPU1_STBY - Force CPU0 requesting standby mode
54360  */
54361 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK)
54362 
54363 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U)
54364 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U)
54365 /*! FORCE_CPU2_STBY - Force CPU2 requesting standby mode
54366  */
54367 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK)
54368 
54369 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U)
54370 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U)
54371 /*! FORCE_CPU3_STBY - Force CPU3 requesting standby mode
54372  */
54373 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK)
54374 /*! @} */
54375 
54376 /*! @name STBY_LPCG_IN_CTRL - STBY lpcg_in control */
54377 /*! @{ */
54378 
54379 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54380 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U)
54381 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54382  */
54383 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK)
54384 
54385 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54386 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U)
54387 /*! CNT_MODE - Count mode
54388  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54389  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54390  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54391  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54392  */
54393 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK)
54394 
54395 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U)
54396 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U)
54397 /*! DISABLE - Disable this step
54398  */
54399 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK)
54400 /*! @} */
54401 
54402 /*! @name STBY_PLL_IN_CTRL - STBY pll_in control */
54403 /*! @{ */
54404 
54405 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54406 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U)
54407 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54408  */
54409 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK)
54410 
54411 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54412 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U)
54413 /*! CNT_MODE - Count mode
54414  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54415  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54416  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54417  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54418  */
54419 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK)
54420 
54421 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U)
54422 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U)
54423 /*! DISABLE - Disable this step
54424  */
54425 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK)
54426 /*! @} */
54427 
54428 /*! @name STBY_BIAS_IN_CTRL - STBY bias_in control */
54429 /*! @{ */
54430 
54431 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54432 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U)
54433 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54434  */
54435 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK)
54436 
54437 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54438 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U)
54439 /*! CNT_MODE - Count mode
54440  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54441  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54442  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54443  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54444  */
54445 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK)
54446 
54447 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U)
54448 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U)
54449 /*! DISABLE - Disable this step
54450  */
54451 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK)
54452 /*! @} */
54453 
54454 /*! @name STBY_PLDO_IN_CTRL - STBY pldo_in control */
54455 /*! @{ */
54456 
54457 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54458 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U)
54459 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54460  */
54461 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK)
54462 
54463 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54464 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U)
54465 /*! CNT_MODE - Count mode
54466  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54467  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54468  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54469  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54470  */
54471 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK)
54472 
54473 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U)
54474 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U)
54475 /*! DISABLE - Disable this step
54476  */
54477 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK)
54478 /*! @} */
54479 
54480 /*! @name STBY_BANDGAP_IN_CTRL - STBY bandgap_in control */
54481 /*! @{ */
54482 
54483 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54484 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U)
54485 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54486  */
54487 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK)
54488 
54489 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54490 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U)
54491 /*! CNT_MODE - Count mode
54492  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54493  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54494  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54495  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54496  */
54497 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK)
54498 
54499 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U)
54500 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U)
54501 /*! DISABLE - Disable this step
54502  */
54503 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK)
54504 /*! @} */
54505 
54506 /*! @name STBY_LDO_IN_CTRL - STBY ldo_in control */
54507 /*! @{ */
54508 
54509 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54510 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U)
54511 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54512  */
54513 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK)
54514 
54515 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54516 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U)
54517 /*! CNT_MODE - Count mode
54518  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54519  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54520  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54521  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54522  */
54523 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK)
54524 
54525 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U)
54526 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U)
54527 /*! DISABLE - Disable this step
54528  */
54529 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK)
54530 /*! @} */
54531 
54532 /*! @name STBY_DCDC_IN_CTRL - STBY dcdc_in control */
54533 /*! @{ */
54534 
54535 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54536 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U)
54537 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54538  */
54539 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK)
54540 
54541 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54542 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U)
54543 /*! CNT_MODE - Count mode
54544  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54545  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54546  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54547  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54548  */
54549 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK)
54550 
54551 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
54552 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
54553 /*! DISABLE - Disable this step
54554  */
54555 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK)
54556 /*! @} */
54557 
54558 /*! @name STBY_PMIC_IN_CTRL - STBY PMIC in control */
54559 /*! @{ */
54560 
54561 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
54562 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U)
54563 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54564  */
54565 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK)
54566 
54567 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
54568 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U)
54569 /*! CNT_MODE - Count mode
54570  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54571  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54572  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54573  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54574  */
54575 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK)
54576 
54577 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
54578 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
54579 /*! DISABLE - Disable this step
54580  */
54581 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK)
54582 /*! @} */
54583 
54584 /*! @name STBY_PMIC_OUT_CTRL - STBY PMIC out control */
54585 /*! @{ */
54586 
54587 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54588 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U)
54589 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54590  */
54591 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK)
54592 
54593 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54594 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U)
54595 /*! CNT_MODE - Count mode
54596  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54597  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54598  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54599  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54600  */
54601 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK)
54602 
54603 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
54604 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
54605 /*! DISABLE - Disable this step
54606  */
54607 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK)
54608 /*! @} */
54609 
54610 /*! @name STBY_DCDC_OUT_CTRL - STBY DCDC out control */
54611 /*! @{ */
54612 
54613 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54614 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U)
54615 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54616  */
54617 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK)
54618 
54619 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54620 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U)
54621 /*! CNT_MODE - Count mode
54622  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54623  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54624  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54625  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54626  */
54627 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK)
54628 
54629 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
54630 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
54631 /*! DISABLE - Disable this step
54632  */
54633 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK)
54634 /*! @} */
54635 
54636 /*! @name STBY_LDO_OUT_CTRL - STBY LDO out control */
54637 /*! @{ */
54638 
54639 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54640 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
54641 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54642  */
54643 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK)
54644 
54645 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54646 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
54647 /*! CNT_MODE - Count mode
54648  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54649  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54650  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54651  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54652  */
54653 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK)
54654 
54655 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
54656 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U)
54657 /*! DISABLE - Disable this step
54658  */
54659 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK)
54660 /*! @} */
54661 
54662 /*! @name STBY_BANDGAP_OUT_CTRL - STBY bandgap out control */
54663 /*! @{ */
54664 
54665 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54666 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U)
54667 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54668  */
54669 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK)
54670 
54671 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54672 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U)
54673 /*! CNT_MODE - Count mode
54674  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54675  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54676  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54677  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54678  */
54679 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK)
54680 
54681 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U)
54682 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U)
54683 /*! DISABLE - Disable this step
54684  */
54685 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK)
54686 /*! @} */
54687 
54688 /*! @name STBY_PLDO_OUT_CTRL - STBY pldo out control */
54689 /*! @{ */
54690 
54691 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54692 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
54693 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54694  */
54695 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK)
54696 
54697 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54698 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
54699 /*! CNT_MODE - Count mode
54700  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54701  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54702  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54703  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54704  */
54705 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK)
54706 
54707 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
54708 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U)
54709 /*! DISABLE - Disable this step
54710  */
54711 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK)
54712 /*! @} */
54713 
54714 /*! @name STBY_BIAS_OUT_CTRL - STBY bias out control */
54715 /*! @{ */
54716 
54717 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54718 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U)
54719 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54720  */
54721 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK)
54722 
54723 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54724 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U)
54725 /*! CNT_MODE - Count mode
54726  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54727  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54728  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54729  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54730  */
54731 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK)
54732 
54733 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U)
54734 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U)
54735 /*! DISABLE - Disable this step
54736  */
54737 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK)
54738 /*! @} */
54739 
54740 /*! @name STBY_PLL_OUT_CTRL - STBY PLL out control */
54741 /*! @{ */
54742 
54743 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54744 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U)
54745 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54746  */
54747 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK)
54748 
54749 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54750 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U)
54751 /*! CNT_MODE - Count mode
54752  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54753  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54754  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54755  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54756  */
54757 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK)
54758 
54759 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U)
54760 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U)
54761 /*! DISABLE - Disable this step
54762  */
54763 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK)
54764 /*! @} */
54765 
54766 /*! @name STBY_LPCG_OUT_CTRL - STBY LPCG out control */
54767 /*! @{ */
54768 
54769 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
54770 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U)
54771 /*! STEP_CNT - Step count, useage is depending on CNT_MODE
54772  */
54773 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK)
54774 
54775 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
54776 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U)
54777 /*! CNT_MODE - Count mode
54778  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
54779  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
54780  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
54781  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
54782  */
54783 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK)
54784 
54785 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U)
54786 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U)
54787 /*! DISABLE - Disable this step
54788  */
54789 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK)
54790 /*! @} */
54791 
54792 
54793 /*!
54794  * @}
54795  */ /* end of group GPC_STBY_CTRL_Register_Masks */
54796 
54797 
54798 /* GPC_STBY_CTRL - Peripheral instance base addresses */
54799 /** Peripheral GPC_STBY_CTRL base address */
54800 #define GPC_STBY_CTRL_BASE                       (0x40C02800u)
54801 /** Peripheral GPC_STBY_CTRL base pointer */
54802 #define GPC_STBY_CTRL                            ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
54803 /** Array initializer of GPC_STBY_CTRL peripheral base addresses */
54804 #define GPC_STBY_CTRL_BASE_ADDRS                 { GPC_STBY_CTRL_BASE }
54805 /** Array initializer of GPC_STBY_CTRL peripheral base pointers */
54806 #define GPC_STBY_CTRL_BASE_PTRS                  { GPC_STBY_CTRL }
54807 
54808 /*!
54809  * @}
54810  */ /* end of group GPC_STBY_CTRL_Peripheral_Access_Layer */
54811 
54812 
54813 /* ----------------------------------------------------------------------------
54814    -- GPIO Peripheral Access Layer
54815    ---------------------------------------------------------------------------- */
54816 
54817 /*!
54818  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
54819  * @{
54820  */
54821 
54822 /** GPIO - Register Layout Typedef */
54823 typedef struct {
54824   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
54825   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
54826   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
54827   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
54828   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
54829   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
54830   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
54831   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
54832        uint8_t RESERVED_0[100];
54833   __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
54834   __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
54835   __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
54836 } GPIO_Type;
54837 
54838 /* ----------------------------------------------------------------------------
54839    -- GPIO Register Masks
54840    ---------------------------------------------------------------------------- */
54841 
54842 /*!
54843  * @addtogroup GPIO_Register_Masks GPIO Register Masks
54844  * @{
54845  */
54846 
54847 /*! @name DR - GPIO data register */
54848 /*! @{ */
54849 
54850 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
54851 #define GPIO_DR_DR_SHIFT                         (0U)
54852 /*! DR - DR data bits
54853  */
54854 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
54855 /*! @} */
54856 
54857 /*! @name GDIR - GPIO direction register */
54858 /*! @{ */
54859 
54860 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
54861 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
54862 /*! GDIR - GPIO direction bits
54863  */
54864 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
54865 /*! @} */
54866 
54867 /*! @name PSR - GPIO pad status register */
54868 /*! @{ */
54869 
54870 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
54871 #define GPIO_PSR_PSR_SHIFT                       (0U)
54872 /*! PSR - GPIO pad status bits
54873  */
54874 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
54875 /*! @} */
54876 
54877 /*! @name ICR1 - GPIO interrupt configuration register1 */
54878 /*! @{ */
54879 
54880 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
54881 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
54882 /*! ICR0 - Interrupt configuration field for GPIO interrupt 0
54883  *  0b00..Interrupt 0 is low-level sensitive.
54884  *  0b01..Interrupt 0 is high-level sensitive.
54885  *  0b10..Interrupt 0 is rising-edge sensitive.
54886  *  0b11..Interrupt 0 is falling-edge sensitive.
54887  */
54888 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
54889 
54890 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
54891 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
54892 /*! ICR1 - Interrupt configuration field for GPIO interrupt 1
54893  *  0b00..Interrupt 1 is low-level sensitive.
54894  *  0b01..Interrupt 1 is high-level sensitive.
54895  *  0b10..Interrupt 1 is rising-edge sensitive.
54896  *  0b11..Interrupt 1 is falling-edge sensitive.
54897  */
54898 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
54899 
54900 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
54901 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
54902 /*! ICR2 - Interrupt configuration field for GPIO interrupt 2
54903  *  0b00..Interrupt 2 is low-level sensitive.
54904  *  0b01..Interrupt 2 is high-level sensitive.
54905  *  0b10..Interrupt 2 is rising-edge sensitive.
54906  *  0b11..Interrupt 2 is falling-edge sensitive.
54907  */
54908 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
54909 
54910 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
54911 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
54912 /*! ICR3 - Interrupt configuration field for GPIO interrupt 3
54913  *  0b00..Interrupt 3 is low-level sensitive.
54914  *  0b01..Interrupt 3 is high-level sensitive.
54915  *  0b10..Interrupt 3 is rising-edge sensitive.
54916  *  0b11..Interrupt 3 is falling-edge sensitive.
54917  */
54918 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
54919 
54920 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
54921 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
54922 /*! ICR4 - Interrupt configuration field for GPIO interrupt 4
54923  *  0b00..Interrupt 4 is low-level sensitive.
54924  *  0b01..Interrupt 4 is high-level sensitive.
54925  *  0b10..Interrupt 4 is rising-edge sensitive.
54926  *  0b11..Interrupt 4 is falling-edge sensitive.
54927  */
54928 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
54929 
54930 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
54931 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
54932 /*! ICR5 - Interrupt configuration field for GPIO interrupt 5
54933  *  0b00..Interrupt 5 is low-level sensitive.
54934  *  0b01..Interrupt 5 is high-level sensitive.
54935  *  0b10..Interrupt 5 is rising-edge sensitive.
54936  *  0b11..Interrupt 5 is falling-edge sensitive.
54937  */
54938 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
54939 
54940 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
54941 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
54942 /*! ICR6 - Interrupt configuration field for GPIO interrupt 6
54943  *  0b00..Interrupt 6 is low-level sensitive.
54944  *  0b01..Interrupt 6 is high-level sensitive.
54945  *  0b10..Interrupt 6 is rising-edge sensitive.
54946  *  0b11..Interrupt 6 is falling-edge sensitive.
54947  */
54948 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
54949 
54950 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
54951 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
54952 /*! ICR7 - Interrupt configuration field for GPIO interrupt 7
54953  *  0b00..Interrupt 7 is low-level sensitive.
54954  *  0b01..Interrupt 7 is high-level sensitive.
54955  *  0b10..Interrupt 7 is rising-edge sensitive.
54956  *  0b11..Interrupt 7 is falling-edge sensitive.
54957  */
54958 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
54959 
54960 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
54961 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
54962 /*! ICR8 - Interrupt configuration field for GPIO interrupt 8
54963  *  0b00..Interrupt 8 is low-level sensitive.
54964  *  0b01..Interrupt 8 is high-level sensitive.
54965  *  0b10..Interrupt 8 is rising-edge sensitive.
54966  *  0b11..Interrupt 8 is falling-edge sensitive.
54967  */
54968 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
54969 
54970 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
54971 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
54972 /*! ICR9 - Interrupt configuration field for GPIO interrupt 9
54973  *  0b00..Interrupt 9 is low-level sensitive.
54974  *  0b01..Interrupt 9 is high-level sensitive.
54975  *  0b10..Interrupt 9 is rising-edge sensitive.
54976  *  0b11..Interrupt 9 is falling-edge sensitive.
54977  */
54978 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
54979 
54980 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
54981 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
54982 /*! ICR10 - Interrupt configuration field for GPIO interrupt 10
54983  *  0b00..Interrupt 10 is low-level sensitive.
54984  *  0b01..Interrupt 10 is high-level sensitive.
54985  *  0b10..Interrupt 10 is rising-edge sensitive.
54986  *  0b11..Interrupt 10 is falling-edge sensitive.
54987  */
54988 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
54989 
54990 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
54991 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
54992 /*! ICR11 - Interrupt configuration field for GPIO interrupt 11
54993  *  0b00..Interrupt 11 is low-level sensitive.
54994  *  0b01..Interrupt 11 is high-level sensitive.
54995  *  0b10..Interrupt 11 is rising-edge sensitive.
54996  *  0b11..Interrupt 11 is falling-edge sensitive.
54997  */
54998 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
54999 
55000 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
55001 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
55002 /*! ICR12 - Interrupt configuration field for GPIO interrupt 12
55003  *  0b00..Interrupt 12 is low-level sensitive.
55004  *  0b01..Interrupt 12 is high-level sensitive.
55005  *  0b10..Interrupt 12 is rising-edge sensitive.
55006  *  0b11..Interrupt 12 is falling-edge sensitive.
55007  */
55008 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
55009 
55010 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
55011 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
55012 /*! ICR13 - Interrupt configuration field for GPIO interrupt 13
55013  *  0b00..Interrupt 13 is low-level sensitive.
55014  *  0b01..Interrupt 13 is high-level sensitive.
55015  *  0b10..Interrupt 13 is rising-edge sensitive.
55016  *  0b11..Interrupt 13 is falling-edge sensitive.
55017  */
55018 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
55019 
55020 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
55021 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
55022 /*! ICR14 - Interrupt configuration field for GPIO interrupt 14
55023  *  0b00..Interrupt 14 is low-level sensitive.
55024  *  0b01..Interrupt 14 is high-level sensitive.
55025  *  0b10..Interrupt 14 is rising-edge sensitive.
55026  *  0b11..Interrupt 14 is falling-edge sensitive.
55027  */
55028 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
55029 
55030 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
55031 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
55032 /*! ICR15 - Interrupt configuration field for GPIO interrupt 15
55033  *  0b00..Interrupt 15 is low-level sensitive.
55034  *  0b01..Interrupt 15 is high-level sensitive.
55035  *  0b10..Interrupt 15 is rising-edge sensitive.
55036  *  0b11..Interrupt 15 is falling-edge sensitive.
55037  */
55038 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
55039 /*! @} */
55040 
55041 /*! @name ICR2 - GPIO interrupt configuration register2 */
55042 /*! @{ */
55043 
55044 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
55045 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
55046 /*! ICR16 - Interrupt configuration field for GPIO interrupt 16
55047  *  0b00..Interrupt 16 is low-level sensitive.
55048  *  0b01..Interrupt 16 is high-level sensitive.
55049  *  0b10..Interrupt 16 is rising-edge sensitive.
55050  *  0b11..Interrupt 16 is falling-edge sensitive.
55051  */
55052 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
55053 
55054 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
55055 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
55056 /*! ICR17 - Interrupt configuration field for GPIO interrupt 17
55057  *  0b00..Interrupt 17 is low-level sensitive.
55058  *  0b01..Interrupt 17 is high-level sensitive.
55059  *  0b10..Interrupt 17 is rising-edge sensitive.
55060  *  0b11..Interrupt 17 is falling-edge sensitive.
55061  */
55062 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
55063 
55064 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
55065 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
55066 /*! ICR18 - Interrupt configuration field for GPIO interrupt 18
55067  *  0b00..Interrupt 18 is low-level sensitive.
55068  *  0b01..Interrupt 18 is high-level sensitive.
55069  *  0b10..Interrupt 18 is rising-edge sensitive.
55070  *  0b11..Interrupt 18 is falling-edge sensitive.
55071  */
55072 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
55073 
55074 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
55075 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
55076 /*! ICR19 - Interrupt configuration field for GPIO interrupt 19
55077  *  0b00..Interrupt 19 is low-level sensitive.
55078  *  0b01..Interrupt 19 is high-level sensitive.
55079  *  0b10..Interrupt 19 is rising-edge sensitive.
55080  *  0b11..Interrupt 19 is falling-edge sensitive.
55081  */
55082 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
55083 
55084 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
55085 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
55086 /*! ICR20 - Interrupt configuration field for GPIO interrupt 20
55087  *  0b00..Interrupt 20 is low-level sensitive.
55088  *  0b01..Interrupt 20 is high-level sensitive.
55089  *  0b10..Interrupt 20 is rising-edge sensitive.
55090  *  0b11..Interrupt 20 is falling-edge sensitive.
55091  */
55092 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
55093 
55094 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
55095 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
55096 /*! ICR21 - Interrupt configuration field for GPIO interrupt 21
55097  *  0b00..Interrupt 21 is low-level sensitive.
55098  *  0b01..Interrupt 21 is high-level sensitive.
55099  *  0b10..Interrupt 21 is rising-edge sensitive.
55100  *  0b11..Interrupt 21 is falling-edge sensitive.
55101  */
55102 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
55103 
55104 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
55105 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
55106 /*! ICR22 - Interrupt configuration field for GPIO interrupt 22
55107  *  0b00..Interrupt 22 is low-level sensitive.
55108  *  0b01..Interrupt 22 is high-level sensitive.
55109  *  0b10..Interrupt 22 is rising-edge sensitive.
55110  *  0b11..Interrupt 22 is falling-edge sensitive.
55111  */
55112 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
55113 
55114 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
55115 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
55116 /*! ICR23 - Interrupt configuration field for GPIO interrupt 23
55117  *  0b00..Interrupt 23 is low-level sensitive.
55118  *  0b01..Interrupt 23 is high-level sensitive.
55119  *  0b10..Interrupt 23 is rising-edge sensitive.
55120  *  0b11..Interrupt 23 is falling-edge sensitive.
55121  */
55122 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
55123 
55124 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
55125 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
55126 /*! ICR24 - Interrupt configuration field for GPIO interrupt 24
55127  *  0b00..Interrupt 24 is low-level sensitive.
55128  *  0b01..Interrupt 24 is high-level sensitive.
55129  *  0b10..Interrupt 24 is rising-edge sensitive.
55130  *  0b11..Interrupt 24 is falling-edge sensitive.
55131  */
55132 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
55133 
55134 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
55135 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
55136 /*! ICR25 - Interrupt configuration field for GPIO interrupt 25
55137  *  0b00..Interrupt 25 is low-level sensitive.
55138  *  0b01..Interrupt 25 is high-level sensitive.
55139  *  0b10..Interrupt 25 is rising-edge sensitive.
55140  *  0b11..Interrupt 25 is falling-edge sensitive.
55141  */
55142 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
55143 
55144 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
55145 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
55146 /*! ICR26 - Interrupt configuration field for GPIO interrupt 26
55147  *  0b00..Interrupt 26 is low-level sensitive.
55148  *  0b01..Interrupt 26 is high-level sensitive.
55149  *  0b10..Interrupt 26 is rising-edge sensitive.
55150  *  0b11..Interrupt 26 is falling-edge sensitive.
55151  */
55152 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
55153 
55154 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
55155 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
55156 /*! ICR27 - Interrupt configuration field for GPIO interrupt 27
55157  *  0b00..Interrupt 27 is low-level sensitive.
55158  *  0b01..Interrupt 27 is high-level sensitive.
55159  *  0b10..Interrupt 27 is rising-edge sensitive.
55160  *  0b11..Interrupt 27 is falling-edge sensitive.
55161  */
55162 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
55163 
55164 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
55165 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
55166 /*! ICR28 - Interrupt configuration field for GPIO interrupt 28
55167  *  0b00..Interrupt 28 is low-level sensitive.
55168  *  0b01..Interrupt 28 is high-level sensitive.
55169  *  0b10..Interrupt 28 is rising-edge sensitive.
55170  *  0b11..Interrupt 28 is falling-edge sensitive.
55171  */
55172 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
55173 
55174 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
55175 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
55176 /*! ICR29 - Interrupt configuration field for GPIO interrupt 29
55177  *  0b00..Interrupt 29 is low-level sensitive.
55178  *  0b01..Interrupt 29 is high-level sensitive.
55179  *  0b10..Interrupt 29 is rising-edge sensitive.
55180  *  0b11..Interrupt 29 is falling-edge sensitive.
55181  */
55182 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
55183 
55184 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
55185 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
55186 /*! ICR30 - Interrupt configuration field for GPIO interrupt 30
55187  *  0b00..Interrupt 30 is low-level sensitive.
55188  *  0b01..Interrupt 30 is high-level sensitive.
55189  *  0b10..Interrupt 30 is rising-edge sensitive.
55190  *  0b11..Interrupt 30 is falling-edge sensitive.
55191  */
55192 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
55193 
55194 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
55195 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
55196 /*! ICR31 - Interrupt configuration field for GPIO interrupt 31
55197  *  0b00..Interrupt 31 is low-level sensitive.
55198  *  0b01..Interrupt 31 is high-level sensitive.
55199  *  0b10..Interrupt 31 is rising-edge sensitive.
55200  *  0b11..Interrupt 31 is falling-edge sensitive.
55201  */
55202 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
55203 /*! @} */
55204 
55205 /*! @name IMR - GPIO interrupt mask register */
55206 /*! @{ */
55207 
55208 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
55209 #define GPIO_IMR_IMR_SHIFT                       (0U)
55210 /*! IMR - Interrupt Mask bits
55211  */
55212 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
55213 /*! @} */
55214 
55215 /*! @name ISR - GPIO interrupt status register */
55216 /*! @{ */
55217 
55218 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
55219 #define GPIO_ISR_ISR_SHIFT                       (0U)
55220 /*! ISR - Interrupt status bits
55221  */
55222 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
55223 /*! @} */
55224 
55225 /*! @name EDGE_SEL - GPIO edge select register */
55226 /*! @{ */
55227 
55228 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
55229 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
55230 /*! GPIO_EDGE_SEL - Edge select
55231  */
55232 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
55233 /*! @} */
55234 
55235 /*! @name DR_SET - GPIO data register SET */
55236 /*! @{ */
55237 
55238 #define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
55239 #define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
55240 /*! DR_SET - Set
55241  */
55242 #define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
55243 /*! @} */
55244 
55245 /*! @name DR_CLEAR - GPIO data register CLEAR */
55246 /*! @{ */
55247 
55248 #define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
55249 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
55250 /*! DR_CLEAR - Clear
55251  */
55252 #define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
55253 /*! @} */
55254 
55255 /*! @name DR_TOGGLE - GPIO data register TOGGLE */
55256 /*! @{ */
55257 
55258 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
55259 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
55260 /*! DR_TOGGLE - Toggle
55261  */
55262 #define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
55263 /*! @} */
55264 
55265 
55266 /*!
55267  * @}
55268  */ /* end of group GPIO_Register_Masks */
55269 
55270 
55271 /* GPIO - Peripheral instance base addresses */
55272 /** Peripheral GPIO1 base address */
55273 #define GPIO1_BASE                               (0x4012C000u)
55274 /** Peripheral GPIO1 base pointer */
55275 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
55276 /** Peripheral GPIO2 base address */
55277 #define GPIO2_BASE                               (0x40130000u)
55278 /** Peripheral GPIO2 base pointer */
55279 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
55280 /** Peripheral GPIO3 base address */
55281 #define GPIO3_BASE                               (0x40134000u)
55282 /** Peripheral GPIO3 base pointer */
55283 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
55284 /** Peripheral GPIO4 base address */
55285 #define GPIO4_BASE                               (0x40138000u)
55286 /** Peripheral GPIO4 base pointer */
55287 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
55288 /** Peripheral GPIO5 base address */
55289 #define GPIO5_BASE                               (0x4013C000u)
55290 /** Peripheral GPIO5 base pointer */
55291 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
55292 /** Peripheral GPIO6 base address */
55293 #define GPIO6_BASE                               (0x40140000u)
55294 /** Peripheral GPIO6 base pointer */
55295 #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
55296 /** Peripheral GPIO7 base address */
55297 #define GPIO7_BASE                               (0x40C5C000u)
55298 /** Peripheral GPIO7 base pointer */
55299 #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
55300 /** Peripheral GPIO8 base address */
55301 #define GPIO8_BASE                               (0x40C60000u)
55302 /** Peripheral GPIO8 base pointer */
55303 #define GPIO8                                    ((GPIO_Type *)GPIO8_BASE)
55304 /** Peripheral GPIO9 base address */
55305 #define GPIO9_BASE                               (0x40C64000u)
55306 /** Peripheral GPIO9 base pointer */
55307 #define GPIO9                                    ((GPIO_Type *)GPIO9_BASE)
55308 /** Peripheral GPIO10 base address */
55309 #define GPIO10_BASE                              (0x40C68000u)
55310 /** Peripheral GPIO10 base pointer */
55311 #define GPIO10                                   ((GPIO_Type *)GPIO10_BASE)
55312 /** Peripheral GPIO11 base address */
55313 #define GPIO11_BASE                              (0x40C6C000u)
55314 /** Peripheral GPIO11 base pointer */
55315 #define GPIO11                                   ((GPIO_Type *)GPIO11_BASE)
55316 /** Peripheral GPIO12 base address */
55317 #define GPIO12_BASE                              (0x40C70000u)
55318 /** Peripheral GPIO12 base pointer */
55319 #define GPIO12                                   ((GPIO_Type *)GPIO12_BASE)
55320 /** Peripheral GPIO13 base address */
55321 #define GPIO13_BASE                              (0x40CA0000u)
55322 /** Peripheral GPIO13 base pointer */
55323 #define GPIO13                                   ((GPIO_Type *)GPIO13_BASE)
55324 /** Peripheral CM7_GPIO2 base address */
55325 #define CM7_GPIO2_BASE                           (0x42008000u)
55326 /** Peripheral CM7_GPIO2 base pointer */
55327 #define CM7_GPIO2                                ((GPIO_Type *)CM7_GPIO2_BASE)
55328 /** Peripheral CM7_GPIO3 base address */
55329 #define CM7_GPIO3_BASE                           (0x4200C000u)
55330 /** Peripheral CM7_GPIO3 base pointer */
55331 #define CM7_GPIO3                                ((GPIO_Type *)CM7_GPIO3_BASE)
55332 /** Array initializer of GPIO peripheral base addresses */
55333 #define GPIO_BASE_ADDRS                          { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
55334 /** Array initializer of GPIO peripheral base pointers */
55335 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
55336 /** Interrupt vectors for the GPIO peripheral type */
55337 #define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_Combined_0_15_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
55338 #define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_Combined_16_31_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
55339 
55340 /*!
55341  * @}
55342  */ /* end of group GPIO_Peripheral_Access_Layer */
55343 
55344 
55345 /* ----------------------------------------------------------------------------
55346    -- GPT Peripheral Access Layer
55347    ---------------------------------------------------------------------------- */
55348 
55349 /*!
55350  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
55351  * @{
55352  */
55353 
55354 /** GPT - Register Layout Typedef */
55355 typedef struct {
55356   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
55357   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
55358   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
55359   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
55360   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register, array offset: 0x10, array step: 0x4 */
55361   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register, array offset: 0x1C, array step: 0x4 */
55362   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
55363 } GPT_Type;
55364 
55365 /* ----------------------------------------------------------------------------
55366    -- GPT Register Masks
55367    ---------------------------------------------------------------------------- */
55368 
55369 /*!
55370  * @addtogroup GPT_Register_Masks GPT Register Masks
55371  * @{
55372  */
55373 
55374 /*! @name CR - GPT Control Register */
55375 /*! @{ */
55376 
55377 #define GPT_CR_EN_MASK                           (0x1U)
55378 #define GPT_CR_EN_SHIFT                          (0U)
55379 /*! EN - GPT Enable
55380  *  0b0..Disable
55381  *  0b1..Enable
55382  */
55383 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
55384 
55385 #define GPT_CR_ENMOD_MASK                        (0x2U)
55386 #define GPT_CR_ENMOD_SHIFT                       (1U)
55387 /*! ENMOD - GPT Enable Mode
55388  *  0b0..Restart counting from their frozen values after GPT is enabled (EN=1).
55389  *  0b1..Reset counting from 0 after GPT is enabled (EN=1).
55390  */
55391 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
55392 
55393 #define GPT_CR_DBGEN_MASK                        (0x4U)
55394 #define GPT_CR_DBGEN_SHIFT                       (2U)
55395 /*! DBGEN - GPT Debug Mode Enable
55396  *  0b0..Disable in Debug mode
55397  *  0b1..Enable in Debug mode
55398  */
55399 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
55400 
55401 #define GPT_CR_WAITEN_MASK                       (0x8U)
55402 #define GPT_CR_WAITEN_SHIFT                      (3U)
55403 /*! WAITEN - GPT Wait Mode Enable
55404  *  0b0..Disable in Wait mode
55405  *  0b1..Enable in Wait mode
55406  */
55407 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
55408 
55409 #define GPT_CR_DOZEEN_MASK                       (0x10U)
55410 #define GPT_CR_DOZEEN_SHIFT                      (4U)
55411 /*! DOZEEN - GPT Doze Mode Enable
55412  *  0b0..Disable in Doze mode
55413  *  0b1..Enable in Doze mode
55414  */
55415 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
55416 
55417 #define GPT_CR_STOPEN_MASK                       (0x20U)
55418 #define GPT_CR_STOPEN_SHIFT                      (5U)
55419 /*! STOPEN - GPT Stop Mode Enable
55420  *  0b0..Disable in Stop mode
55421  *  0b1..Enable in Stop mode
55422  */
55423 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
55424 
55425 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
55426 #define GPT_CR_CLKSRC_SHIFT                      (6U)
55427 /*! CLKSRC - Clock Source Select
55428  *  0b000..No clock
55429  *  0b001..Peripheral Clock (ipg_clk)
55430  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
55431  *  0b011..External Clock
55432  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
55433  *  0b101..Oscillator as Reference Clock (ipg_clk_16M)
55434  */
55435 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
55436 
55437 #define GPT_CR_FRR_MASK                          (0x200U)
55438 #define GPT_CR_FRR_SHIFT                         (9U)
55439 /*! FRR - Free-Run or Restart Mode
55440  *  0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting.
55441  *  0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.
55442  */
55443 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
55444 
55445 #define GPT_CR_EN_24M_MASK                       (0x400U)
55446 #define GPT_CR_EN_24M_SHIFT                      (10U)
55447 /*! EN_24M - Enable Oscillator Clock Input
55448  *  0b0..Disable
55449  *  0b1..Enable
55450  */
55451 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
55452 
55453 #define GPT_CR_SWR_MASK                          (0x8000U)
55454 #define GPT_CR_SWR_SHIFT                         (15U)
55455 /*! SWR - Software Reset
55456  *  0b0..GPT is not in software reset state
55457  *  0b1..GPT is in software reset state
55458  */
55459 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
55460 
55461 #define GPT_CR_IM1_MASK                          (0x30000U)
55462 #define GPT_CR_IM1_SHIFT                         (16U)
55463 /*! IM1 - Input Capture Operating Mode for Channel 1
55464  *  0b00..Capture disabled
55465  *  0b01..Capture on rising edge only
55466  *  0b10..Capture on falling edge only
55467  *  0b11..Capture on both edges
55468  */
55469 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
55470 
55471 #define GPT_CR_IM2_MASK                          (0xC0000U)
55472 #define GPT_CR_IM2_SHIFT                         (18U)
55473 /*! IM2 - Input Capture Operating Mode for Channel 2
55474  *  0b00..Capture disabled
55475  *  0b01..Capture on rising edge only
55476  *  0b10..Capture on falling edge only
55477  *  0b11..Capture on both edges
55478  */
55479 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
55480 
55481 #define GPT_CR_OM1_MASK                          (0x700000U)
55482 #define GPT_CR_OM1_SHIFT                         (20U)
55483 /*! OM1 - Output Compare Operating Mode for Channel 1
55484  *  0b000..Output disabled. No response on pin.
55485  *  0b001..Toggle output pin
55486  *  0b010..Clear output pin
55487  *  0b011..Set output pin
55488  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
55489  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
55490  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
55491  */
55492 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
55493 
55494 #define GPT_CR_OM2_MASK                          (0x3800000U)
55495 #define GPT_CR_OM2_SHIFT                         (23U)
55496 /*! OM2 - Output Compare Operating Mode for Channel 2
55497  *  0b000..Output disabled. No response on pin.
55498  *  0b001..Toggle output pin
55499  *  0b010..Clear output pin
55500  *  0b011..Set output pin
55501  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
55502  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
55503  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
55504  */
55505 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
55506 
55507 #define GPT_CR_OM3_MASK                          (0x1C000000U)
55508 #define GPT_CR_OM3_SHIFT                         (26U)
55509 /*! OM3 - Output Compare Operating Mode for Channel 3
55510  *  0b000..Output disabled. No response on pin.
55511  *  0b001..Toggle output pin
55512  *  0b010..Clear output pin
55513  *  0b011..Set output pin
55514  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
55515  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
55516  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
55517  */
55518 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
55519 
55520 #define GPT_CR_FO1_MASK                          (0x20000000U)
55521 #define GPT_CR_FO1_SHIFT                         (29U)
55522 /*! FO1 - Force Output Compare for Channel 1
55523  *  0b0..No effect
55524  *  0b1..Trigger the programmed response on the pin
55525  */
55526 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
55527 
55528 #define GPT_CR_FO2_MASK                          (0x40000000U)
55529 #define GPT_CR_FO2_SHIFT                         (30U)
55530 /*! FO2 - Force Output Compare for Channel 2
55531  *  0b0..No effect
55532  *  0b1..Trigger the programmed response on the pin
55533  */
55534 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
55535 
55536 #define GPT_CR_FO3_MASK                          (0x80000000U)
55537 #define GPT_CR_FO3_SHIFT                         (31U)
55538 /*! FO3 - Force Output Compare for Channel 3
55539  *  0b0..No effect
55540  *  0b1..Trigger the programmed response on the pin
55541  */
55542 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
55543 /*! @} */
55544 
55545 /*! @name PR - GPT Prescaler Register */
55546 /*! @{ */
55547 
55548 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
55549 #define GPT_PR_PRESCALER_SHIFT                   (0U)
55550 /*! PRESCALER - Prescaler divide value
55551  *  0b000000000000..Divide by 1
55552  *  0b000000000001..Divide by 2
55553  *  0b111111111111..Divide by 4096
55554  */
55555 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
55556 
55557 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
55558 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
55559 /*! PRESCALER24M - Prescaler divide value for the oscillator clock
55560  *  0b0000..Divide by 1
55561  *  0b0001..Divide by 2
55562  *  0b1111..Divide by 16
55563  */
55564 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
55565 /*! @} */
55566 
55567 /*! @name SR - GPT Status Register */
55568 /*! @{ */
55569 
55570 #define GPT_SR_OF1_MASK                          (0x1U)
55571 #define GPT_SR_OF1_SHIFT                         (0U)
55572 /*! OF1 - Output Compare Flag for Channel 1
55573  *  0b0..Compare event has not occurred.
55574  *  0b1..Compare event has occurred.
55575  */
55576 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
55577 
55578 #define GPT_SR_OF2_MASK                          (0x2U)
55579 #define GPT_SR_OF2_SHIFT                         (1U)
55580 /*! OF2 - Output Compare Flag for Channel 2
55581  *  0b0..Compare event has not occurred.
55582  *  0b1..Compare event has occurred.
55583  */
55584 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
55585 
55586 #define GPT_SR_OF3_MASK                          (0x4U)
55587 #define GPT_SR_OF3_SHIFT                         (2U)
55588 /*! OF3 - Output Compare Flag for Channel 3
55589  *  0b0..Compare event has not occurred.
55590  *  0b1..Compare event has occurred.
55591  */
55592 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
55593 
55594 #define GPT_SR_IF1_MASK                          (0x8U)
55595 #define GPT_SR_IF1_SHIFT                         (3U)
55596 /*! IF1 - Input Capture Flag for Channel 1
55597  *  0b0..Capture event has not occurred.
55598  *  0b1..Capture event has occurred.
55599  */
55600 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
55601 
55602 #define GPT_SR_IF2_MASK                          (0x10U)
55603 #define GPT_SR_IF2_SHIFT                         (4U)
55604 /*! IF2 - Input Capture Flag for Channel 2
55605  *  0b0..Capture event has not occurred.
55606  *  0b1..Capture event has occurred.
55607  */
55608 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
55609 
55610 #define GPT_SR_ROV_MASK                          (0x20U)
55611 #define GPT_SR_ROV_SHIFT                         (5U)
55612 /*! ROV - Rollover Flag
55613  *  0b0..Rollover has not occurred.
55614  *  0b1..Rollover has occurred.
55615  */
55616 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
55617 /*! @} */
55618 
55619 /*! @name IR - GPT Interrupt Register */
55620 /*! @{ */
55621 
55622 #define GPT_IR_OF1IE_MASK                        (0x1U)
55623 #define GPT_IR_OF1IE_SHIFT                       (0U)
55624 /*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable
55625  *  0b0..Disable
55626  *  0b1..Enable
55627  */
55628 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
55629 
55630 #define GPT_IR_OF2IE_MASK                        (0x2U)
55631 #define GPT_IR_OF2IE_SHIFT                       (1U)
55632 /*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable
55633  *  0b0..Disable
55634  *  0b1..Enable
55635  */
55636 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
55637 
55638 #define GPT_IR_OF3IE_MASK                        (0x4U)
55639 #define GPT_IR_OF3IE_SHIFT                       (2U)
55640 /*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable
55641  *  0b0..Disable
55642  *  0b1..Enable
55643  */
55644 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
55645 
55646 #define GPT_IR_IF1IE_MASK                        (0x8U)
55647 #define GPT_IR_IF1IE_SHIFT                       (3U)
55648 /*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable
55649  *  0b0..Disable
55650  *  0b1..Enable
55651  */
55652 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
55653 
55654 #define GPT_IR_IF2IE_MASK                        (0x10U)
55655 #define GPT_IR_IF2IE_SHIFT                       (4U)
55656 /*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable
55657  *  0b0..Disable
55658  *  0b1..Enable
55659  */
55660 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
55661 
55662 #define GPT_IR_ROVIE_MASK                        (0x20U)
55663 #define GPT_IR_ROVIE_SHIFT                       (5U)
55664 /*! ROVIE - Rollover Interrupt Enable
55665  *  0b0..Disable
55666  *  0b1..Enable
55667  */
55668 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
55669 /*! @} */
55670 
55671 /*! @name OCR - GPT Output Compare Register */
55672 /*! @{ */
55673 
55674 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
55675 #define GPT_OCR_COMP_SHIFT                       (0U)
55676 /*! COMP - Compare Value
55677  */
55678 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
55679 /*! @} */
55680 
55681 /* The count of GPT_OCR */
55682 #define GPT_OCR_COUNT                            (3U)
55683 
55684 /*! @name ICR - GPT Input Capture Register */
55685 /*! @{ */
55686 
55687 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
55688 #define GPT_ICR_CAPT_SHIFT                       (0U)
55689 /*! CAPT - Capture Value
55690  */
55691 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
55692 /*! @} */
55693 
55694 /* The count of GPT_ICR */
55695 #define GPT_ICR_COUNT                            (2U)
55696 
55697 /*! @name CNT - GPT Counter Register */
55698 /*! @{ */
55699 
55700 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
55701 #define GPT_CNT_COUNT_SHIFT                      (0U)
55702 /*! COUNT - Counter Value
55703  */
55704 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
55705 /*! @} */
55706 
55707 
55708 /*!
55709  * @}
55710  */ /* end of group GPT_Register_Masks */
55711 
55712 
55713 /* GPT - Peripheral instance base addresses */
55714 /** Peripheral GPT1 base address */
55715 #define GPT1_BASE                                (0x400EC000u)
55716 /** Peripheral GPT1 base pointer */
55717 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
55718 /** Peripheral GPT2 base address */
55719 #define GPT2_BASE                                (0x400F0000u)
55720 /** Peripheral GPT2 base pointer */
55721 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
55722 /** Peripheral GPT3 base address */
55723 #define GPT3_BASE                                (0x400F4000u)
55724 /** Peripheral GPT3 base pointer */
55725 #define GPT3                                     ((GPT_Type *)GPT3_BASE)
55726 /** Peripheral GPT4 base address */
55727 #define GPT4_BASE                                (0x400F8000u)
55728 /** Peripheral GPT4 base pointer */
55729 #define GPT4                                     ((GPT_Type *)GPT4_BASE)
55730 /** Peripheral GPT5 base address */
55731 #define GPT5_BASE                                (0x400FC000u)
55732 /** Peripheral GPT5 base pointer */
55733 #define GPT5                                     ((GPT_Type *)GPT5_BASE)
55734 /** Peripheral GPT6 base address */
55735 #define GPT6_BASE                                (0x40100000u)
55736 /** Peripheral GPT6 base pointer */
55737 #define GPT6                                     ((GPT_Type *)GPT6_BASE)
55738 /** Array initializer of GPT peripheral base addresses */
55739 #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
55740 /** Array initializer of GPT peripheral base pointers */
55741 #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
55742 /** Interrupt vectors for the GPT peripheral type */
55743 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
55744 
55745 /*!
55746  * @}
55747  */ /* end of group GPT_Peripheral_Access_Layer */
55748 
55749 
55750 /* ----------------------------------------------------------------------------
55751    -- I2S Peripheral Access Layer
55752    ---------------------------------------------------------------------------- */
55753 
55754 /*!
55755  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
55756  * @{
55757  */
55758 
55759 /** I2S - Register Layout Typedef */
55760 typedef struct {
55761   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
55762   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
55763   __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
55764   __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
55765   __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
55766   __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
55767   __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
55768   __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
55769   __O  uint32_t TDR[4];                            /**< Transmit Data, array offset: 0x20, array step: 0x4 */
55770        uint8_t RESERVED_0[16];
55771   __I  uint32_t TFR[4];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */
55772        uint8_t RESERVED_1[16];
55773   __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
55774        uint8_t RESERVED_2[36];
55775   __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
55776   __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
55777   __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
55778   __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
55779   __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
55780   __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
55781   __I  uint32_t RDR[4];                            /**< Receive Data, array offset: 0xA0, array step: 0x4 */
55782        uint8_t RESERVED_3[16];
55783   __I  uint32_t RFR[4];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */
55784        uint8_t RESERVED_4[16];
55785   __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
55786 } I2S_Type;
55787 
55788 /* ----------------------------------------------------------------------------
55789    -- I2S Register Masks
55790    ---------------------------------------------------------------------------- */
55791 
55792 /*!
55793  * @addtogroup I2S_Register_Masks I2S Register Masks
55794  * @{
55795  */
55796 
55797 /*! @name VERID - Version ID */
55798 /*! @{ */
55799 
55800 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
55801 #define I2S_VERID_FEATURE_SHIFT                  (0U)
55802 /*! FEATURE - Feature Specification Number
55803  *  0b0000000000000000..Standard feature set.
55804  */
55805 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
55806 
55807 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
55808 #define I2S_VERID_MINOR_SHIFT                    (16U)
55809 /*! MINOR - Minor Version Number
55810  */
55811 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
55812 
55813 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
55814 #define I2S_VERID_MAJOR_SHIFT                    (24U)
55815 /*! MAJOR - Major Version Number
55816  */
55817 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
55818 /*! @} */
55819 
55820 /*! @name PARAM - Parameter */
55821 /*! @{ */
55822 
55823 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
55824 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
55825 /*! DATALINE - Number of Datalines
55826  */
55827 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
55828 
55829 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
55830 #define I2S_PARAM_FIFO_SHIFT                     (8U)
55831 /*! FIFO - FIFO Size
55832  */
55833 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
55834 
55835 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
55836 #define I2S_PARAM_FRAME_SHIFT                    (16U)
55837 /*! FRAME - Frame Size
55838  */
55839 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
55840 /*! @} */
55841 
55842 /*! @name TCSR - Transmit Control */
55843 /*! @{ */
55844 
55845 #define I2S_TCSR_FRDE_MASK                       (0x1U)
55846 #define I2S_TCSR_FRDE_SHIFT                      (0U)
55847 /*! FRDE - FIFO Request DMA Enable
55848  *  0b0..Disables the DMA request.
55849  *  0b1..Enables the DMA request.
55850  */
55851 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
55852 
55853 #define I2S_TCSR_FWDE_MASK                       (0x2U)
55854 #define I2S_TCSR_FWDE_SHIFT                      (1U)
55855 /*! FWDE - FIFO Warning DMA Enable
55856  *  0b0..Disables the DMA request.
55857  *  0b1..Enables the DMA request.
55858  */
55859 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
55860 
55861 #define I2S_TCSR_FRIE_MASK                       (0x100U)
55862 #define I2S_TCSR_FRIE_SHIFT                      (8U)
55863 /*! FRIE - FIFO Request Interrupt Enable
55864  *  0b0..Disables the interrupt.
55865  *  0b1..Enables the interrupt.
55866  */
55867 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
55868 
55869 #define I2S_TCSR_FWIE_MASK                       (0x200U)
55870 #define I2S_TCSR_FWIE_SHIFT                      (9U)
55871 /*! FWIE - FIFO Warning Interrupt Enable
55872  *  0b0..Disables the interrupt.
55873  *  0b1..Enables the interrupt.
55874  */
55875 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
55876 
55877 #define I2S_TCSR_FEIE_MASK                       (0x400U)
55878 #define I2S_TCSR_FEIE_SHIFT                      (10U)
55879 /*! FEIE - FIFO Error Interrupt Enable
55880  *  0b0..Disables the interrupt.
55881  *  0b1..Enables the interrupt.
55882  */
55883 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
55884 
55885 #define I2S_TCSR_SEIE_MASK                       (0x800U)
55886 #define I2S_TCSR_SEIE_SHIFT                      (11U)
55887 /*! SEIE - Sync Error Interrupt Enable
55888  *  0b0..Disables interrupt.
55889  *  0b1..Enables interrupt.
55890  */
55891 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
55892 
55893 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
55894 #define I2S_TCSR_WSIE_SHIFT                      (12U)
55895 /*! WSIE - Word Start Interrupt Enable
55896  *  0b0..Disables interrupt.
55897  *  0b1..Enables interrupt.
55898  */
55899 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
55900 
55901 #define I2S_TCSR_FRF_MASK                        (0x10000U)
55902 #define I2S_TCSR_FRF_SHIFT                       (16U)
55903 /*! FRF - FIFO Request Flag
55904  *  0b0..Transmit FIFO watermark has not been reached.
55905  *  0b1..Transmit FIFO watermark has been reached.
55906  */
55907 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
55908 
55909 #define I2S_TCSR_FWF_MASK                        (0x20000U)
55910 #define I2S_TCSR_FWF_SHIFT                       (17U)
55911 /*! FWF - FIFO Warning Flag
55912  *  0b0..No enabled transmit FIFO is empty.
55913  *  0b1..Enabled transmit FIFO is empty.
55914  */
55915 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
55916 
55917 #define I2S_TCSR_FEF_MASK                        (0x40000U)
55918 #define I2S_TCSR_FEF_SHIFT                       (18U)
55919 /*! FEF - FIFO Error Flag
55920  *  0b0..Transmit underrun not detected.
55921  *  0b1..Transmit underrun detected.
55922  */
55923 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
55924 
55925 #define I2S_TCSR_SEF_MASK                        (0x80000U)
55926 #define I2S_TCSR_SEF_SHIFT                       (19U)
55927 /*! SEF - Sync Error Flag
55928  *  0b0..Sync error not detected.
55929  *  0b1..Frame sync error detected.
55930  */
55931 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
55932 
55933 #define I2S_TCSR_WSF_MASK                        (0x100000U)
55934 #define I2S_TCSR_WSF_SHIFT                       (20U)
55935 /*! WSF - Word Start Flag
55936  *  0b0..Start of word not detected.
55937  *  0b1..Start of word detected.
55938  */
55939 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
55940 
55941 #define I2S_TCSR_SR_MASK                         (0x1000000U)
55942 #define I2S_TCSR_SR_SHIFT                        (24U)
55943 /*! SR - Software Reset
55944  *  0b0..No effect.
55945  *  0b1..Software reset.
55946  */
55947 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
55948 
55949 #define I2S_TCSR_FR_MASK                         (0x2000000U)
55950 #define I2S_TCSR_FR_SHIFT                        (25U)
55951 /*! FR - FIFO Reset
55952  *  0b0..No effect.
55953  *  0b1..FIFO reset.
55954  */
55955 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
55956 
55957 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
55958 #define I2S_TCSR_BCE_SHIFT                       (28U)
55959 /*! BCE - Bit Clock Enable
55960  *  0b0..Transmit bit clock is disabled.
55961  *  0b1..Transmit bit clock is enabled.
55962  */
55963 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
55964 
55965 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
55966 #define I2S_TCSR_DBGE_SHIFT                      (29U)
55967 /*! DBGE - Debug Enable
55968  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
55969  *  0b1..Transmitter is enabled in Debug mode.
55970  */
55971 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
55972 
55973 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
55974 #define I2S_TCSR_STOPE_SHIFT                     (30U)
55975 /*! STOPE - Stop Enable
55976  *  0b0..Transmitter disabled in Stop mode.
55977  *  0b1..Transmitter enabled in Stop mode.
55978  */
55979 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
55980 
55981 #define I2S_TCSR_TE_MASK                         (0x80000000U)
55982 #define I2S_TCSR_TE_SHIFT                        (31U)
55983 /*! TE - Transmitter Enable
55984  *  0b0..Transmitter is disabled.
55985  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
55986  */
55987 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
55988 /*! @} */
55989 
55990 /*! @name TCR1 - Transmit Configuration 1 */
55991 /*! @{ */
55992 
55993 #define I2S_TCR1_TFW_MASK                        (0x1FU)
55994 #define I2S_TCR1_TFW_SHIFT                       (0U)
55995 /*! TFW - Transmit FIFO Watermark
55996  */
55997 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
55998 /*! @} */
55999 
56000 /*! @name TCR2 - Transmit Configuration 2 */
56001 /*! @{ */
56002 
56003 #define I2S_TCR2_DIV_MASK                        (0xFFU)
56004 #define I2S_TCR2_DIV_SHIFT                       (0U)
56005 /*! DIV - Bit Clock Divide
56006  */
56007 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
56008 
56009 #define I2S_TCR2_BYP_MASK                        (0x800000U)
56010 #define I2S_TCR2_BYP_SHIFT                       (23U)
56011 /*! BYP - Bit Clock Bypass
56012  *  0b0..Internal bit clock is generated from bit clock divider.
56013  *  0b1..Internal bit clock is divide by one of the audio master clock.
56014  */
56015 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
56016 
56017 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
56018 #define I2S_TCR2_BCD_SHIFT                       (24U)
56019 /*! BCD - Bit Clock Direction
56020  *  0b0..Bit clock is generated externally in Slave mode.
56021  *  0b1..Bit clock is generated internally in Master mode.
56022  */
56023 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
56024 
56025 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
56026 #define I2S_TCR2_BCP_SHIFT                       (25U)
56027 /*! BCP - Bit Clock Polarity
56028  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
56029  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
56030  */
56031 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
56032 
56033 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
56034 #define I2S_TCR2_MSEL_SHIFT                      (26U)
56035 /*! MSEL - MCLK Select
56036  *  0b00..Bus Clock selected.
56037  *  0b01..Master Clock (MCLK) 1 option selected.
56038  *  0b10..Master Clock (MCLK) 2 option selected.
56039  *  0b11..Master Clock (MCLK) 3 option selected.
56040  */
56041 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
56042 
56043 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
56044 #define I2S_TCR2_BCI_SHIFT                       (28U)
56045 /*! BCI - Bit Clock Input
56046  *  0b0..No effect.
56047  *  0b1..Internal logic is clocked as if bit clock was externally generated.
56048  */
56049 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
56050 
56051 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
56052 #define I2S_TCR2_BCS_SHIFT                       (29U)
56053 /*! BCS - Bit Clock Swap
56054  *  0b0..Use the normal bit clock source.
56055  *  0b1..Swap the bit clock source.
56056  */
56057 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
56058 
56059 #define I2S_TCR2_SYNC_MASK                       (0x40000000U)
56060 #define I2S_TCR2_SYNC_SHIFT                      (30U)
56061 /*! SYNC - Synchronous Mode
56062  *  0b0..Asynchronous mode.
56063  *  0b1..Synchronous with receiver.
56064  */
56065 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
56066 /*! @} */
56067 
56068 /*! @name TCR3 - Transmit Configuration 3 */
56069 /*! @{ */
56070 
56071 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
56072 #define I2S_TCR3_WDFL_SHIFT                      (0U)
56073 /*! WDFL - Word Flag Configuration
56074  */
56075 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
56076 
56077 #define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
56078 #define I2S_TCR3_TCE_SHIFT                       (16U)
56079 /*! TCE - Transmit Channel Enable
56080  */
56081 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
56082 
56083 #define I2S_TCR3_CFR_MASK                        (0xF000000U)
56084 #define I2S_TCR3_CFR_SHIFT                       (24U)
56085 /*! CFR - Channel FIFO Reset
56086  */
56087 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
56088 /*! @} */
56089 
56090 /*! @name TCR4 - Transmit Configuration 4 */
56091 /*! @{ */
56092 
56093 #define I2S_TCR4_FSD_MASK                        (0x1U)
56094 #define I2S_TCR4_FSD_SHIFT                       (0U)
56095 /*! FSD - Frame Sync Direction
56096  *  0b0..Frame sync is generated externally in Slave mode.
56097  *  0b1..Frame sync is generated internally in Master mode.
56098  */
56099 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
56100 
56101 #define I2S_TCR4_FSP_MASK                        (0x2U)
56102 #define I2S_TCR4_FSP_SHIFT                       (1U)
56103 /*! FSP - Frame Sync Polarity
56104  *  0b0..Frame sync is active high.
56105  *  0b1..Frame sync is active low.
56106  */
56107 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
56108 
56109 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
56110 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
56111 /*! ONDEM - On Demand Mode
56112  *  0b0..Internal frame sync is generated continuously.
56113  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
56114  */
56115 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
56116 
56117 #define I2S_TCR4_FSE_MASK                        (0x8U)
56118 #define I2S_TCR4_FSE_SHIFT                       (3U)
56119 /*! FSE - Frame Sync Early
56120  *  0b0..Frame sync asserts with the first bit of the frame.
56121  *  0b1..Frame sync asserts one bit before the first bit of the frame.
56122  */
56123 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
56124 
56125 #define I2S_TCR4_MF_MASK                         (0x10U)
56126 #define I2S_TCR4_MF_SHIFT                        (4U)
56127 /*! MF - MSB First
56128  *  0b0..LSB is transmitted first.
56129  *  0b1..MSB is transmitted first.
56130  */
56131 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
56132 
56133 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
56134 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
56135 /*! CHMOD - Channel Mode
56136  *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
56137  *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
56138  */
56139 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
56140 
56141 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
56142 #define I2S_TCR4_SYWD_SHIFT                      (8U)
56143 /*! SYWD - Sync Width
56144  */
56145 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
56146 
56147 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
56148 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
56149 /*! FRSZ - Frame size
56150  */
56151 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
56152 
56153 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
56154 #define I2S_TCR4_FPACK_SHIFT                     (24U)
56155 /*! FPACK - FIFO Packing Mode
56156  *  0b00..FIFO packing is disabled.
56157  *  0b01..Reserved
56158  *  0b10..8-bit FIFO packing is enabled.
56159  *  0b11..16-bit FIFO packing is enabled.
56160  */
56161 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
56162 
56163 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
56164 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
56165 /*! FCOMB - FIFO Combine Mode
56166  *  0b00..FIFO combine mode disabled.
56167  *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
56168  *  0b10..FIFO combine mode enabled on FIFO writes (by software).
56169  *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
56170  */
56171 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
56172 
56173 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
56174 #define I2S_TCR4_FCONT_SHIFT                     (28U)
56175 /*! FCONT - FIFO Continue on Error
56176  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
56177  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
56178  */
56179 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
56180 /*! @} */
56181 
56182 /*! @name TCR5 - Transmit Configuration 5 */
56183 /*! @{ */
56184 
56185 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
56186 #define I2S_TCR5_FBT_SHIFT                       (8U)
56187 /*! FBT - First Bit Shifted
56188  */
56189 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
56190 
56191 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
56192 #define I2S_TCR5_W0W_SHIFT                       (16U)
56193 /*! W0W - Word 0 Width
56194  */
56195 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
56196 
56197 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
56198 #define I2S_TCR5_WNW_SHIFT                       (24U)
56199 /*! WNW - Word N Width
56200  */
56201 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
56202 /*! @} */
56203 
56204 /*! @name TDR - Transmit Data */
56205 /*! @{ */
56206 
56207 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
56208 #define I2S_TDR_TDR_SHIFT                        (0U)
56209 /*! TDR - Transmit Data Register
56210  */
56211 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
56212 /*! @} */
56213 
56214 /* The count of I2S_TDR */
56215 #define I2S_TDR_COUNT                            (4U)
56216 
56217 /*! @name TFR - Transmit FIFO */
56218 /*! @{ */
56219 
56220 #define I2S_TFR_RFP_MASK                         (0x3FU)
56221 #define I2S_TFR_RFP_SHIFT                        (0U)
56222 /*! RFP - Read FIFO Pointer
56223  */
56224 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
56225 
56226 #define I2S_TFR_WFP_MASK                         (0x3F0000U)
56227 #define I2S_TFR_WFP_SHIFT                        (16U)
56228 /*! WFP - Write FIFO Pointer
56229  */
56230 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
56231 
56232 #define I2S_TFR_WCP_MASK                         (0x80000000U)
56233 #define I2S_TFR_WCP_SHIFT                        (31U)
56234 /*! WCP - Write Channel Pointer
56235  *  0b0..No effect.
56236  *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
56237  */
56238 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
56239 /*! @} */
56240 
56241 /* The count of I2S_TFR */
56242 #define I2S_TFR_COUNT                            (4U)
56243 
56244 /*! @name TMR - Transmit Mask */
56245 /*! @{ */
56246 
56247 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
56248 #define I2S_TMR_TWM_SHIFT                        (0U)
56249 /*! TWM - Transmit Word Mask
56250  *  0b00000000000000000000000000000000..Word N is enabled.
56251  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
56252  */
56253 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
56254 /*! @} */
56255 
56256 /*! @name RCSR - Receive Control */
56257 /*! @{ */
56258 
56259 #define I2S_RCSR_FRDE_MASK                       (0x1U)
56260 #define I2S_RCSR_FRDE_SHIFT                      (0U)
56261 /*! FRDE - FIFO Request DMA Enable
56262  *  0b0..Disables the DMA request.
56263  *  0b1..Enables the DMA request.
56264  */
56265 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
56266 
56267 #define I2S_RCSR_FWDE_MASK                       (0x2U)
56268 #define I2S_RCSR_FWDE_SHIFT                      (1U)
56269 /*! FWDE - FIFO Warning DMA Enable
56270  *  0b0..Disables the DMA request.
56271  *  0b1..Enables the DMA request.
56272  */
56273 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
56274 
56275 #define I2S_RCSR_FRIE_MASK                       (0x100U)
56276 #define I2S_RCSR_FRIE_SHIFT                      (8U)
56277 /*! FRIE - FIFO Request Interrupt Enable
56278  *  0b0..Disables the interrupt.
56279  *  0b1..Enables the interrupt.
56280  */
56281 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
56282 
56283 #define I2S_RCSR_FWIE_MASK                       (0x200U)
56284 #define I2S_RCSR_FWIE_SHIFT                      (9U)
56285 /*! FWIE - FIFO Warning Interrupt Enable
56286  *  0b0..Disables the interrupt.
56287  *  0b1..Enables the interrupt.
56288  */
56289 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
56290 
56291 #define I2S_RCSR_FEIE_MASK                       (0x400U)
56292 #define I2S_RCSR_FEIE_SHIFT                      (10U)
56293 /*! FEIE - FIFO Error Interrupt Enable
56294  *  0b0..Disables the interrupt.
56295  *  0b1..Enables the interrupt.
56296  */
56297 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
56298 
56299 #define I2S_RCSR_SEIE_MASK                       (0x800U)
56300 #define I2S_RCSR_SEIE_SHIFT                      (11U)
56301 /*! SEIE - Sync Error Interrupt Enable
56302  *  0b0..Disables interrupt.
56303  *  0b1..Enables interrupt.
56304  */
56305 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
56306 
56307 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
56308 #define I2S_RCSR_WSIE_SHIFT                      (12U)
56309 /*! WSIE - Word Start Interrupt Enable
56310  *  0b0..Disables interrupt.
56311  *  0b1..Enables interrupt.
56312  */
56313 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
56314 
56315 #define I2S_RCSR_FRF_MASK                        (0x10000U)
56316 #define I2S_RCSR_FRF_SHIFT                       (16U)
56317 /*! FRF - FIFO Request Flag
56318  *  0b0..Receive FIFO watermark not reached.
56319  *  0b1..Receive FIFO watermark has been reached.
56320  */
56321 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
56322 
56323 #define I2S_RCSR_FWF_MASK                        (0x20000U)
56324 #define I2S_RCSR_FWF_SHIFT                       (17U)
56325 /*! FWF - FIFO Warning Flag
56326  *  0b0..No enabled receive FIFO is full.
56327  *  0b1..Enabled receive FIFO is full.
56328  */
56329 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
56330 
56331 #define I2S_RCSR_FEF_MASK                        (0x40000U)
56332 #define I2S_RCSR_FEF_SHIFT                       (18U)
56333 /*! FEF - FIFO Error Flag
56334  *  0b0..Receive overflow not detected.
56335  *  0b1..Receive overflow detected.
56336  */
56337 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
56338 
56339 #define I2S_RCSR_SEF_MASK                        (0x80000U)
56340 #define I2S_RCSR_SEF_SHIFT                       (19U)
56341 /*! SEF - Sync Error Flag
56342  *  0b0..Sync error not detected.
56343  *  0b1..Frame sync error detected.
56344  */
56345 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
56346 
56347 #define I2S_RCSR_WSF_MASK                        (0x100000U)
56348 #define I2S_RCSR_WSF_SHIFT                       (20U)
56349 /*! WSF - Word Start Flag
56350  *  0b0..Start of word not detected.
56351  *  0b1..Start of word detected.
56352  */
56353 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
56354 
56355 #define I2S_RCSR_SR_MASK                         (0x1000000U)
56356 #define I2S_RCSR_SR_SHIFT                        (24U)
56357 /*! SR - Software Reset
56358  *  0b0..No effect.
56359  *  0b1..Software reset.
56360  */
56361 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
56362 
56363 #define I2S_RCSR_FR_MASK                         (0x2000000U)
56364 #define I2S_RCSR_FR_SHIFT                        (25U)
56365 /*! FR - FIFO Reset
56366  *  0b0..No effect.
56367  *  0b1..FIFO reset.
56368  */
56369 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
56370 
56371 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
56372 #define I2S_RCSR_BCE_SHIFT                       (28U)
56373 /*! BCE - Bit Clock Enable
56374  *  0b0..Receive bit clock is disabled.
56375  *  0b1..Receive bit clock is enabled.
56376  */
56377 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
56378 
56379 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
56380 #define I2S_RCSR_DBGE_SHIFT                      (29U)
56381 /*! DBGE - Debug Enable
56382  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
56383  *  0b1..Receiver is enabled in Debug mode.
56384  */
56385 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
56386 
56387 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
56388 #define I2S_RCSR_STOPE_SHIFT                     (30U)
56389 /*! STOPE - Stop Enable
56390  *  0b0..Receiver disabled in Stop mode.
56391  *  0b1..Receiver enabled in Stop mode.
56392  */
56393 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
56394 
56395 #define I2S_RCSR_RE_MASK                         (0x80000000U)
56396 #define I2S_RCSR_RE_SHIFT                        (31U)
56397 /*! RE - Receiver Enable
56398  *  0b0..Receiver is disabled.
56399  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
56400  */
56401 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
56402 /*! @} */
56403 
56404 /*! @name RCR1 - Receive Configuration 1 */
56405 /*! @{ */
56406 
56407 #define I2S_RCR1_RFW_MASK                        (0x1FU)
56408 #define I2S_RCR1_RFW_SHIFT                       (0U)
56409 /*! RFW - Receive FIFO Watermark
56410  */
56411 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
56412 /*! @} */
56413 
56414 /*! @name RCR2 - Receive Configuration 2 */
56415 /*! @{ */
56416 
56417 #define I2S_RCR2_DIV_MASK                        (0xFFU)
56418 #define I2S_RCR2_DIV_SHIFT                       (0U)
56419 /*! DIV - Bit Clock Divide
56420  */
56421 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
56422 
56423 #define I2S_RCR2_BYP_MASK                        (0x800000U)
56424 #define I2S_RCR2_BYP_SHIFT                       (23U)
56425 /*! BYP - Bit Clock Bypass
56426  *  0b0..Internal bit clock is generated from bit clock divider.
56427  *  0b1..Internal bit clock is divide by one of the audio master clock.
56428  */
56429 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
56430 
56431 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
56432 #define I2S_RCR2_BCD_SHIFT                       (24U)
56433 /*! BCD - Bit Clock Direction
56434  *  0b0..Bit clock is generated externally in Slave mode.
56435  *  0b1..Bit clock is generated internally in Master mode.
56436  */
56437 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
56438 
56439 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
56440 #define I2S_RCR2_BCP_SHIFT                       (25U)
56441 /*! BCP - Bit Clock Polarity
56442  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
56443  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
56444  */
56445 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
56446 
56447 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
56448 #define I2S_RCR2_MSEL_SHIFT                      (26U)
56449 /*! MSEL - MCLK Select
56450  *  0b00..Bus Clock selected.
56451  *  0b01..Master Clock (MCLK) 1 option selected.
56452  *  0b10..Master Clock (MCLK) 2 option selected.
56453  *  0b11..Master Clock (MCLK) 3 option selected.
56454  */
56455 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
56456 
56457 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
56458 #define I2S_RCR2_BCI_SHIFT                       (28U)
56459 /*! BCI - Bit Clock Input
56460  *  0b0..No effect.
56461  *  0b1..Internal logic is clocked as if bit clock was externally generated.
56462  */
56463 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
56464 
56465 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
56466 #define I2S_RCR2_BCS_SHIFT                       (29U)
56467 /*! BCS - Bit Clock Swap
56468  *  0b0..Use the normal bit clock source.
56469  *  0b1..Swap the bit clock source.
56470  */
56471 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
56472 
56473 #define I2S_RCR2_SYNC_MASK                       (0x40000000U)
56474 #define I2S_RCR2_SYNC_SHIFT                      (30U)
56475 /*! SYNC - Synchronous Mode
56476  *  0b0..Asynchronous mode.
56477  *  0b1..Synchronous with transmitter.
56478  */
56479 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
56480 /*! @} */
56481 
56482 /*! @name RCR3 - Receive Configuration 3 */
56483 /*! @{ */
56484 
56485 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
56486 #define I2S_RCR3_WDFL_SHIFT                      (0U)
56487 /*! WDFL - Word Flag Configuration
56488  */
56489 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
56490 
56491 #define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
56492 #define I2S_RCR3_RCE_SHIFT                       (16U)
56493 /*! RCE - Receive Channel Enable
56494  */
56495 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
56496 
56497 #define I2S_RCR3_CFR_MASK                        (0xF000000U)
56498 #define I2S_RCR3_CFR_SHIFT                       (24U)
56499 /*! CFR - Channel FIFO Reset
56500  */
56501 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
56502 /*! @} */
56503 
56504 /*! @name RCR4 - Receive Configuration 4 */
56505 /*! @{ */
56506 
56507 #define I2S_RCR4_FSD_MASK                        (0x1U)
56508 #define I2S_RCR4_FSD_SHIFT                       (0U)
56509 /*! FSD - Frame Sync Direction
56510  *  0b0..Frame Sync is generated externally in Slave mode.
56511  *  0b1..Frame Sync is generated internally in Master mode.
56512  */
56513 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
56514 
56515 #define I2S_RCR4_FSP_MASK                        (0x2U)
56516 #define I2S_RCR4_FSP_SHIFT                       (1U)
56517 /*! FSP - Frame Sync Polarity
56518  *  0b0..Frame sync is active high.
56519  *  0b1..Frame sync is active low.
56520  */
56521 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
56522 
56523 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
56524 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
56525 /*! ONDEM - On Demand Mode
56526  *  0b0..Internal frame sync is generated continuously.
56527  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
56528  */
56529 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
56530 
56531 #define I2S_RCR4_FSE_MASK                        (0x8U)
56532 #define I2S_RCR4_FSE_SHIFT                       (3U)
56533 /*! FSE - Frame Sync Early
56534  *  0b0..Frame sync asserts with the first bit of the frame.
56535  *  0b1..Frame sync asserts one bit before the first bit of the frame.
56536  */
56537 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
56538 
56539 #define I2S_RCR4_MF_MASK                         (0x10U)
56540 #define I2S_RCR4_MF_SHIFT                        (4U)
56541 /*! MF - MSB First
56542  *  0b0..LSB is received first.
56543  *  0b1..MSB is received first.
56544  */
56545 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
56546 
56547 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
56548 #define I2S_RCR4_SYWD_SHIFT                      (8U)
56549 /*! SYWD - Sync Width
56550  */
56551 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
56552 
56553 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
56554 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
56555 /*! FRSZ - Frame Size
56556  */
56557 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
56558 
56559 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
56560 #define I2S_RCR4_FPACK_SHIFT                     (24U)
56561 /*! FPACK - FIFO Packing Mode
56562  *  0b00..FIFO packing is disabled
56563  *  0b01..Reserved.
56564  *  0b10..8-bit FIFO packing is enabled
56565  *  0b11..16-bit FIFO packing is enabled
56566  */
56567 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
56568 
56569 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
56570 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
56571 /*! FCOMB - FIFO Combine Mode
56572  *  0b00..FIFO combine mode disabled.
56573  *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
56574  *  0b10..FIFO combine mode enabled on FIFO reads (by software).
56575  *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
56576  */
56577 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
56578 
56579 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
56580 #define I2S_RCR4_FCONT_SHIFT                     (28U)
56581 /*! FCONT - FIFO Continue on Error
56582  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
56583  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
56584  */
56585 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
56586 /*! @} */
56587 
56588 /*! @name RCR5 - Receive Configuration 5 */
56589 /*! @{ */
56590 
56591 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
56592 #define I2S_RCR5_FBT_SHIFT                       (8U)
56593 /*! FBT - First Bit Shifted
56594  */
56595 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
56596 
56597 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
56598 #define I2S_RCR5_W0W_SHIFT                       (16U)
56599 /*! W0W - Word 0 Width
56600  */
56601 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
56602 
56603 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
56604 #define I2S_RCR5_WNW_SHIFT                       (24U)
56605 /*! WNW - Word N Width
56606  */
56607 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
56608 /*! @} */
56609 
56610 /*! @name RDR - Receive Data */
56611 /*! @{ */
56612 
56613 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
56614 #define I2S_RDR_RDR_SHIFT                        (0U)
56615 /*! RDR - Receive Data Register
56616  */
56617 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
56618 /*! @} */
56619 
56620 /* The count of I2S_RDR */
56621 #define I2S_RDR_COUNT                            (4U)
56622 
56623 /*! @name RFR - Receive FIFO */
56624 /*! @{ */
56625 
56626 #define I2S_RFR_RFP_MASK                         (0x3FU)
56627 #define I2S_RFR_RFP_SHIFT                        (0U)
56628 /*! RFP - Read FIFO Pointer
56629  */
56630 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
56631 
56632 #define I2S_RFR_RCP_MASK                         (0x8000U)
56633 #define I2S_RFR_RCP_SHIFT                        (15U)
56634 /*! RCP - Receive Channel Pointer
56635  *  0b0..No effect.
56636  *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
56637  */
56638 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
56639 
56640 #define I2S_RFR_WFP_MASK                         (0x3F0000U)
56641 #define I2S_RFR_WFP_SHIFT                        (16U)
56642 /*! WFP - Write FIFO Pointer
56643  */
56644 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
56645 /*! @} */
56646 
56647 /* The count of I2S_RFR */
56648 #define I2S_RFR_COUNT                            (4U)
56649 
56650 /*! @name RMR - Receive Mask */
56651 /*! @{ */
56652 
56653 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
56654 #define I2S_RMR_RWM_SHIFT                        (0U)
56655 /*! RWM - Receive Word Mask
56656  *  0b00000000000000000000000000000000..Word N is enabled.
56657  *  0b00000000000000000000000000000001..Word N is masked.
56658  */
56659 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
56660 /*! @} */
56661 
56662 
56663 /*!
56664  * @}
56665  */ /* end of group I2S_Register_Masks */
56666 
56667 
56668 /* I2S - Peripheral instance base addresses */
56669 /** Peripheral SAI1 base address */
56670 #define SAI1_BASE                                (0x40404000u)
56671 /** Peripheral SAI1 base pointer */
56672 #define SAI1                                     ((I2S_Type *)SAI1_BASE)
56673 /** Peripheral SAI2 base address */
56674 #define SAI2_BASE                                (0x40408000u)
56675 /** Peripheral SAI2 base pointer */
56676 #define SAI2                                     ((I2S_Type *)SAI2_BASE)
56677 /** Peripheral SAI3 base address */
56678 #define SAI3_BASE                                (0x4040C000u)
56679 /** Peripheral SAI3 base pointer */
56680 #define SAI3                                     ((I2S_Type *)SAI3_BASE)
56681 /** Peripheral SAI4 base address */
56682 #define SAI4_BASE                                (0x40C40000u)
56683 /** Peripheral SAI4 base pointer */
56684 #define SAI4                                     ((I2S_Type *)SAI4_BASE)
56685 /** Array initializer of I2S peripheral base addresses */
56686 #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
56687 /** Array initializer of I2S peripheral base pointers */
56688 #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
56689 /** Interrupt vectors for the I2S peripheral type */
56690 #define I2S_RX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
56691 #define I2S_TX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
56692 
56693 /*!
56694  * @}
56695  */ /* end of group I2S_Peripheral_Access_Layer */
56696 
56697 
56698 /* ----------------------------------------------------------------------------
56699    -- IEE Peripheral Access Layer
56700    ---------------------------------------------------------------------------- */
56701 
56702 /*!
56703  * @addtogroup IEE_Peripheral_Access_Layer IEE Peripheral Access Layer
56704  * @{
56705  */
56706 
56707 /** IEE - Register Layout Typedef */
56708 typedef struct {
56709   __IO uint32_t GCFG;                              /**< IEE Global Configuration, offset: 0x0 */
56710   __I  uint32_t STA;                               /**< IEE Status, offset: 0x4 */
56711   __IO uint32_t TSTMD;                             /**< IEE Test Mode Register, offset: 0x8 */
56712   __O  uint32_t DPAMS;                             /**< AES Mask Generation Seed, offset: 0xC */
56713        uint8_t RESERVED_0[16];
56714   __IO uint32_t PC_S_LT;                           /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */
56715   __IO uint32_t PC_M_LT;                           /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */
56716        uint8_t RESERVED_1[24];
56717   __IO uint32_t PC_BLK_ENC;                        /**< Performance Counter, Number of AES Block Encryptions, offset: 0x40 */
56718   __IO uint32_t PC_BLK_DEC;                        /**< Performance Counter, Number of AES Block Decryptions, offset: 0x44 */
56719        uint8_t RESERVED_2[8];
56720   __IO uint32_t PC_SR_TRANS;                       /**< Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50 */
56721   __IO uint32_t PC_SW_TRANS;                       /**< Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54 */
56722   __IO uint32_t PC_MR_TRANS;                       /**< Performance Counter, Number of AXI Master Read Transactions, offset: 0x58 */
56723   __IO uint32_t PC_MW_TRANS;                       /**< Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C */
56724        uint8_t RESERVED_3[4];
56725   __IO uint32_t PC_M_MBR;                          /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */
56726        uint8_t RESERVED_4[8];
56727   __IO uint32_t PC_SR_TBC_U;                       /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */
56728   __IO uint32_t PC_SR_TBC_L;                       /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */
56729   __IO uint32_t PC_SW_TBC_U;                       /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */
56730   __IO uint32_t PC_SW_TBC_L;                       /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */
56731   __IO uint32_t PC_MR_TBC_U;                       /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */
56732   __IO uint32_t PC_MR_TBC_L;                       /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */
56733   __IO uint32_t PC_MW_TBC_U;                       /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */
56734   __IO uint32_t PC_MW_TBC_L;                       /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */
56735   __IO uint32_t PC_SR_TLGTT;                       /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */
56736   __IO uint32_t PC_SW_TLGTT;                       /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */
56737   __IO uint32_t PC_MR_TLGTT;                       /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */
56738   __IO uint32_t PC_MW_TLGTT;                       /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */
56739   __IO uint32_t PC_SR_TLAT_U;                      /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */
56740   __IO uint32_t PC_SR_TLAT_L;                      /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */
56741   __IO uint32_t PC_SW_TLAT_U;                      /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */
56742   __IO uint32_t PC_SW_TLAT_L;                      /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */
56743   __IO uint32_t PC_MR_TLAT_U;                      /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */
56744   __IO uint32_t PC_MR_TLAT_L;                      /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */
56745   __IO uint32_t PC_MW_TLAT_U;                      /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */
56746   __IO uint32_t PC_MW_TLAT_L;                      /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */
56747   __IO uint32_t PC_SR_TNRT_U;                      /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */
56748   __IO uint32_t PC_SR_TNRT_L;                      /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */
56749   __IO uint32_t PC_SW_TNRT_U;                      /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */
56750   __IO uint32_t PC_SW_TNRT_L;                      /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */
56751        uint8_t RESERVED_5[32];
56752   __I  uint32_t VIDR1;                             /**< IEE Version ID Register 1, offset: 0xF0 */
56753        uint8_t RESERVED_6[4];
56754   __I  uint32_t AESVID;                            /**< IEE AES Version ID Register, offset: 0xF8 */
56755        uint8_t RESERVED_7[4];
56756   struct {                                         /* offset: 0x100, array step: 0x100 */
56757     __IO uint32_t REGATTR;                           /**< IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100 */
56758          uint8_t RESERVED_0[4];
56759     __IO uint32_t REGPO;                             /**< IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100 */
56760          uint8_t RESERVED_1[52];
56761     __O  uint32_t REGKEY1[8];                        /**< IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4 */
56762          uint8_t RESERVED_2[32];
56763     __O  uint32_t REGKEY2[8];                        /**< IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4 */
56764          uint8_t RESERVED_3[96];
56765   } REGX[8];
56766        uint8_t RESERVED_8[1536];
56767   __IO uint32_t AES_TST_DB[32];                    /**< IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4 */
56768 } IEE_Type;
56769 
56770 /* ----------------------------------------------------------------------------
56771    -- IEE Register Masks
56772    ---------------------------------------------------------------------------- */
56773 
56774 /*!
56775  * @addtogroup IEE_Register_Masks IEE Register Masks
56776  * @{
56777  */
56778 
56779 /*! @name GCFG - IEE Global Configuration */
56780 /*! @{ */
56781 
56782 #define IEE_GCFG_RL0_MASK                        (0x1U)
56783 #define IEE_GCFG_RL0_SHIFT                       (0U)
56784 /*! RL0
56785  *  0b0..Unlocked.
56786  *  0b1..Key, Offset and Attribute registers are locked.
56787  */
56788 #define IEE_GCFG_RL0(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
56789 
56790 #define IEE_GCFG_RL1_MASK                        (0x2U)
56791 #define IEE_GCFG_RL1_SHIFT                       (1U)
56792 /*! RL1
56793  *  0b0..Unlocked.
56794  *  0b1..Key, Offset and Attribute registers are locked.
56795  */
56796 #define IEE_GCFG_RL1(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
56797 
56798 #define IEE_GCFG_RL2_MASK                        (0x4U)
56799 #define IEE_GCFG_RL2_SHIFT                       (2U)
56800 /*! RL2
56801  *  0b0..Unlocked.
56802  *  0b1..Key, Offset and Attribute registers are locked.
56803  */
56804 #define IEE_GCFG_RL2(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
56805 
56806 #define IEE_GCFG_RL3_MASK                        (0x8U)
56807 #define IEE_GCFG_RL3_SHIFT                       (3U)
56808 /*! RL3
56809  *  0b0..Unlocked.
56810  *  0b1..Key, Offset and Attribute registers are locked.
56811  */
56812 #define IEE_GCFG_RL3(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
56813 
56814 #define IEE_GCFG_RL4_MASK                        (0x10U)
56815 #define IEE_GCFG_RL4_SHIFT                       (4U)
56816 /*! RL4
56817  *  0b0..Unlocked.
56818  *  0b1..Key, Offset and Attribute registers are locked.
56819  */
56820 #define IEE_GCFG_RL4(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
56821 
56822 #define IEE_GCFG_RL5_MASK                        (0x20U)
56823 #define IEE_GCFG_RL5_SHIFT                       (5U)
56824 /*! RL5
56825  *  0b0..Unlocked.
56826  *  0b1..Key, Offset and Attribute registers are locked.
56827  */
56828 #define IEE_GCFG_RL5(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
56829 
56830 #define IEE_GCFG_RL6_MASK                        (0x40U)
56831 #define IEE_GCFG_RL6_SHIFT                       (6U)
56832 /*! RL6
56833  *  0b0..Unlocked.
56834  *  0b1..Key, Offset and Attribute registers are locked.
56835  */
56836 #define IEE_GCFG_RL6(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
56837 
56838 #define IEE_GCFG_RL7_MASK                        (0x80U)
56839 #define IEE_GCFG_RL7_SHIFT                       (7U)
56840 /*! RL7
56841  *  0b0..Unlocked.
56842  *  0b1..Key, Offset and Attribute registers are locked.
56843  */
56844 #define IEE_GCFG_RL7(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
56845 
56846 #define IEE_GCFG_TME_MASK                        (0x10000U)
56847 #define IEE_GCFG_TME_SHIFT                       (16U)
56848 /*! TME
56849  *  0b0..Disabled.
56850  *  0b1..Enabled.
56851  */
56852 #define IEE_GCFG_TME(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
56853 
56854 #define IEE_GCFG_TMD_MASK                        (0x20000U)
56855 #define IEE_GCFG_TMD_SHIFT                       (17U)
56856 /*! TMD
56857  *  0b0..Test mode is usable.
56858  *  0b1..Test mode is disabled.
56859  */
56860 #define IEE_GCFG_TMD(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
56861 
56862 #define IEE_GCFG_KEY_RD_DIS_MASK                 (0x2000000U)
56863 #define IEE_GCFG_KEY_RD_DIS_SHIFT                (25U)
56864 /*! KEY_RD_DIS
56865  *  0b0..Key read enabled. Reading the key registers is allowed.
56866  *  0b1..Key read disabled. Reading the key registers is disabled.
56867  */
56868 #define IEE_GCFG_KEY_RD_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
56869 
56870 #define IEE_GCFG_MON_EN_MASK                     (0x10000000U)
56871 #define IEE_GCFG_MON_EN_SHIFT                    (28U)
56872 /*! MON_EN
56873  *  0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled.
56874  *  0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.
56875  */
56876 #define IEE_GCFG_MON_EN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
56877 
56878 #define IEE_GCFG_CLR_MON_MASK                    (0x20000000U)
56879 #define IEE_GCFG_CLR_MON_SHIFT                   (29U)
56880 /*! CLR_MON
56881  *  0b0..Do not reset.
56882  *  0b1..Reset performance counters.
56883  */
56884 #define IEE_GCFG_CLR_MON(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
56885 
56886 #define IEE_GCFG_RST_MASK                        (0x80000000U)
56887 #define IEE_GCFG_RST_SHIFT                       (31U)
56888 /*! RST
56889  *  0b0..Do Not Reset.
56890  *  0b1..Reset IEE.
56891  */
56892 #define IEE_GCFG_RST(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
56893 /*! @} */
56894 
56895 /*! @name STA - IEE Status */
56896 /*! @{ */
56897 
56898 #define IEE_STA_DSR_MASK                         (0x1U)
56899 #define IEE_STA_DSR_SHIFT                        (0U)
56900 /*! DSR
56901  *  0b0..No seed request present
56902  *  0b1..Seed request present
56903  */
56904 #define IEE_STA_DSR(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
56905 
56906 #define IEE_STA_AFD_MASK                         (0x10U)
56907 #define IEE_STA_AFD_SHIFT                        (4U)
56908 /*! AFD
56909  *  0b0..No fault detected
56910  *  0b1..Fault detected
56911  */
56912 #define IEE_STA_AFD(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
56913 /*! @} */
56914 
56915 /*! @name TSTMD - IEE Test Mode Register */
56916 /*! @{ */
56917 
56918 #define IEE_TSTMD_TMRDY_MASK                     (0x1U)
56919 #define IEE_TSTMD_TMRDY_SHIFT                    (0U)
56920 /*! TMRDY
56921  *  0b0..Not Ready.
56922  *  0b1..Ready.
56923  */
56924 #define IEE_TSTMD_TMRDY(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
56925 
56926 #define IEE_TSTMD_TMR_MASK                       (0x2U)
56927 #define IEE_TSTMD_TMR_SHIFT                      (1U)
56928 /*! TMR
56929  *  0b0..Not running. May be written if IEE_GCFG[TME] = 1
56930  *  0b1..Run AES Test until TMDONE is indicated.
56931  */
56932 #define IEE_TSTMD_TMR(x)                         (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
56933 
56934 #define IEE_TSTMD_TMENCR_MASK                    (0x4U)
56935 #define IEE_TSTMD_TMENCR_SHIFT                   (2U)
56936 /*! TMENCR
56937  *  0b0..AES Test mode will do decryption.
56938  *  0b1..AES Test mode will do encryption.
56939  */
56940 #define IEE_TSTMD_TMENCR(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
56941 
56942 #define IEE_TSTMD_TMCONT_MASK                    (0x8U)
56943 #define IEE_TSTMD_TMCONT_SHIFT                   (3U)
56944 /*! TMCONT
56945  *  0b0..Do not continue. This is the last block of data for AES.
56946  *  0b1..Continue. Do not initialize AES after this block.
56947  */
56948 #define IEE_TSTMD_TMCONT(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
56949 
56950 #define IEE_TSTMD_TMDONE_MASK                    (0x10U)
56951 #define IEE_TSTMD_TMDONE_SHIFT                   (4U)
56952 /*! TMDONE
56953  *  0b0..Not Done.
56954  *  0b1..Test Done.
56955  */
56956 #define IEE_TSTMD_TMDONE(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
56957 
56958 #define IEE_TSTMD_TMLEN_MASK                     (0xF00U)
56959 #define IEE_TSTMD_TMLEN_SHIFT                    (8U)
56960 #define IEE_TSTMD_TMLEN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
56961 /*! @} */
56962 
56963 /*! @name DPAMS - AES Mask Generation Seed */
56964 /*! @{ */
56965 
56966 #define IEE_DPAMS_DPAMS_MASK                     (0xFFFFFFFFU)
56967 #define IEE_DPAMS_DPAMS_SHIFT                    (0U)
56968 #define IEE_DPAMS_DPAMS(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
56969 /*! @} */
56970 
56971 /*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */
56972 /*! @{ */
56973 
56974 #define IEE_PC_S_LT_SW_LT_MASK                   (0xFFFFU)
56975 #define IEE_PC_S_LT_SW_LT_SHIFT                  (0U)
56976 #define IEE_PC_S_LT_SW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
56977 
56978 #define IEE_PC_S_LT_SR_LT_MASK                   (0xFFFF0000U)
56979 #define IEE_PC_S_LT_SR_LT_SHIFT                  (16U)
56980 #define IEE_PC_S_LT_SR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
56981 /*! @} */
56982 
56983 /*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */
56984 /*! @{ */
56985 
56986 #define IEE_PC_M_LT_MW_LT_MASK                   (0xFFFU)
56987 #define IEE_PC_M_LT_MW_LT_SHIFT                  (0U)
56988 #define IEE_PC_M_LT_MW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
56989 
56990 #define IEE_PC_M_LT_MR_LT_MASK                   (0xFFF0000U)
56991 #define IEE_PC_M_LT_MR_LT_SHIFT                  (16U)
56992 #define IEE_PC_M_LT_MR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
56993 /*! @} */
56994 
56995 /*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */
56996 /*! @{ */
56997 
56998 #define IEE_PC_BLK_ENC_BLK_ENC_MASK              (0xFFFFFFFFU)
56999 #define IEE_PC_BLK_ENC_BLK_ENC_SHIFT             (0U)
57000 #define IEE_PC_BLK_ENC_BLK_ENC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
57001 /*! @} */
57002 
57003 /*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */
57004 /*! @{ */
57005 
57006 #define IEE_PC_BLK_DEC_BLK_DEC_MASK              (0xFFFFFFFFU)
57007 #define IEE_PC_BLK_DEC_BLK_DEC_SHIFT             (0U)
57008 #define IEE_PC_BLK_DEC_BLK_DEC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
57009 /*! @} */
57010 
57011 /*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */
57012 /*! @{ */
57013 
57014 #define IEE_PC_SR_TRANS_SR_TRANS_MASK            (0xFFFFFFFFU)
57015 #define IEE_PC_SR_TRANS_SR_TRANS_SHIFT           (0U)
57016 #define IEE_PC_SR_TRANS_SR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
57017 /*! @} */
57018 
57019 /*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */
57020 /*! @{ */
57021 
57022 #define IEE_PC_SW_TRANS_SW_TRANS_MASK            (0xFFFFFFFFU)
57023 #define IEE_PC_SW_TRANS_SW_TRANS_SHIFT           (0U)
57024 #define IEE_PC_SW_TRANS_SW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
57025 /*! @} */
57026 
57027 /*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */
57028 /*! @{ */
57029 
57030 #define IEE_PC_MR_TRANS_MR_TRANS_MASK            (0xFFFFFFFFU)
57031 #define IEE_PC_MR_TRANS_MR_TRANS_SHIFT           (0U)
57032 #define IEE_PC_MR_TRANS_MR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
57033 /*! @} */
57034 
57035 /*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */
57036 /*! @{ */
57037 
57038 #define IEE_PC_MW_TRANS_MW_TRANS_MASK            (0xFFFFFFFFU)
57039 #define IEE_PC_MW_TRANS_MW_TRANS_SHIFT           (0U)
57040 #define IEE_PC_MW_TRANS_MW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
57041 /*! @} */
57042 
57043 /*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */
57044 /*! @{ */
57045 
57046 #define IEE_PC_M_MBR_M_MBR_MASK                  (0xFFFFFFFFU)
57047 #define IEE_PC_M_MBR_M_MBR_SHIFT                 (0U)
57048 #define IEE_PC_M_MBR_M_MBR(x)                    (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
57049 /*! @} */
57050 
57051 /*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */
57052 /*! @{ */
57053 
57054 #define IEE_PC_SR_TBC_U_SR_TBC_MASK              (0xFFFFU)
57055 #define IEE_PC_SR_TBC_U_SR_TBC_SHIFT             (0U)
57056 #define IEE_PC_SR_TBC_U_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
57057 /*! @} */
57058 
57059 /*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */
57060 /*! @{ */
57061 
57062 #define IEE_PC_SR_TBC_L_SR_TBC_MASK              (0xFFFFFFFFU)
57063 #define IEE_PC_SR_TBC_L_SR_TBC_SHIFT             (0U)
57064 #define IEE_PC_SR_TBC_L_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
57065 /*! @} */
57066 
57067 /*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */
57068 /*! @{ */
57069 
57070 #define IEE_PC_SW_TBC_U_SW_TBC_MASK              (0xFFFFU)
57071 #define IEE_PC_SW_TBC_U_SW_TBC_SHIFT             (0U)
57072 #define IEE_PC_SW_TBC_U_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
57073 /*! @} */
57074 
57075 /*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */
57076 /*! @{ */
57077 
57078 #define IEE_PC_SW_TBC_L_SW_TBC_MASK              (0xFFFFFFFFU)
57079 #define IEE_PC_SW_TBC_L_SW_TBC_SHIFT             (0U)
57080 #define IEE_PC_SW_TBC_L_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
57081 /*! @} */
57082 
57083 /*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */
57084 /*! @{ */
57085 
57086 #define IEE_PC_MR_TBC_U_MR_TBC_MASK              (0xFFFFU)
57087 #define IEE_PC_MR_TBC_U_MR_TBC_SHIFT             (0U)
57088 #define IEE_PC_MR_TBC_U_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
57089 /*! @} */
57090 
57091 /*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */
57092 /*! @{ */
57093 
57094 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK          (0xFU)
57095 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT         (0U)
57096 #define IEE_PC_MR_TBC_L_MR_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
57097 
57098 #define IEE_PC_MR_TBC_L_MR_TBC_MASK              (0xFFFFFFF0U)
57099 #define IEE_PC_MR_TBC_L_MR_TBC_SHIFT             (4U)
57100 #define IEE_PC_MR_TBC_L_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
57101 /*! @} */
57102 
57103 /*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */
57104 /*! @{ */
57105 
57106 #define IEE_PC_MW_TBC_U_MW_TBC_MASK              (0xFFFFU)
57107 #define IEE_PC_MW_TBC_U_MW_TBC_SHIFT             (0U)
57108 #define IEE_PC_MW_TBC_U_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
57109 /*! @} */
57110 
57111 /*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */
57112 /*! @{ */
57113 
57114 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK          (0xFU)
57115 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT         (0U)
57116 #define IEE_PC_MW_TBC_L_MW_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
57117 
57118 #define IEE_PC_MW_TBC_L_MW_TBC_MASK              (0xFFFFFFF0U)
57119 #define IEE_PC_MW_TBC_L_MW_TBC_SHIFT             (4U)
57120 #define IEE_PC_MW_TBC_L_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
57121 /*! @} */
57122 
57123 /*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */
57124 /*! @{ */
57125 
57126 #define IEE_PC_SR_TLGTT_SR_TLGTT_MASK            (0xFFFFFFFFU)
57127 #define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT           (0U)
57128 #define IEE_PC_SR_TLGTT_SR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
57129 /*! @} */
57130 
57131 /*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */
57132 /*! @{ */
57133 
57134 #define IEE_PC_SW_TLGTT_SW_TLGTT_MASK            (0xFFFFFFFFU)
57135 #define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT           (0U)
57136 #define IEE_PC_SW_TLGTT_SW_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
57137 /*! @} */
57138 
57139 /*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */
57140 /*! @{ */
57141 
57142 #define IEE_PC_MR_TLGTT_MR_TLGTT_MASK            (0xFFFFFFFFU)
57143 #define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT           (0U)
57144 #define IEE_PC_MR_TLGTT_MR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
57145 /*! @} */
57146 
57147 /*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */
57148 /*! @{ */
57149 
57150 #define IEE_PC_MW_TLGTT_MW_TGTT_MASK             (0xFFFFFFFFU)
57151 #define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT            (0U)
57152 #define IEE_PC_MW_TLGTT_MW_TGTT(x)               (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
57153 /*! @} */
57154 
57155 /*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */
57156 /*! @{ */
57157 
57158 #define IEE_PC_SR_TLAT_U_SR_TLAT_MASK            (0xFFFFU)
57159 #define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT           (0U)
57160 #define IEE_PC_SR_TLAT_U_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
57161 /*! @} */
57162 
57163 /*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */
57164 /*! @{ */
57165 
57166 #define IEE_PC_SR_TLAT_L_SR_TLAT_MASK            (0xFFFFFFFFU)
57167 #define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT           (0U)
57168 #define IEE_PC_SR_TLAT_L_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
57169 /*! @} */
57170 
57171 /*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */
57172 /*! @{ */
57173 
57174 #define IEE_PC_SW_TLAT_U_SW_TLAT_MASK            (0xFFFFU)
57175 #define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT           (0U)
57176 #define IEE_PC_SW_TLAT_U_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
57177 /*! @} */
57178 
57179 /*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */
57180 /*! @{ */
57181 
57182 #define IEE_PC_SW_TLAT_L_SW_TLAT_MASK            (0xFFFFFFFFU)
57183 #define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT           (0U)
57184 #define IEE_PC_SW_TLAT_L_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
57185 /*! @} */
57186 
57187 /*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */
57188 /*! @{ */
57189 
57190 #define IEE_PC_MR_TLAT_U_MR_TLAT_MASK            (0xFFFFU)
57191 #define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT           (0U)
57192 #define IEE_PC_MR_TLAT_U_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
57193 /*! @} */
57194 
57195 /*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */
57196 /*! @{ */
57197 
57198 #define IEE_PC_MR_TLAT_L_MR_TLAT_MASK            (0xFFFFFFFFU)
57199 #define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT           (0U)
57200 #define IEE_PC_MR_TLAT_L_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
57201 /*! @} */
57202 
57203 /*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */
57204 /*! @{ */
57205 
57206 #define IEE_PC_MW_TLAT_U_MW_TLAT_MASK            (0xFFFFU)
57207 #define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT           (0U)
57208 #define IEE_PC_MW_TLAT_U_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
57209 /*! @} */
57210 
57211 /*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */
57212 /*! @{ */
57213 
57214 #define IEE_PC_MW_TLAT_L_MW_TLAT_MASK            (0xFFFFFFFFU)
57215 #define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT           (0U)
57216 #define IEE_PC_MW_TLAT_L_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
57217 /*! @} */
57218 
57219 /*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */
57220 /*! @{ */
57221 
57222 #define IEE_PC_SR_TNRT_U_SR_TNRT_MASK            (0xFFFFU)
57223 #define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT           (0U)
57224 #define IEE_PC_SR_TNRT_U_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
57225 /*! @} */
57226 
57227 /*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */
57228 /*! @{ */
57229 
57230 #define IEE_PC_SR_TNRT_L_SR_TNRT_MASK            (0xFFFFFFFFU)
57231 #define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT           (0U)
57232 #define IEE_PC_SR_TNRT_L_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
57233 /*! @} */
57234 
57235 /*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */
57236 /*! @{ */
57237 
57238 #define IEE_PC_SW_TNRT_U_SW_TNRT_MASK            (0xFFFFU)
57239 #define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT           (0U)
57240 #define IEE_PC_SW_TNRT_U_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
57241 /*! @} */
57242 
57243 /*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */
57244 /*! @{ */
57245 
57246 #define IEE_PC_SW_TNRT_L_SW_TNRT_MASK            (0xFFFFFFFFU)
57247 #define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT           (0U)
57248 #define IEE_PC_SW_TNRT_L_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
57249 /*! @} */
57250 
57251 /*! @name VIDR1 - IEE Version ID Register 1 */
57252 /*! @{ */
57253 
57254 #define IEE_VIDR1_MIN_REV_MASK                   (0xFFU)
57255 #define IEE_VIDR1_MIN_REV_SHIFT                  (0U)
57256 #define IEE_VIDR1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
57257 
57258 #define IEE_VIDR1_MAJ_REV_MASK                   (0xFF00U)
57259 #define IEE_VIDR1_MAJ_REV_SHIFT                  (8U)
57260 #define IEE_VIDR1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
57261 
57262 #define IEE_VIDR1_IP_ID_MASK                     (0xFFFF0000U)
57263 #define IEE_VIDR1_IP_ID_SHIFT                    (16U)
57264 #define IEE_VIDR1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
57265 /*! @} */
57266 
57267 /*! @name AESVID - IEE AES Version ID Register */
57268 /*! @{ */
57269 
57270 #define IEE_AESVID_AESRN_MASK                    (0xFU)
57271 #define IEE_AESVID_AESRN_SHIFT                   (0U)
57272 #define IEE_AESVID_AESRN(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
57273 
57274 #define IEE_AESVID_AESVID_MASK                   (0xF0U)
57275 #define IEE_AESVID_AESVID_SHIFT                  (4U)
57276 #define IEE_AESVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
57277 /*! @} */
57278 
57279 /*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */
57280 /*! @{ */
57281 
57282 #define IEE_REGATTR_KS_MASK                      (0x1U)
57283 #define IEE_REGATTR_KS_SHIFT                     (0U)
57284 /*! KS
57285  *  0b0..128 bits (CTR), 256 bits (XTS).
57286  *  0b1..256 bits (CTR), 512 bits (XTS).
57287  */
57288 #define IEE_REGATTR_KS(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
57289 
57290 #define IEE_REGATTR_MD_MASK                      (0x70U)
57291 #define IEE_REGATTR_MD_SHIFT                     (4U)
57292 /*! MD
57293  *  0b000..None (AXI error if accessed)
57294  *  0b001..XTS
57295  *  0b010..CTR w/ address binding
57296  *  0b011..CTR w/o address binding
57297  *  0b100..CTR keystream only
57298  *  0b101..Undefined, AXI error if used
57299  *  0b110..Undefined, AXI error if used
57300  *  0b111..Undefined, AXI error if used
57301  */
57302 #define IEE_REGATTR_MD(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
57303 
57304 #define IEE_REGATTR_BYP_MASK                     (0x80U)
57305 #define IEE_REGATTR_BYP_SHIFT                    (7U)
57306 /*! BYP
57307  *  0b0..use MD field
57308  *  0b1..Bypass AES, no encrypt/decrypt
57309  */
57310 #define IEE_REGATTR_BYP(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
57311 /*! @} */
57312 
57313 /* The count of IEE_REGATTR */
57314 #define IEE_REGATTR_COUNT                        (8U)
57315 
57316 /*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */
57317 /*! @{ */
57318 
57319 #define IEE_REGPO_PGOFF_MASK                     (0xFFFFFFU)
57320 #define IEE_REGPO_PGOFF_SHIFT                    (0U)
57321 #define IEE_REGPO_PGOFF(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
57322 /*! @} */
57323 
57324 /* The count of IEE_REGPO */
57325 #define IEE_REGPO_COUNT                          (8U)
57326 
57327 /*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */
57328 /*! @{ */
57329 
57330 #define IEE_REGKEY1_KEY1_MASK                    (0xFFFFFFFFU)
57331 #define IEE_REGKEY1_KEY1_SHIFT                   (0U)
57332 #define IEE_REGKEY1_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
57333 /*! @} */
57334 
57335 /* The count of IEE_REGKEY1 */
57336 #define IEE_REGKEY1_COUNT                        (8U)
57337 
57338 /* The count of IEE_REGKEY1 */
57339 #define IEE_REGKEY1_COUNT2                       (8U)
57340 
57341 /*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */
57342 /*! @{ */
57343 
57344 #define IEE_REGKEY2_KEY2_MASK                    (0xFFFFFFFFU)
57345 #define IEE_REGKEY2_KEY2_SHIFT                   (0U)
57346 #define IEE_REGKEY2_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
57347 /*! @} */
57348 
57349 /* The count of IEE_REGKEY2 */
57350 #define IEE_REGKEY2_COUNT                        (8U)
57351 
57352 /* The count of IEE_REGKEY2 */
57353 #define IEE_REGKEY2_COUNT2                       (8U)
57354 
57355 /*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */
57356 /*! @{ */
57357 
57358 #define IEE_AES_TST_DB_AES_TST_DB0_MASK          (0xFFFFFFFFU)
57359 #define IEE_AES_TST_DB_AES_TST_DB0_SHIFT         (0U)
57360 #define IEE_AES_TST_DB_AES_TST_DB0(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
57361 
57362 #define IEE_AES_TST_DB_AES_TST_DB1_MASK          (0xFFFFFFFFU)
57363 #define IEE_AES_TST_DB_AES_TST_DB1_SHIFT         (0U)
57364 #define IEE_AES_TST_DB_AES_TST_DB1(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
57365 
57366 #define IEE_AES_TST_DB_AES_TST_DB2_MASK          (0xFFFFFFFFU)
57367 #define IEE_AES_TST_DB_AES_TST_DB2_SHIFT         (0U)
57368 #define IEE_AES_TST_DB_AES_TST_DB2(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
57369 
57370 #define IEE_AES_TST_DB_AES_TST_DB3_MASK          (0xFFFFFFFFU)
57371 #define IEE_AES_TST_DB_AES_TST_DB3_SHIFT         (0U)
57372 #define IEE_AES_TST_DB_AES_TST_DB3(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
57373 
57374 #define IEE_AES_TST_DB_AES_TST_DB4_MASK          (0xFFFFFFFFU)
57375 #define IEE_AES_TST_DB_AES_TST_DB4_SHIFT         (0U)
57376 #define IEE_AES_TST_DB_AES_TST_DB4(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
57377 
57378 #define IEE_AES_TST_DB_AES_TST_DB5_MASK          (0xFFFFFFFFU)
57379 #define IEE_AES_TST_DB_AES_TST_DB5_SHIFT         (0U)
57380 #define IEE_AES_TST_DB_AES_TST_DB5(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
57381 
57382 #define IEE_AES_TST_DB_AES_TST_DB6_MASK          (0xFFFFFFFFU)
57383 #define IEE_AES_TST_DB_AES_TST_DB6_SHIFT         (0U)
57384 #define IEE_AES_TST_DB_AES_TST_DB6(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
57385 
57386 #define IEE_AES_TST_DB_AES_TST_DB7_MASK          (0xFFFFFFFFU)
57387 #define IEE_AES_TST_DB_AES_TST_DB7_SHIFT         (0U)
57388 #define IEE_AES_TST_DB_AES_TST_DB7(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
57389 
57390 #define IEE_AES_TST_DB_AES_TST_DB8_MASK          (0xFFFFFFFFU)
57391 #define IEE_AES_TST_DB_AES_TST_DB8_SHIFT         (0U)
57392 #define IEE_AES_TST_DB_AES_TST_DB8(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
57393 
57394 #define IEE_AES_TST_DB_AES_TST_DB9_MASK          (0xFFFFFFFFU)
57395 #define IEE_AES_TST_DB_AES_TST_DB9_SHIFT         (0U)
57396 #define IEE_AES_TST_DB_AES_TST_DB9(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
57397 
57398 #define IEE_AES_TST_DB_AES_TST_DB10_MASK         (0xFFFFFFFFU)
57399 #define IEE_AES_TST_DB_AES_TST_DB10_SHIFT        (0U)
57400 #define IEE_AES_TST_DB_AES_TST_DB10(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
57401 
57402 #define IEE_AES_TST_DB_AES_TST_DB11_MASK         (0xFFFFFFFFU)
57403 #define IEE_AES_TST_DB_AES_TST_DB11_SHIFT        (0U)
57404 #define IEE_AES_TST_DB_AES_TST_DB11(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
57405 
57406 #define IEE_AES_TST_DB_AES_TST_DB12_MASK         (0xFFFFFFFFU)
57407 #define IEE_AES_TST_DB_AES_TST_DB12_SHIFT        (0U)
57408 #define IEE_AES_TST_DB_AES_TST_DB12(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
57409 
57410 #define IEE_AES_TST_DB_AES_TST_DB13_MASK         (0xFFFFFFFFU)
57411 #define IEE_AES_TST_DB_AES_TST_DB13_SHIFT        (0U)
57412 #define IEE_AES_TST_DB_AES_TST_DB13(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
57413 
57414 #define IEE_AES_TST_DB_AES_TST_DB14_MASK         (0xFFFFFFFFU)
57415 #define IEE_AES_TST_DB_AES_TST_DB14_SHIFT        (0U)
57416 #define IEE_AES_TST_DB_AES_TST_DB14(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
57417 
57418 #define IEE_AES_TST_DB_AES_TST_DB15_MASK         (0xFFFFFFFFU)
57419 #define IEE_AES_TST_DB_AES_TST_DB15_SHIFT        (0U)
57420 #define IEE_AES_TST_DB_AES_TST_DB15(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
57421 
57422 #define IEE_AES_TST_DB_AES_TST_DB16_MASK         (0xFFFFFFFFU)
57423 #define IEE_AES_TST_DB_AES_TST_DB16_SHIFT        (0U)
57424 #define IEE_AES_TST_DB_AES_TST_DB16(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
57425 
57426 #define IEE_AES_TST_DB_AES_TST_DB17_MASK         (0xFFFFFFFFU)
57427 #define IEE_AES_TST_DB_AES_TST_DB17_SHIFT        (0U)
57428 #define IEE_AES_TST_DB_AES_TST_DB17(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
57429 
57430 #define IEE_AES_TST_DB_AES_TST_DB18_MASK         (0xFFFFFFFFU)
57431 #define IEE_AES_TST_DB_AES_TST_DB18_SHIFT        (0U)
57432 #define IEE_AES_TST_DB_AES_TST_DB18(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
57433 
57434 #define IEE_AES_TST_DB_AES_TST_DB19_MASK         (0xFFFFFFFFU)
57435 #define IEE_AES_TST_DB_AES_TST_DB19_SHIFT        (0U)
57436 #define IEE_AES_TST_DB_AES_TST_DB19(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
57437 
57438 #define IEE_AES_TST_DB_AES_TST_DB20_MASK         (0xFFFFFFFFU)
57439 #define IEE_AES_TST_DB_AES_TST_DB20_SHIFT        (0U)
57440 #define IEE_AES_TST_DB_AES_TST_DB20(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
57441 
57442 #define IEE_AES_TST_DB_AES_TST_DB21_MASK         (0xFFFFFFFFU)
57443 #define IEE_AES_TST_DB_AES_TST_DB21_SHIFT        (0U)
57444 #define IEE_AES_TST_DB_AES_TST_DB21(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
57445 
57446 #define IEE_AES_TST_DB_AES_TST_DB22_MASK         (0xFFFFFFFFU)
57447 #define IEE_AES_TST_DB_AES_TST_DB22_SHIFT        (0U)
57448 #define IEE_AES_TST_DB_AES_TST_DB22(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
57449 
57450 #define IEE_AES_TST_DB_AES_TST_DB23_MASK         (0xFFFFFFFFU)
57451 #define IEE_AES_TST_DB_AES_TST_DB23_SHIFT        (0U)
57452 #define IEE_AES_TST_DB_AES_TST_DB23(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
57453 
57454 #define IEE_AES_TST_DB_AES_TST_DB24_MASK         (0xFFFFFFFFU)
57455 #define IEE_AES_TST_DB_AES_TST_DB24_SHIFT        (0U)
57456 #define IEE_AES_TST_DB_AES_TST_DB24(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
57457 
57458 #define IEE_AES_TST_DB_AES_TST_DB25_MASK         (0xFFFFFFFFU)
57459 #define IEE_AES_TST_DB_AES_TST_DB25_SHIFT        (0U)
57460 #define IEE_AES_TST_DB_AES_TST_DB25(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
57461 
57462 #define IEE_AES_TST_DB_AES_TST_DB26_MASK         (0xFFFFFFFFU)
57463 #define IEE_AES_TST_DB_AES_TST_DB26_SHIFT        (0U)
57464 #define IEE_AES_TST_DB_AES_TST_DB26(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
57465 
57466 #define IEE_AES_TST_DB_AES_TST_DB27_MASK         (0xFFFFFFFFU)
57467 #define IEE_AES_TST_DB_AES_TST_DB27_SHIFT        (0U)
57468 #define IEE_AES_TST_DB_AES_TST_DB27(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
57469 
57470 #define IEE_AES_TST_DB_AES_TST_DB28_MASK         (0xFFFFFFFFU)
57471 #define IEE_AES_TST_DB_AES_TST_DB28_SHIFT        (0U)
57472 #define IEE_AES_TST_DB_AES_TST_DB28(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
57473 
57474 #define IEE_AES_TST_DB_AES_TST_DB29_MASK         (0xFFFFFFFFU)
57475 #define IEE_AES_TST_DB_AES_TST_DB29_SHIFT        (0U)
57476 #define IEE_AES_TST_DB_AES_TST_DB29(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
57477 
57478 #define IEE_AES_TST_DB_AES_TST_DB30_MASK         (0xFFFFFFFFU)
57479 #define IEE_AES_TST_DB_AES_TST_DB30_SHIFT        (0U)
57480 #define IEE_AES_TST_DB_AES_TST_DB30(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
57481 
57482 #define IEE_AES_TST_DB_AES_TST_DB31_MASK         (0xFFFFFFFFU)
57483 #define IEE_AES_TST_DB_AES_TST_DB31_SHIFT        (0U)
57484 #define IEE_AES_TST_DB_AES_TST_DB31(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
57485 /*! @} */
57486 
57487 /* The count of IEE_AES_TST_DB */
57488 #define IEE_AES_TST_DB_COUNT                     (32U)
57489 
57490 
57491 /*!
57492  * @}
57493  */ /* end of group IEE_Register_Masks */
57494 
57495 
57496 /* IEE - Peripheral instance base addresses */
57497 /** Peripheral IEE__IEE_RT1170 base address */
57498 #define IEE__IEE_RT1170_BASE                     (0x4006C000u)
57499 /** Peripheral IEE__IEE_RT1170 base pointer */
57500 #define IEE__IEE_RT1170                          ((IEE_Type *)IEE__IEE_RT1170_BASE)
57501 /** Array initializer of IEE peripheral base addresses */
57502 #define IEE_BASE_ADDRS                           { IEE__IEE_RT1170_BASE }
57503 /** Array initializer of IEE peripheral base pointers */
57504 #define IEE_BASE_PTRS                            { IEE__IEE_RT1170 }
57505 
57506 /*!
57507  * @}
57508  */ /* end of group IEE_Peripheral_Access_Layer */
57509 
57510 
57511 /* ----------------------------------------------------------------------------
57512    -- IEE_APC Peripheral Access Layer
57513    ---------------------------------------------------------------------------- */
57514 
57515 /*!
57516  * @addtogroup IEE_APC_Peripheral_Access_Layer IEE_APC Peripheral Access Layer
57517  * @{
57518  */
57519 
57520 /** IEE_APC - Register Layout Typedef */
57521 typedef struct {
57522   __IO uint32_t REGION0_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x0 */
57523   __IO uint32_t REGION0_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x4 */
57524   __IO uint32_t REGION0_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x8 */
57525   __IO uint32_t REGION0_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0xC */
57526   __IO uint32_t REGION1_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x10 */
57527   __IO uint32_t REGION1_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x14 */
57528   __IO uint32_t REGION1_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x18 */
57529   __IO uint32_t REGION1_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x1C */
57530   __IO uint32_t REGION2_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x20 */
57531   __IO uint32_t REGION2_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x24 */
57532   __IO uint32_t REGION2_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x28 */
57533   __IO uint32_t REGION2_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x2C */
57534   __IO uint32_t REGION3_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x30 */
57535   __IO uint32_t REGION3_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x34 */
57536   __IO uint32_t REGION3_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x38 */
57537   __IO uint32_t REGION3_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x3C */
57538   __IO uint32_t REGION4_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x40 */
57539   __IO uint32_t REGION4_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x44 */
57540   __IO uint32_t REGION4_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x48 */
57541   __IO uint32_t REGION4_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x4C */
57542   __IO uint32_t REGION5_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x50 */
57543   __IO uint32_t REGION5_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x54 */
57544   __IO uint32_t REGION5_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x58 */
57545   __IO uint32_t REGION5_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x5C */
57546   __IO uint32_t REGION6_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x60 */
57547   __IO uint32_t REGION6_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x64 */
57548   __IO uint32_t REGION6_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x68 */
57549   __IO uint32_t REGION6_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x6C */
57550   __IO uint32_t REGION7_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x70 */
57551   __IO uint32_t REGION7_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x74 */
57552   __IO uint32_t REGION7_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x78 */
57553   __IO uint32_t REGION7_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x7C */
57554 } IEE_APC_Type;
57555 
57556 /* ----------------------------------------------------------------------------
57557    -- IEE_APC Register Masks
57558    ---------------------------------------------------------------------------- */
57559 
57560 /*!
57561  * @addtogroup IEE_APC_Register_Masks IEE_APC Register Masks
57562  * @{
57563  */
57564 
57565 /*! @name REGION0_TOP_ADDR - End address of IEE region (n) */
57566 /*! @{ */
57567 
57568 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57569 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57570 /*! TOP_ADDR - End address of IEE region
57571  */
57572 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
57573 /*! @} */
57574 
57575 /*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */
57576 /*! @{ */
57577 
57578 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57579 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57580 /*! BOT_ADDR - Start address of IEE region
57581  */
57582 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
57583 /*! @} */
57584 
57585 /*! @name REGION0_RDC_D0 - Region control of core domain 0 for region (n) */
57586 /*! @{ */
57587 
57588 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57589 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57590 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57591  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57592  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57593  */
57594 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57595 
57596 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57597 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57598 /*! RDC_D0_LOCK - Lock bit for bit 0
57599  *  0b0..Bit 0 is unlocked
57600  *  0b1..Bit 0 is locked
57601  */
57602 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)
57603 /*! @} */
57604 
57605 /*! @name REGION0_RDC_D1 - Region control of core domain 1 for region (n) */
57606 /*! @{ */
57607 
57608 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57609 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57610 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57611  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57612  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57613  */
57614 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57615 
57616 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57617 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57618 /*! RDC_D1_LOCK - Lock bit for bit 0
57619  *  0b0..Bit 0 is unlocked
57620  *  0b1..Bit 0 is locked
57621  */
57622 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)
57623 /*! @} */
57624 
57625 /*! @name REGION1_TOP_ADDR - End address of IEE region (n) */
57626 /*! @{ */
57627 
57628 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57629 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57630 /*! TOP_ADDR - End address of IEE region
57631  */
57632 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
57633 /*! @} */
57634 
57635 /*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */
57636 /*! @{ */
57637 
57638 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57639 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57640 /*! BOT_ADDR - Start address of IEE region
57641  */
57642 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
57643 /*! @} */
57644 
57645 /*! @name REGION1_RDC_D0 - Region control of core domain 0 for region (n) */
57646 /*! @{ */
57647 
57648 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57649 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57650 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57651  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57652  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57653  */
57654 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57655 
57656 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57657 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57658 /*! RDC_D0_LOCK - Lock bit for bit 0
57659  *  0b0..Bit 0 is unlocked
57660  *  0b1..Bit 0 is locked
57661  */
57662 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)
57663 /*! @} */
57664 
57665 /*! @name REGION1_RDC_D1 - Region control of core domain 1 for region (n) */
57666 /*! @{ */
57667 
57668 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57669 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57670 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57671  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57672  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57673  */
57674 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57675 
57676 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57677 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57678 /*! RDC_D1_LOCK - Lock bit for bit 0
57679  *  0b0..Bit 0 is unlocked
57680  *  0b1..Bit 0 is locked
57681  */
57682 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)
57683 /*! @} */
57684 
57685 /*! @name REGION2_TOP_ADDR - End address of IEE region (n) */
57686 /*! @{ */
57687 
57688 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57689 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57690 /*! TOP_ADDR - End address of IEE region
57691  */
57692 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
57693 /*! @} */
57694 
57695 /*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */
57696 /*! @{ */
57697 
57698 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57699 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57700 /*! BOT_ADDR - Start address of IEE region
57701  */
57702 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
57703 /*! @} */
57704 
57705 /*! @name REGION2_RDC_D0 - Region control of core domain 0 for region (n) */
57706 /*! @{ */
57707 
57708 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57709 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57710 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57711  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57712  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57713  */
57714 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57715 
57716 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57717 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57718 /*! RDC_D0_LOCK - Lock bit for bit 0
57719  *  0b0..Bit 0 is unlocked
57720  *  0b1..Bit 0 is locked
57721  */
57722 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)
57723 /*! @} */
57724 
57725 /*! @name REGION2_RDC_D1 - Region control of core domain 1 for region (n) */
57726 /*! @{ */
57727 
57728 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57729 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57730 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57731  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57732  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57733  */
57734 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57735 
57736 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57737 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57738 /*! RDC_D1_LOCK - Lock bit for bit 0
57739  *  0b0..Bit 0 is unlocked
57740  *  0b1..Bit 0 is locked
57741  */
57742 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)
57743 /*! @} */
57744 
57745 /*! @name REGION3_TOP_ADDR - End address of IEE region (n) */
57746 /*! @{ */
57747 
57748 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57749 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57750 /*! TOP_ADDR - End address of IEE region
57751  */
57752 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
57753 /*! @} */
57754 
57755 /*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */
57756 /*! @{ */
57757 
57758 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57759 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57760 /*! BOT_ADDR - Start address of IEE region
57761  */
57762 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
57763 /*! @} */
57764 
57765 /*! @name REGION3_RDC_D0 - Region control of core domain 0 for region (n) */
57766 /*! @{ */
57767 
57768 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57769 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57770 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57771  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57772  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57773  */
57774 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57775 
57776 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57777 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57778 /*! RDC_D0_LOCK - Lock bit for bit 0
57779  *  0b0..Bit 0 is unlocked
57780  *  0b1..Bit 0 is locked
57781  */
57782 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)
57783 /*! @} */
57784 
57785 /*! @name REGION3_RDC_D1 - Region control of core domain 1 for region (n) */
57786 /*! @{ */
57787 
57788 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57789 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57790 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57791  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57792  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57793  */
57794 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57795 
57796 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57797 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57798 /*! RDC_D1_LOCK - Lock bit for bit 0
57799  *  0b0..Bit 0 is unlocked
57800  *  0b1..Bit 0 is locked
57801  */
57802 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)
57803 /*! @} */
57804 
57805 /*! @name REGION4_TOP_ADDR - End address of IEE region (n) */
57806 /*! @{ */
57807 
57808 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57809 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57810 /*! TOP_ADDR - End address of IEE region
57811  */
57812 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
57813 /*! @} */
57814 
57815 /*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */
57816 /*! @{ */
57817 
57818 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57819 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57820 /*! BOT_ADDR - Start address of IEE region
57821  */
57822 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
57823 /*! @} */
57824 
57825 /*! @name REGION4_RDC_D0 - Region control of core domain 0 for region (n) */
57826 /*! @{ */
57827 
57828 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57829 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57830 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57831  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57832  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57833  */
57834 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57835 
57836 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57837 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57838 /*! RDC_D0_LOCK - Lock bit for bit 0
57839  *  0b0..Bit 0 is unlocked
57840  *  0b1..Bit 0 is locked
57841  */
57842 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)
57843 /*! @} */
57844 
57845 /*! @name REGION4_RDC_D1 - Region control of core domain 1 for region (n) */
57846 /*! @{ */
57847 
57848 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57849 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57850 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57851  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57852  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57853  */
57854 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57855 
57856 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57857 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57858 /*! RDC_D1_LOCK - Lock bit for bit 0
57859  *  0b0..Bit 0 is unlocked
57860  *  0b1..Bit 0 is locked
57861  */
57862 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)
57863 /*! @} */
57864 
57865 /*! @name REGION5_TOP_ADDR - End address of IEE region (n) */
57866 /*! @{ */
57867 
57868 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57869 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57870 /*! TOP_ADDR - End address of IEE region
57871  */
57872 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
57873 /*! @} */
57874 
57875 /*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */
57876 /*! @{ */
57877 
57878 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57879 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57880 /*! BOT_ADDR - Start address of IEE region
57881  */
57882 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
57883 /*! @} */
57884 
57885 /*! @name REGION5_RDC_D0 - Region control of core domain 0 for region (n) */
57886 /*! @{ */
57887 
57888 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57889 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57890 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57891  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57892  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57893  */
57894 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57895 
57896 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57897 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57898 /*! RDC_D0_LOCK - Lock bit for bit 0
57899  *  0b0..Bit 0 is unlocked
57900  *  0b1..Bit 0 is locked
57901  */
57902 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)
57903 /*! @} */
57904 
57905 /*! @name REGION5_RDC_D1 - Region control of core domain 1 for region (n) */
57906 /*! @{ */
57907 
57908 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57909 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57910 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57911  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57912  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57913  */
57914 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57915 
57916 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57917 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57918 /*! RDC_D1_LOCK - Lock bit for bit 0
57919  *  0b0..Bit 0 is unlocked
57920  *  0b1..Bit 0 is locked
57921  */
57922 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)
57923 /*! @} */
57924 
57925 /*! @name REGION6_TOP_ADDR - End address of IEE region (n) */
57926 /*! @{ */
57927 
57928 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57929 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57930 /*! TOP_ADDR - End address of IEE region
57931  */
57932 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
57933 /*! @} */
57934 
57935 /*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */
57936 /*! @{ */
57937 
57938 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57939 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
57940 /*! BOT_ADDR - Start address of IEE region
57941  */
57942 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
57943 /*! @} */
57944 
57945 /*! @name REGION6_RDC_D0 - Region control of core domain 0 for region (n) */
57946 /*! @{ */
57947 
57948 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
57949 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
57950 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
57951  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57952  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57953  */
57954 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)
57955 
57956 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
57957 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
57958 /*! RDC_D0_LOCK - Lock bit for bit 0
57959  *  0b0..Bit 0 is unlocked
57960  *  0b1..Bit 0 is locked
57961  */
57962 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)
57963 /*! @} */
57964 
57965 /*! @name REGION6_RDC_D1 - Region control of core domain 1 for region (n) */
57966 /*! @{ */
57967 
57968 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
57969 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
57970 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
57971  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
57972  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
57973  */
57974 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)
57975 
57976 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
57977 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
57978 /*! RDC_D1_LOCK - Lock bit for bit 0
57979  *  0b0..Bit 0 is unlocked
57980  *  0b1..Bit 0 is locked
57981  */
57982 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)
57983 /*! @} */
57984 
57985 /*! @name REGION7_TOP_ADDR - End address of IEE region (n) */
57986 /*! @{ */
57987 
57988 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
57989 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
57990 /*! TOP_ADDR - End address of IEE region
57991  */
57992 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
57993 /*! @} */
57994 
57995 /*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */
57996 /*! @{ */
57997 
57998 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
57999 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
58000 /*! BOT_ADDR - Start address of IEE region
58001  */
58002 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
58003 /*! @} */
58004 
58005 /*! @name REGION7_RDC_D0 - Region control of core domain 0 for region (n) */
58006 /*! @{ */
58007 
58008 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
58009 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
58010 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
58011  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
58012  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
58013  */
58014 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)
58015 
58016 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
58017 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
58018 /*! RDC_D0_LOCK - Lock bit for bit 0
58019  *  0b0..Bit 0 is unlocked
58020  *  0b1..Bit 0 is locked
58021  */
58022 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)
58023 /*! @} */
58024 
58025 /*! @name REGION7_RDC_D1 - Region control of core domain 1 for region (n) */
58026 /*! @{ */
58027 
58028 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
58029 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
58030 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
58031  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
58032  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
58033  */
58034 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)
58035 
58036 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
58037 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
58038 /*! RDC_D1_LOCK - Lock bit for bit 0
58039  *  0b0..Bit 0 is unlocked
58040  *  0b1..Bit 0 is locked
58041  */
58042 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)
58043 /*! @} */
58044 
58045 
58046 /*!
58047  * @}
58048  */ /* end of group IEE_APC_Register_Masks */
58049 
58050 
58051 /* IEE_APC - Peripheral instance base addresses */
58052 /** Peripheral IEE_APC base address */
58053 #define IEE_APC_BASE                             (0x40068000u)
58054 /** Peripheral IEE_APC base pointer */
58055 #define IEE_APC                                  ((IEE_APC_Type *)IEE_APC_BASE)
58056 /** Array initializer of IEE_APC peripheral base addresses */
58057 #define IEE_APC_BASE_ADDRS                       { IEE_APC_BASE }
58058 /** Array initializer of IEE_APC peripheral base pointers */
58059 #define IEE_APC_BASE_PTRS                        { IEE_APC }
58060 
58061 /*!
58062  * @}
58063  */ /* end of group IEE_APC_Peripheral_Access_Layer */
58064 
58065 
58066 /* ----------------------------------------------------------------------------
58067    -- IOMUXC Peripheral Access Layer
58068    ---------------------------------------------------------------------------- */
58069 
58070 /*!
58071  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
58072  * @{
58073  */
58074 
58075 /** IOMUXC - Register Layout Typedef */
58076 typedef struct {
58077        uint8_t RESERVED_0[16];
58078   __IO uint32_t SW_MUX_CTL_PAD[145];               /**< SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4 */
58079   __IO uint32_t SW_PAD_CTL_PAD[145];               /**< SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4 */
58080   __IO uint32_t SELECT_INPUT[160];                 /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4 */
58081 } IOMUXC_Type;
58082 
58083 /* ----------------------------------------------------------------------------
58084    -- IOMUXC Register Masks
58085    ---------------------------------------------------------------------------- */
58086 
58087 /*!
58088  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
58089  * @{
58090  */
58091 
58092 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register */
58093 /*! @{ */
58094 
58095 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0xFU)
58096 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
58097 /*! MUX_MODE - MUX Mode Select Field.
58098  *  0b0000..Select mux mode: ALT0 mux port: SEMC_DATA16 of instance: SEMC
58099  *  0b0001..Select mux mode: ALT1 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
58100  *  0b0010..Select mux mode: ALT2 mux port: TMR3_TIMER1 of instance: TMR3
58101  *  0b0011..Select mux mode: ALT3 mux port: LPUART6_CTS_B of instance: LPUART6
58102  *  0b0100..Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA06 of instance: FLEXSPI2
58103  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX2_IO10 of instance: GPIO_MUX2
58104  *  0b0110..Select mux mode: ALT6 mux port: XBAR1_INOUT20 of instance: XBAR1
58105  *  0b0111..Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_OUT of instance: ENET_QOS
58106  *  0b1000..Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: LPSPI1
58107  *  0b1001..Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2
58108  *  0b1010..Select mux mode: ALT10 mux port: GPIO8_IO10 of instance: GPIO8
58109  *  0b1011..Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3
58110  */
58111 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
58112 
58113 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
58114 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
58115 /*! SION - Software Input On Field.
58116  *  0b1..Force input path of pad GPIO_DISP_B1_00
58117  *  0b0..Input Path is determined by functionality
58118  */
58119 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
58120 /*! @} */
58121 
58122 /* The count of IOMUXC_SW_MUX_CTL_PAD */
58123 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (145U)
58124 
58125 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register */
58126 /*! @{ */
58127 
58128 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
58129 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
58130 /*! SRE - Slew Rate Field
58131  *  0b0..Slow Slew Rate
58132  *  0b1..Fast Slew Rate
58133  */
58134 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
58135 
58136 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x2U)
58137 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (1U)
58138 /*! DSE - Drive Strength Field
58139  *  0b0..normal drive strength
58140  *  0b1..high drive strength
58141  */
58142 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
58143 
58144 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK          (0x2U)
58145 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT         (1U)
58146 /*! PDRV - PDRV Field
58147  *  0b0..high drive strength
58148  *  0b1..normal drive strength
58149  */
58150 #define IOMUXC_SW_PAD_CTL_PAD_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
58151 
58152 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x4U)
58153 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (2U)
58154 /*! PUE - Pull / Keep Select Field
58155  *  0b0..Pull Disable, Highz
58156  *  0b1..Pull Enable
58157  */
58158 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
58159 
58160 #define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK          (0xCU)
58161 #define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT         (2U)
58162 /*! PULL - Pull Down Pull Up Field
58163  *  0b00..Forbidden
58164  *  0b01..Internal pullup resistor enabled
58165  *  0b10..Internal pulldown resistor enabled
58166  *  0b11..No Pull
58167  */
58168 #define IOMUXC_SW_PAD_CTL_PAD_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
58169 
58170 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0x8U)
58171 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (3U)
58172 /*! PUS - Pull Up / Down Config. Field
58173  *  0b0..Weak pull down
58174  *  0b1..Weak pull up
58175  */
58176 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
58177 
58178 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x10U)
58179 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (4U)
58180 /*! ODE - Open Drain Field
58181  *  0b0..Disabled
58182  *  0b1..Enabled
58183  */
58184 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
58185 
58186 #define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK           (0x30000000U)
58187 #define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT          (28U)
58188 /*! DWP - Domain write protection
58189  *  0b00..Both cores are allowed
58190  *  0b01..CM7 is forbidden
58191  *  0b10..CM4 is forbidden
58192  *  0b11..Both cores are forbidden
58193  */
58194 #define IOMUXC_SW_PAD_CTL_PAD_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
58195 
58196 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK      (0xC0000000U)
58197 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT     (30U)
58198 /*! DWP_LOCK - Domain write protection lock
58199  *  0b00..Neither of DWP bits is locked
58200  *  0b01..The lower DWP bit is locked
58201  *  0b10..The higher DWP bit is locked
58202  *  0b11..Both DWP bits are locked
58203  */
58204 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
58205 /*! @} */
58206 
58207 /* The count of IOMUXC_SW_PAD_CTL_PAD */
58208 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (145U)
58209 
58210 /*! @name SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register */
58211 /*! @{ */
58212 
58213 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
58214 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
58215 /*! DAISY - Selecting Pads Involved in Daisy Chain.
58216  *  0b00..Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3
58217  *  0b01..Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3
58218  *  0b10..Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2
58219  *  0b11..Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4
58220  */
58221 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
58222 /*! @} */
58223 
58224 /* The count of IOMUXC_SELECT_INPUT */
58225 #define IOMUXC_SELECT_INPUT_COUNT                (160U)
58226 
58227 
58228 /*!
58229  * @}
58230  */ /* end of group IOMUXC_Register_Masks */
58231 
58232 
58233 /* IOMUXC - Peripheral instance base addresses */
58234 /** Peripheral IOMUXC base address */
58235 #define IOMUXC_BASE                              (0x400E8000u)
58236 /** Peripheral IOMUXC base pointer */
58237 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
58238 /** Array initializer of IOMUXC peripheral base addresses */
58239 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
58240 /** Array initializer of IOMUXC peripheral base pointers */
58241 #define IOMUXC_BASE_PTRS                         { IOMUXC }
58242 
58243 /*!
58244  * @}
58245  */ /* end of group IOMUXC_Peripheral_Access_Layer */
58246 
58247 
58248 /* ----------------------------------------------------------------------------
58249    -- IOMUXC_GPR Peripheral Access Layer
58250    ---------------------------------------------------------------------------- */
58251 
58252 /*!
58253  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
58254  * @{
58255  */
58256 
58257 /** IOMUXC_GPR - Register Layout Typedef */
58258 typedef struct {
58259   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
58260   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
58261   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
58262   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
58263   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
58264   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
58265   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
58266   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
58267   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
58268   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
58269   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
58270   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
58271   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
58272   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
58273   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
58274   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
58275   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
58276   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
58277   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
58278        uint8_t RESERVED_0[4];
58279   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
58280   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
58281   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
58282   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
58283   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
58284   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
58285   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
58286   __IO uint32_t GPR27;                             /**< GPR27 General Purpose Register, offset: 0x6C */
58287   __IO uint32_t GPR28;                             /**< GPR28 General Purpose Register, offset: 0x70 */
58288   __IO uint32_t GPR29;                             /**< GPR29 General Purpose Register, offset: 0x74 */
58289   __IO uint32_t GPR30;                             /**< GPR30 General Purpose Register, offset: 0x78 */
58290   __IO uint32_t GPR31;                             /**< GPR31 General Purpose Register, offset: 0x7C */
58291   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
58292   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
58293   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
58294   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
58295   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
58296   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
58297   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
58298   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
58299   __IO uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
58300   __IO uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
58301   __IO uint32_t GPR42;                             /**< GPR42 General Purpose Register, offset: 0xA8 */
58302   __IO uint32_t GPR43;                             /**< GPR43 General Purpose Register, offset: 0xAC */
58303   __IO uint32_t GPR44;                             /**< GPR44 General Purpose Register, offset: 0xB0 */
58304   __IO uint32_t GPR45;                             /**< GPR45 General Purpose Register, offset: 0xB4 */
58305   __IO uint32_t GPR46;                             /**< GPR46 General Purpose Register, offset: 0xB8 */
58306   __IO uint32_t GPR47;                             /**< GPR47 General Purpose Register, offset: 0xBC */
58307   __IO uint32_t GPR48;                             /**< GPR48 General Purpose Register, offset: 0xC0 */
58308   __IO uint32_t GPR49;                             /**< GPR49 General Purpose Register, offset: 0xC4 */
58309   __IO uint32_t GPR50;                             /**< GPR50 General Purpose Register, offset: 0xC8 */
58310   __IO uint32_t GPR51;                             /**< GPR51 General Purpose Register, offset: 0xCC */
58311   __IO uint32_t GPR52;                             /**< GPR52 General Purpose Register, offset: 0xD0 */
58312   __IO uint32_t GPR53;                             /**< GPR53 General Purpose Register, offset: 0xD4 */
58313   __IO uint32_t GPR54;                             /**< GPR54 General Purpose Register, offset: 0xD8 */
58314   __IO uint32_t GPR55;                             /**< GPR55 General Purpose Register, offset: 0xDC */
58315        uint8_t RESERVED_1[12];
58316   __IO uint32_t GPR59;                             /**< GPR59 General Purpose Register, offset: 0xEC */
58317        uint8_t RESERVED_2[8];
58318   __IO uint32_t GPR62;                             /**< GPR62 General Purpose Register, offset: 0xF8 */
58319   __I  uint32_t GPR63;                             /**< GPR63 General Purpose Register, offset: 0xFC */
58320   __IO uint32_t GPR64;                             /**< GPR64 General Purpose Register, offset: 0x100 */
58321   __IO uint32_t GPR65;                             /**< GPR65 General Purpose Register, offset: 0x104 */
58322   __IO uint32_t GPR66;                             /**< GPR66 General Purpose Register, offset: 0x108 */
58323   __IO uint32_t GPR67;                             /**< GPR67 General Purpose Register, offset: 0x10C */
58324   __IO uint32_t GPR68;                             /**< GPR68 General Purpose Register, offset: 0x110 */
58325   __IO uint32_t GPR69;                             /**< GPR69 General Purpose Register, offset: 0x114 */
58326   __IO uint32_t GPR70;                             /**< GPR70 General Purpose Register, offset: 0x118 */
58327   __IO uint32_t GPR71;                             /**< GPR71 General Purpose Register, offset: 0x11C */
58328   __IO uint32_t GPR72;                             /**< GPR72 General Purpose Register, offset: 0x120 */
58329   __IO uint32_t GPR73;                             /**< GPR73 General Purpose Register, offset: 0x124 */
58330   __IO uint32_t GPR74;                             /**< GPR74 General Purpose Register, offset: 0x128 */
58331   __I  uint32_t GPR75;                             /**< GPR75 General Purpose Register, offset: 0x12C */
58332   __I  uint32_t GPR76;                             /**< GPR76 General Purpose Register, offset: 0x130 */
58333 } IOMUXC_GPR_Type;
58334 
58335 /* ----------------------------------------------------------------------------
58336    -- IOMUXC_GPR Register Masks
58337    ---------------------------------------------------------------------------- */
58338 
58339 /*!
58340  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
58341  * @{
58342  */
58343 
58344 /*! @name GPR0 - GPR0 General Purpose Register */
58345 /*! @{ */
58346 
58347 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK      (0x7U)
58348 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT     (0U)
58349 /*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select
58350  */
58351 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
58352 
58353 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK      (0x38U)
58354 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT     (3U)
58355 /*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select
58356  */
58357 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
58358 
58359 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK      (0xC0U)
58360 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT     (6U)
58361 /*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select
58362  */
58363 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
58364 
58365 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK       (0x100U)
58366 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT      (8U)
58367 /*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control
58368  */
58369 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
58370 
58371 #define IOMUXC_GPR_GPR0_DWP_MASK                 (0x30000000U)
58372 #define IOMUXC_GPR_GPR0_DWP_SHIFT                (28U)
58373 /*! DWP - Domain write protection
58374  *  0b00..Both cores are allowed
58375  *  0b01..CM7 is forbidden
58376  *  0b10..CM4 is forbidden
58377  *  0b11..Both cores are forbidden
58378  */
58379 #define IOMUXC_GPR_GPR0_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
58380 
58381 #define IOMUXC_GPR_GPR0_DWP_LOCK_MASK            (0xC0000000U)
58382 #define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT           (30U)
58383 /*! DWP_LOCK - Domain write protection lock
58384  *  0b00..Neither of DWP bits is locked
58385  *  0b01..The lower DWP bit is locked
58386  *  0b10..The higher DWP bit is locked
58387  *  0b11..Both DWP bits are locked
58388  */
58389 #define IOMUXC_GPR_GPR0_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
58390 /*! @} */
58391 
58392 /*! @name GPR1 - GPR1 General Purpose Register */
58393 /*! @{ */
58394 
58395 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK      (0x3U)
58396 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT     (0U)
58397 /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select
58398  */
58399 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
58400 
58401 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK       (0x100U)
58402 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT      (8U)
58403 /*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control
58404  */
58405 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
58406 
58407 #define IOMUXC_GPR_GPR1_DWP_MASK                 (0x30000000U)
58408 #define IOMUXC_GPR_GPR1_DWP_SHIFT                (28U)
58409 /*! DWP - Domain write protection
58410  *  0b00..Both cores are allowed
58411  *  0b01..CM7 is forbidden
58412  *  0b10..CM4 is forbidden
58413  *  0b11..Both cores are forbidden
58414  */
58415 #define IOMUXC_GPR_GPR1_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
58416 
58417 #define IOMUXC_GPR_GPR1_DWP_LOCK_MASK            (0xC0000000U)
58418 #define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT           (30U)
58419 /*! DWP_LOCK - Domain write protection lock
58420  *  0b00..Neither of DWP bits is locked
58421  *  0b01..The lower DWP bit is locked
58422  *  0b10..The higher DWP bit is locked
58423  *  0b11..Both DWP bits are locked
58424  */
58425 #define IOMUXC_GPR_GPR1_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
58426 /*! @} */
58427 
58428 /*! @name GPR2 - GPR2 General Purpose Register */
58429 /*! @{ */
58430 
58431 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK      (0x3U)
58432 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT     (0U)
58433 /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select
58434  */
58435 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
58436 
58437 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK       (0x100U)
58438 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT      (8U)
58439 /*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control
58440  */
58441 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
58442 
58443 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK       (0x200U)
58444 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT      (9U)
58445 /*! SAI4_MCLK_DIR - SAI4_MCLK signal direction control
58446  */
58447 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
58448 
58449 #define IOMUXC_GPR_GPR2_DWP_MASK                 (0x30000000U)
58450 #define IOMUXC_GPR_GPR2_DWP_SHIFT                (28U)
58451 /*! DWP - Domain write protection
58452  *  0b00..Both cores are allowed
58453  *  0b01..CM7 is forbidden
58454  *  0b10..CM4 is forbidden
58455  *  0b11..Both cores are forbidden
58456  */
58457 #define IOMUXC_GPR_GPR2_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
58458 
58459 #define IOMUXC_GPR_GPR2_DWP_LOCK_MASK            (0xC0000000U)
58460 #define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT           (30U)
58461 /*! DWP_LOCK - Domain write protection lock
58462  *  0b00..Neither of DWP bits is locked
58463  *  0b01..The lower DWP bit is locked
58464  *  0b10..The higher DWP bit is locked
58465  *  0b11..Both DWP bits are locked
58466  */
58467 #define IOMUXC_GPR_GPR2_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
58468 /*! @} */
58469 
58470 /*! @name GPR3 - GPR3 General Purpose Register */
58471 /*! @{ */
58472 
58473 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK         (0xFFU)
58474 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT        (0U)
58475 /*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk.
58476  */
58477 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
58478 
58479 #define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK          (0x100U)
58480 #define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT         (8U)
58481 /*! MQS_SW_RST - MQS software reset
58482  */
58483 #define IOMUXC_GPR_GPR3_MQS_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
58484 
58485 #define IOMUXC_GPR_GPR3_MQS_EN_MASK              (0x200U)
58486 #define IOMUXC_GPR_GPR3_MQS_EN_SHIFT             (9U)
58487 /*! MQS_EN - MQS enable
58488  */
58489 #define IOMUXC_GPR_GPR3_MQS_EN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
58490 
58491 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK      (0x400U)
58492 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT     (10U)
58493 /*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample
58494  */
58495 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
58496 
58497 #define IOMUXC_GPR_GPR3_DWP_MASK                 (0x30000000U)
58498 #define IOMUXC_GPR_GPR3_DWP_SHIFT                (28U)
58499 /*! DWP - Domain write protection
58500  *  0b00..Both cores are allowed
58501  *  0b01..CM7 is forbidden
58502  *  0b10..CM4 is forbidden
58503  *  0b11..Both cores are forbidden
58504  */
58505 #define IOMUXC_GPR_GPR3_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
58506 
58507 #define IOMUXC_GPR_GPR3_DWP_LOCK_MASK            (0xC0000000U)
58508 #define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT           (30U)
58509 /*! DWP_LOCK - Domain write protection lock
58510  *  0b00..Neither of DWP bits is locked
58511  *  0b01..The lower DWP bit is locked
58512  *  0b10..The higher DWP bit is locked
58513  *  0b11..Both DWP bits are locked
58514  */
58515 #define IOMUXC_GPR_GPR3_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
58516 /*! @} */
58517 
58518 /*! @name GPR4 - GPR4 General Purpose Register */
58519 /*! @{ */
58520 
58521 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK     (0x1U)
58522 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT    (0U)
58523 /*! ENET_TX_CLK_SEL - ENET TX_CLK select
58524  */
58525 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
58526 
58527 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK    (0x2U)
58528 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
58529 /*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control
58530  */
58531 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
58532 
58533 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK       (0x4U)
58534 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT      (2U)
58535 /*! ENET_TIME_SEL - ENET master timer source select
58536  */
58537 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
58538 
58539 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
58540 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT  (3U)
58541 /*! ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select
58542  */
58543 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
58544 
58545 #define IOMUXC_GPR_GPR4_DWP_MASK                 (0x30000000U)
58546 #define IOMUXC_GPR_GPR4_DWP_SHIFT                (28U)
58547 /*! DWP - Domain write protection
58548  *  0b00..Both cores are allowed
58549  *  0b01..CM7 is forbidden
58550  *  0b10..CM4 is forbidden
58551  *  0b11..Both cores are forbidden
58552  */
58553 #define IOMUXC_GPR_GPR4_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
58554 
58555 #define IOMUXC_GPR_GPR4_DWP_LOCK_MASK            (0xC0000000U)
58556 #define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT           (30U)
58557 /*! DWP_LOCK - Domain write protection lock
58558  *  0b00..Neither of DWP bits is locked
58559  *  0b01..The lower DWP bit is locked
58560  *  0b10..The higher DWP bit is locked
58561  *  0b11..Both DWP bits are locked
58562  */
58563 #define IOMUXC_GPR_GPR4_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
58564 /*! @} */
58565 
58566 /*! @name GPR5 - GPR5 General Purpose Register */
58567 /*! @{ */
58568 
58569 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
58570 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT  (0U)
58571 /*! ENET1G_TX_CLK_SEL - ENET1G TX_CLK select
58572  */
58573 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
58574 
58575 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK  (0x2U)
58576 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U)
58577 /*! ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control
58578  */
58579 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
58580 
58581 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK     (0x4U)
58582 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT    (2U)
58583 /*! ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable
58584  */
58585 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
58586 
58587 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK     (0x8U)
58588 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT    (3U)
58589 /*! ENET1G_TIME_SEL - ENET1G master timer source select
58590  */
58591 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
58592 
58593 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U)
58594 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U)
58595 /*! ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select
58596  */
58597 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
58598 
58599 #define IOMUXC_GPR_GPR5_DWP_MASK                 (0x30000000U)
58600 #define IOMUXC_GPR_GPR5_DWP_SHIFT                (28U)
58601 /*! DWP - Domain write protection
58602  *  0b00..Both cores are allowed
58603  *  0b01..CM7 is forbidden
58604  *  0b10..CM4 is forbidden
58605  *  0b11..Both cores are forbidden
58606  */
58607 #define IOMUXC_GPR_GPR5_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
58608 
58609 #define IOMUXC_GPR_GPR5_DWP_LOCK_MASK            (0xC0000000U)
58610 #define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT           (30U)
58611 /*! DWP_LOCK - Domain write protection lock
58612  *  0b00..Neither of DWP bits is locked
58613  *  0b01..The lower DWP bit is locked
58614  *  0b10..The higher DWP bit is locked
58615  *  0b11..Both DWP bits are locked
58616  */
58617 #define IOMUXC_GPR_GPR5_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
58618 /*! @} */
58619 
58620 /*! @name GPR6 - GPR6 General Purpose Register */
58621 /*! @{ */
58622 
58623 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK (0x1U)
58624 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT (0U)
58625 /*! ENET_QOS_REF_CLK_DIR - ENET_QOS_REF_CLK direction control
58626  */
58627 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK)
58628 
58629 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK   (0x2U)
58630 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT  (1U)
58631 /*! ENET_QOS_RGMII_EN - ENET_QOS RGMII TX clock output enable
58632  */
58633 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK)
58634 
58635 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK   (0x4U)
58636 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT  (2U)
58637 /*! ENET_QOS_TIME_SEL - ENET_QOS master timer source select
58638  */
58639 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK)
58640 
58641 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK   (0x38U)
58642 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT  (3U)
58643 /*! ENET_QOS_INTF_SEL - ENET_QOS PHY Interface Select
58644  */
58645 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK)
58646 
58647 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK  (0x40U)
58648 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT (6U)
58649 /*! ENET_QOS_CLKGEN_EN - ENET_QOS clock generator enable
58650  */
58651 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK)
58652 
58653 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK (0x80U)
58654 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT (7U)
58655 /*! ENET_QOS_EVENT0IN_SEL - ENET_QOS ENET_1588_EVENT0_IN source select
58656  */
58657 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK)
58658 
58659 #define IOMUXC_GPR_GPR6_DWP_MASK                 (0x30000000U)
58660 #define IOMUXC_GPR_GPR6_DWP_SHIFT                (28U)
58661 /*! DWP - Domain write protection
58662  *  0b00..Both cores are allowed
58663  *  0b01..CM7 is forbidden
58664  *  0b10..CM4 is forbidden
58665  *  0b11..Both cores are forbidden
58666  */
58667 #define IOMUXC_GPR_GPR6_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_SHIFT)) & IOMUXC_GPR_GPR6_DWP_MASK)
58668 
58669 #define IOMUXC_GPR_GPR6_DWP_LOCK_MASK            (0xC0000000U)
58670 #define IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT           (30U)
58671 /*! DWP_LOCK - Domain write protection lock
58672  *  0b00..Neither of DWP bits is locked
58673  *  0b01..The lower DWP bit is locked
58674  *  0b10..The higher DWP bit is locked
58675  *  0b11..Both DWP bits are locked
58676  */
58677 #define IOMUXC_GPR_GPR6_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR6_DWP_LOCK_MASK)
58678 /*! @} */
58679 
58680 /*! @name GPR7 - GPR7 General Purpose Register */
58681 /*! @{ */
58682 
58683 #define IOMUXC_GPR_GPR7_GINT_MASK                (0x1U)
58684 #define IOMUXC_GPR_GPR7_GINT_SHIFT               (0U)
58685 /*! GINT - Global interrupt
58686  */
58687 #define IOMUXC_GPR_GPR7_GINT(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
58688 
58689 #define IOMUXC_GPR_GPR7_DWP_MASK                 (0x30000000U)
58690 #define IOMUXC_GPR_GPR7_DWP_SHIFT                (28U)
58691 /*! DWP - Domain write protection
58692  *  0b00..Both cores are allowed
58693  *  0b01..CM7 is forbidden
58694  *  0b10..CM4 is forbidden
58695  *  0b11..Both cores are forbidden
58696  */
58697 #define IOMUXC_GPR_GPR7_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
58698 
58699 #define IOMUXC_GPR_GPR7_DWP_LOCK_MASK            (0xC0000000U)
58700 #define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT           (30U)
58701 /*! DWP_LOCK - Domain write protection lock
58702  *  0b00..Neither of DWP bits is locked
58703  *  0b01..The lower DWP bit is locked
58704  *  0b10..The higher DWP bit is locked
58705  *  0b11..Both DWP bits are locked
58706  */
58707 #define IOMUXC_GPR_GPR7_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
58708 /*! @} */
58709 
58710 /*! @name GPR8 - GPR8 General Purpose Register */
58711 /*! @{ */
58712 
58713 #define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK          (0x1U)
58714 #define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT         (0U)
58715 /*! WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY
58716  */
58717 #define IOMUXC_GPR_GPR8_WDOG1_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
58718 
58719 #define IOMUXC_GPR_GPR8_DWP_MASK                 (0x30000000U)
58720 #define IOMUXC_GPR_GPR8_DWP_SHIFT                (28U)
58721 /*! DWP - Domain write protection
58722  *  0b00..Both cores are allowed
58723  *  0b01..CM7 is forbidden
58724  *  0b10..CM4 is forbidden
58725  *  0b11..Both cores are forbidden
58726  */
58727 #define IOMUXC_GPR_GPR8_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
58728 
58729 #define IOMUXC_GPR_GPR8_DWP_LOCK_MASK            (0xC0000000U)
58730 #define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT           (30U)
58731 /*! DWP_LOCK - Domain write protection lock
58732  *  0b00..Neither of DWP bits is locked
58733  *  0b01..The lower DWP bit is locked
58734  *  0b10..The higher DWP bit is locked
58735  *  0b11..Both DWP bits are locked
58736  */
58737 #define IOMUXC_GPR_GPR8_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
58738 /*! @} */
58739 
58740 /*! @name GPR9 - GPR9 General Purpose Register */
58741 /*! @{ */
58742 
58743 #define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK          (0x1U)
58744 #define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT         (0U)
58745 /*! WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY
58746  */
58747 #define IOMUXC_GPR_GPR9_WDOG2_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
58748 
58749 #define IOMUXC_GPR_GPR9_DWP_MASK                 (0x30000000U)
58750 #define IOMUXC_GPR_GPR9_DWP_SHIFT                (28U)
58751 /*! DWP - Domain write protection
58752  *  0b00..Both cores are allowed
58753  *  0b01..CM7 is forbidden
58754  *  0b10..CM4 is forbidden
58755  *  0b11..Both cores are forbidden
58756  */
58757 #define IOMUXC_GPR_GPR9_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
58758 
58759 #define IOMUXC_GPR_GPR9_DWP_LOCK_MASK            (0xC0000000U)
58760 #define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT           (30U)
58761 /*! DWP_LOCK - Domain write protection lock
58762  *  0b00..Neither of DWP bits is locked
58763  *  0b01..The lower DWP bit is locked
58764  *  0b10..The higher DWP bit is locked
58765  *  0b11..Both DWP bits are locked
58766  */
58767 #define IOMUXC_GPR_GPR9_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
58768 /*! @} */
58769 
58770 /*! @name GPR10 - GPR10 General Purpose Register */
58771 /*! @{ */
58772 
58773 #define IOMUXC_GPR_GPR10_DWP_MASK                (0x30000000U)
58774 #define IOMUXC_GPR_GPR10_DWP_SHIFT               (28U)
58775 /*! DWP - Domain write protection
58776  *  0b00..Both cores are allowed
58777  *  0b01..CM7 is forbidden
58778  *  0b10..CM4 is forbidden
58779  *  0b11..Both cores are forbidden
58780  */
58781 #define IOMUXC_GPR_GPR10_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
58782 
58783 #define IOMUXC_GPR_GPR10_DWP_LOCK_MASK           (0xC0000000U)
58784 #define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT          (30U)
58785 /*! DWP_LOCK - Domain write protection lock
58786  *  0b00..Neither of DWP bits is locked
58787  *  0b01..The lower DWP bit is locked
58788  *  0b10..The higher DWP bit is locked
58789  *  0b11..Both DWP bits are locked
58790  */
58791 #define IOMUXC_GPR_GPR10_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
58792 /*! @} */
58793 
58794 /*! @name GPR11 - GPR11 General Purpose Register */
58795 /*! @{ */
58796 
58797 #define IOMUXC_GPR_GPR11_DWP_MASK                (0x30000000U)
58798 #define IOMUXC_GPR_GPR11_DWP_SHIFT               (28U)
58799 /*! DWP - Domain write protection
58800  *  0b00..Both cores are allowed
58801  *  0b01..CM7 is forbidden
58802  *  0b10..CM4 is forbidden
58803  *  0b11..Both cores are forbidden
58804  */
58805 #define IOMUXC_GPR_GPR11_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
58806 
58807 #define IOMUXC_GPR_GPR11_DWP_LOCK_MASK           (0xC0000000U)
58808 #define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT          (30U)
58809 /*! DWP_LOCK - Domain write protection lock
58810  *  0b00..Neither of DWP bits is locked
58811  *  0b01..The lower DWP bit is locked
58812  *  0b10..The higher DWP bit is locked
58813  *  0b11..Both DWP bits are locked
58814  */
58815 #define IOMUXC_GPR_GPR11_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
58816 /*! @} */
58817 
58818 /*! @name GPR12 - GPR12 General Purpose Register */
58819 /*! @{ */
58820 
58821 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
58822 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
58823 /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze
58824  */
58825 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
58826 
58827 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U)
58828 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U)
58829 /*! QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select
58830  */
58831 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
58832 
58833 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U)
58834 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U)
58835 /*! QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select
58836  */
58837 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
58838 
58839 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U)
58840 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U)
58841 /*! QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select
58842  */
58843 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
58844 
58845 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U)
58846 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U)
58847 /*! QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select
58848  */
58849 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
58850 
58851 #define IOMUXC_GPR_GPR12_DWP_MASK                (0x30000000U)
58852 #define IOMUXC_GPR_GPR12_DWP_SHIFT               (28U)
58853 /*! DWP - Domain write protection
58854  *  0b00..Both cores are allowed
58855  *  0b01..CM7 is forbidden
58856  *  0b10..CM4 is forbidden
58857  *  0b11..Both cores are forbidden
58858  */
58859 #define IOMUXC_GPR_GPR12_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
58860 
58861 #define IOMUXC_GPR_GPR12_DWP_LOCK_MASK           (0xC0000000U)
58862 #define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT          (30U)
58863 /*! DWP_LOCK - Domain write protection lock
58864  *  0b00..Neither of DWP bits is locked
58865  *  0b01..The lower DWP bit is locked
58866  *  0b10..The higher DWP bit is locked
58867  *  0b11..Both DWP bits are locked
58868  */
58869 #define IOMUXC_GPR_GPR12_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
58870 /*! @} */
58871 
58872 /*! @name GPR13 - GPR13 General Purpose Register */
58873 /*! @{ */
58874 
58875 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U)
58876 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U)
58877 /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze
58878  */
58879 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
58880 
58881 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U)
58882 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U)
58883 /*! QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select
58884  */
58885 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
58886 
58887 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U)
58888 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U)
58889 /*! QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select
58890  */
58891 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
58892 
58893 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U)
58894 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U)
58895 /*! QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select
58896  */
58897 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
58898 
58899 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U)
58900 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U)
58901 /*! QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select
58902  */
58903 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
58904 
58905 #define IOMUXC_GPR_GPR13_DWP_MASK                (0x30000000U)
58906 #define IOMUXC_GPR_GPR13_DWP_SHIFT               (28U)
58907 /*! DWP - Domain write protection
58908  *  0b00..Both cores are allowed
58909  *  0b01..CM7 is forbidden
58910  *  0b10..CM4 is forbidden
58911  *  0b11..Both cores are forbidden
58912  */
58913 #define IOMUXC_GPR_GPR13_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
58914 
58915 #define IOMUXC_GPR_GPR13_DWP_LOCK_MASK           (0xC0000000U)
58916 #define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT          (30U)
58917 /*! DWP_LOCK - Domain write protection lock
58918  *  0b00..Neither of DWP bits is locked
58919  *  0b01..The lower DWP bit is locked
58920  *  0b10..The higher DWP bit is locked
58921  *  0b11..Both DWP bits are locked
58922  */
58923 #define IOMUXC_GPR_GPR13_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
58924 /*! @} */
58925 
58926 /*! @name GPR14 - GPR14 General Purpose Register */
58927 /*! @{ */
58928 
58929 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U)
58930 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U)
58931 /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze
58932  */
58933 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
58934 
58935 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
58936 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
58937 /*! QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select
58938  */
58939 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
58940 
58941 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
58942 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
58943 /*! QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select
58944  */
58945 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
58946 
58947 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
58948 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
58949 /*! QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select
58950  */
58951 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
58952 
58953 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
58954 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
58955 /*! QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select
58956  */
58957 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
58958 
58959 #define IOMUXC_GPR_GPR14_DWP_MASK                (0x30000000U)
58960 #define IOMUXC_GPR_GPR14_DWP_SHIFT               (28U)
58961 /*! DWP - Domain write protection
58962  *  0b00..Both cores are allowed
58963  *  0b01..CM7 is forbidden
58964  *  0b10..CM4 is forbidden
58965  *  0b11..Both cores are forbidden
58966  */
58967 #define IOMUXC_GPR_GPR14_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
58968 
58969 #define IOMUXC_GPR_GPR14_DWP_LOCK_MASK           (0xC0000000U)
58970 #define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT          (30U)
58971 /*! DWP_LOCK - Domain write protection lock
58972  *  0b00..Neither of DWP bits is locked
58973  *  0b01..The lower DWP bit is locked
58974  *  0b10..The higher DWP bit is locked
58975  *  0b11..Both DWP bits are locked
58976  */
58977 #define IOMUXC_GPR_GPR14_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
58978 /*! @} */
58979 
58980 /*! @name GPR15 - GPR15 General Purpose Register */
58981 /*! @{ */
58982 
58983 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U)
58984 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U)
58985 /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze
58986  */
58987 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
58988 
58989 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U)
58990 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U)
58991 /*! QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select
58992  */
58993 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
58994 
58995 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U)
58996 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U)
58997 /*! QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select
58998  */
58999 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
59000 
59001 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U)
59002 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U)
59003 /*! QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select
59004  */
59005 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
59006 
59007 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U)
59008 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U)
59009 /*! QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select
59010  */
59011 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
59012 
59013 #define IOMUXC_GPR_GPR15_DWP_MASK                (0x30000000U)
59014 #define IOMUXC_GPR_GPR15_DWP_SHIFT               (28U)
59015 /*! DWP - Domain write protection
59016  *  0b00..Both cores are allowed
59017  *  0b01..CM7 is forbidden
59018  *  0b10..CM4 is forbidden
59019  *  0b11..Both cores are forbidden
59020  */
59021 #define IOMUXC_GPR_GPR15_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
59022 
59023 #define IOMUXC_GPR_GPR15_DWP_LOCK_MASK           (0xC0000000U)
59024 #define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT          (30U)
59025 /*! DWP_LOCK - Domain write protection lock
59026  *  0b00..Neither of DWP bits is locked
59027  *  0b01..The lower DWP bit is locked
59028  *  0b10..The higher DWP bit is locked
59029  *  0b11..Both DWP bits are locked
59030  */
59031 #define IOMUXC_GPR_GPR15_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
59032 /*! @} */
59033 
59034 /*! @name GPR16 - GPR16 General Purpose Register */
59035 /*! @{ */
59036 
59037 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
59038 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
59039 /*! FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select
59040  */
59041 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
59042 
59043 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK  (0x8U)
59044 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U)
59045 /*! CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable
59046  */
59047 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
59048 
59049 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
59050 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT  (5U)
59051 /*! M7_GPC_SLEEP_SEL - CM7 sleep request selection
59052  */
59053 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
59054 
59055 #define IOMUXC_GPR_GPR16_DWP_MASK                (0x30000000U)
59056 #define IOMUXC_GPR_GPR16_DWP_SHIFT               (28U)
59057 /*! DWP - Domain write protection
59058  *  0b00..Both cores are allowed
59059  *  0b01..CM7 is forbidden
59060  *  0b10..CM4 is forbidden
59061  *  0b11..Both cores are forbidden
59062  */
59063 #define IOMUXC_GPR_GPR16_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
59064 
59065 #define IOMUXC_GPR_GPR16_DWP_LOCK_MASK           (0xC0000000U)
59066 #define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT          (30U)
59067 /*! DWP_LOCK - Domain write protection lock
59068  *  0b00..Neither of DWP bits is locked
59069  *  0b01..The lower DWP bit is locked
59070  *  0b10..The higher DWP bit is locked
59071  *  0b11..Both DWP bits are locked
59072  */
59073 #define IOMUXC_GPR_GPR16_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
59074 /*! @} */
59075 
59076 /*! @name GPR17 - GPR17 General Purpose Register */
59077 /*! @{ */
59078 
59079 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU)
59080 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U)
59081 /*! FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value
59082  */
59083 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
59084 
59085 #define IOMUXC_GPR_GPR17_DWP_MASK                (0x30000000U)
59086 #define IOMUXC_GPR_GPR17_DWP_SHIFT               (28U)
59087 /*! DWP - Domain write protection
59088  *  0b00..Both cores are allowed
59089  *  0b01..CM7 is forbidden
59090  *  0b10..CM4 is forbidden
59091  *  0b11..Both cores are forbidden
59092  */
59093 #define IOMUXC_GPR_GPR17_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
59094 
59095 #define IOMUXC_GPR_GPR17_DWP_LOCK_MASK           (0xC0000000U)
59096 #define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT          (30U)
59097 /*! DWP_LOCK - Domain write protection lock
59098  *  0b00..Neither of DWP bits is locked
59099  *  0b01..The lower DWP bit is locked
59100  *  0b10..The higher DWP bit is locked
59101  *  0b11..Both DWP bits are locked
59102  */
59103 #define IOMUXC_GPR_GPR17_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
59104 /*! @} */
59105 
59106 /*! @name GPR18 - GPR18 General Purpose Register */
59107 /*! @{ */
59108 
59109 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU)
59110 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U)
59111 /*! FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value
59112  */
59113 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
59114 
59115 #define IOMUXC_GPR_GPR18_DWP_MASK                (0x30000000U)
59116 #define IOMUXC_GPR_GPR18_DWP_SHIFT               (28U)
59117 /*! DWP - Domain write protection
59118  *  0b00..Both cores are allowed
59119  *  0b01..CM7 is forbidden
59120  *  0b10..CM4 is forbidden
59121  *  0b11..Both cores are forbidden
59122  */
59123 #define IOMUXC_GPR_GPR18_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
59124 
59125 #define IOMUXC_GPR_GPR18_DWP_LOCK_MASK           (0xC0000000U)
59126 #define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT          (30U)
59127 /*! DWP_LOCK - Domain write protection lock
59128  *  0b00..Neither of DWP bits is locked
59129  *  0b01..The lower DWP bit is locked
59130  *  0b10..The higher DWP bit is locked
59131  *  0b11..Both DWP bits are locked
59132  */
59133 #define IOMUXC_GPR_GPR18_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
59134 /*! @} */
59135 
59136 /*! @name GPR20 - GPR20 General Purpose Register */
59137 /*! @{ */
59138 
59139 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U)
59140 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U)
59141 /*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select
59142  */
59143 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
59144 
59145 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U)
59146 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U)
59147 /*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select
59148  */
59149 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
59150 
59151 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U)
59152 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U)
59153 /*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select
59154  */
59155 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
59156 
59157 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U)
59158 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U)
59159 /*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select
59160  */
59161 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
59162 
59163 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U)
59164 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U)
59165 /*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select
59166  */
59167 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
59168 
59169 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U)
59170 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U)
59171 /*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select
59172  */
59173 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
59174 
59175 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U)
59176 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U)
59177 /*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select
59178  */
59179 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
59180 
59181 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U)
59182 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U)
59183 /*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select
59184  */
59185 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
59186 
59187 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U)
59188 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U)
59189 /*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select
59190  */
59191 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
59192 
59193 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U)
59194 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U)
59195 /*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select
59196  */
59197 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
59198 
59199 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U)
59200 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U)
59201 /*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select
59202  */
59203 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
59204 
59205 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U)
59206 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U)
59207 /*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select
59208  */
59209 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
59210 
59211 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U)
59212 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U)
59213 /*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select
59214  */
59215 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
59216 
59217 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U)
59218 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U)
59219 /*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select
59220  */
59221 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
59222 
59223 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U)
59224 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U)
59225 /*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select
59226  */
59227 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
59228 
59229 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U)
59230 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U)
59231 /*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select
59232  */
59233 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
59234 
59235 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U)
59236 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U)
59237 /*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select
59238  */
59239 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
59240 
59241 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U)
59242 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U)
59243 /*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select
59244  */
59245 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
59246 
59247 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U)
59248 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U)
59249 /*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select
59250  */
59251 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
59252 
59253 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U)
59254 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U)
59255 /*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select
59256  */
59257 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
59258 
59259 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U)
59260 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U)
59261 /*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select
59262  */
59263 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
59264 
59265 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U)
59266 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U)
59267 /*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select
59268  */
59269 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
59270 
59271 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U)
59272 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U)
59273 /*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select
59274  */
59275 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
59276 
59277 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U)
59278 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U)
59279 /*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select
59280  */
59281 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
59282 
59283 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U)
59284 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U)
59285 /*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select
59286  */
59287 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
59288 
59289 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U)
59290 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U)
59291 /*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select
59292  */
59293 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
59294 
59295 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U)
59296 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U)
59297 /*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select
59298  */
59299 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
59300 
59301 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U)
59302 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U)
59303 /*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select
59304  */
59305 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
59306 
59307 #define IOMUXC_GPR_GPR20_DWP_MASK                (0x30000000U)
59308 #define IOMUXC_GPR_GPR20_DWP_SHIFT               (28U)
59309 /*! DWP - Domain write protection
59310  *  0b00..Both cores are allowed
59311  *  0b01..CM7 is forbidden
59312  *  0b10..CM4 is forbidden
59313  *  0b11..Both cores are forbidden
59314  */
59315 #define IOMUXC_GPR_GPR20_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
59316 
59317 #define IOMUXC_GPR_GPR20_DWP_LOCK_MASK           (0xC0000000U)
59318 #define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT          (30U)
59319 /*! DWP_LOCK - Domain write protection lock
59320  *  0b00..Neither of DWP bits is locked
59321  *  0b01..The lower DWP bit is locked
59322  *  0b10..The higher DWP bit is locked
59323  *  0b11..Both DWP bits are locked
59324  */
59325 #define IOMUXC_GPR_GPR20_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
59326 /*! @} */
59327 
59328 /*! @name GPR21 - GPR21 General Purpose Register */
59329 /*! @{ */
59330 
59331 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
59332 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
59333 /*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select
59334  */
59335 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
59336 
59337 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
59338 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
59339 /*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select
59340  */
59341 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
59342 
59343 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
59344 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
59345 /*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select
59346  */
59347 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
59348 
59349 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
59350 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
59351 /*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select
59352  */
59353 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
59354 
59355 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
59356 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
59357 /*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select
59358  */
59359 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
59360 
59361 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
59362 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
59363 /*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select
59364  */
59365 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
59366 
59367 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U)
59368 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U)
59369 /*! IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select
59370  */
59371 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
59372 
59373 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U)
59374 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U)
59375 /*! IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select
59376  */
59377 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
59378 
59379 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U)
59380 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U)
59381 /*! IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select
59382  */
59383 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
59384 
59385 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U)
59386 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U)
59387 /*! IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select
59388  */
59389 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
59390 
59391 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U)
59392 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U)
59393 /*! IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select
59394  */
59395 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
59396 
59397 #define IOMUXC_GPR_GPR21_DWP_MASK                (0x30000000U)
59398 #define IOMUXC_GPR_GPR21_DWP_SHIFT               (28U)
59399 /*! DWP - Domain write protection
59400  *  0b00..Both cores are allowed
59401  *  0b01..CM7 is forbidden
59402  *  0b10..CM4 is forbidden
59403  *  0b11..Both cores are forbidden
59404  */
59405 #define IOMUXC_GPR_GPR21_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
59406 
59407 #define IOMUXC_GPR_GPR21_DWP_LOCK_MASK           (0xC0000000U)
59408 #define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT          (30U)
59409 /*! DWP_LOCK - Domain write protection lock
59410  *  0b00..Neither of DWP bits is locked
59411  *  0b01..The lower DWP bit is locked
59412  *  0b10..The higher DWP bit is locked
59413  *  0b11..Both DWP bits are locked
59414  */
59415 #define IOMUXC_GPR_GPR21_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
59416 /*! @} */
59417 
59418 /*! @name GPR22 - GPR22 General Purpose Register */
59419 /*! @{ */
59420 
59421 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK    (0x1U)
59422 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
59423 /*! REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select
59424  */
59425 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
59426 
59427 #define IOMUXC_GPR_GPR22_DWP_MASK                (0x30000000U)
59428 #define IOMUXC_GPR_GPR22_DWP_SHIFT               (28U)
59429 /*! DWP - Domain write protection
59430  *  0b00..Both cores are allowed
59431  *  0b01..CM7 is forbidden
59432  *  0b10..CM4 is forbidden
59433  *  0b11..Both cores are forbidden
59434  */
59435 #define IOMUXC_GPR_GPR22_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
59436 
59437 #define IOMUXC_GPR_GPR22_DWP_LOCK_MASK           (0xC0000000U)
59438 #define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT          (30U)
59439 /*! DWP_LOCK - Domain write protection lock
59440  *  0b00..Neither of DWP bits is locked
59441  *  0b01..The lower DWP bit is locked
59442  *  0b10..The higher DWP bit is locked
59443  *  0b11..Both DWP bits are locked
59444  */
59445 #define IOMUXC_GPR_GPR22_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
59446 /*! @} */
59447 
59448 /*! @name GPR23 - GPR23 General Purpose Register */
59449 /*! @{ */
59450 
59451 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK    (0x1U)
59452 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
59453 /*! REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select
59454  */
59455 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
59456 
59457 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK    (0x2U)
59458 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
59459 /*! GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select
59460  */
59461 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
59462 
59463 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK    (0x4U)
59464 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
59465 /*! GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select
59466  */
59467 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
59468 
59469 #define IOMUXC_GPR_GPR23_DWP_MASK                (0x30000000U)
59470 #define IOMUXC_GPR_GPR23_DWP_SHIFT               (28U)
59471 /*! DWP - Domain write protection
59472  *  0b00..Both cores are allowed
59473  *  0b01..CM7 is forbidden
59474  *  0b10..CM4 is forbidden
59475  *  0b11..Both cores are forbidden
59476  */
59477 #define IOMUXC_GPR_GPR23_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
59478 
59479 #define IOMUXC_GPR_GPR23_DWP_LOCK_MASK           (0xC0000000U)
59480 #define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT          (30U)
59481 /*! DWP_LOCK - Domain write protection lock
59482  *  0b00..Neither of DWP bits is locked
59483  *  0b01..The lower DWP bit is locked
59484  *  0b10..The higher DWP bit is locked
59485  *  0b11..Both DWP bits are locked
59486  */
59487 #define IOMUXC_GPR_GPR23_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
59488 /*! @} */
59489 
59490 /*! @name GPR24 - GPR24 General Purpose Register */
59491 /*! @{ */
59492 
59493 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK    (0x1U)
59494 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
59495 /*! REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select
59496  */
59497 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
59498 
59499 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK    (0x2U)
59500 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
59501 /*! GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select
59502  */
59503 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
59504 
59505 #define IOMUXC_GPR_GPR24_DWP_MASK                (0x30000000U)
59506 #define IOMUXC_GPR_GPR24_DWP_SHIFT               (28U)
59507 /*! DWP - Domain write protection
59508  *  0b00..Both cores are allowed
59509  *  0b01..CM7 is forbidden
59510  *  0b10..CM4 is forbidden
59511  *  0b11..Both cores are forbidden
59512  */
59513 #define IOMUXC_GPR_GPR24_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
59514 
59515 #define IOMUXC_GPR_GPR24_DWP_LOCK_MASK           (0xC0000000U)
59516 #define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT          (30U)
59517 /*! DWP_LOCK - Domain write protection lock
59518  *  0b00..Neither of DWP bits is locked
59519  *  0b01..The lower DWP bit is locked
59520  *  0b10..The higher DWP bit is locked
59521  *  0b11..Both DWP bits are locked
59522  */
59523 #define IOMUXC_GPR_GPR24_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
59524 /*! @} */
59525 
59526 /*! @name GPR25 - GPR25 General Purpose Register */
59527 /*! @{ */
59528 
59529 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK    (0x1U)
59530 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
59531 /*! REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select
59532  */
59533 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
59534 
59535 #define IOMUXC_GPR_GPR25_DWP_MASK                (0x30000000U)
59536 #define IOMUXC_GPR_GPR25_DWP_SHIFT               (28U)
59537 /*! DWP - Domain write protection
59538  *  0b00..Both cores are allowed
59539  *  0b01..CM7 is forbidden
59540  *  0b10..CM4 is forbidden
59541  *  0b11..Both cores are forbidden
59542  */
59543 #define IOMUXC_GPR_GPR25_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
59544 
59545 #define IOMUXC_GPR_GPR25_DWP_LOCK_MASK           (0xC0000000U)
59546 #define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT          (30U)
59547 /*! DWP_LOCK - Domain write protection lock
59548  *  0b00..Neither of DWP bits is locked
59549  *  0b01..The lower DWP bit is locked
59550  *  0b10..The higher DWP bit is locked
59551  *  0b11..Both DWP bits are locked
59552  */
59553 #define IOMUXC_GPR_GPR25_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
59554 /*! @} */
59555 
59556 /*! @name GPR26 - GPR26 General Purpose Register */
59557 /*! @{ */
59558 
59559 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK    (0x1U)
59560 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
59561 /*! REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select
59562  */
59563 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
59564 
59565 #define IOMUXC_GPR_GPR26_DWP_MASK                (0x30000000U)
59566 #define IOMUXC_GPR_GPR26_DWP_SHIFT               (28U)
59567 /*! DWP - Domain write protection
59568  *  0b00..Both cores are allowed
59569  *  0b01..CM7 is forbidden
59570  *  0b10..CM4 is forbidden
59571  *  0b11..Both cores are forbidden
59572  */
59573 #define IOMUXC_GPR_GPR26_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
59574 
59575 #define IOMUXC_GPR_GPR26_DWP_LOCK_MASK           (0xC0000000U)
59576 #define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT          (30U)
59577 /*! DWP_LOCK - Domain write protection lock
59578  *  0b00..Neither of DWP bits is locked
59579  *  0b01..The lower DWP bit is locked
59580  *  0b10..The higher DWP bit is locked
59581  *  0b11..Both DWP bits are locked
59582  */
59583 #define IOMUXC_GPR_GPR26_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
59584 /*! @} */
59585 
59586 /*! @name GPR27 - GPR27 General Purpose Register */
59587 /*! @{ */
59588 
59589 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK    (0x1U)
59590 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
59591 /*! REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select
59592  */
59593 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
59594 
59595 #define IOMUXC_GPR_GPR27_DWP_MASK                (0x30000000U)
59596 #define IOMUXC_GPR_GPR27_DWP_SHIFT               (28U)
59597 /*! DWP - Domain write protection
59598  *  0b00..Both cores are allowed
59599  *  0b01..CM7 is forbidden
59600  *  0b10..CM4 is forbidden
59601  *  0b11..Both cores are forbidden
59602  */
59603 #define IOMUXC_GPR_GPR27_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
59604 
59605 #define IOMUXC_GPR_GPR27_DWP_LOCK_MASK           (0xC0000000U)
59606 #define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT          (30U)
59607 /*! DWP_LOCK - Domain write protection lock
59608  *  0b00..Neither of DWP bits is locked
59609  *  0b01..The lower DWP bit is locked
59610  *  0b10..The higher DWP bit is locked
59611  *  0b11..Both DWP bits are locked
59612  */
59613 #define IOMUXC_GPR_GPR27_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
59614 /*! @} */
59615 
59616 /*! @name GPR28 - GPR28 General Purpose Register */
59617 /*! @{ */
59618 
59619 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK      (0x1U)
59620 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT     (0U)
59621 /*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions
59622  */
59623 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
59624 
59625 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK      (0x2U)
59626 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT     (1U)
59627 /*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions
59628  */
59629 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
59630 
59631 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK       (0x20U)
59632 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT      (5U)
59633 #define IOMUXC_GPR_GPR28_CACHE_ENET1G(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
59634 
59635 #define IOMUXC_GPR_GPR28_CACHE_ENET_MASK         (0x80U)
59636 #define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT        (7U)
59637 /*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions
59638  */
59639 #define IOMUXC_GPR_GPR28_CACHE_ENET(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
59640 
59641 #define IOMUXC_GPR_GPR28_CACHE_USB_MASK          (0x2000U)
59642 #define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT         (13U)
59643 /*! CACHE_USB - USB block cacheable attribute value of AXI transactions
59644  */
59645 #define IOMUXC_GPR_GPR28_CACHE_USB(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
59646 
59647 #define IOMUXC_GPR_GPR28_DWP_MASK                (0x30000000U)
59648 #define IOMUXC_GPR_GPR28_DWP_SHIFT               (28U)
59649 /*! DWP - Domain write protection
59650  *  0b00..Both cores are allowed
59651  *  0b01..CM7 is forbidden
59652  *  0b10..CM4 is forbidden
59653  *  0b11..Both cores are forbidden
59654  */
59655 #define IOMUXC_GPR_GPR28_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
59656 
59657 #define IOMUXC_GPR_GPR28_DWP_LOCK_MASK           (0xC0000000U)
59658 #define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT          (30U)
59659 /*! DWP_LOCK - Domain write protection lock
59660  *  0b00..Neither of DWP bits is locked
59661  *  0b01..The lower DWP bit is locked
59662  *  0b10..The higher DWP bit is locked
59663  *  0b11..Both DWP bits are locked
59664  */
59665 #define IOMUXC_GPR_GPR28_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
59666 /*! @} */
59667 
59668 /*! @name GPR29 - GPR29 General Purpose Register */
59669 /*! @{ */
59670 
59671 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
59672 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
59673 /*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable
59674  */
59675 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
59676 
59677 #define IOMUXC_GPR_GPR29_DWP_MASK                (0x30000000U)
59678 #define IOMUXC_GPR_GPR29_DWP_SHIFT               (28U)
59679 /*! DWP - Domain write protection
59680  *  0b00..Both cores are allowed
59681  *  0b01..CM7 is forbidden
59682  *  0b10..CM4 is forbidden
59683  *  0b11..Both cores are forbidden
59684  */
59685 #define IOMUXC_GPR_GPR29_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
59686 
59687 #define IOMUXC_GPR_GPR29_DWP_LOCK_MASK           (0xC0000000U)
59688 #define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT          (30U)
59689 /*! DWP_LOCK - Domain write protection lock
59690  *  0b00..Neither of DWP bits is locked
59691  *  0b01..The lower DWP bit is locked
59692  *  0b10..The higher DWP bit is locked
59693  *  0b11..Both DWP bits are locked
59694  */
59695 #define IOMUXC_GPR_GPR29_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
59696 /*! @} */
59697 
59698 /*! @name GPR30 - GPR30 General Purpose Register */
59699 /*! @{ */
59700 
59701 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U)
59702 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U)
59703 /*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable
59704  */
59705 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
59706 
59707 #define IOMUXC_GPR_GPR30_DWP_MASK                (0x30000000U)
59708 #define IOMUXC_GPR_GPR30_DWP_SHIFT               (28U)
59709 /*! DWP - Domain write protection
59710  *  0b00..Both cores are allowed
59711  *  0b01..CM7 is forbidden
59712  *  0b10..CM4 is forbidden
59713  *  0b11..Both cores are forbidden
59714  */
59715 #define IOMUXC_GPR_GPR30_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
59716 
59717 #define IOMUXC_GPR_GPR30_DWP_LOCK_MASK           (0xC0000000U)
59718 #define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT          (30U)
59719 /*! DWP_LOCK - Domain write protection lock
59720  *  0b00..Neither of DWP bits is locked
59721  *  0b01..The lower DWP bit is locked
59722  *  0b10..The higher DWP bit is locked
59723  *  0b11..Both DWP bits are locked
59724  */
59725 #define IOMUXC_GPR_GPR30_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
59726 /*! @} */
59727 
59728 /*! @name GPR31 - GPR31 General Purpose Register */
59729 /*! @{ */
59730 
59731 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
59732 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
59733 /*! RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable
59734  */
59735 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
59736 
59737 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U)
59738 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U)
59739 /*! OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable
59740  */
59741 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
59742 
59743 #define IOMUXC_GPR_GPR31_DWP_MASK                (0x30000000U)
59744 #define IOMUXC_GPR_GPR31_DWP_SHIFT               (28U)
59745 /*! DWP - Domain write protection
59746  *  0b00..Both cores are allowed
59747  *  0b01..CM7 is forbidden
59748  *  0b10..CM4 is forbidden
59749  *  0b11..Both cores are forbidden
59750  */
59751 #define IOMUXC_GPR_GPR31_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
59752 
59753 #define IOMUXC_GPR_GPR31_DWP_LOCK_MASK           (0xC0000000U)
59754 #define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT          (30U)
59755 /*! DWP_LOCK - Domain write protection lock
59756  *  0b00..Neither of DWP bits is locked
59757  *  0b01..The lower DWP bit is locked
59758  *  0b10..The higher DWP bit is locked
59759  *  0b11..Both DWP bits are locked
59760  */
59761 #define IOMUXC_GPR_GPR31_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
59762 /*! @} */
59763 
59764 /*! @name GPR32 - GPR32 General Purpose Register */
59765 /*! @{ */
59766 
59767 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U)
59768 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U)
59769 /*! RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable
59770  */
59771 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
59772 
59773 #define IOMUXC_GPR_GPR32_DWP_MASK                (0x30000000U)
59774 #define IOMUXC_GPR_GPR32_DWP_SHIFT               (28U)
59775 /*! DWP - Domain write protection
59776  *  0b00..Both cores are allowed
59777  *  0b01..CM7 is forbidden
59778  *  0b10..CM4 is forbidden
59779  *  0b11..Both cores are forbidden
59780  */
59781 #define IOMUXC_GPR_GPR32_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
59782 
59783 #define IOMUXC_GPR_GPR32_DWP_LOCK_MASK           (0xC0000000U)
59784 #define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT          (30U)
59785 /*! DWP_LOCK - Domain write protection lock
59786  *  0b00..Neither of DWP bits is locked
59787  *  0b01..The lower DWP bit is locked
59788  *  0b10..The higher DWP bit is locked
59789  *  0b11..Both DWP bits are locked
59790  */
59791 #define IOMUXC_GPR_GPR32_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
59792 /*! @} */
59793 
59794 /*! @name GPR33 - GPR33 General Purpose Register */
59795 /*! @{ */
59796 
59797 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
59798 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
59799 /*! RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable
59800  */
59801 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
59802 
59803 #define IOMUXC_GPR_GPR33_DWP_MASK                (0x30000000U)
59804 #define IOMUXC_GPR_GPR33_DWP_SHIFT               (28U)
59805 /*! DWP - Domain write protection
59806  *  0b00..Both cores are allowed
59807  *  0b01..CM7 is forbidden
59808  *  0b10..CM4 is forbidden
59809  *  0b11..Both cores are forbidden
59810  */
59811 #define IOMUXC_GPR_GPR33_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
59812 
59813 #define IOMUXC_GPR_GPR33_DWP_LOCK_MASK           (0xC0000000U)
59814 #define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT          (30U)
59815 /*! DWP_LOCK - Domain write protection lock
59816  *  0b00..Neither of DWP bits is locked
59817  *  0b01..The lower DWP bit is locked
59818  *  0b10..The higher DWP bit is locked
59819  *  0b11..Both DWP bits are locked
59820  */
59821 #define IOMUXC_GPR_GPR33_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
59822 /*! @} */
59823 
59824 /*! @name GPR34 - GPR34 General Purpose Register */
59825 /*! @{ */
59826 
59827 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U)
59828 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U)
59829 /*! XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable
59830  */
59831 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
59832 
59833 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK  (0x2U)
59834 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U)
59835 /*! FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable
59836  */
59837 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
59838 
59839 #define IOMUXC_GPR_GPR34_DWP_MASK                (0x30000000U)
59840 #define IOMUXC_GPR_GPR34_DWP_SHIFT               (28U)
59841 /*! DWP - Domain write protection
59842  *  0b00..Both cores are allowed
59843  *  0b01..CM7 is forbidden
59844  *  0b10..CM4 is forbidden
59845  *  0b11..Both cores are forbidden
59846  */
59847 #define IOMUXC_GPR_GPR34_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
59848 
59849 #define IOMUXC_GPR_GPR34_DWP_LOCK_MASK           (0xC0000000U)
59850 #define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT          (30U)
59851 /*! DWP_LOCK - Domain write protection lock
59852  *  0b00..Neither of DWP bits is locked
59853  *  0b01..The lower DWP bit is locked
59854  *  0b10..The higher DWP bit is locked
59855  *  0b11..Both DWP bits are locked
59856  */
59857 #define IOMUXC_GPR_GPR34_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
59858 /*! @} */
59859 
59860 /*! @name GPR35 - GPR35 General Purpose Register */
59861 /*! @{ */
59862 
59863 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U)
59864 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U)
59865 /*! XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable
59866  */
59867 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
59868 
59869 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK  (0x2U)
59870 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U)
59871 /*! FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable
59872  */
59873 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
59874 
59875 #define IOMUXC_GPR_GPR35_DWP_MASK                (0x30000000U)
59876 #define IOMUXC_GPR_GPR35_DWP_SHIFT               (28U)
59877 /*! DWP - Domain write protection
59878  *  0b00..Both cores are allowed
59879  *  0b01..CM7 is forbidden
59880  *  0b10..CM4 is forbidden
59881  *  0b11..Both cores are forbidden
59882  */
59883 #define IOMUXC_GPR_GPR35_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
59884 
59885 #define IOMUXC_GPR_GPR35_DWP_LOCK_MASK           (0xC0000000U)
59886 #define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT          (30U)
59887 /*! DWP_LOCK - Domain write protection lock
59888  *  0b00..Neither of DWP bits is locked
59889  *  0b01..The lower DWP bit is locked
59890  *  0b10..The higher DWP bit is locked
59891  *  0b11..Both DWP bits are locked
59892  */
59893 #define IOMUXC_GPR_GPR35_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
59894 /*! @} */
59895 
59896 /*! @name GPR36 - GPR36 General Purpose Register */
59897 /*! @{ */
59898 
59899 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U)
59900 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U)
59901 /*! XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable
59902  */
59903 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
59904 
59905 #define IOMUXC_GPR_GPR36_DWP_MASK                (0x30000000U)
59906 #define IOMUXC_GPR_GPR36_DWP_SHIFT               (28U)
59907 /*! DWP - Domain write protection
59908  *  0b00..Both cores are allowed
59909  *  0b01..CM7 is forbidden
59910  *  0b10..CM4 is forbidden
59911  *  0b11..Both cores are forbidden
59912  */
59913 #define IOMUXC_GPR_GPR36_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
59914 
59915 #define IOMUXC_GPR_GPR36_DWP_LOCK_MASK           (0xC0000000U)
59916 #define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT          (30U)
59917 /*! DWP_LOCK - Domain write protection lock
59918  *  0b00..Neither of DWP bits is locked
59919  *  0b01..The lower DWP bit is locked
59920  *  0b10..The higher DWP bit is locked
59921  *  0b11..Both DWP bits are locked
59922  */
59923 #define IOMUXC_GPR_GPR36_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
59924 /*! @} */
59925 
59926 /*! @name GPR37 - GPR37 General Purpose Register */
59927 /*! @{ */
59928 
59929 #define IOMUXC_GPR_GPR37_NIDEN_MASK              (0x1U)
59930 #define IOMUXC_GPR_GPR37_NIDEN_SHIFT             (0U)
59931 /*! NIDEN - ARM non-secure (non-invasive) debug enable
59932  */
59933 #define IOMUXC_GPR_GPR37_NIDEN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
59934 
59935 #define IOMUXC_GPR_GPR37_DBG_EN_MASK             (0x2U)
59936 #define IOMUXC_GPR_GPR37_DBG_EN_SHIFT            (1U)
59937 /*! DBG_EN - ARM invasive debug enable
59938  */
59939 #define IOMUXC_GPR_GPR37_DBG_EN(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
59940 
59941 #define IOMUXC_GPR_GPR37_EXC_MON_MASK            (0x8U)
59942 #define IOMUXC_GPR_GPR37_EXC_MON_SHIFT           (3U)
59943 /*! EXC_MON - Exclusive monitor response select of illegal command
59944  */
59945 #define IOMUXC_GPR_GPR37_EXC_MON(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
59946 
59947 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK    (0x20U)
59948 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
59949 /*! M7_DBG_ACK_MASK - CM7 debug halt mask
59950  */
59951 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
59952 
59953 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK    (0x40U)
59954 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
59955 /*! M4_DBG_ACK_MASK - CM4 debug halt mask
59956  */
59957 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
59958 
59959 #define IOMUXC_GPR_GPR37_DWP_MASK                (0x30000000U)
59960 #define IOMUXC_GPR_GPR37_DWP_SHIFT               (28U)
59961 /*! DWP - Domain write protection
59962  *  0b00..Both cores are allowed
59963  *  0b01..CM7 is forbidden
59964  *  0b10..CM4 is forbidden
59965  *  0b11..Both cores are forbidden
59966  */
59967 #define IOMUXC_GPR_GPR37_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
59968 
59969 #define IOMUXC_GPR_GPR37_DWP_LOCK_MASK           (0xC0000000U)
59970 #define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT          (30U)
59971 /*! DWP_LOCK - Domain write protection lock
59972  *  0b00..Neither of DWP bits is locked
59973  *  0b01..The lower DWP bit is locked
59974  *  0b10..The higher DWP bit is locked
59975  *  0b11..Both DWP bits are locked
59976  */
59977 #define IOMUXC_GPR_GPR37_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
59978 /*! @} */
59979 
59980 /*! @name GPR38 - GPR38 General Purpose Register */
59981 /*! @{ */
59982 
59983 #define IOMUXC_GPR_GPR38_DWP_MASK                (0x30000000U)
59984 #define IOMUXC_GPR_GPR38_DWP_SHIFT               (28U)
59985 /*! DWP - Domain write protection
59986  *  0b00..Both cores are allowed
59987  *  0b01..CM7 is forbidden
59988  *  0b10..CM4 is forbidden
59989  *  0b11..Both cores are forbidden
59990  */
59991 #define IOMUXC_GPR_GPR38_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
59992 
59993 #define IOMUXC_GPR_GPR38_DWP_LOCK_MASK           (0xC0000000U)
59994 #define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT          (30U)
59995 /*! DWP_LOCK - Domain write protection lock
59996  *  0b00..Neither of DWP bits is locked
59997  *  0b01..The lower DWP bit is locked
59998  *  0b10..The higher DWP bit is locked
59999  *  0b11..Both DWP bits are locked
60000  */
60001 #define IOMUXC_GPR_GPR38_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
60002 /*! @} */
60003 
60004 /*! @name GPR39 - GPR39 General Purpose Register */
60005 /*! @{ */
60006 
60007 #define IOMUXC_GPR_GPR39_DWP_MASK                (0x30000000U)
60008 #define IOMUXC_GPR_GPR39_DWP_SHIFT               (28U)
60009 /*! DWP - Domain write protection
60010  *  0b00..Both cores are allowed
60011  *  0b01..CM7 is forbidden
60012  *  0b10..CM4 is forbidden
60013  *  0b11..Both cores are forbidden
60014  */
60015 #define IOMUXC_GPR_GPR39_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
60016 
60017 #define IOMUXC_GPR_GPR39_DWP_LOCK_MASK           (0xC0000000U)
60018 #define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT          (30U)
60019 /*! DWP_LOCK - Domain write protection lock
60020  *  0b00..Neither of DWP bits is locked
60021  *  0b01..The lower DWP bit is locked
60022  *  0b10..The higher DWP bit is locked
60023  *  0b11..Both DWP bits are locked
60024  */
60025 #define IOMUXC_GPR_GPR39_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
60026 /*! @} */
60027 
60028 /*! @name GPR40 - GPR40 General Purpose Register */
60029 /*! @{ */
60030 
60031 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU)
60032 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U)
60033 /*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
60034  */
60035 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
60036 
60037 #define IOMUXC_GPR_GPR40_DWP_MASK                (0x30000000U)
60038 #define IOMUXC_GPR_GPR40_DWP_SHIFT               (28U)
60039 /*! DWP - Domain write protection
60040  *  0b00..Both cores are allowed
60041  *  0b01..CM7 is forbidden
60042  *  0b10..CM4 is forbidden
60043  *  0b11..Both cores are forbidden
60044  */
60045 #define IOMUXC_GPR_GPR40_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
60046 
60047 #define IOMUXC_GPR_GPR40_DWP_LOCK_MASK           (0xC0000000U)
60048 #define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT          (30U)
60049 /*! DWP_LOCK - Domain write protection lock
60050  *  0b00..Neither of DWP bits is locked
60051  *  0b01..The lower DWP bit is locked
60052  *  0b10..The higher DWP bit is locked
60053  *  0b11..Both DWP bits are locked
60054  */
60055 #define IOMUXC_GPR_GPR40_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
60056 /*! @} */
60057 
60058 /*! @name GPR41 - GPR41 General Purpose Register */
60059 /*! @{ */
60060 
60061 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU)
60062 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U)
60063 /*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
60064  */
60065 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
60066 
60067 #define IOMUXC_GPR_GPR41_DWP_MASK                (0x30000000U)
60068 #define IOMUXC_GPR_GPR41_DWP_SHIFT               (28U)
60069 /*! DWP - Domain write protection
60070  *  0b00..Both cores are allowed
60071  *  0b01..CM7 is forbidden
60072  *  0b10..CM4 is forbidden
60073  *  0b11..Both cores are forbidden
60074  */
60075 #define IOMUXC_GPR_GPR41_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
60076 
60077 #define IOMUXC_GPR_GPR41_DWP_LOCK_MASK           (0xC0000000U)
60078 #define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT          (30U)
60079 /*! DWP_LOCK - Domain write protection lock
60080  *  0b00..Neither of DWP bits is locked
60081  *  0b01..The lower DWP bit is locked
60082  *  0b10..The higher DWP bit is locked
60083  *  0b11..Both DWP bits are locked
60084  */
60085 #define IOMUXC_GPR_GPR41_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
60086 /*! @} */
60087 
60088 /*! @name GPR42 - GPR42 General Purpose Register */
60089 /*! @{ */
60090 
60091 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU)
60092 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U)
60093 /*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
60094  */
60095 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
60096 
60097 #define IOMUXC_GPR_GPR42_DWP_MASK                (0x30000000U)
60098 #define IOMUXC_GPR_GPR42_DWP_SHIFT               (28U)
60099 /*! DWP - Domain write protection
60100  *  0b00..Both cores are allowed
60101  *  0b01..CM7 is forbidden
60102  *  0b10..CM4 is forbidden
60103  *  0b11..Both cores are forbidden
60104  */
60105 #define IOMUXC_GPR_GPR42_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
60106 
60107 #define IOMUXC_GPR_GPR42_DWP_LOCK_MASK           (0xC0000000U)
60108 #define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT          (30U)
60109 /*! DWP_LOCK - Domain write protection lock
60110  *  0b00..Neither of DWP bits is locked
60111  *  0b01..The lower DWP bit is locked
60112  *  0b10..The higher DWP bit is locked
60113  *  0b11..Both DWP bits are locked
60114  */
60115 #define IOMUXC_GPR_GPR42_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
60116 /*! @} */
60117 
60118 /*! @name GPR43 - GPR43 General Purpose Register */
60119 /*! @{ */
60120 
60121 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU)
60122 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U)
60123 /*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
60124  */
60125 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
60126 
60127 #define IOMUXC_GPR_GPR43_DWP_MASK                (0x30000000U)
60128 #define IOMUXC_GPR_GPR43_DWP_SHIFT               (28U)
60129 /*! DWP - Domain write protection
60130  *  0b00..Both cores are allowed
60131  *  0b01..CM7 is forbidden
60132  *  0b10..CM4 is forbidden
60133  *  0b11..Both cores are forbidden
60134  */
60135 #define IOMUXC_GPR_GPR43_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
60136 
60137 #define IOMUXC_GPR_GPR43_DWP_LOCK_MASK           (0xC0000000U)
60138 #define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT          (30U)
60139 /*! DWP_LOCK - Domain write protection lock
60140  *  0b00..Neither of DWP bits is locked
60141  *  0b01..The lower DWP bit is locked
60142  *  0b10..The higher DWP bit is locked
60143  *  0b11..Both DWP bits are locked
60144  */
60145 #define IOMUXC_GPR_GPR43_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
60146 /*! @} */
60147 
60148 /*! @name GPR44 - GPR44 General Purpose Register */
60149 /*! @{ */
60150 
60151 #define IOMUXC_GPR_GPR44_DWP_MASK                (0x30000000U)
60152 #define IOMUXC_GPR_GPR44_DWP_SHIFT               (28U)
60153 /*! DWP - Domain write protection
60154  *  0b00..Both cores are allowed
60155  *  0b01..CM7 is forbidden
60156  *  0b10..CM4 is forbidden
60157  *  0b11..Both cores are forbidden
60158  */
60159 #define IOMUXC_GPR_GPR44_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
60160 
60161 #define IOMUXC_GPR_GPR44_DWP_LOCK_MASK           (0xC0000000U)
60162 #define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT          (30U)
60163 /*! DWP_LOCK - Domain write protection lock
60164  *  0b00..Neither of DWP bits is locked
60165  *  0b01..The lower DWP bit is locked
60166  *  0b10..The higher DWP bit is locked
60167  *  0b11..Both DWP bits are locked
60168  */
60169 #define IOMUXC_GPR_GPR44_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
60170 /*! @} */
60171 
60172 /*! @name GPR45 - GPR45 General Purpose Register */
60173 /*! @{ */
60174 
60175 #define IOMUXC_GPR_GPR45_DWP_MASK                (0x30000000U)
60176 #define IOMUXC_GPR_GPR45_DWP_SHIFT               (28U)
60177 /*! DWP - Domain write protection
60178  *  0b00..Both cores are allowed
60179  *  0b01..CM7 is forbidden
60180  *  0b10..CM4 is forbidden
60181  *  0b11..Both cores are forbidden
60182  */
60183 #define IOMUXC_GPR_GPR45_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
60184 
60185 #define IOMUXC_GPR_GPR45_DWP_LOCK_MASK           (0xC0000000U)
60186 #define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT          (30U)
60187 /*! DWP_LOCK - Domain write protection lock
60188  *  0b00..Neither of DWP bits is locked
60189  *  0b01..The lower DWP bit is locked
60190  *  0b10..The higher DWP bit is locked
60191  *  0b11..Both DWP bits are locked
60192  */
60193 #define IOMUXC_GPR_GPR45_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
60194 /*! @} */
60195 
60196 /*! @name GPR46 - GPR46 General Purpose Register */
60197 /*! @{ */
60198 
60199 #define IOMUXC_GPR_GPR46_DWP_MASK                (0x30000000U)
60200 #define IOMUXC_GPR_GPR46_DWP_SHIFT               (28U)
60201 /*! DWP - Domain write protection
60202  *  0b00..Both cores are allowed
60203  *  0b01..CM7 is forbidden
60204  *  0b10..CM4 is forbidden
60205  *  0b11..Both cores are forbidden
60206  */
60207 #define IOMUXC_GPR_GPR46_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
60208 
60209 #define IOMUXC_GPR_GPR46_DWP_LOCK_MASK           (0xC0000000U)
60210 #define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT          (30U)
60211 /*! DWP_LOCK - Domain write protection lock
60212  *  0b00..Neither of DWP bits is locked
60213  *  0b01..The lower DWP bit is locked
60214  *  0b10..The higher DWP bit is locked
60215  *  0b11..Both DWP bits are locked
60216  */
60217 #define IOMUXC_GPR_GPR46_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
60218 /*! @} */
60219 
60220 /*! @name GPR47 - GPR47 General Purpose Register */
60221 /*! @{ */
60222 
60223 #define IOMUXC_GPR_GPR47_DWP_MASK                (0x30000000U)
60224 #define IOMUXC_GPR_GPR47_DWP_SHIFT               (28U)
60225 /*! DWP - Domain write protection
60226  *  0b00..Both cores are allowed
60227  *  0b01..CM7 is forbidden
60228  *  0b10..CM4 is forbidden
60229  *  0b11..Both cores are forbidden
60230  */
60231 #define IOMUXC_GPR_GPR47_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
60232 
60233 #define IOMUXC_GPR_GPR47_DWP_LOCK_MASK           (0xC0000000U)
60234 #define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT          (30U)
60235 /*! DWP_LOCK - Domain write protection lock
60236  *  0b00..Neither of DWP bits is locked
60237  *  0b01..The lower DWP bit is locked
60238  *  0b10..The higher DWP bit is locked
60239  *  0b11..Both DWP bits are locked
60240  */
60241 #define IOMUXC_GPR_GPR47_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
60242 /*! @} */
60243 
60244 /*! @name GPR48 - GPR48 General Purpose Register */
60245 /*! @{ */
60246 
60247 #define IOMUXC_GPR_GPR48_DWP_MASK                (0x30000000U)
60248 #define IOMUXC_GPR_GPR48_DWP_SHIFT               (28U)
60249 /*! DWP - Domain write protection
60250  *  0b00..Both cores are allowed
60251  *  0b01..CM7 is forbidden
60252  *  0b10..CM4 is forbidden
60253  *  0b11..Both cores are forbidden
60254  */
60255 #define IOMUXC_GPR_GPR48_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
60256 
60257 #define IOMUXC_GPR_GPR48_DWP_LOCK_MASK           (0xC0000000U)
60258 #define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT          (30U)
60259 /*! DWP_LOCK - Domain write protection lock
60260  *  0b00..Neither of DWP bits is locked
60261  *  0b01..The lower DWP bit is locked
60262  *  0b10..The higher DWP bit is locked
60263  *  0b11..Both DWP bits are locked
60264  */
60265 #define IOMUXC_GPR_GPR48_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
60266 /*! @} */
60267 
60268 /*! @name GPR49 - GPR49 General Purpose Register */
60269 /*! @{ */
60270 
60271 #define IOMUXC_GPR_GPR49_DWP_MASK                (0x30000000U)
60272 #define IOMUXC_GPR_GPR49_DWP_SHIFT               (28U)
60273 /*! DWP - Domain write protection
60274  *  0b00..Both cores are allowed
60275  *  0b01..CM7 is forbidden
60276  *  0b10..CM4 is forbidden
60277  *  0b11..Both cores are forbidden
60278  */
60279 #define IOMUXC_GPR_GPR49_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
60280 
60281 #define IOMUXC_GPR_GPR49_DWP_LOCK_MASK           (0xC0000000U)
60282 #define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT          (30U)
60283 /*! DWP_LOCK - Domain write protection lock
60284  *  0b00..Neither of DWP bits is locked
60285  *  0b01..The lower DWP bit is locked
60286  *  0b10..The higher DWP bit is locked
60287  *  0b11..Both DWP bits are locked
60288  */
60289 #define IOMUXC_GPR_GPR49_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
60290 /*! @} */
60291 
60292 /*! @name GPR50 - GPR50 General Purpose Register */
60293 /*! @{ */
60294 
60295 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK       (0x1FU)
60296 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT      (0U)
60297 /*! CAAM_IPS_MGR - CAAM manager processor identifier
60298  */
60299 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
60300 
60301 #define IOMUXC_GPR_GPR50_DWP_MASK                (0x30000000U)
60302 #define IOMUXC_GPR_GPR50_DWP_SHIFT               (28U)
60303 /*! DWP - Domain write protection
60304  *  0b00..Both cores are allowed
60305  *  0b01..CM7 is forbidden
60306  *  0b10..CM4 is forbidden
60307  *  0b11..Both cores are forbidden
60308  */
60309 #define IOMUXC_GPR_GPR50_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
60310 
60311 #define IOMUXC_GPR_GPR50_DWP_LOCK_MASK           (0xC0000000U)
60312 #define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT          (30U)
60313 /*! DWP_LOCK - Domain write protection lock
60314  *  0b00..Neither of DWP bits is locked
60315  *  0b01..The lower DWP bit is locked
60316  *  0b10..The higher DWP bit is locked
60317  *  0b11..Both DWP bits are locked
60318  */
60319 #define IOMUXC_GPR_GPR50_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
60320 /*! @} */
60321 
60322 /*! @name GPR51 - GPR51 General Purpose Register */
60323 /*! @{ */
60324 
60325 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK       (0x1U)
60326 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT      (0U)
60327 /*! M7_NMI_CLEAR - Clear CM7 NMI holding register
60328  */
60329 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
60330 
60331 #define IOMUXC_GPR_GPR51_DWP_MASK                (0x30000000U)
60332 #define IOMUXC_GPR_GPR51_DWP_SHIFT               (28U)
60333 /*! DWP - Domain write protection
60334  *  0b00..Both cores are allowed
60335  *  0b01..CM7 is forbidden
60336  *  0b10..CM4 is forbidden
60337  *  0b11..Both cores are forbidden
60338  */
60339 #define IOMUXC_GPR_GPR51_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
60340 
60341 #define IOMUXC_GPR_GPR51_DWP_LOCK_MASK           (0xC0000000U)
60342 #define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT          (30U)
60343 /*! DWP_LOCK - Domain write protection lock
60344  *  0b00..Neither of DWP bits is locked
60345  *  0b01..The lower DWP bit is locked
60346  *  0b10..The higher DWP bit is locked
60347  *  0b11..Both DWP bits are locked
60348  */
60349 #define IOMUXC_GPR_GPR51_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
60350 /*! @} */
60351 
60352 /*! @name GPR52 - GPR52 General Purpose Register */
60353 /*! @{ */
60354 
60355 #define IOMUXC_GPR_GPR52_DWP_MASK                (0x30000000U)
60356 #define IOMUXC_GPR_GPR52_DWP_SHIFT               (28U)
60357 /*! DWP - Domain write protection
60358  *  0b00..Both cores are allowed
60359  *  0b01..CM7 is forbidden
60360  *  0b10..CM4 is forbidden
60361  *  0b11..Both cores are forbidden
60362  */
60363 #define IOMUXC_GPR_GPR52_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
60364 
60365 #define IOMUXC_GPR_GPR52_DWP_LOCK_MASK           (0xC0000000U)
60366 #define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT          (30U)
60367 /*! DWP_LOCK - Domain write protection lock
60368  *  0b00..Neither of DWP bits is locked
60369  *  0b01..The lower DWP bit is locked
60370  *  0b10..The higher DWP bit is locked
60371  *  0b11..Both DWP bits are locked
60372  */
60373 #define IOMUXC_GPR_GPR52_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
60374 /*! @} */
60375 
60376 /*! @name GPR53 - GPR53 General Purpose Register */
60377 /*! @{ */
60378 
60379 #define IOMUXC_GPR_GPR53_DWP_MASK                (0x30000000U)
60380 #define IOMUXC_GPR_GPR53_DWP_SHIFT               (28U)
60381 /*! DWP - Domain write protection
60382  *  0b00..Both cores are allowed
60383  *  0b01..CM7 is forbidden
60384  *  0b10..CM4 is forbidden
60385  *  0b11..Both cores are forbidden
60386  */
60387 #define IOMUXC_GPR_GPR53_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
60388 
60389 #define IOMUXC_GPR_GPR53_DWP_LOCK_MASK           (0xC0000000U)
60390 #define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT          (30U)
60391 /*! DWP_LOCK - Domain write protection lock
60392  *  0b00..Neither of DWP bits is locked
60393  *  0b01..The lower DWP bit is locked
60394  *  0b10..The higher DWP bit is locked
60395  *  0b11..Both DWP bits are locked
60396  */
60397 #define IOMUXC_GPR_GPR53_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
60398 /*! @} */
60399 
60400 /*! @name GPR54 - GPR54 General Purpose Register */
60401 /*! @{ */
60402 
60403 #define IOMUXC_GPR_GPR54_DWP_MASK                (0x30000000U)
60404 #define IOMUXC_GPR_GPR54_DWP_SHIFT               (28U)
60405 /*! DWP - Domain write protection
60406  *  0b00..Both cores are allowed
60407  *  0b01..CM7 is forbidden
60408  *  0b10..CM4 is forbidden
60409  *  0b11..Both cores are forbidden
60410  */
60411 #define IOMUXC_GPR_GPR54_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
60412 
60413 #define IOMUXC_GPR_GPR54_DWP_LOCK_MASK           (0xC0000000U)
60414 #define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT          (30U)
60415 /*! DWP_LOCK - Domain write protection lock
60416  *  0b00..Neither of DWP bits is locked
60417  *  0b01..The lower DWP bit is locked
60418  *  0b10..The higher DWP bit is locked
60419  *  0b11..Both DWP bits are locked
60420  */
60421 #define IOMUXC_GPR_GPR54_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
60422 /*! @} */
60423 
60424 /*! @name GPR55 - GPR55 General Purpose Register */
60425 /*! @{ */
60426 
60427 #define IOMUXC_GPR_GPR55_DWP_MASK                (0x30000000U)
60428 #define IOMUXC_GPR_GPR55_DWP_SHIFT               (28U)
60429 /*! DWP - Domain write protection
60430  *  0b00..Both cores are allowed
60431  *  0b01..CM7 is forbidden
60432  *  0b10..CM4 is forbidden
60433  *  0b11..Both cores are forbidden
60434  */
60435 #define IOMUXC_GPR_GPR55_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
60436 
60437 #define IOMUXC_GPR_GPR55_DWP_LOCK_MASK           (0xC0000000U)
60438 #define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT          (30U)
60439 /*! DWP_LOCK - Domain write protection lock
60440  *  0b00..Neither of DWP bits is locked
60441  *  0b01..The lower DWP bit is locked
60442  *  0b10..The higher DWP bit is locked
60443  *  0b11..Both DWP bits are locked
60444  */
60445 #define IOMUXC_GPR_GPR55_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
60446 /*! @} */
60447 
60448 /*! @name GPR59 - GPR59 General Purpose Register */
60449 /*! @{ */
60450 
60451 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U)
60452 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U)
60453 /*! MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.
60454  */
60455 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
60456 
60457 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U)
60458 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U)
60459 /*! MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit
60460  *  0b0..Assert reset
60461  *  0b1..De-assert reset
60462  */
60463 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
60464 
60465 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U)
60466 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U)
60467 /*! MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state
60468  *    during continuous clock mode operation, despite line glitches.
60469  */
60470 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
60471 
60472 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U)
60473 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U)
60474 /*! MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS
60475  */
60476 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
60477 
60478 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK     (0x10U)
60479 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT    (4U)
60480 /*! MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY.
60481  */
60482 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
60483 
60484 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U)
60485 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U)
60486 /*! MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable
60487  */
60488 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
60489 
60490 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
60491 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT  (6U)
60492 /*! MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits
60493  */
60494 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
60495 
60496 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK    (0x300U)
60497 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
60498 /*! MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01
60499  *  0b00..344mV
60500  *  0b01..325mV (Default)
60501  *  0b10..307mV
60502  *  0b11..Invalid
60503  */
60504 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
60505 
60506 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK    (0xC00U)
60507 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
60508 /*! MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01
60509  */
60510 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
60511 
60512 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U)
60513 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U)
60514 /*! MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE.
60515  */
60516 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
60517 
60518 #define IOMUXC_GPR_GPR59_DWP_MASK                (0x30000000U)
60519 #define IOMUXC_GPR_GPR59_DWP_SHIFT               (28U)
60520 /*! DWP - Domain write protection
60521  *  0b00..Both cores are allowed
60522  *  0b01..CM7 is forbidden
60523  *  0b10..CM4 is forbidden
60524  *  0b11..Both cores are forbidden
60525  */
60526 #define IOMUXC_GPR_GPR59_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
60527 
60528 #define IOMUXC_GPR_GPR59_DWP_LOCK_MASK           (0xC0000000U)
60529 #define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT          (30U)
60530 /*! DWP_LOCK - Domain write protection lock
60531  *  0b00..Neither of DWP bits is locked
60532  *  0b01..The lower DWP bit is locked
60533  *  0b10..The higher DWP bit is locked
60534  *  0b11..Both DWP bits are locked
60535  */
60536 #define IOMUXC_GPR_GPR59_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
60537 /*! @} */
60538 
60539 /*! @name GPR62 - GPR62 General Purpose Register */
60540 /*! @{ */
60541 
60542 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK    (0x7U)
60543 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
60544 /*! MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits
60545  */
60546 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
60547 
60548 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK     (0x38U)
60549 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT    (3U)
60550 /*! MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits
60551  */
60552 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
60553 
60554 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK     (0x1C0U)
60555 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT    (6U)
60556 /*! MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits
60557  */
60558 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
60559 
60560 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
60561 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT  (9U)
60562 /*! MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits
60563  */
60564 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
60565 
60566 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U)
60567 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U)
60568 /*! MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable
60569  */
60570 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
60571 
60572 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U)
60573 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U)
60574 /*! MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit
60575  *  0b0..Assert reset
60576  *  0b1..De-assert reset
60577  */
60578 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
60579 
60580 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U)
60581 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U)
60582 /*! MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit
60583  *  0b0..Assert reset
60584  *  0b1..De-assert reset
60585  */
60586 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
60587 
60588 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U)
60589 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U)
60590 /*! MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit
60591  *  0b0..Assert reset
60592  *  0b1..De-assert reset
60593  */
60594 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
60595 
60596 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U)
60597 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U)
60598 /*! MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit
60599  *  0b0..Assert reset
60600  *  0b1..De-assert reset
60601  */
60602 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
60603 
60604 #define IOMUXC_GPR_GPR62_DWP_MASK                (0x30000000U)
60605 #define IOMUXC_GPR_GPR62_DWP_SHIFT               (28U)
60606 /*! DWP - Domain write protection
60607  *  0b00..Both cores are allowed
60608  *  0b01..CM7 is forbidden
60609  *  0b10..CM4 is forbidden
60610  *  0b11..Both cores are forbidden
60611  */
60612 #define IOMUXC_GPR_GPR62_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
60613 
60614 #define IOMUXC_GPR_GPR62_DWP_LOCK_MASK           (0xC0000000U)
60615 #define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT          (30U)
60616 /*! DWP_LOCK - Domain write protection lock
60617  *  0b00..Neither of DWP bits is locked
60618  *  0b01..The lower DWP bit is locked
60619  *  0b10..The higher DWP bit is locked
60620  *  0b11..Both DWP bits are locked
60621  */
60622 #define IOMUXC_GPR_GPR62_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
60623 /*! @} */
60624 
60625 /*! @name GPR63 - GPR63 General Purpose Register */
60626 /*! @{ */
60627 
60628 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U)
60629 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U)
60630 /*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag
60631  */
60632 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
60633 /*! @} */
60634 
60635 /*! @name GPR64 - GPR64 General Purpose Register */
60636 /*! @{ */
60637 
60638 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK  (0x1U)
60639 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U)
60640 /*! GPIO_DISP1_FREEZE - Compensation code freeze
60641  */
60642 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
60643 
60644 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK  (0x2U)
60645 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U)
60646 /*! GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60647  */
60648 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
60649 
60650 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK  (0x4U)
60651 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U)
60652 /*! GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60653  */
60654 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
60655 
60656 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U)
60657 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U)
60658 /*! GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze
60659  */
60660 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
60661 
60662 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK  (0xF0U)
60663 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U)
60664 /*! GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core
60665  */
60666 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
60667 
60668 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK  (0xF00U)
60669 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U)
60670 /*! GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core
60671  */
60672 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
60673 
60674 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U)
60675 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U)
60676 /*! GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection
60677  */
60678 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
60679 
60680 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U)
60681 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U)
60682 /*! GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable
60683  */
60684 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
60685 
60686 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U)
60687 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U)
60688 /*! GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable
60689  */
60690 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
60691 
60692 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK  (0x100000U)
60693 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U)
60694 /*! GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag
60695  */
60696 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
60697 
60698 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
60699 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT  (21U)
60700 /*! GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes
60701  */
60702 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
60703 
60704 #define IOMUXC_GPR_GPR64_DWP_MASK                (0x30000000U)
60705 #define IOMUXC_GPR_GPR64_DWP_SHIFT               (28U)
60706 /*! DWP - Domain write protection
60707  *  0b00..Both cores are allowed
60708  *  0b01..CM7 is forbidden
60709  *  0b10..CM4 is forbidden
60710  *  0b11..Both cores are forbidden
60711  */
60712 #define IOMUXC_GPR_GPR64_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
60713 
60714 #define IOMUXC_GPR_GPR64_DWP_LOCK_MASK           (0xC0000000U)
60715 #define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT          (30U)
60716 /*! DWP_LOCK - Domain write protection lock
60717  *  0b00..Neither of DWP bits is locked
60718  *  0b01..The lower DWP bit is locked
60719  *  0b10..The higher DWP bit is locked
60720  *  0b11..Both DWP bits are locked
60721  */
60722 #define IOMUXC_GPR_GPR64_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
60723 /*! @} */
60724 
60725 /*! @name GPR65 - GPR65 General Purpose Register */
60726 /*! @{ */
60727 
60728 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
60729 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT  (0U)
60730 /*! GPIO_EMC1_FREEZE - Compensation code freeze
60731  */
60732 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
60733 
60734 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
60735 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT  (1U)
60736 /*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60737  */
60738 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
60739 
60740 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
60741 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT  (2U)
60742 /*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60743  */
60744 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
60745 
60746 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
60747 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
60748 /*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze
60749  */
60750 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
60751 
60752 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
60753 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT  (4U)
60754 /*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core
60755  */
60756 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
60757 
60758 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
60759 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT  (8U)
60760 /*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core
60761  */
60762 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
60763 
60764 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
60765 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
60766 /*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection
60767  */
60768 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
60769 
60770 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
60771 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
60772 /*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable
60773  */
60774 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
60775 
60776 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
60777 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
60778 /*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable
60779  */
60780 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
60781 
60782 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
60783 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT  (20U)
60784 /*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag
60785  */
60786 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
60787 
60788 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK    (0x1E00000U)
60789 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
60790 /*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes
60791  */
60792 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
60793 
60794 #define IOMUXC_GPR_GPR65_DWP_MASK                (0x30000000U)
60795 #define IOMUXC_GPR_GPR65_DWP_SHIFT               (28U)
60796 /*! DWP - Domain write protection
60797  *  0b00..Both cores are allowed
60798  *  0b01..CM7 is forbidden
60799  *  0b10..CM4 is forbidden
60800  *  0b11..Both cores are forbidden
60801  */
60802 #define IOMUXC_GPR_GPR65_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
60803 
60804 #define IOMUXC_GPR_GPR65_DWP_LOCK_MASK           (0xC0000000U)
60805 #define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT          (30U)
60806 /*! DWP_LOCK - Domain write protection lock
60807  *  0b00..Neither of DWP bits is locked
60808  *  0b01..The lower DWP bit is locked
60809  *  0b10..The higher DWP bit is locked
60810  *  0b11..Both DWP bits are locked
60811  */
60812 #define IOMUXC_GPR_GPR65_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
60813 /*! @} */
60814 
60815 /*! @name GPR66 - GPR66 General Purpose Register */
60816 /*! @{ */
60817 
60818 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
60819 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT  (0U)
60820 /*! GPIO_EMC2_FREEZE - Compensation code freeze
60821  */
60822 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
60823 
60824 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
60825 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT  (1U)
60826 /*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60827  */
60828 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
60829 
60830 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
60831 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT  (2U)
60832 /*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60833  */
60834 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
60835 
60836 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
60837 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
60838 /*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze
60839  */
60840 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
60841 
60842 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
60843 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT  (4U)
60844 /*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core
60845  */
60846 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
60847 
60848 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
60849 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT  (8U)
60850 /*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core
60851  */
60852 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
60853 
60854 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
60855 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
60856 /*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection
60857  */
60858 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
60859 
60860 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
60861 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
60862 /*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable
60863  */
60864 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
60865 
60866 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
60867 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
60868 /*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable
60869  */
60870 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
60871 
60872 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
60873 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT  (20U)
60874 /*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag
60875  */
60876 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
60877 
60878 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK    (0x1E00000U)
60879 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
60880 /*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes
60881  */
60882 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
60883 
60884 #define IOMUXC_GPR_GPR66_DWP_MASK                (0x30000000U)
60885 #define IOMUXC_GPR_GPR66_DWP_SHIFT               (28U)
60886 /*! DWP - Domain write protection
60887  *  0b00..Both cores are allowed
60888  *  0b01..CM7 is forbidden
60889  *  0b10..CM4 is forbidden
60890  *  0b11..Both cores are forbidden
60891  */
60892 #define IOMUXC_GPR_GPR66_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
60893 
60894 #define IOMUXC_GPR_GPR66_DWP_LOCK_MASK           (0xC0000000U)
60895 #define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT          (30U)
60896 /*! DWP_LOCK - Domain write protection lock
60897  *  0b00..Neither of DWP bits is locked
60898  *  0b01..The lower DWP bit is locked
60899  *  0b10..The higher DWP bit is locked
60900  *  0b11..Both DWP bits are locked
60901  */
60902 #define IOMUXC_GPR_GPR66_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
60903 /*! @} */
60904 
60905 /*! @name GPR67 - GPR67 General Purpose Register */
60906 /*! @{ */
60907 
60908 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK    (0x1U)
60909 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
60910 /*! GPIO_SD1_FREEZE - Compensation code freeze
60911  */
60912 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
60913 
60914 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK    (0x2U)
60915 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
60916 /*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
60917  */
60918 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
60919 
60920 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK    (0x4U)
60921 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
60922 /*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
60923  */
60924 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
60925 
60926 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
60927 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
60928 /*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze
60929  */
60930 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
60931 
60932 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK    (0xF0U)
60933 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
60934 /*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core
60935  */
60936 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
60937 
60938 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK    (0xF00U)
60939 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
60940 /*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core
60941  */
60942 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
60943 
60944 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
60945 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
60946 /*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection
60947  */
60948 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
60949 
60950 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
60951 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
60952 /*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable
60953  */
60954 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
60955 
60956 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
60957 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
60958 /*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable
60959  */
60960 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
60961 
60962 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK    (0x100000U)
60963 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
60964 /*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag
60965  */
60966 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
60967 
60968 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK     (0x1E00000U)
60969 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT    (21U)
60970 /*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes
60971  */
60972 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
60973 
60974 #define IOMUXC_GPR_GPR67_DWP_MASK                (0x30000000U)
60975 #define IOMUXC_GPR_GPR67_DWP_SHIFT               (28U)
60976 /*! DWP - Domain write protection
60977  *  0b00..Both cores are allowed
60978  *  0b01..CM7 is forbidden
60979  *  0b10..CM4 is forbidden
60980  *  0b11..Both cores are forbidden
60981  */
60982 #define IOMUXC_GPR_GPR67_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
60983 
60984 #define IOMUXC_GPR_GPR67_DWP_LOCK_MASK           (0xC0000000U)
60985 #define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT          (30U)
60986 /*! DWP_LOCK - Domain write protection lock
60987  *  0b00..Neither of DWP bits is locked
60988  *  0b01..The lower DWP bit is locked
60989  *  0b10..The higher DWP bit is locked
60990  *  0b11..Both DWP bits are locked
60991  */
60992 #define IOMUXC_GPR_GPR67_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
60993 /*! @} */
60994 
60995 /*! @name GPR68 - GPR68 General Purpose Register */
60996 /*! @{ */
60997 
60998 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK    (0x1U)
60999 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
61000 /*! GPIO_SD2_FREEZE - Compensation code freeze
61001  */
61002 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
61003 
61004 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK    (0x2U)
61005 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
61006 /*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
61007  */
61008 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
61009 
61010 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK    (0x4U)
61011 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
61012 /*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
61013  */
61014 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
61015 
61016 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
61017 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
61018 /*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze
61019  */
61020 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
61021 
61022 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK    (0xF0U)
61023 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
61024 /*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core
61025  */
61026 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
61027 
61028 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK    (0xF00U)
61029 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
61030 /*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core
61031  */
61032 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
61033 
61034 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
61035 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
61036 /*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection
61037  */
61038 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
61039 
61040 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
61041 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
61042 /*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable
61043  */
61044 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
61045 
61046 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
61047 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
61048 /*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable
61049  */
61050 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
61051 
61052 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK    (0x100000U)
61053 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
61054 /*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag
61055  */
61056 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
61057 
61058 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK     (0x1E00000U)
61059 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT    (21U)
61060 /*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes
61061  */
61062 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
61063 
61064 #define IOMUXC_GPR_GPR68_DWP_MASK                (0x30000000U)
61065 #define IOMUXC_GPR_GPR68_DWP_SHIFT               (28U)
61066 /*! DWP - Domain write protection
61067  *  0b00..Both cores are allowed
61068  *  0b01..CM7 is forbidden
61069  *  0b10..CM4 is forbidden
61070  *  0b11..Both cores are forbidden
61071  */
61072 #define IOMUXC_GPR_GPR68_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
61073 
61074 #define IOMUXC_GPR_GPR68_DWP_LOCK_MASK           (0xC0000000U)
61075 #define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT          (30U)
61076 /*! DWP_LOCK - Domain write protection lock
61077  *  0b00..Neither of DWP bits is locked
61078  *  0b01..The lower DWP bit is locked
61079  *  0b10..The higher DWP bit is locked
61080  *  0b11..Both DWP bits are locked
61081  */
61082 #define IOMUXC_GPR_GPR68_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
61083 /*! @} */
61084 
61085 /*! @name GPR69 - GPR69 General Purpose Register */
61086 /*! @{ */
61087 
61088 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U)
61089 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U)
61090 /*! GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
61091  */
61092 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
61093 
61094 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U)
61095 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U)
61096 /*! GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
61097  */
61098 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
61099 
61100 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U)
61101 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U)
61102 /*! GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
61103  */
61104 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
61105 
61106 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U)
61107 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U)
61108 /*! GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
61109  */
61110 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
61111 
61112 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U)
61113 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U)
61114 /*! GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
61115  */
61116 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
61117 
61118 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U)
61119 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U)
61120 /*! GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
61121  */
61122 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
61123 
61124 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U)
61125 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U)
61126 /*! SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable
61127  */
61128 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
61129 
61130 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
61131 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
61132 /*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable
61133  */
61134 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
61135 
61136 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
61137 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
61138 /*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable
61139  */
61140 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
61141 
61142 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
61143 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U)
61144 /*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable
61145  */
61146 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
61147 
61148 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
61149 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U)
61150 /*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable
61151  */
61152 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
61153 
61154 #define IOMUXC_GPR_GPR69_DWP_MASK                (0x30000000U)
61155 #define IOMUXC_GPR_GPR69_DWP_SHIFT               (28U)
61156 /*! DWP - Domain write protection
61157  *  0b00..Both cores are allowed
61158  *  0b01..CM7 is forbidden
61159  *  0b10..CM4 is forbidden
61160  *  0b11..Both cores are forbidden
61161  */
61162 #define IOMUXC_GPR_GPR69_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
61163 
61164 #define IOMUXC_GPR_GPR69_DWP_LOCK_MASK           (0xC0000000U)
61165 #define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT          (30U)
61166 /*! DWP_LOCK - Domain write protection lock
61167  *  0b00..Neither of DWP bits is locked
61168  *  0b01..The lower DWP bit is locked
61169  *  0b10..The higher DWP bit is locked
61170  *  0b11..Both DWP bits are locked
61171  */
61172 #define IOMUXC_GPR_GPR69_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
61173 /*! @} */
61174 
61175 /*! @name GPR70 - GPR70 General Purpose Register */
61176 /*! @{ */
61177 
61178 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK      (0x1U)
61179 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT     (0U)
61180 /*! ADC1_IPG_DOZE - ADC1 doze mode
61181  */
61182 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
61183 
61184 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK      (0x2U)
61185 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT     (1U)
61186 /*! ADC1_STOP_REQ - ADC1 stop request
61187  */
61188 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
61189 
61190 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U)
61191 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U)
61192 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted.
61193  *  0b0..This module is functional in Stop Mode
61194  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61195  */
61196 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
61197 
61198 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK      (0x8U)
61199 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT     (3U)
61200 /*! ADC2_IPG_DOZE - ADC2 doze mode
61201  */
61202 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
61203 
61204 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK      (0x10U)
61205 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT     (4U)
61206 /*! ADC2_STOP_REQ - ADC2 stop request
61207  */
61208 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
61209 
61210 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U)
61211 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U)
61212 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted.
61213  *  0b0..This module is functional in Stop Mode
61214  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61215  */
61216 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
61217 
61218 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK      (0x40U)
61219 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT     (6U)
61220 /*! CAAM_IPG_DOZE - CAN3 doze mode
61221  */
61222 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
61223 
61224 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK      (0x80U)
61225 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT     (7U)
61226 /*! CAAM_STOP_REQ - CAAM stop request
61227  */
61228 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
61229 
61230 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK      (0x100U)
61231 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT     (8U)
61232 /*! CAN1_IPG_DOZE - CAN1 doze mode
61233  */
61234 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
61235 
61236 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK      (0x200U)
61237 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT     (9U)
61238 /*! CAN1_STOP_REQ - CAN1 stop request
61239  */
61240 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
61241 
61242 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK      (0x400U)
61243 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT     (10U)
61244 /*! CAN2_IPG_DOZE - CAN2 doze mode
61245  */
61246 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
61247 
61248 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK      (0x800U)
61249 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT     (11U)
61250 /*! CAN2_STOP_REQ - CAN2 stop request
61251  */
61252 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
61253 
61254 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK      (0x1000U)
61255 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT     (12U)
61256 /*! CAN3_IPG_DOZE - CAN3 doze mode
61257  */
61258 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
61259 
61260 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK      (0x2000U)
61261 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT     (13U)
61262 /*! CAN3_STOP_REQ - CAN3 stop request
61263  */
61264 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
61265 
61266 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK      (0x8000U)
61267 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT     (15U)
61268 /*! EDMA_STOP_REQ - EDMA stop request
61269  */
61270 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
61271 
61272 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
61273 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U)
61274 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
61275  */
61276 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
61277 
61278 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK      (0x20000U)
61279 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT     (17U)
61280 /*! ENET_IPG_DOZE - ENET doze mode
61281  */
61282 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
61283 
61284 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK      (0x40000U)
61285 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT     (18U)
61286 /*! ENET_STOP_REQ - ENET stop request
61287  */
61288 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
61289 
61290 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK    (0x80000U)
61291 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
61292 /*! ENET1G_IPG_DOZE - ENET1G doze mode
61293  */
61294 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
61295 
61296 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK    (0x100000U)
61297 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
61298 /*! ENET1G_STOP_REQ - ENET1G stop request
61299  */
61300 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
61301 
61302 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
61303 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT  (21U)
61304 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
61305  */
61306 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
61307 
61308 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
61309 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT  (22U)
61310 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
61311  */
61312 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
61313 
61314 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK  (0x800000U)
61315 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U)
61316 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
61317  */
61318 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
61319 
61320 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK  (0x1000000U)
61321 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U)
61322 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
61323  */
61324 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
61325 
61326 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK  (0x2000000U)
61327 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U)
61328 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
61329  */
61330 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
61331 
61332 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK  (0x4000000U)
61333 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U)
61334 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
61335  */
61336 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
61337 
61338 #define IOMUXC_GPR_GPR70_DWP_MASK                (0x30000000U)
61339 #define IOMUXC_GPR_GPR70_DWP_SHIFT               (28U)
61340 /*! DWP - Domain write protection
61341  *  0b00..Both cores are allowed
61342  *  0b01..CM7 is forbidden
61343  *  0b10..CM4 is forbidden
61344  *  0b11..Both cores are forbidden
61345  */
61346 #define IOMUXC_GPR_GPR70_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
61347 
61348 #define IOMUXC_GPR_GPR70_DWP_LOCK_MASK           (0xC0000000U)
61349 #define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT          (30U)
61350 /*! DWP_LOCK - Domain write protection lock
61351  *  0b00..Neither of DWP bits is locked
61352  *  0b01..The lower DWP bit is locked
61353  *  0b10..The higher DWP bit is locked
61354  *  0b11..Both DWP bits are locked
61355  */
61356 #define IOMUXC_GPR_GPR70_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
61357 /*! @} */
61358 
61359 /*! @name GPR71 - GPR71 General Purpose Register */
61360 /*! @{ */
61361 
61362 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK      (0x1U)
61363 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT     (0U)
61364 /*! GPT1_IPG_DOZE - GPT1 doze mode
61365  */
61366 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
61367 
61368 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK      (0x2U)
61369 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT     (1U)
61370 /*! GPT2_IPG_DOZE - GPT2 doze mode
61371  */
61372 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
61373 
61374 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK      (0x4U)
61375 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT     (2U)
61376 /*! GPT3_IPG_DOZE - GPT3 doze mode
61377  */
61378 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
61379 
61380 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK      (0x8U)
61381 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT     (3U)
61382 /*! GPT4_IPG_DOZE - GPT4 doze mode
61383  */
61384 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
61385 
61386 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK      (0x10U)
61387 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT     (4U)
61388 /*! GPT5_IPG_DOZE - GPT5 doze mode
61389  */
61390 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
61391 
61392 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK      (0x20U)
61393 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT     (5U)
61394 /*! GPT6_IPG_DOZE - GPT6 doze mode
61395  */
61396 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
61397 
61398 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK    (0x40U)
61399 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
61400 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
61401  */
61402 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
61403 
61404 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK    (0x80U)
61405 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
61406 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
61407  */
61408 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
61409 
61410 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
61411 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
61412 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted.
61413  *  0b0..This module is functional in Stop Mode
61414  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61415  */
61416 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
61417 
61418 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK    (0x200U)
61419 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
61420 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
61421  */
61422 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
61423 
61424 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK    (0x400U)
61425 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
61426 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
61427  */
61428 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
61429 
61430 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
61431 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
61432 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted.
61433  *  0b0..This module is functional in Stop Mode
61434  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61435  */
61436 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
61437 
61438 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK    (0x1000U)
61439 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
61440 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
61441  */
61442 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
61443 
61444 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK    (0x2000U)
61445 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
61446 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
61447  */
61448 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
61449 
61450 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
61451 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
61452 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted.
61453  *  0b0..This module is functional in Stop Mode
61454  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61455  */
61456 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
61457 
61458 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK    (0x8000U)
61459 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
61460 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
61461  */
61462 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
61463 
61464 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK    (0x10000U)
61465 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
61466 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
61467  */
61468 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
61469 
61470 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
61471 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
61472 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted.
61473  *  0b0..This module is functional in Stop Mode
61474  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61475  */
61476 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
61477 
61478 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK    (0x40000U)
61479 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
61480 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
61481  */
61482 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
61483 
61484 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK    (0x80000U)
61485 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
61486 /*! LPI2C5_STOP_REQ - LPI2C5 stop request
61487  */
61488 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
61489 
61490 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
61491 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
61492 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted.
61493  *  0b0..This module is functional in Stop Mode
61494  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61495  */
61496 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
61497 
61498 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK    (0x200000U)
61499 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
61500 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
61501  */
61502 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
61503 
61504 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK    (0x400000U)
61505 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
61506 /*! LPI2C6_STOP_REQ - LPI2C6 stop request
61507  */
61508 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
61509 
61510 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
61511 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
61512 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted.
61513  *  0b0..This module is functional in Stop Mode
61514  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61515  */
61516 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
61517 
61518 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK    (0x1000000U)
61519 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
61520 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
61521  */
61522 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
61523 
61524 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK    (0x2000000U)
61525 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
61526 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
61527  */
61528 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
61529 
61530 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
61531 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
61532 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted.
61533  *  0b0..This module is functional in Stop Mode
61534  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61535  */
61536 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
61537 
61538 #define IOMUXC_GPR_GPR71_DWP_MASK                (0x30000000U)
61539 #define IOMUXC_GPR_GPR71_DWP_SHIFT               (28U)
61540 /*! DWP - Domain write protection
61541  *  0b00..Both cores are allowed
61542  *  0b01..CM7 is forbidden
61543  *  0b10..CM4 is forbidden
61544  *  0b11..Both cores are forbidden
61545  */
61546 #define IOMUXC_GPR_GPR71_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
61547 
61548 #define IOMUXC_GPR_GPR71_DWP_LOCK_MASK           (0xC0000000U)
61549 #define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT          (30U)
61550 /*! DWP_LOCK - Domain write protection lock
61551  *  0b00..Neither of DWP bits is locked
61552  *  0b01..The lower DWP bit is locked
61553  *  0b10..The higher DWP bit is locked
61554  *  0b11..Both DWP bits are locked
61555  */
61556 #define IOMUXC_GPR_GPR71_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
61557 /*! @} */
61558 
61559 /*! @name GPR72 - GPR72 General Purpose Register */
61560 /*! @{ */
61561 
61562 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK    (0x1U)
61563 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
61564 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
61565  */
61566 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
61567 
61568 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK    (0x2U)
61569 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
61570 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
61571  */
61572 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
61573 
61574 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
61575 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
61576 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted.
61577  *  0b0..This module is functional in Stop Mode
61578  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61579  */
61580 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
61581 
61582 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK    (0x8U)
61583 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
61584 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
61585  */
61586 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
61587 
61588 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK    (0x10U)
61589 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
61590 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
61591  */
61592 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
61593 
61594 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
61595 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
61596 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted.
61597  *  0b0..This module is functional in Stop Mode
61598  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61599  */
61600 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
61601 
61602 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK    (0x40U)
61603 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
61604 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
61605  */
61606 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
61607 
61608 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK    (0x80U)
61609 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
61610 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
61611  */
61612 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
61613 
61614 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
61615 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
61616 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted.
61617  *  0b0..This module is functional in Stop Mode
61618  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61619  */
61620 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
61621 
61622 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK    (0x200U)
61623 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
61624 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
61625  */
61626 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
61627 
61628 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK    (0x400U)
61629 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
61630 /*! LPSPI5_STOP_REQ - LPSPI5 stop request
61631  */
61632 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
61633 
61634 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
61635 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
61636 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted.
61637  *  0b0..This module is functional in Stop Mode
61638  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61639  */
61640 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
61641 
61642 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK    (0x1000U)
61643 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
61644 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
61645  */
61646 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
61647 
61648 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK    (0x2000U)
61649 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
61650 /*! LPSPI6_STOP_REQ - LPSPI6 stop request
61651  */
61652 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
61653 
61654 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
61655 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
61656 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted.
61657  *  0b0..This module is functional in Stop Mode
61658  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61659  */
61660 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
61661 
61662 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
61663 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT  (15U)
61664 /*! LPUART1_IPG_DOZE - LPUART1 doze mode
61665  */
61666 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
61667 
61668 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
61669 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT  (16U)
61670 /*! LPUART1_STOP_REQ - LPUART1 stop request
61671  */
61672 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
61673 
61674 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
61675 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U)
61676 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted.
61677  *  0b0..This module is functional in Stop Mode
61678  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61679  */
61680 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
61681 
61682 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
61683 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT  (18U)
61684 /*! LPUART2_IPG_DOZE - LPUART2 doze mode
61685  */
61686 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
61687 
61688 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
61689 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT  (19U)
61690 /*! LPUART2_STOP_REQ - LPUART2 stop request
61691  */
61692 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
61693 
61694 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
61695 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U)
61696 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted.
61697  *  0b0..This module is functional in Stop Mode
61698  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61699  */
61700 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
61701 
61702 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
61703 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT  (21U)
61704 /*! LPUART3_IPG_DOZE - LPUART3 doze mode
61705  */
61706 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
61707 
61708 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
61709 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT  (22U)
61710 /*! LPUART3_STOP_REQ - LPUART3 stop request
61711  */
61712 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
61713 
61714 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
61715 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U)
61716 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted.
61717  *  0b0..This module is functional in Stop Mode
61718  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61719  */
61720 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
61721 
61722 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
61723 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT  (24U)
61724 /*! LPUART4_IPG_DOZE - LPUART4 doze mode
61725  */
61726 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
61727 
61728 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
61729 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT  (25U)
61730 /*! LPUART4_STOP_REQ - LPUART4 stop request
61731  */
61732 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
61733 
61734 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
61735 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U)
61736 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted.
61737  *  0b0..This module is functional in Stop Mode
61738  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61739  */
61740 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
61741 
61742 #define IOMUXC_GPR_GPR72_DWP_MASK                (0x30000000U)
61743 #define IOMUXC_GPR_GPR72_DWP_SHIFT               (28U)
61744 /*! DWP - Domain write protection
61745  *  0b00..Both cores are allowed
61746  *  0b01..CM7 is forbidden
61747  *  0b10..CM4 is forbidden
61748  *  0b11..Both cores are forbidden
61749  */
61750 #define IOMUXC_GPR_GPR72_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
61751 
61752 #define IOMUXC_GPR_GPR72_DWP_LOCK_MASK           (0xC0000000U)
61753 #define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT          (30U)
61754 /*! DWP_LOCK - Domain write protection lock
61755  *  0b00..Neither of DWP bits is locked
61756  *  0b01..The lower DWP bit is locked
61757  *  0b10..The higher DWP bit is locked
61758  *  0b11..Both DWP bits are locked
61759  */
61760 #define IOMUXC_GPR_GPR72_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
61761 /*! @} */
61762 
61763 /*! @name GPR73 - GPR73 General Purpose Register */
61764 /*! @{ */
61765 
61766 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
61767 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT  (0U)
61768 /*! LPUART5_IPG_DOZE - LPUART5 doze mode
61769  */
61770 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
61771 
61772 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
61773 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT  (1U)
61774 /*! LPUART5_STOP_REQ - LPUART5 stop request
61775  */
61776 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
61777 
61778 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U)
61779 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U)
61780 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted.
61781  *  0b0..This module is functional in Stop Mode
61782  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61783  */
61784 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
61785 
61786 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
61787 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT  (3U)
61788 /*! LPUART6_IPG_DOZE - LPUART6 doze mode
61789  */
61790 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
61791 
61792 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
61793 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT  (4U)
61794 /*! LPUART6_STOP_REQ - LPUART6 stop request
61795  */
61796 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
61797 
61798 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U)
61799 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U)
61800 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted.
61801  *  0b0..This module is functional in Stop Mode
61802  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61803  */
61804 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
61805 
61806 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
61807 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT  (6U)
61808 /*! LPUART7_IPG_DOZE - LPUART7 doze mode
61809  */
61810 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
61811 
61812 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
61813 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT  (7U)
61814 /*! LPUART7_STOP_REQ - LPUART7 stop request
61815  */
61816 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
61817 
61818 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U)
61819 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U)
61820 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted.
61821  *  0b0..This module is functional in Stop Mode
61822  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61823  */
61824 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
61825 
61826 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
61827 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT  (9U)
61828 /*! LPUART8_IPG_DOZE - LPUART8 doze mode
61829  */
61830 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
61831 
61832 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
61833 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT  (10U)
61834 /*! LPUART8_STOP_REQ - LPUART8 stop request
61835  */
61836 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
61837 
61838 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U)
61839 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U)
61840 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted.
61841  *  0b0..This module is functional in Stop Mode
61842  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61843  */
61844 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
61845 
61846 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
61847 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT  (12U)
61848 /*! LPUART9_IPG_DOZE - LPUART9 doze mode
61849  */
61850 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
61851 
61852 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
61853 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT  (13U)
61854 /*! LPUART9_STOP_REQ - LPUART9 stop request
61855  */
61856 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
61857 
61858 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
61859 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U)
61860 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted.
61861  *  0b0..This module is functional in Stop Mode
61862  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61863  */
61864 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
61865 
61866 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK  (0x8000U)
61867 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U)
61868 /*! LPUART10_IPG_DOZE - LPUART10 doze mode
61869  */
61870 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
61871 
61872 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK  (0x10000U)
61873 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U)
61874 /*! LPUART10_STOP_REQ - LPUART10 stop request
61875  */
61876 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
61877 
61878 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
61879 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U)
61880 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted.
61881  *  0b0..This module is functional in Stop Mode
61882  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61883  */
61884 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
61885 
61886 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK  (0x40000U)
61887 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U)
61888 /*! LPUART11_IPG_DOZE - LPUART11 doze mode
61889  */
61890 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
61891 
61892 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK  (0x80000U)
61893 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U)
61894 /*! LPUART11_STOP_REQ - LPUART11 stop request
61895  */
61896 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
61897 
61898 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
61899 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U)
61900 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted.
61901  *  0b0..This module is functional in Stop Mode
61902  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61903  */
61904 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
61905 
61906 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK  (0x200000U)
61907 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U)
61908 /*! LPUART12_IPG_DOZE - LPUART12 doze mode
61909  */
61910 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
61911 
61912 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK  (0x400000U)
61913 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U)
61914 /*! LPUART12_STOP_REQ - LPUART12 stop request
61915  */
61916 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
61917 
61918 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
61919 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U)
61920 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted.
61921  *  0b0..This module is functional in Stop Mode
61922  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61923  */
61924 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
61925 
61926 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK       (0x1000000U)
61927 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT      (24U)
61928 /*! MIC_IPG_DOZE - MIC doze mode
61929  */
61930 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
61931 
61932 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK       (0x2000000U)
61933 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT      (25U)
61934 /*! MIC_STOP_REQ - MIC stop request
61935  */
61936 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
61937 
61938 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK  (0x4000000U)
61939 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U)
61940 /*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted.
61941  *  0b0..This module is functional in Stop Mode
61942  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61943  */
61944 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
61945 
61946 #define IOMUXC_GPR_GPR73_DWP_MASK                (0x30000000U)
61947 #define IOMUXC_GPR_GPR73_DWP_SHIFT               (28U)
61948 /*! DWP - Domain write protection
61949  *  0b00..Both cores are allowed
61950  *  0b01..CM7 is forbidden
61951  *  0b10..CM4 is forbidden
61952  *  0b11..Both cores are forbidden
61953  */
61954 #define IOMUXC_GPR_GPR73_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
61955 
61956 #define IOMUXC_GPR_GPR73_DWP_LOCK_MASK           (0xC0000000U)
61957 #define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT          (30U)
61958 /*! DWP_LOCK - Domain write protection lock
61959  *  0b00..Neither of DWP bits is locked
61960  *  0b01..The lower DWP bit is locked
61961  *  0b10..The higher DWP bit is locked
61962  *  0b11..Both DWP bits are locked
61963  */
61964 #define IOMUXC_GPR_GPR73_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
61965 /*! @} */
61966 
61967 /*! @name GPR74 - GPR74 General Purpose Register */
61968 /*! @{ */
61969 
61970 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK      (0x2U)
61971 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT     (1U)
61972 /*! PIT1_STOP_REQ - PIT1 stop request
61973  */
61974 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
61975 
61976 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK      (0x4U)
61977 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT     (2U)
61978 /*! PIT2_STOP_REQ - PIT2 stop request
61979  */
61980 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
61981 
61982 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK      (0x8U)
61983 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT     (3U)
61984 /*! SEMC_STOP_REQ - SEMC stop request
61985  */
61986 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
61987 
61988 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK      (0x10U)
61989 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT     (4U)
61990 /*! SIM1_IPG_DOZE - SIM1 doze mode
61991  */
61992 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
61993 
61994 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK      (0x20U)
61995 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT     (5U)
61996 /*! SIM2_IPG_DOZE - SIM2 doze mode
61997  */
61998 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
61999 
62000 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
62001 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT  (6U)
62002 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
62003  */
62004 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
62005 
62006 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
62007 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT  (7U)
62008 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request
62009  */
62010 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
62011 
62012 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK     (0x100U)
62013 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT    (8U)
62014 /*! WDOG1_IPG_DOZE - WDOG1 doze mode
62015  */
62016 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
62017 
62018 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK     (0x200U)
62019 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT    (9U)
62020 /*! WDOG2_IPG_DOZE - WDOG2 doze mode
62021  */
62022 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
62023 
62024 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK      (0x400U)
62025 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT     (10U)
62026 /*! SAI1_STOP_REQ - SAI1 stop request
62027  */
62028 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
62029 
62030 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK      (0x800U)
62031 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT     (11U)
62032 /*! SAI2_STOP_REQ - SAI2 stop request
62033  */
62034 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
62035 
62036 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK      (0x1000U)
62037 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT     (12U)
62038 /*! SAI3_STOP_REQ - SAI3 stop request
62039  */
62040 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
62041 
62042 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK      (0x2000U)
62043 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT     (13U)
62044 /*! SAI4_STOP_REQ - SAI4 stop request
62045  */
62046 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
62047 
62048 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
62049 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
62050 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
62051  */
62052 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
62053 
62054 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
62055 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
62056 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
62057  */
62058 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
62059 
62060 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
62061 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
62062 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
62063  */
62064 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
62065 
62066 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
62067 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
62068 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
62069  */
62070 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
62071 
62072 #define IOMUXC_GPR_GPR74_DWP_MASK                (0x30000000U)
62073 #define IOMUXC_GPR_GPR74_DWP_SHIFT               (28U)
62074 /*! DWP - Domain write protection
62075  *  0b00..Both cores are allowed
62076  *  0b01..CM7 is forbidden
62077  *  0b10..CM4 is forbidden
62078  *  0b11..Both cores are forbidden
62079  */
62080 #define IOMUXC_GPR_GPR74_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
62081 
62082 #define IOMUXC_GPR_GPR74_DWP_LOCK_MASK           (0xC0000000U)
62083 #define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT          (30U)
62084 /*! DWP_LOCK - Domain write protection lock
62085  *  0b00..Neither of DWP bits is locked
62086  *  0b01..The lower DWP bit is locked
62087  *  0b10..The higher DWP bit is locked
62088  *  0b11..Both DWP bits are locked
62089  */
62090 #define IOMUXC_GPR_GPR74_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
62091 /*! @} */
62092 
62093 /*! @name GPR75 - GPR75 General Purpose Register */
62094 /*! @{ */
62095 
62096 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK      (0x1U)
62097 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT     (0U)
62098 /*! ADC1_STOP_ACK - ADC1 stop acknowledge
62099  */
62100 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
62101 
62102 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK      (0x2U)
62103 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT     (1U)
62104 /*! ADC2_STOP_ACK - ADC2 stop acknowledge
62105  */
62106 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
62107 
62108 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK      (0x4U)
62109 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT     (2U)
62110 /*! CAAM_STOP_ACK - CAAM stop acknowledge
62111  */
62112 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
62113 
62114 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK      (0x8U)
62115 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT     (3U)
62116 /*! CAN1_STOP_ACK - CAN1 stop acknowledge
62117  */
62118 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
62119 
62120 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK      (0x10U)
62121 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT     (4U)
62122 /*! CAN2_STOP_ACK - CAN2 stop acknowledge
62123  */
62124 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
62125 
62126 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK      (0x20U)
62127 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT     (5U)
62128 /*! CAN3_STOP_ACK - CAN3 stop acknowledge
62129  */
62130 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
62131 
62132 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK      (0x40U)
62133 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT     (6U)
62134 /*! EDMA_STOP_ACK - EDMA stop acknowledge
62135  */
62136 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
62137 
62138 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U)
62139 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U)
62140 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
62141  */
62142 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
62143 
62144 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK      (0x100U)
62145 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT     (8U)
62146 /*! ENET_STOP_ACK - ENET stop acknowledge
62147  */
62148 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
62149 
62150 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK    (0x200U)
62151 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
62152 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge
62153  */
62154 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
62155 
62156 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK  (0x400U)
62157 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U)
62158 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
62159  */
62160 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
62161 
62162 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK  (0x800U)
62163 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U)
62164 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
62165  */
62166 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
62167 
62168 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK    (0x1000U)
62169 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
62170 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
62171  */
62172 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
62173 
62174 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK    (0x2000U)
62175 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
62176 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
62177  */
62178 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
62179 
62180 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK    (0x4000U)
62181 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
62182 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
62183  */
62184 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
62185 
62186 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK    (0x8000U)
62187 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
62188 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
62189  */
62190 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
62191 
62192 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK    (0x10000U)
62193 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
62194 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
62195  */
62196 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
62197 
62198 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK    (0x20000U)
62199 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
62200 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
62201  */
62202 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
62203 
62204 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK    (0x40000U)
62205 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
62206 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
62207  */
62208 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
62209 
62210 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK    (0x80000U)
62211 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
62212 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
62213  */
62214 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
62215 
62216 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK    (0x100000U)
62217 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
62218 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
62219  */
62220 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
62221 
62222 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK    (0x200000U)
62223 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
62224 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
62225  */
62226 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
62227 
62228 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK    (0x400000U)
62229 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
62230 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
62231  */
62232 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
62233 
62234 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK    (0x800000U)
62235 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
62236 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
62237  */
62238 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
62239 
62240 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
62241 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT  (24U)
62242 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
62243  */
62244 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
62245 
62246 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
62247 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT  (25U)
62248 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
62249  */
62250 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
62251 
62252 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
62253 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT  (26U)
62254 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
62255  */
62256 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
62257 
62258 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
62259 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT  (27U)
62260 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
62261  */
62262 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
62263 
62264 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
62265 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT  (28U)
62266 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
62267  */
62268 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
62269 
62270 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
62271 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT  (29U)
62272 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
62273  */
62274 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
62275 
62276 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
62277 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT  (30U)
62278 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
62279  */
62280 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
62281 
62282 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
62283 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT  (31U)
62284 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
62285  */
62286 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
62287 /*! @} */
62288 
62289 /*! @name GPR76 - GPR76 General Purpose Register */
62290 /*! @{ */
62291 
62292 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
62293 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT  (0U)
62294 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
62295  */
62296 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
62297 
62298 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK  (0x2U)
62299 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U)
62300 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
62301  */
62302 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
62303 
62304 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK  (0x4U)
62305 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U)
62306 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
62307  */
62308 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
62309 
62310 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK  (0x8U)
62311 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U)
62312 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
62313  */
62314 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
62315 
62316 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK       (0x10U)
62317 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT      (4U)
62318 /*! MIC_STOP_ACK - MIC stop acknowledge
62319  */
62320 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
62321 
62322 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK      (0x20U)
62323 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT     (5U)
62324 /*! PIT1_STOP_ACK - PIT1 stop acknowledge
62325  */
62326 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
62327 
62328 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK      (0x40U)
62329 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT     (6U)
62330 /*! PIT2_STOP_ACK - PIT2 stop acknowledge
62331  */
62332 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
62333 
62334 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK      (0x80U)
62335 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT     (7U)
62336 /*! SEMC_STOP_ACK - SEMC stop acknowledge
62337  */
62338 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
62339 
62340 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
62341 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT  (8U)
62342 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
62343  */
62344 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
62345 
62346 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK      (0x200U)
62347 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT     (9U)
62348 /*! SAI1_STOP_ACK - SAI1 stop acknowledge
62349  */
62350 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
62351 
62352 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK      (0x400U)
62353 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT     (10U)
62354 /*! SAI2_STOP_ACK - SAI2 stop acknowledge
62355  */
62356 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
62357 
62358 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK      (0x800U)
62359 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT     (11U)
62360 /*! SAI3_STOP_ACK - SAI3 stop acknowledge
62361  */
62362 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
62363 
62364 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK      (0x1000U)
62365 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT     (12U)
62366 /*! SAI4_STOP_ACK - SAI4 stop acknowledge
62367  */
62368 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
62369 
62370 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
62371 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
62372 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
62373  */
62374 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
62375 
62376 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
62377 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
62378 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
62379  */
62380 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
62381 
62382 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
62383 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
62384 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
62385  */
62386 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
62387 
62388 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
62389 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
62390 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
62391  */
62392 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
62393 /*! @} */
62394 
62395 
62396 /*!
62397  * @}
62398  */ /* end of group IOMUXC_GPR_Register_Masks */
62399 
62400 
62401 /* IOMUXC_GPR - Peripheral instance base addresses */
62402 /** Peripheral IOMUXC_GPR base address */
62403 #define IOMUXC_GPR_BASE                          (0x400E4000u)
62404 /** Peripheral IOMUXC_GPR base pointer */
62405 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
62406 /** Array initializer of IOMUXC_GPR peripheral base addresses */
62407 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
62408 /** Array initializer of IOMUXC_GPR peripheral base pointers */
62409 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
62410 
62411 /*!
62412  * @}
62413  */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
62414 
62415 
62416 /* ----------------------------------------------------------------------------
62417    -- IOMUXC_LPSR Peripheral Access Layer
62418    ---------------------------------------------------------------------------- */
62419 
62420 /*!
62421  * @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer
62422  * @{
62423  */
62424 
62425 /** IOMUXC_LPSR - Register Layout Typedef */
62426 typedef struct {
62427   __IO uint32_t SW_MUX_CTL_PAD[16];                /**< SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4 */
62428   __IO uint32_t SW_PAD_CTL_PAD[16];                /**< SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4 */
62429   __IO uint32_t SELECT_INPUT[24];                  /**< CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4 */
62430 } IOMUXC_LPSR_Type;
62431 
62432 /* ----------------------------------------------------------------------------
62433    -- IOMUXC_LPSR Register Masks
62434    ---------------------------------------------------------------------------- */
62435 
62436 /*!
62437  * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks
62438  * @{
62439  */
62440 
62441 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register */
62442 /*! @{ */
62443 
62444 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
62445 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
62446 /*! MUX_MODE - MUX Mode Select Field.
62447  *  0b1010..Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12
62448  *  0b0000..Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX
62449  *  0b0001..Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11
62450  *  0b0010..Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6
62451  *  0b0011..Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC
62452  *  0b0100..Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6
62453  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6
62454  *  0b0110..Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5
62455  *  0b0111..Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4
62456  *  0b1000..Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12
62457  */
62458 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)
62459 
62460 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK     (0x10U)
62461 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT    (4U)
62462 /*! SION - Software Input On Field.
62463  *  0b1..Force input path of pad GPIO_LPSR_00
62464  *  0b0..Input Path is determined by functionality
62465  */
62466 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)
62467 /*! @} */
62468 
62469 /* The count of IOMUXC_LPSR_SW_MUX_CTL_PAD */
62470 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT         (16U)
62471 
62472 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register */
62473 /*! @{ */
62474 
62475 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK      (0x1U)
62476 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT     (0U)
62477 /*! SRE - Slew Rate Field
62478  *  0b0..Slow Slew Rate
62479  *  0b1..Fast Slew Rate
62480  */
62481 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)
62482 
62483 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK      (0x2U)
62484 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT     (1U)
62485 /*! DSE - Drive Strength Field
62486  *  0b0..normal driver
62487  *  0b1..high driver
62488  */
62489 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)
62490 
62491 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK      (0x4U)
62492 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT     (2U)
62493 /*! PUE - Pull / Keep Select Field
62494  *  0b0..Pull Disable
62495  *  0b1..Pull Enable
62496  */
62497 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)
62498 
62499 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK      (0x8U)
62500 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT     (3U)
62501 /*! PUS - Pull Up / Down Config. Field
62502  *  0b0..Weak pull down
62503  *  0b1..Weak pull up
62504  */
62505 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)
62506 
62507 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)
62508 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)
62509 /*! ODE_LPSR - Open Drain LPSR Field
62510  *  0b0..Disabled
62511  *  0b1..Enabled
62512  */
62513 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)
62514 
62515 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK      (0x30000000U)
62516 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT     (28U)
62517 /*! DWP - Domain write protection
62518  *  0b00..Both cores are allowed
62519  *  0b01..CM7 is forbidden
62520  *  0b10..CM4 is forbidden
62521  *  0b11..Both cores are forbidden
62522  */
62523 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)
62524 
62525 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
62526 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
62527 /*! DWP_LOCK - Domain write protection lock
62528  *  0b00..Neither of DWP bits is locked
62529  *  0b01..The lower DWP bit is locked
62530  *  0b10..The higher DWP bit is locked
62531  *  0b11..Both DWP bits are locked
62532  */
62533 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
62534 /*! @} */
62535 
62536 /* The count of IOMUXC_LPSR_SW_PAD_CTL_PAD */
62537 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT         (16U)
62538 
62539 /*! @name SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */
62540 /*! @{ */
62541 
62542 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK      (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
62543 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT     (0U)
62544 /*! DAISY - Selecting Pads Involved in Daisy Chain.
62545  *  0b00..Selecting Pad: GPIO_LPSR_00 for Mode: ALT6
62546  *  0b01..Selecting Pad: GPIO_LPSR_06 for Mode: ALT3
62547  *  0b10..Selecting Pad: GPIO_LPSR_10 for Mode: ALT8
62548  */
62549 #define IOMUXC_LPSR_SELECT_INPUT_DAISY(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
62550 /*! @} */
62551 
62552 /* The count of IOMUXC_LPSR_SELECT_INPUT */
62553 #define IOMUXC_LPSR_SELECT_INPUT_COUNT           (24U)
62554 
62555 
62556 /*!
62557  * @}
62558  */ /* end of group IOMUXC_LPSR_Register_Masks */
62559 
62560 
62561 /* IOMUXC_LPSR - Peripheral instance base addresses */
62562 /** Peripheral IOMUXC_LPSR base address */
62563 #define IOMUXC_LPSR_BASE                         (0x40C08000u)
62564 /** Peripheral IOMUXC_LPSR base pointer */
62565 #define IOMUXC_LPSR                              ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
62566 /** Array initializer of IOMUXC_LPSR peripheral base addresses */
62567 #define IOMUXC_LPSR_BASE_ADDRS                   { IOMUXC_LPSR_BASE }
62568 /** Array initializer of IOMUXC_LPSR peripheral base pointers */
62569 #define IOMUXC_LPSR_BASE_PTRS                    { IOMUXC_LPSR }
62570 
62571 /*!
62572  * @}
62573  */ /* end of group IOMUXC_LPSR_Peripheral_Access_Layer */
62574 
62575 
62576 /* ----------------------------------------------------------------------------
62577    -- IOMUXC_LPSR_GPR Peripheral Access Layer
62578    ---------------------------------------------------------------------------- */
62579 
62580 /*!
62581  * @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer
62582  * @{
62583  */
62584 
62585 /** IOMUXC_LPSR_GPR - Register Layout Typedef */
62586 typedef struct {
62587   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
62588   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
62589   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
62590   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
62591   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
62592   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
62593   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
62594   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
62595   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
62596   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
62597   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
62598   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
62599   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
62600   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
62601   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
62602   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
62603   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
62604   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
62605   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
62606   __IO uint32_t GPR19;                             /**< GPR19 General Purpose Register, offset: 0x4C */
62607   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
62608   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
62609   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
62610   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
62611   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
62612   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
62613   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
62614        uint8_t RESERVED_0[24];
62615   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
62616   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
62617   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
62618   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
62619   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
62620   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
62621   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
62622   __I  uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
62623   __I  uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
62624 } IOMUXC_LPSR_GPR_Type;
62625 
62626 /* ----------------------------------------------------------------------------
62627    -- IOMUXC_LPSR_GPR Register Masks
62628    ---------------------------------------------------------------------------- */
62629 
62630 /*!
62631  * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks
62632  * @{
62633  */
62634 
62635 /*! @name GPR0 - GPR0 General Purpose Register */
62636 /*! @{ */
62637 
62638 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U)
62639 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U)
62640 /*! CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset
62641  */
62642 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
62643 
62644 #define IOMUXC_LPSR_GPR_GPR0_DWP_MASK            (0x30000000U)
62645 #define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT           (28U)
62646 /*! DWP - Domain write protection
62647  *  0b00..Both cores are allowed
62648  *  0b01..CM7 is forbidden
62649  *  0b10..CM4 is forbidden
62650  *  0b11..Both cores are forbidden
62651  */
62652 #define IOMUXC_LPSR_GPR_GPR0_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
62653 
62654 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK       (0xC0000000U)
62655 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT      (30U)
62656 /*! DWP_LOCK - Domain write protection lock
62657  *  0b00..Neither of DWP bits is locked
62658  *  0b01..The lower DWP bit is locked
62659  *  0b10..The higher DWP bit is locked
62660  *  0b11..Both DWP bits are locked
62661  */
62662 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
62663 /*! @} */
62664 
62665 /*! @name GPR1 - GPR1 General Purpose Register */
62666 /*! @{ */
62667 
62668 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU)
62669 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U)
62670 /*! CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset
62671  */
62672 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
62673 
62674 #define IOMUXC_LPSR_GPR_GPR1_DWP_MASK            (0x30000000U)
62675 #define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT           (28U)
62676 /*! DWP - Domain write protection
62677  *  0b00..Both cores are allowed
62678  *  0b01..CM7 is forbidden
62679  *  0b10..CM4 is forbidden
62680  *  0b11..Both cores are forbidden
62681  */
62682 #define IOMUXC_LPSR_GPR_GPR1_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
62683 
62684 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK       (0xC0000000U)
62685 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT      (30U)
62686 /*! DWP_LOCK - Domain write protection lock
62687  *  0b00..Neither of DWP bits is locked
62688  *  0b01..The lower DWP bit is locked
62689  *  0b10..The higher DWP bit is locked
62690  *  0b11..Both DWP bits are locked
62691  */
62692 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
62693 /*! @} */
62694 
62695 /*! @name GPR2 - GPR2 General Purpose Register */
62696 /*! @{ */
62697 
62698 #define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK           (0x1U)
62699 #define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT          (0U)
62700 /*! LOCK - Lock the write to bit 31:1
62701  *  0b1..Write access to bit 31:1 is blocked
62702  *  0b0..Write access to bit 31:1 is not blocked
62703  */
62704 #define IOMUXC_LPSR_GPR_GPR2_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
62705 
62706 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK  (0xFFFFFFF8U)
62707 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U)
62708 /*! APC_AC_R0_BOT - APC start address of memory region-0
62709  */
62710 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
62711 /*! @} */
62712 
62713 /*! @name GPR3 - GPR3 General Purpose Register */
62714 /*! @{ */
62715 
62716 #define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK           (0x1U)
62717 #define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT          (0U)
62718 /*! LOCK - Lock the write to bit 31:1
62719  *  0b1..Write access to bit 31:1 is blocked
62720  *  0b0..Write access to bit 31:1 is not blocked
62721  */
62722 #define IOMUXC_LPSR_GPR_GPR3_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
62723 
62724 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK  (0xFFFFFFF8U)
62725 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U)
62726 /*! APC_AC_R0_TOP - APC end address of memory region-0
62727  */
62728 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
62729 /*! @} */
62730 
62731 /*! @name GPR4 - GPR4 General Purpose Register */
62732 /*! @{ */
62733 
62734 #define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK           (0x1U)
62735 #define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT          (0U)
62736 /*! LOCK - Lock the write to bit 31:1
62737  *  0b1..Write access to bit 31:1 is blocked
62738  *  0b0..Write access to bit 31:1 is not blocked
62739  */
62740 #define IOMUXC_LPSR_GPR_GPR4_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
62741 
62742 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK  (0xFFFFFFF8U)
62743 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U)
62744 /*! APC_AC_R1_BOT - APC start address of memory region-1
62745  */
62746 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
62747 /*! @} */
62748 
62749 /*! @name GPR5 - GPR5 General Purpose Register */
62750 /*! @{ */
62751 
62752 #define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK           (0x1U)
62753 #define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT          (0U)
62754 /*! LOCK - Lock the write to bit 31:1
62755  *  0b1..Write access to bit 31:1 is blocked
62756  *  0b0..Write access to bit 31:1 is not blocked
62757  */
62758 #define IOMUXC_LPSR_GPR_GPR5_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
62759 
62760 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK  (0xFFFFFFF8U)
62761 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U)
62762 /*! APC_AC_R1_TOP - APC end address of memory region-1
62763  */
62764 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
62765 /*! @} */
62766 
62767 /*! @name GPR6 - GPR6 General Purpose Register */
62768 /*! @{ */
62769 
62770 #define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK           (0x1U)
62771 #define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT          (0U)
62772 /*! LOCK - Lock the write to bit 31:1
62773  *  0b1..Write access to bit 31:1 is blocked
62774  *  0b0..Write access to bit 31:1 is not blocked
62775  */
62776 #define IOMUXC_LPSR_GPR_GPR6_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK)
62777 
62778 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK  (0xFFFFFFF8U)
62779 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U)
62780 /*! APC_AC_R2_BOT - APC start address of memory region-2
62781  */
62782 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK)
62783 /*! @} */
62784 
62785 /*! @name GPR7 - GPR7 General Purpose Register */
62786 /*! @{ */
62787 
62788 #define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK           (0x1U)
62789 #define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT          (0U)
62790 /*! LOCK - Lock the write to bit 31:1
62791  *  0b1..Write access to bit 31:1 is blocked
62792  *  0b0..Write access to bit 31:1 is not blocked
62793  */
62794 #define IOMUXC_LPSR_GPR_GPR7_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
62795 
62796 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK  (0xFFFFFFF8U)
62797 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U)
62798 /*! APC_AC_R2_TOP - APC end address of memory region-2
62799  */
62800 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
62801 /*! @} */
62802 
62803 /*! @name GPR8 - GPR8 General Purpose Register */
62804 /*! @{ */
62805 
62806 #define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK           (0x1U)
62807 #define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT          (0U)
62808 /*! LOCK - Lock the write to bit 31:1
62809  *  0b1..Write access to bit 31:1 is blocked
62810  *  0b0..Write access to bit 31:1 is not blocked
62811  */
62812 #define IOMUXC_LPSR_GPR_GPR8_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
62813 
62814 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK  (0xFFFFFFF8U)
62815 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U)
62816 /*! APC_AC_R3_BOT - APC start address of memory region-3
62817  */
62818 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
62819 /*! @} */
62820 
62821 /*! @name GPR9 - GPR9 General Purpose Register */
62822 /*! @{ */
62823 
62824 #define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK           (0x1U)
62825 #define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT          (0U)
62826 /*! LOCK - Lock the write to bit 31:1
62827  *  0b1..Write access to bit 31:1 is blocked
62828  *  0b0..Write access to bit 31:1 is not blocked
62829  */
62830 #define IOMUXC_LPSR_GPR_GPR9_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
62831 
62832 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK  (0xFFFFFFF8U)
62833 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U)
62834 /*! APC_AC_R3_TOP - APC end address of memory region-3
62835  */
62836 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
62837 /*! @} */
62838 
62839 /*! @name GPR10 - GPR10 General Purpose Register */
62840 /*! @{ */
62841 
62842 #define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK          (0x1U)
62843 #define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT         (0U)
62844 /*! LOCK - Lock the write to bit 31:1
62845  *  0b1..Write access to bit 31:1 is blocked
62846  *  0b0..Write access to bit 31:1 is not blocked
62847  */
62848 #define IOMUXC_LPSR_GPR_GPR10_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
62849 
62850 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U)
62851 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U)
62852 /*! APC_AC_R4_BOT - APC start address of memory region-4
62853  */
62854 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
62855 /*! @} */
62856 
62857 /*! @name GPR11 - GPR11 General Purpose Register */
62858 /*! @{ */
62859 
62860 #define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK          (0x1U)
62861 #define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT         (0U)
62862 /*! LOCK - Lock the write to bit 31:1
62863  *  0b1..Write access to bit 31:1 is blocked
62864  *  0b0..Write access to bit 31:1 is not blocked
62865  */
62866 #define IOMUXC_LPSR_GPR_GPR11_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
62867 
62868 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U)
62869 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U)
62870 /*! APC_AC_R4_TOP - APC end address of memory region-4
62871  */
62872 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
62873 /*! @} */
62874 
62875 /*! @name GPR12 - GPR12 General Purpose Register */
62876 /*! @{ */
62877 
62878 #define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK          (0x1U)
62879 #define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT         (0U)
62880 /*! LOCK - Lock the write to bit 31:1
62881  *  0b1..Write access to bit 31:1 is blocked
62882  *  0b0..Write access to bit 31:1 is not blocked
62883  */
62884 #define IOMUXC_LPSR_GPR_GPR12_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
62885 
62886 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U)
62887 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U)
62888 /*! APC_AC_R5_BOT - APC start address of memory region-5
62889  */
62890 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
62891 /*! @} */
62892 
62893 /*! @name GPR13 - GPR13 General Purpose Register */
62894 /*! @{ */
62895 
62896 #define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK          (0x1U)
62897 #define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT         (0U)
62898 /*! LOCK - Lock the write to bit 31:1
62899  *  0b1..Write access to bit 31:1 is blocked
62900  *  0b0..Write access to bit 31:1 is not blocked
62901  */
62902 #define IOMUXC_LPSR_GPR_GPR13_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
62903 
62904 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U)
62905 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U)
62906 /*! APC_AC_R5_TOP - APC end address of memory region-5
62907  */
62908 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
62909 /*! @} */
62910 
62911 /*! @name GPR14 - GPR14 General Purpose Register */
62912 /*! @{ */
62913 
62914 #define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK          (0x1U)
62915 #define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT         (0U)
62916 /*! LOCK - Lock the write to bit 31:1
62917  *  0b1..Write access to bit 31:1 is blocked
62918  *  0b0..Write access to bit 31:1 is not blocked
62919  */
62920 #define IOMUXC_LPSR_GPR_GPR14_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
62921 
62922 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U)
62923 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U)
62924 /*! APC_AC_R6_BOT - APC start address of memory region-6
62925  */
62926 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
62927 /*! @} */
62928 
62929 /*! @name GPR15 - GPR15 General Purpose Register */
62930 /*! @{ */
62931 
62932 #define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK          (0x1U)
62933 #define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT         (0U)
62934 /*! LOCK - Lock the write to bit 31:1
62935  *  0b1..Write access to bit 31:1 is blocked
62936  *  0b0..Write access to bit 31:1 is not blocked
62937  */
62938 #define IOMUXC_LPSR_GPR_GPR15_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
62939 
62940 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U)
62941 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U)
62942 /*! APC_AC_R6_TOP - APC end address of memory region-6
62943  */
62944 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
62945 /*! @} */
62946 
62947 /*! @name GPR16 - GPR16 General Purpose Register */
62948 /*! @{ */
62949 
62950 #define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK          (0x1U)
62951 #define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT         (0U)
62952 /*! LOCK - Lock the write to bit 31:1
62953  *  0b1..Write access to bit 31:1 is blocked
62954  *  0b0..Write access to bit 31:1 is not blocked
62955  */
62956 #define IOMUXC_LPSR_GPR_GPR16_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
62957 
62958 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U)
62959 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U)
62960 /*! APC_AC_R7_BOT - APC start address of memory region-7
62961  */
62962 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
62963 /*! @} */
62964 
62965 /*! @name GPR17 - GPR17 General Purpose Register */
62966 /*! @{ */
62967 
62968 #define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK          (0x1U)
62969 #define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT         (0U)
62970 /*! LOCK - Lock the write to bit 31:1
62971  *  0b1..Write access to bit 31:1 is blocked
62972  *  0b0..Write access to bit 31:1 is not blocked
62973  */
62974 #define IOMUXC_LPSR_GPR_GPR17_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
62975 
62976 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U)
62977 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U)
62978 /*! APC_AC_R7_TOP - APC end address of memory region-7
62979  */
62980 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
62981 /*! @} */
62982 
62983 /*! @name GPR18 - GPR18 General Purpose Register */
62984 /*! @{ */
62985 
62986 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U)
62987 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U)
62988 /*! APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable
62989  *  0b1..Encryption enabled
62990  *  0b0..No effect
62991  */
62992 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
62993 
62994 #define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK          (0xFFFF0000U)
62995 #define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT         (16U)
62996 /*! LOCK - Lock the write to bit 15:0
62997  */
62998 #define IOMUXC_LPSR_GPR_GPR18_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
62999 /*! @} */
63000 
63001 /*! @name GPR19 - GPR19 General Purpose Register */
63002 /*! @{ */
63003 
63004 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U)
63005 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U)
63006 /*! APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable
63007  *  0b1..Encryption enabled
63008  *  0b0..No effect
63009  */
63010 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK)
63011 
63012 #define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK          (0xFFFF0000U)
63013 #define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT         (16U)
63014 /*! LOCK - Lock the write to bit 15:0
63015  */
63016 #define IOMUXC_LPSR_GPR_GPR19_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK)
63017 /*! @} */
63018 
63019 /*! @name GPR20 - GPR20 General Purpose Register */
63020 /*! @{ */
63021 
63022 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U)
63023 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U)
63024 /*! APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable
63025  *  0b1..Encryption enabled
63026  *  0b0..No effect
63027  */
63028 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
63029 
63030 #define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK          (0xFFFF0000U)
63031 #define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT         (16U)
63032 /*! LOCK - Lock the write to bit 15:0
63033  */
63034 #define IOMUXC_LPSR_GPR_GPR20_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
63035 /*! @} */
63036 
63037 /*! @name GPR21 - GPR21 General Purpose Register */
63038 /*! @{ */
63039 
63040 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U)
63041 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U)
63042 /*! APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable
63043  *  0b1..Encryption enabled
63044  *  0b0..No effect
63045  */
63046 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
63047 
63048 #define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK          (0xFFFF0000U)
63049 #define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT         (16U)
63050 /*! LOCK - Lock the write to bit 15:0
63051  */
63052 #define IOMUXC_LPSR_GPR_GPR21_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
63053 /*! @} */
63054 
63055 /*! @name GPR22 - GPR22 General Purpose Register */
63056 /*! @{ */
63057 
63058 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U)
63059 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U)
63060 /*! APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable
63061  *  0b1..Encryption enabled
63062  *  0b0..No effect
63063  */
63064 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
63065 
63066 #define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK          (0xFFFF0000U)
63067 #define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT         (16U)
63068 /*! LOCK - Lock the write to bit 15:0
63069  */
63070 #define IOMUXC_LPSR_GPR_GPR22_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
63071 /*! @} */
63072 
63073 /*! @name GPR23 - GPR23 General Purpose Register */
63074 /*! @{ */
63075 
63076 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U)
63077 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U)
63078 /*! APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable
63079  *  0b1..Encryption enabled
63080  *  0b0..No effect
63081  */
63082 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
63083 
63084 #define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK          (0xFFFF0000U)
63085 #define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT         (16U)
63086 /*! LOCK - Lock the write to bit 15:0
63087  */
63088 #define IOMUXC_LPSR_GPR_GPR23_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
63089 /*! @} */
63090 
63091 /*! @name GPR24 - GPR24 General Purpose Register */
63092 /*! @{ */
63093 
63094 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U)
63095 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U)
63096 /*! APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable
63097  *  0b1..Encryption enabled
63098  *  0b0..No effect
63099  */
63100 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
63101 
63102 #define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK          (0xFFFF0000U)
63103 #define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT         (16U)
63104 /*! LOCK - Lock the write to bit 15:0
63105  */
63106 #define IOMUXC_LPSR_GPR_GPR24_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
63107 /*! @} */
63108 
63109 /*! @name GPR25 - GPR25 General Purpose Register */
63110 /*! @{ */
63111 
63112 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U)
63113 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U)
63114 /*! APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable
63115  *  0b1..Encryption enabled
63116  *  0b0..No effect
63117  */
63118 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
63119 
63120 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK     (0x20U)
63121 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT    (5U)
63122 /*! APC_VALID - APC global enable bit
63123  *  0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25)
63124  *  0b0..No effect
63125  */
63126 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
63127 
63128 #define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK          (0xFFFF0000U)
63129 #define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT         (16U)
63130 /*! LOCK - Lock the write to bit 15:0
63131  */
63132 #define IOMUXC_LPSR_GPR_GPR25_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
63133 /*! @} */
63134 
63135 /*! @name GPR26 - GPR26 General Purpose Register */
63136 /*! @{ */
63137 
63138 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU)
63139 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U)
63140 /*! CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture
63141  *    Reference Manual for more information about the vector table offset register (VTOR).
63142  */
63143 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
63144 
63145 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK       (0xE000000U)
63146 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT      (25U)
63147 /*! FIELD_0 - General purpose bits
63148  */
63149 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
63150 
63151 #define IOMUXC_LPSR_GPR_GPR26_DWP_MASK           (0x30000000U)
63152 #define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT          (28U)
63153 /*! DWP - Domain write protection
63154  *  0b00..Both cores are allowed
63155  *  0b01..CM7 is forbidden
63156  *  0b10..CM4 is forbidden
63157  *  0b11..Both cores are forbidden
63158  */
63159 #define IOMUXC_LPSR_GPR_GPR26_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
63160 
63161 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK      (0xC0000000U)
63162 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT     (30U)
63163 /*! DWP_LOCK - Domain write protection lock
63164  *  0b00..Neither of DWP bits is locked
63165  *  0b01..The lower DWP bit is locked
63166  *  0b10..The higher DWP bit is locked
63167  *  0b11..Both DWP bits are locked
63168  */
63169 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
63170 /*! @} */
63171 
63172 /*! @name GPR33 - GPR33 General Purpose Register */
63173 /*! @{ */
63174 
63175 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK  (0x1U)
63176 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U)
63177 /*! M4_NMI_CLEAR - Clear CM4 NMI holding register
63178  */
63179 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
63180 
63181 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U)
63182 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U)
63183 /*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
63184  */
63185 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
63186 
63187 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U)
63188 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U)
63189 /*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
63190  */
63191 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
63192 
63193 #define IOMUXC_LPSR_GPR_GPR33_DWP_MASK           (0x30000000U)
63194 #define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT          (28U)
63195 /*! DWP - Domain write protection
63196  *  0b00..Both cores are allowed
63197  *  0b01..CM7 is forbidden
63198  *  0b10..CM4 is forbidden
63199  *  0b11..Both cores are forbidden
63200  */
63201 #define IOMUXC_LPSR_GPR_GPR33_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
63202 
63203 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK      (0xC0000000U)
63204 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT     (30U)
63205 /*! DWP_LOCK - Domain write protection lock
63206  *  0b00..Neither of DWP bits is locked
63207  *  0b01..The lower DWP bit is locked
63208  *  0b10..The higher DWP bit is locked
63209  *  0b11..Both DWP bits are locked
63210  */
63211 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
63212 /*! @} */
63213 
63214 /*! @name GPR34 - GPR34 General Purpose Register */
63215 /*! @{ */
63216 
63217 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U)
63218 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U)
63219 /*! GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection
63220  */
63221 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
63222 
63223 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U)
63224 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U)
63225 /*! GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection
63226  */
63227 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
63228 
63229 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
63230 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT  (3U)
63231 /*! M7_NMI_MASK - Mask CM7 NMI pin input
63232  *  0b0..NMI input from IO to CM7 is not blocked
63233  *  0b1..NMI input from IO to CM7 is blocked
63234  */
63235 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
63236 
63237 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
63238 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT  (4U)
63239 /*! M4_NMI_MASK - Mask CM4 NMI pin input
63240  *  0b0..NMI input from IO to CM4 is not blocked
63241  *  0b1..NMI input from IO to CM4 is blocked
63242  */
63243 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
63244 
63245 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U)
63246 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U)
63247 /*! M4_GPC_SLEEP_SEL - CM4 sleep request selection
63248  *  0b0..CM4 SLEEPDEEP is sent to GPC
63249  *  0b1..CM4 SLEEPING is sent to GPC
63250  */
63251 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
63252 
63253 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK  (0x800U)
63254 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U)
63255 /*! SEC_ERR_RESP - Security error response enable
63256  *  0b0..OKEY response
63257  *  0b1..SLVError (default)
63258  */
63259 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
63260 
63261 #define IOMUXC_LPSR_GPR_GPR34_DWP_MASK           (0x30000000U)
63262 #define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT          (28U)
63263 /*! DWP - Domain write protection
63264  *  0b00..Both cores are allowed
63265  *  0b01..CM7 is forbidden
63266  *  0b10..CM4 is forbidden
63267  *  0b11..Both cores are forbidden
63268  */
63269 #define IOMUXC_LPSR_GPR_GPR34_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
63270 
63271 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK      (0xC0000000U)
63272 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT     (30U)
63273 /*! DWP_LOCK - Domain write protection lock
63274  *  0b00..Neither of DWP bits is locked
63275  *  0b01..The lower DWP bit is locked
63276  *  0b10..The higher DWP bit is locked
63277  *  0b11..Both DWP bits are locked
63278  */
63279 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
63280 /*! @} */
63281 
63282 /*! @name GPR35 - GPR35 General Purpose Register */
63283 /*! @{ */
63284 
63285 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U)
63286 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U)
63287 /*! ADC1_IPG_DOZE - ADC1 doze mode
63288  *  0b0..Not in doze mode
63289  *  0b1..In doze mode
63290  */
63291 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
63292 
63293 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U)
63294 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U)
63295 /*! ADC1_STOP_REQ - ADC1 stop request
63296  *  0b0..Stop request off
63297  *  0b1..Stop request on
63298  */
63299 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
63300 
63301 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U)
63302 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U)
63303 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted.
63304  *  0b0..This module is functional in Stop Mode
63305  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63306  */
63307 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
63308 
63309 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U)
63310 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U)
63311 /*! ADC2_IPG_DOZE - ADC2 doze mode
63312  *  0b0..Not in doze mode
63313  *  0b1..In doze mode
63314  */
63315 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
63316 
63317 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U)
63318 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U)
63319 /*! ADC2_STOP_REQ - ADC2 stop request
63320  *  0b0..Stop request off
63321  *  0b1..Stop request on
63322  */
63323 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
63324 
63325 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U)
63326 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U)
63327 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted.
63328  *  0b0..This module is functional in Stop Mode
63329  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63330  */
63331 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
63332 
63333 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U)
63334 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U)
63335 /*! CAAM_IPG_DOZE - CAN3 doze mode
63336  *  0b0..Not in doze mode
63337  *  0b1..In doze mode
63338  */
63339 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
63340 
63341 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U)
63342 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U)
63343 /*! CAAM_STOP_REQ - CAAM stop request
63344  *  0b0..Stop request off
63345  *  0b1..Stop request on
63346  */
63347 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
63348 
63349 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U)
63350 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U)
63351 /*! CAN1_IPG_DOZE - CAN1 doze mode
63352  *  0b0..Not in doze mode
63353  *  0b1..In doze mode
63354  */
63355 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
63356 
63357 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U)
63358 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U)
63359 /*! CAN1_STOP_REQ - CAN1 stop request
63360  *  0b0..Stop request off
63361  *  0b1..Stop request on
63362  */
63363 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
63364 
63365 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U)
63366 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U)
63367 /*! CAN2_IPG_DOZE - CAN2 doze mode
63368  *  0b0..Not in doze mode
63369  *  0b1..In doze mode
63370  */
63371 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
63372 
63373 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U)
63374 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U)
63375 /*! CAN2_STOP_REQ - CAN2 stop request
63376  *  0b0..Stop request off
63377  *  0b1..Stop request on
63378  */
63379 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
63380 
63381 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U)
63382 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U)
63383 /*! CAN3_IPG_DOZE - CAN3 doze mode
63384  *  0b0..Not in doze mode
63385  *  0b1..In doze mode
63386  */
63387 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
63388 
63389 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U)
63390 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U)
63391 /*! CAN3_STOP_REQ - CAN3 stop request
63392  *  0b0..Stop request off
63393  *  0b1..Stop request on
63394  */
63395 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
63396 
63397 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U)
63398 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U)
63399 /*! EDMA_STOP_REQ - EDMA stop request
63400  *  0b0..Stop request off
63401  *  0b1..Stop request on
63402  */
63403 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
63404 
63405 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
63406 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U)
63407 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
63408  *  0b0..Stop request off
63409  *  0b1..Stop request on
63410  */
63411 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
63412 
63413 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U)
63414 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U)
63415 /*! ENET_IPG_DOZE - ENET doze mode
63416  *  0b0..Not in doze mode
63417  *  0b1..In doze mode
63418  */
63419 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
63420 
63421 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U)
63422 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U)
63423 /*! ENET_STOP_REQ - ENET stop request
63424  *  0b0..Stop request off
63425  *  0b1..Stop request on
63426  */
63427 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
63428 
63429 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U)
63430 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U)
63431 /*! ENET1G_IPG_DOZE - ENET1G doze mode
63432  *  0b0..Not in doze mode
63433  *  0b1..In doze mode
63434  */
63435 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
63436 
63437 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U)
63438 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U)
63439 /*! ENET1G_STOP_REQ - ENET1G stop request
63440  *  0b0..Stop request off
63441  *  0b1..Stop request on
63442  */
63443 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
63444 
63445 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U)
63446 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U)
63447 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
63448  *  0b0..Not in doze mode
63449  *  0b1..In doze mode
63450  */
63451 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
63452 
63453 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U)
63454 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U)
63455 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
63456  *  0b0..Not in doze mode
63457  *  0b1..In doze mode
63458  */
63459 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
63460 
63461 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
63462 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U)
63463 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
63464  *  0b0..Not in doze mode
63465  *  0b1..In doze mode
63466  */
63467 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
63468 
63469 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
63470 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U)
63471 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
63472  *  0b0..Stop request off
63473  *  0b1..Stop request on
63474  */
63475 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
63476 
63477 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
63478 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U)
63479 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
63480  *  0b0..Not in doze mode
63481  *  0b1..In doze mode
63482  */
63483 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
63484 
63485 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
63486 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U)
63487 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
63488  *  0b0..Stop request off
63489  *  0b1..Stop request on
63490  */
63491 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
63492 
63493 #define IOMUXC_LPSR_GPR_GPR35_DWP_MASK           (0x30000000U)
63494 #define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT          (28U)
63495 /*! DWP - Domain write protection
63496  *  0b00..Both cores are allowed
63497  *  0b01..CM7 is forbidden
63498  *  0b10..CM4 is forbidden
63499  *  0b11..Both cores are forbidden
63500  */
63501 #define IOMUXC_LPSR_GPR_GPR35_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
63502 
63503 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK      (0xC0000000U)
63504 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT     (30U)
63505 /*! DWP_LOCK - Domain write protection lock
63506  *  0b00..Neither of DWP bits is locked
63507  *  0b01..The lower DWP bit is locked
63508  *  0b10..The higher DWP bit is locked
63509  *  0b11..Both DWP bits are locked
63510  */
63511 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
63512 /*! @} */
63513 
63514 /*! @name GPR36 - GPR36 General Purpose Register */
63515 /*! @{ */
63516 
63517 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U)
63518 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U)
63519 /*! GPT1_IPG_DOZE - GPT1 doze mode
63520  *  0b0..Not in doze mode
63521  *  0b1..In doze mode
63522  */
63523 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
63524 
63525 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U)
63526 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U)
63527 /*! GPT2_IPG_DOZE - GPT2 doze mode
63528  *  0b0..Not in doze mode
63529  *  0b1..In doze mode
63530  */
63531 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
63532 
63533 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U)
63534 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U)
63535 /*! GPT3_IPG_DOZE - GPT3 doze mode
63536  *  0b0..Not in doze mode
63537  *  0b1..In doze mode
63538  */
63539 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
63540 
63541 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U)
63542 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U)
63543 /*! GPT4_IPG_DOZE - GPT4 doze mode
63544  *  0b0..Not in doze mode
63545  *  0b1..In doze mode
63546  */
63547 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
63548 
63549 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U)
63550 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U)
63551 /*! GPT5_IPG_DOZE - GPT5 doze mode
63552  *  0b0..Not in doze mode
63553  *  0b1..In doze mode
63554  */
63555 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
63556 
63557 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U)
63558 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U)
63559 /*! GPT6_IPG_DOZE - GPT6 doze mode
63560  *  0b0..Not in doze mode
63561  *  0b1..In doze mode
63562  */
63563 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
63564 
63565 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U)
63566 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U)
63567 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
63568  *  0b0..Not in doze mode
63569  *  0b1..In doze mode
63570  */
63571 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
63572 
63573 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U)
63574 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U)
63575 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
63576  *  0b0..Stop request off
63577  *  0b1..Stop request on
63578  */
63579 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
63580 
63581 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
63582 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
63583 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted.
63584  *  0b0..This module is functional in Stop Mode
63585  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63586  */
63587 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
63588 
63589 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U)
63590 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U)
63591 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
63592  *  0b0..Not in doze mode
63593  *  0b1..In doze mode
63594  */
63595 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
63596 
63597 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U)
63598 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U)
63599 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
63600  *  0b0..Stop request off
63601  *  0b1..Stop request on
63602  */
63603 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
63604 
63605 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
63606 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
63607 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted.
63608  *  0b0..This module is functional in Stop Mode
63609  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63610  */
63611 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
63612 
63613 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U)
63614 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U)
63615 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
63616  *  0b0..Not in doze mode
63617  *  0b1..In doze mode
63618  */
63619 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
63620 
63621 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U)
63622 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U)
63623 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
63624  *  0b0..Stop request off
63625  *  0b1..Stop request on
63626  */
63627 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
63628 
63629 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
63630 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
63631 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted.
63632  *  0b0..This module is functional in Stop Mode
63633  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63634  */
63635 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
63636 
63637 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U)
63638 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U)
63639 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
63640  *  0b0..Not in doze mode
63641  *  0b1..In doze mode
63642  */
63643 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
63644 
63645 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U)
63646 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U)
63647 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
63648  *  0b0..Stop request off
63649  *  0b1..Stop request on
63650  */
63651 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
63652 
63653 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
63654 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
63655 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted.
63656  *  0b0..This module is functional in Stop Mode
63657  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63658  */
63659 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
63660 
63661 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U)
63662 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U)
63663 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
63664  *  0b0..Not in doze mode
63665  *  0b1..In doze mode
63666  */
63667 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
63668 
63669 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U)
63670 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U)
63671 /*! LPI2C5_STOP_REQ - LPI2C5 stop request
63672  *  0b0..Stop request off
63673  *  0b1..Stop request on
63674  */
63675 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
63676 
63677 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
63678 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
63679 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted.
63680  *  0b0..This module is functional in Stop Mode
63681  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63682  */
63683 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
63684 
63685 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U)
63686 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U)
63687 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
63688  *  0b0..Not in doze mode
63689  *  0b1..In doze mode
63690  */
63691 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
63692 
63693 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U)
63694 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U)
63695 /*! LPI2C6_STOP_REQ - LPI2C6 stop request
63696  *  0b0..Stop request off
63697  *  0b1..Stop request on
63698  */
63699 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
63700 
63701 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
63702 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
63703 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted.
63704  *  0b0..This module is functional in Stop Mode
63705  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63706  */
63707 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
63708 
63709 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U)
63710 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U)
63711 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
63712  *  0b0..Not in doze mode
63713  *  0b1..In doze mode
63714  */
63715 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
63716 
63717 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U)
63718 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U)
63719 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
63720  *  0b0..Stop request off
63721  *  0b1..Stop request on
63722  */
63723 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
63724 
63725 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
63726 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
63727 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted.
63728  *  0b0..This module is functional in Stop Mode
63729  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63730  */
63731 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
63732 
63733 #define IOMUXC_LPSR_GPR_GPR36_DWP_MASK           (0x30000000U)
63734 #define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT          (28U)
63735 /*! DWP - Domain write protection
63736  *  0b00..Both cores are allowed
63737  *  0b01..CM7 is forbidden
63738  *  0b10..CM4 is forbidden
63739  *  0b11..Both cores are forbidden
63740  */
63741 #define IOMUXC_LPSR_GPR_GPR36_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
63742 
63743 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK      (0xC0000000U)
63744 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT     (30U)
63745 /*! DWP_LOCK - Domain write protection lock
63746  *  0b00..Neither of DWP bits is locked
63747  *  0b01..The lower DWP bit is locked
63748  *  0b10..The higher DWP bit is locked
63749  *  0b11..Both DWP bits are locked
63750  */
63751 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
63752 /*! @} */
63753 
63754 /*! @name GPR37 - GPR37 General Purpose Register */
63755 /*! @{ */
63756 
63757 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U)
63758 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U)
63759 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
63760  *  0b0..Not in doze mode
63761  *  0b1..In doze mode
63762  */
63763 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
63764 
63765 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U)
63766 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U)
63767 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
63768  *  0b0..Stop request off
63769  *  0b1..Stop request on
63770  */
63771 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
63772 
63773 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
63774 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
63775 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted.
63776  *  0b0..This module is functional in Stop Mode
63777  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63778  */
63779 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
63780 
63781 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U)
63782 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U)
63783 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
63784  *  0b0..Not in doze mode
63785  *  0b1..In doze mode
63786  */
63787 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
63788 
63789 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U)
63790 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U)
63791 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
63792  *  0b0..Stop request off
63793  *  0b1..Stop request on
63794  */
63795 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
63796 
63797 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
63798 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
63799 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted.
63800  *  0b0..This module is functional in Stop Mode
63801  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63802  */
63803 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
63804 
63805 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U)
63806 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U)
63807 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
63808  *  0b0..Not in doze mode
63809  *  0b1..In doze mode
63810  */
63811 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
63812 
63813 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U)
63814 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U)
63815 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
63816  *  0b0..Stop request off
63817  *  0b1..Stop request on
63818  */
63819 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
63820 
63821 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
63822 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
63823 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted.
63824  *  0b0..This module is functional in Stop Mode
63825  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63826  */
63827 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
63828 
63829 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U)
63830 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U)
63831 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
63832  *  0b0..Not in doze mode
63833  *  0b1..In doze mode
63834  */
63835 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
63836 
63837 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U)
63838 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U)
63839 /*! LPSPI5_STOP_REQ - LPSPI5 stop request
63840  *  0b0..Stop request off
63841  *  0b1..Stop request on
63842  */
63843 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
63844 
63845 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
63846 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
63847 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted.
63848  *  0b0..This module is functional in Stop Mode
63849  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63850  */
63851 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
63852 
63853 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U)
63854 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U)
63855 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
63856  *  0b0..Not in doze mode
63857  *  0b1..In doze mode
63858  */
63859 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
63860 
63861 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U)
63862 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U)
63863 /*! LPSPI6_STOP_REQ - LPSPI6 stop request
63864  *  0b0..Stop request off
63865  *  0b1..Stop request on
63866  */
63867 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
63868 
63869 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
63870 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
63871 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted.
63872  *  0b0..This module is functional in Stop Mode
63873  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63874  */
63875 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
63876 
63877 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U)
63878 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U)
63879 /*! LPUART1_IPG_DOZE - LPUART1 doze mode
63880  *  0b0..Not in doze mode
63881  *  0b1..In doze mode
63882  */
63883 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
63884 
63885 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U)
63886 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U)
63887 /*! LPUART1_STOP_REQ - LPUART1 stop request
63888  *  0b0..Stop request off
63889  *  0b1..Stop request on
63890  */
63891 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
63892 
63893 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
63894 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U)
63895 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted.
63896  *  0b0..This module is functional in Stop Mode
63897  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63898  */
63899 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
63900 
63901 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U)
63902 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U)
63903 /*! LPUART2_IPG_DOZE - LPUART2 doze mode
63904  *  0b0..Not in doze mode
63905  *  0b1..In doze mode
63906  */
63907 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
63908 
63909 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U)
63910 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U)
63911 /*! LPUART2_STOP_REQ - LPUART2 stop request
63912  *  0b0..Stop request off
63913  *  0b1..Stop request on
63914  */
63915 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
63916 
63917 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
63918 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U)
63919 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted.
63920  *  0b0..This module is functional in Stop Mode
63921  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63922  */
63923 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
63924 
63925 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U)
63926 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U)
63927 /*! LPUART3_IPG_DOZE - LPUART3 doze mode
63928  *  0b0..Not in doze mode
63929  *  0b1..In doze mode
63930  */
63931 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
63932 
63933 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U)
63934 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U)
63935 /*! LPUART3_STOP_REQ - LPUART3 stop request
63936  *  0b0..Stop request off
63937  *  0b1..Stop request on
63938  */
63939 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
63940 
63941 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
63942 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U)
63943 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted.
63944  *  0b0..This module is functional in Stop Mode
63945  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63946  */
63947 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
63948 
63949 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U)
63950 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U)
63951 /*! LPUART4_IPG_DOZE - LPUART4 doze mode
63952  *  0b0..Not in doze mode
63953  *  0b1..In doze mode
63954  */
63955 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
63956 
63957 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U)
63958 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U)
63959 /*! LPUART4_STOP_REQ - LPUART4 stop request
63960  *  0b0..Stop request off
63961  *  0b1..Stop request on
63962  */
63963 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
63964 
63965 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
63966 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U)
63967 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted.
63968  *  0b0..This module is functional in Stop Mode
63969  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
63970  */
63971 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
63972 
63973 #define IOMUXC_LPSR_GPR_GPR37_DWP_MASK           (0x30000000U)
63974 #define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT          (28U)
63975 /*! DWP - Domain write protection
63976  *  0b00..Both cores are allowed
63977  *  0b01..CM7 is forbidden
63978  *  0b10..CM4 is forbidden
63979  *  0b11..Both cores are forbidden
63980  */
63981 #define IOMUXC_LPSR_GPR_GPR37_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
63982 
63983 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK      (0xC0000000U)
63984 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT     (30U)
63985 /*! DWP_LOCK - Domain write protection lock
63986  *  0b00..Neither of DWP bits is locked
63987  *  0b01..The lower DWP bit is locked
63988  *  0b10..The higher DWP bit is locked
63989  *  0b11..Both DWP bits are locked
63990  */
63991 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
63992 /*! @} */
63993 
63994 /*! @name GPR38 - GPR38 General Purpose Register */
63995 /*! @{ */
63996 
63997 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U)
63998 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U)
63999 /*! LPUART5_IPG_DOZE - LPUART5 doze mode
64000  *  0b0..Not in doze mode
64001  *  0b1..In doze mode
64002  */
64003 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
64004 
64005 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U)
64006 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U)
64007 /*! LPUART5_STOP_REQ - LPUART5 stop request
64008  *  0b0..Stop request off
64009  *  0b1..Stop request on
64010  */
64011 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
64012 
64013 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U)
64014 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U)
64015 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted.
64016  *  0b0..This module is functional in Stop Mode
64017  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64018  */
64019 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
64020 
64021 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U)
64022 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U)
64023 /*! LPUART6_IPG_DOZE - LPUART6 doze mode
64024  *  0b0..Not in doze mode
64025  *  0b1..In doze mode
64026  */
64027 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
64028 
64029 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U)
64030 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U)
64031 /*! LPUART6_STOP_REQ - LPUART6 stop request
64032  *  0b0..Stop request off
64033  *  0b1..Stop request on
64034  */
64035 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
64036 
64037 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U)
64038 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U)
64039 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted.
64040  *  0b0..This module is functional in Stop Mode
64041  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64042  */
64043 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
64044 
64045 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U)
64046 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U)
64047 /*! LPUART7_IPG_DOZE - LPUART7 doze mode
64048  *  0b0..Not in doze mode
64049  *  0b1..In doze mode
64050  */
64051 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
64052 
64053 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U)
64054 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U)
64055 /*! LPUART7_STOP_REQ - LPUART7 stop request
64056  *  0b0..Stop request off
64057  *  0b1..Stop request on
64058  */
64059 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
64060 
64061 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U)
64062 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U)
64063 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted.
64064  *  0b0..This module is functional in Stop Mode
64065  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64066  */
64067 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
64068 
64069 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U)
64070 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U)
64071 /*! LPUART8_IPG_DOZE - LPUART8 doze mode
64072  *  0b0..Not in doze mode
64073  *  0b1..In doze mode
64074  */
64075 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
64076 
64077 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U)
64078 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U)
64079 /*! LPUART8_STOP_REQ - LPUART8 stop request
64080  *  0b0..Stop request off
64081  *  0b1..Stop request on
64082  */
64083 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
64084 
64085 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U)
64086 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U)
64087 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted.
64088  *  0b0..This module is functional in Stop Mode
64089  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64090  */
64091 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
64092 
64093 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U)
64094 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U)
64095 /*! LPUART9_IPG_DOZE - LPUART9 doze mode
64096  *  0b0..Not in doze mode
64097  *  0b1..In doze mode
64098  */
64099 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
64100 
64101 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U)
64102 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U)
64103 /*! LPUART9_STOP_REQ - LPUART9 stop request
64104  *  0b0..Stop request off
64105  *  0b1..Stop request on
64106  */
64107 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
64108 
64109 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
64110 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U)
64111 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted.
64112  *  0b0..This module is functional in Stop Mode
64113  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64114  */
64115 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
64116 
64117 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U)
64118 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U)
64119 /*! LPUART10_IPG_DOZE - LPUART10 doze mode
64120  *  0b0..Not in doze mode
64121  *  0b1..In doze mode
64122  */
64123 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
64124 
64125 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U)
64126 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U)
64127 /*! LPUART10_STOP_REQ - LPUART10 stop request
64128  *  0b0..Stop request off
64129  *  0b1..Stop request on
64130  */
64131 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
64132 
64133 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
64134 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U)
64135 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted.
64136  *  0b0..This module is functional in Stop Mode
64137  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64138  */
64139 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
64140 
64141 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U)
64142 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U)
64143 /*! LPUART11_IPG_DOZE - LPUART11 doze mode
64144  *  0b0..Not in doze mode
64145  *  0b1..In doze mode
64146  */
64147 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
64148 
64149 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U)
64150 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U)
64151 /*! LPUART11_STOP_REQ - LPUART11 stop request
64152  *  0b0..Stop request off
64153  *  0b1..Stop request on
64154  */
64155 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
64156 
64157 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
64158 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U)
64159 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted.
64160  *  0b0..This module is functional in Stop Mode
64161  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64162  */
64163 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
64164 
64165 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U)
64166 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U)
64167 /*! LPUART12_IPG_DOZE - LPUART12 doze mode
64168  *  0b0..Not in doze mode
64169  *  0b1..In doze mode
64170  */
64171 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
64172 
64173 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U)
64174 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U)
64175 /*! LPUART12_STOP_REQ - LPUART12 stop request
64176  *  0b0..Stop request off
64177  *  0b1..Stop request on
64178  */
64179 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
64180 
64181 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
64182 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U)
64183 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted.
64184  *  0b0..This module is functional in Stop Mode
64185  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64186  */
64187 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
64188 
64189 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK  (0x1000000U)
64190 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U)
64191 /*! MIC_IPG_DOZE - MIC doze mode
64192  *  0b0..Not in doze mode
64193  *  0b1..In doze mode
64194  */
64195 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
64196 
64197 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK  (0x2000000U)
64198 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U)
64199 /*! MIC_STOP_REQ - MIC stop request
64200  *  0b0..Stop request off
64201  *  0b1..Stop request on
64202  */
64203 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
64204 
64205 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U)
64206 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U)
64207 /*! MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted.
64208  *  0b0..This module is functional in Stop Mode
64209  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
64210  */
64211 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
64212 
64213 #define IOMUXC_LPSR_GPR_GPR38_DWP_MASK           (0x30000000U)
64214 #define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT          (28U)
64215 /*! DWP - Domain write protection
64216  *  0b00..Both cores are allowed
64217  *  0b01..CM7 is forbidden
64218  *  0b10..CM4 is forbidden
64219  *  0b11..Both cores are forbidden
64220  */
64221 #define IOMUXC_LPSR_GPR_GPR38_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
64222 
64223 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK      (0xC0000000U)
64224 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT     (30U)
64225 /*! DWP_LOCK - Domain write protection lock
64226  *  0b00..Neither of DWP bits is locked
64227  *  0b01..The lower DWP bit is locked
64228  *  0b10..The higher DWP bit is locked
64229  *  0b11..Both DWP bits are locked
64230  */
64231 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
64232 /*! @} */
64233 
64234 /*! @name GPR39 - GPR39 General Purpose Register */
64235 /*! @{ */
64236 
64237 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U)
64238 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U)
64239 /*! PIT1_STOP_REQ - PIT1 stop request
64240  *  0b0..Stop request off
64241  *  0b1..Stop request on
64242  */
64243 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
64244 
64245 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U)
64246 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U)
64247 /*! PIT2_STOP_REQ - PIT2 stop request
64248  *  0b0..Stop request off
64249  *  0b1..Stop request on
64250  */
64251 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
64252 
64253 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U)
64254 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U)
64255 /*! SEMC_STOP_REQ - SEMC stop request
64256  *  0b0..Stop request off
64257  *  0b1..Stop request on
64258  */
64259 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
64260 
64261 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U)
64262 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U)
64263 /*! SIM1_IPG_DOZE - SIM1 doze mode
64264  *  0b0..Not in doze mode
64265  *  0b1..In doze mode
64266  */
64267 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
64268 
64269 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U)
64270 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U)
64271 /*! SIM2_IPG_DOZE - SIM2 doze mode
64272  *  0b0..Not in doze mode
64273  *  0b1..In doze mode
64274  */
64275 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
64276 
64277 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U)
64278 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U)
64279 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
64280  *  0b0..Not in doze mode
64281  *  0b1..In doze mode
64282  */
64283 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
64284 
64285 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U)
64286 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U)
64287 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request
64288  *  0b0..Stop request off
64289  *  0b1..Stop request on
64290  */
64291 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
64292 
64293 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U)
64294 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U)
64295 /*! WDOG1_IPG_DOZE - WDOG1 doze mode
64296  *  0b0..Not in doze mode
64297  *  0b1..In doze mode
64298  */
64299 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
64300 
64301 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U)
64302 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U)
64303 /*! WDOG2_IPG_DOZE - WDOG2 doze mode
64304  *  0b0..Not in doze mode
64305  *  0b1..In doze mode
64306  */
64307 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
64308 
64309 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U)
64310 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U)
64311 /*! SAI1_STOP_REQ - SAI1 stop request
64312  *  0b0..Stop request off
64313  *  0b1..Stop request on
64314  */
64315 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
64316 
64317 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U)
64318 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U)
64319 /*! SAI2_STOP_REQ - SAI2 stop request
64320  *  0b0..Stop request off
64321  *  0b1..Stop request on
64322  */
64323 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
64324 
64325 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U)
64326 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U)
64327 /*! SAI3_STOP_REQ - SAI3 stop request
64328  *  0b0..Stop request off
64329  *  0b1..Stop request on
64330  */
64331 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
64332 
64333 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U)
64334 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U)
64335 /*! SAI4_STOP_REQ - SAI4 stop request
64336  *  0b0..Stop request off
64337  *  0b1..Stop request on
64338  */
64339 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
64340 
64341 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
64342 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
64343 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
64344  *  0b0..Stop request off
64345  *  0b1..Stop request on
64346  */
64347 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
64348 
64349 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
64350 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
64351 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
64352  *  0b0..Stop request off
64353  *  0b1..Stop request on
64354  */
64355 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
64356 
64357 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
64358 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
64359 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
64360  *  0b0..Stop request off
64361  *  0b1..Stop request on
64362  */
64363 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
64364 
64365 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
64366 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
64367 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
64368  *  0b0..Stop request off
64369  *  0b1..Stop request on
64370  */
64371 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
64372 
64373 #define IOMUXC_LPSR_GPR_GPR39_DWP_MASK           (0x30000000U)
64374 #define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT          (28U)
64375 /*! DWP - Domain write protection
64376  *  0b00..Both cores are allowed
64377  *  0b01..CM7 is forbidden
64378  *  0b10..CM4 is forbidden
64379  *  0b11..Both cores are forbidden
64380  */
64381 #define IOMUXC_LPSR_GPR_GPR39_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
64382 
64383 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK      (0xC0000000U)
64384 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT     (30U)
64385 /*! DWP_LOCK - Domain write protection lock
64386  *  0b00..Neither of DWP bits is locked
64387  *  0b01..The lower DWP bit is locked
64388  *  0b10..The higher DWP bit is locked
64389  *  0b11..Both DWP bits are locked
64390  */
64391 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
64392 /*! @} */
64393 
64394 /*! @name GPR40 - GPR40 General Purpose Register */
64395 /*! @{ */
64396 
64397 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U)
64398 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U)
64399 /*! ADC1_STOP_ACK - ADC1 stop acknowledge
64400  */
64401 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
64402 
64403 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U)
64404 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U)
64405 /*! ADC2_STOP_ACK - ADC2 stop acknowledge
64406  */
64407 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
64408 
64409 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U)
64410 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U)
64411 /*! CAAM_STOP_ACK - CAAM stop acknowledge
64412  */
64413 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
64414 
64415 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U)
64416 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U)
64417 /*! CAN1_STOP_ACK - CAN1 stop acknowledge
64418  */
64419 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
64420 
64421 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U)
64422 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U)
64423 /*! CAN2_STOP_ACK - CAN2 stop acknowledge
64424  */
64425 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
64426 
64427 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U)
64428 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U)
64429 /*! CAN3_STOP_ACK - CAN3 stop acknowledge
64430  */
64431 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
64432 
64433 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U)
64434 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U)
64435 /*! EDMA_STOP_ACK - EDMA stop acknowledge
64436  */
64437 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
64438 
64439 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U)
64440 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U)
64441 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
64442  */
64443 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
64444 
64445 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U)
64446 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U)
64447 /*! ENET_STOP_ACK - ENET stop acknowledge
64448  */
64449 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
64450 
64451 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U)
64452 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U)
64453 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge
64454  */
64455 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
64456 
64457 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U)
64458 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U)
64459 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
64460  */
64461 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
64462 
64463 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U)
64464 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U)
64465 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
64466  */
64467 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
64468 
64469 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U)
64470 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U)
64471 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
64472  */
64473 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
64474 
64475 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U)
64476 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U)
64477 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
64478  */
64479 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
64480 
64481 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U)
64482 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U)
64483 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
64484  */
64485 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
64486 
64487 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U)
64488 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U)
64489 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
64490  */
64491 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
64492 
64493 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U)
64494 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U)
64495 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
64496  */
64497 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
64498 
64499 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U)
64500 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U)
64501 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
64502  */
64503 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
64504 
64505 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U)
64506 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U)
64507 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
64508  */
64509 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
64510 
64511 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U)
64512 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U)
64513 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
64514  */
64515 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
64516 
64517 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U)
64518 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U)
64519 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
64520  */
64521 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
64522 
64523 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U)
64524 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U)
64525 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
64526  */
64527 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
64528 
64529 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U)
64530 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U)
64531 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
64532  */
64533 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
64534 
64535 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U)
64536 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U)
64537 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
64538  */
64539 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
64540 
64541 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U)
64542 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U)
64543 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
64544  */
64545 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
64546 
64547 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U)
64548 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U)
64549 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
64550  */
64551 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
64552 
64553 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U)
64554 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U)
64555 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
64556  */
64557 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
64558 
64559 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U)
64560 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U)
64561 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
64562  */
64563 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
64564 
64565 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U)
64566 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U)
64567 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
64568  */
64569 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
64570 
64571 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U)
64572 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U)
64573 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
64574  */
64575 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
64576 
64577 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U)
64578 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U)
64579 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
64580  */
64581 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
64582 
64583 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U)
64584 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U)
64585 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
64586  */
64587 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
64588 /*! @} */
64589 
64590 /*! @name GPR41 - GPR41 General Purpose Register */
64591 /*! @{ */
64592 
64593 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U)
64594 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U)
64595 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
64596  */
64597 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
64598 
64599 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U)
64600 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U)
64601 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
64602  */
64603 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
64604 
64605 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U)
64606 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U)
64607 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
64608  */
64609 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
64610 
64611 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U)
64612 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U)
64613 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
64614  */
64615 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
64616 
64617 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK  (0x10U)
64618 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U)
64619 /*! MIC_STOP_ACK - MIC stop acknowledge
64620  */
64621 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
64622 
64623 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U)
64624 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U)
64625 /*! PIT1_STOP_ACK - PIT1 stop acknowledge
64626  */
64627 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
64628 
64629 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U)
64630 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U)
64631 /*! PIT2_STOP_ACK - PIT2 stop acknowledge
64632  */
64633 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
64634 
64635 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U)
64636 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U)
64637 /*! SEMC_STOP_ACK - SEMC stop acknowledge
64638  */
64639 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
64640 
64641 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U)
64642 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U)
64643 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
64644  */
64645 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
64646 
64647 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U)
64648 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U)
64649 /*! SAI1_STOP_ACK - SAI1 stop acknowledge
64650  */
64651 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
64652 
64653 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U)
64654 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U)
64655 /*! SAI2_STOP_ACK - SAI2 stop acknowledge
64656  */
64657 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
64658 
64659 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U)
64660 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U)
64661 /*! SAI3_STOP_ACK - SAI3 stop acknowledge
64662  */
64663 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
64664 
64665 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U)
64666 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U)
64667 /*! SAI4_STOP_ACK - SAI4 stop acknowledge
64668  */
64669 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
64670 
64671 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
64672 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
64673 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
64674  */
64675 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
64676 
64677 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
64678 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
64679 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
64680  */
64681 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
64682 
64683 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
64684 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
64685 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
64686  */
64687 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
64688 
64689 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
64690 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
64691 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
64692  */
64693 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
64694 
64695 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U)
64696 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U)
64697 /*! ROM_READ_LOCKED - ROM read lock status bit
64698  */
64699 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
64700 /*! @} */
64701 
64702 
64703 /*!
64704  * @}
64705  */ /* end of group IOMUXC_LPSR_GPR_Register_Masks */
64706 
64707 
64708 /* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
64709 /** Peripheral IOMUXC_LPSR_GPR base address */
64710 #define IOMUXC_LPSR_GPR_BASE                     (0x40C0C000u)
64711 /** Peripheral IOMUXC_LPSR_GPR base pointer */
64712 #define IOMUXC_LPSR_GPR                          ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
64713 /** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */
64714 #define IOMUXC_LPSR_GPR_BASE_ADDRS               { IOMUXC_LPSR_GPR_BASE }
64715 /** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */
64716 #define IOMUXC_LPSR_GPR_BASE_PTRS                { IOMUXC_LPSR_GPR }
64717 
64718 /*!
64719  * @}
64720  */ /* end of group IOMUXC_LPSR_GPR_Peripheral_Access_Layer */
64721 
64722 
64723 /* ----------------------------------------------------------------------------
64724    -- IOMUXC_SNVS Peripheral Access Layer
64725    ---------------------------------------------------------------------------- */
64726 
64727 /*!
64728  * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
64729  * @{
64730  */
64731 
64732 /** IOMUXC_SNVS - Register Layout Typedef */
64733 typedef struct {
64734   __IO uint32_t SW_MUX_CTL_PAD_WAKEUP_DIG;         /**< SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0 */
64735   __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4 */
64736   __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8 */
64737   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC */
64738   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10 */
64739   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14 */
64740   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18 */
64741   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C */
64742   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20 */
64743   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24 */
64744   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28 */
64745   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C */
64746   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30 */
64747   __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE_DIG;      /**< SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34 */
64748   __IO uint32_t SW_PAD_CTL_PAD_POR_B_DIG;          /**< SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38 */
64749   __IO uint32_t SW_PAD_CTL_PAD_ONOFF_DIG;          /**< SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C */
64750   __IO uint32_t SW_PAD_CTL_PAD_WAKEUP_DIG;         /**< SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40 */
64751   __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44 */
64752   __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48 */
64753   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C */
64754   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50 */
64755   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54 */
64756   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58 */
64757   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C */
64758   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60 */
64759   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64 */
64760   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68 */
64761   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C */
64762   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70 */
64763 } IOMUXC_SNVS_Type;
64764 
64765 /* ----------------------------------------------------------------------------
64766    -- IOMUXC_SNVS Register Masks
64767    ---------------------------------------------------------------------------- */
64768 
64769 /*!
64770  * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
64771  * @{
64772  */
64773 
64774 /*! @name SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register */
64775 /*! @{ */
64776 
64777 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)
64778 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)
64779 /*! MUX_MODE - MUX Mode Select Field.
64780  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13
64781  *  0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE
64782  */
64783 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)
64784 
64785 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)
64786 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)
64787 /*! SION - Software Input On Field.
64788  *  0b1..Force input path of pad WAKEUP_DIG
64789  *  0b0..Input Path is determined by functionality
64790  */
64791 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)
64792 /*! @} */
64793 
64794 /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register */
64795 /*! @{ */
64796 
64797 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)
64798 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)
64799 /*! MUX_MODE - MUX Mode Select Field.
64800  *  0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP
64801  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13
64802  */
64803 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)
64804 
64805 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)
64806 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)
64807 /*! SION - Software Input On Field.
64808  *  0b1..Force input path of pad PMIC_ON_REQ_DIG
64809  *  0b0..Input Path is determined by functionality
64810  */
64811 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)
64812 /*! @} */
64813 
64814 /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register */
64815 /*! @{ */
64816 
64817 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)
64818 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)
64819 /*! MUX_MODE - MUX Mode Select Field.
64820  *  0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM
64821  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13
64822  */
64823 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)
64824 
64825 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)
64826 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)
64827 /*! SION - Software Input On Field.
64828  *  0b1..Force input path of pad PMIC_STBY_REQ_DIG
64829  *  0b0..Input Path is determined by functionality
64830  */
64831 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)
64832 /*! @} */
64833 
64834 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register */
64835 /*! @{ */
64836 
64837 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)
64838 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)
64839 /*! MUX_MODE - MUX Mode Select Field.
64840  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP
64841  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13
64842  */
64843 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)
64844 
64845 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)
64846 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)
64847 /*! SION - Software Input On Field.
64848  *  0b1..Force input path of pad GPIO_SNVS_00_DIG
64849  *  0b0..Input Path is determined by functionality
64850  */
64851 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)
64852 /*! @} */
64853 
64854 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register */
64855 /*! @{ */
64856 
64857 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)
64858 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)
64859 /*! MUX_MODE - MUX Mode Select Field.
64860  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP
64861  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13
64862  */
64863 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)
64864 
64865 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)
64866 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)
64867 /*! SION - Software Input On Field.
64868  *  0b1..Force input path of pad GPIO_SNVS_01_DIG
64869  *  0b0..Input Path is determined by functionality
64870  */
64871 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)
64872 /*! @} */
64873 
64874 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register */
64875 /*! @{ */
64876 
64877 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)
64878 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)
64879 /*! MUX_MODE - MUX Mode Select Field.
64880  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP
64881  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13
64882  */
64883 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)
64884 
64885 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)
64886 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)
64887 /*! SION - Software Input On Field.
64888  *  0b1..Force input path of pad GPIO_SNVS_02_DIG
64889  *  0b0..Input Path is determined by functionality
64890  */
64891 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)
64892 /*! @} */
64893 
64894 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register */
64895 /*! @{ */
64896 
64897 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)
64898 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)
64899 /*! MUX_MODE - MUX Mode Select Field.
64900  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP
64901  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13
64902  */
64903 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)
64904 
64905 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)
64906 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)
64907 /*! SION - Software Input On Field.
64908  *  0b1..Force input path of pad GPIO_SNVS_03_DIG
64909  *  0b0..Input Path is determined by functionality
64910  */
64911 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)
64912 /*! @} */
64913 
64914 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register */
64915 /*! @{ */
64916 
64917 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)
64918 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)
64919 /*! MUX_MODE - MUX Mode Select Field.
64920  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP
64921  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13
64922  */
64923 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)
64924 
64925 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)
64926 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)
64927 /*! SION - Software Input On Field.
64928  *  0b1..Force input path of pad GPIO_SNVS_04_DIG
64929  *  0b0..Input Path is determined by functionality
64930  */
64931 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)
64932 /*! @} */
64933 
64934 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register */
64935 /*! @{ */
64936 
64937 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)
64938 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)
64939 /*! MUX_MODE - MUX Mode Select Field.
64940  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP
64941  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13
64942  */
64943 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)
64944 
64945 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)
64946 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)
64947 /*! SION - Software Input On Field.
64948  *  0b1..Force input path of pad GPIO_SNVS_05_DIG
64949  *  0b0..Input Path is determined by functionality
64950  */
64951 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)
64952 /*! @} */
64953 
64954 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register */
64955 /*! @{ */
64956 
64957 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)
64958 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)
64959 /*! MUX_MODE - MUX Mode Select Field.
64960  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP
64961  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13
64962  */
64963 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)
64964 
64965 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)
64966 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)
64967 /*! SION - Software Input On Field.
64968  *  0b1..Force input path of pad GPIO_SNVS_06_DIG
64969  *  0b0..Input Path is determined by functionality
64970  */
64971 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)
64972 /*! @} */
64973 
64974 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register */
64975 /*! @{ */
64976 
64977 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)
64978 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)
64979 /*! MUX_MODE - MUX Mode Select Field.
64980  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP
64981  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13
64982  */
64983 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)
64984 
64985 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)
64986 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)
64987 /*! SION - Software Input On Field.
64988  *  0b1..Force input path of pad GPIO_SNVS_07_DIG
64989  *  0b0..Input Path is determined by functionality
64990  */
64991 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)
64992 /*! @} */
64993 
64994 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register */
64995 /*! @{ */
64996 
64997 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)
64998 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)
64999 /*! MUX_MODE - MUX Mode Select Field.
65000  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP
65001  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13
65002  */
65003 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)
65004 
65005 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)
65006 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)
65007 /*! SION - Software Input On Field.
65008  *  0b1..Force input path of pad GPIO_SNVS_08_DIG
65009  *  0b0..Input Path is determined by functionality
65010  */
65011 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)
65012 /*! @} */
65013 
65014 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register */
65015 /*! @{ */
65016 
65017 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)
65018 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)
65019 /*! MUX_MODE - MUX Mode Select Field.
65020  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP
65021  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13
65022  */
65023 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)
65024 
65025 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)
65026 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)
65027 /*! SION - Software Input On Field.
65028  *  0b1..Force input path of pad GPIO_SNVS_09_DIG
65029  *  0b0..Input Path is determined by functionality
65030  */
65031 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)
65032 /*! @} */
65033 
65034 /*! @name SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register */
65035 /*! @{ */
65036 
65037 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)
65038 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)
65039 /*! SRE - Slew Rate Field
65040  *  0b0..Slow Slew Rate
65041  *  0b1..Fast Slew Rate
65042  */
65043 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)
65044 
65045 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)
65046 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)
65047 /*! DSE - Drive Strength Field
65048  *  0b0..normal driver
65049  *  0b1..high driver
65050  */
65051 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)
65052 
65053 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)
65054 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)
65055 /*! PUE - Pull / Keep Select Field
65056  *  0b0..Pull Disable
65057  *  0b1..Pull Enable
65058  */
65059 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)
65060 
65061 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)
65062 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)
65063 /*! PUS - Pull Up / Down Config. Field
65064  *  0b0..Weak pull down
65065  *  0b1..Weak pull up
65066  */
65067 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)
65068 
65069 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)
65070 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)
65071 /*! DWP - Domain write protection
65072  *  0b00..Both cores are allowed
65073  *  0b01..CM7 is forbidden
65074  *  0b10..CM4 is forbidden
65075  *  0b11..Both cores are forbidden
65076  */
65077 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)
65078 
65079 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)
65080 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)
65081 /*! DWP_LOCK - Domain write protection lock
65082  *  0b00..Neither of DWP bits is locked
65083  *  0b01..The lower DWP bit is locked
65084  *  0b10..The higher DWP bit is locked
65085  *  0b11..Both DWP bits are locked
65086  */
65087 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)
65088 /*! @} */
65089 
65090 /*! @name SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register */
65091 /*! @{ */
65092 
65093 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)
65094 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)
65095 /*! SRE - Slew Rate Field
65096  *  0b0..Slow Slew Rate
65097  *  0b1..Fast Slew Rate
65098  */
65099 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)
65100 
65101 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)
65102 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)
65103 /*! DSE - Drive Strength Field
65104  *  0b0..normal driver
65105  *  0b1..high driver
65106  */
65107 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)
65108 
65109 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)
65110 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)
65111 /*! PUE - Pull / Keep Select Field
65112  *  0b0..Pull Disable
65113  *  0b1..Pull Enable
65114  */
65115 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)
65116 
65117 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)
65118 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)
65119 /*! PUS - Pull Up / Down Config. Field
65120  *  0b0..Weak pull down
65121  *  0b1..Weak pull up
65122  */
65123 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)
65124 
65125 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)
65126 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)
65127 /*! DWP - Domain write protection
65128  *  0b00..Both cores are allowed
65129  *  0b01..CM7 is forbidden
65130  *  0b10..CM4 is forbidden
65131  *  0b11..Both cores are forbidden
65132  */
65133 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)
65134 
65135 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)
65136 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)
65137 /*! DWP_LOCK - Domain write protection lock
65138  *  0b00..Neither of DWP bits is locked
65139  *  0b01..The lower DWP bit is locked
65140  *  0b10..The higher DWP bit is locked
65141  *  0b11..Both DWP bits are locked
65142  */
65143 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)
65144 /*! @} */
65145 
65146 /*! @name SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register */
65147 /*! @{ */
65148 
65149 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)
65150 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)
65151 /*! SRE - Slew Rate Field
65152  *  0b0..Slow Slew Rate
65153  *  0b1..Fast Slew Rate
65154  */
65155 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)
65156 
65157 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)
65158 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)
65159 /*! DSE - Drive Strength Field
65160  *  0b0..normal driver
65161  *  0b1..high driver
65162  */
65163 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)
65164 
65165 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)
65166 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)
65167 /*! PUE - Pull / Keep Select Field
65168  *  0b0..Pull Disable
65169  *  0b1..Pull Enable
65170  */
65171 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)
65172 
65173 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)
65174 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)
65175 /*! PUS - Pull Up / Down Config. Field
65176  *  0b0..Weak pull down
65177  *  0b1..Weak pull up
65178  */
65179 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)
65180 
65181 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)
65182 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)
65183 /*! DWP - Domain write protection
65184  *  0b00..Both cores are allowed
65185  *  0b01..CM7 is forbidden
65186  *  0b10..CM4 is forbidden
65187  *  0b11..Both cores are forbidden
65188  */
65189 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)
65190 
65191 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)
65192 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)
65193 /*! DWP_LOCK - Domain write protection lock
65194  *  0b00..Neither of DWP bits is locked
65195  *  0b01..The lower DWP bit is locked
65196  *  0b10..The higher DWP bit is locked
65197  *  0b11..Both DWP bits are locked
65198  */
65199 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)
65200 /*! @} */
65201 
65202 /*! @name SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register */
65203 /*! @{ */
65204 
65205 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)
65206 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)
65207 /*! SRE - Slew Rate Field
65208  *  0b0..Slow Slew Rate
65209  *  0b1..Fast Slew Rate
65210  */
65211 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)
65212 
65213 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)
65214 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)
65215 /*! DSE - Drive Strength Field
65216  *  0b0..normal driver
65217  *  0b1..high driver
65218  */
65219 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)
65220 
65221 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)
65222 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)
65223 /*! PUE - Pull / Keep Select Field
65224  *  0b0..Pull Disable
65225  *  0b1..Pull Enable
65226  */
65227 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)
65228 
65229 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)
65230 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)
65231 /*! PUS - Pull Up / Down Config. Field
65232  *  0b0..Weak pull down
65233  *  0b1..Weak pull up
65234  */
65235 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)
65236 
65237 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)
65238 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)
65239 /*! ODE_SNVS - Open Drain SNVS Field
65240  *  0b0..Disabled
65241  *  0b1..Enabled
65242  */
65243 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)
65244 
65245 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)
65246 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)
65247 /*! DWP - Domain write protection
65248  *  0b00..Both cores are allowed
65249  *  0b01..CM7 is forbidden
65250  *  0b10..CM4 is forbidden
65251  *  0b11..Both cores are forbidden
65252  */
65253 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)
65254 
65255 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)
65256 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)
65257 /*! DWP_LOCK - Domain write protection lock
65258  *  0b00..Neither of DWP bits is locked
65259  *  0b01..The lower DWP bit is locked
65260  *  0b10..The higher DWP bit is locked
65261  *  0b11..Both DWP bits are locked
65262  */
65263 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)
65264 /*! @} */
65265 
65266 /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register */
65267 /*! @{ */
65268 
65269 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)
65270 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)
65271 /*! SRE - Slew Rate Field
65272  *  0b0..Slow Slew Rate
65273  *  0b1..Fast Slew Rate
65274  */
65275 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)
65276 
65277 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)
65278 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)
65279 /*! DSE - Drive Strength Field
65280  *  0b0..normal driver
65281  *  0b1..high driver
65282  */
65283 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)
65284 
65285 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)
65286 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)
65287 /*! PUE - Pull / Keep Select Field
65288  *  0b0..Pull Disable
65289  *  0b1..Pull Enable
65290  */
65291 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)
65292 
65293 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)
65294 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)
65295 /*! PUS - Pull Up / Down Config. Field
65296  *  0b0..Weak pull down
65297  *  0b1..Weak pull up
65298  */
65299 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)
65300 
65301 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)
65302 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)
65303 /*! ODE_SNVS - Open Drain SNVS Field
65304  *  0b0..Disabled
65305  *  0b1..Enabled
65306  */
65307 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)
65308 
65309 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)
65310 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)
65311 /*! DWP - Domain write protection
65312  *  0b00..Both cores are allowed
65313  *  0b01..CM7 is forbidden
65314  *  0b10..CM4 is forbidden
65315  *  0b11..Both cores are forbidden
65316  */
65317 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)
65318 
65319 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
65320 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)
65321 /*! DWP_LOCK - Domain write protection lock
65322  *  0b00..Neither of DWP bits is locked
65323  *  0b01..The lower DWP bit is locked
65324  *  0b10..The higher DWP bit is locked
65325  *  0b11..Both DWP bits are locked
65326  */
65327 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)
65328 /*! @} */
65329 
65330 /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register */
65331 /*! @{ */
65332 
65333 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)
65334 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)
65335 /*! SRE - Slew Rate Field
65336  *  0b0..Slow Slew Rate
65337  *  0b1..Fast Slew Rate
65338  */
65339 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)
65340 
65341 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)
65342 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)
65343 /*! DSE - Drive Strength Field
65344  *  0b0..normal driver
65345  *  0b1..high driver
65346  */
65347 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)
65348 
65349 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)
65350 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)
65351 /*! PUE - Pull / Keep Select Field
65352  *  0b0..Pull Disable
65353  *  0b1..Pull Enable
65354  */
65355 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)
65356 
65357 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)
65358 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)
65359 /*! PUS - Pull Up / Down Config. Field
65360  *  0b0..Weak pull down
65361  *  0b1..Weak pull up
65362  */
65363 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)
65364 
65365 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)
65366 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)
65367 /*! ODE_SNVS - Open Drain SNVS Field
65368  *  0b0..Disabled
65369  *  0b1..Enabled
65370  */
65371 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)
65372 
65373 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)
65374 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)
65375 /*! DWP - Domain write protection
65376  *  0b00..Both cores are allowed
65377  *  0b01..CM7 is forbidden
65378  *  0b10..CM4 is forbidden
65379  *  0b11..Both cores are forbidden
65380  */
65381 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)
65382 
65383 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
65384 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)
65385 /*! DWP_LOCK - Domain write protection lock
65386  *  0b00..Neither of DWP bits is locked
65387  *  0b01..The lower DWP bit is locked
65388  *  0b10..The higher DWP bit is locked
65389  *  0b11..Both DWP bits are locked
65390  */
65391 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)
65392 /*! @} */
65393 
65394 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register */
65395 /*! @{ */
65396 
65397 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)
65398 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)
65399 /*! SRE - Slew Rate Field
65400  *  0b0..Slow Slew Rate
65401  *  0b1..Fast Slew Rate
65402  */
65403 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)
65404 
65405 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)
65406 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)
65407 /*! DSE - Drive Strength Field
65408  *  0b0..normal driver
65409  *  0b1..high driver
65410  */
65411 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)
65412 
65413 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)
65414 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)
65415 /*! PUE - Pull / Keep Select Field
65416  *  0b0..Pull Disable
65417  *  0b1..Pull Enable
65418  */
65419 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)
65420 
65421 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)
65422 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)
65423 /*! PUS - Pull Up / Down Config. Field
65424  *  0b0..Weak pull down
65425  *  0b1..Weak pull up
65426  */
65427 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)
65428 
65429 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)
65430 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)
65431 /*! ODE_SNVS - Open Drain SNVS Field
65432  *  0b0..Disabled
65433  *  0b1..Enabled
65434  */
65435 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)
65436 
65437 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)
65438 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)
65439 /*! DWP - Domain write protection
65440  *  0b00..Both cores are allowed
65441  *  0b01..CM7 is forbidden
65442  *  0b10..CM4 is forbidden
65443  *  0b11..Both cores are forbidden
65444  */
65445 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)
65446 
65447 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)
65448 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)
65449 /*! DWP_LOCK - Domain write protection lock
65450  *  0b00..Neither of DWP bits is locked
65451  *  0b01..The lower DWP bit is locked
65452  *  0b10..The higher DWP bit is locked
65453  *  0b11..Both DWP bits are locked
65454  */
65455 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)
65456 /*! @} */
65457 
65458 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register */
65459 /*! @{ */
65460 
65461 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)
65462 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)
65463 /*! SRE - Slew Rate Field
65464  *  0b0..Slow Slew Rate
65465  *  0b1..Fast Slew Rate
65466  */
65467 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)
65468 
65469 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)
65470 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)
65471 /*! DSE - Drive Strength Field
65472  *  0b0..normal driver
65473  *  0b1..high driver
65474  */
65475 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)
65476 
65477 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)
65478 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)
65479 /*! PUE - Pull / Keep Select Field
65480  *  0b0..Pull Disable
65481  *  0b1..Pull Enable
65482  */
65483 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)
65484 
65485 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)
65486 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)
65487 /*! PUS - Pull Up / Down Config. Field
65488  *  0b0..Weak pull down
65489  *  0b1..Weak pull up
65490  */
65491 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)
65492 
65493 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)
65494 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)
65495 /*! ODE_SNVS - Open Drain SNVS Field
65496  *  0b0..Disabled
65497  *  0b1..Enabled
65498  */
65499 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)
65500 
65501 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)
65502 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)
65503 /*! DWP - Domain write protection
65504  *  0b00..Both cores are allowed
65505  *  0b01..CM7 is forbidden
65506  *  0b10..CM4 is forbidden
65507  *  0b11..Both cores are forbidden
65508  */
65509 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)
65510 
65511 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)
65512 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)
65513 /*! DWP_LOCK - Domain write protection lock
65514  *  0b00..Neither of DWP bits is locked
65515  *  0b01..The lower DWP bit is locked
65516  *  0b10..The higher DWP bit is locked
65517  *  0b11..Both DWP bits are locked
65518  */
65519 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)
65520 /*! @} */
65521 
65522 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register */
65523 /*! @{ */
65524 
65525 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)
65526 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)
65527 /*! SRE - Slew Rate Field
65528  *  0b0..Slow Slew Rate
65529  *  0b1..Fast Slew Rate
65530  */
65531 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)
65532 
65533 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)
65534 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)
65535 /*! DSE - Drive Strength Field
65536  *  0b0..normal driver
65537  *  0b1..high driver
65538  */
65539 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)
65540 
65541 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)
65542 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)
65543 /*! PUE - Pull / Keep Select Field
65544  *  0b0..Pull Disable
65545  *  0b1..Pull Enable
65546  */
65547 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)
65548 
65549 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)
65550 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)
65551 /*! PUS - Pull Up / Down Config. Field
65552  *  0b0..Weak pull down
65553  *  0b1..Weak pull up
65554  */
65555 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)
65556 
65557 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)
65558 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)
65559 /*! ODE_SNVS - Open Drain SNVS Field
65560  *  0b0..Disabled
65561  *  0b1..Enabled
65562  */
65563 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)
65564 
65565 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)
65566 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)
65567 /*! DWP - Domain write protection
65568  *  0b00..Both cores are allowed
65569  *  0b01..CM7 is forbidden
65570  *  0b10..CM4 is forbidden
65571  *  0b11..Both cores are forbidden
65572  */
65573 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)
65574 
65575 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)
65576 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)
65577 /*! DWP_LOCK - Domain write protection lock
65578  *  0b00..Neither of DWP bits is locked
65579  *  0b01..The lower DWP bit is locked
65580  *  0b10..The higher DWP bit is locked
65581  *  0b11..Both DWP bits are locked
65582  */
65583 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)
65584 /*! @} */
65585 
65586 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register */
65587 /*! @{ */
65588 
65589 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)
65590 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)
65591 /*! SRE - Slew Rate Field
65592  *  0b0..Slow Slew Rate
65593  *  0b1..Fast Slew Rate
65594  */
65595 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)
65596 
65597 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)
65598 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)
65599 /*! DSE - Drive Strength Field
65600  *  0b0..normal driver
65601  *  0b1..high driver
65602  */
65603 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)
65604 
65605 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)
65606 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)
65607 /*! PUE - Pull / Keep Select Field
65608  *  0b0..Pull Disable
65609  *  0b1..Pull Enable
65610  */
65611 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)
65612 
65613 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)
65614 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)
65615 /*! PUS - Pull Up / Down Config. Field
65616  *  0b0..Weak pull down
65617  *  0b1..Weak pull up
65618  */
65619 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)
65620 
65621 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)
65622 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)
65623 /*! ODE_SNVS - Open Drain SNVS Field
65624  *  0b0..Disabled
65625  *  0b1..Enabled
65626  */
65627 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)
65628 
65629 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)
65630 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)
65631 /*! DWP - Domain write protection
65632  *  0b00..Both cores are allowed
65633  *  0b01..CM7 is forbidden
65634  *  0b10..CM4 is forbidden
65635  *  0b11..Both cores are forbidden
65636  */
65637 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)
65638 
65639 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)
65640 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)
65641 /*! DWP_LOCK - Domain write protection lock
65642  *  0b00..Neither of DWP bits is locked
65643  *  0b01..The lower DWP bit is locked
65644  *  0b10..The higher DWP bit is locked
65645  *  0b11..Both DWP bits are locked
65646  */
65647 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)
65648 /*! @} */
65649 
65650 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register */
65651 /*! @{ */
65652 
65653 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)
65654 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)
65655 /*! SRE - Slew Rate Field
65656  *  0b0..Slow Slew Rate
65657  *  0b1..Fast Slew Rate
65658  */
65659 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)
65660 
65661 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)
65662 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)
65663 /*! DSE - Drive Strength Field
65664  *  0b0..normal driver
65665  *  0b1..high driver
65666  */
65667 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)
65668 
65669 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)
65670 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)
65671 /*! PUE - Pull / Keep Select Field
65672  *  0b0..Pull Disable
65673  *  0b1..Pull Enable
65674  */
65675 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)
65676 
65677 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)
65678 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)
65679 /*! PUS - Pull Up / Down Config. Field
65680  *  0b0..Weak pull down
65681  *  0b1..Weak pull up
65682  */
65683 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)
65684 
65685 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)
65686 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)
65687 /*! ODE_SNVS - Open Drain SNVS Field
65688  *  0b0..Disabled
65689  *  0b1..Enabled
65690  */
65691 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)
65692 
65693 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)
65694 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)
65695 /*! DWP - Domain write protection
65696  *  0b00..Both cores are allowed
65697  *  0b01..CM7 is forbidden
65698  *  0b10..CM4 is forbidden
65699  *  0b11..Both cores are forbidden
65700  */
65701 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)
65702 
65703 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)
65704 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)
65705 /*! DWP_LOCK - Domain write protection lock
65706  *  0b00..Neither of DWP bits is locked
65707  *  0b01..The lower DWP bit is locked
65708  *  0b10..The higher DWP bit is locked
65709  *  0b11..Both DWP bits are locked
65710  */
65711 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)
65712 /*! @} */
65713 
65714 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register */
65715 /*! @{ */
65716 
65717 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)
65718 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)
65719 /*! SRE - Slew Rate Field
65720  *  0b0..Slow Slew Rate
65721  *  0b1..Fast Slew Rate
65722  */
65723 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)
65724 
65725 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)
65726 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)
65727 /*! DSE - Drive Strength Field
65728  *  0b0..normal driver
65729  *  0b1..high driver
65730  */
65731 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)
65732 
65733 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)
65734 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)
65735 /*! PUE - Pull / Keep Select Field
65736  *  0b0..Pull Disable
65737  *  0b1..Pull Enable
65738  */
65739 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)
65740 
65741 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)
65742 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)
65743 /*! PUS - Pull Up / Down Config. Field
65744  *  0b0..Weak pull down
65745  *  0b1..Weak pull up
65746  */
65747 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)
65748 
65749 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)
65750 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)
65751 /*! ODE_SNVS - Open Drain SNVS Field
65752  *  0b0..Disabled
65753  *  0b1..Enabled
65754  */
65755 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)
65756 
65757 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)
65758 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)
65759 /*! DWP - Domain write protection
65760  *  0b00..Both cores are allowed
65761  *  0b01..CM7 is forbidden
65762  *  0b10..CM4 is forbidden
65763  *  0b11..Both cores are forbidden
65764  */
65765 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)
65766 
65767 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)
65768 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)
65769 /*! DWP_LOCK - Domain write protection lock
65770  *  0b00..Neither of DWP bits is locked
65771  *  0b01..The lower DWP bit is locked
65772  *  0b10..The higher DWP bit is locked
65773  *  0b11..Both DWP bits are locked
65774  */
65775 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)
65776 /*! @} */
65777 
65778 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register */
65779 /*! @{ */
65780 
65781 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)
65782 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)
65783 /*! SRE - Slew Rate Field
65784  *  0b0..Slow Slew Rate
65785  *  0b1..Fast Slew Rate
65786  */
65787 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)
65788 
65789 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)
65790 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)
65791 /*! DSE - Drive Strength Field
65792  *  0b0..normal driver
65793  *  0b1..high driver
65794  */
65795 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)
65796 
65797 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)
65798 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)
65799 /*! PUE - Pull / Keep Select Field
65800  *  0b0..Pull Disable
65801  *  0b1..Pull Enable
65802  */
65803 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)
65804 
65805 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)
65806 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)
65807 /*! PUS - Pull Up / Down Config. Field
65808  *  0b0..Weak pull down
65809  *  0b1..Weak pull up
65810  */
65811 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)
65812 
65813 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)
65814 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)
65815 /*! ODE_SNVS - Open Drain SNVS Field
65816  *  0b0..Disabled
65817  *  0b1..Enabled
65818  */
65819 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)
65820 
65821 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)
65822 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)
65823 /*! DWP - Domain write protection
65824  *  0b00..Both cores are allowed
65825  *  0b01..CM7 is forbidden
65826  *  0b10..CM4 is forbidden
65827  *  0b11..Both cores are forbidden
65828  */
65829 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)
65830 
65831 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)
65832 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)
65833 /*! DWP_LOCK - Domain write protection lock
65834  *  0b00..Neither of DWP bits is locked
65835  *  0b01..The lower DWP bit is locked
65836  *  0b10..The higher DWP bit is locked
65837  *  0b11..Both DWP bits are locked
65838  */
65839 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)
65840 /*! @} */
65841 
65842 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register */
65843 /*! @{ */
65844 
65845 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)
65846 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)
65847 /*! SRE - Slew Rate Field
65848  *  0b0..Slow Slew Rate
65849  *  0b1..Fast Slew Rate
65850  */
65851 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)
65852 
65853 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)
65854 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)
65855 /*! DSE - Drive Strength Field
65856  *  0b0..normal driver
65857  *  0b1..high driver
65858  */
65859 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)
65860 
65861 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)
65862 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)
65863 /*! PUE - Pull / Keep Select Field
65864  *  0b0..Pull Disable
65865  *  0b1..Pull Enable
65866  */
65867 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)
65868 
65869 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)
65870 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)
65871 /*! PUS - Pull Up / Down Config. Field
65872  *  0b0..Weak pull down
65873  *  0b1..Weak pull up
65874  */
65875 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)
65876 
65877 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)
65878 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)
65879 /*! ODE_SNVS - Open Drain SNVS Field
65880  *  0b0..Disabled
65881  *  0b1..Enabled
65882  */
65883 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)
65884 
65885 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)
65886 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)
65887 /*! DWP - Domain write protection
65888  *  0b00..Both cores are allowed
65889  *  0b01..CM7 is forbidden
65890  *  0b10..CM4 is forbidden
65891  *  0b11..Both cores are forbidden
65892  */
65893 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)
65894 
65895 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)
65896 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)
65897 /*! DWP_LOCK - Domain write protection lock
65898  *  0b00..Neither of DWP bits is locked
65899  *  0b01..The lower DWP bit is locked
65900  *  0b10..The higher DWP bit is locked
65901  *  0b11..Both DWP bits are locked
65902  */
65903 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)
65904 /*! @} */
65905 
65906 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register */
65907 /*! @{ */
65908 
65909 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)
65910 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)
65911 /*! SRE - Slew Rate Field
65912  *  0b0..Slow Slew Rate
65913  *  0b1..Fast Slew Rate
65914  */
65915 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)
65916 
65917 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)
65918 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)
65919 /*! DSE - Drive Strength Field
65920  *  0b0..normal driver
65921  *  0b1..high driver
65922  */
65923 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)
65924 
65925 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)
65926 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)
65927 /*! PUE - Pull / Keep Select Field
65928  *  0b0..Pull Disable
65929  *  0b1..Pull Enable
65930  */
65931 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)
65932 
65933 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)
65934 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)
65935 /*! PUS - Pull Up / Down Config. Field
65936  *  0b0..Weak pull down
65937  *  0b1..Weak pull up
65938  */
65939 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)
65940 
65941 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)
65942 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)
65943 /*! ODE_SNVS - Open Drain SNVS Field
65944  *  0b0..Disabled
65945  *  0b1..Enabled
65946  */
65947 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)
65948 
65949 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)
65950 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)
65951 /*! DWP - Domain write protection
65952  *  0b00..Both cores are allowed
65953  *  0b01..CM7 is forbidden
65954  *  0b10..CM4 is forbidden
65955  *  0b11..Both cores are forbidden
65956  */
65957 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)
65958 
65959 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)
65960 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)
65961 /*! DWP_LOCK - Domain write protection lock
65962  *  0b00..Neither of DWP bits is locked
65963  *  0b01..The lower DWP bit is locked
65964  *  0b10..The higher DWP bit is locked
65965  *  0b11..Both DWP bits are locked
65966  */
65967 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)
65968 /*! @} */
65969 
65970 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register */
65971 /*! @{ */
65972 
65973 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)
65974 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)
65975 /*! SRE - Slew Rate Field
65976  *  0b0..Slow Slew Rate
65977  *  0b1..Fast Slew Rate
65978  */
65979 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)
65980 
65981 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)
65982 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)
65983 /*! DSE - Drive Strength Field
65984  *  0b0..normal driver
65985  *  0b1..high driver
65986  */
65987 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)
65988 
65989 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)
65990 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)
65991 /*! PUE - Pull / Keep Select Field
65992  *  0b0..Pull Disable
65993  *  0b1..Pull Enable
65994  */
65995 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)
65996 
65997 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)
65998 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)
65999 /*! PUS - Pull Up / Down Config. Field
66000  *  0b0..Weak pull down
66001  *  0b1..Weak pull up
66002  */
66003 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)
66004 
66005 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)
66006 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)
66007 /*! ODE_SNVS - Open Drain SNVS Field
66008  *  0b0..Disabled
66009  *  0b1..Enabled
66010  */
66011 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)
66012 
66013 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)
66014 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)
66015 /*! DWP - Domain write protection
66016  *  0b00..Both cores are allowed
66017  *  0b01..CM7 is forbidden
66018  *  0b10..CM4 is forbidden
66019  *  0b11..Both cores are forbidden
66020  */
66021 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)
66022 
66023 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)
66024 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)
66025 /*! DWP_LOCK - Domain write protection lock
66026  *  0b00..Neither of DWP bits is locked
66027  *  0b01..The lower DWP bit is locked
66028  *  0b10..The higher DWP bit is locked
66029  *  0b11..Both DWP bits are locked
66030  */
66031 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)
66032 /*! @} */
66033 
66034 
66035 /*!
66036  * @}
66037  */ /* end of group IOMUXC_SNVS_Register_Masks */
66038 
66039 
66040 /* IOMUXC_SNVS - Peripheral instance base addresses */
66041 /** Peripheral IOMUXC_SNVS base address */
66042 #define IOMUXC_SNVS_BASE                         (0x40C94000u)
66043 /** Peripheral IOMUXC_SNVS base pointer */
66044 #define IOMUXC_SNVS                              ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
66045 /** Array initializer of IOMUXC_SNVS peripheral base addresses */
66046 #define IOMUXC_SNVS_BASE_ADDRS                   { IOMUXC_SNVS_BASE }
66047 /** Array initializer of IOMUXC_SNVS peripheral base pointers */
66048 #define IOMUXC_SNVS_BASE_PTRS                    { IOMUXC_SNVS }
66049 
66050 /*!
66051  * @}
66052  */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
66053 
66054 
66055 /* ----------------------------------------------------------------------------
66056    -- IOMUXC_SNVS_GPR Peripheral Access Layer
66057    ---------------------------------------------------------------------------- */
66058 
66059 /*!
66060  * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
66061  * @{
66062  */
66063 
66064 /** IOMUXC_SNVS_GPR - Register Layout Typedef */
66065 typedef struct {
66066   __IO uint32_t GPR[32];                           /**< GPR0 General Purpose Register, array offset: 0x0, array step: 0x4 */
66067   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
66068   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
66069   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
66070   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
66071   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
66072   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
66073 } IOMUXC_SNVS_GPR_Type;
66074 
66075 /* ----------------------------------------------------------------------------
66076    -- IOMUXC_SNVS_GPR Register Masks
66077    ---------------------------------------------------------------------------- */
66078 
66079 /*!
66080  * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
66081  * @{
66082  */
66083 
66084 /*! @name GPR - GPR0 General Purpose Register */
66085 /*! @{ */
66086 
66087 #define IOMUXC_SNVS_GPR_GPR_GPR_MASK             (0xFFFFFFFFU)
66088 #define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT            (0U)
66089 /*! GPR - General purpose bits
66090  */
66091 #define IOMUXC_SNVS_GPR_GPR_GPR(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK)
66092 /*! @} */
66093 
66094 /* The count of IOMUXC_SNVS_GPR_GPR */
66095 #define IOMUXC_SNVS_GPR_GPR_COUNT                (32U)
66096 
66097 /*! @name GPR32 - GPR32 General Purpose Register */
66098 /*! @{ */
66099 
66100 #define IOMUXC_SNVS_GPR_GPR32_GPR_MASK           (0xFFFEU)
66101 #define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT          (1U)
66102 /*! GPR - General purpose bits
66103  */
66104 #define IOMUXC_SNVS_GPR_GPR32_GPR(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
66105 
66106 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK          (0xFFFF0000U)
66107 #define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT         (16U)
66108 /*! LOCK - Lock the write to bit 15:0
66109  */
66110 #define IOMUXC_SNVS_GPR_GPR32_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
66111 /*! @} */
66112 
66113 /*! @name GPR33 - GPR33 General Purpose Register */
66114 /*! @{ */
66115 
66116 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
66117 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
66118 /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
66119  *  0b0..No change
66120  *  0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
66121  */
66122 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
66123 
66124 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U)
66125 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U)
66126 /*! SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable
66127  *  0b1..Enable bypass
66128  *  0b0..Disable bypass
66129  */
66130 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
66131 
66132 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U)
66133 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U)
66134 /*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect
66135  *  0b1..Voltage on DCDC_IN is lower than 2.6V
66136  *  0b0..Voltage on DCDC_IN is higher than 2.6V
66137  */
66138 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
66139 
66140 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U)
66141 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U)
66142 /*! DCDC_OVER_CUR - DCDC output over current alert
66143  *  0b1..Overcurrent on DCDC output
66144  *  0b0..No Overcurrent on DCDC output
66145  */
66146 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
66147 
66148 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U)
66149 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U)
66150 /*! DCDC_OVER_VOL - DCDC output over voltage alert
66151  *  0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output
66152  *  0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
66153  */
66154 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
66155 
66156 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U)
66157 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U)
66158 /*! DCDC_STS_DC_OK - DCDC status OK
66159  *  0b0..DCDC is settling
66160  *  0b1..DCDC already settled
66161  */
66162 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
66163 
66164 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U)
66165 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U)
66166 /*! SNVS_XTAL_CLK_OK - 32K OSC ok flag
66167  *  0b1..32K oscillator is stable into normal operation
66168  *  0b0..32K oscillator is NOT stable into normal operation
66169  */
66170 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
66171 /*! @} */
66172 
66173 /*! @name GPR34 - GPR34 General Purpose Register */
66174 /*! @{ */
66175 
66176 #define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK          (0x1U)
66177 #define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT         (0U)
66178 /*! LOCK - Lock the write to bit 31:1
66179  *  0b0..Write access is not blocked
66180  *  0b1..Write access is blocked
66181  */
66182 #define IOMUXC_SNVS_GPR_GPR34_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
66183 
66184 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
66185 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
66186 /*! SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select
66187  *  0b0..The trimming codes are selected from eFuse
66188  *  0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
66189  */
66190 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
66191 
66192 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU)
66193 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U)
66194 /*! SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim
66195  */
66196 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
66197 
66198 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U)
66199 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U)
66200 /*! SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select
66201  *  0b0..The trimming codes are selected from eFuse
66202  *  0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
66203  */
66204 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
66205 
66206 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U)
66207 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U)
66208 /*! SNVS_CLK_DET_TRIM - SNVS clock detect trim bits
66209  */
66210 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
66211 
66212 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U)
66213 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U)
66214 /*! SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency
66215  *  0b00..No change (Default)
66216  *  0b01..Add +5 to the Trim
66217  *  0b10..Add +10 to the trim
66218  *  0b11..Add -5 to the Trim
66219  */
66220 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
66221 
66222 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U)
66223 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U)
66224 /*! SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency
66225  *  0b00..No change (Default)
66226  *  0b01..Add +5 to the Trim
66227  *  0b10..Add +10 to the trim
66228  *  0b11..Add -5 to the Trim
66229  */
66230 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
66231 
66232 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U)
66233 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U)
66234 /*! SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select
66235  *  0b0..The trimming codes are selected from eFuse
66236  *  0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
66237  */
66238 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
66239 
66240 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U)
66241 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U)
66242 /*! SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim
66243  */
66244 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
66245 /*! @} */
66246 
66247 /*! @name GPR35 - GPR35 General Purpose Register */
66248 /*! @{ */
66249 
66250 #define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK          (0x1U)
66251 #define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT         (0U)
66252 /*! LOCK - Lock the write to bit 31:1
66253  *  0b0..Write access is not blocked
66254  *  0b1..Write access is blocked
66255  */
66256 #define IOMUXC_SNVS_GPR_GPR35_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
66257 
66258 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U)
66259 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U)
66260 /*! SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select
66261  *  0b0..The trimming codes are selected from eFuse
66262  *  0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
66263  */
66264 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
66265 
66266 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U)
66267 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U)
66268 /*! SNVS_VOLT_DET_TRIM - SNVS voltage detect trim
66269  */
66270 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
66271 
66272 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U)
66273 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U)
66274 /*! SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select
66275  *  0b0..The trimming codes are selected from eFuse
66276  *  0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
66277  */
66278 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
66279 
66280 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U)
66281 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U)
66282 /*! SNVS_TEMP_DET_TRIM - SNVS temperature detect trim
66283  */
66284 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
66285 
66286 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U)
66287 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U)
66288 /*! SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary
66289  *  0b00..No change (Default)
66290  *  0b01..Add +5 to the Trim
66291  *  0b10..Add +10 to the trim
66292  *  0b11..Add -5 to the Trim
66293  */
66294 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
66295 
66296 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U)
66297 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U)
66298 /*! SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary
66299  *  0b00..No change (Default)
66300  *  0b01..Add +5 to the Trim
66301  *  0b10..Add +10 to the trim
66302  *  0b11..Add -5 to the Trim
66303  */
66304 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
66305 /*! @} */
66306 
66307 /*! @name GPR36 - GPR36 General Purpose Register */
66308 /*! @{ */
66309 
66310 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U)
66311 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U)
66312 /*! SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit
66313  *  0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off
66314  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
66315  */
66316 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
66317 
66318 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U)
66319 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U)
66320 /*! SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit
66321  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled)
66322  *  0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit
66323  *       ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so
66324  *       this bit is default high.
66325  */
66326 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
66327 
66328 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U)
66329 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U)
66330 /*! SNVS_SRAM_STDBY - SNVS SRAM standby enable bit
66331  *  0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF
66332  *  0b0..SNVS SRAM does not enter low leakage state
66333  */
66334 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
66335 
66336 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U)
66337 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U)
66338 /*! SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral
66339  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
66340  *  0b0..Switch on SNVS SRAM power for peripheral
66341  */
66342 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
66343 
66344 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U)
66345 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U)
66346 /*! SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit
66347  *  0b1..Switch off SNVS SRAM power for peripheral and array
66348  *  0b0..Switch on SNVS SRAM power for peripheral and array
66349  */
66350 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
66351 
66352 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U)
66353 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U)
66354 /*! SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral
66355  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
66356  *  0b0..Switch on SNVS SRAM power for peripheral
66357  */
66358 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
66359 
66360 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U)
66361 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U)
66362 /*! SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit
66363  *  0b1..Switch off SNVS SRAM power for peripheral and array
66364  *  0b0..Switch on SNVS SRAM power for peripheral and array
66365  */
66366 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
66367 /*! @} */
66368 
66369 /*! @name GPR37 - GPR37 General Purpose Register */
66370 /*! @{ */
66371 
66372 #define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK          (0x1U)
66373 #define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT         (0U)
66374 /*! LOCK - Lock the write to bit 31:1
66375  *  0b0..Write access is not blocked
66376  *  0b1..Write access is blocked
66377  */
66378 #define IOMUXC_SNVS_GPR_GPR37_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
66379 
66380 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU)
66381 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U)
66382 /*! SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit
66383  */
66384 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
66385 
66386 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U)
66387 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U)
66388 /*! SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit
66389  */
66390 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
66391 /*! @} */
66392 
66393 
66394 /*!
66395  * @}
66396  */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
66397 
66398 
66399 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
66400 /** Peripheral IOMUXC_SNVS_GPR base address */
66401 #define IOMUXC_SNVS_GPR_BASE                     (0x40C98000u)
66402 /** Peripheral IOMUXC_SNVS_GPR base pointer */
66403 #define IOMUXC_SNVS_GPR                          ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
66404 /** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
66405 #define IOMUXC_SNVS_GPR_BASE_ADDRS               { IOMUXC_SNVS_GPR_BASE }
66406 /** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
66407 #define IOMUXC_SNVS_GPR_BASE_PTRS                { IOMUXC_SNVS_GPR }
66408 
66409 /*!
66410  * @}
66411  */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
66412 
66413 
66414 /* ----------------------------------------------------------------------------
66415    -- IPS_DOMAIN Peripheral Access Layer
66416    ---------------------------------------------------------------------------- */
66417 
66418 /*!
66419  * @addtogroup IPS_DOMAIN_Peripheral_Access_Layer IPS_DOMAIN Peripheral Access Layer
66420  * @{
66421  */
66422 
66423 /** IPS_DOMAIN - Register Layout Typedef */
66424 typedef struct {
66425   struct {                                         /* offset: 0x0, array step: 0x10 */
66426     __IO uint32_t SLOT_CTRL;                         /**< Slot Control Register, array offset: 0x0, array step: 0x10 */
66427          uint8_t RESERVED_0[12];
66428   } SLOT_CTRL[38];
66429 } IPS_DOMAIN_Type;
66430 
66431 /* ----------------------------------------------------------------------------
66432    -- IPS_DOMAIN Register Masks
66433    ---------------------------------------------------------------------------- */
66434 
66435 /*!
66436  * @addtogroup IPS_DOMAIN_Register_Masks IPS_DOMAIN Register Masks
66437  * @{
66438  */
66439 
66440 /*! @name SLOT_CTRL - Slot Control Register */
66441 /*! @{ */
66442 
66443 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU)
66444 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U)
66445 /*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked
66446  */
66447 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
66448 
66449 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK    (0x8000U)
66450 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT   (15U)
66451 /*! DOMAIN_LOCK - Lock domain ID of this slot
66452  *  0b0..Do not lock the domain ID
66453  *  0b1..Lock the domain ID
66454  */
66455 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK)
66456 
66457 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U)
66458 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U)
66459 /*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register
66460  *  0b0..Do not allow non-secure write access
66461  *  0b1..Allow non-secure write access
66462  */
66463 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x)  (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK)
66464 
66465 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK     (0x20000U)
66466 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT    (17U)
66467 /*! ALLOW_USER - Allow user write access to this domain control register or domain register
66468  *  0b0..Do not allow user write access
66469  *  0b1..Allow user write access
66470  */
66471 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x)       (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK)
66472 
66473 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
66474 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT  (31U)
66475 /*! LOCK_CONTROL - Lock control of this slot
66476  *  0b0..Do not lock the control register of this slot
66477  *  0b1..Lock the control register of this slot
66478  */
66479 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x)     (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK)
66480 /*! @} */
66481 
66482 /* The count of IPS_DOMAIN_SLOT_CTRL */
66483 #define IPS_DOMAIN_SLOT_CTRL_COUNT               (38U)
66484 
66485 
66486 /*!
66487  * @}
66488  */ /* end of group IPS_DOMAIN_Register_Masks */
66489 
66490 
66491 /* IPS_DOMAIN - Peripheral instance base addresses */
66492 /** Peripheral IPS_DOMAIN base address */
66493 #define IPS_DOMAIN_BASE                          (0x40C87C00u)
66494 /** Peripheral IPS_DOMAIN base pointer */
66495 #define IPS_DOMAIN                               ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
66496 /** Array initializer of IPS_DOMAIN peripheral base addresses */
66497 #define IPS_DOMAIN_BASE_ADDRS                    { IPS_DOMAIN_BASE }
66498 /** Array initializer of IPS_DOMAIN peripheral base pointers */
66499 #define IPS_DOMAIN_BASE_PTRS                     { IPS_DOMAIN }
66500 
66501 /*!
66502  * @}
66503  */ /* end of group IPS_DOMAIN_Peripheral_Access_Layer */
66504 
66505 
66506 /* ----------------------------------------------------------------------------
66507    -- KEY_MANAGER Peripheral Access Layer
66508    ---------------------------------------------------------------------------- */
66509 
66510 /*!
66511  * @addtogroup KEY_MANAGER_Peripheral_Access_Layer KEY_MANAGER Peripheral Access Layer
66512  * @{
66513  */
66514 
66515 /** KEY_MANAGER - Register Layout Typedef */
66516 typedef struct {
66517   __IO uint32_t MASTER_KEY_CTRL;                   /**< CSR Master Key Control Register, offset: 0x0 */
66518        uint8_t RESERVED_0[12];
66519   __IO uint32_t OTFAD1_KEY_CTRL;                   /**< CSR OTFAD-1 Key Control, offset: 0x10 */
66520        uint8_t RESERVED_1[4];
66521   __IO uint32_t OTFAD2_KEY_CTRL;                   /**< CSR OTFAD-2 Key Control, offset: 0x18 */
66522        uint8_t RESERVED_2[4];
66523   __IO uint32_t IEE_KEY_CTRL;                      /**< CSR IEE Key Control, offset: 0x20 */
66524        uint8_t RESERVED_3[12];
66525   __IO uint32_t PUF_KEY_CTRL;                      /**< CSR PUF Key Control, offset: 0x30 */
66526        uint8_t RESERVED_4[972];
66527   __IO uint32_t SLOT0_CTRL;                        /**< Slot 0 Control, offset: 0x400 */
66528   __IO uint32_t SLOT1_CTRL;                        /**< Slot1 Control, offset: 0x404 */
66529   __IO uint32_t SLOT2_CTRL;                        /**< Slot2 Control, offset: 0x408 */
66530   __IO uint32_t SLOT3_CTRL;                        /**< Slot3 Control, offset: 0x40C */
66531   __IO uint32_t SLOT4_CTRL;                        /**< Slot 4 Control, offset: 0x410 */
66532 } KEY_MANAGER_Type;
66533 
66534 /* ----------------------------------------------------------------------------
66535    -- KEY_MANAGER Register Masks
66536    ---------------------------------------------------------------------------- */
66537 
66538 /*!
66539  * @addtogroup KEY_MANAGER_Register_Masks KEY_MANAGER Register Masks
66540  * @{
66541  */
66542 
66543 /*! @name MASTER_KEY_CTRL - CSR Master Key Control Register */
66544 /*! @{ */
66545 
66546 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK  (0x1U)
66547 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U)
66548 /*! SELECT - Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL.
66549  *  0b0..select key from UDF
66550  *  0b1..If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS)
66551  */
66552 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK)
66553 
66554 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK    (0x10000U)
66555 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT   (16U)
66556 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK.
66557  *  0b0..not locked
66558  *  0b1..locked
66559  */
66560 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK)
66561 /*! @} */
66562 
66563 /*! @name OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */
66564 /*! @{ */
66565 
66566 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK  (0x1U)
66567 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U)
66568 /*! SELECT - key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL.
66569  *  0b0..Select key from OCOTP USER_KEY5
66570  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
66571  */
66572 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK)
66573 
66574 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK    (0x10000U)
66575 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT   (16U)
66576 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK.
66577  *  0b0..not locked
66578  *  0b1..locked
66579  */
66580 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK)
66581 /*! @} */
66582 
66583 /*! @name OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */
66584 /*! @{ */
66585 
66586 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK  (0x1U)
66587 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U)
66588 /*! SELECT - key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL.
66589  *  0b0..select key from OCOTP USER_KEY5
66590  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
66591  */
66592 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK)
66593 
66594 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK    (0x10000U)
66595 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT   (16U)
66596 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK.
66597  *  0b0..not locked
66598  *  0b1..locked
66599  */
66600 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK)
66601 /*! @} */
66602 
66603 /*! @name IEE_KEY_CTRL - CSR IEE Key Control */
66604 /*! @{ */
66605 
66606 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK     (0x1U)
66607 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT    (0U)
66608 /*! RELOAD - Restart load key signal for IEE
66609  *  0b0..Do nothing
66610  *  0b1..Restart IEE key load flow
66611  */
66612 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK)
66613 /*! @} */
66614 
66615 /*! @name PUF_KEY_CTRL - CSR PUF Key Control */
66616 /*! @{ */
66617 
66618 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK       (0x1U)
66619 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT      (0U)
66620 /*! LOCK - Lock signal for key select
66621  *  0b0..Do not lock the key select
66622  *  0b1..Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has
66623  *       been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done.
66624  */
66625 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK)
66626 /*! @} */
66627 
66628 /*! @name SLOT0_CTRL - Slot 0 Control */
66629 /*! @{ */
66630 
66631 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK   (0xFU)
66632 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT  (0U)
66633 /*! WHITE_LIST - Whitelist
66634  */
66635 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK)
66636 
66637 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK    (0x8000U)
66638 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT   (15U)
66639 /*! LOCK_LIST - Lock whitelist
66640  *  0b0..Whitelist is not locked
66641  *  0b1..Whitelist is locked
66642  */
66643 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK)
66644 
66645 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK        (0x10000U)
66646 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT       (16U)
66647 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66648  *  0b0..Do not allow non-secure write access
66649  *  0b1..Allow non-secure write access
66650  */
66651 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK)
66652 
66653 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK      (0x20000U)
66654 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT     (17U)
66655 /*! TZ_USER - Allow user write access to this register and the slot it controls
66656  *  0b0..Do not allow user write access
66657  *  0b1..Allow user write access
66658  */
66659 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK)
66660 
66661 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66662 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U)
66663 /*! LOCK_CONTROL - Lock control of this slot
66664  *  0b0..Do not lock the control register of this slot
66665  *  0b1..Lock the control register of this slot
66666  */
66667 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK)
66668 /*! @} */
66669 
66670 /*! @name SLOT1_CTRL - Slot1 Control */
66671 /*! @{ */
66672 
66673 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK   (0xFU)
66674 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT  (0U)
66675 /*! WHITE_LIST - Whitelist
66676  */
66677 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK)
66678 
66679 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK    (0x8000U)
66680 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT   (15U)
66681 /*! LOCK_LIST - Lock whitelist
66682  *  0b0..Whitelist is not locked
66683  *  0b1..Whitelist is locked
66684  */
66685 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK)
66686 
66687 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK        (0x10000U)
66688 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT       (16U)
66689 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66690  *  0b0..Do not allow non-secure write access
66691  *  0b1..Allow non-secure write access
66692  */
66693 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK)
66694 
66695 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK      (0x20000U)
66696 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT     (17U)
66697 /*! TZ_USER - Allow user write access to this register and the slot it controls
66698  *  0b0..Do not allow user write access
66699  *  0b1..Allow user write access
66700  */
66701 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK)
66702 
66703 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66704 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U)
66705 /*! LOCK_CONTROL - Lock control of this slot
66706  *  0b0..Do not lock the control register of this slot
66707  *  0b1..Lock the control register of this slot
66708  */
66709 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK)
66710 /*! @} */
66711 
66712 /*! @name SLOT2_CTRL - Slot2 Control */
66713 /*! @{ */
66714 
66715 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK   (0xFU)
66716 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT  (0U)
66717 /*! WHITE_LIST - Whitelist
66718  */
66719 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK)
66720 
66721 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK    (0x8000U)
66722 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT   (15U)
66723 /*! LOCK_LIST - Lock whitelist
66724  *  0b0..Whitelist is not locked
66725  *  0b1..Whitelist is locked
66726  */
66727 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK)
66728 
66729 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK        (0x10000U)
66730 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT       (16U)
66731 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66732  *  0b0..Do not allow non-secure write access
66733  *  0b1..Allow non-secure write access
66734  */
66735 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK)
66736 
66737 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK      (0x20000U)
66738 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT     (17U)
66739 /*! TZ_USER - Allow user write access to this register and the slot it controls
66740  *  0b0..Do not allow user write access
66741  *  0b1..Allow user write access
66742  */
66743 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK)
66744 
66745 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66746 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U)
66747 /*! LOCK_CONTROL - Lock control of this slot
66748  *  0b0..Do not lock the control register of this slot
66749  *  0b1..Lock the control register of this slot
66750  */
66751 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK)
66752 /*! @} */
66753 
66754 /*! @name SLOT3_CTRL - Slot3 Control */
66755 /*! @{ */
66756 
66757 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK   (0xFU)
66758 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT  (0U)
66759 /*! WHITE_LIST - Whitelist
66760  */
66761 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK)
66762 
66763 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK    (0x8000U)
66764 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT   (15U)
66765 /*! LOCK_LIST - Lock whitelist
66766  *  0b0..Whitelist is not locked
66767  *  0b1..Whitelist is locked
66768  */
66769 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK)
66770 
66771 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK        (0x10000U)
66772 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT       (16U)
66773 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66774  *  0b0..Do not allow non-secure write access
66775  *  0b1..Allow non-secure write access
66776  */
66777 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK)
66778 
66779 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK      (0x20000U)
66780 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT     (17U)
66781 /*! TZ_USER - Allow user write access to this register and the slot it controls
66782  *  0b0..Do not allow user write access
66783  *  0b1..Allow user write access
66784  */
66785 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK)
66786 
66787 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66788 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U)
66789 /*! LOCK_CONTROL - Lock control of this slot
66790  *  0b0..Do not lock the control register of this slot
66791  *  0b1..Lock the control register of this slot
66792  */
66793 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK)
66794 /*! @} */
66795 
66796 /*! @name SLOT4_CTRL - Slot 4 Control */
66797 /*! @{ */
66798 
66799 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK   (0xFU)
66800 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT  (0U)
66801 /*! WHITE_LIST - Whitelist
66802  */
66803 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK)
66804 
66805 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK    (0x8000U)
66806 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT   (15U)
66807 /*! LOCK_LIST - Lock whitelist
66808  *  0b0..Whitelist is not locked
66809  *  0b1..Whitelist is locked
66810  */
66811 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK)
66812 
66813 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK        (0x10000U)
66814 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT       (16U)
66815 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
66816  *  0b0..Do not allow non-secure write access
66817  *  0b1..Allow non-secure write access
66818  */
66819 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK)
66820 
66821 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK      (0x20000U)
66822 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT     (17U)
66823 /*! TZ_USER - Allow user write access to this register and the slot it controls
66824  *  0b0..Do not allow user write access
66825  *  0b1..Allow user write access
66826  */
66827 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK)
66828 
66829 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U)
66830 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U)
66831 /*! LOCK_CONTROL - Lock control of this slot
66832  *  0b0..Do not lock the control register of this slot
66833  *  0b1..Lock the control register of this slot
66834  */
66835 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK)
66836 /*! @} */
66837 
66838 
66839 /*!
66840  * @}
66841  */ /* end of group KEY_MANAGER_Register_Masks */
66842 
66843 
66844 /* KEY_MANAGER - Peripheral instance base addresses */
66845 /** Peripheral KEY_MANAGER base address */
66846 #define KEY_MANAGER_BASE                         (0x40C80000u)
66847 /** Peripheral KEY_MANAGER base pointer */
66848 #define KEY_MANAGER                              ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
66849 /** Array initializer of KEY_MANAGER peripheral base addresses */
66850 #define KEY_MANAGER_BASE_ADDRS                   { KEY_MANAGER_BASE }
66851 /** Array initializer of KEY_MANAGER peripheral base pointers */
66852 #define KEY_MANAGER_BASE_PTRS                    { KEY_MANAGER }
66853 
66854 /*!
66855  * @}
66856  */ /* end of group KEY_MANAGER_Peripheral_Access_Layer */
66857 
66858 
66859 /* ----------------------------------------------------------------------------
66860    -- KPP Peripheral Access Layer
66861    ---------------------------------------------------------------------------- */
66862 
66863 /*!
66864  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
66865  * @{
66866  */
66867 
66868 /** KPP - Register Layout Typedef */
66869 typedef struct {
66870   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
66871   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
66872   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
66873   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
66874 } KPP_Type;
66875 
66876 /* ----------------------------------------------------------------------------
66877    -- KPP Register Masks
66878    ---------------------------------------------------------------------------- */
66879 
66880 /*!
66881  * @addtogroup KPP_Register_Masks KPP Register Masks
66882  * @{
66883  */
66884 
66885 /*! @name KPCR - Keypad Control Register */
66886 /*! @{ */
66887 
66888 #define KPP_KPCR_KRE_MASK                        (0xFFU)
66889 #define KPP_KPCR_KRE_SHIFT                       (0U)
66890 /*! KRE - KRE
66891  *  0b00000000..Row is not included in the keypad key press detect.
66892  *  0b00000001..Row is included in the keypad key press detect.
66893  */
66894 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
66895 
66896 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
66897 #define KPP_KPCR_KCO_SHIFT                       (8U)
66898 /*! KCO - KCO
66899  *  0b00000000..Column strobe output is totem pole drive.
66900  *  0b00000001..Column strobe output is open drain.
66901  */
66902 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
66903 /*! @} */
66904 
66905 /*! @name KPSR - Keypad Status Register */
66906 /*! @{ */
66907 
66908 #define KPP_KPSR_KPKD_MASK                       (0x1U)
66909 #define KPP_KPSR_KPKD_SHIFT                      (0U)
66910 /*! KPKD - KPKD
66911  *  0b0..No key presses detected
66912  *  0b1..A key has been depressed
66913  */
66914 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
66915 
66916 #define KPP_KPSR_KPKR_MASK                       (0x2U)
66917 #define KPP_KPSR_KPKR_SHIFT                      (1U)
66918 /*! KPKR - KPKR
66919  *  0b0..No key release detected
66920  *  0b1..All keys have been released
66921  */
66922 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
66923 
66924 #define KPP_KPSR_KDSC_MASK                       (0x4U)
66925 #define KPP_KPSR_KDSC_SHIFT                      (2U)
66926 /*! KDSC - KDSC
66927  *  0b0..No effect
66928  *  0b1..Set bits that clear the keypad depress synchronizer chain
66929  */
66930 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
66931 
66932 #define KPP_KPSR_KRSS_MASK                       (0x8U)
66933 #define KPP_KPSR_KRSS_SHIFT                      (3U)
66934 /*! KRSS - KRSS
66935  *  0b0..No effect
66936  *  0b1..Set bits which sets keypad release synchronizer chain
66937  */
66938 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
66939 
66940 #define KPP_KPSR_KDIE_MASK                       (0x100U)
66941 #define KPP_KPSR_KDIE_SHIFT                      (8U)
66942 /*! KDIE - KDIE
66943  *  0b0..No interrupt request is generated when KPKD is set.
66944  *  0b1..An interrupt request is generated when KPKD is set.
66945  */
66946 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
66947 
66948 #define KPP_KPSR_KRIE_MASK                       (0x200U)
66949 #define KPP_KPSR_KRIE_SHIFT                      (9U)
66950 /*! KRIE - KRIE
66951  *  0b0..No interrupt request is generated when KPKR is set.
66952  *  0b1..An interrupt request is generated when KPKR is set.
66953  */
66954 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
66955 /*! @} */
66956 
66957 /*! @name KDDR - Keypad Data Direction Register */
66958 /*! @{ */
66959 
66960 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
66961 #define KPP_KDDR_KRDD_SHIFT                      (0U)
66962 /*! KRDD - KRDD
66963  *  0b00000000..ROWn pin configured as an input.
66964  *  0b00000001..ROWn pin configured as an output.
66965  */
66966 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
66967 
66968 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
66969 #define KPP_KDDR_KCDD_SHIFT                      (8U)
66970 /*! KCDD - KCDD
66971  *  0b00000000..COLn pin is configured as an input.
66972  *  0b00000001..COLn pin is configured as an output.
66973  */
66974 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
66975 /*! @} */
66976 
66977 /*! @name KPDR - Keypad Data Register */
66978 /*! @{ */
66979 
66980 #define KPP_KPDR_KRD_MASK                        (0xFFU)
66981 #define KPP_KPDR_KRD_SHIFT                       (0U)
66982 /*! KRD - KRD
66983  */
66984 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
66985 
66986 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
66987 #define KPP_KPDR_KCD_SHIFT                       (8U)
66988 /*! KCD - KCD
66989  */
66990 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
66991 /*! @} */
66992 
66993 
66994 /*!
66995  * @}
66996  */ /* end of group KPP_Register_Masks */
66997 
66998 
66999 /* KPP - Peripheral instance base addresses */
67000 /** Peripheral KPP base address */
67001 #define KPP_BASE                                 (0x400E0000u)
67002 /** Peripheral KPP base pointer */
67003 #define KPP                                      ((KPP_Type *)KPP_BASE)
67004 /** Array initializer of KPP peripheral base addresses */
67005 #define KPP_BASE_ADDRS                           { KPP_BASE }
67006 /** Array initializer of KPP peripheral base pointers */
67007 #define KPP_BASE_PTRS                            { KPP }
67008 /** Interrupt vectors for the KPP peripheral type */
67009 #define KPP_IRQS                                 { KPP_IRQn }
67010 
67011 /*!
67012  * @}
67013  */ /* end of group KPP_Peripheral_Access_Layer */
67014 
67015 
67016 /* ----------------------------------------------------------------------------
67017    -- LCDIF Peripheral Access Layer
67018    ---------------------------------------------------------------------------- */
67019 
67020 /*!
67021  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
67022  * @{
67023  */
67024 
67025 /** LCDIF - Register Layout Typedef */
67026 typedef struct {
67027   __IO uint32_t CTRL;                              /**< LCDIF General Control Register, offset: 0x0 */
67028   __IO uint32_t CTRL_SET;                          /**< LCDIF General Control Register, offset: 0x4 */
67029   __IO uint32_t CTRL_CLR;                          /**< LCDIF General Control Register, offset: 0x8 */
67030   __IO uint32_t CTRL_TOG;                          /**< LCDIF General Control Register, offset: 0xC */
67031   __IO uint32_t CTRL1;                             /**< LCDIF General Control1 Register, offset: 0x10 */
67032   __IO uint32_t CTRL1_SET;                         /**< LCDIF General Control1 Register, offset: 0x14 */
67033   __IO uint32_t CTRL1_CLR;                         /**< LCDIF General Control1 Register, offset: 0x18 */
67034   __IO uint32_t CTRL1_TOG;                         /**< LCDIF General Control1 Register, offset: 0x1C */
67035   __IO uint32_t CTRL2;                             /**< LCDIF General Control2 Register, offset: 0x20 */
67036   __IO uint32_t CTRL2_SET;                         /**< LCDIF General Control2 Register, offset: 0x24 */
67037   __IO uint32_t CTRL2_CLR;                         /**< LCDIF General Control2 Register, offset: 0x28 */
67038   __IO uint32_t CTRL2_TOG;                         /**< LCDIF General Control2 Register, offset: 0x2C */
67039   __IO uint32_t TRANSFER_COUNT;                    /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
67040        uint8_t RESERVED_0[12];
67041   __IO uint32_t CUR_BUF;                           /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
67042        uint8_t RESERVED_1[12];
67043   __IO uint32_t NEXT_BUF;                          /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
67044        uint8_t RESERVED_2[28];
67045   __IO uint32_t VDCTRL0;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
67046   __IO uint32_t VDCTRL0_SET;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
67047   __IO uint32_t VDCTRL0_CLR;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
67048   __IO uint32_t VDCTRL0_TOG;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
67049   __IO uint32_t VDCTRL1;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
67050        uint8_t RESERVED_3[12];
67051   __IO uint32_t VDCTRL2;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
67052        uint8_t RESERVED_4[12];
67053   __IO uint32_t VDCTRL3;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
67054        uint8_t RESERVED_5[12];
67055   __IO uint32_t VDCTRL4;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
67056        uint8_t RESERVED_6[220];
67057   __IO uint32_t BM_ERROR_STAT;                     /**< Bus Master Error Status Register, offset: 0x190 */
67058        uint8_t RESERVED_7[12];
67059   __IO uint32_t CRC_STAT;                          /**< CRC Status Register, offset: 0x1A0 */
67060        uint8_t RESERVED_8[12];
67061   __I  uint32_t STAT;                              /**< LCD Interface Status Register, offset: 0x1B0 */
67062        uint8_t RESERVED_9[76];
67063   __IO uint32_t THRES;                             /**< LCDIF Threshold Register, offset: 0x200 */
67064        uint8_t RESERVED_10[380];
67065   __IO uint32_t PIGEONCTRL0;                       /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
67066   __IO uint32_t PIGEONCTRL0_SET;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
67067   __IO uint32_t PIGEONCTRL0_CLR;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
67068   __IO uint32_t PIGEONCTRL0_TOG;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
67069   __IO uint32_t PIGEONCTRL1;                       /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
67070   __IO uint32_t PIGEONCTRL1_SET;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
67071   __IO uint32_t PIGEONCTRL1_CLR;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
67072   __IO uint32_t PIGEONCTRL1_TOG;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
67073   __IO uint32_t PIGEONCTRL2;                       /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
67074   __IO uint32_t PIGEONCTRL2_SET;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
67075   __IO uint32_t PIGEONCTRL2_CLR;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
67076   __IO uint32_t PIGEONCTRL2_TOG;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
67077        uint8_t RESERVED_11[1104];
67078   struct {                                         /* offset: 0x800, array step: 0x40 */
67079     __IO uint32_t PIGEON_0;                          /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
67080          uint8_t RESERVED_0[12];
67081     __IO uint32_t PIGEON_1;                          /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
67082          uint8_t RESERVED_1[12];
67083     __IO uint32_t PIGEON_2;                          /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
67084          uint8_t RESERVED_2[28];
67085   } PIGEON[12];
67086   __IO uint32_t LUT_CTRL;                          /**< Look Up Table Control Register, offset: 0xB00 */
67087        uint8_t RESERVED_12[12];
67088   __IO uint32_t LUT0_ADDR;                         /**< Lookup Table 0 Index Register, offset: 0xB10 */
67089        uint8_t RESERVED_13[12];
67090   __IO uint32_t LUT0_DATA;                         /**< Lookup Table 0 Data Register, offset: 0xB20 */
67091        uint8_t RESERVED_14[12];
67092   __IO uint32_t LUT1_ADDR;                         /**< Lookup Table 1 Index Register, offset: 0xB30 */
67093        uint8_t RESERVED_15[12];
67094   __IO uint32_t LUT1_DATA;                         /**< Lookup Table 1 Data Register, offset: 0xB40 */
67095 } LCDIF_Type;
67096 
67097 /* ----------------------------------------------------------------------------
67098    -- LCDIF Register Masks
67099    ---------------------------------------------------------------------------- */
67100 
67101 /*!
67102  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
67103  * @{
67104  */
67105 
67106 /*! @name CTRL - LCDIF General Control Register */
67107 /*! @{ */
67108 
67109 #define LCDIF_CTRL_RUN_MASK                      (0x1U)
67110 #define LCDIF_CTRL_RUN_SHIFT                     (0U)
67111 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
67112 
67113 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
67114 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
67115 /*! DATA_FORMAT_24_BIT
67116  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
67117  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
67118  *       each byte do not contain any useful data, and should be dropped.
67119  */
67120 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
67121 
67122 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
67123 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
67124 /*! DATA_FORMAT_18_BIT
67125  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
67126  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
67127  */
67128 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
67129 
67130 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
67131 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
67132 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
67133 
67134 #define LCDIF_CTRL_RSRVD0_MASK                   (0x10U)
67135 #define LCDIF_CTRL_RSRVD0_SHIFT                  (4U)
67136 #define LCDIF_CTRL_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
67137 
67138 #define LCDIF_CTRL_MASTER_MASK                   (0x20U)
67139 #define LCDIF_CTRL_MASTER_SHIFT                  (5U)
67140 #define LCDIF_CTRL_MASTER(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
67141 
67142 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK     (0x40U)
67143 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT    (6U)
67144 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
67145 
67146 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
67147 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
67148 /*! WORD_LENGTH
67149  *  0b00..Input data is 16 bits per pixel.
67150  *  0b01..Input data is 8 bits wide.
67151  *  0b10..Input data is 18 bits per pixel.
67152  *  0b11..Input data is 24 bits per pixel.
67153  */
67154 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
67155 
67156 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
67157 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
67158 /*! LCD_DATABUS_WIDTH
67159  *  0b00..16-bit data bus mode.
67160  *  0b01..8-bit data bus mode.
67161  *  0b10..18-bit data bus mode.
67162  *  0b11..24-bit data bus mode.
67163  */
67164 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
67165 
67166 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
67167 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
67168 /*! CSC_DATA_SWIZZLE
67169  *  0b00..No byte swapping.(Little endian)
67170  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67171  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67172  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67173  *  0b10..Swap half-words.
67174  *  0b11..Swap bytes within each half-word.
67175  */
67176 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
67177 
67178 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
67179 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
67180 /*! INPUT_DATA_SWIZZLE
67181  *  0b00..No byte swapping.(Little endian)
67182  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67183  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67184  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67185  *  0b10..Swap half-words.
67186  *  0b11..Swap bytes within each half-word.
67187  */
67188 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
67189 
67190 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
67191 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
67192 #define LCDIF_CTRL_DOTCLK_MODE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
67193 
67194 #define LCDIF_CTRL_BYPASS_COUNT_MASK             (0x80000U)
67195 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT            (19U)
67196 #define LCDIF_CTRL_BYPASS_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
67197 
67198 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK           (0x3E00000U)
67199 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT          (21U)
67200 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
67201 
67202 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
67203 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
67204 /*! DATA_SHIFT_DIR
67205  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
67206  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
67207  */
67208 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
67209 
67210 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
67211 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
67212 #define LCDIF_CTRL_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
67213 
67214 #define LCDIF_CTRL_SFTRST_MASK                   (0x80000000U)
67215 #define LCDIF_CTRL_SFTRST_SHIFT                  (31U)
67216 #define LCDIF_CTRL_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
67217 /*! @} */
67218 
67219 /*! @name CTRL_SET - LCDIF General Control Register */
67220 /*! @{ */
67221 
67222 #define LCDIF_CTRL_SET_RUN_MASK                  (0x1U)
67223 #define LCDIF_CTRL_SET_RUN_SHIFT                 (0U)
67224 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
67225 
67226 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
67227 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
67228 /*! DATA_FORMAT_24_BIT
67229  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
67230  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
67231  *       each byte do not contain any useful data, and should be dropped.
67232  */
67233 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
67234 
67235 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
67236 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
67237 /*! DATA_FORMAT_18_BIT
67238  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
67239  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
67240  */
67241 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
67242 
67243 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
67244 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
67245 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
67246 
67247 #define LCDIF_CTRL_SET_RSRVD0_MASK               (0x10U)
67248 #define LCDIF_CTRL_SET_RSRVD0_SHIFT              (4U)
67249 #define LCDIF_CTRL_SET_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
67250 
67251 #define LCDIF_CTRL_SET_MASTER_MASK               (0x20U)
67252 #define LCDIF_CTRL_SET_MASTER_SHIFT              (5U)
67253 #define LCDIF_CTRL_SET_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
67254 
67255 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
67256 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
67257 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
67258 
67259 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
67260 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
67261 /*! WORD_LENGTH
67262  *  0b00..Input data is 16 bits per pixel.
67263  *  0b01..Input data is 8 bits wide.
67264  *  0b10..Input data is 18 bits per pixel.
67265  *  0b11..Input data is 24 bits per pixel.
67266  */
67267 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
67268 
67269 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
67270 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
67271 /*! LCD_DATABUS_WIDTH
67272  *  0b00..16-bit data bus mode.
67273  *  0b01..8-bit data bus mode.
67274  *  0b10..18-bit data bus mode.
67275  *  0b11..24-bit data bus mode.
67276  */
67277 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
67278 
67279 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
67280 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
67281 /*! CSC_DATA_SWIZZLE
67282  *  0b00..No byte swapping.(Little endian)
67283  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67284  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67285  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67286  *  0b10..Swap half-words.
67287  *  0b11..Swap bytes within each half-word.
67288  */
67289 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
67290 
67291 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
67292 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
67293 /*! INPUT_DATA_SWIZZLE
67294  *  0b00..No byte swapping.(Little endian)
67295  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67296  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67297  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67298  *  0b10..Swap half-words.
67299  *  0b11..Swap bytes within each half-word.
67300  */
67301 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
67302 
67303 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
67304 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
67305 #define LCDIF_CTRL_SET_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
67306 
67307 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK         (0x80000U)
67308 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT        (19U)
67309 #define LCDIF_CTRL_SET_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
67310 
67311 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK       (0x3E00000U)
67312 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT      (21U)
67313 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
67314 
67315 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
67316 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
67317 /*! DATA_SHIFT_DIR
67318  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
67319  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
67320  */
67321 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
67322 
67323 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
67324 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
67325 #define LCDIF_CTRL_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
67326 
67327 #define LCDIF_CTRL_SET_SFTRST_MASK               (0x80000000U)
67328 #define LCDIF_CTRL_SET_SFTRST_SHIFT              (31U)
67329 #define LCDIF_CTRL_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
67330 /*! @} */
67331 
67332 /*! @name CTRL_CLR - LCDIF General Control Register */
67333 /*! @{ */
67334 
67335 #define LCDIF_CTRL_CLR_RUN_MASK                  (0x1U)
67336 #define LCDIF_CTRL_CLR_RUN_SHIFT                 (0U)
67337 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
67338 
67339 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
67340 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
67341 /*! DATA_FORMAT_24_BIT
67342  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
67343  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
67344  *       each byte do not contain any useful data, and should be dropped.
67345  */
67346 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
67347 
67348 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
67349 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
67350 /*! DATA_FORMAT_18_BIT
67351  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
67352  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
67353  */
67354 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
67355 
67356 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
67357 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
67358 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
67359 
67360 #define LCDIF_CTRL_CLR_RSRVD0_MASK               (0x10U)
67361 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT              (4U)
67362 #define LCDIF_CTRL_CLR_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
67363 
67364 #define LCDIF_CTRL_CLR_MASTER_MASK               (0x20U)
67365 #define LCDIF_CTRL_CLR_MASTER_SHIFT              (5U)
67366 #define LCDIF_CTRL_CLR_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
67367 
67368 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
67369 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
67370 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
67371 
67372 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
67373 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
67374 /*! WORD_LENGTH
67375  *  0b00..Input data is 16 bits per pixel.
67376  *  0b01..Input data is 8 bits wide.
67377  *  0b10..Input data is 18 bits per pixel.
67378  *  0b11..Input data is 24 bits per pixel.
67379  */
67380 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
67381 
67382 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
67383 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
67384 /*! LCD_DATABUS_WIDTH
67385  *  0b00..16-bit data bus mode.
67386  *  0b01..8-bit data bus mode.
67387  *  0b10..18-bit data bus mode.
67388  *  0b11..24-bit data bus mode.
67389  */
67390 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
67391 
67392 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
67393 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
67394 /*! CSC_DATA_SWIZZLE
67395  *  0b00..No byte swapping.(Little endian)
67396  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67397  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67398  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67399  *  0b10..Swap half-words.
67400  *  0b11..Swap bytes within each half-word.
67401  */
67402 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
67403 
67404 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
67405 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
67406 /*! INPUT_DATA_SWIZZLE
67407  *  0b00..No byte swapping.(Little endian)
67408  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67409  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67410  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67411  *  0b10..Swap half-words.
67412  *  0b11..Swap bytes within each half-word.
67413  */
67414 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
67415 
67416 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
67417 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
67418 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
67419 
67420 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK         (0x80000U)
67421 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT        (19U)
67422 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
67423 
67424 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK       (0x3E00000U)
67425 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT      (21U)
67426 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
67427 
67428 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
67429 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
67430 /*! DATA_SHIFT_DIR
67431  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
67432  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
67433  */
67434 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
67435 
67436 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
67437 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
67438 #define LCDIF_CTRL_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
67439 
67440 #define LCDIF_CTRL_CLR_SFTRST_MASK               (0x80000000U)
67441 #define LCDIF_CTRL_CLR_SFTRST_SHIFT              (31U)
67442 #define LCDIF_CTRL_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
67443 /*! @} */
67444 
67445 /*! @name CTRL_TOG - LCDIF General Control Register */
67446 /*! @{ */
67447 
67448 #define LCDIF_CTRL_TOG_RUN_MASK                  (0x1U)
67449 #define LCDIF_CTRL_TOG_RUN_SHIFT                 (0U)
67450 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
67451 
67452 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
67453 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
67454 /*! DATA_FORMAT_24_BIT
67455  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
67456  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
67457  *       each byte do not contain any useful data, and should be dropped.
67458  */
67459 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
67460 
67461 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
67462 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
67463 /*! DATA_FORMAT_18_BIT
67464  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
67465  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
67466  */
67467 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
67468 
67469 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
67470 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
67471 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
67472 
67473 #define LCDIF_CTRL_TOG_RSRVD0_MASK               (0x10U)
67474 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT              (4U)
67475 #define LCDIF_CTRL_TOG_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
67476 
67477 #define LCDIF_CTRL_TOG_MASTER_MASK               (0x20U)
67478 #define LCDIF_CTRL_TOG_MASTER_SHIFT              (5U)
67479 #define LCDIF_CTRL_TOG_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
67480 
67481 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
67482 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
67483 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
67484 
67485 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
67486 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
67487 /*! WORD_LENGTH
67488  *  0b00..Input data is 16 bits per pixel.
67489  *  0b01..Input data is 8 bits wide.
67490  *  0b10..Input data is 18 bits per pixel.
67491  *  0b11..Input data is 24 bits per pixel.
67492  */
67493 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
67494 
67495 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
67496 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
67497 /*! LCD_DATABUS_WIDTH
67498  *  0b00..16-bit data bus mode.
67499  *  0b01..8-bit data bus mode.
67500  *  0b10..18-bit data bus mode.
67501  *  0b11..24-bit data bus mode.
67502  */
67503 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
67504 
67505 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
67506 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
67507 /*! CSC_DATA_SWIZZLE
67508  *  0b00..No byte swapping.(Little endian)
67509  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67510  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67511  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67512  *  0b10..Swap half-words.
67513  *  0b11..Swap bytes within each half-word.
67514  */
67515 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
67516 
67517 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
67518 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
67519 /*! INPUT_DATA_SWIZZLE
67520  *  0b00..No byte swapping.(Little endian)
67521  *  0b00..Little Endian byte ordering (same as NO_SWAP).
67522  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
67523  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
67524  *  0b10..Swap half-words.
67525  *  0b11..Swap bytes within each half-word.
67526  */
67527 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
67528 
67529 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
67530 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
67531 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
67532 
67533 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK         (0x80000U)
67534 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT        (19U)
67535 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
67536 
67537 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK       (0x3E00000U)
67538 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT      (21U)
67539 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
67540 
67541 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
67542 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
67543 /*! DATA_SHIFT_DIR
67544  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
67545  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
67546  */
67547 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
67548 
67549 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
67550 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
67551 #define LCDIF_CTRL_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
67552 
67553 #define LCDIF_CTRL_TOG_SFTRST_MASK               (0x80000000U)
67554 #define LCDIF_CTRL_TOG_SFTRST_SHIFT              (31U)
67555 #define LCDIF_CTRL_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
67556 /*! @} */
67557 
67558 /*! @name CTRL1 - LCDIF General Control1 Register */
67559 /*! @{ */
67560 
67561 #define LCDIF_CTRL1_RSRVD0_MASK                  (0xF8U)
67562 #define LCDIF_CTRL1_RSRVD0_SHIFT                 (3U)
67563 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
67564 
67565 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
67566 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
67567 /*! VSYNC_EDGE_IRQ
67568  *  0b0..No Interrupt Request Pending.
67569  *  0b1..Interrupt Request Pending.
67570  */
67571 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
67572 
67573 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
67574 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
67575 /*! CUR_FRAME_DONE_IRQ
67576  *  0b0..No Interrupt Request Pending.
67577  *  0b1..Interrupt Request Pending.
67578  */
67579 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
67580 
67581 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
67582 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
67583 /*! UNDERFLOW_IRQ
67584  *  0b0..No Interrupt Request Pending.
67585  *  0b1..Interrupt Request Pending.
67586  */
67587 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
67588 
67589 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
67590 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
67591 /*! OVERFLOW_IRQ
67592  *  0b0..No Interrupt Request Pending.
67593  *  0b1..Interrupt Request Pending.
67594  */
67595 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
67596 
67597 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
67598 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
67599 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
67600 
67601 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
67602 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  (13U)
67603 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
67604 
67605 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        (0x4000U)
67606 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       (14U)
67607 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
67608 
67609 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         (0x8000U)
67610 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        (15U)
67611 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
67612 
67613 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     (0xF0000U)
67614 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    (16U)
67615 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
67616 
67617 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67618 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67619 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
67620 
67621 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              (0x200000U)
67622 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             (21U)
67623 #define LCDIF_CTRL1_FIFO_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
67624 
67625 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67626 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67627 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67628 
67629 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        (0x800000U)
67630 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       (23U)
67631 #define LCDIF_CTRL1_INTERLACE_FIELDS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
67632 
67633 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    (0x1000000U)
67634 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
67635 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
67636 
67637 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
67638 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
67639 /*! BM_ERROR_IRQ
67640  *  0b0..No Interrupt Request Pending.
67641  *  0b1..Interrupt Request Pending.
67642  */
67643 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
67644 
67645 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
67646 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
67647 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
67648 
67649 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK           (0x40000000U)
67650 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT          (30U)
67651 #define LCDIF_CTRL1_CS_OUT_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
67652 
67653 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK       (0x80000000U)
67654 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT      (31U)
67655 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
67656 /*! @} */
67657 
67658 /*! @name CTRL1_SET - LCDIF General Control1 Register */
67659 /*! @{ */
67660 
67661 #define LCDIF_CTRL1_SET_RSRVD0_MASK              (0xF8U)
67662 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             (3U)
67663 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
67664 
67665 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
67666 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
67667 /*! VSYNC_EDGE_IRQ
67668  *  0b0..No Interrupt Request Pending.
67669  *  0b1..Interrupt Request Pending.
67670  */
67671 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
67672 
67673 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67674 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67675 /*! CUR_FRAME_DONE_IRQ
67676  *  0b0..No Interrupt Request Pending.
67677  *  0b1..Interrupt Request Pending.
67678  */
67679 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
67680 
67681 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
67682 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
67683 /*! UNDERFLOW_IRQ
67684  *  0b0..No Interrupt Request Pending.
67685  *  0b1..Interrupt Request Pending.
67686  */
67687 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
67688 
67689 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
67690 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
67691 /*! OVERFLOW_IRQ
67692  *  0b0..No Interrupt Request Pending.
67693  *  0b1..Interrupt Request Pending.
67694  */
67695 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
67696 
67697 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67698 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67699 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
67700 
67701 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67702 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67703 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
67704 
67705 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67706 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67707 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
67708 
67709 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67710 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    (15U)
67711 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
67712 
67713 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67714 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
67715 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
67716 
67717 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67718 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67719 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
67720 
67721 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          (0x200000U)
67722 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         (21U)
67723 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
67724 
67725 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67726 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67727 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67728 
67729 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    (0x800000U)
67730 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
67731 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
67732 
67733 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67734 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67735 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
67736 
67737 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
67738 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
67739 /*! BM_ERROR_IRQ
67740  *  0b0..No Interrupt Request Pending.
67741  *  0b1..Interrupt Request Pending.
67742  */
67743 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
67744 
67745 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67746 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
67747 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
67748 
67749 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK       (0x40000000U)
67750 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT      (30U)
67751 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
67752 
67753 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67754 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT  (31U)
67755 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
67756 /*! @} */
67757 
67758 /*! @name CTRL1_CLR - LCDIF General Control1 Register */
67759 /*! @{ */
67760 
67761 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              (0xF8U)
67762 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             (3U)
67763 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
67764 
67765 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
67766 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
67767 /*! VSYNC_EDGE_IRQ
67768  *  0b0..No Interrupt Request Pending.
67769  *  0b1..Interrupt Request Pending.
67770  */
67771 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
67772 
67773 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67774 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67775 /*! CUR_FRAME_DONE_IRQ
67776  *  0b0..No Interrupt Request Pending.
67777  *  0b1..Interrupt Request Pending.
67778  */
67779 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
67780 
67781 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
67782 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
67783 /*! UNDERFLOW_IRQ
67784  *  0b0..No Interrupt Request Pending.
67785  *  0b1..Interrupt Request Pending.
67786  */
67787 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
67788 
67789 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
67790 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
67791 /*! OVERFLOW_IRQ
67792  *  0b0..No Interrupt Request Pending.
67793  *  0b1..Interrupt Request Pending.
67794  */
67795 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
67796 
67797 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67798 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67799 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
67800 
67801 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67802 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67803 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
67804 
67805 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67806 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67807 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
67808 
67809 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67810 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    (15U)
67811 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
67812 
67813 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67814 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
67815 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
67816 
67817 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67818 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67819 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
67820 
67821 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          (0x200000U)
67822 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         (21U)
67823 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
67824 
67825 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67826 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67827 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67828 
67829 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    (0x800000U)
67830 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
67831 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
67832 
67833 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67834 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67835 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
67836 
67837 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
67838 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
67839 /*! BM_ERROR_IRQ
67840  *  0b0..No Interrupt Request Pending.
67841  *  0b1..Interrupt Request Pending.
67842  */
67843 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
67844 
67845 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67846 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
67847 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
67848 
67849 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK       (0x40000000U)
67850 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT      (30U)
67851 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
67852 
67853 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67854 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT  (31U)
67855 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
67856 /*! @} */
67857 
67858 /*! @name CTRL1_TOG - LCDIF General Control1 Register */
67859 /*! @{ */
67860 
67861 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              (0xF8U)
67862 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             (3U)
67863 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
67864 
67865 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
67866 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
67867 /*! VSYNC_EDGE_IRQ
67868  *  0b0..No Interrupt Request Pending.
67869  *  0b1..Interrupt Request Pending.
67870  */
67871 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
67872 
67873 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
67874 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
67875 /*! CUR_FRAME_DONE_IRQ
67876  *  0b0..No Interrupt Request Pending.
67877  *  0b1..Interrupt Request Pending.
67878  */
67879 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
67880 
67881 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
67882 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
67883 /*! UNDERFLOW_IRQ
67884  *  0b0..No Interrupt Request Pending.
67885  *  0b1..Interrupt Request Pending.
67886  */
67887 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
67888 
67889 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
67890 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
67891 /*! OVERFLOW_IRQ
67892  *  0b0..No Interrupt Request Pending.
67893  *  0b1..Interrupt Request Pending.
67894  */
67895 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
67896 
67897 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
67898 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
67899 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
67900 
67901 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
67902 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
67903 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
67904 
67905 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
67906 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
67907 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
67908 
67909 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     (0x8000U)
67910 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    (15U)
67911 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
67912 
67913 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
67914 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
67915 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
67916 
67917 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
67918 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
67919 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
67920 
67921 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          (0x200000U)
67922 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         (21U)
67923 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
67924 
67925 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
67926 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
67927 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
67928 
67929 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    (0x800000U)
67930 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
67931 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
67932 
67933 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
67934 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
67935 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
67936 
67937 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
67938 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
67939 /*! BM_ERROR_IRQ
67940  *  0b0..No Interrupt Request Pending.
67941  *  0b1..Interrupt Request Pending.
67942  */
67943 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
67944 
67945 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
67946 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
67947 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
67948 
67949 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK       (0x40000000U)
67950 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT      (30U)
67951 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
67952 
67953 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK   (0x80000000U)
67954 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT  (31U)
67955 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
67956 /*! @} */
67957 
67958 /*! @name CTRL2 - LCDIF General Control2 Register */
67959 /*! @{ */
67960 
67961 #define LCDIF_CTRL2_RSRVD0_MASK                  (0xFFFU)
67962 #define LCDIF_CTRL2_RSRVD0_SHIFT                 (0U)
67963 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
67964 
67965 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
67966 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
67967 /*! EVEN_LINE_PATTERN
67968  *  0b000..RGB
67969  *  0b001..RBG
67970  *  0b010..GBR
67971  *  0b011..GRB
67972  *  0b100..BRG
67973  *  0b101..BGR
67974  */
67975 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
67976 
67977 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
67978 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
67979 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
67980 
67981 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
67982 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
67983 /*! ODD_LINE_PATTERN
67984  *  0b000..RGB
67985  *  0b001..RBG
67986  *  0b010..GBR
67987  *  0b011..GRB
67988  *  0b100..BRG
67989  *  0b101..BGR
67990  */
67991 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
67992 
67993 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
67994 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
67995 #define LCDIF_CTRL2_RSRVD4(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
67996 
67997 #define LCDIF_CTRL2_BURST_LEN_8_MASK             (0x100000U)
67998 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            (20U)
67999 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
68000 
68001 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
68002 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
68003 /*! OUTSTANDING_REQS
68004  *  0b000..REQ_1
68005  *  0b001..REQ_2
68006  *  0b010..REQ_4
68007  *  0b011..REQ_8
68008  *  0b100..REQ_16
68009  */
68010 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
68011 
68012 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
68013 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
68014 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
68015 /*! @} */
68016 
68017 /*! @name CTRL2_SET - LCDIF General Control2 Register */
68018 /*! @{ */
68019 
68020 #define LCDIF_CTRL2_SET_RSRVD0_MASK              (0xFFFU)
68021 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             (0U)
68022 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
68023 
68024 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
68025 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
68026 /*! EVEN_LINE_PATTERN
68027  *  0b000..RGB
68028  *  0b001..RBG
68029  *  0b010..GBR
68030  *  0b011..GRB
68031  *  0b100..BRG
68032  *  0b101..BGR
68033  */
68034 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
68035 
68036 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
68037 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
68038 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
68039 
68040 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
68041 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
68042 /*! ODD_LINE_PATTERN
68043  *  0b000..RGB
68044  *  0b001..RBG
68045  *  0b010..GBR
68046  *  0b011..GRB
68047  *  0b100..BRG
68048  *  0b101..BGR
68049  */
68050 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
68051 
68052 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
68053 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
68054 #define LCDIF_CTRL2_SET_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
68055 
68056 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         (0x100000U)
68057 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        (20U)
68058 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
68059 
68060 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
68061 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
68062 /*! OUTSTANDING_REQS
68063  *  0b000..REQ_1
68064  *  0b001..REQ_2
68065  *  0b010..REQ_4
68066  *  0b011..REQ_8
68067  *  0b100..REQ_16
68068  */
68069 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
68070 
68071 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
68072 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
68073 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
68074 /*! @} */
68075 
68076 /*! @name CTRL2_CLR - LCDIF General Control2 Register */
68077 /*! @{ */
68078 
68079 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              (0xFFFU)
68080 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             (0U)
68081 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
68082 
68083 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
68084 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
68085 /*! EVEN_LINE_PATTERN
68086  *  0b000..RGB
68087  *  0b001..RBG
68088  *  0b010..GBR
68089  *  0b011..GRB
68090  *  0b100..BRG
68091  *  0b101..BGR
68092  */
68093 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
68094 
68095 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
68096 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
68097 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
68098 
68099 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
68100 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
68101 /*! ODD_LINE_PATTERN
68102  *  0b000..RGB
68103  *  0b001..RBG
68104  *  0b010..GBR
68105  *  0b011..GRB
68106  *  0b100..BRG
68107  *  0b101..BGR
68108  */
68109 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
68110 
68111 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
68112 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
68113 #define LCDIF_CTRL2_CLR_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
68114 
68115 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         (0x100000U)
68116 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        (20U)
68117 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
68118 
68119 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
68120 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
68121 /*! OUTSTANDING_REQS
68122  *  0b000..REQ_1
68123  *  0b001..REQ_2
68124  *  0b010..REQ_4
68125  *  0b011..REQ_8
68126  *  0b100..REQ_16
68127  */
68128 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
68129 
68130 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
68131 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
68132 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
68133 /*! @} */
68134 
68135 /*! @name CTRL2_TOG - LCDIF General Control2 Register */
68136 /*! @{ */
68137 
68138 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              (0xFFFU)
68139 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             (0U)
68140 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
68141 
68142 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
68143 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
68144 /*! EVEN_LINE_PATTERN
68145  *  0b000..RGB
68146  *  0b001..RBG
68147  *  0b010..GBR
68148  *  0b011..GRB
68149  *  0b100..BRG
68150  *  0b101..BGR
68151  */
68152 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
68153 
68154 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
68155 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
68156 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
68157 
68158 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
68159 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
68160 /*! ODD_LINE_PATTERN
68161  *  0b000..RGB
68162  *  0b001..RBG
68163  *  0b010..GBR
68164  *  0b011..GRB
68165  *  0b100..BRG
68166  *  0b101..BGR
68167  */
68168 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
68169 
68170 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
68171 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
68172 #define LCDIF_CTRL2_TOG_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
68173 
68174 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         (0x100000U)
68175 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        (20U)
68176 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
68177 
68178 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
68179 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
68180 /*! OUTSTANDING_REQS
68181  *  0b000..REQ_1
68182  *  0b001..REQ_2
68183  *  0b010..REQ_4
68184  *  0b011..REQ_8
68185  *  0b100..REQ_16
68186  */
68187 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
68188 
68189 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
68190 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
68191 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
68192 /*! @} */
68193 
68194 /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
68195 /*! @{ */
68196 
68197 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        (0xFFFFU)
68198 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       (0U)
68199 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
68200 
68201 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        (0xFFFF0000U)
68202 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       (16U)
68203 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
68204 /*! @} */
68205 
68206 /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
68207 /*! @{ */
68208 
68209 #define LCDIF_CUR_BUF_ADDR_MASK                  (0xFFFFFFFFU)
68210 #define LCDIF_CUR_BUF_ADDR_SHIFT                 (0U)
68211 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
68212 /*! @} */
68213 
68214 /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
68215 /*! @{ */
68216 
68217 #define LCDIF_NEXT_BUF_ADDR_MASK                 (0xFFFFFFFFU)
68218 #define LCDIF_NEXT_BUF_ADDR_SHIFT                (0U)
68219 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
68220 /*! @} */
68221 
68222 /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
68223 /*! @{ */
68224 
68225 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     (0x3FFFFU)
68226 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    (0U)
68227 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
68228 
68229 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        (0x40000U)
68230 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       (18U)
68231 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
68232 
68233 #define LCDIF_VDCTRL0_HALF_LINE_MASK             (0x80000U)
68234 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            (19U)
68235 #define LCDIF_VDCTRL0_HALF_LINE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
68236 
68237 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
68238 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
68239 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
68240 
68241 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     (0x200000U)
68242 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    (21U)
68243 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
68244 
68245 #define LCDIF_VDCTRL0_RSRVD1_MASK                (0xC00000U)
68246 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               (22U)
68247 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
68248 
68249 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            (0x1000000U)
68250 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           (24U)
68251 #define LCDIF_VDCTRL0_ENABLE_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
68252 
68253 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            (0x2000000U)
68254 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           (25U)
68255 #define LCDIF_VDCTRL0_DOTCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
68256 
68257 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             (0x4000000U)
68258 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            (26U)
68259 #define LCDIF_VDCTRL0_HSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
68260 
68261 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             (0x8000000U)
68262 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            (27U)
68263 #define LCDIF_VDCTRL0_VSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
68264 
68265 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        (0x10000000U)
68266 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       (28U)
68267 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
68268 
68269 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             (0x20000000U)
68270 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            (29U)
68271 /*! VSYNC_OEB
68272  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
68273  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
68274  */
68275 #define LCDIF_VDCTRL0_VSYNC_OEB(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
68276 
68277 #define LCDIF_VDCTRL0_RSRVD2_MASK                (0xC0000000U)
68278 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               (30U)
68279 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
68280 /*! @} */
68281 
68282 /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
68283 /*! @{ */
68284 
68285 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
68286 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
68287 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
68288 
68289 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    (0x40000U)
68290 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
68291 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
68292 
68293 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         (0x80000U)
68294 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        (19U)
68295 #define LCDIF_VDCTRL0_SET_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
68296 
68297 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
68298 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
68299 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
68300 
68301 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
68302 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
68303 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
68304 
68305 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            (0xC00000U)
68306 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           (22U)
68307 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
68308 
68309 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        (0x1000000U)
68310 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       (24U)
68311 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
68312 
68313 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        (0x2000000U)
68314 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       (25U)
68315 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
68316 
68317 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         (0x4000000U)
68318 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        (26U)
68319 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
68320 
68321 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         (0x8000000U)
68322 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        (27U)
68323 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
68324 
68325 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    (0x10000000U)
68326 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
68327 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
68328 
68329 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         (0x20000000U)
68330 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        (29U)
68331 /*! VSYNC_OEB
68332  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
68333  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
68334  */
68335 #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
68336 
68337 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            (0xC0000000U)
68338 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           (30U)
68339 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
68340 /*! @} */
68341 
68342 /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
68343 /*! @{ */
68344 
68345 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
68346 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
68347 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
68348 
68349 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    (0x40000U)
68350 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
68351 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
68352 
68353 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         (0x80000U)
68354 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        (19U)
68355 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
68356 
68357 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
68358 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
68359 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
68360 
68361 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
68362 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
68363 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
68364 
68365 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            (0xC00000U)
68366 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           (22U)
68367 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
68368 
68369 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        (0x1000000U)
68370 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       (24U)
68371 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
68372 
68373 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        (0x2000000U)
68374 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       (25U)
68375 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
68376 
68377 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         (0x4000000U)
68378 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        (26U)
68379 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
68380 
68381 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         (0x8000000U)
68382 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        (27U)
68383 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
68384 
68385 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    (0x10000000U)
68386 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
68387 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
68388 
68389 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         (0x20000000U)
68390 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        (29U)
68391 /*! VSYNC_OEB
68392  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
68393  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
68394  */
68395 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
68396 
68397 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            (0xC0000000U)
68398 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           (30U)
68399 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
68400 /*! @} */
68401 
68402 /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
68403 /*! @{ */
68404 
68405 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
68406 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
68407 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
68408 
68409 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    (0x40000U)
68410 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
68411 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
68412 
68413 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         (0x80000U)
68414 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        (19U)
68415 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
68416 
68417 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
68418 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
68419 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
68420 
68421 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
68422 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
68423 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
68424 
68425 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            (0xC00000U)
68426 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           (22U)
68427 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
68428 
68429 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        (0x1000000U)
68430 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       (24U)
68431 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
68432 
68433 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        (0x2000000U)
68434 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       (25U)
68435 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
68436 
68437 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         (0x4000000U)
68438 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        (26U)
68439 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
68440 
68441 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         (0x8000000U)
68442 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        (27U)
68443 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
68444 
68445 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    (0x10000000U)
68446 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
68447 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
68448 
68449 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         (0x20000000U)
68450 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        (29U)
68451 /*! VSYNC_OEB
68452  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
68453  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
68454  */
68455 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
68456 
68457 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            (0xC0000000U)
68458 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           (30U)
68459 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
68460 /*! @} */
68461 
68462 /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
68463 /*! @{ */
68464 
68465 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          (0xFFFFFFFFU)
68466 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         (0U)
68467 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
68468 /*! @} */
68469 
68470 /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
68471 /*! @{ */
68472 
68473 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          (0x3FFFFU)
68474 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         (0U)
68475 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
68476 
68477 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     (0xFFFC0000U)
68478 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    (18U)
68479 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
68480 /*! @} */
68481 
68482 /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
68483 /*! @{ */
68484 
68485 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     (0xFFFFU)
68486 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    (0U)
68487 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
68488 
68489 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
68490 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  (16U)
68491 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
68492 
68493 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            (0x10000000U)
68494 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           (28U)
68495 #define LCDIF_VDCTRL3_VSYNC_ONLY(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
68496 
68497 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      (0x20000000U)
68498 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     (29U)
68499 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
68500 
68501 #define LCDIF_VDCTRL3_RSRVD0_MASK                (0xC0000000U)
68502 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               (30U)
68503 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
68504 /*! @} */
68505 
68506 /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
68507 /*! @{ */
68508 
68509 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
68510 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
68511 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
68512 
68513 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       (0x40000U)
68514 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      (18U)
68515 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
68516 
68517 #define LCDIF_VDCTRL4_RSRVD0_MASK                (0x1FF80000U)
68518 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               (19U)
68519 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
68520 
68521 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        (0xE0000000U)
68522 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       (29U)
68523 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
68524 /*! @} */
68525 
68526 /*! @name BM_ERROR_STAT - Bus Master Error Status Register */
68527 /*! @{ */
68528 
68529 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            (0xFFFFFFFFU)
68530 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           (0U)
68531 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
68532 /*! @} */
68533 
68534 /*! @name CRC_STAT - CRC Status Register */
68535 /*! @{ */
68536 
68537 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            (0xFFFFFFFFU)
68538 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           (0U)
68539 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
68540 /*! @} */
68541 
68542 /*! @name STAT - LCD Interface Status Register */
68543 /*! @{ */
68544 
68545 #define LCDIF_STAT_LFIFO_COUNT_MASK              (0x1FFU)
68546 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             (0U)
68547 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
68548 
68549 #define LCDIF_STAT_RSRVD0_MASK                   (0x1FFFE00U)
68550 #define LCDIF_STAT_RSRVD0_SHIFT                  (9U)
68551 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
68552 
68553 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             (0x4000000U)
68554 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            (26U)
68555 #define LCDIF_STAT_TXFIFO_EMPTY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
68556 
68557 #define LCDIF_STAT_TXFIFO_FULL_MASK              (0x8000000U)
68558 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             (27U)
68559 #define LCDIF_STAT_TXFIFO_FULL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
68560 
68561 #define LCDIF_STAT_LFIFO_EMPTY_MASK              (0x10000000U)
68562 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             (28U)
68563 #define LCDIF_STAT_LFIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
68564 
68565 #define LCDIF_STAT_LFIFO_FULL_MASK               (0x20000000U)
68566 #define LCDIF_STAT_LFIFO_FULL_SHIFT              (29U)
68567 #define LCDIF_STAT_LFIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
68568 
68569 #define LCDIF_STAT_DMA_REQ_MASK                  (0x40000000U)
68570 #define LCDIF_STAT_DMA_REQ_SHIFT                 (30U)
68571 #define LCDIF_STAT_DMA_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
68572 
68573 #define LCDIF_STAT_PRESENT_MASK                  (0x80000000U)
68574 #define LCDIF_STAT_PRESENT_SHIFT                 (31U)
68575 #define LCDIF_STAT_PRESENT(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
68576 /*! @} */
68577 
68578 /*! @name THRES - LCDIF Threshold Register */
68579 /*! @{ */
68580 
68581 #define LCDIF_THRES_RSRVD_MASK                   (0x1FFU)
68582 #define LCDIF_THRES_RSRVD_SHIFT                  (0U)
68583 #define LCDIF_THRES_RSRVD(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)
68584 
68585 #define LCDIF_THRES_RSRVD1_MASK                  (0xFE00U)
68586 #define LCDIF_THRES_RSRVD1_SHIFT                 (9U)
68587 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
68588 
68589 #define LCDIF_THRES_FASTCLOCK_MASK               (0x1FF0000U)
68590 #define LCDIF_THRES_FASTCLOCK_SHIFT              (16U)
68591 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
68592 
68593 #define LCDIF_THRES_RSRVD2_MASK                  (0xFE000000U)
68594 #define LCDIF_THRES_RSRVD2_SHIFT                 (25U)
68595 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
68596 /*! @} */
68597 
68598 /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
68599 /*! @{ */
68600 
68601 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK         (0xFFFU)
68602 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT        (0U)
68603 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
68604 
68605 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK         (0xFFF0000U)
68606 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT        (16U)
68607 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
68608 /*! @} */
68609 
68610 /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
68611 /*! @{ */
68612 
68613 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK     (0xFFFU)
68614 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT    (0U)
68615 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
68616 
68617 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK     (0xFFF0000U)
68618 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT    (16U)
68619 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
68620 /*! @} */
68621 
68622 /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
68623 /*! @{ */
68624 
68625 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK     (0xFFFU)
68626 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT    (0U)
68627 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
68628 
68629 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK     (0xFFF0000U)
68630 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT    (16U)
68631 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
68632 /*! @} */
68633 
68634 /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
68635 /*! @{ */
68636 
68637 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK     (0xFFFU)
68638 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT    (0U)
68639 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
68640 
68641 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK     (0xFFF0000U)
68642 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT    (16U)
68643 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
68644 /*! @} */
68645 
68646 /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
68647 /*! @{ */
68648 
68649 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK  (0xFFFU)
68650 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
68651 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
68652 
68653 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK  (0xFFF0000U)
68654 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
68655 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
68656 /*! @} */
68657 
68658 /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
68659 /*! @{ */
68660 
68661 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
68662 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
68663 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
68664 
68665 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68666 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
68667 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
68668 /*! @} */
68669 
68670 /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
68671 /*! @{ */
68672 
68673 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
68674 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
68675 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
68676 
68677 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68678 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
68679 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
68680 /*! @} */
68681 
68682 /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
68683 /*! @{ */
68684 
68685 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
68686 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
68687 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
68688 
68689 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
68690 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
68691 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
68692 /*! @} */
68693 
68694 /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
68695 /*! @{ */
68696 
68697 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK    (0x1U)
68698 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT   (0U)
68699 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
68700 
68701 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK   (0x2U)
68702 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT  (1U)
68703 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
68704 /*! @} */
68705 
68706 /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
68707 /*! @{ */
68708 
68709 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
68710 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
68711 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
68712 
68713 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
68714 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
68715 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
68716 /*! @} */
68717 
68718 /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
68719 /*! @{ */
68720 
68721 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
68722 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
68723 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
68724 
68725 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
68726 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
68727 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
68728 /*! @} */
68729 
68730 /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
68731 /*! @{ */
68732 
68733 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
68734 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
68735 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
68736 
68737 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
68738 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
68739 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
68740 /*! @} */
68741 
68742 /*! @name PIGEON_0 - Panel Interface Signal Generator Register */
68743 /*! @{ */
68744 
68745 #define LCDIF_PIGEON_0_EN_MASK                   (0x1U)
68746 #define LCDIF_PIGEON_0_EN_SHIFT                  (0U)
68747 #define LCDIF_PIGEON_0_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
68748 
68749 #define LCDIF_PIGEON_0_POL_MASK                  (0x2U)
68750 #define LCDIF_PIGEON_0_POL_SHIFT                 (1U)
68751 /*! POL
68752  *  0b0..Normal Signal (Active high)
68753  *  0b1..Inverted signal (Active low)
68754  */
68755 #define LCDIF_PIGEON_0_POL(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
68756 
68757 #define LCDIF_PIGEON_0_INC_SEL_MASK              (0xCU)
68758 #define LCDIF_PIGEON_0_INC_SEL_SHIFT             (2U)
68759 /*! INC_SEL
68760  *  0b00..pclk
68761  *  0b01..Line start pulse
68762  *  0b10..Frame start pulse
68763  *  0b11..Use another signal as tick event
68764  */
68765 #define LCDIF_PIGEON_0_INC_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
68766 
68767 #define LCDIF_PIGEON_0_OFFSET_MASK               (0xF0U)
68768 #define LCDIF_PIGEON_0_OFFSET_SHIFT              (4U)
68769 #define LCDIF_PIGEON_0_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
68770 
68771 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK         (0xF00U)
68772 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT        (8U)
68773 /*! MASK_CNT_SEL
68774  *  0b0000..pclk counter within one hscan state
68775  *  0b0001..pclk cycle within one hscan state
68776  *  0b0010..line counter within one vscan state
68777  *  0b0011..line cycle within one vscan state
68778  *  0b0100..frame counter
68779  *  0b0101..frame cycle
68780  *  0b0110..horizontal counter (pclk counter within one line )
68781  *  0b0111..vertical counter (line counter within one frame)
68782  */
68783 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
68784 
68785 #define LCDIF_PIGEON_0_MASK_CNT_MASK             (0xFFF000U)
68786 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT            (12U)
68787 #define LCDIF_PIGEON_0_MASK_CNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
68788 
68789 #define LCDIF_PIGEON_0_STATE_MASK_MASK           (0xFF000000U)
68790 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT          (24U)
68791 /*! STATE_MASK
68792  *  0b00000001..FRAME SYNC
68793  *  0b00000010..FRAME BEGIN
68794  *  0b00000100..FRAME DATA
68795  *  0b00001000..FRAME END
68796  *  0b00010000..LINE SYNC
68797  *  0b00100000..LINE BEGIN
68798  *  0b01000000..LINE DATA
68799  *  0b10000000..LINE END
68800  */
68801 #define LCDIF_PIGEON_0_STATE_MASK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
68802 /*! @} */
68803 
68804 /* The count of LCDIF_PIGEON_0 */
68805 #define LCDIF_PIGEON_0_COUNT                     (12U)
68806 
68807 /*! @name PIGEON_1 - Panel Interface Signal Generator Register */
68808 /*! @{ */
68809 
68810 #define LCDIF_PIGEON_1_SET_CNT_MASK              (0xFFFFU)
68811 #define LCDIF_PIGEON_1_SET_CNT_SHIFT             (0U)
68812 /*! SET_CNT
68813  *  0b0000000000000000..Start as active
68814  */
68815 #define LCDIF_PIGEON_1_SET_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
68816 
68817 #define LCDIF_PIGEON_1_CLR_CNT_MASK              (0xFFFF0000U)
68818 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT             (16U)
68819 /*! CLR_CNT
68820  *  0b0000000000000000..Keep active until mask off
68821  */
68822 #define LCDIF_PIGEON_1_CLR_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
68823 /*! @} */
68824 
68825 /* The count of LCDIF_PIGEON_1 */
68826 #define LCDIF_PIGEON_1_COUNT                     (12U)
68827 
68828 /*! @name PIGEON_2 - Panel Interface Signal Generator Register */
68829 /*! @{ */
68830 
68831 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK            (0xFU)
68832 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT           (0U)
68833 /*! SIG_LOGIC
68834  *  0b0000..No logic operation
68835  *  0b0001..sigout = sig_another AND this_sig
68836  *  0b0010..sigout = sig_another OR this_sig
68837  *  0b0011..mask = sig_another AND other_masks
68838  */
68839 #define LCDIF_PIGEON_2_SIG_LOGIC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
68840 
68841 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK          (0x1F0U)
68842 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT         (4U)
68843 /*! SIG_ANOTHER
68844  *  0b00000..Keep active until mask off
68845  */
68846 #define LCDIF_PIGEON_2_SIG_ANOTHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
68847 
68848 #define LCDIF_PIGEON_2_RSVD_MASK                 (0xFFFFFE00U)
68849 #define LCDIF_PIGEON_2_RSVD_SHIFT                (9U)
68850 #define LCDIF_PIGEON_2_RSVD(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
68851 /*! @} */
68852 
68853 /* The count of LCDIF_PIGEON_2 */
68854 #define LCDIF_PIGEON_2_COUNT                     (12U)
68855 
68856 /*! @name LUT_CTRL - Look Up Table Control Register */
68857 /*! @{ */
68858 
68859 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK           (0x1U)
68860 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT          (0U)
68861 #define LCDIF_LUT_CTRL_LUT_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
68862 /*! @} */
68863 
68864 /*! @name LUT0_ADDR - Lookup Table 0 Index Register */
68865 /*! @{ */
68866 
68867 #define LCDIF_LUT0_ADDR_ADDR_MASK                (0xFFU)
68868 #define LCDIF_LUT0_ADDR_ADDR_SHIFT               (0U)
68869 #define LCDIF_LUT0_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
68870 /*! @} */
68871 
68872 /*! @name LUT0_DATA - Lookup Table 0 Data Register */
68873 /*! @{ */
68874 
68875 #define LCDIF_LUT0_DATA_DATA_MASK                (0xFFFFFFFFU)
68876 #define LCDIF_LUT0_DATA_DATA_SHIFT               (0U)
68877 #define LCDIF_LUT0_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
68878 /*! @} */
68879 
68880 /*! @name LUT1_ADDR - Lookup Table 1 Index Register */
68881 /*! @{ */
68882 
68883 #define LCDIF_LUT1_ADDR_ADDR_MASK                (0xFFU)
68884 #define LCDIF_LUT1_ADDR_ADDR_SHIFT               (0U)
68885 #define LCDIF_LUT1_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
68886 /*! @} */
68887 
68888 /*! @name LUT1_DATA - Lookup Table 1 Data Register */
68889 /*! @{ */
68890 
68891 #define LCDIF_LUT1_DATA_DATA_MASK                (0xFFFFFFFFU)
68892 #define LCDIF_LUT1_DATA_DATA_SHIFT               (0U)
68893 #define LCDIF_LUT1_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
68894 /*! @} */
68895 
68896 
68897 /*!
68898  * @}
68899  */ /* end of group LCDIF_Register_Masks */
68900 
68901 
68902 /* LCDIF - Peripheral instance base addresses */
68903 /** Peripheral LCDIF base address */
68904 #define LCDIF_BASE                               (0x40804000u)
68905 /** Peripheral LCDIF base pointer */
68906 #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
68907 /** Array initializer of LCDIF peripheral base addresses */
68908 #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
68909 /** Array initializer of LCDIF peripheral base pointers */
68910 #define LCDIF_BASE_PTRS                          { LCDIF }
68911 /** Interrupt vectors for the LCDIF peripheral type */
68912 #define LCDIF_IRQ0_IRQS                          { eLCDIF_IRQn }
68913 
68914 /*!
68915  * @}
68916  */ /* end of group LCDIF_Peripheral_Access_Layer */
68917 
68918 
68919 /* ----------------------------------------------------------------------------
68920    -- LCDIFV2 Peripheral Access Layer
68921    ---------------------------------------------------------------------------- */
68922 
68923 /*!
68924  * @addtogroup LCDIFV2_Peripheral_Access_Layer LCDIFV2 Peripheral Access Layer
68925  * @{
68926  */
68927 
68928 /** LCDIFV2 - Register Layout Typedef */
68929 typedef struct {
68930   __IO uint32_t CTRL;                              /**< LCDIFv2 display control Register, offset: 0x0 */
68931   __IO uint32_t CTRL_SET;                          /**< LCDIFv2 display control Register, offset: 0x4 */
68932   __IO uint32_t CTRL_CLR;                          /**< LCDIFv2 display control Register, offset: 0x8 */
68933   __IO uint32_t CTRL_TOG;                          /**< LCDIFv2 display control Register, offset: 0xC */
68934   __IO uint32_t DISP_PARA;                         /**< Display Parameter Register, offset: 0x10 */
68935   __IO uint32_t DISP_SIZE;                         /**< Display Size Register, offset: 0x14 */
68936   __IO uint32_t HSYN_PARA;                         /**< Horizontal Sync Parameter Register, offset: 0x18 */
68937   __IO uint32_t VSYN_PARA;                         /**< Vertical Sync Parameter Register, offset: 0x1C */
68938   struct {                                         /* offset: 0x20, array step: 0x10 */
68939     __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10 */
68940     __IO uint32_t INT_ENABLE;                        /**< Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10 */
68941          uint8_t RESERVED_0[8];
68942   } INT[2];
68943   __IO uint32_t PDI_PARA;                          /**< Parallel Data Interface Parameter Register, offset: 0x40 */
68944        uint8_t RESERVED_0[444];
68945   struct {                                         /* offset: 0x200, array step: 0x40 */
68946     __IO uint32_t CTRLDESCL1;                        /**< Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40 */
68947     __IO uint32_t CTRLDESCL2;                        /**< Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40 */
68948     __IO uint32_t CTRLDESCL3;                        /**< Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40 */
68949     __IO uint32_t CTRLDESCL4;                        /**< Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40 */
68950     __IO uint32_t CTRLDESCL5;                        /**< Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40 */
68951     __IO uint32_t CTRLDESCL6;                        /**< Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40 */
68952     __IO uint32_t CSC_COEF0;                         /**< Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances */
68953     __IO uint32_t CSC_COEF1;                         /**< Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances */
68954     __IO uint32_t CSC_COEF2;                         /**< Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances */
68955          uint8_t RESERVED_0[28];
68956   } LAYER[8];
68957   __IO uint32_t CLUT_LOAD;                         /**< LCDIFv2 CLUT load Register, offset: 0x400 */
68958 } LCDIFV2_Type;
68959 
68960 /* ----------------------------------------------------------------------------
68961    -- LCDIFV2 Register Masks
68962    ---------------------------------------------------------------------------- */
68963 
68964 /*!
68965  * @addtogroup LCDIFV2_Register_Masks LCDIFV2 Register Masks
68966  * @{
68967  */
68968 
68969 /*! @name CTRL - LCDIFv2 display control Register */
68970 /*! @{ */
68971 
68972 #define LCDIFV2_CTRL_INV_HS_MASK                 (0x1U)
68973 #define LCDIFV2_CTRL_INV_HS_SHIFT                (0U)
68974 /*! INV_HS - Invert Horizontal synchronization signal
68975  *  0b0..HSYNC signal not inverted (active HIGH)
68976  *  0b1..Invert HSYNC signal (active LOW)
68977  */
68978 #define LCDIFV2_CTRL_INV_HS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
68979 
68980 #define LCDIFV2_CTRL_INV_VS_MASK                 (0x2U)
68981 #define LCDIFV2_CTRL_INV_VS_SHIFT                (1U)
68982 /*! INV_VS - Invert Vertical synchronization signal
68983  *  0b0..VSYNC signal not inverted (active HIGH)
68984  *  0b1..Invert VSYNC signal (active LOW)
68985  */
68986 #define LCDIFV2_CTRL_INV_VS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
68987 
68988 #define LCDIFV2_CTRL_INV_DE_MASK                 (0x4U)
68989 #define LCDIFV2_CTRL_INV_DE_SHIFT                (2U)
68990 /*! INV_DE - Invert Data Enable polarity
68991  *  0b0..Data enable is active high
68992  *  0b1..Data enable is active low
68993  */
68994 #define LCDIFV2_CTRL_INV_DE(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
68995 
68996 #define LCDIFV2_CTRL_INV_PXCK_MASK               (0x8U)
68997 #define LCDIFV2_CTRL_INV_PXCK_SHIFT              (3U)
68998 /*! INV_PXCK - Polarity change of Pixel Clock
68999  *  0b0..Display samples data on the falling edge
69000  *  0b1..Display samples data on the rising edge
69001  */
69002 #define LCDIFV2_CTRL_INV_PXCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
69003 
69004 #define LCDIFV2_CTRL_NEG_MASK                    (0x10U)
69005 #define LCDIFV2_CTRL_NEG_SHIFT                   (4U)
69006 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
69007  *  0b0..Output is to remain same
69008  *  0b1..Output to be negated
69009  */
69010 #define LCDIFV2_CTRL_NEG(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
69011 
69012 #define LCDIFV2_CTRL_SW_RESET_MASK               (0x80000000U)
69013 #define LCDIFV2_CTRL_SW_RESET_SHIFT              (31U)
69014 /*! SW_RESET - Software Reset
69015  *  0b0..No action
69016  *  0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected
69017  */
69018 #define LCDIFV2_CTRL_SW_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)
69019 /*! @} */
69020 
69021 /*! @name CTRL_SET - LCDIFv2 display control Register */
69022 /*! @{ */
69023 
69024 #define LCDIFV2_CTRL_SET_INV_HS_MASK             (0x1U)
69025 #define LCDIFV2_CTRL_SET_INV_HS_SHIFT            (0U)
69026 /*! INV_HS - Invert Horizontal synchronization signal
69027  */
69028 #define LCDIFV2_CTRL_SET_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
69029 
69030 #define LCDIFV2_CTRL_SET_INV_VS_MASK             (0x2U)
69031 #define LCDIFV2_CTRL_SET_INV_VS_SHIFT            (1U)
69032 /*! INV_VS - Invert Vertical synchronization signal
69033  */
69034 #define LCDIFV2_CTRL_SET_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
69035 
69036 #define LCDIFV2_CTRL_SET_INV_DE_MASK             (0x4U)
69037 #define LCDIFV2_CTRL_SET_INV_DE_SHIFT            (2U)
69038 /*! INV_DE - Invert Data Enable polarity
69039  */
69040 #define LCDIFV2_CTRL_SET_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
69041 
69042 #define LCDIFV2_CTRL_SET_INV_PXCK_MASK           (0x8U)
69043 #define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT          (3U)
69044 /*! INV_PXCK - Polarity change of Pixel Clock
69045  */
69046 #define LCDIFV2_CTRL_SET_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
69047 
69048 #define LCDIFV2_CTRL_SET_NEG_MASK                (0x10U)
69049 #define LCDIFV2_CTRL_SET_NEG_SHIFT               (4U)
69050 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
69051  */
69052 #define LCDIFV2_CTRL_SET_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
69053 
69054 #define LCDIFV2_CTRL_SET_SW_RESET_MASK           (0x80000000U)
69055 #define LCDIFV2_CTRL_SET_SW_RESET_SHIFT          (31U)
69056 /*! SW_RESET - Software Reset
69057  */
69058 #define LCDIFV2_CTRL_SET_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)
69059 /*! @} */
69060 
69061 /*! @name CTRL_CLR - LCDIFv2 display control Register */
69062 /*! @{ */
69063 
69064 #define LCDIFV2_CTRL_CLR_INV_HS_MASK             (0x1U)
69065 #define LCDIFV2_CTRL_CLR_INV_HS_SHIFT            (0U)
69066 /*! INV_HS - Invert Horizontal synchronization signal
69067  */
69068 #define LCDIFV2_CTRL_CLR_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
69069 
69070 #define LCDIFV2_CTRL_CLR_INV_VS_MASK             (0x2U)
69071 #define LCDIFV2_CTRL_CLR_INV_VS_SHIFT            (1U)
69072 /*! INV_VS - Invert Vertical synchronization signal
69073  */
69074 #define LCDIFV2_CTRL_CLR_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
69075 
69076 #define LCDIFV2_CTRL_CLR_INV_DE_MASK             (0x4U)
69077 #define LCDIFV2_CTRL_CLR_INV_DE_SHIFT            (2U)
69078 /*! INV_DE - Invert Data Enable polarity
69079  */
69080 #define LCDIFV2_CTRL_CLR_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
69081 
69082 #define LCDIFV2_CTRL_CLR_INV_PXCK_MASK           (0x8U)
69083 #define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT          (3U)
69084 /*! INV_PXCK - Polarity change of Pixel Clock
69085  */
69086 #define LCDIFV2_CTRL_CLR_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
69087 
69088 #define LCDIFV2_CTRL_CLR_NEG_MASK                (0x10U)
69089 #define LCDIFV2_CTRL_CLR_NEG_SHIFT               (4U)
69090 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
69091  */
69092 #define LCDIFV2_CTRL_CLR_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
69093 
69094 #define LCDIFV2_CTRL_CLR_SW_RESET_MASK           (0x80000000U)
69095 #define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT          (31U)
69096 /*! SW_RESET - Software Reset
69097  */
69098 #define LCDIFV2_CTRL_CLR_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)
69099 /*! @} */
69100 
69101 /*! @name CTRL_TOG - LCDIFv2 display control Register */
69102 /*! @{ */
69103 
69104 #define LCDIFV2_CTRL_TOG_INV_HS_MASK             (0x1U)
69105 #define LCDIFV2_CTRL_TOG_INV_HS_SHIFT            (0U)
69106 /*! INV_HS - Invert Horizontal synchronization signal
69107  */
69108 #define LCDIFV2_CTRL_TOG_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
69109 
69110 #define LCDIFV2_CTRL_TOG_INV_VS_MASK             (0x2U)
69111 #define LCDIFV2_CTRL_TOG_INV_VS_SHIFT            (1U)
69112 /*! INV_VS - Invert Vertical synchronization signal
69113  */
69114 #define LCDIFV2_CTRL_TOG_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
69115 
69116 #define LCDIFV2_CTRL_TOG_INV_DE_MASK             (0x4U)
69117 #define LCDIFV2_CTRL_TOG_INV_DE_SHIFT            (2U)
69118 /*! INV_DE - Invert Data Enable polarity
69119  */
69120 #define LCDIFV2_CTRL_TOG_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
69121 
69122 #define LCDIFV2_CTRL_TOG_INV_PXCK_MASK           (0x8U)
69123 #define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT          (3U)
69124 /*! INV_PXCK - Polarity change of Pixel Clock
69125  */
69126 #define LCDIFV2_CTRL_TOG_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
69127 
69128 #define LCDIFV2_CTRL_TOG_NEG_MASK                (0x10U)
69129 #define LCDIFV2_CTRL_TOG_NEG_SHIFT               (4U)
69130 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
69131  */
69132 #define LCDIFV2_CTRL_TOG_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
69133 
69134 #define LCDIFV2_CTRL_TOG_SW_RESET_MASK           (0x80000000U)
69135 #define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT          (31U)
69136 /*! SW_RESET - Software Reset
69137  */
69138 #define LCDIFV2_CTRL_TOG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)
69139 /*! @} */
69140 
69141 /*! @name DISP_PARA - Display Parameter Register */
69142 /*! @{ */
69143 
69144 #define LCDIFV2_DISP_PARA_BGND_B_MASK            (0xFFU)
69145 #define LCDIFV2_DISP_PARA_BGND_B_SHIFT           (0U)
69146 /*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active
69147  */
69148 #define LCDIFV2_DISP_PARA_BGND_B(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
69149 
69150 #define LCDIFV2_DISP_PARA_BGND_G_MASK            (0xFF00U)
69151 #define LCDIFV2_DISP_PARA_BGND_G_SHIFT           (8U)
69152 /*! BGND_G - Green component of the default color displayed in the sectors where no layer is active
69153  */
69154 #define LCDIFV2_DISP_PARA_BGND_G(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
69155 
69156 #define LCDIFV2_DISP_PARA_BGND_R_MASK            (0xFF0000U)
69157 #define LCDIFV2_DISP_PARA_BGND_R_SHIFT           (16U)
69158 /*! BGND_R - Red component of the default color displayed in the sectors where no layer is active
69159  */
69160 #define LCDIFV2_DISP_PARA_BGND_R(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
69161 
69162 #define LCDIFV2_DISP_PARA_DISP_MODE_MASK         (0x3000000U)
69163 #define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT        (24U)
69164 /*! DISP_MODE - LCDIFv2 operating mode
69165  *  0b00..Normal mode. Panel content controlled by layer configuration
69166  *  0b01..Test Mode1(BGND Color Display)
69167  *  0b10..Test Mode2(Column Color Bar)
69168  *  0b11..Test Mode3(Row Color Bar)
69169  */
69170 #define LCDIFV2_DISP_PARA_DISP_MODE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
69171 
69172 #define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK      (0x1C000000U)
69173 #define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT     (26U)
69174 /*! LINE_PATTERN - LCDIFv2 line output order
69175  *  0b000..RGB
69176  *  0b001..RBG
69177  *  0b010..GBR
69178  *  0b011..GRB
69179  *  0b100..BRG
69180  *  0b101..BGR
69181  */
69182 #define LCDIFV2_DISP_PARA_LINE_PATTERN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
69183 
69184 #define LCDIFV2_DISP_PARA_DISP_ON_MASK           (0x80000000U)
69185 #define LCDIFV2_DISP_PARA_DISP_ON_SHIFT          (31U)
69186 /*! DISP_ON - Display panel On/Off mode
69187  *  0b0..Display Off
69188  *  0b1..Display On
69189  */
69190 #define LCDIFV2_DISP_PARA_DISP_ON(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)
69191 /*! @} */
69192 
69193 /*! @name DISP_SIZE - Display Size Register */
69194 /*! @{ */
69195 
69196 #define LCDIFV2_DISP_SIZE_DELTA_X_MASK           (0xFFFU)
69197 #define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT          (0U)
69198 /*! DELTA_X - Sets the display size horizontal resolution in pixels
69199  */
69200 #define LCDIFV2_DISP_SIZE_DELTA_X(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
69201 
69202 #define LCDIFV2_DISP_SIZE_DELTA_Y_MASK           (0xFFF0000U)
69203 #define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT          (16U)
69204 /*! DELTA_Y - Sets the display size vertical resolution in pixels
69205  */
69206 #define LCDIFV2_DISP_SIZE_DELTA_Y(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)
69207 /*! @} */
69208 
69209 /*! @name HSYN_PARA - Horizontal Sync Parameter Register */
69210 /*! @{ */
69211 
69212 #define LCDIFV2_HSYN_PARA_FP_H_MASK              (0x1FFU)
69213 #define LCDIFV2_HSYN_PARA_FP_H_SHIFT             (0U)
69214 /*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
69215  */
69216 #define LCDIFV2_HSYN_PARA_FP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
69217 
69218 #define LCDIFV2_HSYN_PARA_PW_H_MASK              (0xFF800U)
69219 #define LCDIFV2_HSYN_PARA_PW_H_SHIFT             (11U)
69220 /*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
69221  */
69222 #define LCDIFV2_HSYN_PARA_PW_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
69223 
69224 #define LCDIFV2_HSYN_PARA_BP_H_MASK              (0x7FC00000U)
69225 #define LCDIFV2_HSYN_PARA_BP_H_SHIFT             (22U)
69226 /*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
69227  */
69228 #define LCDIFV2_HSYN_PARA_BP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)
69229 /*! @} */
69230 
69231 /*! @name VSYN_PARA - Vertical Sync Parameter Register */
69232 /*! @{ */
69233 
69234 #define LCDIFV2_VSYN_PARA_FP_V_MASK              (0x1FFU)
69235 #define LCDIFV2_VSYN_PARA_FP_V_SHIFT             (0U)
69236 /*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
69237  */
69238 #define LCDIFV2_VSYN_PARA_FP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
69239 
69240 #define LCDIFV2_VSYN_PARA_PW_V_MASK              (0xFF800U)
69241 #define LCDIFV2_VSYN_PARA_PW_V_SHIFT             (11U)
69242 /*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
69243  */
69244 #define LCDIFV2_VSYN_PARA_PW_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
69245 
69246 #define LCDIFV2_VSYN_PARA_BP_V_MASK              (0x7FC00000U)
69247 #define LCDIFV2_VSYN_PARA_BP_V_SHIFT             (22U)
69248 /*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
69249  */
69250 #define LCDIFV2_VSYN_PARA_BP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)
69251 /*! @} */
69252 
69253 /*! @name INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 */
69254 /*! @{ */
69255 
69256 #define LCDIFV2_INT_STATUS_VSYNC_MASK            (0x1U)
69257 #define LCDIFV2_INT_STATUS_VSYNC_SHIFT           (0U)
69258 /*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
69259  *  0b0..VSYNC has not started
69260  *  0b1..VSYNC has started
69261  */
69262 #define LCDIFV2_INT_STATUS_VSYNC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
69263 
69264 #define LCDIFV2_INT_STATUS_UNDERRUN_MASK         (0x2U)
69265 #define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT        (1U)
69266 /*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition
69267  *  0b0..Output buffer not underrun
69268  *  0b1..Output buffer underrun
69269  */
69270 #define LCDIFV2_INT_STATUS_UNDERRUN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
69271 
69272 #define LCDIFV2_INT_STATUS_VS_BLANK_MASK         (0x4U)
69273 #define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT        (2U)
69274 /*! VS_BLANK - Interrupt flag to indicate vertical blanking period
69275  *  0b0..Vertical blanking period has not started
69276  *  0b1..Vertical blanking period has started
69277  */
69278 #define LCDIFV2_INT_STATUS_VS_BLANK(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
69279 
69280 #define LCDIFV2_INT_STATUS_DMA_ERR_MASK          (0xFF00U)
69281 #define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT         (8U)
69282 /*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
69283  */
69284 #define LCDIFV2_INT_STATUS_DMA_ERR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
69285 
69286 #define LCDIFV2_INT_STATUS_DMA_DONE_MASK         (0xFF0000U)
69287 #define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT        (16U)
69288 /*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
69289  */
69290 #define LCDIFV2_INT_STATUS_DMA_DONE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
69291 
69292 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK       (0xFF000000U)
69293 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT      (24U)
69294 /*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed
69295  */
69296 #define LCDIFV2_INT_STATUS_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)
69297 /*! @} */
69298 
69299 /* The count of LCDIFV2_INT_STATUS */
69300 #define LCDIFV2_INT_STATUS_COUNT                 (2U)
69301 
69302 /*! @name INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 */
69303 /*! @{ */
69304 
69305 #define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK         (0x1U)
69306 #define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT        (0U)
69307 /*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
69308  *  0b0..VSYNC interrupt disable
69309  *  0b1..VSYNC interrupt enable
69310  */
69311 #define LCDIFV2_INT_ENABLE_VSYNC_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
69312 
69313 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK      (0x2U)
69314 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT     (1U)
69315 /*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition
69316  *  0b0..Output buffer underrun disable
69317  *  0b1..Output buffer underrun enable
69318  */
69319 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
69320 
69321 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK      (0x4U)
69322 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT     (2U)
69323 /*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period
69324  *  0b0..Vertical blanking start interrupt disable
69325  *  0b1..Vertical blanking start interrupt enable
69326  */
69327 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
69328 
69329 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK       (0xFF00U)
69330 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT      (8U)
69331 /*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
69332  */
69333 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
69334 
69335 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK      (0xFF0000U)
69336 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT     (16U)
69337 /*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
69338  */
69339 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
69340 
69341 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK    (0xFF000000U)
69342 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
69343 /*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed
69344  */
69345 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)
69346 /*! @} */
69347 
69348 /* The count of LCDIFV2_INT_ENABLE */
69349 #define LCDIFV2_INT_ENABLE_COUNT                 (2U)
69350 
69351 /*! @name PDI_PARA - Parallel Data Interface Parameter Register */
69352 /*! @{ */
69353 
69354 #define LCDIFV2_PDI_PARA_INV_PDI_HS_MASK         (0x1U)
69355 #define LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT        (0U)
69356 /*! INV_PDI_HS - Polarity of PDI input HSYNC
69357  *  0b0..HSYNC is active HIGH
69358  *  0b1..HSYNC is active LOW
69359  */
69360 #define LCDIFV2_PDI_PARA_INV_PDI_HS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
69361 
69362 #define LCDIFV2_PDI_PARA_INV_PDI_VS_MASK         (0x2U)
69363 #define LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT        (1U)
69364 /*! INV_PDI_VS - Polarity of PDI input VSYNC
69365  *  0b0..VSYNC is active HIGH
69366  *  0b1..VSYNC is active LOW
69367  */
69368 #define LCDIFV2_PDI_PARA_INV_PDI_VS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
69369 
69370 #define LCDIFV2_PDI_PARA_INV_PDI_DE_MASK         (0x4U)
69371 #define LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT        (2U)
69372 /*! INV_PDI_DE - Polarity of PDI input Data Enable
69373  *  0b0..Data enable is active HIGH
69374  *  0b1..Data enable is active LOW
69375  */
69376 #define LCDIFV2_PDI_PARA_INV_PDI_DE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
69377 
69378 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK       (0x8U)
69379 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT      (3U)
69380 /*! INV_PDI_PXCK - Polarity of PDI input Pixel Clock
69381  *  0b0..Samples data on the falling edge
69382  *  0b1..Samples data on the rising edge
69383  */
69384 #define LCDIFV2_PDI_PARA_INV_PDI_PXCK(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
69385 
69386 #define LCDIFV2_PDI_PARA_MODE_MASK               (0xF0U)
69387 #define LCDIFV2_PDI_PARA_MODE_SHIFT              (4U)
69388 /*! MODE - The PDI mode for input data format
69389  *  0b0000..32 bpp (ARGB8888)
69390  *  0b0001..24 bpp (RGB888)
69391  *  0b0010..24 bpp (RGB666)
69392  *  0b0011..16 bpp (RGB565)
69393  *  0b0100..16 bpp (RGB444)
69394  *  0b0101..16 bpp (RGB555)
69395  *  0b0110..16 bpp (YCbCr422)
69396  */
69397 #define LCDIFV2_PDI_PARA_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
69398 
69399 #define LCDIFV2_PDI_PARA_PDI_SEL_MASK            (0x40000000U)
69400 #define LCDIFV2_PDI_PARA_PDI_SEL_SHIFT           (30U)
69401 /*! PDI_SEL - PDI selected on LCDIFv2 plane number
69402  *  0b0..PDI selected on LCDIFv2 plane 0
69403  *  0b1..PDI selected on LCDIFv2 plane 1
69404  */
69405 #define LCDIFV2_PDI_PARA_PDI_SEL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
69406 
69407 #define LCDIFV2_PDI_PARA_PDI_EN_MASK             (0x80000000U)
69408 #define LCDIFV2_PDI_PARA_PDI_EN_SHIFT            (31U)
69409 /*! PDI_EN - Enable PDI input data to LCDIFv2 display
69410  *  0b0..Disable PDI input data
69411  *  0b1..Enable PDI input data
69412  */
69413 #define LCDIFV2_PDI_PARA_PDI_EN(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)
69414 /*! @} */
69415 
69416 /*! @name CTRLDESCL1 - Control Descriptor Layer 1 Register */
69417 /*! @{ */
69418 
69419 #define LCDIFV2_CTRLDESCL1_WIDTH_MASK            (0xFFFU)
69420 #define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT           (0U)
69421 /*! WIDTH - Width of the layer in pixels
69422  */
69423 #define LCDIFV2_CTRLDESCL1_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
69424 
69425 #define LCDIFV2_CTRLDESCL1_HEIGHT_MASK           (0xFFF0000U)
69426 #define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT          (16U)
69427 /*! HEIGHT - Height of the layer in pixels
69428  */
69429 #define LCDIFV2_CTRLDESCL1_HEIGHT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)
69430 /*! @} */
69431 
69432 /* The count of LCDIFV2_CTRLDESCL1 */
69433 #define LCDIFV2_CTRLDESCL1_COUNT                 (8U)
69434 
69435 /*! @name CTRLDESCL2 - Control Descriptor Layer 2 Register */
69436 /*! @{ */
69437 
69438 #define LCDIFV2_CTRLDESCL2_POSX_MASK             (0xFFFU)
69439 #define LCDIFV2_CTRLDESCL2_POSX_SHIFT            (0U)
69440 /*! POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column
69441  *    of the panel, only positive values are to the right the left-hand column of the panel
69442  */
69443 #define LCDIFV2_CTRLDESCL2_POSX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
69444 
69445 #define LCDIFV2_CTRLDESCL2_POSY_MASK             (0xFFF0000U)
69446 #define LCDIFV2_CTRLDESCL2_POSY_SHIFT            (16U)
69447 /*! POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only
69448  *    positive values are below the top row of the panel
69449  */
69450 #define LCDIFV2_CTRLDESCL2_POSY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)
69451 /*! @} */
69452 
69453 /* The count of LCDIFV2_CTRLDESCL2 */
69454 #define LCDIFV2_CTRLDESCL2_COUNT                 (8U)
69455 
69456 /*! @name CTRLDESCL3 - Control Descriptor Layer 3 Register */
69457 /*! @{ */
69458 
69459 #define LCDIFV2_CTRLDESCL3_PITCH_MASK            (0xFFFFU)
69460 #define LCDIFV2_CTRLDESCL3_PITCH_SHIFT           (0U)
69461 /*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
69462  *    is supported, but SW should align to 64B boundry
69463  */
69464 #define LCDIFV2_CTRLDESCL3_PITCH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)
69465 /*! @} */
69466 
69467 /* The count of LCDIFV2_CTRLDESCL3 */
69468 #define LCDIFV2_CTRLDESCL3_COUNT                 (8U)
69469 
69470 /*! @name CTRLDESCL4 - Control Descriptor Layer 4 Register */
69471 /*! @{ */
69472 
69473 #define LCDIFV2_CTRLDESCL4_ADDR_MASK             (0xFFFFFFFFU)
69474 #define LCDIFV2_CTRLDESCL4_ADDR_SHIFT            (0U)
69475 /*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned
69476  */
69477 #define LCDIFV2_CTRLDESCL4_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)
69478 /*! @} */
69479 
69480 /* The count of LCDIFV2_CTRLDESCL4 */
69481 #define LCDIFV2_CTRLDESCL4_COUNT                 (8U)
69482 
69483 /*! @name CTRLDESCL5 - Control Descriptor Layer 5 Register */
69484 /*! @{ */
69485 
69486 #define LCDIFV2_CTRLDESCL5_AB_MODE_MASK          (0x3U)
69487 #define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT         (0U)
69488 /*! AB_MODE - Alpha Blending Mode
69489  *  0b00..No alpha Blending (The SAFETY_EN bit need set to 1)
69490  *  0b01..Blend with global ALPHA
69491  *  0b10..Blend with embedded ALPHA
69492  *  0b11..Blend with PoterDuff enable
69493  */
69494 #define LCDIFV2_CTRLDESCL5_AB_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
69495 
69496 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
69497 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT  (4U)
69498 /*! PD_FACTOR_MODE - PoterDuff factor mode
69499  *  0b00..Using 1
69500  *  0b01..Using 0
69501  *  0b10..Using straight alpha
69502  *  0b11..Using inverse alpha
69503  */
69504 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
69505 
69506 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U)
69507 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U)
69508 /*! PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode
69509  *  0b00..Using global alpha
69510  *  0b01..Using local alpha
69511  *  0b10..Using scaled alpha
69512  *  0b11..Using scaled alpha
69513  */
69514 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
69515 
69516 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK    (0x100U)
69517 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
69518 /*! PD_ALPHA_MODE - PoterDuff alpha mode
69519  *  0b0..Straight mode for Porter Duff alpha
69520  *  0b1..Inversed mode for Porter Duff alpha
69521  */
69522 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
69523 
69524 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK    (0x200U)
69525 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
69526 /*! PD_COLOR_MODE - PoterDuff alpha mode
69527  *  0b0..Straight mode for Porter Duff color
69528  *  0b1..Inversed mode for Porter Duff color
69529  */
69530 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
69531 
69532 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK       (0xC000U)
69533 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT      (14U)
69534 /*! YUV_FORMAT - The YUV422 input format selection
69535  *  0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2
69536  *  0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2
69537  *  0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1
69538  *  0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1
69539  */
69540 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
69541 
69542 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK     (0xFF0000U)
69543 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT    (16U)
69544 /*! GLOBAL_ALPHA - Global Alpha
69545  */
69546 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)       (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
69547 
69548 #define LCDIFV2_CTRLDESCL5_BPP_MASK              (0xF000000U)
69549 #define LCDIFV2_CTRLDESCL5_BPP_SHIFT             (24U)
69550 /*! BPP - Layer encoding format (bit per pixel)
69551  *  0b0000..1 bpp
69552  *  0b0001..2 bpp
69553  *  0b0010..4 bpp
69554  *  0b0011..8 bpp
69555  *  0b0100..16 bpp (RGB565)
69556  *  0b0101..16 bpp (ARGB1555)
69557  *  0b0110..16 bpp (ARGB4444)
69558  *  0b0111..YCbCr422 (Only layer 0/1 can support this format)
69559  *  0b1000..24 bpp (RGB888)
69560  *  0b1001..32 bpp (ARGB8888)
69561  *  0b1010..32 bpp (ABGR8888)
69562  */
69563 #define LCDIFV2_CTRLDESCL5_BPP(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
69564 
69565 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK        (0x10000000U)
69566 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT       (28U)
69567 /*! SAFETY_EN - Safety Mode Enable Bit
69568  *  0b0..Safety Mode is disabled
69569  *  0b1..Safety Mode is enabled for this layer
69570  */
69571 #define LCDIFV2_CTRLDESCL5_SAFETY_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
69572 
69573 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
69574 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT  (30U)
69575 /*! SHADOW_LOAD_EN - Shadow Load Enable
69576  */
69577 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
69578 
69579 #define LCDIFV2_CTRLDESCL5_EN_MASK               (0x80000000U)
69580 #define LCDIFV2_CTRLDESCL5_EN_SHIFT              (31U)
69581 /*! EN - Enable the layer for DMA
69582  *  0b0..OFF
69583  *  0b1..ON
69584  */
69585 #define LCDIFV2_CTRLDESCL5_EN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)
69586 /*! @} */
69587 
69588 /* The count of LCDIFV2_CTRLDESCL5 */
69589 #define LCDIFV2_CTRLDESCL5_COUNT                 (8U)
69590 
69591 /*! @name CTRLDESCL6 - Control Descriptor Layer 6 Register */
69592 /*! @{ */
69593 
69594 #define LCDIFV2_CTRLDESCL6_BCLR_B_MASK           (0xFFU)
69595 #define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT          (0U)
69596 /*! BCLR_B - Background B component value
69597  */
69598 #define LCDIFV2_CTRLDESCL6_BCLR_B(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
69599 
69600 #define LCDIFV2_CTRLDESCL6_BCLR_G_MASK           (0xFF00U)
69601 #define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT          (8U)
69602 /*! BCLR_G - Background G component value
69603  */
69604 #define LCDIFV2_CTRLDESCL6_BCLR_G(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
69605 
69606 #define LCDIFV2_CTRLDESCL6_BCLR_R_MASK           (0xFF0000U)
69607 #define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT          (16U)
69608 /*! BCLR_R - Background R component value
69609  */
69610 #define LCDIFV2_CTRLDESCL6_BCLR_R(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)
69611 /*! @} */
69612 
69613 /* The count of LCDIFV2_CTRLDESCL6 */
69614 #define LCDIFV2_CTRLDESCL6_COUNT                 (8U)
69615 
69616 /*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */
69617 /*! @{ */
69618 
69619 #define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK          (0x1FFU)
69620 #define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT         (0U)
69621 /*! Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically
69622  *    0 and for YCbCr, this is typically -16 (0x1F0)
69623  */
69624 #define LCDIFV2_CSC_COEF0_Y_OFFSET(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
69625 
69626 #define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK         (0x3FE00U)
69627 #define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT        (9U)
69628 /*! UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to
69629  *    RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to
69630  *    0.5 range)
69631  */
69632 #define LCDIFV2_CSC_COEF0_UV_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
69633 
69634 #define LCDIFV2_CSC_COEF0_C0_MASK                (0x1FFC0000U)
69635 #define LCDIFV2_CSC_COEF0_C0_SHIFT               (18U)
69636 /*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)
69637  */
69638 #define LCDIFV2_CSC_COEF0_C0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
69639 
69640 #define LCDIFV2_CSC_COEF0_ENABLE_MASK            (0x40000000U)
69641 #define LCDIFV2_CSC_COEF0_ENABLE_SHIFT           (30U)
69642 /*! ENABLE - Enable the CSC unit in the LCDIFv2 plane data path
69643  *  0b0..The CSC is bypassed and the input pixels are RGB data already
69644  *  0b1..The CSC is enabled and the pixels will be converted to RGB data
69645  */
69646 #define LCDIFV2_CSC_COEF0_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
69647 
69648 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK        (0x80000000U)
69649 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT       (31U)
69650 /*! YCBCR_MODE - This bit changes the behavior when performing U/V converting
69651  *  0b0..Converting YUV to RGB data
69652  *  0b1..Converting YCbCr to RGB data
69653  */
69654 #define LCDIFV2_CSC_COEF0_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)
69655 /*! @} */
69656 
69657 /* The count of LCDIFV2_CSC_COEF0 */
69658 #define LCDIFV2_CSC_COEF0_COUNT                  (8U)
69659 
69660 /*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */
69661 /*! @{ */
69662 
69663 #define LCDIFV2_CSC_COEF1_C4_MASK                (0x7FFU)
69664 #define LCDIFV2_CSC_COEF1_C4_SHIFT               (0U)
69665 /*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)
69666  */
69667 #define LCDIFV2_CSC_COEF1_C4(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
69668 
69669 #define LCDIFV2_CSC_COEF1_C1_MASK                (0x7FF0000U)
69670 #define LCDIFV2_CSC_COEF1_C1_SHIFT               (16U)
69671 /*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)
69672  */
69673 #define LCDIFV2_CSC_COEF1_C1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)
69674 /*! @} */
69675 
69676 /* The count of LCDIFV2_CSC_COEF1 */
69677 #define LCDIFV2_CSC_COEF1_COUNT                  (8U)
69678 
69679 /*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */
69680 /*! @{ */
69681 
69682 #define LCDIFV2_CSC_COEF2_C3_MASK                (0x7FFU)
69683 #define LCDIFV2_CSC_COEF2_C3_SHIFT               (0U)
69684 /*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)
69685  */
69686 #define LCDIFV2_CSC_COEF2_C3(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
69687 
69688 #define LCDIFV2_CSC_COEF2_C2_MASK                (0x7FF0000U)
69689 #define LCDIFV2_CSC_COEF2_C2_SHIFT               (16U)
69690 /*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)
69691  */
69692 #define LCDIFV2_CSC_COEF2_C2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)
69693 /*! @} */
69694 
69695 /* The count of LCDIFV2_CSC_COEF2 */
69696 #define LCDIFV2_CSC_COEF2_COUNT                  (8U)
69697 
69698 /*! @name CLUT_LOAD - LCDIFv2 CLUT load Register */
69699 /*! @{ */
69700 
69701 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK    (0x1U)
69702 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
69703 /*! CLUT_UPDATE_EN - CLUT Update Enable
69704  */
69705 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
69706 
69707 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK      (0x70U)
69708 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT     (4U)
69709 /*! SEL_CLUT_NUM - Selected CLUT Number
69710  */
69711 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)
69712 /*! @} */
69713 
69714 
69715 /*!
69716  * @}
69717  */ /* end of group LCDIFV2_Register_Masks */
69718 
69719 
69720 /* LCDIFV2 - Peripheral instance base addresses */
69721 /** Peripheral LCDIFV2 base address */
69722 #define LCDIFV2_BASE                             (0x40808000u)
69723 /** Peripheral LCDIFV2 base pointer */
69724 #define LCDIFV2                                  ((LCDIFV2_Type *)LCDIFV2_BASE)
69725 /** Array initializer of LCDIFV2 peripheral base addresses */
69726 #define LCDIFV2_BASE_ADDRS                       { LCDIFV2_BASE }
69727 /** Array initializer of LCDIFV2 peripheral base pointers */
69728 #define LCDIFV2_BASE_PTRS                        { LCDIFV2 }
69729 
69730 /*!
69731  * @}
69732  */ /* end of group LCDIFV2_Peripheral_Access_Layer */
69733 
69734 
69735 /* ----------------------------------------------------------------------------
69736    -- LPI2C Peripheral Access Layer
69737    ---------------------------------------------------------------------------- */
69738 
69739 /*!
69740  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
69741  * @{
69742  */
69743 
69744 /** LPI2C - Register Layout Typedef */
69745 typedef struct {
69746   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
69747   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
69748        uint8_t RESERVED_0[8];
69749   __IO uint32_t MCR;                               /**< Master Control, offset: 0x10 */
69750   __IO uint32_t MSR;                               /**< Master Status, offset: 0x14 */
69751   __IO uint32_t MIER;                              /**< Master Interrupt Enable, offset: 0x18 */
69752   __IO uint32_t MDER;                              /**< Master DMA Enable, offset: 0x1C */
69753   __IO uint32_t MCFGR0;                            /**< Master Configuration 0, offset: 0x20 */
69754   __IO uint32_t MCFGR1;                            /**< Master Configuration 1, offset: 0x24 */
69755   __IO uint32_t MCFGR2;                            /**< Master Configuration 2, offset: 0x28 */
69756   __IO uint32_t MCFGR3;                            /**< Master Configuration 3, offset: 0x2C */
69757        uint8_t RESERVED_1[16];
69758   __IO uint32_t MDMR;                              /**< Master Data Match, offset: 0x40 */
69759        uint8_t RESERVED_2[4];
69760   __IO uint32_t MCCR0;                             /**< Master Clock Configuration 0, offset: 0x48 */
69761        uint8_t RESERVED_3[4];
69762   __IO uint32_t MCCR1;                             /**< Master Clock Configuration 1, offset: 0x50 */
69763        uint8_t RESERVED_4[4];
69764   __IO uint32_t MFCR;                              /**< Master FIFO Control, offset: 0x58 */
69765   __I  uint32_t MFSR;                              /**< Master FIFO Status, offset: 0x5C */
69766   __O  uint32_t MTDR;                              /**< Master Transmit Data, offset: 0x60 */
69767        uint8_t RESERVED_5[12];
69768   __I  uint32_t MRDR;                              /**< Master Receive Data, offset: 0x70 */
69769        uint8_t RESERVED_6[156];
69770   __IO uint32_t SCR;                               /**< Slave Control, offset: 0x110 */
69771   __IO uint32_t SSR;                               /**< Slave Status, offset: 0x114 */
69772   __IO uint32_t SIER;                              /**< Slave Interrupt Enable, offset: 0x118 */
69773   __IO uint32_t SDER;                              /**< Slave DMA Enable, offset: 0x11C */
69774        uint8_t RESERVED_7[4];
69775   __IO uint32_t SCFGR1;                            /**< Slave Configuration 1, offset: 0x124 */
69776   __IO uint32_t SCFGR2;                            /**< Slave Configuration 2, offset: 0x128 */
69777        uint8_t RESERVED_8[20];
69778   __IO uint32_t SAMR;                              /**< Slave Address Match, offset: 0x140 */
69779        uint8_t RESERVED_9[12];
69780   __I  uint32_t SASR;                              /**< Slave Address Status, offset: 0x150 */
69781   __IO uint32_t STAR;                              /**< Slave Transmit ACK, offset: 0x154 */
69782        uint8_t RESERVED_10[8];
69783   __O  uint32_t STDR;                              /**< Slave Transmit Data, offset: 0x160 */
69784        uint8_t RESERVED_11[12];
69785   __I  uint32_t SRDR;                              /**< Slave Receive Data, offset: 0x170 */
69786 } LPI2C_Type;
69787 
69788 /* ----------------------------------------------------------------------------
69789    -- LPI2C Register Masks
69790    ---------------------------------------------------------------------------- */
69791 
69792 /*!
69793  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
69794  * @{
69795  */
69796 
69797 /*! @name VERID - Version ID */
69798 /*! @{ */
69799 
69800 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
69801 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
69802 /*! FEATURE - Feature Specification Number
69803  *  0b0000000000000010..Master only, with standard feature set
69804  *  0b0000000000000011..Master and slave, with standard feature set
69805  */
69806 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
69807 
69808 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
69809 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
69810 /*! MINOR - Minor Version Number
69811  */
69812 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
69813 
69814 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
69815 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
69816 /*! MAJOR - Major Version Number
69817  */
69818 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
69819 /*! @} */
69820 
69821 /*! @name PARAM - Parameter */
69822 /*! @{ */
69823 
69824 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
69825 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
69826 /*! MTXFIFO - Master Transmit FIFO Size
69827  */
69828 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
69829 
69830 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
69831 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
69832 /*! MRXFIFO - Master Receive FIFO Size
69833  */
69834 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
69835 /*! @} */
69836 
69837 /*! @name MCR - Master Control */
69838 /*! @{ */
69839 
69840 #define LPI2C_MCR_MEN_MASK                       (0x1U)
69841 #define LPI2C_MCR_MEN_SHIFT                      (0U)
69842 /*! MEN - Master Enable
69843  *  0b0..Master logic is disabled
69844  *  0b1..Master logic is enabled
69845  */
69846 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
69847 
69848 #define LPI2C_MCR_RST_MASK                       (0x2U)
69849 #define LPI2C_MCR_RST_SHIFT                      (1U)
69850 /*! RST - Software Reset
69851  *  0b0..Master logic is not reset
69852  *  0b1..Master logic is reset
69853  */
69854 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
69855 
69856 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
69857 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
69858 /*! DOZEN - Doze mode enable
69859  *  0b0..Master is enabled in Doze mode
69860  *  0b1..Master is disabled in Doze mode
69861  */
69862 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
69863 
69864 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
69865 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
69866 /*! DBGEN - Debug Enable
69867  *  0b0..Master is disabled in debug mode
69868  *  0b1..Master is enabled in debug mode
69869  */
69870 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
69871 
69872 #define LPI2C_MCR_RTF_MASK                       (0x100U)
69873 #define LPI2C_MCR_RTF_SHIFT                      (8U)
69874 /*! RTF - Reset Transmit FIFO
69875  *  0b0..No effect
69876  *  0b1..Transmit FIFO is reset
69877  */
69878 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
69879 
69880 #define LPI2C_MCR_RRF_MASK                       (0x200U)
69881 #define LPI2C_MCR_RRF_SHIFT                      (9U)
69882 /*! RRF - Reset Receive FIFO
69883  *  0b0..No effect
69884  *  0b1..Receive FIFO is reset
69885  */
69886 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
69887 /*! @} */
69888 
69889 /*! @name MSR - Master Status */
69890 /*! @{ */
69891 
69892 #define LPI2C_MSR_TDF_MASK                       (0x1U)
69893 #define LPI2C_MSR_TDF_SHIFT                      (0U)
69894 /*! TDF - Transmit Data Flag
69895  *  0b0..Transmit data is not requested
69896  *  0b1..Transmit data is requested
69897  */
69898 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
69899 
69900 #define LPI2C_MSR_RDF_MASK                       (0x2U)
69901 #define LPI2C_MSR_RDF_SHIFT                      (1U)
69902 /*! RDF - Receive Data Flag
69903  *  0b0..Receive Data is not ready
69904  *  0b1..Receive data is ready
69905  */
69906 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
69907 
69908 #define LPI2C_MSR_EPF_MASK                       (0x100U)
69909 #define LPI2C_MSR_EPF_SHIFT                      (8U)
69910 /*! EPF - End Packet Flag
69911  *  0b0..Master has not generated a STOP or Repeated START condition
69912  *  0b1..Master has generated a STOP or Repeated START condition
69913  */
69914 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
69915 
69916 #define LPI2C_MSR_SDF_MASK                       (0x200U)
69917 #define LPI2C_MSR_SDF_SHIFT                      (9U)
69918 /*! SDF - STOP Detect Flag
69919  *  0b0..Master has not generated a STOP condition
69920  *  0b1..Master has generated a STOP condition
69921  */
69922 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
69923 
69924 #define LPI2C_MSR_NDF_MASK                       (0x400U)
69925 #define LPI2C_MSR_NDF_SHIFT                      (10U)
69926 /*! NDF - NACK Detect Flag
69927  *  0b0..Unexpected NACK was not detected
69928  *  0b1..Unexpected NACK was detected
69929  */
69930 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
69931 
69932 #define LPI2C_MSR_ALF_MASK                       (0x800U)
69933 #define LPI2C_MSR_ALF_SHIFT                      (11U)
69934 /*! ALF - Arbitration Lost Flag
69935  *  0b0..Master has not lost arbitration
69936  *  0b1..Master has lost arbitration
69937  */
69938 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
69939 
69940 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
69941 #define LPI2C_MSR_FEF_SHIFT                      (12U)
69942 /*! FEF - FIFO Error Flag
69943  *  0b0..No error
69944  *  0b1..Master sending or receiving data without a START condition
69945  */
69946 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
69947 
69948 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
69949 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
69950 /*! PLTF - Pin Low Timeout Flag
69951  *  0b0..Pin low timeout has not occurred or is disabled
69952  *  0b1..Pin low timeout has occurred
69953  */
69954 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
69955 
69956 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
69957 #define LPI2C_MSR_DMF_SHIFT                      (14U)
69958 /*! DMF - Data Match Flag
69959  *  0b0..Have not received matching data
69960  *  0b1..Have received matching data
69961  */
69962 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
69963 
69964 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
69965 #define LPI2C_MSR_MBF_SHIFT                      (24U)
69966 /*! MBF - Master Busy Flag
69967  *  0b0..I2C Master is idle
69968  *  0b1..I2C Master is busy
69969  */
69970 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
69971 
69972 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
69973 #define LPI2C_MSR_BBF_SHIFT                      (25U)
69974 /*! BBF - Bus Busy Flag
69975  *  0b0..I2C Bus is idle
69976  *  0b1..I2C Bus is busy
69977  */
69978 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
69979 /*! @} */
69980 
69981 /*! @name MIER - Master Interrupt Enable */
69982 /*! @{ */
69983 
69984 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
69985 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
69986 /*! TDIE - Transmit Data Interrupt Enable
69987  *  0b0..Disabled
69988  *  0b1..Enabled
69989  */
69990 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
69991 
69992 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
69993 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
69994 /*! RDIE - Receive Data Interrupt Enable
69995  *  0b0..Disabled
69996  *  0b1..Enabled
69997  */
69998 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
69999 
70000 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
70001 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
70002 /*! EPIE - End Packet Interrupt Enable
70003  *  0b0..Disabled
70004  *  0b1..Enabled
70005  */
70006 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
70007 
70008 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
70009 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
70010 /*! SDIE - STOP Detect Interrupt Enable
70011  *  0b0..Disabled
70012  *  0b1..Enabled
70013  */
70014 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
70015 
70016 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
70017 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
70018 /*! NDIE - NACK Detect Interrupt Enable
70019  *  0b0..Disabled
70020  *  0b1..Enabled
70021  */
70022 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
70023 
70024 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
70025 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
70026 /*! ALIE - Arbitration Lost Interrupt Enable
70027  *  0b0..Disabled
70028  *  0b1..Enabled
70029  */
70030 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
70031 
70032 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
70033 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
70034 /*! FEIE - FIFO Error Interrupt Enable
70035  *  0b0..Enabled
70036  *  0b1..Disabled
70037  */
70038 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
70039 
70040 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
70041 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
70042 /*! PLTIE - Pin Low Timeout Interrupt Enable
70043  *  0b0..Disabled
70044  *  0b1..Enabled
70045  */
70046 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
70047 
70048 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
70049 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
70050 /*! DMIE - Data Match Interrupt Enable
70051  *  0b0..Disabled
70052  *  0b1..Enabled
70053  */
70054 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
70055 /*! @} */
70056 
70057 /*! @name MDER - Master DMA Enable */
70058 /*! @{ */
70059 
70060 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
70061 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
70062 /*! TDDE - Transmit Data DMA Enable
70063  *  0b0..DMA request is disabled
70064  *  0b1..DMA request is enabled
70065  */
70066 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
70067 
70068 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
70069 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
70070 /*! RDDE - Receive Data DMA Enable
70071  *  0b0..DMA request is disabled
70072  *  0b1..DMA request is enabled
70073  */
70074 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
70075 /*! @} */
70076 
70077 /*! @name MCFGR0 - Master Configuration 0 */
70078 /*! @{ */
70079 
70080 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
70081 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
70082 /*! HREN - Host Request Enable
70083  *  0b0..Host request input is disabled
70084  *  0b1..Host request input is enabled
70085  */
70086 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
70087 
70088 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
70089 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
70090 /*! HRPOL - Host Request Polarity
70091  *  0b0..Active low
70092  *  0b1..Active high
70093  */
70094 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
70095 
70096 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
70097 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
70098 /*! HRSEL - Host Request Select
70099  *  0b0..Host request input is pin HREQ
70100  *  0b1..Host request input is input trigger
70101  */
70102 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
70103 
70104 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
70105 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
70106 /*! CIRFIFO - Circular FIFO Enable
70107  *  0b0..Circular FIFO is disabled
70108  *  0b1..Circular FIFO is enabled
70109  */
70110 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
70111 
70112 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
70113 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
70114 /*! RDMO - Receive Data Match Only
70115  *  0b0..Received data is stored in the receive FIFO
70116  *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
70117  */
70118 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
70119 /*! @} */
70120 
70121 /*! @name MCFGR1 - Master Configuration 1 */
70122 /*! @{ */
70123 
70124 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
70125 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
70126 /*! PRESCALE - Prescaler
70127  *  0b000..Divide by 1
70128  *  0b001..Divide by 2
70129  *  0b010..Divide by 4
70130  *  0b011..Divide by 8
70131  *  0b100..Divide by 16
70132  *  0b101..Divide by 32
70133  *  0b110..Divide by 64
70134  *  0b111..Divide by 128
70135  */
70136 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
70137 
70138 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
70139 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
70140 /*! AUTOSTOP - Automatic STOP Generation
70141  *  0b0..No effect
70142  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
70143  */
70144 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
70145 
70146 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
70147 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
70148 /*! IGNACK - IGNACK
70149  *  0b0..LPI2C Master receives ACK and NACK normally
70150  *  0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK
70151  */
70152 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
70153 
70154 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
70155 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
70156 /*! TIMECFG - Timeout Configuration
70157  *  0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
70158  *  0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
70159  */
70160 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
70161 
70162 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
70163 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
70164 /*! MATCFG - Match Configuration
70165  *  0b000..Match is disabled
70166  *  0b001..Reserved
70167  *  0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
70168  *  0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
70169  *  0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
70170  *  0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
70171  *  0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
70172  *  0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
70173  */
70174 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
70175 
70176 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
70177 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
70178 /*! PINCFG - Pin Configuration
70179  *  0b000..2-pin open drain mode
70180  *  0b001..2-pin output only mode (ultra-fast mode)
70181  *  0b010..2-pin push-pull mode
70182  *  0b011..4-pin push-pull mode
70183  *  0b100..2-pin open drain mode with separate LPI2C slave
70184  *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
70185  *  0b110..2-pin push-pull mode with separate LPI2C slave
70186  *  0b111..4-pin push-pull mode (inverted outputs)
70187  */
70188 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
70189 /*! @} */
70190 
70191 /*! @name MCFGR2 - Master Configuration 2 */
70192 /*! @{ */
70193 
70194 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
70195 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
70196 /*! BUSIDLE - Bus Idle Timeout
70197  */
70198 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
70199 
70200 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
70201 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
70202 /*! FILTSCL - Glitch Filter SCL
70203  */
70204 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
70205 
70206 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
70207 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
70208 /*! FILTSDA - Glitch Filter SDA
70209  */
70210 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
70211 /*! @} */
70212 
70213 /*! @name MCFGR3 - Master Configuration 3 */
70214 /*! @{ */
70215 
70216 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
70217 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
70218 /*! PINLOW - Pin Low Timeout
70219  */
70220 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
70221 /*! @} */
70222 
70223 /*! @name MDMR - Master Data Match */
70224 /*! @{ */
70225 
70226 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
70227 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
70228 /*! MATCH0 - Match 0 Value
70229  */
70230 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
70231 
70232 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
70233 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
70234 /*! MATCH1 - Match 1 Value
70235  */
70236 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
70237 /*! @} */
70238 
70239 /*! @name MCCR0 - Master Clock Configuration 0 */
70240 /*! @{ */
70241 
70242 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
70243 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
70244 /*! CLKLO - Clock Low Period
70245  */
70246 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
70247 
70248 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
70249 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
70250 /*! CLKHI - Clock High Period
70251  */
70252 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
70253 
70254 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
70255 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
70256 /*! SETHOLD - Setup Hold Delay
70257  */
70258 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
70259 
70260 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
70261 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
70262 /*! DATAVD - Data Valid Delay
70263  */
70264 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
70265 /*! @} */
70266 
70267 /*! @name MCCR1 - Master Clock Configuration 1 */
70268 /*! @{ */
70269 
70270 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
70271 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
70272 /*! CLKLO - Clock Low Period
70273  */
70274 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
70275 
70276 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
70277 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
70278 /*! CLKHI - Clock High Period
70279  */
70280 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
70281 
70282 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
70283 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
70284 /*! SETHOLD - Setup Hold Delay
70285  */
70286 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
70287 
70288 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
70289 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
70290 /*! DATAVD - Data Valid Delay
70291  */
70292 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
70293 /*! @} */
70294 
70295 /*! @name MFCR - Master FIFO Control */
70296 /*! @{ */
70297 
70298 #define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
70299 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
70300 /*! TXWATER - Transmit FIFO Watermark
70301  */
70302 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
70303 
70304 #define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
70305 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
70306 /*! RXWATER - Receive FIFO Watermark
70307  */
70308 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
70309 /*! @} */
70310 
70311 /*! @name MFSR - Master FIFO Status */
70312 /*! @{ */
70313 
70314 #define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
70315 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
70316 /*! TXCOUNT - Transmit FIFO Count
70317  */
70318 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
70319 
70320 #define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
70321 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
70322 /*! RXCOUNT - Receive FIFO Count
70323  */
70324 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
70325 /*! @} */
70326 
70327 /*! @name MTDR - Master Transmit Data */
70328 /*! @{ */
70329 
70330 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
70331 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
70332 /*! DATA - Transmit Data
70333  */
70334 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
70335 
70336 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
70337 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
70338 /*! CMD - Command Data
70339  *  0b000..Transmit DATA[7:0]
70340  *  0b001..Receive (DATA[7:0] + 1) bytes
70341  *  0b010..Generate STOP condition
70342  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
70343  *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
70344  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
70345  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
70346  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
70347  */
70348 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
70349 /*! @} */
70350 
70351 /*! @name MRDR - Master Receive Data */
70352 /*! @{ */
70353 
70354 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
70355 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
70356 /*! DATA - Receive Data
70357  */
70358 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
70359 
70360 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
70361 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
70362 /*! RXEMPTY - RX Empty
70363  *  0b0..Receive FIFO is not empty
70364  *  0b1..Receive FIFO is empty
70365  */
70366 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
70367 /*! @} */
70368 
70369 /*! @name SCR - Slave Control */
70370 /*! @{ */
70371 
70372 #define LPI2C_SCR_SEN_MASK                       (0x1U)
70373 #define LPI2C_SCR_SEN_SHIFT                      (0U)
70374 /*! SEN - Slave Enable
70375  *  0b0..I2C Slave mode is disabled
70376  *  0b1..I2C Slave mode is enabled
70377  */
70378 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
70379 
70380 #define LPI2C_SCR_RST_MASK                       (0x2U)
70381 #define LPI2C_SCR_RST_SHIFT                      (1U)
70382 /*! RST - Software Reset
70383  *  0b0..Slave mode logic is not reset
70384  *  0b1..Slave mode logic is reset
70385  */
70386 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
70387 
70388 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
70389 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
70390 /*! FILTEN - Filter Enable
70391  *  0b0..Disable digital filter and output delay counter for slave mode
70392  *  0b1..Enable digital filter and output delay counter for slave mode
70393  */
70394 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
70395 
70396 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
70397 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
70398 /*! FILTDZ - Filter Doze Enable
70399  *  0b0..Filter remains enabled in Doze mode
70400  *  0b1..Filter is disabled in Doze mode
70401  */
70402 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
70403 
70404 #define LPI2C_SCR_RTF_MASK                       (0x100U)
70405 #define LPI2C_SCR_RTF_SHIFT                      (8U)
70406 /*! RTF - Reset Transmit FIFO
70407  *  0b0..No effect
70408  *  0b1..Transmit Data Register is now empty
70409  */
70410 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
70411 
70412 #define LPI2C_SCR_RRF_MASK                       (0x200U)
70413 #define LPI2C_SCR_RRF_SHIFT                      (9U)
70414 /*! RRF - Reset Receive FIFO
70415  *  0b0..No effect
70416  *  0b1..Receive Data Register is now empty
70417  */
70418 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
70419 /*! @} */
70420 
70421 /*! @name SSR - Slave Status */
70422 /*! @{ */
70423 
70424 #define LPI2C_SSR_TDF_MASK                       (0x1U)
70425 #define LPI2C_SSR_TDF_SHIFT                      (0U)
70426 /*! TDF - Transmit Data Flag
70427  *  0b0..Transmit data not requested
70428  *  0b1..Transmit data is requested
70429  */
70430 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
70431 
70432 #define LPI2C_SSR_RDF_MASK                       (0x2U)
70433 #define LPI2C_SSR_RDF_SHIFT                      (1U)
70434 /*! RDF - Receive Data Flag
70435  *  0b0..Receive data is not ready
70436  *  0b1..Receive data is ready
70437  */
70438 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
70439 
70440 #define LPI2C_SSR_AVF_MASK                       (0x4U)
70441 #define LPI2C_SSR_AVF_SHIFT                      (2U)
70442 /*! AVF - Address Valid Flag
70443  *  0b0..Address Status Register is not valid
70444  *  0b1..Address Status Register is valid
70445  */
70446 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
70447 
70448 #define LPI2C_SSR_TAF_MASK                       (0x8U)
70449 #define LPI2C_SSR_TAF_SHIFT                      (3U)
70450 /*! TAF - Transmit ACK Flag
70451  *  0b0..Transmit ACK/NACK is not required
70452  *  0b1..Transmit ACK/NACK is required
70453  */
70454 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
70455 
70456 #define LPI2C_SSR_RSF_MASK                       (0x100U)
70457 #define LPI2C_SSR_RSF_SHIFT                      (8U)
70458 /*! RSF - Repeated Start Flag
70459  *  0b0..Slave has not detected a Repeated START condition
70460  *  0b1..Slave has detected a Repeated START condition
70461  */
70462 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
70463 
70464 #define LPI2C_SSR_SDF_MASK                       (0x200U)
70465 #define LPI2C_SSR_SDF_SHIFT                      (9U)
70466 /*! SDF - STOP Detect Flag
70467  *  0b0..Slave has not detected a STOP condition
70468  *  0b1..Slave has detected a STOP condition
70469  */
70470 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
70471 
70472 #define LPI2C_SSR_BEF_MASK                       (0x400U)
70473 #define LPI2C_SSR_BEF_SHIFT                      (10U)
70474 /*! BEF - Bit Error Flag
70475  *  0b0..Slave has not detected a bit error
70476  *  0b1..Slave has detected a bit error
70477  */
70478 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
70479 
70480 #define LPI2C_SSR_FEF_MASK                       (0x800U)
70481 #define LPI2C_SSR_FEF_SHIFT                      (11U)
70482 /*! FEF - FIFO Error Flag
70483  *  0b0..FIFO underflow or overflow was not detected
70484  *  0b1..FIFO underflow or overflow was detected
70485  */
70486 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
70487 
70488 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
70489 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
70490 /*! AM0F - Address Match 0 Flag
70491  *  0b0..Have not received an ADDR0 matching address
70492  *  0b1..Have received an ADDR0 matching address
70493  */
70494 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
70495 
70496 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
70497 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
70498 /*! AM1F - Address Match 1 Flag
70499  *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
70500  *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
70501  */
70502 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
70503 
70504 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
70505 #define LPI2C_SSR_GCF_SHIFT                      (14U)
70506 /*! GCF - General Call Flag
70507  *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
70508  *  0b1..Slave has detected the General Call Address
70509  */
70510 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
70511 
70512 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
70513 #define LPI2C_SSR_SARF_SHIFT                     (15U)
70514 /*! SARF - SMBus Alert Response Flag
70515  *  0b0..SMBus Alert Response is disabled or not detected
70516  *  0b1..SMBus Alert Response is enabled and detected
70517  */
70518 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
70519 
70520 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
70521 #define LPI2C_SSR_SBF_SHIFT                      (24U)
70522 /*! SBF - Slave Busy Flag
70523  *  0b0..I2C Slave is idle
70524  *  0b1..I2C Slave is busy
70525  */
70526 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
70527 
70528 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
70529 #define LPI2C_SSR_BBF_SHIFT                      (25U)
70530 /*! BBF - Bus Busy Flag
70531  *  0b0..I2C Bus is idle
70532  *  0b1..I2C Bus is busy
70533  */
70534 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
70535 /*! @} */
70536 
70537 /*! @name SIER - Slave Interrupt Enable */
70538 /*! @{ */
70539 
70540 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
70541 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
70542 /*! TDIE - Transmit Data Interrupt Enable
70543  *  0b0..Disabled
70544  *  0b1..Enabled
70545  */
70546 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
70547 
70548 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
70549 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
70550 /*! RDIE - Receive Data Interrupt Enable
70551  *  0b0..Disabled
70552  *  0b1..Enabled
70553  */
70554 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
70555 
70556 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
70557 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
70558 /*! AVIE - Address Valid Interrupt Enable
70559  *  0b0..Disabled
70560  *  0b1..Enabled
70561  */
70562 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
70563 
70564 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
70565 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
70566 /*! TAIE - Transmit ACK Interrupt Enable
70567  *  0b0..Disabled
70568  *  0b1..Enabled
70569  */
70570 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
70571 
70572 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
70573 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
70574 /*! RSIE - Repeated Start Interrupt Enable
70575  *  0b0..Disabled
70576  *  0b1..Enabled
70577  */
70578 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
70579 
70580 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
70581 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
70582 /*! SDIE - STOP Detect Interrupt Enable
70583  *  0b0..Disabled
70584  *  0b1..Enabled
70585  */
70586 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
70587 
70588 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
70589 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
70590 /*! BEIE - Bit Error Interrupt Enable
70591  *  0b0..Disabled
70592  *  0b1..Enabled
70593  */
70594 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
70595 
70596 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
70597 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
70598 /*! FEIE - FIFO Error Interrupt Enable
70599  *  0b0..Disabled
70600  *  0b1..Enabled
70601  */
70602 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
70603 
70604 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
70605 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
70606 /*! AM0IE - Address Match 0 Interrupt Enable
70607  *  0b0..Disabled
70608  *  0b1..Enabled
70609  */
70610 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
70611 
70612 #define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
70613 #define LPI2C_SIER_AM1IE_SHIFT                   (13U)
70614 /*! AM1IE - Address Match 1 Interrupt Enable
70615  *  0b0..Disabled
70616  *  0b1..Enabled
70617  */
70618 #define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
70619 
70620 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
70621 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
70622 /*! GCIE - General Call Interrupt Enable
70623  *  0b0..Disabled
70624  *  0b1..Enabled
70625  */
70626 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
70627 
70628 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
70629 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
70630 /*! SARIE - SMBus Alert Response Interrupt Enable
70631  *  0b0..Disabled
70632  *  0b1..Enabled
70633  */
70634 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
70635 /*! @} */
70636 
70637 /*! @name SDER - Slave DMA Enable */
70638 /*! @{ */
70639 
70640 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
70641 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
70642 /*! TDDE - Transmit Data DMA Enable
70643  *  0b0..DMA request is disabled
70644  *  0b1..DMA request is enabled
70645  */
70646 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
70647 
70648 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
70649 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
70650 /*! RDDE - Receive Data DMA Enable
70651  *  0b0..DMA request is disabled
70652  *  0b1..DMA request is enabled
70653  */
70654 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
70655 
70656 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
70657 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
70658 /*! AVDE - Address Valid DMA Enable
70659  *  0b0..DMA request is disabled
70660  *  0b1..DMA request is enabled
70661  */
70662 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
70663 /*! @} */
70664 
70665 /*! @name SCFGR1 - Slave Configuration 1 */
70666 /*! @{ */
70667 
70668 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
70669 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
70670 /*! ADRSTALL - Address SCL Stall
70671  *  0b0..Clock stretching is disabled
70672  *  0b1..Clock stretching is enabled
70673  */
70674 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
70675 
70676 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
70677 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
70678 /*! RXSTALL - RX SCL Stall
70679  *  0b0..Clock stretching is disabled
70680  *  0b1..Clock stretching is enabled
70681  */
70682 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
70683 
70684 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
70685 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
70686 /*! TXDSTALL - TX Data SCL Stall
70687  *  0b0..Clock stretching is disabled
70688  *  0b1..Clock stretching is enabled
70689  */
70690 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
70691 
70692 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
70693 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
70694 /*! ACKSTALL - ACK SCL Stall
70695  *  0b0..Clock stretching is disabled
70696  *  0b1..Clock stretching is enabled
70697  */
70698 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
70699 
70700 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
70701 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
70702 /*! GCEN - General Call Enable
70703  *  0b0..General Call address is disabled
70704  *  0b1..General Call address is enabled
70705  */
70706 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
70707 
70708 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
70709 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
70710 /*! SAEN - SMBus Alert Enable
70711  *  0b0..Disables match on SMBus Alert
70712  *  0b1..Enables match on SMBus Alert
70713  */
70714 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
70715 
70716 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
70717 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
70718 /*! TXCFG - Transmit Flag Configuration
70719  *  0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
70720  *  0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
70721  */
70722 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
70723 
70724 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
70725 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
70726 /*! RXCFG - Receive Data Configuration
70727  *  0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]).
70728  *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address
70729  *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag
70730  *       is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
70731  */
70732 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
70733 
70734 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
70735 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
70736 /*! IGNACK - Ignore NACK
70737  *  0b0..Slave ends transfer when NACK is detected
70738  *  0b1..Slave does not end transfer when NACK detected
70739  */
70740 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
70741 
70742 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
70743 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
70744 /*! HSMEN - High Speed Mode Enable
70745  *  0b0..Disables detection of HS-mode master code
70746  *  0b1..Enables detection of HS-mode master code
70747  */
70748 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
70749 
70750 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
70751 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
70752 /*! ADDRCFG - Address Configuration
70753  *  0b000..Address match 0 (7-bit)
70754  *  0b001..Address match 0 (10-bit)
70755  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
70756  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
70757  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
70758  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
70759  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
70760  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
70761  */
70762 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
70763 /*! @} */
70764 
70765 /*! @name SCFGR2 - Slave Configuration 2 */
70766 /*! @{ */
70767 
70768 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
70769 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
70770 /*! CLKHOLD - Clock Hold Time
70771  */
70772 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
70773 
70774 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
70775 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
70776 /*! DATAVD - Data Valid Delay
70777  */
70778 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
70779 
70780 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
70781 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
70782 /*! FILTSCL - Glitch Filter SCL
70783  */
70784 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
70785 
70786 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
70787 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
70788 /*! FILTSDA - Glitch Filter SDA
70789  */
70790 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
70791 /*! @} */
70792 
70793 /*! @name SAMR - Slave Address Match */
70794 /*! @{ */
70795 
70796 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
70797 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
70798 /*! ADDR0 - Address 0 Value
70799  */
70800 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
70801 
70802 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
70803 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
70804 /*! ADDR1 - Address 1 Value
70805  */
70806 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
70807 /*! @} */
70808 
70809 /*! @name SASR - Slave Address Status */
70810 /*! @{ */
70811 
70812 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
70813 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
70814 /*! RADDR - Received Address
70815  */
70816 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
70817 
70818 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
70819 #define LPI2C_SASR_ANV_SHIFT                     (14U)
70820 /*! ANV - Address Not Valid
70821  *  0b0..Received Address (RADDR) is valid
70822  *  0b1..Received Address (RADDR) is not valid
70823  */
70824 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
70825 /*! @} */
70826 
70827 /*! @name STAR - Slave Transmit ACK */
70828 /*! @{ */
70829 
70830 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
70831 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
70832 /*! TXNACK - Transmit NACK
70833  *  0b0..Write a Transmit ACK for each received word
70834  *  0b1..Write a Transmit NACK for each received word
70835  */
70836 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
70837 /*! @} */
70838 
70839 /*! @name STDR - Slave Transmit Data */
70840 /*! @{ */
70841 
70842 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
70843 #define LPI2C_STDR_DATA_SHIFT                    (0U)
70844 /*! DATA - Transmit Data
70845  */
70846 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
70847 /*! @} */
70848 
70849 /*! @name SRDR - Slave Receive Data */
70850 /*! @{ */
70851 
70852 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
70853 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
70854 /*! DATA - Receive Data
70855  */
70856 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
70857 
70858 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
70859 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
70860 /*! RXEMPTY - RX Empty
70861  *  0b0..The Receive Data Register is not empty
70862  *  0b1..The Receive Data Register is empty
70863  */
70864 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
70865 
70866 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
70867 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
70868 /*! SOF - Start Of Frame
70869  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
70870  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
70871  */
70872 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
70873 /*! @} */
70874 
70875 
70876 /*!
70877  * @}
70878  */ /* end of group LPI2C_Register_Masks */
70879 
70880 
70881 /* LPI2C - Peripheral instance base addresses */
70882 /** Peripheral LPI2C1 base address */
70883 #define LPI2C1_BASE                              (0x40104000u)
70884 /** Peripheral LPI2C1 base pointer */
70885 #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
70886 /** Peripheral LPI2C2 base address */
70887 #define LPI2C2_BASE                              (0x40108000u)
70888 /** Peripheral LPI2C2 base pointer */
70889 #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
70890 /** Peripheral LPI2C3 base address */
70891 #define LPI2C3_BASE                              (0x4010C000u)
70892 /** Peripheral LPI2C3 base pointer */
70893 #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
70894 /** Peripheral LPI2C4 base address */
70895 #define LPI2C4_BASE                              (0x40110000u)
70896 /** Peripheral LPI2C4 base pointer */
70897 #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
70898 /** Peripheral LPI2C5 base address */
70899 #define LPI2C5_BASE                              (0x40C34000u)
70900 /** Peripheral LPI2C5 base pointer */
70901 #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
70902 /** Peripheral LPI2C6 base address */
70903 #define LPI2C6_BASE                              (0x40C38000u)
70904 /** Peripheral LPI2C6 base pointer */
70905 #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
70906 /** Array initializer of LPI2C peripheral base addresses */
70907 #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
70908 /** Array initializer of LPI2C peripheral base pointers */
70909 #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
70910 /** Interrupt vectors for the LPI2C peripheral type */
70911 #define LPI2C_IRQS                               { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
70912 
70913 /*!
70914  * @}
70915  */ /* end of group LPI2C_Peripheral_Access_Layer */
70916 
70917 
70918 /* ----------------------------------------------------------------------------
70919    -- LPSPI Peripheral Access Layer
70920    ---------------------------------------------------------------------------- */
70921 
70922 /*!
70923  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
70924  * @{
70925  */
70926 
70927 /** LPSPI - Register Layout Typedef */
70928 typedef struct {
70929   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
70930   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
70931        uint8_t RESERVED_0[8];
70932   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
70933   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
70934   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
70935   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
70936   __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
70937   __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
70938        uint8_t RESERVED_1[8];
70939   __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
70940   __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
70941        uint8_t RESERVED_2[8];
70942   __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
70943        uint8_t RESERVED_3[20];
70944   __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
70945   __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
70946   __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
70947   __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
70948        uint8_t RESERVED_4[8];
70949   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
70950   __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
70951 } LPSPI_Type;
70952 
70953 /* ----------------------------------------------------------------------------
70954    -- LPSPI Register Masks
70955    ---------------------------------------------------------------------------- */
70956 
70957 /*!
70958  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
70959  * @{
70960  */
70961 
70962 /*! @name VERID - Version ID */
70963 /*! @{ */
70964 
70965 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
70966 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
70967 /*! FEATURE - Module Identification Number
70968  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
70969  */
70970 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
70971 
70972 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
70973 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
70974 /*! MINOR - Minor Version Number
70975  */
70976 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
70977 
70978 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
70979 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
70980 /*! MAJOR - Major Version Number
70981  */
70982 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
70983 /*! @} */
70984 
70985 /*! @name PARAM - Parameter */
70986 /*! @{ */
70987 
70988 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
70989 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
70990 /*! TXFIFO - Transmit FIFO Size
70991  */
70992 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
70993 
70994 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
70995 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
70996 /*! RXFIFO - Receive FIFO Size
70997  */
70998 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
70999 
71000 #define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
71001 #define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
71002 /*! PCSNUM - PCS Number
71003  */
71004 #define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
71005 /*! @} */
71006 
71007 /*! @name CR - Control */
71008 /*! @{ */
71009 
71010 #define LPSPI_CR_MEN_MASK                        (0x1U)
71011 #define LPSPI_CR_MEN_SHIFT                       (0U)
71012 /*! MEN - Module Enable
71013  *  0b0..Module is disabled
71014  *  0b1..Module is enabled
71015  */
71016 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
71017 
71018 #define LPSPI_CR_RST_MASK                        (0x2U)
71019 #define LPSPI_CR_RST_SHIFT                       (1U)
71020 /*! RST - Software Reset
71021  *  0b0..Module is not reset
71022  *  0b1..Module is reset
71023  */
71024 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
71025 
71026 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
71027 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
71028 /*! DOZEN - Doze Mode Enable
71029  *  0b0..LPSPI module is enabled in Doze mode
71030  *  0b1..LPSPI module is disabled in Doze mode
71031  */
71032 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
71033 
71034 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
71035 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
71036 /*! DBGEN - Debug Enable
71037  *  0b0..LPSPI module is disabled in debug mode
71038  *  0b1..LPSPI module is enabled in debug mode
71039  */
71040 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
71041 
71042 #define LPSPI_CR_RTF_MASK                        (0x100U)
71043 #define LPSPI_CR_RTF_SHIFT                       (8U)
71044 /*! RTF - Reset Transmit FIFO
71045  *  0b0..No effect
71046  *  0b1..Reset the Transmit FIFO. The register bit always reads zero.
71047  */
71048 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
71049 
71050 #define LPSPI_CR_RRF_MASK                        (0x200U)
71051 #define LPSPI_CR_RRF_SHIFT                       (9U)
71052 /*! RRF - Reset Receive FIFO
71053  *  0b0..No effect
71054  *  0b1..Reset the Receive FIFO. The register bit always reads zero.
71055  */
71056 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
71057 /*! @} */
71058 
71059 /*! @name SR - Status */
71060 /*! @{ */
71061 
71062 #define LPSPI_SR_TDF_MASK                        (0x1U)
71063 #define LPSPI_SR_TDF_SHIFT                       (0U)
71064 /*! TDF - Transmit Data Flag
71065  *  0b0..Transmit data not requested
71066  *  0b1..Transmit data is requested
71067  */
71068 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
71069 
71070 #define LPSPI_SR_RDF_MASK                        (0x2U)
71071 #define LPSPI_SR_RDF_SHIFT                       (1U)
71072 /*! RDF - Receive Data Flag
71073  *  0b0..Receive Data is not ready
71074  *  0b1..Receive data is ready
71075  */
71076 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
71077 
71078 #define LPSPI_SR_WCF_MASK                        (0x100U)
71079 #define LPSPI_SR_WCF_SHIFT                       (8U)
71080 /*! WCF - Word Complete Flag
71081  *  0b0..Transfer of a received word has not yet completed
71082  *  0b1..Transfer of a received word has completed
71083  */
71084 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
71085 
71086 #define LPSPI_SR_FCF_MASK                        (0x200U)
71087 #define LPSPI_SR_FCF_SHIFT                       (9U)
71088 /*! FCF - Frame Complete Flag
71089  *  0b0..Frame transfer has not completed
71090  *  0b1..Frame transfer has completed
71091  */
71092 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
71093 
71094 #define LPSPI_SR_TCF_MASK                        (0x400U)
71095 #define LPSPI_SR_TCF_SHIFT                       (10U)
71096 /*! TCF - Transfer Complete Flag
71097  *  0b0..All transfers have not completed
71098  *  0b1..All transfers have completed
71099  */
71100 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
71101 
71102 #define LPSPI_SR_TEF_MASK                        (0x800U)
71103 #define LPSPI_SR_TEF_SHIFT                       (11U)
71104 /*! TEF - Transmit Error Flag
71105  *  0b0..Transmit FIFO underrun has not occurred
71106  *  0b1..Transmit FIFO underrun has occurred
71107  */
71108 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
71109 
71110 #define LPSPI_SR_REF_MASK                        (0x1000U)
71111 #define LPSPI_SR_REF_SHIFT                       (12U)
71112 /*! REF - Receive Error Flag
71113  *  0b0..Receive FIFO has not overflowed
71114  *  0b1..Receive FIFO has overflowed
71115  */
71116 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
71117 
71118 #define LPSPI_SR_DMF_MASK                        (0x2000U)
71119 #define LPSPI_SR_DMF_SHIFT                       (13U)
71120 /*! DMF - Data Match Flag
71121  *  0b0..Have not received matching data
71122  *  0b1..Have received matching data
71123  */
71124 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
71125 
71126 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
71127 #define LPSPI_SR_MBF_SHIFT                       (24U)
71128 /*! MBF - Module Busy Flag
71129  *  0b0..LPSPI is idle
71130  *  0b1..LPSPI is busy
71131  */
71132 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
71133 /*! @} */
71134 
71135 /*! @name IER - Interrupt Enable */
71136 /*! @{ */
71137 
71138 #define LPSPI_IER_TDIE_MASK                      (0x1U)
71139 #define LPSPI_IER_TDIE_SHIFT                     (0U)
71140 /*! TDIE - Transmit Data Interrupt Enable
71141  *  0b0..Disabled
71142  *  0b1..Enabled
71143  */
71144 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
71145 
71146 #define LPSPI_IER_RDIE_MASK                      (0x2U)
71147 #define LPSPI_IER_RDIE_SHIFT                     (1U)
71148 /*! RDIE - Receive Data Interrupt Enable
71149  *  0b0..Disabled
71150  *  0b1..Enabled
71151  */
71152 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
71153 
71154 #define LPSPI_IER_WCIE_MASK                      (0x100U)
71155 #define LPSPI_IER_WCIE_SHIFT                     (8U)
71156 /*! WCIE - Word Complete Interrupt Enable
71157  *  0b0..Disabled
71158  *  0b1..Enabled
71159  */
71160 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
71161 
71162 #define LPSPI_IER_FCIE_MASK                      (0x200U)
71163 #define LPSPI_IER_FCIE_SHIFT                     (9U)
71164 /*! FCIE - Frame Complete Interrupt Enable
71165  *  0b0..Disabled
71166  *  0b1..Enabled
71167  */
71168 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
71169 
71170 #define LPSPI_IER_TCIE_MASK                      (0x400U)
71171 #define LPSPI_IER_TCIE_SHIFT                     (10U)
71172 /*! TCIE - Transfer Complete Interrupt Enable
71173  *  0b0..Disabled
71174  *  0b1..Enabled
71175  */
71176 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
71177 
71178 #define LPSPI_IER_TEIE_MASK                      (0x800U)
71179 #define LPSPI_IER_TEIE_SHIFT                     (11U)
71180 /*! TEIE - Transmit Error Interrupt Enable
71181  *  0b0..Disabled
71182  *  0b1..Enabled
71183  */
71184 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
71185 
71186 #define LPSPI_IER_REIE_MASK                      (0x1000U)
71187 #define LPSPI_IER_REIE_SHIFT                     (12U)
71188 /*! REIE - Receive Error Interrupt Enable
71189  *  0b0..Disabled
71190  *  0b1..Enabled
71191  */
71192 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
71193 
71194 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
71195 #define LPSPI_IER_DMIE_SHIFT                     (13U)
71196 /*! DMIE - Data Match Interrupt Enable
71197  *  0b0..Disabled
71198  *  0b1..Enabled
71199  */
71200 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
71201 /*! @} */
71202 
71203 /*! @name DER - DMA Enable */
71204 /*! @{ */
71205 
71206 #define LPSPI_DER_TDDE_MASK                      (0x1U)
71207 #define LPSPI_DER_TDDE_SHIFT                     (0U)
71208 /*! TDDE - Transmit Data DMA Enable
71209  *  0b0..DMA request is disabled
71210  *  0b1..DMA request is enabled
71211  */
71212 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
71213 
71214 #define LPSPI_DER_RDDE_MASK                      (0x2U)
71215 #define LPSPI_DER_RDDE_SHIFT                     (1U)
71216 /*! RDDE - Receive Data DMA Enable
71217  *  0b0..DMA request is disabled
71218  *  0b1..DMA request is enabled
71219  */
71220 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
71221 /*! @} */
71222 
71223 /*! @name CFGR0 - Configuration 0 */
71224 /*! @{ */
71225 
71226 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
71227 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
71228 /*! CIRFIFO - Circular FIFO Enable
71229  *  0b0..Circular FIFO is disabled
71230  *  0b1..Circular FIFO is enabled
71231  */
71232 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
71233 
71234 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
71235 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
71236 /*! RDMO - Receive Data Match Only
71237  *  0b0..Received data is stored in the receive FIFO as in normal operations
71238  *  0b1..Received data is discarded unless the SR[DMF] = 1
71239  */
71240 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
71241 /*! @} */
71242 
71243 /*! @name CFGR1 - Configuration 1 */
71244 /*! @{ */
71245 
71246 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
71247 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
71248 /*! MASTER - Master Mode
71249  *  0b0..Slave mode
71250  *  0b1..Master mode
71251  */
71252 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
71253 
71254 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
71255 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
71256 /*! SAMPLE - Sample Point
71257  *  0b0..Input data is sampled on SCK edge
71258  *  0b1..Input data is sampled on delayed SCK edge
71259  */
71260 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
71261 
71262 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
71263 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
71264 /*! AUTOPCS - Automatic PCS
71265  *  0b0..Automatic PCS generation is disabled
71266  *  0b1..Automatic PCS generation is enabled
71267  */
71268 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
71269 
71270 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
71271 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
71272 /*! NOSTALL - No Stall
71273  *  0b0..Transfers stall when the transmit FIFO is empty
71274  *  0b1..Transfers do not stall, allowing transmit FIFO underruns to occur
71275  */
71276 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
71277 
71278 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
71279 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
71280 /*! PCSPOL - Peripheral Chip Select Polarity
71281  */
71282 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
71283 
71284 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
71285 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
71286 /*! MATCFG - Match Configuration
71287  *  0b000..Match is disabled
71288  *  0b001..Reserved
71289  *  0b010..Match is enabled is 1st data word is MATCH0 or MATCH1
71290  *  0b011..Match is enabled on any data word equal MATCH0 or MATCH1
71291  *  0b100..Match is enabled on data match sequence
71292  *  0b101..Match is enabled on data match sequence
71293  *  0b110..Match is enabled
71294  *  0b111..Match is enabled
71295  */
71296 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
71297 
71298 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
71299 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
71300 /*! PINCFG - Pin Configuration
71301  *  0b00..SIN is used for input data and SOUT is used for output data
71302  *  0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
71303  *  0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
71304  *  0b11..SOUT is used for input data and SIN is used for output data
71305  */
71306 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
71307 
71308 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
71309 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
71310 /*! OUTCFG - Output Configuration
71311  *  0b0..Output data retains last value when chip select is negated
71312  *  0b1..Output data is tristated when chip select is negated
71313  */
71314 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
71315 
71316 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
71317 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
71318 /*! PCSCFG - Peripheral Chip Select Configuration
71319  *  0b0..PCS[3:2] are configured for chip select function
71320  *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
71321  */
71322 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
71323 /*! @} */
71324 
71325 /*! @name DMR0 - Data Match 0 */
71326 /*! @{ */
71327 
71328 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
71329 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
71330 /*! MATCH0 - Match 0 Value
71331  */
71332 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
71333 /*! @} */
71334 
71335 /*! @name DMR1 - Data Match 1 */
71336 /*! @{ */
71337 
71338 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
71339 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
71340 /*! MATCH1 - Match 1 Value
71341  */
71342 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
71343 /*! @} */
71344 
71345 /*! @name CCR - Clock Configuration */
71346 /*! @{ */
71347 
71348 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
71349 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
71350 /*! SCKDIV - SCK Divider
71351  */
71352 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
71353 
71354 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
71355 #define LPSPI_CCR_DBT_SHIFT                      (8U)
71356 /*! DBT - Delay Between Transfers
71357  */
71358 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
71359 
71360 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
71361 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
71362 /*! PCSSCK - PCS-to-SCK Delay
71363  */
71364 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
71365 
71366 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
71367 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
71368 /*! SCKPCS - SCK-to-PCS Delay
71369  */
71370 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
71371 /*! @} */
71372 
71373 /*! @name FCR - FIFO Control */
71374 /*! @{ */
71375 
71376 #define LPSPI_FCR_TXWATER_MASK                   (0xFU)
71377 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
71378 /*! TXWATER - Transmit FIFO Watermark
71379  */
71380 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
71381 
71382 #define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)
71383 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
71384 /*! RXWATER - Receive FIFO Watermark
71385  */
71386 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
71387 /*! @} */
71388 
71389 /*! @name FSR - FIFO Status */
71390 /*! @{ */
71391 
71392 #define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)
71393 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
71394 /*! TXCOUNT - Transmit FIFO Count
71395  */
71396 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
71397 
71398 #define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)
71399 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
71400 /*! RXCOUNT - Receive FIFO Count
71401  */
71402 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
71403 /*! @} */
71404 
71405 /*! @name TCR - Transmit Command */
71406 /*! @{ */
71407 
71408 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
71409 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
71410 /*! FRAMESZ - Frame Size
71411  */
71412 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
71413 
71414 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
71415 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
71416 /*! WIDTH - Transfer Width
71417  *  0b00..1 bit transfer
71418  *  0b01..2 bit transfer
71419  *  0b10..4 bit transfer
71420  *  0b11..Reserved
71421  */
71422 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
71423 
71424 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
71425 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
71426 /*! TXMSK - Transmit Data Mask
71427  *  0b0..Normal transfer
71428  *  0b1..Mask transmit data
71429  */
71430 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
71431 
71432 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
71433 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
71434 /*! RXMSK - Receive Data Mask
71435  *  0b0..Normal transfer
71436  *  0b1..Receive data is masked
71437  */
71438 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
71439 
71440 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
71441 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
71442 /*! CONTC - Continuing Command
71443  *  0b0..Command word for start of new transfer
71444  *  0b1..Command word for continuing transfer
71445  */
71446 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
71447 
71448 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
71449 #define LPSPI_TCR_CONT_SHIFT                     (21U)
71450 /*! CONT - Continuous Transfer
71451  *  0b0..Continuous transfer is disabled
71452  *  0b1..Continuous transfer is enabled
71453  */
71454 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
71455 
71456 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
71457 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
71458 /*! BYSW - Byte Swap
71459  *  0b0..Byte swap is disabled
71460  *  0b1..Byte swap is enabled
71461  */
71462 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
71463 
71464 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
71465 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
71466 /*! LSBF - LSB First
71467  *  0b0..Data is transferred MSB first
71468  *  0b1..Data is transferred LSB first
71469  */
71470 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
71471 
71472 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
71473 #define LPSPI_TCR_PCS_SHIFT                      (24U)
71474 /*! PCS - Peripheral Chip Select
71475  *  0b00..Transfer using PCS[0]
71476  *  0b01..Transfer using PCS[1]
71477  *  0b10..Transfer using PCS[2]
71478  *  0b11..Transfer using PCS[3]
71479  */
71480 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
71481 
71482 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
71483 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
71484 /*! PRESCALE - Prescaler Value
71485  *  0b000..Divide by 1
71486  *  0b001..Divide by 2
71487  *  0b010..Divide by 4
71488  *  0b011..Divide by 8
71489  *  0b100..Divide by 16
71490  *  0b101..Divide by 32
71491  *  0b110..Divide by 64
71492  *  0b111..Divide by 128
71493  */
71494 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
71495 
71496 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
71497 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
71498 /*! CPHA - Clock Phase
71499  *  0b0..Captured
71500  *  0b1..Changed
71501  */
71502 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
71503 
71504 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
71505 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
71506 /*! CPOL - Clock Polarity
71507  *  0b0..The inactive state value of SCK is low
71508  *  0b1..The inactive state value of SCK is high
71509  */
71510 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
71511 /*! @} */
71512 
71513 /*! @name TDR - Transmit Data */
71514 /*! @{ */
71515 
71516 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
71517 #define LPSPI_TDR_DATA_SHIFT                     (0U)
71518 /*! DATA - Transmit Data
71519  */
71520 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
71521 /*! @} */
71522 
71523 /*! @name RSR - Receive Status */
71524 /*! @{ */
71525 
71526 #define LPSPI_RSR_SOF_MASK                       (0x1U)
71527 #define LPSPI_RSR_SOF_SHIFT                      (0U)
71528 /*! SOF - Start Of Frame
71529  *  0b0..Subsequent data word received after PCS assertion
71530  *  0b1..First data word received after PCS assertion
71531  */
71532 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
71533 
71534 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
71535 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
71536 /*! RXEMPTY - RX FIFO Empty
71537  *  0b0..RX FIFO is not empty
71538  *  0b1..RX FIFO is empty
71539  */
71540 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
71541 /*! @} */
71542 
71543 /*! @name RDR - Receive Data */
71544 /*! @{ */
71545 
71546 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
71547 #define LPSPI_RDR_DATA_SHIFT                     (0U)
71548 /*! DATA - Receive Data
71549  */
71550 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
71551 /*! @} */
71552 
71553 
71554 /*!
71555  * @}
71556  */ /* end of group LPSPI_Register_Masks */
71557 
71558 
71559 /* LPSPI - Peripheral instance base addresses */
71560 /** Peripheral LPSPI1 base address */
71561 #define LPSPI1_BASE                              (0x40114000u)
71562 /** Peripheral LPSPI1 base pointer */
71563 #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
71564 /** Peripheral LPSPI2 base address */
71565 #define LPSPI2_BASE                              (0x40118000u)
71566 /** Peripheral LPSPI2 base pointer */
71567 #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
71568 /** Peripheral LPSPI3 base address */
71569 #define LPSPI3_BASE                              (0x4011C000u)
71570 /** Peripheral LPSPI3 base pointer */
71571 #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
71572 /** Peripheral LPSPI4 base address */
71573 #define LPSPI4_BASE                              (0x40120000u)
71574 /** Peripheral LPSPI4 base pointer */
71575 #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
71576 /** Peripheral LPSPI5 base address */
71577 #define LPSPI5_BASE                              (0x40C2C000u)
71578 /** Peripheral LPSPI5 base pointer */
71579 #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
71580 /** Peripheral LPSPI6 base address */
71581 #define LPSPI6_BASE                              (0x40C30000u)
71582 /** Peripheral LPSPI6 base pointer */
71583 #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
71584 /** Array initializer of LPSPI peripheral base addresses */
71585 #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
71586 /** Array initializer of LPSPI peripheral base pointers */
71587 #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
71588 /** Interrupt vectors for the LPSPI peripheral type */
71589 #define LPSPI_IRQS                               { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
71590 
71591 /*!
71592  * @}
71593  */ /* end of group LPSPI_Peripheral_Access_Layer */
71594 
71595 
71596 /* ----------------------------------------------------------------------------
71597    -- LPUART Peripheral Access Layer
71598    ---------------------------------------------------------------------------- */
71599 
71600 /*!
71601  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
71602  * @{
71603  */
71604 
71605 /** LPUART - Register Layout Typedef */
71606 typedef struct {
71607   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
71608   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
71609   __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
71610   __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
71611   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
71612   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
71613   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
71614   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
71615   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
71616   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
71617   __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
71618   __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
71619 } LPUART_Type;
71620 
71621 /* ----------------------------------------------------------------------------
71622    -- LPUART Register Masks
71623    ---------------------------------------------------------------------------- */
71624 
71625 /*!
71626  * @addtogroup LPUART_Register_Masks LPUART Register Masks
71627  * @{
71628  */
71629 
71630 /*! @name VERID - Version ID Register */
71631 /*! @{ */
71632 
71633 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
71634 #define LPUART_VERID_FEATURE_SHIFT               (0U)
71635 /*! FEATURE - Feature Identification Number
71636  *  0b0000000000000001..Standard feature set.
71637  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
71638  */
71639 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
71640 
71641 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
71642 #define LPUART_VERID_MINOR_SHIFT                 (16U)
71643 /*! MINOR - Minor Version Number
71644  */
71645 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
71646 
71647 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
71648 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
71649 /*! MAJOR - Major Version Number
71650  */
71651 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
71652 /*! @} */
71653 
71654 /*! @name PARAM - Parameter Register */
71655 /*! @{ */
71656 
71657 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
71658 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
71659 /*! TXFIFO - Transmit FIFO Size
71660  */
71661 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
71662 
71663 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
71664 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
71665 /*! RXFIFO - Receive FIFO Size
71666  */
71667 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
71668 /*! @} */
71669 
71670 /*! @name GLOBAL - LPUART Global Register */
71671 /*! @{ */
71672 
71673 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
71674 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
71675 /*! RST - Software Reset
71676  *  0b0..Module is not reset.
71677  *  0b1..Module is reset.
71678  */
71679 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
71680 /*! @} */
71681 
71682 /*! @name PINCFG - LPUART Pin Configuration Register */
71683 /*! @{ */
71684 
71685 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
71686 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
71687 /*! TRGSEL - Trigger Select
71688  *  0b00..Input trigger is disabled.
71689  *  0b01..Input trigger is used instead of RXD pin input.
71690  *  0b10..Input trigger is used instead of CTS_B pin input.
71691  *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
71692  *        internally ANDed with the input trigger.
71693  */
71694 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
71695 /*! @} */
71696 
71697 /*! @name BAUD - LPUART Baud Rate Register */
71698 /*! @{ */
71699 
71700 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
71701 #define LPUART_BAUD_SBR_SHIFT                    (0U)
71702 /*! SBR - Baud Rate Modulo Divisor.
71703  */
71704 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
71705 
71706 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
71707 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
71708 /*! SBNS - Stop Bit Number Select
71709  *  0b0..One stop bit.
71710  *  0b1..Two stop bits.
71711  */
71712 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
71713 
71714 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
71715 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
71716 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
71717  *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
71718  *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
71719  */
71720 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
71721 
71722 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
71723 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
71724 /*! LBKDIE - LIN Break Detect Interrupt Enable
71725  *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
71726  *  0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
71727  */
71728 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
71729 
71730 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
71731 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
71732 /*! RESYNCDIS - Resynchronization Disable
71733  *  0b0..Resynchronization during received data word is supported.
71734  *  0b1..Resynchronization during received data word is disabled.
71735  */
71736 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
71737 
71738 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
71739 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
71740 /*! BOTHEDGE - Both Edge Sampling
71741  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
71742  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
71743  */
71744 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
71745 
71746 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
71747 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
71748 /*! MATCFG - Match Configuration
71749  *  0b00..Address Match Wakeup
71750  *  0b01..Idle Match Wakeup
71751  *  0b10..Match On and Match Off
71752  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
71753  */
71754 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
71755 
71756 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
71757 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
71758 /*! RDMAE - Receiver Full DMA Enable
71759  *  0b0..DMA request disabled.
71760  *  0b1..DMA request enabled.
71761  */
71762 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
71763 
71764 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
71765 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
71766 /*! TDMAE - Transmitter DMA Enable
71767  *  0b0..DMA request disabled.
71768  *  0b1..DMA request enabled.
71769  */
71770 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
71771 
71772 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
71773 #define LPUART_BAUD_OSR_SHIFT                    (24U)
71774 /*! OSR - Oversampling Ratio
71775  *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
71776  *  0b00001..Reserved
71777  *  0b00010..Reserved
71778  *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
71779  *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
71780  *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
71781  *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
71782  *  0b00111..Oversampling ratio of 8.
71783  *  0b01000..Oversampling ratio of 9.
71784  *  0b01001..Oversampling ratio of 10.
71785  *  0b01010..Oversampling ratio of 11.
71786  *  0b01011..Oversampling ratio of 12.
71787  *  0b01100..Oversampling ratio of 13.
71788  *  0b01101..Oversampling ratio of 14.
71789  *  0b01110..Oversampling ratio of 15.
71790  *  0b01111..Oversampling ratio of 16.
71791  *  0b10000..Oversampling ratio of 17.
71792  *  0b10001..Oversampling ratio of 18.
71793  *  0b10010..Oversampling ratio of 19.
71794  *  0b10011..Oversampling ratio of 20.
71795  *  0b10100..Oversampling ratio of 21.
71796  *  0b10101..Oversampling ratio of 22.
71797  *  0b10110..Oversampling ratio of 23.
71798  *  0b10111..Oversampling ratio of 24.
71799  *  0b11000..Oversampling ratio of 25.
71800  *  0b11001..Oversampling ratio of 26.
71801  *  0b11010..Oversampling ratio of 27.
71802  *  0b11011..Oversampling ratio of 28.
71803  *  0b11100..Oversampling ratio of 29.
71804  *  0b11101..Oversampling ratio of 30.
71805  *  0b11110..Oversampling ratio of 31.
71806  *  0b11111..Oversampling ratio of 32.
71807  */
71808 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
71809 
71810 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
71811 #define LPUART_BAUD_M10_SHIFT                    (29U)
71812 /*! M10 - 10-bit Mode select
71813  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
71814  *  0b1..Receiver and transmitter use 10-bit data characters.
71815  */
71816 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
71817 
71818 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
71819 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
71820 /*! MAEN2 - Match Address Mode Enable 2
71821  *  0b0..Normal operation.
71822  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
71823  */
71824 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
71825 
71826 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
71827 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
71828 /*! MAEN1 - Match Address Mode Enable 1
71829  *  0b0..Normal operation.
71830  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
71831  */
71832 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
71833 /*! @} */
71834 
71835 /*! @name STAT - LPUART Status Register */
71836 /*! @{ */
71837 
71838 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
71839 #define LPUART_STAT_MA2F_SHIFT                   (14U)
71840 /*! MA2F - Match 2 Flag
71841  *  0b0..Received data is not equal to MA2
71842  *  0b1..Received data is equal to MA2
71843  */
71844 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
71845 
71846 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
71847 #define LPUART_STAT_MA1F_SHIFT                   (15U)
71848 /*! MA1F - Match 1 Flag
71849  *  0b0..Received data is not equal to MA1
71850  *  0b1..Received data is equal to MA1
71851  */
71852 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
71853 
71854 #define LPUART_STAT_PF_MASK                      (0x10000U)
71855 #define LPUART_STAT_PF_SHIFT                     (16U)
71856 /*! PF - Parity Error Flag
71857  *  0b0..No parity error.
71858  *  0b1..Parity error.
71859  */
71860 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
71861 
71862 #define LPUART_STAT_FE_MASK                      (0x20000U)
71863 #define LPUART_STAT_FE_SHIFT                     (17U)
71864 /*! FE - Framing Error Flag
71865  *  0b0..No framing error detected. This does not guarantee the framing is correct.
71866  *  0b1..Framing error.
71867  */
71868 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
71869 
71870 #define LPUART_STAT_NF_MASK                      (0x40000U)
71871 #define LPUART_STAT_NF_SHIFT                     (18U)
71872 /*! NF - Noise Flag
71873  *  0b0..No noise detected.
71874  *  0b1..Noise detected in the received character in the DATA register.
71875  */
71876 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
71877 
71878 #define LPUART_STAT_OR_MASK                      (0x80000U)
71879 #define LPUART_STAT_OR_SHIFT                     (19U)
71880 /*! OR - Receiver Overrun Flag
71881  *  0b0..No overrun.
71882  *  0b1..Receive overrun (new LPUART data lost).
71883  */
71884 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
71885 
71886 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
71887 #define LPUART_STAT_IDLE_SHIFT                   (20U)
71888 /*! IDLE - Idle Line Flag
71889  *  0b0..No idle line detected.
71890  *  0b1..Idle line is detected.
71891  */
71892 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
71893 
71894 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
71895 #define LPUART_STAT_RDRF_SHIFT                   (21U)
71896 /*! RDRF - Receive Data Register Full Flag
71897  *  0b0..Receive FIFO level is less than watermark.
71898  *  0b1..Receive FIFO level is equal or greater than watermark.
71899  */
71900 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
71901 
71902 #define LPUART_STAT_TC_MASK                      (0x400000U)
71903 #define LPUART_STAT_TC_SHIFT                     (22U)
71904 /*! TC - Transmission Complete Flag
71905  *  0b0..Transmitter active (sending data, a preamble, or a break).
71906  *  0b1..Transmitter idle (transmission activity complete).
71907  */
71908 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
71909 
71910 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
71911 #define LPUART_STAT_TDRE_SHIFT                   (23U)
71912 /*! TDRE - Transmit Data Register Empty Flag
71913  *  0b0..Transmit FIFO level is greater than watermark.
71914  *  0b1..Transmit FIFO level is equal or less than watermark.
71915  */
71916 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
71917 
71918 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
71919 #define LPUART_STAT_RAF_SHIFT                    (24U)
71920 /*! RAF - Receiver Active Flag
71921  *  0b0..LPUART receiver idle waiting for a start bit.
71922  *  0b1..LPUART receiver active (RXD input not idle).
71923  */
71924 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
71925 
71926 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
71927 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
71928 /*! LBKDE - LIN Break Detection Enable
71929  *  0b0..LIN break detect is disabled, normal break character can be detected.
71930  *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
71931  */
71932 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
71933 
71934 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
71935 #define LPUART_STAT_BRK13_SHIFT                  (26U)
71936 /*! BRK13 - Break Character Generation Length
71937  *  0b0..Break character is transmitted with length of 9 to 13 bit times.
71938  *  0b1..Break character is transmitted with length of 12 to 15 bit times.
71939  */
71940 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
71941 
71942 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
71943 #define LPUART_STAT_RWUID_SHIFT                  (27U)
71944 /*! RWUID - Receive Wake Up Idle Detect
71945  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
71946  *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
71947  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
71948  *       address match wakeup, the IDLE bit does set when an address does not match.
71949  */
71950 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
71951 
71952 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
71953 #define LPUART_STAT_RXINV_SHIFT                  (28U)
71954 /*! RXINV - Receive Data Inversion
71955  *  0b0..Receive data not inverted.
71956  *  0b1..Receive data inverted.
71957  */
71958 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
71959 
71960 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
71961 #define LPUART_STAT_MSBF_SHIFT                   (29U)
71962 /*! MSBF - MSB First
71963  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
71964  *       after the start bit is identified as bit0.
71965  *  0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
71966  *       depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
71967  */
71968 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
71969 
71970 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
71971 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
71972 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
71973  *  0b0..No active edge on the receive pin has occurred.
71974  *  0b1..An active edge on the receive pin has occurred.
71975  */
71976 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
71977 
71978 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
71979 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
71980 /*! LBKDIF - LIN Break Detect Interrupt Flag
71981  *  0b0..No LIN break character has been detected.
71982  *  0b1..LIN break character has been detected.
71983  */
71984 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
71985 /*! @} */
71986 
71987 /*! @name CTRL - LPUART Control Register */
71988 /*! @{ */
71989 
71990 #define LPUART_CTRL_PT_MASK                      (0x1U)
71991 #define LPUART_CTRL_PT_SHIFT                     (0U)
71992 /*! PT - Parity Type
71993  *  0b0..Even parity.
71994  *  0b1..Odd parity.
71995  */
71996 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
71997 
71998 #define LPUART_CTRL_PE_MASK                      (0x2U)
71999 #define LPUART_CTRL_PE_SHIFT                     (1U)
72000 /*! PE - Parity Enable
72001  *  0b0..No hardware parity generation or checking.
72002  *  0b1..Parity enabled.
72003  */
72004 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
72005 
72006 #define LPUART_CTRL_ILT_MASK                     (0x4U)
72007 #define LPUART_CTRL_ILT_SHIFT                    (2U)
72008 /*! ILT - Idle Line Type Select
72009  *  0b0..Idle character bit count starts after start bit.
72010  *  0b1..Idle character bit count starts after stop bit.
72011  */
72012 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
72013 
72014 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
72015 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
72016 /*! WAKE - Receiver Wakeup Method Select
72017  *  0b0..Configures RWU for idle-line wakeup.
72018  *  0b1..Configures RWU with address-mark wakeup.
72019  */
72020 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
72021 
72022 #define LPUART_CTRL_M_MASK                       (0x10U)
72023 #define LPUART_CTRL_M_SHIFT                      (4U)
72024 /*! M - 9-Bit or 8-Bit Mode Select
72025  *  0b0..Receiver and transmitter use 8-bit data characters.
72026  *  0b1..Receiver and transmitter use 9-bit data characters.
72027  */
72028 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
72029 
72030 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
72031 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
72032 /*! RSRC - Receiver Source Select
72033  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
72034  *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
72035  */
72036 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
72037 
72038 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
72039 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
72040 /*! DOZEEN - Doze Enable
72041  *  0b0..LPUART is enabled in Doze mode.
72042  *  0b1..LPUART is disabled in Doze mode .
72043  */
72044 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
72045 
72046 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
72047 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
72048 /*! LOOPS - Loop Mode Select
72049  *  0b0..Normal operation - RXD and TXD use separate pins.
72050  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
72051  */
72052 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
72053 
72054 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
72055 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
72056 /*! IDLECFG - Idle Configuration
72057  *  0b000..1 idle character
72058  *  0b001..2 idle characters
72059  *  0b010..4 idle characters
72060  *  0b011..8 idle characters
72061  *  0b100..16 idle characters
72062  *  0b101..32 idle characters
72063  *  0b110..64 idle characters
72064  *  0b111..128 idle characters
72065  */
72066 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
72067 
72068 #define LPUART_CTRL_M7_MASK                      (0x800U)
72069 #define LPUART_CTRL_M7_SHIFT                     (11U)
72070 /*! M7 - 7-Bit Mode Select
72071  *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
72072  *  0b1..Receiver and transmitter use 7-bit data characters.
72073  */
72074 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
72075 
72076 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
72077 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
72078 /*! MA2IE - Match 2 Interrupt Enable
72079  *  0b0..MA2F interrupt disabled
72080  *  0b1..MA2F interrupt enabled
72081  */
72082 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
72083 
72084 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
72085 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
72086 /*! MA1IE - Match 1 Interrupt Enable
72087  *  0b0..MA1F interrupt disabled
72088  *  0b1..MA1F interrupt enabled
72089  */
72090 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
72091 
72092 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
72093 #define LPUART_CTRL_SBK_SHIFT                    (16U)
72094 /*! SBK - Send Break
72095  *  0b0..Normal transmitter operation.
72096  *  0b1..Queue break character(s) to be sent.
72097  */
72098 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
72099 
72100 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
72101 #define LPUART_CTRL_RWU_SHIFT                    (17U)
72102 /*! RWU - Receiver Wakeup Control
72103  *  0b0..Normal receiver operation.
72104  *  0b1..LPUART receiver in standby waiting for wakeup condition.
72105  */
72106 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
72107 
72108 #define LPUART_CTRL_RE_MASK                      (0x40000U)
72109 #define LPUART_CTRL_RE_SHIFT                     (18U)
72110 /*! RE - Receiver Enable
72111  *  0b0..Receiver disabled.
72112  *  0b1..Receiver enabled.
72113  */
72114 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
72115 
72116 #define LPUART_CTRL_TE_MASK                      (0x80000U)
72117 #define LPUART_CTRL_TE_SHIFT                     (19U)
72118 /*! TE - Transmitter Enable
72119  *  0b0..Transmitter disabled.
72120  *  0b1..Transmitter enabled.
72121  */
72122 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
72123 
72124 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
72125 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
72126 /*! ILIE - Idle Line Interrupt Enable
72127  *  0b0..Hardware interrupts from IDLE disabled; use polling.
72128  *  0b1..Hardware interrupt is requested when IDLE flag is 1.
72129  */
72130 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
72131 
72132 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
72133 #define LPUART_CTRL_RIE_SHIFT                    (21U)
72134 /*! RIE - Receiver Interrupt Enable
72135  *  0b0..Hardware interrupts from RDRF disabled.
72136  *  0b1..Hardware interrupt is requested when RDRF flag is 1.
72137  */
72138 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
72139 
72140 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
72141 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
72142 /*! TCIE - Transmission Complete Interrupt Enable for
72143  *  0b0..Hardware interrupts from TC disabled.
72144  *  0b1..Hardware interrupt is requested when TC flag is 1.
72145  */
72146 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
72147 
72148 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
72149 #define LPUART_CTRL_TIE_SHIFT                    (23U)
72150 /*! TIE - Transmit Interrupt Enable
72151  *  0b0..Hardware interrupts from TDRE disabled.
72152  *  0b1..Hardware interrupt is requested when TDRE flag is 1.
72153  */
72154 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
72155 
72156 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
72157 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
72158 /*! PEIE - Parity Error Interrupt Enable
72159  *  0b0..PF interrupts disabled; use polling).
72160  *  0b1..Hardware interrupt is requested when PF is set.
72161  */
72162 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
72163 
72164 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
72165 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
72166 /*! FEIE - Framing Error Interrupt Enable
72167  *  0b0..FE interrupts disabled; use polling.
72168  *  0b1..Hardware interrupt is requested when FE is set.
72169  */
72170 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
72171 
72172 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
72173 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
72174 /*! NEIE - Noise Error Interrupt Enable
72175  *  0b0..NF interrupts disabled; use polling.
72176  *  0b1..Hardware interrupt is requested when NF is set.
72177  */
72178 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
72179 
72180 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
72181 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
72182 /*! ORIE - Overrun Interrupt Enable
72183  *  0b0..OR interrupts disabled; use polling.
72184  *  0b1..Hardware interrupt is requested when OR is set.
72185  */
72186 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
72187 
72188 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
72189 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
72190 /*! TXINV - Transmit Data Inversion
72191  *  0b0..Transmit data not inverted.
72192  *  0b1..Transmit data inverted.
72193  */
72194 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
72195 
72196 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
72197 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
72198 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
72199  *  0b0..TXD pin is an input in single-wire mode.
72200  *  0b1..TXD pin is an output in single-wire mode.
72201  */
72202 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
72203 
72204 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
72205 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
72206 /*! R9T8 - Receive Bit 9 / Transmit Bit 8
72207  */
72208 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
72209 
72210 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
72211 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
72212 /*! R8T9 - Receive Bit 8 / Transmit Bit 9
72213  */
72214 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
72215 /*! @} */
72216 
72217 /*! @name DATA - LPUART Data Register */
72218 /*! @{ */
72219 
72220 #define LPUART_DATA_R0T0_MASK                    (0x1U)
72221 #define LPUART_DATA_R0T0_SHIFT                   (0U)
72222 /*! R0T0 - R0T0
72223  */
72224 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
72225 
72226 #define LPUART_DATA_R1T1_MASK                    (0x2U)
72227 #define LPUART_DATA_R1T1_SHIFT                   (1U)
72228 /*! R1T1 - R1T1
72229  */
72230 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
72231 
72232 #define LPUART_DATA_R2T2_MASK                    (0x4U)
72233 #define LPUART_DATA_R2T2_SHIFT                   (2U)
72234 /*! R2T2 - R2T2
72235  */
72236 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
72237 
72238 #define LPUART_DATA_R3T3_MASK                    (0x8U)
72239 #define LPUART_DATA_R3T3_SHIFT                   (3U)
72240 /*! R3T3 - R3T3
72241  */
72242 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
72243 
72244 #define LPUART_DATA_R4T4_MASK                    (0x10U)
72245 #define LPUART_DATA_R4T4_SHIFT                   (4U)
72246 /*! R4T4 - R4T4
72247  */
72248 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
72249 
72250 #define LPUART_DATA_R5T5_MASK                    (0x20U)
72251 #define LPUART_DATA_R5T5_SHIFT                   (5U)
72252 /*! R5T5 - R5T5
72253  */
72254 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
72255 
72256 #define LPUART_DATA_R6T6_MASK                    (0x40U)
72257 #define LPUART_DATA_R6T6_SHIFT                   (6U)
72258 /*! R6T6 - R6T6
72259  */
72260 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
72261 
72262 #define LPUART_DATA_R7T7_MASK                    (0x80U)
72263 #define LPUART_DATA_R7T7_SHIFT                   (7U)
72264 /*! R7T7 - R7T7
72265  */
72266 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
72267 
72268 #define LPUART_DATA_R8T8_MASK                    (0x100U)
72269 #define LPUART_DATA_R8T8_SHIFT                   (8U)
72270 /*! R8T8 - R8T8
72271  */
72272 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
72273 
72274 #define LPUART_DATA_R9T9_MASK                    (0x200U)
72275 #define LPUART_DATA_R9T9_SHIFT                   (9U)
72276 /*! R9T9 - R9T9
72277  */
72278 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
72279 
72280 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
72281 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
72282 /*! IDLINE - Idle Line
72283  *  0b0..Receiver was not idle before receiving this character.
72284  *  0b1..Receiver was idle before receiving this character.
72285  */
72286 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
72287 
72288 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
72289 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
72290 /*! RXEMPT - Receive Buffer Empty
72291  *  0b0..Receive buffer contains valid data.
72292  *  0b1..Receive buffer is empty, data returned on read is not valid.
72293  */
72294 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
72295 
72296 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
72297 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
72298 /*! FRETSC - Frame Error / Transmit Special Character
72299  *  0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
72300  *  0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
72301  */
72302 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
72303 
72304 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
72305 #define LPUART_DATA_PARITYE_SHIFT                (14U)
72306 /*! PARITYE - Parity Error
72307  *  0b0..The dataword is received without a parity error.
72308  *  0b1..The dataword is received with a parity error.
72309  */
72310 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
72311 
72312 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
72313 #define LPUART_DATA_NOISY_SHIFT                  (15U)
72314 /*! NOISY - Noisy Data Received
72315  *  0b0..The dataword is received without noise.
72316  *  0b1..The data is received with noise.
72317  */
72318 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
72319 /*! @} */
72320 
72321 /*! @name MATCH - LPUART Match Address Register */
72322 /*! @{ */
72323 
72324 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
72325 #define LPUART_MATCH_MA1_SHIFT                   (0U)
72326 /*! MA1 - Match Address 1
72327  */
72328 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
72329 
72330 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
72331 #define LPUART_MATCH_MA2_SHIFT                   (16U)
72332 /*! MA2 - Match Address 2
72333  */
72334 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
72335 /*! @} */
72336 
72337 /*! @name MODIR - LPUART Modem IrDA Register */
72338 /*! @{ */
72339 
72340 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
72341 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
72342 /*! TXCTSE - Transmitter clear-to-send enable
72343  *  0b0..CTS has no effect on the transmitter.
72344  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
72345  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
72346  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
72347  *       do not affect its transmission.
72348  */
72349 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
72350 
72351 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
72352 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
72353 /*! TXRTSE - Transmitter request-to-send enable
72354  *  0b0..The transmitter has no effect on RTS.
72355  *  0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
72356  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
72357  *       register are completely sent, including the last stop bit.
72358  */
72359 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
72360 
72361 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
72362 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
72363 /*! TXRTSPOL - Transmitter request-to-send polarity
72364  *  0b0..Transmitter RTS is active low.
72365  *  0b1..Transmitter RTS is active high.
72366  */
72367 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
72368 
72369 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
72370 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
72371 /*! RXRTSE - Receiver request-to-send enable
72372  *  0b0..The receiver has no effect on RTS.
72373  *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
72374  *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
72375  *       has not detected a start bit that would cause the receiver data register to become full.
72376  */
72377 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
72378 
72379 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
72380 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
72381 /*! TXCTSC - Transmit CTS Configuration
72382  *  0b0..CTS input is sampled at the start of each character.
72383  *  0b1..CTS input is sampled when the transmitter is idle.
72384  */
72385 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
72386 
72387 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
72388 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
72389 /*! TXCTSSRC - Transmit CTS Source
72390  *  0b0..CTS input is the CTS_B pin.
72391  *  0b1..CTS input is an internal connection to the receiver address match result.
72392  */
72393 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
72394 
72395 #define LPUART_MODIR_RTSWATER_MASK               (0x300U)
72396 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
72397 /*! RTSWATER - Receive RTS Configuration
72398  */
72399 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
72400 
72401 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
72402 #define LPUART_MODIR_TNP_SHIFT                   (16U)
72403 /*! TNP - Transmitter narrow pulse
72404  *  0b00..1/OSR.
72405  *  0b01..2/OSR.
72406  *  0b10..3/OSR.
72407  *  0b11..4/OSR.
72408  */
72409 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
72410 
72411 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
72412 #define LPUART_MODIR_IREN_SHIFT                  (18U)
72413 /*! IREN - Infrared enable
72414  *  0b0..IR disabled.
72415  *  0b1..IR enabled.
72416  */
72417 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
72418 /*! @} */
72419 
72420 /*! @name FIFO - LPUART FIFO Register */
72421 /*! @{ */
72422 
72423 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
72424 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
72425 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
72426  *  0b000..Receive FIFO/Buffer depth = 1 dataword.
72427  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
72428  *  0b010..Receive FIFO/Buffer depth = 8 datawords.
72429  *  0b011..Receive FIFO/Buffer depth = 16 datawords.
72430  *  0b100..Receive FIFO/Buffer depth = 32 datawords.
72431  *  0b101..Receive FIFO/Buffer depth = 64 datawords.
72432  *  0b110..Receive FIFO/Buffer depth = 128 datawords.
72433  *  0b111..Receive FIFO/Buffer depth = 256 datawords.
72434  */
72435 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
72436 
72437 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
72438 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
72439 /*! RXFE - Receive FIFO Enable
72440  *  0b0..Receive FIFO is not enabled. Buffer depth is 1.
72441  *  0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
72442  */
72443 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
72444 
72445 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
72446 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
72447 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
72448  *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
72449  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
72450  *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
72451  *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
72452  *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
72453  *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
72454  *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
72455  *  0b111..Transmit FIFO/Buffer depth = 256 datawords
72456  */
72457 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
72458 
72459 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
72460 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
72461 /*! TXFE - Transmit FIFO Enable
72462  *  0b0..Transmit FIFO is not enabled. Buffer depth is 1.
72463  *  0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
72464  */
72465 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
72466 
72467 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
72468 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
72469 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
72470  *  0b0..RXUF flag does not generate an interrupt to the host.
72471  *  0b1..RXUF flag generates an interrupt to the host.
72472  */
72473 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
72474 
72475 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
72476 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
72477 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
72478  *  0b0..TXOF flag does not generate an interrupt to the host.
72479  *  0b1..TXOF flag generates an interrupt to the host.
72480  */
72481 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
72482 
72483 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
72484 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
72485 /*! RXIDEN - Receiver Idle Empty Enable
72486  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
72487  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
72488  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
72489  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
72490  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
72491  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
72492  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
72493  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
72494  */
72495 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
72496 
72497 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
72498 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
72499 /*! RXFLUSH - Receive FIFO Flush
72500  *  0b0..No flush operation occurs.
72501  *  0b1..All data in the receive FIFO/buffer is cleared out.
72502  */
72503 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
72504 
72505 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
72506 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
72507 /*! TXFLUSH - Transmit FIFO Flush
72508  *  0b0..No flush operation occurs.
72509  *  0b1..All data in the transmit FIFO is cleared out.
72510  */
72511 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
72512 
72513 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
72514 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
72515 /*! RXUF - Receiver FIFO Underflow Flag
72516  *  0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
72517  *  0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
72518  */
72519 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
72520 
72521 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
72522 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
72523 /*! TXOF - Transmitter FIFO Overflow Flag
72524  *  0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
72525  *  0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
72526  */
72527 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
72528 
72529 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
72530 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
72531 /*! RXEMPT - Receive FIFO/Buffer Empty
72532  *  0b0..Receive buffer is not empty.
72533  *  0b1..Receive buffer is empty.
72534  */
72535 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
72536 
72537 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
72538 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
72539 /*! TXEMPT - Transmit FIFO/Buffer Empty
72540  *  0b0..Transmit buffer is not empty.
72541  *  0b1..Transmit buffer is empty.
72542  */
72543 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
72544 /*! @} */
72545 
72546 /*! @name WATER - LPUART Watermark Register */
72547 /*! @{ */
72548 
72549 #define LPUART_WATER_TXWATER_MASK                (0x3U)
72550 #define LPUART_WATER_TXWATER_SHIFT               (0U)
72551 /*! TXWATER - Transmit Watermark
72552  */
72553 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
72554 
72555 #define LPUART_WATER_TXCOUNT_MASK                (0x700U)
72556 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
72557 /*! TXCOUNT - Transmit Counter
72558  */
72559 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
72560 
72561 #define LPUART_WATER_RXWATER_MASK                (0x30000U)
72562 #define LPUART_WATER_RXWATER_SHIFT               (16U)
72563 /*! RXWATER - Receive Watermark
72564  */
72565 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
72566 
72567 #define LPUART_WATER_RXCOUNT_MASK                (0x7000000U)
72568 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
72569 /*! RXCOUNT - Receive Counter
72570  */
72571 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
72572 /*! @} */
72573 
72574 
72575 /*!
72576  * @}
72577  */ /* end of group LPUART_Register_Masks */
72578 
72579 
72580 /* LPUART - Peripheral instance base addresses */
72581 /** Peripheral LPUART1 base address */
72582 #define LPUART1_BASE                             (0x4007C000u)
72583 /** Peripheral LPUART1 base pointer */
72584 #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
72585 /** Peripheral LPUART2 base address */
72586 #define LPUART2_BASE                             (0x40080000u)
72587 /** Peripheral LPUART2 base pointer */
72588 #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
72589 /** Peripheral LPUART3 base address */
72590 #define LPUART3_BASE                             (0x40084000u)
72591 /** Peripheral LPUART3 base pointer */
72592 #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
72593 /** Peripheral LPUART4 base address */
72594 #define LPUART4_BASE                             (0x40088000u)
72595 /** Peripheral LPUART4 base pointer */
72596 #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
72597 /** Peripheral LPUART5 base address */
72598 #define LPUART5_BASE                             (0x4008C000u)
72599 /** Peripheral LPUART5 base pointer */
72600 #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
72601 /** Peripheral LPUART6 base address */
72602 #define LPUART6_BASE                             (0x40090000u)
72603 /** Peripheral LPUART6 base pointer */
72604 #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
72605 /** Peripheral LPUART7 base address */
72606 #define LPUART7_BASE                             (0x40094000u)
72607 /** Peripheral LPUART7 base pointer */
72608 #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
72609 /** Peripheral LPUART8 base address */
72610 #define LPUART8_BASE                             (0x40098000u)
72611 /** Peripheral LPUART8 base pointer */
72612 #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
72613 /** Peripheral LPUART9 base address */
72614 #define LPUART9_BASE                             (0x4009C000u)
72615 /** Peripheral LPUART9 base pointer */
72616 #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
72617 /** Peripheral LPUART10 base address */
72618 #define LPUART10_BASE                            (0x400A0000u)
72619 /** Peripheral LPUART10 base pointer */
72620 #define LPUART10                                 ((LPUART_Type *)LPUART10_BASE)
72621 /** Peripheral LPUART11 base address */
72622 #define LPUART11_BASE                            (0x40C24000u)
72623 /** Peripheral LPUART11 base pointer */
72624 #define LPUART11                                 ((LPUART_Type *)LPUART11_BASE)
72625 /** Peripheral LPUART12 base address */
72626 #define LPUART12_BASE                            (0x40C28000u)
72627 /** Peripheral LPUART12 base pointer */
72628 #define LPUART12                                 ((LPUART_Type *)LPUART12_BASE)
72629 /** Array initializer of LPUART peripheral base addresses */
72630 #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
72631 /** Array initializer of LPUART peripheral base pointers */
72632 #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
72633 /** Interrupt vectors for the LPUART peripheral type */
72634 #define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
72635 
72636 /*!
72637  * @}
72638  */ /* end of group LPUART_Peripheral_Access_Layer */
72639 
72640 
72641 /* ----------------------------------------------------------------------------
72642    -- MCM Peripheral Access Layer
72643    ---------------------------------------------------------------------------- */
72644 
72645 /*!
72646  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
72647  * @{
72648  */
72649 
72650 /** MCM - Register Layout Typedef */
72651 typedef struct {
72652        uint8_t RESERVED_0[16];
72653   __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
72654 } MCM_Type;
72655 
72656 /* ----------------------------------------------------------------------------
72657    -- MCM Register Masks
72658    ---------------------------------------------------------------------------- */
72659 
72660 /*!
72661  * @addtogroup MCM_Register_Masks MCM Register Masks
72662  * @{
72663  */
72664 
72665 /*! @name ISCR - Interrupt Status and Control Register */
72666 /*! @{ */
72667 
72668 #define MCM_ISCR_WABS_MASK                       (0x20U)
72669 #define MCM_ISCR_WABS_SHIFT                      (5U)
72670 /*! WABS - Write Abort on Slave
72671  *  0b0..No abort
72672  *  0b1..Abort
72673  */
72674 #define MCM_ISCR_WABS(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)
72675 
72676 #define MCM_ISCR_WABSO_MASK                      (0x40U)
72677 #define MCM_ISCR_WABSO_SHIFT                     (6U)
72678 /*! WABSO - Write Abort on Slave Overrun
72679  *  0b0..No write abort overrun
72680  *  0b1..Write abort overrun occurred
72681  */
72682 #define MCM_ISCR_WABSO(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)
72683 
72684 #define MCM_ISCR_FIOC_MASK                       (0x100U)
72685 #define MCM_ISCR_FIOC_SHIFT                      (8U)
72686 /*! FIOC - FPU Invalid Operation interrupt Status
72687  *  0b0..No interrupt
72688  *  0b1..Interrupt occured
72689  */
72690 #define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
72691 
72692 #define MCM_ISCR_FDZC_MASK                       (0x200U)
72693 #define MCM_ISCR_FDZC_SHIFT                      (9U)
72694 /*! FDZC - FPU Divide-by-Zero Interrupt Status
72695  *  0b0..No interrupt
72696  *  0b1..Interrupt occured
72697  */
72698 #define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
72699 
72700 #define MCM_ISCR_FOFC_MASK                       (0x400U)
72701 #define MCM_ISCR_FOFC_SHIFT                      (10U)
72702 /*! FOFC - FPU Overflow interrupt status
72703  *  0b0..No interrupt
72704  *  0b1..Interrupt occured
72705  */
72706 #define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
72707 
72708 #define MCM_ISCR_FUFC_MASK                       (0x800U)
72709 #define MCM_ISCR_FUFC_SHIFT                      (11U)
72710 /*! FUFC - FPU Underflow Interrupt Status
72711  *  0b0..No interrupt
72712  *  0b1..Interrupt occured
72713  */
72714 #define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
72715 
72716 #define MCM_ISCR_FIXC_MASK                       (0x1000U)
72717 #define MCM_ISCR_FIXC_SHIFT                      (12U)
72718 /*! FIXC - FPU Inexact Interrupt Status
72719  *  0b0..No interrupt
72720  *  0b1..Interrupt occured
72721  */
72722 #define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
72723 
72724 #define MCM_ISCR_FIDC_MASK                       (0x8000U)
72725 #define MCM_ISCR_FIDC_SHIFT                      (15U)
72726 /*! FIDC - FPU Input Denormal Interrupt Status
72727  *  0b0..No interrupt
72728  *  0b1..Interrupt occured
72729  */
72730 #define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
72731 
72732 #define MCM_ISCR_WABE_MASK                       (0x200000U)
72733 #define MCM_ISCR_WABE_SHIFT                      (21U)
72734 /*! WABE - TCM Write Abort Interrupt enable
72735  *  0b0..Disable interrupt
72736  *  0b1..Enable interrupt
72737  */
72738 #define MCM_ISCR_WABE(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)
72739 
72740 #define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
72741 #define MCM_ISCR_FIOCE_SHIFT                     (24U)
72742 /*! FIOCE - FPU Invalid Operation Interrupt Enable
72743  *  0b0..Disable interrupt
72744  *  0b1..Enable interrupt
72745  */
72746 #define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
72747 
72748 #define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
72749 #define MCM_ISCR_FDZCE_SHIFT                     (25U)
72750 /*! FDZCE - FPU Divide-by-Zero Interrupt Enable
72751  *  0b0..Disable interrupt
72752  *  0b1..Enable interrupt
72753  */
72754 #define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
72755 
72756 #define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
72757 #define MCM_ISCR_FOFCE_SHIFT                     (26U)
72758 /*! FOFCE - FPU Overflow Interrupt Enable
72759  *  0b0..Disable interrupt
72760  *  0b1..Enable interrupt
72761  */
72762 #define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
72763 
72764 #define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
72765 #define MCM_ISCR_FUFCE_SHIFT                     (27U)
72766 /*! FUFCE - FPU Underflow Interrupt Enable
72767  *  0b0..Disable interrupt
72768  *  0b1..Enable interrupt
72769  */
72770 #define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
72771 
72772 #define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
72773 #define MCM_ISCR_FIXCE_SHIFT                     (28U)
72774 /*! FIXCE - FPU Inexact Interrupt Enable
72775  *  0b0..Disable interrupt
72776  *  0b1..Enable interrupt
72777  */
72778 #define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
72779 
72780 #define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
72781 #define MCM_ISCR_FIDCE_SHIFT                     (31U)
72782 /*! FIDCE - FPU Input Denormal Interrupt Enable
72783  *  0b0..Disable interrupt
72784  *  0b1..Enable interrupt
72785  */
72786 #define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
72787 /*! @} */
72788 
72789 
72790 /*!
72791  * @}
72792  */ /* end of group MCM_Register_Masks */
72793 
72794 
72795 /* MCM - Peripheral instance base addresses */
72796 /** Peripheral CM7_MCM base address */
72797 #define CM7_MCM_BASE                             (0xE0080000u)
72798 /** Peripheral CM7_MCM base pointer */
72799 #define CM7_MCM                                  ((MCM_Type *)CM7_MCM_BASE)
72800 /** Array initializer of MCM peripheral base addresses */
72801 #define MCM_BASE_ADDRS                           { CM7_MCM_BASE }
72802 /** Array initializer of MCM peripheral base pointers */
72803 #define MCM_BASE_PTRS                            { CM7_MCM }
72804 
72805 /*!
72806  * @}
72807  */ /* end of group MCM_Peripheral_Access_Layer */
72808 
72809 
72810 /* ----------------------------------------------------------------------------
72811    -- MECC Peripheral Access Layer
72812    ---------------------------------------------------------------------------- */
72813 
72814 /*!
72815  * @addtogroup MECC_Peripheral_Access_Layer MECC Peripheral Access Layer
72816  * @{
72817  */
72818 
72819 /** MECC - Register Layout Typedef */
72820 typedef struct {
72821   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x0 */
72822   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x4 */
72823   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0x8 */
72824   __IO uint32_t ERR_DATA_INJ_LOW0;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */
72825   __IO uint32_t ERR_DATA_INJ_HIGH0;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */
72826   __IO uint32_t ERR_ECC_INJ0;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */
72827   __IO uint32_t ERR_DATA_INJ_LOW1;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */
72828   __IO uint32_t ERR_DATA_INJ_HIGH1;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */
72829   __IO uint32_t ERR_ECC_INJ1;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */
72830   __IO uint32_t ERR_DATA_INJ_LOW2;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */
72831   __IO uint32_t ERR_DATA_INJ_HIGH2;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */
72832   __IO uint32_t ERR_ECC_INJ2;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */
72833   __IO uint32_t ERR_DATA_INJ_LOW3;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */
72834   __IO uint32_t ERR_DATA_INJ_HIGH3;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */
72835   __IO uint32_t ERR_ECC_INJ3;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */
72836   __I  uint32_t SINGLE_ERR_ADDR_ECC0;              /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */
72837   __I  uint32_t SINGLE_ERR_DATA_LOW0;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */
72838   __I  uint32_t SINGLE_ERR_DATA_HIGH0;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */
72839   __I  uint32_t SINGLE_ERR_POS_LOW0;               /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */
72840   __I  uint32_t SINGLE_ERR_POS_HIGH0;              /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */
72841   __I  uint32_t SINGLE_ERR_ADDR_ECC1;              /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */
72842   __I  uint32_t SINGLE_ERR_DATA_LOW1;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */
72843   __I  uint32_t SINGLE_ERR_DATA_HIGH1;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */
72844   __I  uint32_t SINGLE_ERR_POS_LOW1;               /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */
72845   __I  uint32_t SINGLE_ERR_POS_HIGH1;              /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */
72846   __I  uint32_t SINGLE_ERR_ADDR_ECC2;              /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */
72847   __I  uint32_t SINGLE_ERR_DATA_LOW2;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */
72848   __I  uint32_t SINGLE_ERR_DATA_HIGH2;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */
72849   __I  uint32_t SINGLE_ERR_POS_LOW2;               /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */
72850   __I  uint32_t SINGLE_ERR_POS_HIGH2;              /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */
72851   __I  uint32_t SINGLE_ERR_ADDR_ECC3;              /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */
72852   __I  uint32_t SINGLE_ERR_DATA_LOW3;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */
72853   __I  uint32_t SINGLE_ERR_DATA_HIGH3;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */
72854   __I  uint32_t SINGLE_ERR_POS_LOW3;               /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */
72855   __I  uint32_t SINGLE_ERR_POS_HIGH3;              /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */
72856   __I  uint32_t MULTI_ERR_ADDR_ECC0;               /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */
72857   __I  uint32_t MULTI_ERR_DATA_LOW0;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */
72858   __I  uint32_t MULTI_ERR_DATA_HIGH0;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */
72859   __I  uint32_t MULTI_ERR_ADDR_ECC1;               /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */
72860   __I  uint32_t MULTI_ERR_DATA_LOW1;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */
72861   __I  uint32_t MULTI_ERR_DATA_HIGH1;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */
72862   __I  uint32_t MULTI_ERR_ADDR_ECC2;               /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */
72863   __I  uint32_t MULTI_ERR_DATA_LOW2;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */
72864   __I  uint32_t MULTI_ERR_DATA_HIGH2;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */
72865   __I  uint32_t MULTI_ERR_ADDR_ECC3;               /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */
72866   __I  uint32_t MULTI_ERR_DATA_LOW3;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */
72867   __I  uint32_t MULTI_ERR_DATA_HIGH3;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */
72868        uint8_t RESERVED_0[68];
72869   __IO uint32_t PIPE_ECC_EN;                       /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */
72870   __I  uint32_t PENDING_STAT;                      /**< Pending Status, offset: 0x104 */
72871 } MECC_Type;
72872 
72873 /* ----------------------------------------------------------------------------
72874    -- MECC Register Masks
72875    ---------------------------------------------------------------------------- */
72876 
72877 /*!
72878  * @addtogroup MECC_Register_Masks MECC Register Masks
72879  * @{
72880  */
72881 
72882 /*! @name ERR_STATUS - Error Interrupt Status Register */
72883 /*! @{ */
72884 
72885 #define MECC_ERR_STATUS_SINGLE_ERR0_MASK         (0x1U)
72886 #define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT        (0U)
72887 /*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0
72888  *  0b0..Single bit error does not happen on OCRAM bank0.
72889  *  0b1..Single bit error happens on OCRAM bank0.
72890  */
72891 #define MECC_ERR_STATUS_SINGLE_ERR0(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
72892 
72893 #define MECC_ERR_STATUS_SINGLE_ERR1_MASK         (0x2U)
72894 #define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT        (1U)
72895 /*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1
72896  *  0b0..Single bit error does not happen on OCRAM bank1.
72897  *  0b1..Single bit error happens on OCRAM bank1.
72898  */
72899 #define MECC_ERR_STATUS_SINGLE_ERR1(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
72900 
72901 #define MECC_ERR_STATUS_SINGLE_ERR2_MASK         (0x4U)
72902 #define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT        (2U)
72903 /*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2
72904  *  0b0..Single bit error does not happen on OCRAM bank2.
72905  *  0b1..Single bit error happens on OCRAM bank2.
72906  */
72907 #define MECC_ERR_STATUS_SINGLE_ERR2(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
72908 
72909 #define MECC_ERR_STATUS_SINGLE_ERR3_MASK         (0x8U)
72910 #define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT        (3U)
72911 /*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3
72912  *  0b0..Single bit error does not happen on OCRAM bank3.
72913  *  0b1..Single bit error happens on OCRAM bank3.
72914  */
72915 #define MECC_ERR_STATUS_SINGLE_ERR3(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
72916 
72917 #define MECC_ERR_STATUS_MULTI_ERR0_MASK          (0x10U)
72918 #define MECC_ERR_STATUS_MULTI_ERR0_SHIFT         (4U)
72919 /*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0
72920  *  0b0..Multiple bits error does not happen on OCRAM bank0.
72921  *  0b1..Multiple bits error happens on OCRAM bank0.
72922  */
72923 #define MECC_ERR_STATUS_MULTI_ERR0(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
72924 
72925 #define MECC_ERR_STATUS_MULTI_ERR1_MASK          (0x20U)
72926 #define MECC_ERR_STATUS_MULTI_ERR1_SHIFT         (5U)
72927 /*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1
72928  *  0b0..Multiple bits error does not happen on OCRAM bank1.
72929  *  0b1..Multiple bits error happens on OCRAM bank1.
72930  */
72931 #define MECC_ERR_STATUS_MULTI_ERR1(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
72932 
72933 #define MECC_ERR_STATUS_MULTI_ERR2_MASK          (0x40U)
72934 #define MECC_ERR_STATUS_MULTI_ERR2_SHIFT         (6U)
72935 /*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2
72936  *  0b0..Multiple bits error does not happen on OCRAM bank2.
72937  *  0b1..Multiple bits error happens on OCRAM bank2.
72938  */
72939 #define MECC_ERR_STATUS_MULTI_ERR2(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
72940 
72941 #define MECC_ERR_STATUS_MULTI_ERR3_MASK          (0x80U)
72942 #define MECC_ERR_STATUS_MULTI_ERR3_SHIFT         (7U)
72943 /*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3
72944  *  0b0..Multiple bits error does not happen on OCRAM bank3.
72945  *  0b1..Multiple bits error happens on OCRAM bank3.
72946  */
72947 #define MECC_ERR_STATUS_MULTI_ERR3(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
72948 
72949 #define MECC_ERR_STATUS_STRB_ERR0_MASK           (0x100U)
72950 #define MECC_ERR_STATUS_STRB_ERR0_SHIFT          (8U)
72951 /*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0
72952  *  0b0..AXI strobe error does not happen on OCRAM bank0.
72953  *  0b1..AXI strobe error happens on OCRAM bank0.
72954  */
72955 #define MECC_ERR_STATUS_STRB_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
72956 
72957 #define MECC_ERR_STATUS_STRB_ERR1_MASK           (0x200U)
72958 #define MECC_ERR_STATUS_STRB_ERR1_SHIFT          (9U)
72959 /*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1
72960  *  0b0..AXI strobe error does not happen on OCRAM bank1.
72961  *  0b1..AXI strobe error happens on OCRAM bank1.
72962  */
72963 #define MECC_ERR_STATUS_STRB_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
72964 
72965 #define MECC_ERR_STATUS_STRB_ERR2_MASK           (0x400U)
72966 #define MECC_ERR_STATUS_STRB_ERR2_SHIFT          (10U)
72967 /*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2
72968  *  0b0..AXI strobe error does not happen on OCRAM bank2.
72969  *  0b1..AXI strobe error happens on OCRAM bank2.
72970  */
72971 #define MECC_ERR_STATUS_STRB_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
72972 
72973 #define MECC_ERR_STATUS_STRB_ERR3_MASK           (0x800U)
72974 #define MECC_ERR_STATUS_STRB_ERR3_SHIFT          (11U)
72975 /*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3
72976  *  0b0..AXI strobe error does not happen on OCRAM bank3.
72977  *  0b1..AXI strobe error happens on OCRAM bank3.
72978  */
72979 #define MECC_ERR_STATUS_STRB_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
72980 
72981 #define MECC_ERR_STATUS_ADDR_ERR0_MASK           (0x1000U)
72982 #define MECC_ERR_STATUS_ADDR_ERR0_SHIFT          (12U)
72983 /*! ADDR_ERR0 - OCRAM Access Error On Bank0
72984  *  0b0..OCRAM access error does not happen on OCRAM bank0.
72985  *  0b1..OCRAM access error happens on OCRAM bank0.
72986  */
72987 #define MECC_ERR_STATUS_ADDR_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
72988 
72989 #define MECC_ERR_STATUS_ADDR_ERR1_MASK           (0x2000U)
72990 #define MECC_ERR_STATUS_ADDR_ERR1_SHIFT          (13U)
72991 /*! ADDR_ERR1 - OCRAM Access Error On Bank1
72992  *  0b0..OCRAM access error does not happen on OCRAM bank1.
72993  *  0b1..OCRAM access error happens on OCRAM bank1.
72994  */
72995 #define MECC_ERR_STATUS_ADDR_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
72996 
72997 #define MECC_ERR_STATUS_ADDR_ERR2_MASK           (0x4000U)
72998 #define MECC_ERR_STATUS_ADDR_ERR2_SHIFT          (14U)
72999 /*! ADDR_ERR2 - OCRAM Access Error On Bank2
73000  *  0b0..OCRAM access error does not happen on OCRAM bank2.
73001  *  0b1..OCRAM access error happens on OCRAM bank2.
73002  */
73003 #define MECC_ERR_STATUS_ADDR_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
73004 
73005 #define MECC_ERR_STATUS_ADDR_ERR3_MASK           (0x8000U)
73006 #define MECC_ERR_STATUS_ADDR_ERR3_SHIFT          (15U)
73007 /*! ADDR_ERR3 - OCRAM Access Error On Bank3
73008  *  0b0..OCRAM access error does not happen on OCRAM bank3.
73009  *  0b1..OCRAM access error happens on OCRAM bank3.
73010  */
73011 #define MECC_ERR_STATUS_ADDR_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
73012 /*! @} */
73013 
73014 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
73015 /*! @{ */
73016 
73017 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
73018 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
73019 /*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0
73020  *  0b0..Disabled
73021  *  0b1..Enabled
73022  */
73023 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
73024 
73025 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
73026 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
73027 /*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1
73028  *  0b0..Disabled
73029  *  0b1..Enabled
73030  */
73031 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
73032 
73033 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
73034 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
73035 /*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2
73036  *  0b0..Disabled
73037  *  0b1..Enabled
73038  */
73039 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
73040 
73041 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
73042 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
73043 /*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3
73044  *  0b0..Disabled
73045  *  0b1..Enabled
73046  */
73047 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
73048 
73049 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
73050 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
73051 /*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0
73052  *  0b0..Disabled
73053  *  0b1..Enabled
73054  */
73055 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
73056 
73057 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
73058 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
73059 /*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1
73060  *  0b0..Disabled
73061  *  0b1..Enabled
73062  */
73063 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
73064 
73065 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
73066 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
73067 /*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2
73068  *  0b0..Disabled
73069  *  0b1..Enabled
73070  */
73071 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
73072 
73073 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
73074 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
73075 /*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3
73076  *  0b0..Disabled
73077  *  0b1..Enabled
73078  */
73079 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
73080 
73081 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK  (0x100U)
73082 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
73083 /*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0
73084  *  0b0..Disabled
73085  *  0b1..Enabled
73086  */
73087 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
73088 
73089 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK  (0x200U)
73090 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
73091 /*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1
73092  *  0b0..Disabled
73093  *  0b1..Enabled
73094  */
73095 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
73096 
73097 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK  (0x400U)
73098 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
73099 /*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2
73100  *  0b0..Disabled
73101  *  0b1..Enabled
73102  */
73103 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
73104 
73105 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK  (0x800U)
73106 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
73107 /*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3
73108  *  0b0..Disabled
73109  *  0b1..Enabled
73110  */
73111 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
73112 
73113 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK  (0x1000U)
73114 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
73115 /*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0
73116  *  0b0..Disabled
73117  *  0b1..Enabled
73118  */
73119 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
73120 
73121 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK  (0x2000U)
73122 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
73123 /*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1
73124  *  0b0..Disabled
73125  *  0b1..Enabled
73126  */
73127 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
73128 
73129 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK  (0x4000U)
73130 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
73131 /*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2
73132  *  0b0..Disabled
73133  *  0b1..Enabled
73134  */
73135 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
73136 
73137 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK  (0x8000U)
73138 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
73139 /*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3
73140  *  0b0..Disabled
73141  *  0b1..Enabled
73142  */
73143 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
73144 /*! @} */
73145 
73146 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
73147 /*! @{ */
73148 
73149 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK  (0x1U)
73150 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
73151 /*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0
73152  *  0b0..Disabled
73153  *  0b1..Enabled
73154  */
73155 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
73156 
73157 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK  (0x2U)
73158 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
73159 /*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1
73160  *  0b0..Disabled
73161  *  0b1..Enabled
73162  */
73163 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
73164 
73165 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK  (0x4U)
73166 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
73167 /*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2
73168  *  0b0..Disabled
73169  *  0b1..Enabled
73170  */
73171 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
73172 
73173 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK  (0x8U)
73174 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
73175 /*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3
73176  *  0b0..Disabled
73177  *  0b1..Enabled
73178  */
73179 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
73180 
73181 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK   (0x10U)
73182 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT  (4U)
73183 /*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0
73184  *  0b0..Disabled
73185  *  0b1..Enabled
73186  */
73187 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
73188 
73189 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK   (0x20U)
73190 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT  (5U)
73191 /*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1
73192  *  0b0..Disabled
73193  *  0b1..Enabled
73194  */
73195 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
73196 
73197 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK   (0x40U)
73198 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT  (6U)
73199 /*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2
73200  *  0b0..Disabled
73201  *  0b1..Enabled
73202  */
73203 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
73204 
73205 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK   (0x80U)
73206 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT  (7U)
73207 /*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3
73208  *  0b0..Disabled
73209  *  0b1..Enabled
73210  */
73211 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
73212 
73213 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK    (0x100U)
73214 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT   (8U)
73215 /*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0
73216  *  0b0..Disabled
73217  *  0b1..Enabled
73218  */
73219 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
73220 
73221 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK    (0x200U)
73222 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT   (9U)
73223 /*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1
73224  *  0b0..Disabled
73225  *  0b1..Enabled
73226  */
73227 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
73228 
73229 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK    (0x400U)
73230 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT   (10U)
73231 /*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2
73232  *  0b0..Disabled
73233  *  0b1..Enabled
73234  */
73235 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
73236 
73237 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK    (0x800U)
73238 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT   (11U)
73239 /*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3
73240  *  0b0..Disabled
73241  *  0b1..Enabled
73242  */
73243 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
73244 
73245 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK    (0x1000U)
73246 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT   (12U)
73247 /*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0
73248  *  0b0..Disabled
73249  *  0b1..Enabled
73250  */
73251 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
73252 
73253 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK    (0x2000U)
73254 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT   (13U)
73255 /*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1
73256  *  0b0..Disabled
73257  *  0b1..Enabled
73258  */
73259 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
73260 
73261 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK    (0x4000U)
73262 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT   (14U)
73263 /*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2
73264  *  0b0..Disabled
73265  *  0b1..Enabled
73266  */
73267 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
73268 
73269 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK    (0x8000U)
73270 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT   (15U)
73271 /*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3
73272  *  0b0..Disabled
73273  *  0b1..Enabled
73274  */
73275 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
73276 /*! @} */
73277 
73278 /*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
73279 /*! @{ */
73280 
73281 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73282 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
73283 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
73284  */
73285 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
73286 /*! @} */
73287 
73288 /*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
73289 /*! @{ */
73290 
73291 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73292 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
73293 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
73294  */
73295 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
73296 /*! @} */
73297 
73298 /*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
73299 /*! @{ */
73300 
73301 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK       (0xFFU)
73302 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT      (0U)
73303 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
73304  */
73305 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
73306 /*! @} */
73307 
73308 /*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
73309 /*! @{ */
73310 
73311 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73312 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
73313 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
73314  */
73315 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
73316 /*! @} */
73317 
73318 /*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
73319 /*! @{ */
73320 
73321 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73322 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
73323 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
73324  */
73325 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
73326 /*! @} */
73327 
73328 /*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
73329 /*! @{ */
73330 
73331 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK       (0xFFU)
73332 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT      (0U)
73333 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
73334  */
73335 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
73336 /*! @} */
73337 
73338 /*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
73339 /*! @{ */
73340 
73341 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73342 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
73343 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
73344  */
73345 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
73346 /*! @} */
73347 
73348 /*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
73349 /*! @{ */
73350 
73351 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73352 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
73353 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
73354  */
73355 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
73356 /*! @} */
73357 
73358 /*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
73359 /*! @{ */
73360 
73361 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK       (0xFFU)
73362 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT      (0U)
73363 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
73364  */
73365 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
73366 /*! @} */
73367 
73368 /*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
73369 /*! @{ */
73370 
73371 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73372 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
73373 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
73374  */
73375 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
73376 /*! @} */
73377 
73378 /*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
73379 /*! @{ */
73380 
73381 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
73382 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
73383 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
73384  */
73385 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
73386 /*! @} */
73387 
73388 /*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
73389 /*! @{ */
73390 
73391 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK       (0xFFU)
73392 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT      (0U)
73393 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
73394  */
73395 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
73396 /*! @} */
73397 
73398 /*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */
73399 /*! @{ */
73400 
73401 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
73402 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
73403 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0
73404  */
73405 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
73406 
73407 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73408 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
73409 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0
73410  */
73411 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)
73412 /*! @} */
73413 
73414 /*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
73415 /*! @{ */
73416 
73417 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73418 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
73419 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0
73420  */
73421 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
73422 /*! @} */
73423 
73424 /*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
73425 /*! @{ */
73426 
73427 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73428 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
73429 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
73430  */
73431 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
73432 /*! @} */
73433 
73434 /*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */
73435 /*! @{ */
73436 
73437 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73438 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
73439 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0
73440  */
73441 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
73442 /*! @} */
73443 
73444 /*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */
73445 /*! @{ */
73446 
73447 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73448 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
73449 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0
73450  */
73451 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
73452 /*! @} */
73453 
73454 /*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */
73455 /*! @{ */
73456 
73457 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
73458 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
73459 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1
73460  */
73461 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
73462 
73463 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73464 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
73465 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1
73466  */
73467 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)
73468 /*! @} */
73469 
73470 /*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
73471 /*! @{ */
73472 
73473 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73474 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
73475 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1
73476  */
73477 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
73478 /*! @} */
73479 
73480 /*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
73481 /*! @{ */
73482 
73483 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73484 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
73485 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
73486  */
73487 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
73488 /*! @} */
73489 
73490 /*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */
73491 /*! @{ */
73492 
73493 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73494 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
73495 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1
73496  */
73497 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
73498 /*! @} */
73499 
73500 /*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */
73501 /*! @{ */
73502 
73503 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73504 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
73505 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1
73506  */
73507 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
73508 /*! @} */
73509 
73510 /*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */
73511 /*! @{ */
73512 
73513 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
73514 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
73515 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2
73516  */
73517 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
73518 
73519 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73520 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
73521 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2
73522  */
73523 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)
73524 /*! @} */
73525 
73526 /*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
73527 /*! @{ */
73528 
73529 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73530 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
73531 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2
73532  */
73533 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
73534 /*! @} */
73535 
73536 /*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
73537 /*! @{ */
73538 
73539 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73540 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
73541 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
73542  */
73543 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
73544 /*! @} */
73545 
73546 /*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */
73547 /*! @{ */
73548 
73549 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73550 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
73551 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2
73552  */
73553 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
73554 /*! @} */
73555 
73556 /*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */
73557 /*! @{ */
73558 
73559 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73560 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
73561 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2
73562  */
73563 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
73564 /*! @} */
73565 
73566 /*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */
73567 /*! @{ */
73568 
73569 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
73570 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
73571 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3
73572  */
73573 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
73574 
73575 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
73576 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
73577 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3
73578  */
73579 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)
73580 /*! @} */
73581 
73582 /*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
73583 /*! @{ */
73584 
73585 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73586 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
73587 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3
73588  */
73589 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
73590 /*! @} */
73591 
73592 /*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
73593 /*! @{ */
73594 
73595 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
73596 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
73597 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
73598  */
73599 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
73600 /*! @} */
73601 
73602 /*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */
73603 /*! @{ */
73604 
73605 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73606 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
73607 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3
73608  */
73609 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
73610 /*! @} */
73611 
73612 /*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */
73613 /*! @{ */
73614 
73615 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
73616 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
73617 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3
73618  */
73619 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
73620 /*! @} */
73621 
73622 /*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */
73623 /*! @{ */
73624 
73625 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
73626 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
73627 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0
73628  */
73629 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
73630 
73631 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73632 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
73633 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0
73634  */
73635 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)
73636 /*! @} */
73637 
73638 /*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
73639 /*! @{ */
73640 
73641 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73642 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
73643 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
73644  */
73645 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
73646 /*! @} */
73647 
73648 /*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
73649 /*! @{ */
73650 
73651 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73652 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
73653 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
73654  */
73655 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
73656 /*! @} */
73657 
73658 /*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */
73659 /*! @{ */
73660 
73661 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
73662 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
73663 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1
73664  */
73665 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
73666 
73667 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73668 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
73669 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1
73670  */
73671 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)
73672 /*! @} */
73673 
73674 /*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
73675 /*! @{ */
73676 
73677 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73678 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
73679 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
73680  */
73681 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
73682 /*! @} */
73683 
73684 /*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
73685 /*! @{ */
73686 
73687 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73688 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
73689 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
73690  */
73691 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
73692 /*! @} */
73693 
73694 /*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */
73695 /*! @{ */
73696 
73697 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
73698 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
73699 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2
73700  */
73701 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
73702 
73703 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73704 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
73705 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2
73706  */
73707 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)
73708 /*! @} */
73709 
73710 /*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
73711 /*! @{ */
73712 
73713 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73714 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
73715 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
73716  */
73717 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
73718 /*! @} */
73719 
73720 /*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
73721 /*! @{ */
73722 
73723 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73724 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
73725 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
73726  */
73727 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
73728 /*! @} */
73729 
73730 /*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */
73731 /*! @{ */
73732 
73733 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
73734 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
73735 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3
73736  */
73737 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
73738 
73739 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
73740 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
73741 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3
73742  */
73743 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)
73744 /*! @} */
73745 
73746 /*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
73747 /*! @{ */
73748 
73749 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73750 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
73751 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
73752  */
73753 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
73754 /*! @} */
73755 
73756 /*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
73757 /*! @{ */
73758 
73759 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
73760 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
73761 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
73762  */
73763 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
73764 /*! @} */
73765 
73766 /*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */
73767 /*! @{ */
73768 
73769 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK  (0x1U)
73770 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
73771 /*! READ_DATA_WAIT_EN - Read Data Wait Enable
73772  *  0b0..Disable.
73773  *  0b1..Enable.
73774  */
73775 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
73776 
73777 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK  (0x2U)
73778 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
73779 /*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable
73780  *  0b0..Disable.
73781  *  0b1..Enable.
73782  */
73783 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
73784 
73785 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
73786 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
73787 /*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable
73788  *  0b0..Disable.
73789  *  0b1..Enable.
73790  */
73791 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
73792 
73793 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
73794 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
73795 /*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable
73796  *  0b0..Disable.
73797  *  0b1..Enable.
73798  */
73799 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
73800 
73801 #define MECC_PIPE_ECC_EN_ECC_EN_MASK             (0x10U)
73802 #define MECC_PIPE_ECC_EN_ECC_EN_SHIFT            (4U)
73803 /*! ECC_EN - ECC Function Enable
73804  *  0b0..Disable.
73805  *  0b1..Enable.
73806  */
73807 #define MECC_PIPE_ECC_EN_ECC_EN(x)               (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
73808 /*! @} */
73809 
73810 /*! @name PENDING_STAT - Pending Status */
73811 /*! @{ */
73812 
73813 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
73814 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
73815 /*! READ_DATA_WAIT_PENDING - Read Data Wait Pending
73816  *  0b0..No update pending status for READ_DATA_WAIT_EN.
73817  *  0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
73818  */
73819 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
73820 
73821 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
73822 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
73823 /*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending
73824  *  0b0..No update pending status for READ_ADDR_PIPE_EN.
73825  *  0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
73826  */
73827 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
73828 
73829 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
73830 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
73831 /*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending
73832  *  0b0..No update pending status for WRITE_DATA_PIPE_EN.
73833  *  0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
73834  */
73835 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
73836 
73837 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
73838 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
73839 /*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending
73840  *  0b0..No update pending status for WRITE_ADDR_PIPE_EN.
73841  *  0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
73842  */
73843 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)
73844 /*! @} */
73845 
73846 
73847 /*!
73848  * @}
73849  */ /* end of group MECC_Register_Masks */
73850 
73851 
73852 /* MECC - Peripheral instance base addresses */
73853 /** Peripheral MECC1 base address */
73854 #define MECC1_BASE                               (0x40014000u)
73855 /** Peripheral MECC1 base pointer */
73856 #define MECC1                                    ((MECC_Type *)MECC1_BASE)
73857 /** Peripheral MECC2 base address */
73858 #define MECC2_BASE                               (0x40018000u)
73859 /** Peripheral MECC2 base pointer */
73860 #define MECC2                                    ((MECC_Type *)MECC2_BASE)
73861 /** Array initializer of MECC peripheral base addresses */
73862 #define MECC_BASE_ADDRS                          { 0u, MECC1_BASE, MECC2_BASE }
73863 /** Array initializer of MECC peripheral base pointers */
73864 #define MECC_BASE_PTRS                           { (MECC_Type *)0u, MECC1, MECC2 }
73865 
73866 /*!
73867  * @}
73868  */ /* end of group MECC_Peripheral_Access_Layer */
73869 
73870 
73871 /* ----------------------------------------------------------------------------
73872    -- MIPI_CSI2RX Peripheral Access Layer
73873    ---------------------------------------------------------------------------- */
73874 
73875 /*!
73876  * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
73877  * @{
73878  */
73879 
73880 /** MIPI_CSI2RX - Register Layout Typedef */
73881 typedef struct {
73882        uint8_t RESERVED_0[256];
73883   __IO uint32_t CFG_NUM_LANES;                     /**< Lane Configuration Register, offset: 0x100 */
73884   __IO uint32_t CFG_DISABLE_DATA_LANES;            /**< Disable Data Lane Register, offset: 0x104 */
73885   __I  uint32_t BIT_ERR;                           /**< ECC and CRC Error Status Register, offset: 0x108 */
73886   __I  uint32_t IRQ_STATUS;                        /**< IRQ Status Register, offset: 0x10C */
73887   __IO uint32_t IRQ_MASK;                          /**< IRQ Mask Setting Register, offset: 0x110 */
73888   __I  uint32_t ULPS_STATUS;                       /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */
73889   __I  uint32_t PPI_ERRSOT_HS;                     /**< ERRSot HS Status Register, offset: 0x118 */
73890   __I  uint32_t PPI_ERRSOTSYNC_HS;                 /**< ErrSotSync HS Status Register, offset: 0x11C */
73891   __I  uint32_t PPI_ERRESC;                        /**< ErrEsc Status Register, offset: 0x120 */
73892   __I  uint32_t PPI_ERRSYNCESC;                    /**< ErrSyncEsc Status Register, offset: 0x124 */
73893   __I  uint32_t PPI_ERRCONTROL;                    /**< ErrControl Status Register, offset: 0x128 */
73894   __IO uint32_t CFG_DISABLE_PAYLOAD_0;             /**< Disable Payload 0 Register, offset: 0x12C */
73895   __IO uint32_t CFG_DISABLE_PAYLOAD_1;             /**< Disable Payload 1 Register, offset: 0x130 */
73896        uint8_t RESERVED_1[76];
73897   __IO uint32_t CFG_IGNORE_VC;                     /**< Ignore Virtual Channel Register, offset: 0x180 */
73898   __IO uint32_t CFG_VID_VC;                        /**< Virtual Channel value Register, offset: 0x184 */
73899   __IO uint32_t CFG_VID_P_FIFO_SEND_LEVEL;         /**< FIFO Send Level Configuration Register, offset: 0x188 */
73900   __IO uint32_t CFG_VID_VSYNC;                     /**< VSYNC Configuration Register, offset: 0x18C */
73901   __IO uint32_t CFG_VID_HSYNC_FP;                  /**< Start of HSYNC Delay control Register, offset: 0x190 */
73902   __IO uint32_t CFG_VID_HSYNC;                     /**< HSYNC Configuration Register, offset: 0x194 */
73903   __IO uint32_t CFG_VID_HSYNC_BP;                  /**< End of HSYNC Delay Control Register, offset: 0x198 */
73904 } MIPI_CSI2RX_Type;
73905 
73906 /* ----------------------------------------------------------------------------
73907    -- MIPI_CSI2RX Register Masks
73908    ---------------------------------------------------------------------------- */
73909 
73910 /*!
73911  * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
73912  * @{
73913  */
73914 
73915 /*! @name CFG_NUM_LANES - Lane Configuration Register */
73916 /*! @{ */
73917 
73918 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
73919 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
73920 /*! CFG_NUM_LANES - This field is used to set the number of active lanes for receiving data.
73921  *  0b00..1 Lane
73922  *  0b01..2 Lane
73923  *  0b10-0b11..Reserved
73924  */
73925 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
73926 /*! @} */
73927 
73928 /*! @name CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
73929 /*! @{ */
73930 
73931 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
73932 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
73933 /*! CFG_DISABLE_DATA_LANES - This field is used to disable data lanes.
73934  */
73935 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
73936 /*! @} */
73937 
73938 /*! @name BIT_ERR - ECC and CRC Error Status Register */
73939 /*! @{ */
73940 
73941 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK         (0x3FFU)
73942 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT        (0U)
73943 /*! BIT_ERR - This field shows the error status of ECC and CRC
73944  */
73945 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK)
73946 /*! @} */
73947 
73948 /*! @name IRQ_STATUS - IRQ Status Register */
73949 /*! @{ */
73950 
73951 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK   (0x1FFU)
73952 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT  (0U)
73953 /*! IRQ_STATUS - This field shows the IRQ status
73954  */
73955 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
73956 /*! @} */
73957 
73958 /*! @name IRQ_MASK - IRQ Mask Setting Register */
73959 /*! @{ */
73960 
73961 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK       (0x1FFU)
73962 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT      (0U)
73963 /*! IRQ_MASK - This field shows the IRQ Mask setting
73964  */
73965 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
73966 /*! @} */
73967 
73968 /*! @name ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */
73969 /*! @{ */
73970 
73971 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK      (0x3FFU)
73972 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT     (0U)
73973 /*! STATUS - This field shows the status of Rx D-PHY ULPS state
73974  */
73975 #define MIPI_CSI2RX_ULPS_STATUS_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK)
73976 /*! @} */
73977 
73978 /*! @name PPI_ERRSOT_HS - ERRSot HS Status Register */
73979 /*! @{ */
73980 
73981 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK    (0xFU)
73982 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT   (0U)
73983 /*! STATUS - This field indicates PPI ErrSotHS captured status from D-PHY
73984  */
73985 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
73986 /*! @} */
73987 
73988 /*! @name PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
73989 /*! @{ */
73990 
73991 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
73992 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
73993 /*! STATUS - This field indicates PPI ErrSotSync_HS captured status from D-PHY
73994  */
73995 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
73996 /*! @} */
73997 
73998 /*! @name PPI_ERRESC - ErrEsc Status Register */
73999 /*! @{ */
74000 
74001 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK       (0xFU)
74002 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT      (0U)
74003 /*! STATUS - This field indicates PPI ErrEsc captured status from D-PHY
74004  */
74005 #define MIPI_CSI2RX_PPI_ERRESC_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK)
74006 /*! @} */
74007 
74008 /*! @name PPI_ERRSYNCESC - ErrSyncEsc Status Register */
74009 /*! @{ */
74010 
74011 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK   (0xFU)
74012 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT  (0U)
74013 /*! STATUS - This field indicates PPI ErrSyncEsc captured status from D-PHY
74014  */
74015 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
74016 /*! @} */
74017 
74018 /*! @name PPI_ERRCONTROL - ErrControl Status Register */
74019 /*! @{ */
74020 
74021 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK   (0xFU)
74022 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT  (0U)
74023 /*! STATUS - This field indicates PPI ErrControl captured status from D-PHY
74024  */
74025 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
74026 /*! @} */
74027 
74028 /*! @name CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
74029 /*! @{ */
74030 
74031 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
74032 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
74033 /*! DIS_PAYLOAD_NULL - Null
74034  */
74035 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
74036 
74037 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
74038 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
74039 /*! DIS_PAYLOAD_BLANK - Blank
74040  */
74041 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
74042 
74043 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
74044 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
74045 /*! DIS_PAYLOAD_EMBEDDED - Embedded
74046  */
74047 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
74048 
74049 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
74050 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
74051 /*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit
74052  */
74053 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
74054 
74055 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
74056 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
74057 /*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit
74058  */
74059 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
74060 
74061 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
74062 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
74063 /*! DIS_PAYLOAD_RGB444 - RGB444
74064  */
74065 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
74066 
74067 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
74068 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
74069 /*! DIS_PAYLOAD_RGB555 - RGB555
74070  */
74071 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
74072 
74073 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
74074 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
74075 /*! DIS_PAYLOAD_RGB565 - RGB565
74076  */
74077 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
74078 
74079 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
74080 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
74081 /*! DIS_PAYLOAD_RGB666 - RGB666
74082  */
74083 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
74084 
74085 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
74086 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
74087 /*! DIS_PAYLOAD_RGB888 - RGB888
74088  */
74089 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
74090 /*! @} */
74091 
74092 /*! @name CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
74093 /*! @{ */
74094 
74095 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
74096 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
74097 /*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31
74098  */
74099 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
74100 
74101 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
74102 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
74103 /*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32
74104  */
74105 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
74106 
74107 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
74108 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
74109 /*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33
74110  */
74111 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
74112 
74113 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
74114 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
74115 /*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34
74116  */
74117 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
74118 
74119 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
74120 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
74121 /*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35
74122  */
74123 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
74124 
74125 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
74126 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
74127 /*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35
74128  */
74129 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
74130 
74131 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
74132 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
74133 /*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36
74134  */
74135 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
74136 
74137 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
74138 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
74139 /*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37
74140  */
74141 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
74142 
74143 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
74144 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
74145 /*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types
74146  */
74147 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
74148 /*! @} */
74149 
74150 /*! @name CFG_IGNORE_VC - Ignore Virtual Channel Register */
74151 /*! @{ */
74152 
74153 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U)
74154 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U)
74155 #define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK)
74156 /*! @} */
74157 
74158 /*! @name CFG_VID_VC - Virtual Channel value Register */
74159 /*! @{ */
74160 
74161 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK       (0x3U)
74162 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT      (0U)
74163 #define MIPI_CSI2RX_CFG_VID_VC_VID_VC(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK)
74164 /*! @} */
74165 
74166 /*! @name CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */
74167 /*! @{ */
74168 
74169 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU)
74170 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U)
74171 /*! SEND_LEVEL - FIFO Send Level field
74172  */
74173 #define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK)
74174 /*! @} */
74175 
74176 /*! @name CFG_VID_VSYNC - VSYNC Configuration Register */
74177 /*! @{ */
74178 
74179 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK     (0xFFU)
74180 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT    (0U)
74181 /*! WIDTH - Width of VSYNC
74182  */
74183 #define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK)
74184 /*! @} */
74185 
74186 /*! @name CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */
74187 /*! @{ */
74188 
74189 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU)
74190 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U)
74191 /*! DELAY_CTL - Delay control for beginning of HSYNC pulse
74192  */
74193 #define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK)
74194 /*! @} */
74195 
74196 /*! @name CFG_VID_HSYNC - HSYNC Configuration Register */
74197 /*! @{ */
74198 
74199 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK     (0xFFU)
74200 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT    (0U)
74201 /*! WIDTH - Width of HSYNC
74202  */
74203 #define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK)
74204 /*! @} */
74205 
74206 /*! @name CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */
74207 /*! @{ */
74208 
74209 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU)
74210 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U)
74211 /*! DELAY_CTL - Delay Control for end of HSYNC pulse
74212  */
74213 #define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK)
74214 /*! @} */
74215 
74216 
74217 /*!
74218  * @}
74219  */ /* end of group MIPI_CSI2RX_Register_Masks */
74220 
74221 
74222 /* MIPI_CSI2RX - Peripheral instance base addresses */
74223 /** Peripheral MIPI_CSI2RX base address */
74224 #define MIPI_CSI2RX_BASE                         (0x40810000u)
74225 /** Peripheral MIPI_CSI2RX base pointer */
74226 #define MIPI_CSI2RX                              ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
74227 /** Array initializer of MIPI_CSI2RX peripheral base addresses */
74228 #define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI2RX_BASE }
74229 /** Array initializer of MIPI_CSI2RX peripheral base pointers */
74230 #define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI2RX }
74231 
74232 /*!
74233  * @}
74234  */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
74235 
74236 
74237 /* ----------------------------------------------------------------------------
74238    -- MU Peripheral Access Layer
74239    ---------------------------------------------------------------------------- */
74240 
74241 /*!
74242  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
74243  * @{
74244  */
74245 
74246 /** MU - Register Layout Typedef */
74247 typedef struct {
74248   __IO uint32_t TR[4];                             /**< Processor A Transmit Register 0..Processor A Transmit Register 3, array offset: 0x0, array step: 0x4 */
74249   __I  uint32_t RR[4];                             /**< Processor A Receive Register 0..Processor A Receive Register 3, array offset: 0x10, array step: 0x4 */
74250   __IO uint32_t SR;                                /**< Processor A Status Register, offset: 0x20 */
74251   __IO uint32_t CR;                                /**< Processor A Control Register, offset: 0x24 */
74252 } MU_Type;
74253 
74254 /* ----------------------------------------------------------------------------
74255    -- MU Register Masks
74256    ---------------------------------------------------------------------------- */
74257 
74258 /*!
74259  * @addtogroup MU_Register_Masks MU Register Masks
74260  * @{
74261  */
74262 
74263 /*! @name TR - Processor A Transmit Register 0..Processor A Transmit Register 3 */
74264 /*! @{ */
74265 
74266 #define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
74267 #define MU_TR_DATA_SHIFT                         (0U)
74268 /*! DATA - TR3
74269  */
74270 #define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
74271 /*! @} */
74272 
74273 /* The count of MU_TR */
74274 #define MU_TR_COUNT                              (4U)
74275 
74276 /*! @name RR - Processor A Receive Register 0..Processor A Receive Register 3 */
74277 /*! @{ */
74278 
74279 #define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
74280 #define MU_RR_DATA_SHIFT                         (0U)
74281 /*! DATA - RR3
74282  */
74283 #define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
74284 /*! @} */
74285 
74286 /* The count of MU_RR */
74287 #define MU_RR_COUNT                              (4U)
74288 
74289 /*! @name SR - Processor A Status Register */
74290 /*! @{ */
74291 
74292 #define MU_SR_Fn_MASK                            (0x7U)
74293 #define MU_SR_Fn_SHIFT                           (0U)
74294 /*! Fn - Fn
74295  *  0b000..BAFn bit in MUB.CR register is written 0 (default).
74296  *  0b001..BAFn bit in MUB.CR register is written 1.
74297  */
74298 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
74299 
74300 #define MU_SR_EP_MASK                            (0x10U)
74301 #define MU_SR_EP_SHIFT                           (4U)
74302 /*! EP - EP
74303  *  0b0..The Processor A-side event is not pending (default).
74304  *  0b1..The Processor A-side event is pending.
74305  */
74306 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
74307 
74308 #define MU_SR_RS_MASK                            (0x80U)
74309 #define MU_SR_RS_SHIFT                           (7U)
74310 /*! RS - RS
74311  *  0b0..The Processor B-side of the MU is not in reset.
74312  *  0b1..The Processor B-side of the MU is in reset.
74313  */
74314 #define MU_SR_RS(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
74315 
74316 #define MU_SR_FUP_MASK                           (0x100U)
74317 #define MU_SR_FUP_SHIFT                          (8U)
74318 /*! FUP - FUP
74319  *  0b0..No flags updated, initiated by the Processor A, in progress (default)
74320  *  0b1..Processor A initiated flags update, processing
74321  */
74322 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
74323 
74324 #define MU_SR_TEn_MASK                           (0xF00000U)
74325 #define MU_SR_TEn_SHIFT                          (20U)
74326 /*! TEn - TEn
74327  *  0b0000..MUA.TRn register is not empty.
74328  *  0b0001..MUA.TRn register is empty (default).
74329  */
74330 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
74331 
74332 #define MU_SR_RFn_MASK                           (0xF000000U)
74333 #define MU_SR_RFn_SHIFT                          (24U)
74334 /*! RFn - RFn
74335  *  0b0000..MUA.RRn register is not full (default).
74336  *  0b0001..MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A.
74337  */
74338 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
74339 
74340 #define MU_SR_GIPn_MASK                          (0xF0000000U)
74341 #define MU_SR_GIPn_SHIFT                         (28U)
74342 /*! GIPn - GIPn
74343  *  0b0000..Processor A general purpose interrupt n is not pending. (default)
74344  *  0b0001..Processor A general purpose interrupt n is pending.
74345  */
74346 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
74347 /*! @} */
74348 
74349 /*! @name CR - Processor A Control Register */
74350 /*! @{ */
74351 
74352 #define MU_CR_Fn_MASK                            (0x7U)
74353 #define MU_CR_Fn_SHIFT                           (0U)
74354 /*! Fn - Fn
74355  *  0b000..N/A. Self clearing bit (default).
74356  *  0b001..Asserts the Processor A MU reset.
74357  */
74358 #define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
74359 
74360 #define MU_CR_MUR_MASK                           (0x20U)
74361 #define MU_CR_MUR_SHIFT                          (5U)
74362 /*! MUR - MUR
74363  *  0b0..N/A. Self clearing bit (default).
74364  *  0b1..Asserts the Processor A MU reset.
74365  */
74366 #define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
74367 
74368 #define MU_CR_GIRn_MASK                          (0xF0000U)
74369 #define MU_CR_GIRn_SHIFT                         (16U)
74370 /*! GIRn - GIRn
74371  *  0b0000..Processor A General Interrupt n is not requested to the Processor B (default).
74372  *  0b0001..Processor A General Interrupt n is requested to the Processor B.
74373  */
74374 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
74375 
74376 #define MU_CR_TIEn_MASK                          (0xF00000U)
74377 #define MU_CR_TIEn_SHIFT                         (20U)
74378 /*! TIEn - TIEn
74379  *  0b0000..Disables Processor A Transmit Interrupt n. (default)
74380  *  0b0001..Enables Processor A Transmit Interrupt n.
74381  */
74382 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
74383 
74384 #define MU_CR_RIEn_MASK                          (0xF000000U)
74385 #define MU_CR_RIEn_SHIFT                         (24U)
74386 /*! RIEn - RIEn
74387  *  0b0000..Disables Processor A Receive Interrupt n. (default)
74388  *  0b0001..Enables Processor A Receive Interrupt n.
74389  */
74390 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
74391 
74392 #define MU_CR_GIEn_MASK                          (0xF0000000U)
74393 #define MU_CR_GIEn_SHIFT                         (28U)
74394 /*! GIEn - GIEn
74395  *  0b0000..Disables Processor A General Interrupt n. (default)
74396  *  0b0001..Enables Processor A General Interrupt n.
74397  */
74398 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
74399 /*! @} */
74400 
74401 
74402 /*!
74403  * @}
74404  */ /* end of group MU_Register_Masks */
74405 
74406 
74407 /* MU - Peripheral instance base addresses */
74408 /** Peripheral MUA base address */
74409 #define MUA_BASE                                 (0x40C48000u)
74410 /** Peripheral MUA base pointer */
74411 #define MUA                                      ((MU_Type *)MUA_BASE)
74412 /** Array initializer of MU peripheral base addresses */
74413 #define MU_BASE_ADDRS                            { MUA_BASE }
74414 /** Array initializer of MU peripheral base pointers */
74415 #define MU_BASE_PTRS                             { MUA }
74416 /** Interrupt vectors for the MU peripheral type */
74417 #define MU_IRQS                                  { MUA_IRQn }
74418 
74419 /*!
74420  * @}
74421  */ /* end of group MU_Peripheral_Access_Layer */
74422 
74423 
74424 /* ----------------------------------------------------------------------------
74425    -- OCOTP Peripheral Access Layer
74426    ---------------------------------------------------------------------------- */
74427 
74428 /*!
74429  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
74430  * @{
74431  */
74432 
74433 /** OCOTP - Register Layout Typedef */
74434 typedef struct {
74435   __IO uint32_t CTRL;                              /**< OTP Controller Control and Status Register, offset: 0x0 */
74436   __IO uint32_t CTRL_SET;                          /**< OTP Controller Control and Status Register, offset: 0x4 */
74437   __IO uint32_t CTRL_CLR;                          /**< OTP Controller Control and Status Register, offset: 0x8 */
74438   __IO uint32_t CTRL_TOG;                          /**< OTP Controller Control and Status Register, offset: 0xC */
74439   __IO uint32_t PDN;                               /**< OTP Controller PDN Register, offset: 0x10 */
74440        uint8_t RESERVED_0[12];
74441   __IO uint32_t DATA;                              /**< OTP Controller Write Data Register, offset: 0x20 */
74442        uint8_t RESERVED_1[12];
74443   __IO uint32_t READ_CTRL;                         /**< OTP Controller Read Control Register, offset: 0x30 */
74444        uint8_t RESERVED_2[92];
74445   __IO uint32_t OUT_STATUS;                        /**< 8K OTP Memory STATUS Register, offset: 0x90 */
74446   __IO uint32_t OUT_STATUS_SET;                    /**< 8K OTP Memory STATUS Register, offset: 0x94 */
74447   __IO uint32_t OUT_STATUS_CLR;                    /**< 8K OTP Memory STATUS Register, offset: 0x98 */
74448   __IO uint32_t OUT_STATUS_TOG;                    /**< 8K OTP Memory STATUS Register, offset: 0x9C */
74449        uint8_t RESERVED_3[16];
74450   __I  uint32_t VERSION;                           /**< OTP Controller Version Register, offset: 0xB0 */
74451        uint8_t RESERVED_4[76];
74452   struct {                                         /* offset: 0x100, array step: 0x10 */
74453     __IO uint32_t READ_FUSE_DATA;                    /**< OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10 */
74454          uint8_t RESERVED_0[12];
74455   } READ_FUSE_DATAS[4];
74456   __IO uint32_t SW_LOCK;                           /**< SW_LOCK Register, offset: 0x140 */
74457        uint8_t RESERVED_5[12];
74458   __IO uint32_t BIT_LOCK;                          /**< BIT_LOCK Register, offset: 0x150 */
74459        uint8_t RESERVED_6[1196];
74460   __I  uint32_t LOCKED0;                           /**< OTP Controller Program Locked Status 0 Register, offset: 0x600 */
74461        uint8_t RESERVED_7[12];
74462   __I  uint32_t LOCKED1;                           /**< OTP Controller Program Locked Status 1 Register, offset: 0x610 */
74463        uint8_t RESERVED_8[12];
74464   __I  uint32_t LOCKED2;                           /**< OTP Controller Program Locked Status 2 Register, offset: 0x620 */
74465        uint8_t RESERVED_9[12];
74466   __I  uint32_t LOCKED3;                           /**< OTP Controller Program Locked Status 3 Register, offset: 0x630 */
74467        uint8_t RESERVED_10[12];
74468   __I  uint32_t LOCKED4;                           /**< OTP Controller Program Locked Status 4 Register, offset: 0x640 */
74469        uint8_t RESERVED_11[444];
74470   struct {                                         /* offset: 0x800, array step: 0x10 */
74471     __I  uint32_t FUSE;                              /**< Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10 */
74472          uint8_t RESERVED_0[12];
74473   } FUSEN[144];
74474 } OCOTP_Type;
74475 
74476 /* ----------------------------------------------------------------------------
74477    -- OCOTP Register Masks
74478    ---------------------------------------------------------------------------- */
74479 
74480 /*!
74481  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
74482  * @{
74483  */
74484 
74485 /*! @name CTRL - OTP Controller Control and Status Register */
74486 /*! @{ */
74487 
74488 #define OCOTP_CTRL_ADDR_MASK                     (0x3FFU)
74489 #define OCOTP_CTRL_ADDR_SHIFT                    (0U)
74490 /*! ADDR - OTP write and read access address register
74491  *  0b0000000000-0b0000001111..Address of one of the 16 supplementary fuse words in OTP memory.
74492  *  0b0000010000-0b0100001111..Address of one of the 256 user fuse words in OTP memory.
74493  */
74494 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
74495 
74496 #define OCOTP_CTRL_BUSY_MASK                     (0x400U)
74497 #define OCOTP_CTRL_BUSY_SHIFT                    (10U)
74498 /*! BUSY - OTP controller status bit
74499  *  0b0..No write or read access to OTP started.
74500  *  0b1..Write or read access to OTP started.
74501  */
74502 #define OCOTP_CTRL_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
74503 
74504 #define OCOTP_CTRL_ERROR_MASK                    (0x800U)
74505 #define OCOTP_CTRL_ERROR_SHIFT                   (11U)
74506 /*! ERROR - Locked Region Access Error
74507  *  0b0..No error.
74508  *  0b1..Error - access to a locked region requested.
74509  */
74510 #define OCOTP_CTRL_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
74511 
74512 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           (0x1000U)
74513 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          (12U)
74514 /*! RELOAD_SHADOWS - Reload Shadow Registers
74515  *  0b0..Do not force shadow register re-load.
74516  *  0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded.
74517  */
74518 #define OCOTP_CTRL_RELOAD_SHADOWS(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
74519 
74520 #define OCOTP_CTRL_WORDLOCK_MASK                 (0x8000U)
74521 #define OCOTP_CTRL_WORDLOCK_SHIFT                (15U)
74522 /*! WORDLOCK - Lock fuse word
74523  *  0b0..No change to LOCK bit when programming a word using redundancy
74524  *  0b1..LOCK bit for fuse word will be set after successfully programming a word using redundancy
74525  */
74526 #define OCOTP_CTRL_WORDLOCK(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK)
74527 
74528 #define OCOTP_CTRL_WR_UNLOCK_MASK                (0xFFFF0000U)
74529 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               (16U)
74530 /*! WR_UNLOCK - Write unlock
74531  *  0b0000000000000000..OTP write access is locked.
74532  *  0b0011111001110111..OTP write access is unlocked.
74533  */
74534 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
74535 /*! @} */
74536 
74537 /*! @name CTRL_SET - OTP Controller Control and Status Register */
74538 /*! @{ */
74539 
74540 #define OCOTP_CTRL_SET_ADDR_MASK                 (0x3FFU)
74541 #define OCOTP_CTRL_SET_ADDR_SHIFT                (0U)
74542 /*! ADDR - OTP write and read access address register
74543  */
74544 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
74545 
74546 #define OCOTP_CTRL_SET_BUSY_MASK                 (0x400U)
74547 #define OCOTP_CTRL_SET_BUSY_SHIFT                (10U)
74548 /*! BUSY - OTP controller status bit
74549  */
74550 #define OCOTP_CTRL_SET_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
74551 
74552 #define OCOTP_CTRL_SET_ERROR_MASK                (0x800U)
74553 #define OCOTP_CTRL_SET_ERROR_SHIFT               (11U)
74554 /*! ERROR - Locked Region Access Error
74555  */
74556 #define OCOTP_CTRL_SET_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
74557 
74558 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       (0x1000U)
74559 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      (12U)
74560 /*! RELOAD_SHADOWS - Reload Shadow Registers
74561  */
74562 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
74563 
74564 #define OCOTP_CTRL_SET_WORDLOCK_MASK             (0x8000U)
74565 #define OCOTP_CTRL_SET_WORDLOCK_SHIFT            (15U)
74566 /*! WORDLOCK - Lock fuse word
74567  */
74568 #define OCOTP_CTRL_SET_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK)
74569 
74570 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            (0xFFFF0000U)
74571 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           (16U)
74572 /*! WR_UNLOCK - Write unlock
74573  */
74574 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
74575 /*! @} */
74576 
74577 /*! @name CTRL_CLR - OTP Controller Control and Status Register */
74578 /*! @{ */
74579 
74580 #define OCOTP_CTRL_CLR_ADDR_MASK                 (0x3FFU)
74581 #define OCOTP_CTRL_CLR_ADDR_SHIFT                (0U)
74582 /*! ADDR - OTP write and read access address register
74583  */
74584 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
74585 
74586 #define OCOTP_CTRL_CLR_BUSY_MASK                 (0x400U)
74587 #define OCOTP_CTRL_CLR_BUSY_SHIFT                (10U)
74588 /*! BUSY - OTP controller status bit
74589  */
74590 #define OCOTP_CTRL_CLR_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
74591 
74592 #define OCOTP_CTRL_CLR_ERROR_MASK                (0x800U)
74593 #define OCOTP_CTRL_CLR_ERROR_SHIFT               (11U)
74594 /*! ERROR - Locked Region Access Error
74595  */
74596 #define OCOTP_CTRL_CLR_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
74597 
74598 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       (0x1000U)
74599 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      (12U)
74600 /*! RELOAD_SHADOWS - Reload Shadow Registers
74601  */
74602 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
74603 
74604 #define OCOTP_CTRL_CLR_WORDLOCK_MASK             (0x8000U)
74605 #define OCOTP_CTRL_CLR_WORDLOCK_SHIFT            (15U)
74606 /*! WORDLOCK - Lock fuse word
74607  */
74608 #define OCOTP_CTRL_CLR_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK)
74609 
74610 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            (0xFFFF0000U)
74611 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           (16U)
74612 /*! WR_UNLOCK - Write unlock
74613  */
74614 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
74615 /*! @} */
74616 
74617 /*! @name CTRL_TOG - OTP Controller Control and Status Register */
74618 /*! @{ */
74619 
74620 #define OCOTP_CTRL_TOG_ADDR_MASK                 (0x3FFU)
74621 #define OCOTP_CTRL_TOG_ADDR_SHIFT                (0U)
74622 /*! ADDR - OTP write and read access address register
74623  */
74624 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
74625 
74626 #define OCOTP_CTRL_TOG_BUSY_MASK                 (0x400U)
74627 #define OCOTP_CTRL_TOG_BUSY_SHIFT                (10U)
74628 /*! BUSY - OTP controller status bit
74629  */
74630 #define OCOTP_CTRL_TOG_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
74631 
74632 #define OCOTP_CTRL_TOG_ERROR_MASK                (0x800U)
74633 #define OCOTP_CTRL_TOG_ERROR_SHIFT               (11U)
74634 /*! ERROR - Locked Region Access Error
74635  */
74636 #define OCOTP_CTRL_TOG_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
74637 
74638 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       (0x1000U)
74639 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      (12U)
74640 /*! RELOAD_SHADOWS - Reload Shadow Registers
74641  */
74642 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
74643 
74644 #define OCOTP_CTRL_TOG_WORDLOCK_MASK             (0x8000U)
74645 #define OCOTP_CTRL_TOG_WORDLOCK_SHIFT            (15U)
74646 /*! WORDLOCK - Lock fuse word
74647  */
74648 #define OCOTP_CTRL_TOG_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK)
74649 
74650 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            (0xFFFF0000U)
74651 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           (16U)
74652 /*! WR_UNLOCK - Write unlock
74653  */
74654 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
74655 /*! @} */
74656 
74657 /*! @name PDN - OTP Controller PDN Register */
74658 /*! @{ */
74659 
74660 #define OCOTP_PDN_PDN_MASK                       (0x1U)
74661 #define OCOTP_PDN_PDN_SHIFT                      (0U)
74662 /*! PDN - PDN value
74663  *  0b0..OTP memory is not powered
74664  *  0b1..OTP memory is powered
74665  */
74666 #define OCOTP_PDN_PDN(x)                         (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK)
74667 /*! @} */
74668 
74669 /*! @name DATA - OTP Controller Write Data Register */
74670 /*! @{ */
74671 
74672 #define OCOTP_DATA_DATA_MASK                     (0xFFFFFFFFU)
74673 #define OCOTP_DATA_DATA_SHIFT                    (0U)
74674 /*! DATA - Data
74675  */
74676 #define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
74677 /*! @} */
74678 
74679 /*! @name READ_CTRL - OTP Controller Read Control Register */
74680 /*! @{ */
74681 
74682 #define OCOTP_READ_CTRL_READ_FUSE_MASK           (0x1U)
74683 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          (0U)
74684 /*! READ_FUSE - Read Fuse
74685  *  0b0..Do not initiate a read from OTP
74686  *  0b1..Initiate a read from OTP
74687  */
74688 #define OCOTP_READ_CTRL_READ_FUSE(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
74689 
74690 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK      (0x6U)
74691 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT     (1U)
74692 /*! READ_FUSE_CNTR - Number of words to read.
74693  *  0b00..1 word
74694  *  0b01..2 words
74695  *  0b10..3 words
74696  *  0b11..4 words
74697  */
74698 #define OCOTP_READ_CTRL_READ_FUSE_CNTR(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK)
74699 
74700 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U)
74701 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U)
74702 /*! READ_FUSE_DONE_INTR_ENA - Enable read-done interrupt
74703  *  0b0..Disable
74704  *  0b1..Enable
74705  */
74706 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK)
74707 
74708 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U)
74709 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U)
74710 /*! READ_FUSE_ERROR_INTR_ENA - Enable read-error interrupt
74711  *  0b0..Disable
74712  *  0b1..Enable
74713  */
74714 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK)
74715 /*! @} */
74716 
74717 /*! @name OUT_STATUS - 8K OTP Memory STATUS Register */
74718 /*! @{ */
74719 
74720 #define OCOTP_OUT_STATUS_SEC_MASK                (0x200U)
74721 #define OCOTP_OUT_STATUS_SEC_SHIFT               (9U)
74722 /*! SEC - Single Error Correct
74723  */
74724 #define OCOTP_OUT_STATUS_SEC(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK)
74725 
74726 #define OCOTP_OUT_STATUS_DED_MASK                (0x400U)
74727 #define OCOTP_OUT_STATUS_DED_SHIFT               (10U)
74728 /*! DED - Double error detect
74729  */
74730 #define OCOTP_OUT_STATUS_DED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK)
74731 
74732 #define OCOTP_OUT_STATUS_LOCKED_MASK             (0x800U)
74733 #define OCOTP_OUT_STATUS_LOCKED_SHIFT            (11U)
74734 /*! LOCKED - Word Locked
74735  */
74736 #define OCOTP_OUT_STATUS_LOCKED(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK)
74737 
74738 #define OCOTP_OUT_STATUS_PROGFAIL_MASK           (0x1000U)
74739 #define OCOTP_OUT_STATUS_PROGFAIL_SHIFT          (12U)
74740 /*! PROGFAIL - Programming failed
74741  */
74742 #define OCOTP_OUT_STATUS_PROGFAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK)
74743 
74744 #define OCOTP_OUT_STATUS_ACK_MASK                (0x2000U)
74745 #define OCOTP_OUT_STATUS_ACK_SHIFT               (13U)
74746 /*! ACK - Acknowledge
74747  */
74748 #define OCOTP_OUT_STATUS_ACK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK)
74749 
74750 #define OCOTP_OUT_STATUS_PWOK_MASK               (0x4000U)
74751 #define OCOTP_OUT_STATUS_PWOK_SHIFT              (14U)
74752 /*! PWOK - Power OK
74753  */
74754 #define OCOTP_OUT_STATUS_PWOK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK)
74755 
74756 #define OCOTP_OUT_STATUS_FLAGSTATE_MASK          (0x78000U)
74757 #define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT         (15U)
74758 /*! FLAGSTATE - Flag state
74759  */
74760 #define OCOTP_OUT_STATUS_FLAGSTATE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK)
74761 
74762 #define OCOTP_OUT_STATUS_SEC_RELOAD_MASK         (0x80000U)
74763 #define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT        (19U)
74764 /*! SEC_RELOAD - Indicates single error correction occured on reload
74765  */
74766 #define OCOTP_OUT_STATUS_SEC_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK)
74767 
74768 #define OCOTP_OUT_STATUS_DED_RELOAD_MASK         (0x100000U)
74769 #define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT        (20U)
74770 /*! DED_RELOAD - Indicates double error detection occured on reload
74771  */
74772 #define OCOTP_OUT_STATUS_DED_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK)
74773 
74774 #define OCOTP_OUT_STATUS_CALIBRATED_MASK         (0x200000U)
74775 #define OCOTP_OUT_STATUS_CALIBRATED_SHIFT        (21U)
74776 /*! CALIBRATED - Calibrated status
74777  */
74778 #define OCOTP_OUT_STATUS_CALIBRATED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK)
74779 
74780 #define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK     (0x400000U)
74781 #define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT    (22U)
74782 /*! READ_DONE_INTR - Read fuse done
74783  */
74784 #define OCOTP_OUT_STATUS_READ_DONE_INTR(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK)
74785 
74786 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK    (0x800000U)
74787 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT   (23U)
74788 /*! READ_ERROR_INTR - Fuse read error
74789  *  0b0..Read operation finished with out any error
74790  *  0b1..Read operation finished with an error
74791  */
74792 #define OCOTP_OUT_STATUS_READ_ERROR_INTR(x)      (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK)
74793 
74794 #define OCOTP_OUT_STATUS_DED0_MASK               (0x1000000U)
74795 #define OCOTP_OUT_STATUS_DED0_SHIFT              (24U)
74796 /*! DED0 - Double error detect
74797  */
74798 #define OCOTP_OUT_STATUS_DED0(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK)
74799 
74800 #define OCOTP_OUT_STATUS_DED1_MASK               (0x2000000U)
74801 #define OCOTP_OUT_STATUS_DED1_SHIFT              (25U)
74802 /*! DED1 - Double error detect
74803  */
74804 #define OCOTP_OUT_STATUS_DED1(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK)
74805 
74806 #define OCOTP_OUT_STATUS_DED2_MASK               (0x4000000U)
74807 #define OCOTP_OUT_STATUS_DED2_SHIFT              (26U)
74808 /*! DED2 - Double error detect
74809  */
74810 #define OCOTP_OUT_STATUS_DED2(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK)
74811 
74812 #define OCOTP_OUT_STATUS_DED3_MASK               (0x8000000U)
74813 #define OCOTP_OUT_STATUS_DED3_SHIFT              (27U)
74814 /*! DED3 - Double error detect
74815  */
74816 #define OCOTP_OUT_STATUS_DED3(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK)
74817 /*! @} */
74818 
74819 /*! @name OUT_STATUS_SET - 8K OTP Memory STATUS Register */
74820 /*! @{ */
74821 
74822 #define OCOTP_OUT_STATUS_SET_SEC_MASK            (0x200U)
74823 #define OCOTP_OUT_STATUS_SET_SEC_SHIFT           (9U)
74824 /*! SEC - Single Error Correct
74825  */
74826 #define OCOTP_OUT_STATUS_SET_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK)
74827 
74828 #define OCOTP_OUT_STATUS_SET_DED_MASK            (0x400U)
74829 #define OCOTP_OUT_STATUS_SET_DED_SHIFT           (10U)
74830 /*! DED - Double error detect
74831  */
74832 #define OCOTP_OUT_STATUS_SET_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK)
74833 
74834 #define OCOTP_OUT_STATUS_SET_LOCKED_MASK         (0x800U)
74835 #define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT        (11U)
74836 /*! LOCKED - Word Locked
74837  */
74838 #define OCOTP_OUT_STATUS_SET_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK)
74839 
74840 #define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK       (0x1000U)
74841 #define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT      (12U)
74842 /*! PROGFAIL - Programming failed
74843  */
74844 #define OCOTP_OUT_STATUS_SET_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK)
74845 
74846 #define OCOTP_OUT_STATUS_SET_ACK_MASK            (0x2000U)
74847 #define OCOTP_OUT_STATUS_SET_ACK_SHIFT           (13U)
74848 /*! ACK - Acknowledge
74849  */
74850 #define OCOTP_OUT_STATUS_SET_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK)
74851 
74852 #define OCOTP_OUT_STATUS_SET_PWOK_MASK           (0x4000U)
74853 #define OCOTP_OUT_STATUS_SET_PWOK_SHIFT          (14U)
74854 /*! PWOK - Power OK
74855  */
74856 #define OCOTP_OUT_STATUS_SET_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK)
74857 
74858 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK      (0x78000U)
74859 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT     (15U)
74860 /*! FLAGSTATE - Flag state
74861  */
74862 #define OCOTP_OUT_STATUS_SET_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK)
74863 
74864 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK     (0x80000U)
74865 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT    (19U)
74866 /*! SEC_RELOAD - Indicates single error correction occured on reload
74867  */
74868 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK)
74869 
74870 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK     (0x100000U)
74871 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT    (20U)
74872 /*! DED_RELOAD - Indicates double error detection occured on reload
74873  */
74874 #define OCOTP_OUT_STATUS_SET_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK)
74875 
74876 #define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK     (0x200000U)
74877 #define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT    (21U)
74878 /*! CALIBRATED - Calibrated status
74879  */
74880 #define OCOTP_OUT_STATUS_SET_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK)
74881 
74882 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U)
74883 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U)
74884 /*! READ_DONE_INTR - Read fuse done
74885  */
74886 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK)
74887 
74888 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U)
74889 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U)
74890 /*! READ_ERROR_INTR - Fuse read error
74891  */
74892 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK)
74893 
74894 #define OCOTP_OUT_STATUS_SET_DED0_MASK           (0x1000000U)
74895 #define OCOTP_OUT_STATUS_SET_DED0_SHIFT          (24U)
74896 /*! DED0 - Double error detect
74897  */
74898 #define OCOTP_OUT_STATUS_SET_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK)
74899 
74900 #define OCOTP_OUT_STATUS_SET_DED1_MASK           (0x2000000U)
74901 #define OCOTP_OUT_STATUS_SET_DED1_SHIFT          (25U)
74902 /*! DED1 - Double error detect
74903  */
74904 #define OCOTP_OUT_STATUS_SET_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK)
74905 
74906 #define OCOTP_OUT_STATUS_SET_DED2_MASK           (0x4000000U)
74907 #define OCOTP_OUT_STATUS_SET_DED2_SHIFT          (26U)
74908 /*! DED2 - Double error detect
74909  */
74910 #define OCOTP_OUT_STATUS_SET_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK)
74911 
74912 #define OCOTP_OUT_STATUS_SET_DED3_MASK           (0x8000000U)
74913 #define OCOTP_OUT_STATUS_SET_DED3_SHIFT          (27U)
74914 /*! DED3 - Double error detect
74915  */
74916 #define OCOTP_OUT_STATUS_SET_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK)
74917 /*! @} */
74918 
74919 /*! @name OUT_STATUS_CLR - 8K OTP Memory STATUS Register */
74920 /*! @{ */
74921 
74922 #define OCOTP_OUT_STATUS_CLR_SEC_MASK            (0x200U)
74923 #define OCOTP_OUT_STATUS_CLR_SEC_SHIFT           (9U)
74924 /*! SEC - Single Error Correct
74925  */
74926 #define OCOTP_OUT_STATUS_CLR_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK)
74927 
74928 #define OCOTP_OUT_STATUS_CLR_DED_MASK            (0x400U)
74929 #define OCOTP_OUT_STATUS_CLR_DED_SHIFT           (10U)
74930 /*! DED - Double error detect
74931  */
74932 #define OCOTP_OUT_STATUS_CLR_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK)
74933 
74934 #define OCOTP_OUT_STATUS_CLR_LOCKED_MASK         (0x800U)
74935 #define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT        (11U)
74936 /*! LOCKED - Word Locked
74937  */
74938 #define OCOTP_OUT_STATUS_CLR_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK)
74939 
74940 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK       (0x1000U)
74941 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT      (12U)
74942 /*! PROGFAIL - Programming failed
74943  */
74944 #define OCOTP_OUT_STATUS_CLR_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK)
74945 
74946 #define OCOTP_OUT_STATUS_CLR_ACK_MASK            (0x2000U)
74947 #define OCOTP_OUT_STATUS_CLR_ACK_SHIFT           (13U)
74948 /*! ACK - Acknowledge
74949  */
74950 #define OCOTP_OUT_STATUS_CLR_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK)
74951 
74952 #define OCOTP_OUT_STATUS_CLR_PWOK_MASK           (0x4000U)
74953 #define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT          (14U)
74954 /*! PWOK - Power OK
74955  */
74956 #define OCOTP_OUT_STATUS_CLR_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK)
74957 
74958 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK      (0x78000U)
74959 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT     (15U)
74960 /*! FLAGSTATE - Flag state
74961  */
74962 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK)
74963 
74964 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK     (0x80000U)
74965 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT    (19U)
74966 /*! SEC_RELOAD - Indicates single error correction occured on reload
74967  */
74968 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK)
74969 
74970 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK     (0x100000U)
74971 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT    (20U)
74972 /*! DED_RELOAD - Indicates double error detection occured on reload
74973  */
74974 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK)
74975 
74976 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK     (0x200000U)
74977 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT    (21U)
74978 /*! CALIBRATED - Calibrated status
74979  */
74980 #define OCOTP_OUT_STATUS_CLR_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK)
74981 
74982 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U)
74983 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U)
74984 /*! READ_DONE_INTR - Read fuse done
74985  */
74986 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK)
74987 
74988 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U)
74989 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U)
74990 /*! READ_ERROR_INTR - Fuse read error
74991  */
74992 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK)
74993 
74994 #define OCOTP_OUT_STATUS_CLR_DED0_MASK           (0x1000000U)
74995 #define OCOTP_OUT_STATUS_CLR_DED0_SHIFT          (24U)
74996 /*! DED0 - Double error detect
74997  */
74998 #define OCOTP_OUT_STATUS_CLR_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK)
74999 
75000 #define OCOTP_OUT_STATUS_CLR_DED1_MASK           (0x2000000U)
75001 #define OCOTP_OUT_STATUS_CLR_DED1_SHIFT          (25U)
75002 /*! DED1 - Double error detect
75003  */
75004 #define OCOTP_OUT_STATUS_CLR_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK)
75005 
75006 #define OCOTP_OUT_STATUS_CLR_DED2_MASK           (0x4000000U)
75007 #define OCOTP_OUT_STATUS_CLR_DED2_SHIFT          (26U)
75008 /*! DED2 - Double error detect
75009  */
75010 #define OCOTP_OUT_STATUS_CLR_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK)
75011 
75012 #define OCOTP_OUT_STATUS_CLR_DED3_MASK           (0x8000000U)
75013 #define OCOTP_OUT_STATUS_CLR_DED3_SHIFT          (27U)
75014 /*! DED3 - Double error detect
75015  */
75016 #define OCOTP_OUT_STATUS_CLR_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK)
75017 /*! @} */
75018 
75019 /*! @name OUT_STATUS_TOG - 8K OTP Memory STATUS Register */
75020 /*! @{ */
75021 
75022 #define OCOTP_OUT_STATUS_TOG_SEC_MASK            (0x200U)
75023 #define OCOTP_OUT_STATUS_TOG_SEC_SHIFT           (9U)
75024 /*! SEC - Single Error Correct
75025  */
75026 #define OCOTP_OUT_STATUS_TOG_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK)
75027 
75028 #define OCOTP_OUT_STATUS_TOG_DED_MASK            (0x400U)
75029 #define OCOTP_OUT_STATUS_TOG_DED_SHIFT           (10U)
75030 /*! DED - Double error detect
75031  */
75032 #define OCOTP_OUT_STATUS_TOG_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK)
75033 
75034 #define OCOTP_OUT_STATUS_TOG_LOCKED_MASK         (0x800U)
75035 #define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT        (11U)
75036 /*! LOCKED - Word Locked
75037  */
75038 #define OCOTP_OUT_STATUS_TOG_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK)
75039 
75040 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK       (0x1000U)
75041 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT      (12U)
75042 /*! PROGFAIL - Programming failed
75043  */
75044 #define OCOTP_OUT_STATUS_TOG_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK)
75045 
75046 #define OCOTP_OUT_STATUS_TOG_ACK_MASK            (0x2000U)
75047 #define OCOTP_OUT_STATUS_TOG_ACK_SHIFT           (13U)
75048 /*! ACK - Acknowledge
75049  */
75050 #define OCOTP_OUT_STATUS_TOG_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK)
75051 
75052 #define OCOTP_OUT_STATUS_TOG_PWOK_MASK           (0x4000U)
75053 #define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT          (14U)
75054 /*! PWOK - Power OK
75055  */
75056 #define OCOTP_OUT_STATUS_TOG_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK)
75057 
75058 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK      (0x78000U)
75059 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT     (15U)
75060 /*! FLAGSTATE - Flag state
75061  */
75062 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK)
75063 
75064 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK     (0x80000U)
75065 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT    (19U)
75066 /*! SEC_RELOAD - Indicates single error correction occured on reload
75067  */
75068 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK)
75069 
75070 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK     (0x100000U)
75071 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT    (20U)
75072 /*! DED_RELOAD - Indicates double error detection occured on reload
75073  */
75074 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK)
75075 
75076 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK     (0x200000U)
75077 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT    (21U)
75078 /*! CALIBRATED - Calibrated status
75079  */
75080 #define OCOTP_OUT_STATUS_TOG_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK)
75081 
75082 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U)
75083 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U)
75084 /*! READ_DONE_INTR - Read fuse done
75085  */
75086 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK)
75087 
75088 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U)
75089 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U)
75090 /*! READ_ERROR_INTR - Fuse read error
75091  */
75092 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK)
75093 
75094 #define OCOTP_OUT_STATUS_TOG_DED0_MASK           (0x1000000U)
75095 #define OCOTP_OUT_STATUS_TOG_DED0_SHIFT          (24U)
75096 /*! DED0 - Double error detect
75097  */
75098 #define OCOTP_OUT_STATUS_TOG_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK)
75099 
75100 #define OCOTP_OUT_STATUS_TOG_DED1_MASK           (0x2000000U)
75101 #define OCOTP_OUT_STATUS_TOG_DED1_SHIFT          (25U)
75102 /*! DED1 - Double error detect
75103  */
75104 #define OCOTP_OUT_STATUS_TOG_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK)
75105 
75106 #define OCOTP_OUT_STATUS_TOG_DED2_MASK           (0x4000000U)
75107 #define OCOTP_OUT_STATUS_TOG_DED2_SHIFT          (26U)
75108 /*! DED2 - Double error detect
75109  */
75110 #define OCOTP_OUT_STATUS_TOG_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK)
75111 
75112 #define OCOTP_OUT_STATUS_TOG_DED3_MASK           (0x8000000U)
75113 #define OCOTP_OUT_STATUS_TOG_DED3_SHIFT          (27U)
75114 /*! DED3 - Double error detect
75115  */
75116 #define OCOTP_OUT_STATUS_TOG_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK)
75117 /*! @} */
75118 
75119 /*! @name VERSION - OTP Controller Version Register */
75120 /*! @{ */
75121 
75122 #define OCOTP_VERSION_STEP_MASK                  (0xFFFFU)
75123 #define OCOTP_VERSION_STEP_SHIFT                 (0U)
75124 /*! STEP - RTL Version Stepping
75125  */
75126 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
75127 
75128 #define OCOTP_VERSION_MINOR_MASK                 (0xFF0000U)
75129 #define OCOTP_VERSION_MINOR_SHIFT                (16U)
75130 /*! MINOR - Minor RTL Version
75131  */
75132 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
75133 
75134 #define OCOTP_VERSION_MAJOR_MASK                 (0xFF000000U)
75135 #define OCOTP_VERSION_MAJOR_SHIFT                (24U)
75136 /*! MAJOR - Major RTL Version
75137  */
75138 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
75139 /*! @} */
75140 
75141 /*! @name READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register */
75142 /*! @{ */
75143 
75144 #define OCOTP_READ_FUSE_DATA_DATA_MASK           (0xFFFFFFFFU)
75145 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT          (0U)
75146 /*! DATA - Data
75147  */
75148 #define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
75149 /*! @} */
75150 
75151 /* The count of OCOTP_READ_FUSE_DATA */
75152 #define OCOTP_READ_FUSE_DATA_COUNT               (4U)
75153 
75154 /*! @name SW_LOCK - SW_LOCK Register */
75155 /*! @{ */
75156 
75157 #define OCOTP_SW_LOCK_SW_LOCK_MASK               (0xFFFFFFFFU)
75158 #define OCOTP_SW_LOCK_SW_LOCK_SHIFT              (0U)
75159 #define OCOTP_SW_LOCK_SW_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK)
75160 /*! @} */
75161 
75162 /*! @name BIT_LOCK - BIT_LOCK Register */
75163 /*! @{ */
75164 
75165 #define OCOTP_BIT_LOCK_BIT_LOCK_MASK             (0xFFFFFFFFU)
75166 #define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT            (0U)
75167 #define OCOTP_BIT_LOCK_BIT_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK)
75168 /*! @} */
75169 
75170 /*! @name LOCKED0 - OTP Controller Program Locked Status 0 Register */
75171 /*! @{ */
75172 
75173 #define OCOTP_LOCKED0_LOCKED_MASK                (0xFFFFU)
75174 #define OCOTP_LOCKED0_LOCKED_SHIFT               (0U)
75175 #define OCOTP_LOCKED0_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK)
75176 /*! @} */
75177 
75178 /*! @name LOCKED1 - OTP Controller Program Locked Status 1 Register */
75179 /*! @{ */
75180 
75181 #define OCOTP_LOCKED1_LOCKED_MASK                (0xFFFFFFFFU)
75182 #define OCOTP_LOCKED1_LOCKED_SHIFT               (0U)
75183 #define OCOTP_LOCKED1_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK)
75184 /*! @} */
75185 
75186 /*! @name LOCKED2 - OTP Controller Program Locked Status 2 Register */
75187 /*! @{ */
75188 
75189 #define OCOTP_LOCKED2_LOCKED_MASK                (0xFFFFFFFFU)
75190 #define OCOTP_LOCKED2_LOCKED_SHIFT               (0U)
75191 #define OCOTP_LOCKED2_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK)
75192 /*! @} */
75193 
75194 /*! @name LOCKED3 - OTP Controller Program Locked Status 3 Register */
75195 /*! @{ */
75196 
75197 #define OCOTP_LOCKED3_LOCKED_MASK                (0xFFFFFFFFU)
75198 #define OCOTP_LOCKED3_LOCKED_SHIFT               (0U)
75199 #define OCOTP_LOCKED3_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK)
75200 /*! @} */
75201 
75202 /*! @name LOCKED4 - OTP Controller Program Locked Status 4 Register */
75203 /*! @{ */
75204 
75205 #define OCOTP_LOCKED4_LOCKED_MASK                (0xFFFFFFFFU)
75206 #define OCOTP_LOCKED4_LOCKED_SHIFT               (0U)
75207 #define OCOTP_LOCKED4_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK)
75208 /*! @} */
75209 
75210 /*! @name FUSE - Value of fuse word 0..Value of fuse word 143 */
75211 /*! @{ */
75212 
75213 #define OCOTP_FUSE_BITS_MASK                     (0xFFFFFFFFU)
75214 #define OCOTP_FUSE_BITS_SHIFT                    (0U)
75215 /*! BITS - Reflects value of the fuse word
75216  */
75217 #define OCOTP_FUSE_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK)
75218 /*! @} */
75219 
75220 /* The count of OCOTP_FUSE */
75221 #define OCOTP_FUSE_COUNT                         (144U)
75222 
75223 
75224 /*!
75225  * @}
75226  */ /* end of group OCOTP_Register_Masks */
75227 
75228 
75229 /* OCOTP - Peripheral instance base addresses */
75230 /** Peripheral OCOTP base address */
75231 #define OCOTP_BASE                               (0x40CAC000u)
75232 /** Peripheral OCOTP base pointer */
75233 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
75234 /** Array initializer of OCOTP peripheral base addresses */
75235 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
75236 /** Array initializer of OCOTP peripheral base pointers */
75237 #define OCOTP_BASE_PTRS                          { OCOTP }
75238 
75239 /*!
75240  * @}
75241  */ /* end of group OCOTP_Peripheral_Access_Layer */
75242 
75243 
75244 /* ----------------------------------------------------------------------------
75245    -- OSC_RC_400M Peripheral Access Layer
75246    ---------------------------------------------------------------------------- */
75247 
75248 /*!
75249  * @addtogroup OSC_RC_400M_Peripheral_Access_Layer OSC_RC_400M Peripheral Access Layer
75250  * @{
75251  */
75252 
75253 /** OSC_RC_400M - Register Layout Typedef */
75254 typedef struct {
75255   struct {                                         /* offset: 0x0 */
75256     __IO uint32_t RW;                                /**< Control Register 0, offset: 0x0 */
75257     __IO uint32_t SET;                               /**< Control Register 0, offset: 0x4 */
75258     __IO uint32_t CLR;                               /**< Control Register 0, offset: 0x8 */
75259     __IO uint32_t TOG;                               /**< Control Register 0, offset: 0xC */
75260   } CTRL0;
75261   struct {                                         /* offset: 0x10 */
75262     __IO uint32_t RW;                                /**< Control Register 1, offset: 0x10 */
75263     __IO uint32_t SET;                               /**< Control Register 1, offset: 0x14 */
75264     __IO uint32_t CLR;                               /**< Control Register 1, offset: 0x18 */
75265     __IO uint32_t TOG;                               /**< Control Register 1, offset: 0x1C */
75266   } CTRL1;
75267   struct {                                         /* offset: 0x20 */
75268     __IO uint32_t RW;                                /**< Control Register 2, offset: 0x20 */
75269     __IO uint32_t SET;                               /**< Control Register 2, offset: 0x24 */
75270     __IO uint32_t CLR;                               /**< Control Register 2, offset: 0x28 */
75271     __IO uint32_t TOG;                               /**< Control Register 2, offset: 0x2C */
75272   } CTRL2;
75273   struct {                                         /* offset: 0x30 */
75274     __IO uint32_t RW;                                /**< Control Register 3, offset: 0x30 */
75275     __IO uint32_t SET;                               /**< Control Register 3, offset: 0x34 */
75276     __IO uint32_t CLR;                               /**< Control Register 3, offset: 0x38 */
75277     __IO uint32_t TOG;                               /**< Control Register 3, offset: 0x3C */
75278   } CTRL3;
75279        uint8_t RESERVED_0[16];
75280   struct {                                         /* offset: 0x50 */
75281     __I  uint32_t RW;                                /**< Status Register 0, offset: 0x50 */
75282     __I  uint32_t SET;                               /**< Status Register 0, offset: 0x54 */
75283     __I  uint32_t CLR;                               /**< Status Register 0, offset: 0x58 */
75284     __I  uint32_t TOG;                               /**< Status Register 0, offset: 0x5C */
75285   } STAT0;
75286   struct {                                         /* offset: 0x60 */
75287     __I  uint32_t RW;                                /**< Status Register 1, offset: 0x60 */
75288     __I  uint32_t SET;                               /**< Status Register 1, offset: 0x64 */
75289     __I  uint32_t CLR;                               /**< Status Register 1, offset: 0x68 */
75290     __I  uint32_t TOG;                               /**< Status Register 1, offset: 0x6C */
75291   } STAT1;
75292   struct {                                         /* offset: 0x70 */
75293     __I  uint32_t RW;                                /**< Status Register 2, offset: 0x70 */
75294     __I  uint32_t SET;                               /**< Status Register 2, offset: 0x74 */
75295     __I  uint32_t CLR;                               /**< Status Register 2, offset: 0x78 */
75296     __I  uint32_t TOG;                               /**< Status Register 2, offset: 0x7C */
75297   } STAT2;
75298 } OSC_RC_400M_Type;
75299 
75300 /* ----------------------------------------------------------------------------
75301    -- OSC_RC_400M Register Masks
75302    ---------------------------------------------------------------------------- */
75303 
75304 /*!
75305  * @addtogroup OSC_RC_400M_Register_Masks OSC_RC_400M Register Masks
75306  * @{
75307  */
75308 
75309 /*! @name CTRL0 - Control Register 0 */
75310 /*! @{ */
75311 
75312 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK       (0x3F000000U)
75313 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT      (24U)
75314 /*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP)
75315  */
75316 #define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)         (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
75317 /*! @} */
75318 
75319 /*! @name CTRL1 - Control Register 1 */
75320 /*! @{ */
75321 
75322 #define OSC_RC_400M_CTRL1_HYST_MINUS_MASK        (0xFU)
75323 #define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT       (0U)
75324 /*! HYST_MINUS - Negative hysteresis value for the tuned clock
75325  */
75326 #define OSC_RC_400M_CTRL1_HYST_MINUS(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
75327 
75328 #define OSC_RC_400M_CTRL1_HYST_PLUS_MASK         (0xF00U)
75329 #define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT        (8U)
75330 /*! HYST_PLUS - Positive hysteresis value for the tuned clock
75331  */
75332 #define OSC_RC_400M_CTRL1_HYST_PLUS(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
75333 
75334 #define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK      (0xFFFF0000U)
75335 #define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT     (16U)
75336 /*! TARGET_COUNT - Target count for the fast clock
75337  */
75338 #define OSC_RC_400M_CTRL1_TARGET_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
75339 /*! @} */
75340 
75341 /*! @name CTRL2 - Control Register 2 */
75342 /*! @{ */
75343 
75344 #define OSC_RC_400M_CTRL2_TUNE_BYP_MASK          (0x400U)
75345 #define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT         (10U)
75346 /*! TUNE_BYP - Bypass the tuning logic
75347  *  0b0..Use the output of tuning logic to run the oscillator
75348  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
75349  */
75350 #define OSC_RC_400M_CTRL2_TUNE_BYP(x)            (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
75351 
75352 #define OSC_RC_400M_CTRL2_TUNE_EN_MASK           (0x1000U)
75353 #define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT          (12U)
75354 /*! TUNE_EN - Freeze/Unfreeze the tuning value
75355  *  0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value
75356  *  0b1..Unfreezes and continues the tuning operation
75357  */
75358 #define OSC_RC_400M_CTRL2_TUNE_EN(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
75359 
75360 #define OSC_RC_400M_CTRL2_TUNE_START_MASK        (0x4000U)
75361 #define OSC_RC_400M_CTRL2_TUNE_START_SHIFT       (14U)
75362 /*! TUNE_START - Start/Stop tuning
75363  *  0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL
75364  *  0b1..Start tuning
75365  */
75366 #define OSC_RC_400M_CTRL2_TUNE_START(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
75367 
75368 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK      (0xFF000000U)
75369 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT     (24U)
75370 /*! OSC_TUNE_VAL - Program the oscillator frequency
75371  */
75372 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
75373 /*! @} */
75374 
75375 /*! @name CTRL3 - Control Register 3 */
75376 /*! @{ */
75377 
75378 #define OSC_RC_400M_CTRL3_CLR_ERR_MASK           (0x1U)
75379 #define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT          (0U)
75380 /*! CLR_ERR - Clear the error flag CLK1M_ERR
75381  *  0b0..No effect
75382  *  0b1..Clears the error flag CLK1M_ERR in status register STAT0
75383  */
75384 #define OSC_RC_400M_CTRL3_CLR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
75385 
75386 #define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK         (0x100U)
75387 #define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT        (8U)
75388 /*! EN_1M_CLK - Enable 1MHz output Clock
75389  *  0b0..Enable the output (clk_1m_out)
75390  *  0b1..Disable the output (clk_1m_out)
75391  */
75392 #define OSC_RC_400M_CTRL3_EN_1M_CLK(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
75393 
75394 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK        (0x400U)
75395 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT       (10U)
75396 /*! MUX_1M_CLK - Select free/locked 1MHz output
75397  *  0b0..Select free-running 1MHz to be put out on clk_1m_out
75398  *  0b1..Select locked 1MHz to be put out on clk_1m_out
75399  */
75400 #define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
75401 
75402 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK      (0xFFFF0000U)
75403 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT     (16U)
75404 /*! COUNT_1M_CLK - Count for the locked clk_1m_out
75405  */
75406 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
75407 /*! @} */
75408 
75409 /*! @name STAT0 - Status Register 0 */
75410 /*! @{ */
75411 
75412 #define OSC_RC_400M_STAT0_CLK1M_ERR_MASK         (0x1U)
75413 #define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT        (0U)
75414 /*! CLK1M_ERR - Error flag for clk_1m_locked
75415  *  0b0..No effect
75416  *  0b1..The count value has been reached within one divided ref_clk period
75417  */
75418 #define OSC_RC_400M_STAT0_CLK1M_ERR(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
75419 /*! @} */
75420 
75421 /*! @name STAT1 - Status Register 1 */
75422 /*! @{ */
75423 
75424 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK    (0xFFFF0000U)
75425 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
75426 /*! CURR_COUNT_VAL - Current count for the fast clock
75427  */
75428 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)      (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
75429 /*! @} */
75430 
75431 /*! @name STAT2 - Status Register 2 */
75432 /*! @{ */
75433 
75434 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
75435 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
75436 /*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator
75437  */
75438 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
75439 /*! @} */
75440 
75441 
75442 /*!
75443  * @}
75444  */ /* end of group OSC_RC_400M_Register_Masks */
75445 
75446 
75447 /* OSC_RC_400M - Peripheral instance base addresses */
75448 /** Peripheral OSC_RC_400M base address */
75449 #define OSC_RC_400M_BASE                         (0u)
75450 /** Peripheral OSC_RC_400M base pointer */
75451 #define OSC_RC_400M                              ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
75452 /** Array initializer of OSC_RC_400M peripheral base addresses */
75453 #define OSC_RC_400M_BASE_ADDRS                   { OSC_RC_400M_BASE }
75454 /** Array initializer of OSC_RC_400M peripheral base pointers */
75455 #define OSC_RC_400M_BASE_PTRS                    { OSC_RC_400M }
75456 
75457 /*!
75458  * @}
75459  */ /* end of group OSC_RC_400M_Peripheral_Access_Layer */
75460 
75461 
75462 /* ----------------------------------------------------------------------------
75463    -- OTFAD Peripheral Access Layer
75464    ---------------------------------------------------------------------------- */
75465 
75466 /*!
75467  * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
75468  * @{
75469  */
75470 
75471 /** OTFAD - Register Layout Typedef */
75472 typedef struct {
75473        uint8_t RESERVED_0[3072];
75474   __IO uint32_t CR;                                /**< Control Register, offset: 0xC00 */
75475   __IO uint32_t SR;                                /**< Status Register, offset: 0xC04 */
75476        uint8_t RESERVED_1[248];
75477   struct {                                         /* offset: 0xD00, array step: 0x40 */
75478     __IO uint32_t KEY[4];                            /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
75479     __IO uint32_t CTR[2];                            /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
75480     __IO uint32_t RGD_W0;                            /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
75481     __IO uint32_t RGD_W1;                            /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
75482          uint8_t RESERVED_0[32];
75483   } CTX[4];
75484 } OTFAD_Type;
75485 
75486 /* ----------------------------------------------------------------------------
75487    -- OTFAD Register Masks
75488    ---------------------------------------------------------------------------- */
75489 
75490 /*!
75491  * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
75492  * @{
75493  */
75494 
75495 /*! @name CR - Control Register */
75496 /*! @{ */
75497 
75498 #define OTFAD_CR_FERR_MASK                       (0x2U)
75499 #define OTFAD_CR_FERR_SHIFT                      (1U)
75500 /*! FERR - Force Error
75501  *  0b0..No effect on the SR[KBERE] indicator.
75502  *  0b1..SR[KBERR] is immediately set after a write with this data bit set.
75503  */
75504 #define OTFAD_CR_FERR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
75505 
75506 #define OTFAD_CR_FLDM_MASK                       (0x8U)
75507 #define OTFAD_CR_FLDM_SHIFT                      (3U)
75508 /*! FLDM - Force Logically Disabled Mode
75509  *  0b0..No effect on the operating mode.
75510  *  0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
75511  */
75512 #define OTFAD_CR_FLDM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
75513 
75514 #define OTFAD_CR_KBSE_MASK                       (0x10U)
75515 #define OTFAD_CR_KBSE_SHIFT                      (4U)
75516 /*! KBSE - Key Blob Scramble Enable
75517  *  0b0..Key blob KEK scrambling is disabled.
75518  *  0b1..Key blob KEK scrambling is enabled.
75519  */
75520 #define OTFAD_CR_KBSE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
75521 
75522 #define OTFAD_CR_KBPE_MASK                       (0x20U)
75523 #define OTFAD_CR_KBPE_SHIFT                      (5U)
75524 /*! KBPE - Key Blob Processing Enable
75525  *  0b0..Key blob processing is disabled.
75526  *  0b1..Key blob processing is enabled.
75527  */
75528 #define OTFAD_CR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
75529 
75530 #define OTFAD_CR_RRAE_MASK                       (0x80U)
75531 #define OTFAD_CR_RRAE_SHIFT                      (7U)
75532 /*! RRAE - Restricted Register Access Enable
75533  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
75534  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
75535  */
75536 #define OTFAD_CR_RRAE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
75537 
75538 #define OTFAD_CR_SKBP_MASK                       (0x40000000U)
75539 #define OTFAD_CR_SKBP_SHIFT                      (30U)
75540 /*! SKBP - Start key blob processing
75541  *  0b0..Key blob processing is not initiated.
75542  *  0b1..Properly-enabled key blob processing is initiated.
75543  */
75544 #define OTFAD_CR_SKBP(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
75545 
75546 #define OTFAD_CR_GE_MASK                         (0x80000000U)
75547 #define OTFAD_CR_GE_SHIFT                        (31U)
75548 /*! GE - Global OTFAD Enable
75549  *  0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
75550  *  0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
75551  */
75552 #define OTFAD_CR_GE(x)                           (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
75553 /*! @} */
75554 
75555 /*! @name SR - Status Register */
75556 /*! @{ */
75557 
75558 #define OTFAD_SR_KBERR_MASK                      (0x1U)
75559 #define OTFAD_SR_KBERR_SHIFT                     (0U)
75560 /*! KBERR - Key Blob Error
75561  *  0b0..No key blob error detected.
75562  *  0b1..One or more key blob errors has been detected.
75563  */
75564 #define OTFAD_SR_KBERR(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
75565 
75566 #define OTFAD_SR_MDPCP_MASK                      (0x2U)
75567 #define OTFAD_SR_MDPCP_SHIFT                     (1U)
75568 /*! MDPCP - MDPC Present
75569  */
75570 #define OTFAD_SR_MDPCP(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
75571 
75572 #define OTFAD_SR_MODE_MASK                       (0xCU)
75573 #define OTFAD_SR_MODE_SHIFT                      (2U)
75574 /*! MODE - Operating Mode
75575  *  0b00..Operating in Normal mode (NRM)
75576  *  0b01..Unused (reserved)
75577  *  0b10..Unused (reserved)
75578  *  0b11..Operating in Logically Disabled Mode (LDM)
75579  */
75580 #define OTFAD_SR_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
75581 
75582 #define OTFAD_SR_NCTX_MASK                       (0xF0U)
75583 #define OTFAD_SR_NCTX_SHIFT                      (4U)
75584 /*! NCTX - Number of Contexts
75585  */
75586 #define OTFAD_SR_NCTX(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
75587 
75588 #define OTFAD_SR_CTXER0_MASK                     (0x100U)
75589 #define OTFAD_SR_CTXER0_SHIFT                    (8U)
75590 /*! CTXER0 - Context Error
75591  *  0b0..No key blob error was detected for context "n".
75592  *  0b1..A key blob integrity error might have been detected in context "n".
75593  */
75594 #define OTFAD_SR_CTXER0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
75595 
75596 #define OTFAD_SR_CTXER1_MASK                     (0x200U)
75597 #define OTFAD_SR_CTXER1_SHIFT                    (9U)
75598 /*! CTXER1 - Context Error
75599  *  0b0..No key blob error was detected for context "n".
75600  *  0b1..A key blob integrity error might have been detected in context "n".
75601  */
75602 #define OTFAD_SR_CTXER1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
75603 
75604 #define OTFAD_SR_CTXER2_MASK                     (0x400U)
75605 #define OTFAD_SR_CTXER2_SHIFT                    (10U)
75606 /*! CTXER2 - Context Error
75607  *  0b0..No key blob error was detected for context "n".
75608  *  0b1..A key blob integrity error might have been detected in context "n".
75609  */
75610 #define OTFAD_SR_CTXER2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
75611 
75612 #define OTFAD_SR_CTXER3_MASK                     (0x800U)
75613 #define OTFAD_SR_CTXER3_SHIFT                    (11U)
75614 /*! CTXER3 - Context Error
75615  *  0b0..No key blob error was detected for context "n".
75616  *  0b1..A key blob integrity error might have been detected in context "n".
75617  */
75618 #define OTFAD_SR_CTXER3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
75619 
75620 #define OTFAD_SR_CTXIE0_MASK                     (0x10000U)
75621 #define OTFAD_SR_CTXIE0_SHIFT                    (16U)
75622 /*! CTXIE0 - Context Integrity Error
75623  *  0b0..No key blob integrity error was detected for context "n".
75624  *  0b1..A key blob integrity error was detected in context "n".
75625  */
75626 #define OTFAD_SR_CTXIE0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
75627 
75628 #define OTFAD_SR_CTXIE1_MASK                     (0x20000U)
75629 #define OTFAD_SR_CTXIE1_SHIFT                    (17U)
75630 /*! CTXIE1 - Context Integrity Error
75631  *  0b0..No key blob integrity error was detected for context "n".
75632  *  0b1..A key blob integrity error was detected in context "n".
75633  */
75634 #define OTFAD_SR_CTXIE1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
75635 
75636 #define OTFAD_SR_CTXIE2_MASK                     (0x40000U)
75637 #define OTFAD_SR_CTXIE2_SHIFT                    (18U)
75638 /*! CTXIE2 - Context Integrity Error
75639  *  0b0..No key blob integrity error was detected for context "n".
75640  *  0b1..A key blob integrity error was detected in context "n".
75641  */
75642 #define OTFAD_SR_CTXIE2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
75643 
75644 #define OTFAD_SR_CTXIE3_MASK                     (0x80000U)
75645 #define OTFAD_SR_CTXIE3_SHIFT                    (19U)
75646 /*! CTXIE3 - Context Integrity Error
75647  *  0b0..No key blob integrity error was detected for context "n".
75648  *  0b1..A key blob integrity error was detected in context "n".
75649  */
75650 #define OTFAD_SR_CTXIE3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
75651 
75652 #define OTFAD_SR_HRL_MASK                        (0xF000000U)
75653 #define OTFAD_SR_HRL_SHIFT                       (24U)
75654 /*! HRL - Hardware Revision Level
75655  */
75656 #define OTFAD_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
75657 
75658 #define OTFAD_SR_RRAM_MASK                       (0x10000000U)
75659 #define OTFAD_SR_RRAM_SHIFT                      (28U)
75660 /*! RRAM - Restricted Register Access Mode
75661  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
75662  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
75663  */
75664 #define OTFAD_SR_RRAM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
75665 
75666 #define OTFAD_SR_GEM_MASK                        (0x20000000U)
75667 #define OTFAD_SR_GEM_SHIFT                       (29U)
75668 /*! GEM - Global Enable Mode
75669  *  0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
75670  *  0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
75671  */
75672 #define OTFAD_SR_GEM(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
75673 
75674 #define OTFAD_SR_KBPE_MASK                       (0x40000000U)
75675 #define OTFAD_SR_KBPE_SHIFT                      (30U)
75676 /*! KBPE - Key Blob Processing Enable
75677  *  0b0..Key blob processing is not enabled.
75678  *  0b1..Key blob processing is enabled.
75679  */
75680 #define OTFAD_SR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
75681 
75682 #define OTFAD_SR_KBD_MASK                        (0x80000000U)
75683 #define OTFAD_SR_KBD_SHIFT                       (31U)
75684 /*! KBD - Key Blob Processing Done
75685  *  0b0..Key blob processing was not enabled, or is not complete.
75686  *  0b1..Key blob processing was enabled and is complete.
75687  */
75688 #define OTFAD_SR_KBD(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
75689 /*! @} */
75690 
75691 /*! @name KEY - AES Key Word */
75692 /*! @{ */
75693 
75694 #define OTFAD_KEY_KEY_MASK                       (0xFFFFFFFFU)
75695 #define OTFAD_KEY_KEY_SHIFT                      (0U)
75696 /*! KEY - AES Key
75697  */
75698 #define OTFAD_KEY_KEY(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
75699 /*! @} */
75700 
75701 /* The count of OTFAD_KEY */
75702 #define OTFAD_KEY_COUNT                          (4U)
75703 
75704 /* The count of OTFAD_KEY */
75705 #define OTFAD_KEY_COUNT2                         (4U)
75706 
75707 /*! @name CTR - AES Counter Word */
75708 /*! @{ */
75709 
75710 #define OTFAD_CTR_CTR_MASK                       (0xFFFFFFFFU)
75711 #define OTFAD_CTR_CTR_SHIFT                      (0U)
75712 /*! CTR - AES Counter
75713  */
75714 #define OTFAD_CTR_CTR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
75715 /*! @} */
75716 
75717 /* The count of OTFAD_CTR */
75718 #define OTFAD_CTR_COUNT                          (4U)
75719 
75720 /* The count of OTFAD_CTR */
75721 #define OTFAD_CTR_COUNT2                         (2U)
75722 
75723 /*! @name RGD_W0 - AES Region Descriptor Word0 */
75724 /*! @{ */
75725 
75726 #define OTFAD_RGD_W0_SRTADDR_MASK                (0xFFFFFC00U)
75727 #define OTFAD_RGD_W0_SRTADDR_SHIFT               (10U)
75728 /*! SRTADDR - Start Address
75729  */
75730 #define OTFAD_RGD_W0_SRTADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
75731 /*! @} */
75732 
75733 /* The count of OTFAD_RGD_W0 */
75734 #define OTFAD_RGD_W0_COUNT                       (4U)
75735 
75736 /*! @name RGD_W1 - AES Region Descriptor Word1 */
75737 /*! @{ */
75738 
75739 #define OTFAD_RGD_W1_VLD_MASK                    (0x1U)
75740 #define OTFAD_RGD_W1_VLD_SHIFT                   (0U)
75741 /*! VLD - Valid
75742  *  0b0..Context is invalid.
75743  *  0b1..Context is valid.
75744  */
75745 #define OTFAD_RGD_W1_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
75746 
75747 #define OTFAD_RGD_W1_ADE_MASK                    (0x2U)
75748 #define OTFAD_RGD_W1_ADE_SHIFT                   (1U)
75749 /*! ADE - AES Decryption Enable.
75750  *  0b0..Bypass the fetched data.
75751  *  0b1..Perform the CTR-AES128 mode decryption on the fetched data.
75752  */
75753 #define OTFAD_RGD_W1_ADE(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
75754 
75755 #define OTFAD_RGD_W1_RO_MASK                     (0x4U)
75756 #define OTFAD_RGD_W1_RO_SHIFT                    (2U)
75757 /*! RO - Read-Only
75758  *  0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
75759  *  0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
75760  */
75761 #define OTFAD_RGD_W1_RO(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
75762 
75763 #define OTFAD_RGD_W1_ENDADDR_MASK                (0xFFFFFC00U)
75764 #define OTFAD_RGD_W1_ENDADDR_SHIFT               (10U)
75765 /*! ENDADDR - End Address
75766  */
75767 #define OTFAD_RGD_W1_ENDADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
75768 /*! @} */
75769 
75770 /* The count of OTFAD_RGD_W1 */
75771 #define OTFAD_RGD_W1_COUNT                       (4U)
75772 
75773 
75774 /*!
75775  * @}
75776  */ /* end of group OTFAD_Register_Masks */
75777 
75778 
75779 /* OTFAD - Peripheral instance base addresses */
75780 /** Peripheral OTFAD1 base address */
75781 #define OTFAD1_BASE                              (0x400CC000u)
75782 /** Peripheral OTFAD1 base pointer */
75783 #define OTFAD1                                   ((OTFAD_Type *)OTFAD1_BASE)
75784 /** Peripheral OTFAD2 base address */
75785 #define OTFAD2_BASE                              (0x400D0000u)
75786 /** Peripheral OTFAD2 base pointer */
75787 #define OTFAD2                                   ((OTFAD_Type *)OTFAD2_BASE)
75788 /** Array initializer of OTFAD peripheral base addresses */
75789 #define OTFAD_BASE_ADDRS                         { 0u, OTFAD1_BASE, OTFAD2_BASE }
75790 /** Array initializer of OTFAD peripheral base pointers */
75791 #define OTFAD_BASE_PTRS                          { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
75792 
75793 /*!
75794  * @}
75795  */ /* end of group OTFAD_Peripheral_Access_Layer */
75796 
75797 
75798 /* ----------------------------------------------------------------------------
75799    -- PDM Peripheral Access Layer
75800    ---------------------------------------------------------------------------- */
75801 
75802 /*!
75803  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
75804  * @{
75805  */
75806 
75807 /** PDM - Register Layout Typedef */
75808 typedef struct {
75809   __IO uint32_t CTRL_1;                            /**< PDM Control register 1, offset: 0x0 */
75810   __IO uint32_t CTRL_2;                            /**< PDM Control register 2, offset: 0x4 */
75811   __IO uint32_t STAT;                              /**< PDM Status register, offset: 0x8 */
75812        uint8_t RESERVED_0[4];
75813   __IO uint32_t FIFO_CTRL;                         /**< PDM FIFO Control register, offset: 0x10 */
75814   __IO uint32_t FIFO_STAT;                         /**< PDM FIFO Status register, offset: 0x14 */
75815        uint8_t RESERVED_1[12];
75816   __I  uint32_t DATACH[8];                         /**< PDM Output Result Register, array offset: 0x24, array step: 0x4 */
75817        uint8_t RESERVED_2[32];
75818   __IO uint32_t DC_CTRL;                           /**< PDM DC Remover Control register, offset: 0x64 */
75819        uint8_t RESERVED_3[12];
75820   __IO uint32_t RANGE_CTRL;                        /**< PDM Range Control register, offset: 0x74 */
75821        uint8_t RESERVED_4[4];
75822   __IO uint32_t RANGE_STAT;                        /**< PDM Range Status register, offset: 0x7C */
75823        uint8_t RESERVED_5[16];
75824   __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control register, offset: 0x90 */
75825   __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control register, offset: 0x94 */
75826   __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status register, offset: 0x98 */
75827   __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
75828   __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
75829   __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
75830   __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
75831 } PDM_Type;
75832 
75833 /* ----------------------------------------------------------------------------
75834    -- PDM Register Masks
75835    ---------------------------------------------------------------------------- */
75836 
75837 /*!
75838  * @addtogroup PDM_Register_Masks PDM Register Masks
75839  * @{
75840  */
75841 
75842 /*! @name CTRL_1 - PDM Control register 1 */
75843 /*! @{ */
75844 
75845 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
75846 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
75847 /*! CH0EN - Channel 0 Enable
75848  */
75849 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
75850 
75851 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
75852 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
75853 /*! CH1EN - Channel 1 Enable
75854  */
75855 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
75856 
75857 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
75858 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
75859 /*! CH2EN - Channel 2 Enable
75860  */
75861 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
75862 
75863 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
75864 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
75865 /*! CH3EN - Channel 3 Enable
75866  */
75867 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
75868 
75869 #define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
75870 #define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
75871 /*! CH4EN - Channel 4 Enable
75872  */
75873 #define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
75874 
75875 #define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
75876 #define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
75877 /*! CH5EN - Channel 5 Enable
75878  */
75879 #define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
75880 
75881 #define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
75882 #define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
75883 /*! CH6EN - Channel 6 Enable
75884  */
75885 #define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
75886 
75887 #define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
75888 #define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
75889 /*! CH7EN - Channel 7 Enable
75890  */
75891 #define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
75892 
75893 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
75894 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
75895 /*! ERREN - Error Interruption Enable
75896  *  0b0..Error Interrupts disabled
75897  *  0b1..Error Interrupts enabled
75898  */
75899 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
75900 
75901 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
75902 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
75903 /*! DISEL - DMA Interrupt Selection
75904  *  0b00..DMA and interrupt requests disabled
75905  *  0b01..DMA requests enabled
75906  *  0b10..Interrupt requests enabled
75907  *  0b11..Reserved
75908  */
75909 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
75910 
75911 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
75912 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
75913 /*! DBGE - Module Enable in Debug
75914  *  0b0..Disabled after completing the current frame
75915  *  0b1..Enabled
75916  */
75917 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
75918 
75919 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
75920 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
75921 /*! SRES - Software-reset bit
75922  *  0b0..No action
75923  *  0b1..Software reset
75924  */
75925 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
75926 
75927 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
75928 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
75929 /*! DBG - Debug Mode
75930  *  0b0..Normal Mode
75931  *  0b1..Debug Mode
75932  */
75933 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
75934 
75935 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
75936 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
75937 /*! PDMIEN - PDM Enable
75938  *  0b0..PDM stopped
75939  *  0b1..PDM operation started
75940  */
75941 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
75942 
75943 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
75944 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
75945 /*! DOZEN - DOZE enable
75946  */
75947 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
75948 
75949 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
75950 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
75951 /*! MDIS - Module Disable
75952  *  0b0..Normal Mode
75953  *  0b1..Disable/Low Leakage Mode
75954  */
75955 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
75956 /*! @} */
75957 
75958 /*! @name CTRL_2 - PDM Control register 2 */
75959 /*! @{ */
75960 
75961 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
75962 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
75963 /*! CLKDIV - Clock Divider
75964  */
75965 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
75966 
75967 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
75968 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
75969 /*! CICOSR - CIC Decimation Rate
75970  */
75971 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
75972 
75973 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
75974 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
75975 /*! QSEL - Quality Mode
75976  *  0b001..High quality mode
75977  *  0b000..Medium quality mode
75978  *  0b111..Low quality mode
75979  *  0b110..Very low quality 0 mode
75980  *  0b101..Very low quality 1 mode
75981  *  0b100..Very low quality 2 mode
75982  */
75983 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
75984 /*! @} */
75985 
75986 /*! @name STAT - PDM Status register */
75987 /*! @{ */
75988 
75989 #define PDM_STAT_CH0F_MASK                       (0x1U)
75990 #define PDM_STAT_CH0F_SHIFT                      (0U)
75991 /*! CH0F - Channel 0 Output Data Flag
75992  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
75993  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
75994  */
75995 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
75996 
75997 #define PDM_STAT_CH1F_MASK                       (0x2U)
75998 #define PDM_STAT_CH1F_SHIFT                      (1U)
75999 /*! CH1F - Channel 1 Output Data Flag
76000  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76001  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76002  */
76003 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
76004 
76005 #define PDM_STAT_CH2F_MASK                       (0x4U)
76006 #define PDM_STAT_CH2F_SHIFT                      (2U)
76007 /*! CH2F - Channel 2 Output Data Flag
76008  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76009  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76010  */
76011 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
76012 
76013 #define PDM_STAT_CH3F_MASK                       (0x8U)
76014 #define PDM_STAT_CH3F_SHIFT                      (3U)
76015 /*! CH3F - Channel 3 Output Data Flag
76016  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76017  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76018  */
76019 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
76020 
76021 #define PDM_STAT_CH4F_MASK                       (0x10U)
76022 #define PDM_STAT_CH4F_SHIFT                      (4U)
76023 /*! CH4F - Channel 4 Output Data Flag
76024  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76025  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76026  */
76027 #define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
76028 
76029 #define PDM_STAT_CH5F_MASK                       (0x20U)
76030 #define PDM_STAT_CH5F_SHIFT                      (5U)
76031 /*! CH5F - Channel 5 Output Data Flag
76032  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76033  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76034  */
76035 #define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
76036 
76037 #define PDM_STAT_CH6F_MASK                       (0x40U)
76038 #define PDM_STAT_CH6F_SHIFT                      (6U)
76039 /*! CH6F - Channel 6 Output Data Flag
76040  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76041  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76042  */
76043 #define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
76044 
76045 #define PDM_STAT_CH7F_MASK                       (0x80U)
76046 #define PDM_STAT_CH7F_SHIFT                      (7U)
76047 /*! CH7F - Channel 7 Output Data Flag
76048  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
76049  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
76050  */
76051 #define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
76052 
76053 #define PDM_STAT_LOWFREQF_MASK                   (0x20000000U)
76054 #define PDM_STAT_LOWFREQF_SHIFT                  (29U)
76055 /*! LOWFREQF - Low Frequency Flag
76056  *  0b0..CLKDIV value is OK
76057  *  0b1..CLKDIV value is too low
76058  */
76059 #define PDM_STAT_LOWFREQF(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
76060 
76061 #define PDM_STAT_FIR_RDY_MASK                    (0x40000000U)
76062 #define PDM_STAT_FIR_RDY_SHIFT                   (30U)
76063 /*! FIR_RDY - Filter Data Ready
76064  *  0b0..Filter data is not reliable
76065  *  0b1..Filter data is reliable
76066  */
76067 #define PDM_STAT_FIR_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
76068 
76069 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
76070 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
76071 /*! BSY_FIL - Busy Flag
76072  *  0b1..PDM is running
76073  *  0b0..PDM is stopped
76074  */
76075 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
76076 /*! @} */
76077 
76078 /*! @name FIFO_CTRL - PDM FIFO Control register */
76079 /*! @{ */
76080 
76081 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
76082 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
76083 /*! FIFOWMK - FIFO Watermark Control
76084  */
76085 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
76086 /*! @} */
76087 
76088 /*! @name FIFO_STAT - PDM FIFO Status register */
76089 /*! @{ */
76090 
76091 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
76092 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
76093 /*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
76094  *  0b0..No exception by FIFO overflow
76095  *  0b1..Exception by FIFO overflow
76096  */
76097 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
76098 
76099 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
76100 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
76101 /*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
76102  *  0b0..No exception by FIFO overflow
76103  *  0b1..Exception by FIFO overflow
76104  */
76105 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
76106 
76107 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
76108 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
76109 /*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
76110  *  0b0..No exception by FIFO overflow
76111  *  0b1..Exception by FIFO overflow
76112  */
76113 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
76114 
76115 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
76116 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
76117 /*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
76118  *  0b0..No exception by FIFO overflow
76119  *  0b1..Exception by FIFO overflow
76120  */
76121 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
76122 
76123 #define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
76124 #define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
76125 /*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
76126  *  0b0..No exception by FIFO overflow
76127  *  0b1..Exception by FIFO overflow
76128  */
76129 #define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
76130 
76131 #define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
76132 #define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
76133 /*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
76134  *  0b0..No exception by FIFO overflow
76135  *  0b1..Exception by FIFO overflow
76136  */
76137 #define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
76138 
76139 #define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
76140 #define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
76141 /*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
76142  *  0b0..No exception by FIFO overflow
76143  *  0b1..Exception by FIFO overflow
76144  */
76145 #define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
76146 
76147 #define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
76148 #define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
76149 /*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
76150  *  0b0..No exception by FIFO overflow
76151  *  0b1..Exception by FIFO overflow
76152  */
76153 #define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
76154 
76155 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
76156 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
76157 /*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
76158  *  0b0..No exception by FIFO Underflow
76159  *  0b1..Exception by FIFO underflow
76160  */
76161 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
76162 
76163 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
76164 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
76165 /*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
76166  *  0b0..No exception by FIFO Underflow
76167  *  0b1..Exception by FIFO underflow
76168  */
76169 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
76170 
76171 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
76172 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
76173 /*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
76174  *  0b0..No exception by FIFO Underflow
76175  *  0b1..Exception by FIFO underflow
76176  */
76177 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
76178 
76179 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
76180 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
76181 /*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
76182  *  0b0..No exception by FIFO Underflow
76183  *  0b1..Exception by FIFO underflow
76184  */
76185 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
76186 
76187 #define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
76188 #define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
76189 /*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
76190  *  0b0..No exception by FIFO Underflow
76191  *  0b1..Exception by FIFO underflow
76192  */
76193 #define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
76194 
76195 #define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
76196 #define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
76197 /*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
76198  *  0b0..No exception by FIFO Underflow
76199  *  0b1..Exception by FIFO underflow
76200  */
76201 #define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
76202 
76203 #define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
76204 #define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
76205 /*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
76206  *  0b0..No exception by FIFO Underflow
76207  *  0b1..Exception by FIFO underflow
76208  */
76209 #define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
76210 
76211 #define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
76212 #define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
76213 /*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
76214  *  0b0..No exception by FIFO Underflow
76215  *  0b1..Exception by FIFO underflow
76216  */
76217 #define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
76218 /*! @} */
76219 
76220 /*! @name DATACH - PDM Output Result Register */
76221 /*! @{ */
76222 
76223 #define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
76224 #define PDM_DATACH_DATA_SHIFT                    (0U)
76225 /*! DATA - Channel n Data
76226  */
76227 #define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
76228 /*! @} */
76229 
76230 /* The count of PDM_DATACH */
76231 #define PDM_DATACH_COUNT                         (8U)
76232 
76233 /*! @name DC_CTRL - PDM DC Remover Control register */
76234 /*! @{ */
76235 
76236 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
76237 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
76238 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
76239  *  0b11..DC Remover is bypassed
76240  *  0b00..DC Remover cut-off at 21Hz
76241  *  0b01..DC Remover cut-off at 83Hz
76242  *  0b10..DC Remover cut-off at 152Hz
76243  */
76244 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
76245 
76246 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
76247 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
76248 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
76249  *  0b11..DC Remover is bypassed
76250  *  0b00..DC Remover cut-off at 21Hz
76251  *  0b01..DC Remover cut-off at 83Hz
76252  *  0b10..DC Remover cut-off at 152Hz
76253  */
76254 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
76255 
76256 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
76257 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
76258 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
76259  *  0b11..DC Remover is bypassed
76260  *  0b00..DC Remover cut-off at 21Hz
76261  *  0b01..DC Remover cut-off at 83Hz
76262  *  0b10..DC Remover cut-off at 152Hz
76263  */
76264 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
76265 
76266 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
76267 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
76268 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
76269  *  0b11..DC Remover is bypassed
76270  *  0b00..DC Remover cut-off at 21Hz
76271  *  0b01..DC Remover cut-off at 83Hz
76272  *  0b10..DC Remover cut-off at 152Hz
76273  */
76274 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
76275 
76276 #define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
76277 #define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
76278 /*! DCCONFIG4 - Channel 4 DC Remover Configuration
76279  *  0b11..DC Remover is bypassed
76280  *  0b00..DC Remover cut-off at 21Hz
76281  *  0b01..DC Remover cut-off at 83Hz
76282  *  0b10..DC Remover cut-off at 152Hz
76283  */
76284 #define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
76285 
76286 #define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
76287 #define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
76288 /*! DCCONFIG5 - Channel 5 DC Remover Configuration
76289  *  0b11..DC Remover is bypassed
76290  *  0b00..DC Remover cut-off at 21Hz
76291  *  0b01..DC Remover cut-off at 83Hz
76292  *  0b10..DC Remover cut-off at 152Hz
76293  */
76294 #define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
76295 
76296 #define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
76297 #define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
76298 /*! DCCONFIG6 - Channel 6 DC Remover Configuration
76299  *  0b11..DC Remover is bypassed
76300  *  0b00..DC Remover cut-off at 21Hz
76301  *  0b01..DC Remover cut-off at 83Hz
76302  *  0b10..DC Remover cut-off at 152Hz
76303  */
76304 #define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
76305 
76306 #define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
76307 #define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
76308 /*! DCCONFIG7 - Channel 7 DC Remover Configuration
76309  *  0b11..DC Remover is bypassed
76310  *  0b00..DC Remover cut-off at 21Hz
76311  *  0b01..DC Remover cut-off at 83Hz
76312  *  0b10..DC Remover cut-off at 152Hz
76313  */
76314 #define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
76315 /*! @} */
76316 
76317 /*! @name RANGE_CTRL - PDM Range Control register */
76318 /*! @{ */
76319 
76320 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
76321 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
76322 /*! RANGEADJ0 - Channel 0 Range Adjustment
76323  */
76324 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
76325 
76326 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
76327 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
76328 /*! RANGEADJ1 - Channel 1 Range Adjustment
76329  */
76330 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
76331 
76332 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
76333 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
76334 /*! RANGEADJ2 - Channel 2 Range Adjustment
76335  */
76336 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
76337 
76338 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
76339 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
76340 /*! RANGEADJ3 - Channel 3 Range Adjustment
76341  */
76342 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
76343 
76344 #define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
76345 #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
76346 /*! RANGEADJ4 - Channel 4 Range Adjustment
76347  */
76348 #define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
76349 
76350 #define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
76351 #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
76352 /*! RANGEADJ5 - Channel 5 Range Adjustment
76353  */
76354 #define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
76355 
76356 #define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
76357 #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
76358 /*! RANGEADJ6 - Channel 6 Range Adjustment
76359  */
76360 #define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
76361 
76362 #define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
76363 #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
76364 /*! RANGEADJ7 - Channel 7 Range Adjustment
76365  */
76366 #define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
76367 /*! @} */
76368 
76369 /*! @name RANGE_STAT - PDM Range Status register */
76370 /*! @{ */
76371 
76372 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
76373 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
76374 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
76375  *  0b0..No exception by range overflow
76376  *  0b1..Exception by range overflow
76377  */
76378 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
76379 
76380 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
76381 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
76382 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
76383  *  0b0..No exception by range overflow
76384  *  0b1..Exception by range overflow
76385  */
76386 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
76387 
76388 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
76389 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
76390 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
76391  *  0b0..No exception by range overflow
76392  *  0b1..Exception by range overflow
76393  */
76394 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
76395 
76396 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
76397 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
76398 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
76399  *  0b0..No exception by range overflow
76400  *  0b1..Exception by range overflow
76401  */
76402 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
76403 
76404 #define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
76405 #define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
76406 /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
76407  *  0b0..No exception by range overflow
76408  *  0b1..Exception by range overflow
76409  */
76410 #define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
76411 
76412 #define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
76413 #define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
76414 /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
76415  *  0b0..No exception by range overflow
76416  *  0b1..Exception by range overflow
76417  */
76418 #define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
76419 
76420 #define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
76421 #define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
76422 /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
76423  *  0b0..No exception by range overflow
76424  *  0b1..Exception by range overflow
76425  */
76426 #define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
76427 
76428 #define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
76429 #define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
76430 /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
76431  *  0b0..No exception by range overflow
76432  *  0b1..Exception by range overflow
76433  */
76434 #define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
76435 
76436 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
76437 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
76438 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
76439  *  0b0..No exception by range underflow
76440  *  0b1..Exception by range underflow
76441  */
76442 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
76443 
76444 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
76445 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
76446 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
76447  *  0b0..No exception by range underflow
76448  *  0b1..Exception by range underflow
76449  */
76450 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
76451 
76452 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
76453 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
76454 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
76455  *  0b0..No exception by range underflow
76456  *  0b1..Exception by range underflow
76457  */
76458 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
76459 
76460 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
76461 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
76462 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
76463  *  0b0..No exception by range underflow
76464  *  0b1..Exception by range underflow
76465  */
76466 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
76467 
76468 #define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
76469 #define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
76470 /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
76471  *  0b0..No exception by range underflow
76472  *  0b1..Exception by range underflow
76473  */
76474 #define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
76475 
76476 #define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
76477 #define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
76478 /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
76479  *  0b0..No exception by range underflow
76480  *  0b1..Exception by range underflow
76481  */
76482 #define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
76483 
76484 #define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
76485 #define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
76486 /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
76487  *  0b0..No exception by range underflow
76488  *  0b1..Exception by range underflow
76489  */
76490 #define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
76491 
76492 #define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
76493 #define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
76494 /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
76495  *  0b0..No exception by range underflow
76496  *  0b1..Exception by range underflow
76497  */
76498 #define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
76499 /*! @} */
76500 
76501 /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
76502 /*! @{ */
76503 
76504 #define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
76505 #define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
76506 /*! VADEN - Voice Activity Detector Enable
76507  *  0b0..The HWVAD is disabled
76508  *  0b1..The HWVAD is enabled
76509  */
76510 #define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
76511 
76512 #define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
76513 #define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
76514 /*! VADRST - Voice Activity Detector Reset
76515  */
76516 #define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
76517 
76518 #define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
76519 #define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
76520 /*! VADIE - Voice Activity Detector Interruption Enable
76521  *  0b0..HWVAD Interrupts disabled
76522  *  0b1..HWVAD Interrupts enabled
76523  */
76524 #define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
76525 
76526 #define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
76527 #define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
76528 /*! VADERIE - Voice Activity Detector Error Interruption Enable
76529  *  0b0..HWVAD Error Interrupts disabled
76530  *  0b1..HWVAD Error Interrupts enabled
76531  */
76532 #define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
76533 
76534 #define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
76535 #define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
76536 /*! VADST10 - Voice Activity Detector Internal Filters Initialization
76537  *  0b0..Normal operation.
76538  *  0b1..Filters are initialized.
76539  */
76540 #define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
76541 
76542 #define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
76543 #define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
76544 /*! VADINITT - Voice Activity Detector Initialization Time
76545  */
76546 #define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
76547 
76548 #define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
76549 #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
76550 /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate
76551  */
76552 #define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
76553 
76554 #define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
76555 #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
76556 /*! VADCHSEL - Voice Activity Detector Channel Selector
76557  */
76558 #define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
76559 /*! @} */
76560 
76561 /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
76562 /*! @{ */
76563 
76564 #define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
76565 #define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
76566 /*! VADHPF - Voice Activity Detector High-Pass Filter
76567  *  0b00..Filter bypassed.
76568  *  0b01..Cut-off frequency at 1750Hz.
76569  *  0b10..Cut-off frequency at 215Hz.
76570  *  0b11..Cut-off frequency at 102Hz.
76571  */
76572 #define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
76573 
76574 #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
76575 #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
76576 /*! VADINPGAIN - Voice Activity Detector Input Gain
76577  */
76578 #define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
76579 
76580 #define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
76581 #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
76582 /*! VADFRAMET - Voice Activity Detector Frame Time
76583  */
76584 #define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
76585 
76586 #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
76587 #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
76588 /*! VADFOUTDIS - Voice Activity Detector Force Output Disable
76589  *  0b0..Output is enabled.
76590  *  0b1..Output is disabled.
76591  */
76592 #define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
76593 
76594 #define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
76595 #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
76596 /*! VADPREFEN - Voice Activity Detector Pre Filter Enable
76597  *  0b0..Pre-filter is bypassed.
76598  *  0b1..Pre-filter is enabled.
76599  */
76600 #define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
76601 
76602 #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
76603 #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
76604 /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
76605  *  0b1..Frame energy calculus disabled.
76606  *  0b0..Frame energy calculus enabled.
76607  */
76608 #define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
76609 /*! @} */
76610 
76611 /*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
76612 /*! @{ */
76613 
76614 #define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
76615 #define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
76616 /*! VADIF - Voice Activity Detector Interrupt Flag
76617  *  0b0..Voice activity not detected
76618  *  0b1..Voice activity detected
76619  */
76620 #define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
76621 
76622 #define PDM_VAD0_STAT_VADEF_MASK                 (0x8000U)
76623 #define PDM_VAD0_STAT_VADEF_SHIFT                (15U)
76624 /*! VADEF - Voice Activity Detector Event Flag
76625  *  0b0..Voice activity not detected
76626  *  0b1..Voice activity detected
76627  */
76628 #define PDM_VAD0_STAT_VADEF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
76629 
76630 #define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
76631 #define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
76632 /*! VADINSATF - Voice Activity Detector Input Saturation Flag
76633  *  0b0..No exception
76634  *  0b1..Exception
76635  */
76636 #define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
76637 
76638 #define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
76639 #define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
76640 /*! VADINITF - Voice Activity Detector Initialization Flag
76641  *  0b0..HWVAD is not being initialized.
76642  *  0b1..HWVAD is being initialized.
76643  */
76644 #define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
76645 /*! @} */
76646 
76647 /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
76648 /*! @{ */
76649 
76650 #define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
76651 #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
76652 /*! VADSGAIN - Voice Activity Detector Signal Gain
76653  */
76654 #define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
76655 
76656 #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
76657 #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
76658 /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
76659  *  0b0..Maximum block is bypassed.
76660  *  0b1..Maximum block is enabled.
76661  */
76662 #define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
76663 
76664 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
76665 #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
76666 /*! VADSFILEN - Voice Activity Detector Signal Filter Enable
76667  *  0b0..Signal filter is disabled.
76668  *  0b1..Signal filter is enabled.
76669  */
76670 #define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
76671 /*! @} */
76672 
76673 /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
76674 /*! @{ */
76675 
76676 #define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
76677 #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
76678 /*! VADNGAIN - Voice Activity Detector Noise Gain
76679  */
76680 #define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
76681 
76682 #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
76683 #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
76684 /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment
76685  */
76686 #define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
76687 
76688 #define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
76689 #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
76690 /*! VADNOREN - Voice Activity Detector Noise OR Enable
76691  *  0b0..Noise input is not decimated.
76692  *  0b1..Noise input is decimated.
76693  */
76694 #define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
76695 
76696 #define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
76697 #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
76698 /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
76699  *  0b0..Noise input is not decimated.
76700  *  0b1..Noise input is decimated.
76701  */
76702 #define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
76703 
76704 #define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
76705 #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
76706 /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
76707  *  0b0..Minimum block is bypassed.
76708  *  0b1..Minimum block is enabled.
76709  */
76710 #define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
76711 
76712 #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
76713 #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
76714 /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
76715  *  0b0..Noise filter is always enabled.
76716  *  0b1..Noise filter is enabled/disabled based on voice activity information.
76717  */
76718 #define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
76719 /*! @} */
76720 
76721 /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
76722 /*! @{ */
76723 
76724 #define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
76725 #define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
76726 /*! VADNDATA - Voice Activity Detector Noise Data
76727  */
76728 #define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
76729 /*! @} */
76730 
76731 /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
76732 /*! @{ */
76733 
76734 #define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
76735 #define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
76736 /*! VADZCDEN - Zero-Crossing Detector Enable
76737  *  0b0..The ZCD is disabled
76738  *  0b1..The ZCD is enabled
76739  */
76740 #define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
76741 
76742 #define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
76743 #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
76744 /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
76745  *  0b0..The ZCD threshold is not estimated automatically
76746  *  0b1..The ZCD threshold is estimated automatically
76747  */
76748 #define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
76749 
76750 #define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
76751 #define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
76752 /*! VADZCDAND - Zero-Crossing Detector AND Behavior
76753  *  0b0..The ZCD result is OR'ed with the energy-based detection.
76754  *  0b1..The ZCD result is AND'ed with the energy-based detection.
76755  */
76756 #define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
76757 
76758 #define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
76759 #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
76760 /*! VADZCDADJ - Zero-Crossing Detector Adjustment
76761  */
76762 #define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
76763 
76764 #define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
76765 #define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
76766 /*! VADZCDTH - Zero-Crossing Detector Threshold
76767  */
76768 #define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
76769 /*! @} */
76770 
76771 
76772 /*!
76773  * @}
76774  */ /* end of group PDM_Register_Masks */
76775 
76776 
76777 /* PDM - Peripheral instance base addresses */
76778 /** Peripheral PDM base address */
76779 #define PDM_BASE                                 (0x40C20000u)
76780 /** Peripheral PDM base pointer */
76781 #define PDM                                      ((PDM_Type *)PDM_BASE)
76782 /** Array initializer of PDM peripheral base addresses */
76783 #define PDM_BASE_ADDRS                           { PDM_BASE }
76784 /** Array initializer of PDM peripheral base pointers */
76785 #define PDM_BASE_PTRS                            { PDM }
76786 
76787 /*!
76788  * @}
76789  */ /* end of group PDM_Peripheral_Access_Layer */
76790 
76791 
76792 /* ----------------------------------------------------------------------------
76793    -- PGMC_BPC Peripheral Access Layer
76794    ---------------------------------------------------------------------------- */
76795 
76796 /*!
76797  * @addtogroup PGMC_BPC_Peripheral_Access_Layer PGMC_BPC Peripheral Access Layer
76798  * @{
76799  */
76800 
76801 /** PGMC_BPC - Register Layout Typedef */
76802 typedef struct {
76803        uint8_t RESERVED_0[4];
76804   __IO uint32_t BPC_AUTHEN_CTRL;                   /**< BPC Authentication Control, offset: 0x4 */
76805        uint8_t RESERVED_1[8];
76806   __IO uint32_t BPC_MODE;                          /**< BPC Mode, offset: 0x10 */
76807   __IO uint32_t BPC_POWER_CTRL;                    /**< BPC power control, offset: 0x14 */
76808        uint8_t RESERVED_2[20];
76809   __IO uint32_t BPC_FLAG;                          /**< BPC flag, offset: 0x2C */
76810        uint8_t RESERVED_3[16];
76811   __IO uint32_t BPC_SSAR_SAVE_CTRL;                /**< BPC SSAR save control, offset: 0x40 */
76812   __IO uint32_t BPC_SSAR_RESTORE_CTRL;             /**< BPC SSAR restore control, offset: 0x44 */
76813 } PGMC_BPC_Type;
76814 
76815 /* ----------------------------------------------------------------------------
76816    -- PGMC_BPC Register Masks
76817    ---------------------------------------------------------------------------- */
76818 
76819 /*!
76820  * @addtogroup PGMC_BPC_Register_Masks PGMC_BPC Register Masks
76821  * @{
76822  */
76823 
76824 /*! @name BPC_AUTHEN_CTRL - BPC Authentication Control */
76825 /*! @{ */
76826 
76827 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK       (0x1U)
76828 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT      (0U)
76829 /*! USER - Allow user mode access
76830  *  0b0..Allow only privilege mode to access basic power control registers
76831  *  0b1..Allow both privilege and user mode to access basic power control registers
76832  */
76833 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK)
76834 
76835 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
76836 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
76837 /*! NONSECURE - Allow non-secure mode access
76838  *  0b0..Allow only secure mode to access basic power control registers
76839  *  0b1..Allow both secure and non-secure mode to access basic power control registers
76840  */
76841 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK)
76842 
76843 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
76844 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
76845 /*! LOCK_SETTING - Lock NONSECURE and USER
76846  */
76847 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
76848 
76849 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
76850 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
76851 /*! WHITE_LIST - Domain ID white list
76852  */
76853 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)
76854 
76855 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
76856 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
76857 /*! LOCK_LIST - White list lock
76858  */
76859 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK)
76860 
76861 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
76862 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
76863 /*! LOCK_CFG - Configuration lock
76864  */
76865 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK)
76866 /*! @} */
76867 
76868 /*! @name BPC_MODE - BPC Mode */
76869 /*! @{ */
76870 
76871 #define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK         (0x3U)
76872 #define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT        (0U)
76873 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
76874  *  0b00..Not affected by any low power mode
76875  *  0b01..Controlled by CPU power mode of the domain
76876  *  0b10..Controlled by Setpoint
76877  *  0b11..Reserved
76878  */
76879 #define PGMC_BPC_BPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK)
76880 
76881 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
76882 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
76883 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
76884  *  0b00..Domain 0
76885  *  0b01..Domain 1
76886  *  0b10..Domain 2
76887  *  0b11..Domain 3
76888  */
76889 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK)
76890 /*! @} */
76891 
76892 /*! @name BPC_POWER_CTRL - BPC power control */
76893 /*! @{ */
76894 
76895 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
76896 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
76897 /*! PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode
76898  */
76899 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
76900 
76901 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
76902 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
76903 /*! PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode
76904  */
76905 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
76906 
76907 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
76908 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
76909 /*! PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode
76910  */
76911 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
76912 
76913 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
76914 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
76915 /*! ISO_ON_SOFT - Software isolation on trigger
76916  */
76917 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK)
76918 
76919 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
76920 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
76921 /*! PSW_OFF_SOFT - Software power off trigger
76922  */
76923 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK)
76924 
76925 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
76926 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
76927 /*! PSW_ON_SOFT - Software power on trigger
76928  */
76929 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK)
76930 
76931 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
76932 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
76933 /*! ISO_OFF_SOFT - Software isolation off trigger
76934  */
76935 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK)
76936 
76937 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U)
76938 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U)
76939 /*! PWR_OFF_AT_SP - Power off when system enters Setpoint number
76940  */
76941 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK)
76942 /*! @} */
76943 
76944 /*! @name BPC_FLAG - BPC flag */
76945 /*! @{ */
76946 
76947 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK          (0x1U)
76948 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT         (0U)
76949 /*! PDN_FLAG - set to 1 after power switch off, cleared by writing 1
76950  */
76951 #define PGMC_BPC_BPC_FLAG_PDN_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK)
76952 /*! @} */
76953 
76954 /*! @name BPC_SSAR_SAVE_CTRL - BPC SSAR save control */
76955 /*! @{ */
76956 
76957 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U)
76958 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U)
76959 /*! SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process
76960  */
76961 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK)
76962 
76963 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U)
76964 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U)
76965 /*! SAVE_AT_WAIT - Save data when domain enters WAIT mode
76966  */
76967 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK)
76968 
76969 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U)
76970 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U)
76971 /*! SAVE_AT_STOP - Save data when domain enters STOP mode
76972  */
76973 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK)
76974 
76975 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U)
76976 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U)
76977 /*! SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode
76978  */
76979 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK)
76980 
76981 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U)
76982 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U)
76983 /*! SAVE_AT_SP - Save data when system enters a Setpoint.
76984  */
76985 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK)
76986 /*! @} */
76987 
76988 /*! @name BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control */
76989 /*! @{ */
76990 
76991 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U)
76992 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U)
76993 /*! RESTORE_AT_RUN - Restore data at RUN mode
76994  */
76995 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK)
76996 
76997 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U)
76998 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U)
76999 /*! RESTORE_AT_SP - Restore data when system enters a Setpoint.
77000  */
77001 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK)
77002 /*! @} */
77003 
77004 
77005 /*!
77006  * @}
77007  */ /* end of group PGMC_BPC_Register_Masks */
77008 
77009 
77010 /* PGMC_BPC - Peripheral instance base addresses */
77011 /** Peripheral PGMC_BPC0 base address */
77012 #define PGMC_BPC0_BASE                           (0x40C88000u)
77013 /** Peripheral PGMC_BPC0 base pointer */
77014 #define PGMC_BPC0                                ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
77015 /** Peripheral PGMC_BPC1 base address */
77016 #define PGMC_BPC1_BASE                           (0x40C88200u)
77017 /** Peripheral PGMC_BPC1 base pointer */
77018 #define PGMC_BPC1                                ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
77019 /** Peripheral PGMC_BPC2 base address */
77020 #define PGMC_BPC2_BASE                           (0x40C88400u)
77021 /** Peripheral PGMC_BPC2 base pointer */
77022 #define PGMC_BPC2                                ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
77023 /** Peripheral PGMC_BPC3 base address */
77024 #define PGMC_BPC3_BASE                           (0x40C88600u)
77025 /** Peripheral PGMC_BPC3 base pointer */
77026 #define PGMC_BPC3                                ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
77027 /** Peripheral PGMC_BPC4 base address */
77028 #define PGMC_BPC4_BASE                           (0x40C88800u)
77029 /** Peripheral PGMC_BPC4 base pointer */
77030 #define PGMC_BPC4                                ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
77031 /** Peripheral PGMC_BPC5 base address */
77032 #define PGMC_BPC5_BASE                           (0x40C88A00u)
77033 /** Peripheral PGMC_BPC5 base pointer */
77034 #define PGMC_BPC5                                ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
77035 /** Peripheral PGMC_BPC6 base address */
77036 #define PGMC_BPC6_BASE                           (0x40C88C00u)
77037 /** Peripheral PGMC_BPC6 base pointer */
77038 #define PGMC_BPC6                                ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
77039 /** Peripheral PGMC_BPC7 base address */
77040 #define PGMC_BPC7_BASE                           (0x40C88E00u)
77041 /** Peripheral PGMC_BPC7 base pointer */
77042 #define PGMC_BPC7                                ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
77043 /** Array initializer of PGMC_BPC peripheral base addresses */
77044 #define PGMC_BPC_BASE_ADDRS                      { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
77045 /** Array initializer of PGMC_BPC peripheral base pointers */
77046 #define PGMC_BPC_BASE_PTRS                       { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
77047 
77048 /*!
77049  * @}
77050  */ /* end of group PGMC_BPC_Peripheral_Access_Layer */
77051 
77052 
77053 /* ----------------------------------------------------------------------------
77054    -- PGMC_CPC Peripheral Access Layer
77055    ---------------------------------------------------------------------------- */
77056 
77057 /*!
77058  * @addtogroup PGMC_CPC_Peripheral_Access_Layer PGMC_CPC Peripheral Access Layer
77059  * @{
77060  */
77061 
77062 /** PGMC_CPC - Register Layout Typedef */
77063 typedef struct {
77064        uint8_t RESERVED_0[4];
77065   __IO uint32_t CPC_AUTHEN_CTRL;                   /**< CPC Authentication Control, offset: 0x4 */
77066        uint8_t RESERVED_1[8];
77067   __IO uint32_t CPC_CORE_MODE;                     /**< CPC Core Mode, offset: 0x10 */
77068   __IO uint32_t CPC_CORE_POWER_CTRL;               /**< CPC core power control, offset: 0x14 */
77069        uint8_t RESERVED_2[20];
77070   __IO uint32_t CPC_FLAG;                          /**< CPC flag, offset: 0x2C */
77071        uint8_t RESERVED_3[16];
77072   __IO uint32_t CPC_CACHE_MODE;                    /**< CPC Cache Mode, offset: 0x40 */
77073   __IO uint32_t CPC_CACHE_CM_CTRL;                 /**< CPC cache CPU mode control, offset: 0x44 */
77074   __IO uint32_t CPC_CACHE_SP_CTRL_0;               /**< CPC cache Setpoint control 0, offset: 0x48 */
77075   __IO uint32_t CPC_CACHE_SP_CTRL_1;               /**< CPC cache Setpoint control 1, offset: 0x4C */
77076        uint8_t RESERVED_4[112];
77077   __IO uint32_t CPC_LMEM_MODE;                     /**< CPC local memory Mode, offset: 0xC0 */
77078   __IO uint32_t CPC_LMEM_CM_CTRL;                  /**< CPC local memory CPU mode control, offset: 0xC4 */
77079   __IO uint32_t CPC_LMEM_SP_CTRL_0;                /**< CPC local memory Setpoint control 0, offset: 0xC8 */
77080   __IO uint32_t CPC_LMEM_SP_CTRL_1;                /**< CPC local memory Setpoint control 1, offset: 0xCC */
77081 } PGMC_CPC_Type;
77082 
77083 /* ----------------------------------------------------------------------------
77084    -- PGMC_CPC Register Masks
77085    ---------------------------------------------------------------------------- */
77086 
77087 /*!
77088  * @addtogroup PGMC_CPC_Register_Masks PGMC_CPC Register Masks
77089  * @{
77090  */
77091 
77092 /*! @name CPC_AUTHEN_CTRL - CPC Authentication Control */
77093 /*! @{ */
77094 
77095 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK       (0x1U)
77096 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT      (0U)
77097 /*! USER - Allow user mode access
77098  */
77099 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)
77100 
77101 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
77102 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
77103 /*! NONSECURE - Allow non-secure mode access
77104  */
77105 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)
77106 
77107 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
77108 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
77109 /*! LOCK_SETTING - Lock NONSECURE and USER
77110  */
77111 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
77112 
77113 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
77114 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
77115 /*! WHITE_LIST - Domain ID white list
77116  */
77117 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)
77118 
77119 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
77120 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
77121 /*! LOCK_LIST - White list lock
77122  */
77123 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)
77124 
77125 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77126 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77127 /*! LOCK_CFG - Configuration lock
77128  */
77129 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)
77130 /*! @} */
77131 
77132 /*! @name CPC_CORE_MODE - CPC Core Mode */
77133 /*! @{ */
77134 
77135 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK    (0x3U)
77136 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT   (0U)
77137 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77138  *  0b00..Not affected by any low power mode
77139  *  0b01..Controlled by CPU power mode of the domain
77140  *  0b10..Reserved
77141  *  0b11..Reserved
77142  */
77143 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)
77144 /*! @} */
77145 
77146 /*! @name CPC_CORE_POWER_CTRL - CPC core power control */
77147 /*! @{ */
77148 
77149 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
77150 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
77151 /*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode
77152  */
77153 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
77154 
77155 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
77156 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
77157 /*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode
77158  */
77159 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
77160 
77161 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
77162 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
77163 /*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode
77164  */
77165 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
77166 
77167 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
77168 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
77169 /*! ISO_ON_SOFT - Software isolation on trigger
77170  */
77171 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)
77172 
77173 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
77174 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
77175 /*! PSW_OFF_SOFT - Software power off trigger
77176  */
77177 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)
77178 
77179 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
77180 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
77181 /*! PSW_ON_SOFT - Software power on trigger
77182  */
77183 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)
77184 
77185 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
77186 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
77187 /*! ISO_OFF_SOFT - Software isolation off trigger
77188  */
77189 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)
77190 /*! @} */
77191 
77192 /*! @name CPC_FLAG - CPC flag */
77193 /*! @{ */
77194 
77195 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK     (0x1U)
77196 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT    (0U)
77197 /*! CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1
77198  */
77199 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)
77200 /*! @} */
77201 
77202 /*! @name CPC_CACHE_MODE - CPC Cache Mode */
77203 /*! @{ */
77204 
77205 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK   (0x3U)
77206 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT  (0U)
77207 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77208  *  0b00..Not affected by any low power mode
77209  *  0b01..Controlled by CPU power mode of the domain
77210  *  0b10..Controlled by Setpoint
77211  *  0b11..Reserved
77212  */
77213 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)
77214 /*! @} */
77215 
77216 /*! @name CPC_CACHE_CM_CTRL - CPC cache CPU mode control */
77217 /*! @{ */
77218 
77219 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
77220 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
77221 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
77222  */
77223 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)
77224 
77225 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
77226 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
77227 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77228  */
77229 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)
77230 
77231 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
77232 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
77233 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77234  */
77235 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)
77236 
77237 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
77238 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
77239 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77240  */
77241 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)
77242 
77243 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
77244 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)
77245 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
77246  */
77247 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)
77248 /*! @} */
77249 
77250 /*! @name CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 */
77251 /*! @{ */
77252 
77253 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
77254 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
77255 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77256  */
77257 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)
77258 
77259 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
77260 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
77261 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77262  */
77263 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)
77264 
77265 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
77266 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
77267 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77268  */
77269 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)
77270 
77271 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
77272 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
77273 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77274  */
77275 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)
77276 
77277 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
77278 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
77279 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77280  */
77281 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)
77282 
77283 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
77284 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
77285 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77286  */
77287 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)
77288 
77289 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
77290 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
77291 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77292  */
77293 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)
77294 
77295 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
77296 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
77297 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77298  */
77299 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)
77300 /*! @} */
77301 
77302 /*! @name CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 */
77303 /*! @{ */
77304 
77305 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
77306 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
77307 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77308  */
77309 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)
77310 
77311 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
77312 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
77313 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77314  */
77315 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)
77316 
77317 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
77318 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
77319 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77320  */
77321 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)
77322 
77323 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
77324 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
77325 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77326  */
77327 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)
77328 
77329 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
77330 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
77331 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77332  */
77333 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)
77334 
77335 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
77336 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
77337 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77338  */
77339 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)
77340 
77341 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
77342 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
77343 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77344  */
77345 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)
77346 
77347 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
77348 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
77349 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77350  */
77351 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)
77352 /*! @} */
77353 
77354 /*! @name CPC_LMEM_MODE - CPC local memory Mode */
77355 /*! @{ */
77356 
77357 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK    (0x3U)
77358 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT   (0U)
77359 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77360  *  0b00..Not affected by any low power mode
77361  *  0b01..Controlled by CPU power mode of the domain
77362  *  0b10..Controlled by Setpoint
77363  *  0b11..Reserved
77364  */
77365 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)
77366 /*! @} */
77367 
77368 /*! @name CPC_LMEM_CM_CTRL - CPC local memory CPU mode control */
77369 /*! @{ */
77370 
77371 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
77372 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
77373 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
77374  */
77375 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)
77376 
77377 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
77378 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
77379 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77380  */
77381 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)
77382 
77383 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
77384 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
77385 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77386  */
77387 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)
77388 
77389 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
77390 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
77391 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77392  */
77393 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)
77394 
77395 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
77396 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)
77397 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
77398  */
77399 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)
77400 /*! @} */
77401 
77402 /*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 */
77403 /*! @{ */
77404 
77405 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
77406 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
77407 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77408  */
77409 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)
77410 
77411 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
77412 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
77413 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77414  */
77415 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)
77416 
77417 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
77418 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
77419 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77420  */
77421 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)
77422 
77423 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
77424 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
77425 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77426  */
77427 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)
77428 
77429 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
77430 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
77431 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77432  */
77433 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)
77434 
77435 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
77436 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
77437 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77438  */
77439 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)
77440 
77441 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
77442 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
77443 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77444  */
77445 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)
77446 
77447 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
77448 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
77449 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77450  */
77451 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)
77452 /*! @} */
77453 
77454 /*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 */
77455 /*! @{ */
77456 
77457 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
77458 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
77459 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77460  */
77461 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)
77462 
77463 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
77464 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
77465 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77466  */
77467 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)
77468 
77469 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
77470 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
77471 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77472  */
77473 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)
77474 
77475 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
77476 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
77477 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77478  */
77479 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)
77480 
77481 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
77482 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
77483 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77484  */
77485 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)
77486 
77487 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
77488 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
77489 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77490  */
77491 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)
77492 
77493 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
77494 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
77495 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77496  */
77497 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)
77498 
77499 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
77500 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
77501 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77502  */
77503 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)
77504 /*! @} */
77505 
77506 
77507 /*!
77508  * @}
77509  */ /* end of group PGMC_CPC_Register_Masks */
77510 
77511 
77512 /* PGMC_CPC - Peripheral instance base addresses */
77513 /** Peripheral PGMC_CPC0 base address */
77514 #define PGMC_CPC0_BASE                           (0x40C89000u)
77515 /** Peripheral PGMC_CPC0 base pointer */
77516 #define PGMC_CPC0                                ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
77517 /** Peripheral PGMC_CPC1 base address */
77518 #define PGMC_CPC1_BASE                           (0x40C89400u)
77519 /** Peripheral PGMC_CPC1 base pointer */
77520 #define PGMC_CPC1                                ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
77521 /** Array initializer of PGMC_CPC peripheral base addresses */
77522 #define PGMC_CPC_BASE_ADDRS                      { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
77523 /** Array initializer of PGMC_CPC peripheral base pointers */
77524 #define PGMC_CPC_BASE_PTRS                       { PGMC_CPC0, PGMC_CPC1 }
77525 
77526 /*!
77527  * @}
77528  */ /* end of group PGMC_CPC_Peripheral_Access_Layer */
77529 
77530 
77531 /* ----------------------------------------------------------------------------
77532    -- PGMC_MIF Peripheral Access Layer
77533    ---------------------------------------------------------------------------- */
77534 
77535 /*!
77536  * @addtogroup PGMC_MIF_Peripheral_Access_Layer PGMC_MIF Peripheral Access Layer
77537  * @{
77538  */
77539 
77540 /** PGMC_MIF - Register Layout Typedef */
77541 typedef struct {
77542        uint8_t RESERVED_0[4];
77543   __IO uint32_t MIF_AUTHEN_CTRL;                   /**< MIF Authentication Control, offset: 0x4 */
77544        uint8_t RESERVED_1[8];
77545   __IO uint32_t MIF_MLPL_SLEEP;                    /**< MIF MLPL control of SLEEP, offset: 0x10 */
77546        uint8_t RESERVED_2[12];
77547   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of IG, offset: 0x20 */
77548        uint8_t RESERVED_3[12];
77549   __IO uint32_t MIF_MLPL_LS;                       /**< MIF MLPL control of LS, offset: 0x30 */
77550        uint8_t RESERVED_4[12];
77551   __IO uint32_t MIF_MLPL_HS;                       /**< MIF MLPL control of HS, offset: 0x40 */
77552        uint8_t RESERVED_5[12];
77553   __IO uint32_t MIF_MLPL_STDBY;                    /**< MIF MLPL control of STDBY, offset: 0x50 */
77554        uint8_t RESERVED_6[12];
77555   __IO uint32_t MIF_MLPL_ARR_PDN;                  /**< MIF MLPL control of array power down, offset: 0x60 */
77556        uint8_t RESERVED_7[12];
77557   __IO uint32_t MIF_MLPL_PER_PDN;                  /**< MIF MLPL control of peripheral power down, offset: 0x70 */
77558        uint8_t RESERVED_8[12];
77559   __IO uint32_t MIF_MLPL_INITN;                    /**< MIF MLPL control of INITN, offset: 0x80 */
77560        uint8_t RESERVED_9[44];
77561   __IO uint32_t MIF_MLPL_ISO;                      /**< MIF MLPL control of isolation enable, offset: 0xB0 */
77562 } PGMC_MIF_Type;
77563 
77564 /* ----------------------------------------------------------------------------
77565    -- PGMC_MIF Register Masks
77566    ---------------------------------------------------------------------------- */
77567 
77568 /*!
77569  * @addtogroup PGMC_MIF_Register_Masks PGMC_MIF Register Masks
77570  * @{
77571  */
77572 
77573 /*! @name MIF_AUTHEN_CTRL - MIF Authentication Control */
77574 /*! @{ */
77575 
77576 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77577 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77578 /*! LOCK_CFG - Configuration lock
77579  */
77580 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK)
77581 /*! @} */
77582 
77583 /*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */
77584 /*! @{ */
77585 
77586 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK   (0xFFFFU)
77587 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT  (0U)
77588 /*! MLPL_CTRL - Signal behavior at each MLPL
77589  */
77590 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
77591 /*! @} */
77592 
77593 /*! @name MIF_MLPL_IG - MIF MLPL control of IG */
77594 /*! @{ */
77595 
77596 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK      (0xFFFFU)
77597 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT     (0U)
77598 /*! MLPL_CTRL - Signal behavior at each MLPL
77599  */
77600 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK)
77601 /*! @} */
77602 
77603 /*! @name MIF_MLPL_LS - MIF MLPL control of LS */
77604 /*! @{ */
77605 
77606 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK      (0xFFFFU)
77607 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT     (0U)
77608 /*! MLPL_CTRL - Signal behavior at each MLPL
77609  */
77610 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK)
77611 /*! @} */
77612 
77613 /*! @name MIF_MLPL_HS - MIF MLPL control of HS */
77614 /*! @{ */
77615 
77616 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK      (0xFFFFU)
77617 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT     (0U)
77618 /*! MLPL_CTRL - Signal behavior at each MLPL
77619  */
77620 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK)
77621 /*! @} */
77622 
77623 /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
77624 /*! @{ */
77625 
77626 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK   (0xFFFFU)
77627 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT  (0U)
77628 /*! MLPL_CTRL - Signal behavior at each MLPL
77629  */
77630 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
77631 /*! @} */
77632 
77633 /*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */
77634 /*! @{ */
77635 
77636 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU)
77637 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
77638 /*! MLPL_CTRL - Signal behavior at each MLPL
77639  */
77640 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
77641 /*! @} */
77642 
77643 /*! @name MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down */
77644 /*! @{ */
77645 
77646 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU)
77647 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U)
77648 /*! MLPL_CTRL - Signal behavior at each MLPL
77649  */
77650 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK)
77651 /*! @} */
77652 
77653 /*! @name MIF_MLPL_INITN - MIF MLPL control of INITN */
77654 /*! @{ */
77655 
77656 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK   (0xFFFFU)
77657 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT  (0U)
77658 /*! MLPL_CTRL - Signal behavior at each MLPL
77659  */
77660 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK)
77661 
77662 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U)
77663 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U)
77664 /*! BYPASS_VDD_OK - Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77665  */
77666 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK)
77667 /*! @} */
77668 
77669 /*! @name MIF_MLPL_ISO - MIF MLPL control of isolation enable */
77670 /*! @{ */
77671 
77672 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK     (0xFFFFU)
77673 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT    (0U)
77674 /*! MLPL_CTRL - Signal behavior at each MLPL
77675  */
77676 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK)
77677 /*! @} */
77678 
77679 
77680 /*!
77681  * @}
77682  */ /* end of group PGMC_MIF_Register_Masks */
77683 
77684 
77685 /* PGMC_MIF - Peripheral instance base addresses */
77686 /** Peripheral PGMC_CPC0_MIF0 base address */
77687 #define PGMC_CPC0_MIF0_BASE                      (0x40C89100u)
77688 /** Peripheral PGMC_CPC0_MIF0 base pointer */
77689 #define PGMC_CPC0_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
77690 /** Peripheral PGMC_CPC0_MIF1 base address */
77691 #define PGMC_CPC0_MIF1_BASE                      (0x40C89200u)
77692 /** Peripheral PGMC_CPC0_MIF1 base pointer */
77693 #define PGMC_CPC0_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
77694 /** Peripheral PGMC_CPC1_MIF0 base address */
77695 #define PGMC_CPC1_MIF0_BASE                      (0x40C89500u)
77696 /** Peripheral PGMC_CPC1_MIF0 base pointer */
77697 #define PGMC_CPC1_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
77698 /** Peripheral PGMC_CPC1_MIF1 base address */
77699 #define PGMC_CPC1_MIF1_BASE                      (0x40C89600u)
77700 /** Peripheral PGMC_CPC1_MIF1 base pointer */
77701 #define PGMC_CPC1_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
77702 /** Array initializer of PGMC_MIF peripheral base addresses */
77703 #define PGMC_MIF_BASE_ADDRS                      { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
77704 /** Array initializer of PGMC_MIF peripheral base pointers */
77705 #define PGMC_MIF_BASE_PTRS                       { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
77706 
77707 /*!
77708  * @}
77709  */ /* end of group PGMC_MIF_Peripheral_Access_Layer */
77710 
77711 
77712 /* ----------------------------------------------------------------------------
77713    -- PGMC_PPC Peripheral Access Layer
77714    ---------------------------------------------------------------------------- */
77715 
77716 /*!
77717  * @addtogroup PGMC_PPC_Peripheral_Access_Layer PGMC_PPC Peripheral Access Layer
77718  * @{
77719  */
77720 
77721 /** PGMC_PPC - Register Layout Typedef */
77722 typedef struct {
77723        uint8_t RESERVED_0[4];
77724   __IO uint32_t PPC_AUTHEN_CTRL;                   /**< PPC Authentication Control, offset: 0x4 */
77725        uint8_t RESERVED_1[8];
77726   __IO uint32_t PPC_MODE;                          /**< PPC Mode, offset: 0x10 */
77727   __IO uint32_t PPC_STBY_CM_CTRL;                  /**< PPC standby CPU mode control, offset: 0x14 */
77728   __IO uint32_t PPC_STBY_SP_CTRL;                  /**< PPC standby Setpoint control, offset: 0x18 */
77729 } PGMC_PPC_Type;
77730 
77731 /* ----------------------------------------------------------------------------
77732    -- PGMC_PPC Register Masks
77733    ---------------------------------------------------------------------------- */
77734 
77735 /*!
77736  * @addtogroup PGMC_PPC_Register_Masks PGMC_PPC Register Masks
77737  * @{
77738  */
77739 
77740 /*! @name PPC_AUTHEN_CTRL - PPC Authentication Control */
77741 /*! @{ */
77742 
77743 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK       (0x1U)
77744 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT      (0U)
77745 /*! USER - Allow user mode access
77746  */
77747 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK)
77748 
77749 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
77750 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
77751 /*! NONSECURE - Allow non-secure mode access
77752  */
77753 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK)
77754 
77755 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
77756 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
77757 /*! LOCK_SETTING - Lock NONSECURE and USER
77758  */
77759 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
77760 
77761 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
77762 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
77763 /*! WHITE_LIST - Domain ID white list
77764  */
77765 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)
77766 
77767 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
77768 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
77769 /*! LOCK_LIST - White list lock
77770  */
77771 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK)
77772 
77773 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
77774 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
77775 /*! LOCK_CFG - Configuration lock
77776  */
77777 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK)
77778 /*! @} */
77779 
77780 /*! @name PPC_MODE - PPC Mode */
77781 /*! @{ */
77782 
77783 #define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK         (0x3U)
77784 #define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT        (0U)
77785 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77786  *  0b00..Not affected by any low power mode
77787  *  0b01..Controlled by CPU power mode of the domain
77788  *  0b10..Controlled by Setpoint and system standby
77789  *  0b11..Reserved
77790  */
77791 #define PGMC_PPC_PPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK)
77792 
77793 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
77794 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
77795 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
77796  *  0b00..Domain 0
77797  *  0b01..Domain 1
77798  *  0b10..Domain 2
77799  *  0b11..Domain 3
77800  */
77801 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK)
77802 /*! @} */
77803 
77804 /*! @name PPC_STBY_CM_CTRL - PPC standby CPU mode control */
77805 /*! @{ */
77806 
77807 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U)
77808 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U)
77809 /*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77810  */
77811 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK)
77812 
77813 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U)
77814 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U)
77815 /*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77816  */
77817 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK)
77818 
77819 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U)
77820 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U)
77821 /*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77822  */
77823 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK)
77824 
77825 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U)
77826 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U)
77827 /*! STBY_ON_SOFT - Software PMIC standby on trigger
77828  */
77829 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK)
77830 
77831 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U)
77832 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U)
77833 /*! STBY_OFF_SOFT - Software PMIC standby off trigger
77834  */
77835 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK)
77836 /*! @} */
77837 
77838 /*! @name PPC_STBY_SP_CTRL - PPC standby Setpoint control */
77839 /*! @{ */
77840 
77841 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU)
77842 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U)
77843 /*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77844  */
77845 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK)
77846 
77847 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U)
77848 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U)
77849 /*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters Setpoint number and system is in
77850  *    standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
77851  */
77852 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK)
77853 /*! @} */
77854 
77855 
77856 /*!
77857  * @}
77858  */ /* end of group PGMC_PPC_Register_Masks */
77859 
77860 
77861 /* PGMC_PPC - Peripheral instance base addresses */
77862 /** Peripheral PGMC_PPC0 base address */
77863 #define PGMC_PPC0_BASE                           (0x40C8B000u)
77864 /** Peripheral PGMC_PPC0 base pointer */
77865 #define PGMC_PPC0                                ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
77866 /** Array initializer of PGMC_PPC peripheral base addresses */
77867 #define PGMC_PPC_BASE_ADDRS                      { PGMC_PPC0_BASE }
77868 /** Array initializer of PGMC_PPC peripheral base pointers */
77869 #define PGMC_PPC_BASE_PTRS                       { PGMC_PPC0 }
77870 
77871 /*!
77872  * @}
77873  */ /* end of group PGMC_PPC_Peripheral_Access_Layer */
77874 
77875 
77876 /* ----------------------------------------------------------------------------
77877    -- PHY_LDO Peripheral Access Layer
77878    ---------------------------------------------------------------------------- */
77879 
77880 /*!
77881  * @addtogroup PHY_LDO_Peripheral_Access_Layer PHY_LDO Peripheral Access Layer
77882  * @{
77883  */
77884 
77885 /** PHY_LDO - Register Layout Typedef */
77886 typedef struct {
77887   struct {                                         /* offset: 0x0 */
77888     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
77889     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
77890     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
77891     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
77892   } CTRL0;
77893        uint8_t RESERVED_0[64];
77894   struct {                                         /* offset: 0x50 */
77895     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
77896     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
77897     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
77898     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
77899   } STAT0;
77900 } PHY_LDO_Type;
77901 
77902 /* ----------------------------------------------------------------------------
77903    -- PHY_LDO Register Masks
77904    ---------------------------------------------------------------------------- */
77905 
77906 /*!
77907  * @addtogroup PHY_LDO_Register_Masks PHY_LDO Register Masks
77908  * @{
77909  */
77910 
77911 /*! @name CTRL0 - Analog Control Register CTRL0 */
77912 /*! @{ */
77913 
77914 #define PHY_LDO_CTRL0_LINREG_EN_MASK             (0x1U)
77915 #define PHY_LDO_CTRL0_LINREG_EN_SHIFT            (0U)
77916 /*! LINREG_EN - LinrReg master enable
77917  */
77918 #define PHY_LDO_CTRL0_LINREG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
77919 
77920 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK  (0x2U)
77921 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
77922 /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
77923  *  0b0..Internal pull-down enabled
77924  *  0b1..Internal pull-down disabled
77925  */
77926 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x)    (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
77927 
77928 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK      (0x4U)
77929 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT     (2U)
77930 /*! LINREG_ILIMIT_EN - LinReg current-limit enable
77931  */
77932 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
77933 
77934 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK     (0x1F0U)
77935 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT    (4U)
77936 /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
77937  *  0b00000..Set output voltage to x.xV
77938  *  0b10000..Sets output voltage to 1.0V
77939  *  0b11111..Set output voltage to x.xV
77940  */
77941 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
77942 
77943 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK      (0x8000U)
77944 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT     (15U)
77945 /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load
77946  */
77947 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
77948 /*! @} */
77949 
77950 /*! @name STAT0 - Analog Status Register STAT0 */
77951 /*! @{ */
77952 
77953 #define PHY_LDO_STAT0_LINREG_STAT_MASK           (0xFU)
77954 #define PHY_LDO_STAT0_LINREG_STAT_SHIFT          (0U)
77955 /*! LINREG_STAT - LinReg Status Bits
77956  */
77957 #define PHY_LDO_STAT0_LINREG_STAT(x)             (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK)
77958 /*! @} */
77959 
77960 
77961 /*!
77962  * @}
77963  */ /* end of group PHY_LDO_Register_Masks */
77964 
77965 
77966 /* PHY_LDO - Peripheral instance base addresses */
77967 /** Peripheral PHY_LDO base address */
77968 #define PHY_LDO_BASE                             (0u)
77969 /** Peripheral PHY_LDO base pointer */
77970 #define PHY_LDO                                  ((PHY_LDO_Type *)PHY_LDO_BASE)
77971 /** Array initializer of PHY_LDO peripheral base addresses */
77972 #define PHY_LDO_BASE_ADDRS                       { PHY_LDO_BASE }
77973 /** Array initializer of PHY_LDO peripheral base pointers */
77974 #define PHY_LDO_BASE_PTRS                        { PHY_LDO }
77975 
77976 /*!
77977  * @}
77978  */ /* end of group PHY_LDO_Peripheral_Access_Layer */
77979 
77980 
77981 /* ----------------------------------------------------------------------------
77982    -- PIT Peripheral Access Layer
77983    ---------------------------------------------------------------------------- */
77984 
77985 /*!
77986  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
77987  * @{
77988  */
77989 
77990 /** PIT - Register Layout Typedef */
77991 typedef struct {
77992   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
77993        uint8_t RESERVED_0[220];
77994   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
77995   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
77996        uint8_t RESERVED_1[24];
77997   struct {                                         /* offset: 0x100, array step: 0x10 */
77998     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
77999     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
78000     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
78001     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
78002   } CHANNEL[4];
78003 } PIT_Type;
78004 
78005 /* ----------------------------------------------------------------------------
78006    -- PIT Register Masks
78007    ---------------------------------------------------------------------------- */
78008 
78009 /*!
78010  * @addtogroup PIT_Register_Masks PIT Register Masks
78011  * @{
78012  */
78013 
78014 /*! @name MCR - PIT Module Control Register */
78015 /*! @{ */
78016 
78017 #define PIT_MCR_FRZ_MASK                         (0x1U)
78018 #define PIT_MCR_FRZ_SHIFT                        (0U)
78019 /*! FRZ - Freeze
78020  *  0b0..Timers continue to run in Debug mode.
78021  *  0b1..Timers are stopped in Debug mode.
78022  */
78023 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
78024 
78025 #define PIT_MCR_MDIS_MASK                        (0x2U)
78026 #define PIT_MCR_MDIS_SHIFT                       (1U)
78027 /*! MDIS - Module Disable for PIT
78028  *  0b0..Clock for standard PIT timers is enabled.
78029  *  0b1..Clock for standard PIT timers is disabled.
78030  */
78031 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
78032 /*! @} */
78033 
78034 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
78035 /*! @{ */
78036 
78037 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
78038 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
78039 /*! LTH - Life Timer value
78040  */
78041 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
78042 /*! @} */
78043 
78044 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
78045 /*! @{ */
78046 
78047 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
78048 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
78049 /*! LTL - Life Timer value
78050  */
78051 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
78052 /*! @} */
78053 
78054 /*! @name LDVAL - Timer Load Value Register */
78055 /*! @{ */
78056 
78057 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
78058 #define PIT_LDVAL_TSV_SHIFT                      (0U)
78059 /*! TSV - Timer Start Value
78060  */
78061 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
78062 /*! @} */
78063 
78064 /* The count of PIT_LDVAL */
78065 #define PIT_LDVAL_COUNT                          (4U)
78066 
78067 /*! @name CVAL - Current Timer Value Register */
78068 /*! @{ */
78069 
78070 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
78071 #define PIT_CVAL_TVL_SHIFT                       (0U)
78072 /*! TVL - Current Timer Value
78073  */
78074 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
78075 /*! @} */
78076 
78077 /* The count of PIT_CVAL */
78078 #define PIT_CVAL_COUNT                           (4U)
78079 
78080 /*! @name TCTRL - Timer Control Register */
78081 /*! @{ */
78082 
78083 #define PIT_TCTRL_TEN_MASK                       (0x1U)
78084 #define PIT_TCTRL_TEN_SHIFT                      (0U)
78085 /*! TEN - Timer Enable
78086  *  0b0..Timer n is disabled.
78087  *  0b1..Timer n is enabled.
78088  */
78089 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
78090 
78091 #define PIT_TCTRL_TIE_MASK                       (0x2U)
78092 #define PIT_TCTRL_TIE_SHIFT                      (1U)
78093 /*! TIE - Timer Interrupt Enable
78094  *  0b0..Interrupt requests from Timer n are disabled.
78095  *  0b1..Interrupt is requested whenever TIF is set.
78096  */
78097 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
78098 
78099 #define PIT_TCTRL_CHN_MASK                       (0x4U)
78100 #define PIT_TCTRL_CHN_SHIFT                      (2U)
78101 /*! CHN - Chain Mode
78102  *  0b0..Timer is not chained.
78103  *  0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.
78104  */
78105 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
78106 /*! @} */
78107 
78108 /* The count of PIT_TCTRL */
78109 #define PIT_TCTRL_COUNT                          (4U)
78110 
78111 /*! @name TFLG - Timer Flag Register */
78112 /*! @{ */
78113 
78114 #define PIT_TFLG_TIF_MASK                        (0x1U)
78115 #define PIT_TFLG_TIF_SHIFT                       (0U)
78116 /*! TIF - Timer Interrupt Flag
78117  *  0b0..Timeout has not yet occurred.
78118  *  0b1..Timeout has occurred.
78119  */
78120 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
78121 /*! @} */
78122 
78123 /* The count of PIT_TFLG */
78124 #define PIT_TFLG_COUNT                           (4U)
78125 
78126 
78127 /*!
78128  * @}
78129  */ /* end of group PIT_Register_Masks */
78130 
78131 
78132 /* PIT - Peripheral instance base addresses */
78133 /** Peripheral PIT1 base address */
78134 #define PIT1_BASE                                (0x400D8000u)
78135 /** Peripheral PIT1 base pointer */
78136 #define PIT1                                     ((PIT_Type *)PIT1_BASE)
78137 /** Peripheral PIT2 base address */
78138 #define PIT2_BASE                                (0x40CB0000u)
78139 /** Peripheral PIT2 base pointer */
78140 #define PIT2                                     ((PIT_Type *)PIT2_BASE)
78141 /** Array initializer of PIT peripheral base addresses */
78142 #define PIT_BASE_ADDRS                           { 0u, PIT1_BASE, PIT2_BASE }
78143 /** Array initializer of PIT peripheral base pointers */
78144 #define PIT_BASE_PTRS                            { (PIT_Type *)0u, PIT1, PIT2 }
78145 /** Interrupt vectors for the PIT peripheral type */
78146 #define PIT_IRQS                                 { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
78147 
78148 /*!
78149  * @}
78150  */ /* end of group PIT_Peripheral_Access_Layer */
78151 
78152 
78153 /* ----------------------------------------------------------------------------
78154    -- PUF Peripheral Access Layer
78155    ---------------------------------------------------------------------------- */
78156 
78157 /*!
78158  * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
78159  * @{
78160  */
78161 
78162 /** PUF - Register Layout Typedef */
78163 typedef struct {
78164   __IO uint32_t CTRL;                              /**< PUF Control Register, offset: 0x0 */
78165   __IO uint32_t KEYINDEX;                          /**< PUF Key Index Register, offset: 0x4 */
78166   __IO uint32_t KEYSIZE;                           /**< PUF Key Size Register, offset: 0x8 */
78167        uint8_t RESERVED_0[20];
78168   __I  uint32_t STAT;                              /**< PUF Status Register, offset: 0x20 */
78169        uint8_t RESERVED_1[4];
78170   __I  uint32_t ALLOW;                             /**< PUF Allow Register, offset: 0x28 */
78171        uint8_t RESERVED_2[20];
78172   __O  uint32_t KEYINPUT;                          /**< PUF Key Input Register, offset: 0x40 */
78173   __O  uint32_t CODEINPUT;                         /**< PUF Code Input Register, offset: 0x44 */
78174   __I  uint32_t CODEOUTPUT;                        /**< PUF Code Output Register, offset: 0x48 */
78175        uint8_t RESERVED_3[20];
78176   __I  uint32_t KEYOUTINDEX;                       /**< PUF Key Output Index Register, offset: 0x60 */
78177   __I  uint32_t KEYOUTPUT;                         /**< PUF Key Output Register, offset: 0x64 */
78178        uint8_t RESERVED_4[116];
78179   __IO uint32_t IFSTAT;                            /**< PUF Interface Status Register, offset: 0xDC */
78180        uint8_t RESERVED_5[28];
78181   __I  uint32_t VERSION;                           /**< PUF Version Register, offset: 0xFC */
78182   __IO uint32_t INTEN;                             /**< PUF Interrupt Enable, offset: 0x100 */
78183   __IO uint32_t INTSTAT;                           /**< PUF Interrupt Status, offset: 0x104 */
78184   __IO uint32_t PWRCTRL;                           /**< PUF Power Control Of RAM, offset: 0x108 */
78185   __IO uint32_t CFG;                               /**< PUF Configuration Register, offset: 0x10C */
78186        uint8_t RESERVED_6[240];
78187   __IO uint32_t KEYLOCK;                           /**< PUF Key Manager Lock, offset: 0x200 */
78188   __IO uint32_t KEYENABLE;                         /**< PUF Key Manager Enable, offset: 0x204 */
78189   __IO uint32_t KEYRESET;                          /**< PUF Key Manager Reset, offset: 0x208 */
78190   __IO uint32_t IDXBLK;                            /**< PUF Index Block Key Output, offset: 0x20C */
78191   __IO uint32_t IDXBLK_DP;                         /**< PUF Index Block Key Output, offset: 0x210 */
78192   __IO uint32_t KEYMASK[2];                        /**< PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */
78193        uint8_t RESERVED_7[56];
78194   __I  uint32_t IDXBLK_STATUS;                     /**< PUF Index Block Setting Status Register, offset: 0x254 */
78195   __I  uint32_t IDXBLK_SHIFT;                      /**< PUF Key Manager Shift Status, offset: 0x258 */
78196 } PUF_Type;
78197 
78198 /* ----------------------------------------------------------------------------
78199    -- PUF Register Masks
78200    ---------------------------------------------------------------------------- */
78201 
78202 /*!
78203  * @addtogroup PUF_Register_Masks PUF Register Masks
78204  * @{
78205  */
78206 
78207 /*! @name CTRL - PUF Control Register */
78208 /*! @{ */
78209 
78210 #define PUF_CTRL_ZEROIZE_MASK                    (0x1U)
78211 #define PUF_CTRL_ZEROIZE_SHIFT                   (0U)
78212 /*! ZEROIZE - Begin Zeroize operation for PUF and go to Error state
78213  *  0b0..No Zeroize operation in progress
78214  *  0b1..Zeroize operation in progress
78215  */
78216 #define PUF_CTRL_ZEROIZE(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
78217 
78218 #define PUF_CTRL_ENROLL_MASK                     (0x2U)
78219 #define PUF_CTRL_ENROLL_SHIFT                    (1U)
78220 /*! ENROLL - Begin Enroll operation
78221  *  0b0..No Enroll operation in progress
78222  *  0b1..Enroll operation in progress
78223  */
78224 #define PUF_CTRL_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
78225 
78226 #define PUF_CTRL_START_MASK                      (0x4U)
78227 #define PUF_CTRL_START_SHIFT                     (2U)
78228 /*! START - Begin Start operation
78229  *  0b0..No Start operation in progress
78230  *  0b1..Start operation in progress
78231  */
78232 #define PUF_CTRL_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
78233 
78234 #define PUF_CTRL_GENERATEKEY_MASK                (0x8U)
78235 #define PUF_CTRL_GENERATEKEY_SHIFT               (3U)
78236 /*! GENERATEKEY - Begin Set Intrinsic Key operation
78237  *  0b0..No Set Intrinsic Key operation in progress
78238  *  0b1..Set Intrinsic Key operation in progress
78239  */
78240 #define PUF_CTRL_GENERATEKEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
78241 
78242 #define PUF_CTRL_SETKEY_MASK                     (0x10U)
78243 #define PUF_CTRL_SETKEY_SHIFT                    (4U)
78244 /*! SETKEY - Begin Set User Key operation
78245  *  0b0..No Set Key operation in progress
78246  *  0b1..Set Key operation in progress
78247  */
78248 #define PUF_CTRL_SETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
78249 
78250 #define PUF_CTRL_GETKEY_MASK                     (0x40U)
78251 #define PUF_CTRL_GETKEY_SHIFT                    (6U)
78252 /*! GETKEY - Begin Get Key operation
78253  *  0b0..No Get Key operation in progress
78254  *  0b1..Get Key operation in progress
78255  */
78256 #define PUF_CTRL_GETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
78257 /*! @} */
78258 
78259 /*! @name KEYINDEX - PUF Key Index Register */
78260 /*! @{ */
78261 
78262 #define PUF_KEYINDEX_KEYIDX_MASK                 (0xFU)
78263 #define PUF_KEYINDEX_KEYIDX_SHIFT                (0U)
78264 /*! KEYIDX - PUF Key Index
78265  *  0b0000..USE INDEX0
78266  *  0b0001..USE INDEX1
78267  *  0b0010..USE INDEX2
78268  *  0b0011..USE INDEX3
78269  *  0b0100..USE INDEX4
78270  *  0b0101..USE INDEX5
78271  *  0b0110..USE INDEX6
78272  *  0b0111..USE INDEX7
78273  *  0b1000..USE INDEX8
78274  *  0b1001..USE INDEX9
78275  *  0b1010..USE INDEX10
78276  *  0b1011..USE INDEX11
78277  *  0b1100..USE INDEX12
78278  *  0b1101..USE INDEX13
78279  *  0b1110..USE INDEX14
78280  *  0b1111..USE INDEX15
78281  */
78282 #define PUF_KEYINDEX_KEYIDX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
78283 /*! @} */
78284 
78285 /*! @name KEYSIZE - PUF Key Size Register */
78286 /*! @{ */
78287 
78288 #define PUF_KEYSIZE_KEYSIZE_MASK                 (0x3FU)
78289 #define PUF_KEYSIZE_KEYSIZE_SHIFT                (0U)
78290 /*! KEYSIZE - PUF Key Size
78291  *  0b000001..Key Size is 8 Bytes and KC Size is 52 Bytes
78292  *  0b000010..Key Size is 16 Bytes and KC Size is 52 Bytes
78293  *  0b000011..Key Size is 24 Bytes and KC Size is 52 Bytes
78294  *  0b000100..Key Size is 32 Bytes and KC Size is 52 Bytes
78295  *  0b000101..Key Size is 40 Bytes and KC Size is 84 Bytes
78296  *  0b000110..Key Size is 48 Bytes and KC Size is 84 Bytes
78297  *  0b000111..Key Size is 56 Bytes and KC Size is 84 Bytes
78298  *  0b001000..Key Size is 64 Bytes and KC Size is 84 Bytes
78299  *  0b001001..Key Size is 72 Bytes and KC Size is 116 Bytes
78300  *  0b001010..Key Size is 80 Bytes and KC Size is 116 Bytes
78301  *  0b001011..Key Size is 88 Bytes and KC Size is 116 Bytes
78302  *  0b001100..Key Size is 96 Bytes and KC Size is 116 Bytes
78303  *  0b001101..Key Size is 104 Bytes and KC Size is 148 Bytes
78304  *  0b001110..Key Size is 112 Bytes and KC Size is 148 Bytes
78305  *  0b001111..Key Size is 120 Bytes and KC Size is 148 Bytes
78306  *  0b010000..Key Size is 128 Bytes and KC Size is 148 Bytes
78307  *  0b010001..Key Size is 136 Bytes and KC Size is 180 Bytes
78308  *  0b010010..Key Size is 144 Bytes and KC Size is 180 Bytes
78309  *  0b010011..Key Size is 152 Bytes and KC Size is 180 Bytes
78310  *  0b010100..Key Size is 160 Bytes and KC Size is 180 Bytes
78311  *  0b010101..Key Size is 168 Bytes and KC Size is 212 Bytes
78312  *  0b010110..Key Size is 176 Bytes and KC Size is 212 Bytes
78313  *  0b010111..Key Size is 184 Bytes and KC Size is 212 Bytes
78314  *  0b011000..Key Size is 192 Bytes and KC Size is 212 Bytes
78315  *  0b011001..Key Size is 200 Bytes and KC Size is 244 Bytes
78316  *  0b011010..Key Size is 208 Bytes and KC Size is 244 Bytes
78317  *  0b011011..Key Size is 216 Bytes and KC Size is 244 Bytes
78318  *  0b011100..Key Size is 224 Bytes and KC Size is 244 Bytes
78319  *  0b011101..Key Size is 232 Bytes and KC Size is 276 Bytes
78320  *  0b011110..Key Size is 240 Bytes and KC Size is 276 Bytes
78321  *  0b011111..Key Size is 248 Bytes and KC Size is 276 Bytes
78322  *  0b100000..Key Size is 256 Bytes and KC Size is 276 Bytes
78323  *  0b100001..Key Size is 264 Bytes and KC Size is 308 Bytes
78324  *  0b100010..Key Size is 272 Bytes and KC Size is 308 Bytes
78325  *  0b100011..Key Size is 280 Bytes and KC Size is 308 Bytes
78326  *  0b100100..Key Size is 288 Bytes and KC Size is 308 Bytes
78327  *  0b100101..Key Size is 296 Bytes and KC Size is 340 Bytes
78328  *  0b100110..Key Size is 304 Bytes and KC Size is 340 Bytes
78329  *  0b100111..Key Size is 312 Bytes and KC Size is 340 Bytes
78330  *  0b101000..Key Size is 320 Bytes and KC Size is 340 Bytes
78331  *  0b101001..Key Size is 328 Bytes and KC Size is 372 Bytes
78332  *  0b101010..Key Size is 336 Bytes and KC Size is 372 Bytes
78333  *  0b101011..Key Size is 344 Bytes and KC Size is 372 Bytes
78334  *  0b101100..Key Size is 352 Bytes and KC Size is 372 Bytes
78335  *  0b101101..Key Size is 360 Bytes and KC Size is 404 Bytes
78336  *  0b101110..Key Size is 368 Bytes and KC Size is 404 Bytes
78337  *  0b101111..Key Size is 376 Bytes and KC Size is 404 Bytes
78338  *  0b110000..Key Size is 384 Bytes and KC Size is 404 Bytes
78339  *  0b110001..Key Size is 392 Bytes and KC Size is 436 Bytes
78340  *  0b110010..Key Size is 400 Bytes and KC Size is 436 Bytes
78341  *  0b110011..Key Size is 408 Bytes and KC Size is 436 Bytes
78342  *  0b110100..Key Size is 416 Bytes and KC Size is 436 Bytes
78343  *  0b110101..Key Size is 424 Bytes and KC Size is 468 Bytes
78344  *  0b110110..Key Size is 432 Bytes and KC Size is 468 Bytes
78345  *  0b110111..Key Size is 440 Bytes and KC Size is 468 Bytes
78346  *  0b111000..Key Size is 448 Bytes and KC Size is 468 Bytes
78347  *  0b111001..Key Size is 456 Bytes and KC Size is 500 Bytes
78348  *  0b111010..Key Size is 464 Bytes and KC Size is 500 Bytes
78349  *  0b111011..Key Size is 472 Bytes and KC Size is 500 Bytes
78350  *  0b111100..Key Size is 480 Bytes and KC Size is 500 Bytes
78351  *  0b111101..Key Size is 488 Bytes and KC Size is 532 Bytes
78352  *  0b111110..Key Size is 496 Bytes and KC Size is 532 Bytes
78353  *  0b111111..Key Size is 504 Bytes and KC Size is 532 Bytes
78354  *  0b000000..Key Size is 512 Bytes and KC Size is 532 Bytes
78355  */
78356 #define PUF_KEYSIZE_KEYSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
78357 /*! @} */
78358 
78359 /*! @name STAT - PUF Status Register */
78360 /*! @{ */
78361 
78362 #define PUF_STAT_BUSY_MASK                       (0x1U)
78363 #define PUF_STAT_BUSY_SHIFT                      (0U)
78364 /*! BUSY - puf_busy
78365  *  0b0..IDLE
78366  *  0b1..BUSY
78367  */
78368 #define PUF_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
78369 
78370 #define PUF_STAT_SUCCESS_MASK                    (0x2U)
78371 #define PUF_STAT_SUCCESS_SHIFT                   (1U)
78372 /*! SUCCESS - puf_ok
78373  *  0b0..Last operation was unsuccessful
78374  *  0b1..Last operation was successful
78375  */
78376 #define PUF_STAT_SUCCESS(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
78377 
78378 #define PUF_STAT_ERROR_MASK                      (0x4U)
78379 #define PUF_STAT_ERROR_SHIFT                     (2U)
78380 /*! ERROR - puf_error
78381  *  0b0..PUF is not in the Error state
78382  *  0b1..PUF is in the Error state
78383  */
78384 #define PUF_STAT_ERROR(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
78385 
78386 #define PUF_STAT_KEYINREQ_MASK                   (0x10U)
78387 #define PUF_STAT_KEYINREQ_SHIFT                  (4U)
78388 /*! KEYINREQ - KI_ir
78389  *  0b0..No request for next part of key
78390  *  0b1..Request for next part of key in KEYINPUT register
78391  */
78392 #define PUF_STAT_KEYINREQ(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
78393 
78394 #define PUF_STAT_KEYOUTAVAIL_MASK                (0x20U)
78395 #define PUF_STAT_KEYOUTAVAIL_SHIFT               (5U)
78396 /*! KEYOUTAVAIL - KO_or
78397  *  0b0..Next part of key is not available
78398  *  0b1..Next part of key is available in KEYOUTPUT register
78399  */
78400 #define PUF_STAT_KEYOUTAVAIL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
78401 
78402 #define PUF_STAT_CODEINREQ_MASK                  (0x40U)
78403 #define PUF_STAT_CODEINREQ_SHIFT                 (6U)
78404 /*! CODEINREQ - CI_ir
78405  *  0b0..No request for next part of Activation Code/Key Code
78406  *  0b1..request for next part of Activation Code/Key Code in CODEINPUT register
78407  */
78408 #define PUF_STAT_CODEINREQ(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
78409 
78410 #define PUF_STAT_CODEOUTAVAIL_MASK               (0x80U)
78411 #define PUF_STAT_CODEOUTAVAIL_SHIFT              (7U)
78412 /*! CODEOUTAVAIL - CO_or
78413  *  0b0..Next part of Activation Code/Key Code is not available
78414  *  0b1..Next part of Activation Code/Key Code is available in CODEOUTPUT register
78415  */
78416 #define PUF_STAT_CODEOUTAVAIL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
78417 /*! @} */
78418 
78419 /*! @name ALLOW - PUF Allow Register */
78420 /*! @{ */
78421 
78422 #define PUF_ALLOW_ALLOWENROLL_MASK               (0x1U)
78423 #define PUF_ALLOW_ALLOWENROLL_SHIFT              (0U)
78424 /*! ALLOWENROLL - Allow Enroll operation
78425  *  0b0..Specified operation is not currently allowed
78426  *  0b1..Specified operation is allowed
78427  */
78428 #define PUF_ALLOW_ALLOWENROLL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
78429 
78430 #define PUF_ALLOW_ALLOWSTART_MASK                (0x2U)
78431 #define PUF_ALLOW_ALLOWSTART_SHIFT               (1U)
78432 /*! ALLOWSTART - Allow Start operation
78433  *  0b0..Specified operation is not currently allowed
78434  *  0b1..Specified operation is allowed
78435  */
78436 #define PUF_ALLOW_ALLOWSTART(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
78437 
78438 #define PUF_ALLOW_ALLOWSETKEY_MASK               (0x4U)
78439 #define PUF_ALLOW_ALLOWSETKEY_SHIFT              (2U)
78440 /*! ALLOWSETKEY - Allow Set Key operations
78441  *  0b0..Specified operation is not currently allowed
78442  *  0b1..Specified operation is allowed
78443  */
78444 #define PUF_ALLOW_ALLOWSETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
78445 
78446 #define PUF_ALLOW_ALLOWGETKEY_MASK               (0x8U)
78447 #define PUF_ALLOW_ALLOWGETKEY_SHIFT              (3U)
78448 /*! ALLOWGETKEY - Allow Get Key operation
78449  *  0b0..Specified operation is not currently allowed
78450  *  0b1..Specified operation is allowed
78451  */
78452 #define PUF_ALLOW_ALLOWGETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
78453 /*! @} */
78454 
78455 /*! @name KEYINPUT - PUF Key Input Register */
78456 /*! @{ */
78457 
78458 #define PUF_KEYINPUT_KEYIN_MASK                  (0xFFFFFFFFU)
78459 #define PUF_KEYINPUT_KEYIN_SHIFT                 (0U)
78460 /*! KEYIN - Key input data
78461  */
78462 #define PUF_KEYINPUT_KEYIN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
78463 /*! @} */
78464 
78465 /*! @name CODEINPUT - PUF Code Input Register */
78466 /*! @{ */
78467 
78468 #define PUF_CODEINPUT_CODEIN_MASK                (0xFFFFFFFFU)
78469 #define PUF_CODEINPUT_CODEIN_SHIFT               (0U)
78470 /*! CODEIN - AC/KC input data
78471  */
78472 #define PUF_CODEINPUT_CODEIN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
78473 /*! @} */
78474 
78475 /*! @name CODEOUTPUT - PUF Code Output Register */
78476 /*! @{ */
78477 
78478 #define PUF_CODEOUTPUT_CODEOUT_MASK              (0xFFFFFFFFU)
78479 #define PUF_CODEOUTPUT_CODEOUT_SHIFT             (0U)
78480 /*! CODEOUT - AC/KC output data
78481  */
78482 #define PUF_CODEOUTPUT_CODEOUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
78483 /*! @} */
78484 
78485 /*! @name KEYOUTINDEX - PUF Key Output Index Register */
78486 /*! @{ */
78487 
78488 #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK           (0xFFFFFFFFU)
78489 #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT          (0U)
78490 /*! KEYOUTIDX - Output Key index
78491  */
78492 #define PUF_KEYOUTINDEX_KEYOUTIDX(x)             (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
78493 /*! @} */
78494 
78495 /*! @name KEYOUTPUT - PUF Key Output Register */
78496 /*! @{ */
78497 
78498 #define PUF_KEYOUTPUT_KEYOUT_MASK                (0xFFFFFFFFU)
78499 #define PUF_KEYOUTPUT_KEYOUT_SHIFT               (0U)
78500 /*! KEYOUT - Key output data from a Get Key operation
78501  */
78502 #define PUF_KEYOUTPUT_KEYOUT(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
78503 /*! @} */
78504 
78505 /*! @name IFSTAT - PUF Interface Status Register */
78506 /*! @{ */
78507 
78508 #define PUF_IFSTAT_ERROR_MASK                    (0x1U)
78509 #define PUF_IFSTAT_ERROR_SHIFT                   (0U)
78510 /*! ERROR - APB error has occurred
78511  *  0b0..NOERROR
78512  *  0b1..ERROR
78513  */
78514 #define PUF_IFSTAT_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
78515 /*! @} */
78516 
78517 /*! @name VERSION - PUF Version Register */
78518 /*! @{ */
78519 
78520 #define PUF_VERSION_VERSION_MASK                 (0xFFFFFFFFU)
78521 #define PUF_VERSION_VERSION_SHIFT                (0U)
78522 /*! VERSION - Version of PUF
78523  */
78524 #define PUF_VERSION_VERSION(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
78525 /*! @} */
78526 
78527 /*! @name INTEN - PUF Interrupt Enable */
78528 /*! @{ */
78529 
78530 #define PUF_INTEN_READYEN_MASK                   (0x1U)
78531 #define PUF_INTEN_READYEN_SHIFT                  (0U)
78532 /*! READYEN - PUF Ready Interrupt Enable
78533  *  0b0..PUF ready interrupt disabled
78534  *  0b1..PUF ready interrupt enabled
78535  */
78536 #define PUF_INTEN_READYEN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
78537 
78538 #define PUF_INTEN_SUCCESSEN_MASK                 (0x2U)
78539 #define PUF_INTEN_SUCCESSEN_SHIFT                (1U)
78540 /*! SUCCESSEN - PUF_OK Interrupt Enable
78541  *  0b0..PUF successful interrupt disabled
78542  *  0b1..PUF successful interrupt enabled
78543  */
78544 #define PUF_INTEN_SUCCESSEN(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK)
78545 
78546 #define PUF_INTEN_ERROREN_MASK                   (0x4U)
78547 #define PUF_INTEN_ERROREN_SHIFT                  (2U)
78548 /*! ERROREN - PUF Error Interrupt Enable
78549  *  0b0..PUF error interrupt disabled
78550  *  0b1..PUF error interrupt enabled
78551  */
78552 #define PUF_INTEN_ERROREN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
78553 
78554 #define PUF_INTEN_KEYINREQEN_MASK                (0x10U)
78555 #define PUF_INTEN_KEYINREQEN_SHIFT               (4U)
78556 /*! KEYINREQEN - PUF Key Input Register Interrupt Enable
78557  *  0b0..Key interrupt request disabled
78558  *  0b1..Key interrupt request enabled
78559  */
78560 #define PUF_INTEN_KEYINREQEN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
78561 
78562 #define PUF_INTEN_KEYOUTAVAILEN_MASK             (0x20U)
78563 #define PUF_INTEN_KEYOUTAVAILEN_SHIFT            (5U)
78564 /*! KEYOUTAVAILEN - PUF Key Output Register Interrupt Enable
78565  *  0b0..Key available interrupt disabled
78566  *  0b1..Key available interrupt enabled
78567  */
78568 #define PUF_INTEN_KEYOUTAVAILEN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
78569 
78570 #define PUF_INTEN_CODEINREQEN_MASK               (0x40U)
78571 #define PUF_INTEN_CODEINREQEN_SHIFT              (6U)
78572 /*! CODEINREQEN - PUF Code Input Register Interrupt Enable
78573  *  0b0..AC/KC interrupt request disabled
78574  *  0b1..AC/KC interrupt request enabled
78575  */
78576 #define PUF_INTEN_CODEINREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
78577 
78578 #define PUF_INTEN_CODEOUTAVAILEN_MASK            (0x80U)
78579 #define PUF_INTEN_CODEOUTAVAILEN_SHIFT           (7U)
78580 /*! CODEOUTAVAILEN - PUF Code Output Register Interrupt Enable
78581  *  0b0..AC/KC available interrupt disabled
78582  *  0b1..AC/KC available interrupt enabled
78583  */
78584 #define PUF_INTEN_CODEOUTAVAILEN(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
78585 /*! @} */
78586 
78587 /*! @name INTSTAT - PUF Interrupt Status */
78588 /*! @{ */
78589 
78590 #define PUF_INTSTAT_READY_MASK                   (0x1U)
78591 #define PUF_INTSTAT_READY_SHIFT                  (0U)
78592 /*! READY - PUF_FINISH Interrupt Status
78593  *  0b0..Indicates that last operation not finished
78594  *  0b1..Indicates that last operation is finished
78595  */
78596 #define PUF_INTSTAT_READY(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
78597 
78598 #define PUF_INTSTAT_SUCCESS_MASK                 (0x2U)
78599 #define PUF_INTSTAT_SUCCESS_SHIFT                (1U)
78600 /*! SUCCESS - PUF_OK Interrupt Status
78601  *  0b0..Indicates that last operation was not successful
78602  *  0b1..Indicates that last operation was successful
78603  */
78604 #define PUF_INTSTAT_SUCCESS(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
78605 
78606 #define PUF_INTSTAT_ERROR_MASK                   (0x4U)
78607 #define PUF_INTSTAT_ERROR_SHIFT                  (2U)
78608 /*! ERROR - PUF_ERROR Interrupt Status
78609  *  0b0..PUF is not in the Error state and operations can be performed
78610  *  0b1..PUF is in the Error state and no operations can be performed
78611  */
78612 #define PUF_INTSTAT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
78613 
78614 #define PUF_INTSTAT_KEYINREQ_MASK                (0x10U)
78615 #define PUF_INTSTAT_KEYINREQ_SHIFT               (4U)
78616 /*! KEYINREQ - PUF Key Input Register Interrupt Status
78617  *  0b0..No request for next part of key
78618  *  0b1..Request for next part of key
78619  */
78620 #define PUF_INTSTAT_KEYINREQ(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
78621 
78622 #define PUF_INTSTAT_KEYOUTAVAIL_MASK             (0x20U)
78623 #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT            (5U)
78624 /*! KEYOUTAVAIL - PUF Key Output Register Interrupt Status
78625  *  0b0..Next part of key is not available
78626  *  0b1..Next part of key is available
78627  */
78628 #define PUF_INTSTAT_KEYOUTAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
78629 
78630 #define PUF_INTSTAT_CODEINREQ_MASK               (0x40U)
78631 #define PUF_INTSTAT_CODEINREQ_SHIFT              (6U)
78632 /*! CODEINREQ - PUF Code Input Register Interrupt Status
78633  *  0b0..No request for next part of AC/KC
78634  *  0b1..Request for next part of AC/KC
78635  */
78636 #define PUF_INTSTAT_CODEINREQ(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
78637 
78638 #define PUF_INTSTAT_CODEOUTAVAIL_MASK            (0x80U)
78639 #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT           (7U)
78640 /*! CODEOUTAVAIL - PUF Code Output Register Interrupt Status
78641  *  0b0..Next part of AC/KC is not available
78642  *  0b1..Next part of AC/KC is available
78643  */
78644 #define PUF_INTSTAT_CODEOUTAVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
78645 /*! @} */
78646 
78647 /*! @name PWRCTRL - PUF Power Control Of RAM */
78648 /*! @{ */
78649 
78650 #define PUF_PWRCTRL_RAM_ON_MASK                  (0x1U)
78651 #define PUF_PWRCTRL_RAM_ON_SHIFT                 (0U)
78652 /*! RAM_ON - PUF RAM on
78653  *  0b0..PUF RAM is in sleep mode (PUF operation disabled)
78654  *  0b1..PUF RAM is awake (normal PUF operation enabled)
78655  */
78656 #define PUF_PWRCTRL_RAM_ON(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
78657 
78658 #define PUF_PWRCTRL_CK_DIS_MASK                  (0x4U)
78659 #define PUF_PWRCTRL_CK_DIS_SHIFT                 (2U)
78660 /*! CK_DIS - Clock disable
78661  *  0b0..PUF RAM is clocked (normal PUF operation enabled)
78662  *  0b1..PUF RAM clock is gated/disabled (PUF operation disabled)
78663  */
78664 #define PUF_PWRCTRL_CK_DIS(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
78665 
78666 #define PUF_PWRCTRL_RAM_INITN_MASK               (0x8U)
78667 #define PUF_PWRCTRL_RAM_INITN_SHIFT              (3U)
78668 /*! RAM_INITN - RAM initialization
78669  *  0b0..Reset the PUF RAM (PUF operation disabled)
78670  *  0b1..Do not reset the PUF RAM (normal PUF operation enabled)
78671  */
78672 #define PUF_PWRCTRL_RAM_INITN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK)
78673 
78674 #define PUF_PWRCTRL_RAM_PSW_MASK                 (0xF0U)
78675 #define PUF_PWRCTRL_RAM_PSW_SHIFT                (4U)
78676 /*! RAM_PSW - PUF RAM power switches
78677  */
78678 #define PUF_PWRCTRL_RAM_PSW(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK)
78679 /*! @} */
78680 
78681 /*! @name CFG - PUF Configuration Register */
78682 /*! @{ */
78683 
78684 #define PUF_CFG_PUF_BLOCK_SET_KEY_MASK           (0x1U)
78685 #define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT          (0U)
78686 /*! PUF_BLOCK_SET_KEY - PUF Block Set Key Disable
78687  *  0b0..Enable the Set Key state
78688  *  0b1..Disable the Set Key state
78689  */
78690 #define PUF_CFG_PUF_BLOCK_SET_KEY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK)
78691 
78692 #define PUF_CFG_PUF_BLOCK_ENROLL_MASK            (0x2U)
78693 #define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT           (1U)
78694 /*! PUF_BLOCK_ENROLL - PUF Block Enroll Disable
78695  *  0b0..Enable the Enrollment state
78696  *  0b1..Disable the Enrollment state
78697  */
78698 #define PUF_CFG_PUF_BLOCK_ENROLL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK)
78699 /*! @} */
78700 
78701 /*! @name KEYLOCK - PUF Key Manager Lock */
78702 /*! @{ */
78703 
78704 #define PUF_KEYLOCK_LOCK0_MASK                   (0x3U)
78705 #define PUF_KEYLOCK_LOCK0_SHIFT                  (0U)
78706 /*! LOCK0 - Lock Block 0
78707  *  0b11..SNVS Key block locked
78708  *  0b10..SNVS Key block unlocked
78709  *  0b01..SNVS Key block locked
78710  *  0b00..SNVS Key block locked
78711  */
78712 #define PUF_KEYLOCK_LOCK0(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK)
78713 
78714 #define PUF_KEYLOCK_LOCK1_MASK                   (0xCU)
78715 #define PUF_KEYLOCK_LOCK1_SHIFT                  (2U)
78716 /*! LOCK1 - Lock Block 1
78717  *  0b11..OTFAD Key block locked
78718  *  0b10..OTFAD Key block unlocked
78719  *  0b01..OTFAD Key block locked
78720  *  0b00..OTFAD Key block locked
78721  */
78722 #define PUF_KEYLOCK_LOCK1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK)
78723 /*! @} */
78724 
78725 /*! @name KEYENABLE - PUF Key Manager Enable */
78726 /*! @{ */
78727 
78728 #define PUF_KEYENABLE_ENABLE0_MASK               (0x3U)
78729 #define PUF_KEYENABLE_ENABLE0_SHIFT              (0U)
78730 /*! ENABLE0 - Enable Block 0
78731  *  0b11..Key block 0 disabled
78732  *  0b10..Key block 0 enabled
78733  *  0b01..Key block 0 disabled
78734  *  0b00..Key block 0 disabled
78735  */
78736 #define PUF_KEYENABLE_ENABLE0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK)
78737 
78738 #define PUF_KEYENABLE_ENABLE1_MASK               (0xCU)
78739 #define PUF_KEYENABLE_ENABLE1_SHIFT              (2U)
78740 /*! ENABLE1 - Enable Block 1
78741  *  0b11..Key block 1 disabled
78742  *  0b10..Key block 1 enabled
78743  *  0b01..Key block 1 disabled
78744  *  0b00..Key block 1 disabled
78745  */
78746 #define PUF_KEYENABLE_ENABLE1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK)
78747 /*! @} */
78748 
78749 /*! @name KEYRESET - PUF Key Manager Reset */
78750 /*! @{ */
78751 
78752 #define PUF_KEYRESET_RESET0_MASK                 (0x3U)
78753 #define PUF_KEYRESET_RESET0_SHIFT                (0U)
78754 /*! RESET0 - Reset Block 0
78755  *  0b11..Do not reset key block 0
78756  *  0b10..Reset key block 0
78757  *  0b01..Do not reset key block 0
78758  *  0b00..Do not reset key block 0
78759  */
78760 #define PUF_KEYRESET_RESET0(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK)
78761 
78762 #define PUF_KEYRESET_RESET1_MASK                 (0xCU)
78763 #define PUF_KEYRESET_RESET1_SHIFT                (2U)
78764 /*! RESET1 - Reset Block 1
78765  *  0b11..Do not reset key block 1
78766  *  0b10..Reset key block 1
78767  *  0b01..Do not reset key block 1
78768  *  0b00..Do not reset key block 1
78769  */
78770 #define PUF_KEYRESET_RESET1(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK)
78771 /*! @} */
78772 
78773 /*! @name IDXBLK - PUF Index Block Key Output */
78774 /*! @{ */
78775 
78776 #define PUF_IDXBLK_IDXBLK0_MASK                  (0x3U)
78777 #define PUF_IDXBLK_IDXBLK0_SHIFT                 (0U)
78778 /*! IDXBLK0 - idxblk0
78779  */
78780 #define PUF_IDXBLK_IDXBLK0(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK)
78781 
78782 #define PUF_IDXBLK_IDXBLK1_MASK                  (0xCU)
78783 #define PUF_IDXBLK_IDXBLK1_SHIFT                 (2U)
78784 /*! IDXBLK1 - idxblk1
78785  */
78786 #define PUF_IDXBLK_IDXBLK1(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK)
78787 
78788 #define PUF_IDXBLK_IDXBLK2_MASK                  (0x30U)
78789 #define PUF_IDXBLK_IDXBLK2_SHIFT                 (4U)
78790 /*! IDXBLK2 - idxblk2
78791  */
78792 #define PUF_IDXBLK_IDXBLK2(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK)
78793 
78794 #define PUF_IDXBLK_IDXBLK3_MASK                  (0xC0U)
78795 #define PUF_IDXBLK_IDXBLK3_SHIFT                 (6U)
78796 /*! IDXBLK3 - idxblk3
78797  */
78798 #define PUF_IDXBLK_IDXBLK3(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK)
78799 
78800 #define PUF_IDXBLK_IDXBLK4_MASK                  (0x300U)
78801 #define PUF_IDXBLK_IDXBLK4_SHIFT                 (8U)
78802 /*! IDXBLK4 - idxblk4
78803  */
78804 #define PUF_IDXBLK_IDXBLK4(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK)
78805 
78806 #define PUF_IDXBLK_IDXBLK5_MASK                  (0xC00U)
78807 #define PUF_IDXBLK_IDXBLK5_SHIFT                 (10U)
78808 /*! IDXBLK5 - idxblk5
78809  */
78810 #define PUF_IDXBLK_IDXBLK5(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK)
78811 
78812 #define PUF_IDXBLK_IDXBLK6_MASK                  (0x3000U)
78813 #define PUF_IDXBLK_IDXBLK6_SHIFT                 (12U)
78814 /*! IDXBLK6 - idxblk6
78815  */
78816 #define PUF_IDXBLK_IDXBLK6(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK)
78817 
78818 #define PUF_IDXBLK_IDXBLK7_MASK                  (0xC000U)
78819 #define PUF_IDXBLK_IDXBLK7_SHIFT                 (14U)
78820 /*! IDXBLK7 - idxblk7
78821  */
78822 #define PUF_IDXBLK_IDXBLK7(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK)
78823 
78824 #define PUF_IDXBLK_IDXBLK8_MASK                  (0x30000U)
78825 #define PUF_IDXBLK_IDXBLK8_SHIFT                 (16U)
78826 /*! IDXBLK8 - idxblk8
78827  */
78828 #define PUF_IDXBLK_IDXBLK8(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK)
78829 
78830 #define PUF_IDXBLK_IDXBLK9_MASK                  (0xC0000U)
78831 #define PUF_IDXBLK_IDXBLK9_SHIFT                 (18U)
78832 /*! IDXBLK9 - idxblk9
78833  */
78834 #define PUF_IDXBLK_IDXBLK9(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK)
78835 
78836 #define PUF_IDXBLK_IDXBLK10_MASK                 (0x300000U)
78837 #define PUF_IDXBLK_IDXBLK10_SHIFT                (20U)
78838 /*! IDXBLK10 - idxblk10
78839  */
78840 #define PUF_IDXBLK_IDXBLK10(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK)
78841 
78842 #define PUF_IDXBLK_IDXBLK11_MASK                 (0xC00000U)
78843 #define PUF_IDXBLK_IDXBLK11_SHIFT                (22U)
78844 /*! IDXBLK11 - idxblk11
78845  */
78846 #define PUF_IDXBLK_IDXBLK11(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK)
78847 
78848 #define PUF_IDXBLK_IDXBLK12_MASK                 (0x3000000U)
78849 #define PUF_IDXBLK_IDXBLK12_SHIFT                (24U)
78850 /*! IDXBLK12 - idxblk12
78851  */
78852 #define PUF_IDXBLK_IDXBLK12(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK)
78853 
78854 #define PUF_IDXBLK_IDXBLK13_MASK                 (0xC000000U)
78855 #define PUF_IDXBLK_IDXBLK13_SHIFT                (26U)
78856 /*! IDXBLK13 - idxblk13
78857  */
78858 #define PUF_IDXBLK_IDXBLK13(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK)
78859 
78860 #define PUF_IDXBLK_IDXBLK14_MASK                 (0x30000000U)
78861 #define PUF_IDXBLK_IDXBLK14_SHIFT                (28U)
78862 /*! IDXBLK14 - idxblk14
78863  */
78864 #define PUF_IDXBLK_IDXBLK14(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK)
78865 
78866 #define PUF_IDXBLK_IDXBLK15_MASK                 (0xC0000000U)
78867 #define PUF_IDXBLK_IDXBLK15_SHIFT                (30U)
78868 /*! IDXBLK15 - idxblk15
78869  */
78870 #define PUF_IDXBLK_IDXBLK15(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK)
78871 /*! @} */
78872 
78873 /*! @name IDXBLK_DP - PUF Index Block Key Output */
78874 /*! @{ */
78875 
78876 #define PUF_IDXBLK_DP_IDXBLK_DP0_MASK            (0x3U)
78877 #define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT           (0U)
78878 /*! IDXBLK_DP0 - idxblk_dp0
78879  */
78880 #define PUF_IDXBLK_DP_IDXBLK_DP0(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK)
78881 
78882 #define PUF_IDXBLK_DP_IDXBLK_DP1_MASK            (0xCU)
78883 #define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT           (2U)
78884 /*! IDXBLK_DP1 - idxblk_dp1
78885  */
78886 #define PUF_IDXBLK_DP_IDXBLK_DP1(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK)
78887 
78888 #define PUF_IDXBLK_DP_IDXBLK_DP2_MASK            (0x30U)
78889 #define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT           (4U)
78890 /*! IDXBLK_DP2 - idxblk_dp2
78891  */
78892 #define PUF_IDXBLK_DP_IDXBLK_DP2(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK)
78893 
78894 #define PUF_IDXBLK_DP_IDXBLK_DP3_MASK            (0xC0U)
78895 #define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT           (6U)
78896 /*! IDXBLK_DP3 - idxblk_dp3
78897  */
78898 #define PUF_IDXBLK_DP_IDXBLK_DP3(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK)
78899 
78900 #define PUF_IDXBLK_DP_IDXBLK_DP4_MASK            (0x300U)
78901 #define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT           (8U)
78902 /*! IDXBLK_DP4 - idxblk_dp4
78903  */
78904 #define PUF_IDXBLK_DP_IDXBLK_DP4(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK)
78905 
78906 #define PUF_IDXBLK_DP_IDXBLK_DP5_MASK            (0xC00U)
78907 #define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT           (10U)
78908 /*! IDXBLK_DP5 - idxblk_dp5
78909  */
78910 #define PUF_IDXBLK_DP_IDXBLK_DP5(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK)
78911 
78912 #define PUF_IDXBLK_DP_IDXBLK_DP6_MASK            (0x3000U)
78913 #define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT           (12U)
78914 /*! IDXBLK_DP6 - idxblk_dp6
78915  */
78916 #define PUF_IDXBLK_DP_IDXBLK_DP6(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK)
78917 
78918 #define PUF_IDXBLK_DP_IDXBLK_DP7_MASK            (0xC000U)
78919 #define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT           (14U)
78920 /*! IDXBLK_DP7 - idxblk_dp7
78921  */
78922 #define PUF_IDXBLK_DP_IDXBLK_DP7(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK)
78923 
78924 #define PUF_IDXBLK_DP_IDXBLK_DP8_MASK            (0x30000U)
78925 #define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT           (16U)
78926 /*! IDXBLK_DP8 - idxblk_dp8
78927  */
78928 #define PUF_IDXBLK_DP_IDXBLK_DP8(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK)
78929 
78930 #define PUF_IDXBLK_DP_IDXBLK_DP9_MASK            (0xC0000U)
78931 #define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT           (18U)
78932 /*! IDXBLK_DP9 - idxblk_dp9
78933  */
78934 #define PUF_IDXBLK_DP_IDXBLK_DP9(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK)
78935 
78936 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK           (0x300000U)
78937 #define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT          (20U)
78938 /*! IDXBLK_DP10 - idxblk_dp10
78939  */
78940 #define PUF_IDXBLK_DP_IDXBLK_DP10(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
78941 
78942 #define PUF_IDXBLK_DP_IDXBLK_DP11_MASK           (0xC00000U)
78943 #define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT          (22U)
78944 /*! IDXBLK_DP11 - idxblk_dp11
78945  */
78946 #define PUF_IDXBLK_DP_IDXBLK_DP11(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK)
78947 
78948 #define PUF_IDXBLK_DP_IDXBLK_DP12_MASK           (0x3000000U)
78949 #define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT          (24U)
78950 /*! IDXBLK_DP12 - idxblk_dp12
78951  */
78952 #define PUF_IDXBLK_DP_IDXBLK_DP12(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK)
78953 
78954 #define PUF_IDXBLK_DP_IDXBLK_DP13_MASK           (0xC000000U)
78955 #define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT          (26U)
78956 /*! IDXBLK_DP13 - idxblk_dp13
78957  */
78958 #define PUF_IDXBLK_DP_IDXBLK_DP13(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK)
78959 
78960 #define PUF_IDXBLK_DP_IDXBLK_DP14_MASK           (0x30000000U)
78961 #define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT          (28U)
78962 /*! IDXBLK_DP14 - idxblk_dp14
78963  */
78964 #define PUF_IDXBLK_DP_IDXBLK_DP14(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK)
78965 
78966 #define PUF_IDXBLK_DP_IDXBLK_DP15_MASK           (0xC0000000U)
78967 #define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT          (30U)
78968 /*! IDXBLK_DP15 - idxblk_dp15
78969  */
78970 #define PUF_IDXBLK_DP_IDXBLK_DP15(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK)
78971 /*! @} */
78972 
78973 /*! @name KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable */
78974 /*! @{ */
78975 
78976 #define PUF_KEYMASK_KEYMASK_MASK                 (0xFFFFFFFFU)
78977 #define PUF_KEYMASK_KEYMASK_SHIFT                (0U)
78978 /*! KEYMASK - KEYMASK1
78979  */
78980 #define PUF_KEYMASK_KEYMASK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
78981 /*! @} */
78982 
78983 /* The count of PUF_KEYMASK */
78984 #define PUF_KEYMASK_COUNT                        (2U)
78985 
78986 /*! @name IDXBLK_STATUS - PUF Index Block Setting Status Register */
78987 /*! @{ */
78988 
78989 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK    (0x3U)
78990 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT   (0U)
78991 /*! IDXBLK_STATUS0 - idxblk_status0
78992  */
78993 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK)
78994 
78995 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK    (0xCU)
78996 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT   (2U)
78997 /*! IDXBLK_STATUS1 - idxblk_status1
78998  */
78999 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
79000 
79001 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK    (0x30U)
79002 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT   (4U)
79003 /*! IDXBLK_STATUS2 - idxblk_status2
79004  */
79005 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK)
79006 
79007 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK    (0xC0U)
79008 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT   (6U)
79009 /*! IDXBLK_STATUS3 - idxblk_status3
79010  */
79011 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK)
79012 
79013 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK    (0x300U)
79014 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT   (8U)
79015 /*! IDXBLK_STATUS4 - idxblk_status4
79016  */
79017 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK)
79018 
79019 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK    (0xC00U)
79020 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT   (10U)
79021 /*! IDXBLK_STATUS5 - idxblk_status5
79022  */
79023 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK)
79024 
79025 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK    (0x3000U)
79026 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT   (12U)
79027 /*! IDXBLK_STATUS6 - idxblk_status6
79028  */
79029 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK)
79030 
79031 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK    (0xC000U)
79032 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT   (14U)
79033 /*! IDXBLK_STATUS7 - idxblk_status7
79034  */
79035 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK)
79036 
79037 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK    (0x30000U)
79038 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT   (16U)
79039 /*! IDXBLK_STATUS8 - idxblk_status8
79040  */
79041 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK)
79042 
79043 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK    (0xC0000U)
79044 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT   (18U)
79045 /*! IDXBLK_STATUS9 - idxblk_status9
79046  */
79047 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK)
79048 
79049 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK   (0x300000U)
79050 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT  (20U)
79051 /*! IDXBLK_STATUS10 - idxblk_status10
79052  */
79053 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK)
79054 
79055 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK   (0xC00000U)
79056 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT  (22U)
79057 /*! IDXBLK_STATUS11 - idxblk_status11
79058  */
79059 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK)
79060 
79061 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK   (0x3000000U)
79062 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT  (24U)
79063 /*! IDXBLK_STATUS12 - idxblk_status12
79064  */
79065 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK)
79066 
79067 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK   (0xC000000U)
79068 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT  (26U)
79069 /*! IDXBLK_STATUS13 - idxblk_status13
79070  */
79071 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK)
79072 
79073 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK   (0x30000000U)
79074 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT  (28U)
79075 /*! IDXBLK_STATUS14 - idxblk_status14
79076  */
79077 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK)
79078 
79079 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK   (0xC0000000U)
79080 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT  (30U)
79081 /*! IDXBLK_STATUS15 - idxblk_status15
79082  */
79083 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK)
79084 /*! @} */
79085 
79086 /*! @name IDXBLK_SHIFT - PUF Key Manager Shift Status */
79087 /*! @{ */
79088 
79089 #define PUF_IDXBLK_SHIFT_IND_KEY0_MASK           (0xFU)
79090 #define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT          (0U)
79091 /*! IND_KEY0 - Index of key space in block 0
79092  */
79093 #define PUF_IDXBLK_SHIFT_IND_KEY0(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK)
79094 
79095 #define PUF_IDXBLK_SHIFT_IND_KEY1_MASK           (0xF0U)
79096 #define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT          (4U)
79097 /*! IND_KEY1 - Index of key space in block 1
79098  */
79099 #define PUF_IDXBLK_SHIFT_IND_KEY1(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK)
79100 /*! @} */
79101 
79102 
79103 /*!
79104  * @}
79105  */ /* end of group PUF_Register_Masks */
79106 
79107 
79108 /* PUF - Peripheral instance base addresses */
79109 /** Peripheral KEY_MANAGER__PUF base address */
79110 #define KEY_MANAGER__PUF_BASE                    (0x40C82000u)
79111 /** Peripheral KEY_MANAGER__PUF base pointer */
79112 #define KEY_MANAGER__PUF                         ((PUF_Type *)KEY_MANAGER__PUF_BASE)
79113 /** Array initializer of PUF peripheral base addresses */
79114 #define PUF_BASE_ADDRS                           { KEY_MANAGER__PUF_BASE }
79115 /** Array initializer of PUF peripheral base pointers */
79116 #define PUF_BASE_PTRS                            { KEY_MANAGER__PUF }
79117 
79118 /*!
79119  * @}
79120  */ /* end of group PUF_Peripheral_Access_Layer */
79121 
79122 
79123 /* ----------------------------------------------------------------------------
79124    -- PWM Peripheral Access Layer
79125    ---------------------------------------------------------------------------- */
79126 
79127 /*!
79128  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
79129  * @{
79130  */
79131 
79132 /** PWM - Register Layout Typedef */
79133 typedef struct {
79134   struct {                                         /* offset: 0x0, array step: 0x60 */
79135     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
79136     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
79137     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
79138     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
79139          uint8_t RESERVED_0[2];
79140     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
79141     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
79142     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
79143     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
79144     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
79145     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
79146     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
79147     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
79148     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
79149     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
79150     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
79151     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
79152     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
79153     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
79154     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
79155     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
79156     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
79157     __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
79158          uint8_t RESERVED_1[2];
79159     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
79160     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
79161     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
79162     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
79163     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
79164     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
79165     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
79166     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
79167     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
79168     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
79169     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
79170     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
79171     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
79172     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
79173     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
79174     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
79175     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
79176     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
79177     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
79178     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
79179          uint8_t RESERVED_2[8];
79180   } SM[4];
79181   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
79182   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
79183   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
79184   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
79185   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
79186   __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
79187   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
79188   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
79189   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
79190   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
79191   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
79192 } PWM_Type;
79193 
79194 /* ----------------------------------------------------------------------------
79195    -- PWM Register Masks
79196    ---------------------------------------------------------------------------- */
79197 
79198 /*!
79199  * @addtogroup PWM_Register_Masks PWM Register Masks
79200  * @{
79201  */
79202 
79203 /*! @name CNT - Counter Register */
79204 /*! @{ */
79205 
79206 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
79207 #define PWM_CNT_CNT_SHIFT                        (0U)
79208 /*! CNT - Counter Register Bits
79209  */
79210 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
79211 /*! @} */
79212 
79213 /* The count of PWM_CNT */
79214 #define PWM_CNT_COUNT                            (4U)
79215 
79216 /*! @name INIT - Initial Count Register */
79217 /*! @{ */
79218 
79219 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
79220 #define PWM_INIT_INIT_SHIFT                      (0U)
79221 /*! INIT - Initial Count Register Bits
79222  */
79223 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
79224 /*! @} */
79225 
79226 /* The count of PWM_INIT */
79227 #define PWM_INIT_COUNT                           (4U)
79228 
79229 /*! @name CTRL2 - Control 2 Register */
79230 /*! @{ */
79231 
79232 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
79233 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
79234 /*! CLK_SEL - Clock Source Select
79235  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
79236  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
79237  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
79238  *        setting should not be used in submodule 0 as it will force the clock to logic 0.
79239  *  0b11..reserved
79240  */
79241 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
79242 
79243 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
79244 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
79245 /*! RELOAD_SEL - Reload Source Select
79246  *  0b0..The local RELOAD signal is used to reload registers.
79247  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
79248  *       in submodule 0 as it will force the RELOAD signal to logic 0.
79249  */
79250 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
79251 
79252 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
79253 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
79254 /*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
79255  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
79256  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
79257  *         submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
79258  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
79259  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
79260  *         not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
79261  *  0b100..The local sync signal from this submodule is used to force updates.
79262  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
79263  *         submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
79264  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
79265  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
79266  */
79267 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
79268 
79269 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
79270 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
79271 /*! FORCE - Force Initialization
79272  */
79273 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
79274 
79275 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
79276 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
79277 /*! FRCEN - FRCEN
79278  *  0b0..Initialization from a FORCE_OUT is disabled.
79279  *  0b1..Initialization from a FORCE_OUT is enabled.
79280  */
79281 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
79282 
79283 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
79284 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
79285 /*! INIT_SEL - Initialization Control Select
79286  *  0b00..Local sync (PWM_X) causes initialization.
79287  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
79288  *        it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
79289  *        reload occurs.
79290  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
79291  *        will force the INIT signal to logic 0.
79292  *  0b11..EXT_SYNC causes initialization.
79293  */
79294 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
79295 
79296 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
79297 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
79298 /*! PWMX_INIT - PWM_X Initial Value
79299  */
79300 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
79301 
79302 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
79303 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
79304 /*! PWM45_INIT - PWM45 Initial Value
79305  */
79306 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
79307 
79308 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
79309 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
79310 /*! PWM23_INIT - PWM23 Initial Value
79311  */
79312 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
79313 
79314 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
79315 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
79316 /*! INDEP - Independent or Complementary Pair Operation
79317  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
79318  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
79319  */
79320 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
79321 
79322 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
79323 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
79324 /*! WAITEN - WAIT Enable
79325  */
79326 #define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
79327 
79328 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
79329 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
79330 /*! DBGEN - Debug Enable
79331  */
79332 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
79333 /*! @} */
79334 
79335 /* The count of PWM_CTRL2 */
79336 #define PWM_CTRL2_COUNT                          (4U)
79337 
79338 /*! @name CTRL - Control Register */
79339 /*! @{ */
79340 
79341 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
79342 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
79343 /*! DBLEN - Double Switching Enable
79344  *  0b0..Double switching disabled.
79345  *  0b1..Double switching enabled.
79346  */
79347 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
79348 
79349 #define PWM_CTRL_DBLX_MASK                       (0x2U)
79350 #define PWM_CTRL_DBLX_SHIFT                      (1U)
79351 /*! DBLX - PWMX Double Switching Enable
79352  *  0b0..PWMX double pulse disabled.
79353  *  0b1..PWMX double pulse enabled.
79354  */
79355 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
79356 
79357 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
79358 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
79359 /*! LDMOD - Load Mode Select
79360  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
79361  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
79362  *       In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
79363  */
79364 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
79365 
79366 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
79367 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
79368 /*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
79369  *  0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
79370  *  0b1..DBLPWM is split to PWMA and PWMB.
79371  */
79372 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
79373 
79374 #define PWM_CTRL_PRSC_MASK                       (0x70U)
79375 #define PWM_CTRL_PRSC_SHIFT                      (4U)
79376 /*! PRSC - Prescaler
79377  *  0b000..Prescaler 1
79378  *  0b001..Prescaler 2
79379  *  0b010..Prescaler 4
79380  *  0b011..Prescaler 8
79381  *  0b100..Prescaler 16
79382  *  0b101..Prescaler 32
79383  *  0b110..Prescaler 64
79384  *  0b111..Prescaler 128
79385  */
79386 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
79387 
79388 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
79389 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
79390 /*! COMPMODE - Compare Mode
79391  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
79392  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
79393  *       output that is high at the end of a period will maintain this state until a match with VAL3 clears the
79394  *       output in the following period.
79395  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
79396  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
79397  *       values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
79398  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
79399  */
79400 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
79401 
79402 #define PWM_CTRL_DT_MASK                         (0x300U)
79403 #define PWM_CTRL_DT_SHIFT                        (8U)
79404 /*! DT - Deadtime
79405  */
79406 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
79407 
79408 #define PWM_CTRL_FULL_MASK                       (0x400U)
79409 #define PWM_CTRL_FULL_SHIFT                      (10U)
79410 /*! FULL - Full Cycle Reload
79411  *  0b0..Full-cycle reloads disabled.
79412  *  0b1..Full-cycle reloads enabled.
79413  */
79414 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
79415 
79416 #define PWM_CTRL_HALF_MASK                       (0x800U)
79417 #define PWM_CTRL_HALF_SHIFT                      (11U)
79418 /*! HALF - Half Cycle Reload
79419  *  0b0..Half-cycle reloads disabled.
79420  *  0b1..Half-cycle reloads enabled.
79421  */
79422 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
79423 
79424 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
79425 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
79426 /*! LDFQ - Load Frequency
79427  *  0b0000..Every PWM opportunity
79428  *  0b0001..Every 2 PWM opportunities
79429  *  0b0010..Every 3 PWM opportunities
79430  *  0b0011..Every 4 PWM opportunities
79431  *  0b0100..Every 5 PWM opportunities
79432  *  0b0101..Every 6 PWM opportunities
79433  *  0b0110..Every 7 PWM opportunities
79434  *  0b0111..Every 8 PWM opportunities
79435  *  0b1000..Every 9 PWM opportunities
79436  *  0b1001..Every 10 PWM opportunities
79437  *  0b1010..Every 11 PWM opportunities
79438  *  0b1011..Every 12 PWM opportunities
79439  *  0b1100..Every 13 PWM opportunities
79440  *  0b1101..Every 14 PWM opportunities
79441  *  0b1110..Every 15 PWM opportunities
79442  *  0b1111..Every 16 PWM opportunities
79443  */
79444 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
79445 /*! @} */
79446 
79447 /* The count of PWM_CTRL */
79448 #define PWM_CTRL_COUNT                           (4U)
79449 
79450 /*! @name VAL0 - Value Register 0 */
79451 /*! @{ */
79452 
79453 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
79454 #define PWM_VAL0_VAL0_SHIFT                      (0U)
79455 /*! VAL0 - Value Register 0
79456  */
79457 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
79458 /*! @} */
79459 
79460 /* The count of PWM_VAL0 */
79461 #define PWM_VAL0_COUNT                           (4U)
79462 
79463 /*! @name FRACVAL1 - Fractional Value Register 1 */
79464 /*! @{ */
79465 
79466 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
79467 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
79468 /*! FRACVAL1 - Fractional Value 1 Register
79469  */
79470 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
79471 /*! @} */
79472 
79473 /* The count of PWM_FRACVAL1 */
79474 #define PWM_FRACVAL1_COUNT                       (4U)
79475 
79476 /*! @name VAL1 - Value Register 1 */
79477 /*! @{ */
79478 
79479 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
79480 #define PWM_VAL1_VAL1_SHIFT                      (0U)
79481 /*! VAL1 - Value Register 1
79482  */
79483 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
79484 /*! @} */
79485 
79486 /* The count of PWM_VAL1 */
79487 #define PWM_VAL1_COUNT                           (4U)
79488 
79489 /*! @name FRACVAL2 - Fractional Value Register 2 */
79490 /*! @{ */
79491 
79492 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
79493 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
79494 /*! FRACVAL2 - Fractional Value 2
79495  */
79496 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
79497 /*! @} */
79498 
79499 /* The count of PWM_FRACVAL2 */
79500 #define PWM_FRACVAL2_COUNT                       (4U)
79501 
79502 /*! @name VAL2 - Value Register 2 */
79503 /*! @{ */
79504 
79505 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
79506 #define PWM_VAL2_VAL2_SHIFT                      (0U)
79507 /*! VAL2 - Value Register 2
79508  */
79509 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
79510 /*! @} */
79511 
79512 /* The count of PWM_VAL2 */
79513 #define PWM_VAL2_COUNT                           (4U)
79514 
79515 /*! @name FRACVAL3 - Fractional Value Register 3 */
79516 /*! @{ */
79517 
79518 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
79519 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
79520 /*! FRACVAL3 - Fractional Value 3
79521  */
79522 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
79523 /*! @} */
79524 
79525 /* The count of PWM_FRACVAL3 */
79526 #define PWM_FRACVAL3_COUNT                       (4U)
79527 
79528 /*! @name VAL3 - Value Register 3 */
79529 /*! @{ */
79530 
79531 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
79532 #define PWM_VAL3_VAL3_SHIFT                      (0U)
79533 /*! VAL3 - Value Register 3
79534  */
79535 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
79536 /*! @} */
79537 
79538 /* The count of PWM_VAL3 */
79539 #define PWM_VAL3_COUNT                           (4U)
79540 
79541 /*! @name FRACVAL4 - Fractional Value Register 4 */
79542 /*! @{ */
79543 
79544 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
79545 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
79546 /*! FRACVAL4 - Fractional Value 4
79547  */
79548 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
79549 /*! @} */
79550 
79551 /* The count of PWM_FRACVAL4 */
79552 #define PWM_FRACVAL4_COUNT                       (4U)
79553 
79554 /*! @name VAL4 - Value Register 4 */
79555 /*! @{ */
79556 
79557 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
79558 #define PWM_VAL4_VAL4_SHIFT                      (0U)
79559 /*! VAL4 - Value Register 4
79560  */
79561 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
79562 /*! @} */
79563 
79564 /* The count of PWM_VAL4 */
79565 #define PWM_VAL4_COUNT                           (4U)
79566 
79567 /*! @name FRACVAL5 - Fractional Value Register 5 */
79568 /*! @{ */
79569 
79570 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
79571 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
79572 /*! FRACVAL5 - Fractional Value 5
79573  */
79574 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
79575 /*! @} */
79576 
79577 /* The count of PWM_FRACVAL5 */
79578 #define PWM_FRACVAL5_COUNT                       (4U)
79579 
79580 /*! @name VAL5 - Value Register 5 */
79581 /*! @{ */
79582 
79583 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
79584 #define PWM_VAL5_VAL5_SHIFT                      (0U)
79585 /*! VAL5 - Value Register 5
79586  */
79587 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
79588 /*! @} */
79589 
79590 /* The count of PWM_VAL5 */
79591 #define PWM_VAL5_COUNT                           (4U)
79592 
79593 /*! @name FRCTRL - Fractional Control Register */
79594 /*! @{ */
79595 
79596 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
79597 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
79598 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
79599  *  0b0..Disable fractional cycle length for the PWM period.
79600  *  0b1..Enable fractional cycle length for the PWM period.
79601  */
79602 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
79603 
79604 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
79605 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
79606 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
79607  *  0b0..Disable fractional cycle placement for PWM_A.
79608  *  0b1..Enable fractional cycle placement for PWM_A.
79609  */
79610 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
79611 
79612 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
79613 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
79614 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
79615  *  0b0..Disable fractional cycle placement for PWM_B.
79616  *  0b1..Enable fractional cycle placement for PWM_B.
79617  */
79618 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
79619 
79620 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
79621 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
79622 /*! TEST - Test Status Bit
79623  */
79624 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
79625 /*! @} */
79626 
79627 /* The count of PWM_FRCTRL */
79628 #define PWM_FRCTRL_COUNT                         (4U)
79629 
79630 /*! @name OCTRL - Output Control Register */
79631 /*! @{ */
79632 
79633 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
79634 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
79635 /*! PWMXFS - PWM_X Fault State
79636  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
79637  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
79638  *  0b10, 0b11..Output is tristated.
79639  */
79640 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
79641 
79642 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
79643 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
79644 /*! PWMBFS - PWM_B Fault State
79645  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
79646  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
79647  *  0b10, 0b11..Output is tristated.
79648  */
79649 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
79650 
79651 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
79652 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
79653 /*! PWMAFS - PWM_A Fault State
79654  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
79655  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
79656  *  0b10, 0b11..Output is tristated.
79657  */
79658 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
79659 
79660 #define PWM_OCTRL_POLX_MASK                      (0x100U)
79661 #define PWM_OCTRL_POLX_SHIFT                     (8U)
79662 /*! POLX - PWM_X Output Polarity
79663  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
79664  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
79665  */
79666 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
79667 
79668 #define PWM_OCTRL_POLB_MASK                      (0x200U)
79669 #define PWM_OCTRL_POLB_SHIFT                     (9U)
79670 /*! POLB - PWM_B Output Polarity
79671  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
79672  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
79673  */
79674 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
79675 
79676 #define PWM_OCTRL_POLA_MASK                      (0x400U)
79677 #define PWM_OCTRL_POLA_SHIFT                     (10U)
79678 /*! POLA - PWM_A Output Polarity
79679  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
79680  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
79681  */
79682 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
79683 
79684 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
79685 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
79686 /*! PWMX_IN - PWM_X Input
79687  */
79688 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
79689 
79690 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
79691 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
79692 /*! PWMB_IN - PWM_B Input
79693  */
79694 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
79695 
79696 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
79697 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
79698 /*! PWMA_IN - PWM_A Input
79699  */
79700 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
79701 /*! @} */
79702 
79703 /* The count of PWM_OCTRL */
79704 #define PWM_OCTRL_COUNT                          (4U)
79705 
79706 /*! @name STS - Status Register */
79707 /*! @{ */
79708 
79709 #define PWM_STS_CMPF_MASK                        (0x3FU)
79710 #define PWM_STS_CMPF_SHIFT                       (0U)
79711 /*! CMPF - Compare Flags
79712  *  0b000000..No compare event has occurred for a particular VALx value.
79713  *  0b000001..A compare event has occurred for a particular VALx value.
79714  */
79715 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
79716 
79717 #define PWM_STS_CFX0_MASK                        (0x40U)
79718 #define PWM_STS_CFX0_SHIFT                       (6U)
79719 /*! CFX0 - Capture Flag X0
79720  */
79721 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
79722 
79723 #define PWM_STS_CFX1_MASK                        (0x80U)
79724 #define PWM_STS_CFX1_SHIFT                       (7U)
79725 /*! CFX1 - Capture Flag X1
79726  */
79727 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
79728 
79729 #define PWM_STS_CFB0_MASK                        (0x100U)
79730 #define PWM_STS_CFB0_SHIFT                       (8U)
79731 /*! CFB0 - Capture Flag B0
79732  */
79733 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
79734 
79735 #define PWM_STS_CFB1_MASK                        (0x200U)
79736 #define PWM_STS_CFB1_SHIFT                       (9U)
79737 /*! CFB1 - Capture Flag B1
79738  */
79739 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
79740 
79741 #define PWM_STS_CFA0_MASK                        (0x400U)
79742 #define PWM_STS_CFA0_SHIFT                       (10U)
79743 /*! CFA0 - Capture Flag A0
79744  */
79745 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
79746 
79747 #define PWM_STS_CFA1_MASK                        (0x800U)
79748 #define PWM_STS_CFA1_SHIFT                       (11U)
79749 /*! CFA1 - Capture Flag A1
79750  */
79751 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
79752 
79753 #define PWM_STS_RF_MASK                          (0x1000U)
79754 #define PWM_STS_RF_SHIFT                         (12U)
79755 /*! RF - Reload Flag
79756  *  0b0..No new reload cycle since last STS[RF] clearing
79757  *  0b1..New reload cycle since last STS[RF] clearing
79758  */
79759 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
79760 
79761 #define PWM_STS_REF_MASK                         (0x2000U)
79762 #define PWM_STS_REF_SHIFT                        (13U)
79763 /*! REF - Reload Error Flag
79764  *  0b0..No reload error occurred.
79765  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
79766  */
79767 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
79768 
79769 #define PWM_STS_RUF_MASK                         (0x4000U)
79770 #define PWM_STS_RUF_SHIFT                        (14U)
79771 /*! RUF - Registers Updated Flag
79772  *  0b0..No register update has occurred since last reload.
79773  *  0b1..At least one of the double buffered registers has been updated since the last reload.
79774  */
79775 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
79776 /*! @} */
79777 
79778 /* The count of PWM_STS */
79779 #define PWM_STS_COUNT                            (4U)
79780 
79781 /*! @name INTEN - Interrupt Enable Register */
79782 /*! @{ */
79783 
79784 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
79785 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
79786 /*! CMPIE - Compare Interrupt Enables
79787  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
79788  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
79789  */
79790 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
79791 
79792 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
79793 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
79794 /*! CX0IE - Capture X 0 Interrupt Enable
79795  *  0b0..Interrupt request disabled for STS[CFX0].
79796  *  0b1..Interrupt request enabled for STS[CFX0].
79797  */
79798 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
79799 
79800 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
79801 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
79802 /*! CX1IE - Capture X 1 Interrupt Enable
79803  *  0b0..Interrupt request disabled for STS[CFX1].
79804  *  0b1..Interrupt request enabled for STS[CFX1].
79805  */
79806 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
79807 
79808 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
79809 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
79810 /*! CB0IE - Capture B 0 Interrupt Enable
79811  *  0b0..Interrupt request disabled for STS[CFB0].
79812  *  0b1..Interrupt request enabled for STS[CFB0].
79813  */
79814 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
79815 
79816 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
79817 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
79818 /*! CB1IE - Capture B 1 Interrupt Enable
79819  *  0b0..Interrupt request disabled for STS[CFB1].
79820  *  0b1..Interrupt request enabled for STS[CFB1].
79821  */
79822 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
79823 
79824 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
79825 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
79826 /*! CA0IE - Capture A 0 Interrupt Enable
79827  *  0b0..Interrupt request disabled for STS[CFA0].
79828  *  0b1..Interrupt request enabled for STS[CFA0].
79829  */
79830 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
79831 
79832 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
79833 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
79834 /*! CA1IE - Capture A 1 Interrupt Enable
79835  *  0b0..Interrupt request disabled for STS[CFA1].
79836  *  0b1..Interrupt request enabled for STS[CFA1].
79837  */
79838 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
79839 
79840 #define PWM_INTEN_RIE_MASK                       (0x1000U)
79841 #define PWM_INTEN_RIE_SHIFT                      (12U)
79842 /*! RIE - Reload Interrupt Enable
79843  *  0b0..STS[RF] CPU interrupt requests disabled
79844  *  0b1..STS[RF] CPU interrupt requests enabled
79845  */
79846 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
79847 
79848 #define PWM_INTEN_REIE_MASK                      (0x2000U)
79849 #define PWM_INTEN_REIE_SHIFT                     (13U)
79850 /*! REIE - Reload Error Interrupt Enable
79851  *  0b0..STS[REF] CPU interrupt requests disabled
79852  *  0b1..STS[REF] CPU interrupt requests enabled
79853  */
79854 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
79855 /*! @} */
79856 
79857 /* The count of PWM_INTEN */
79858 #define PWM_INTEN_COUNT                          (4U)
79859 
79860 /*! @name DMAEN - DMA Enable Register */
79861 /*! @{ */
79862 
79863 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
79864 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
79865 /*! CX0DE - Capture X0 FIFO DMA Enable
79866  */
79867 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
79868 
79869 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
79870 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
79871 /*! CX1DE - Capture X1 FIFO DMA Enable
79872  */
79873 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
79874 
79875 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
79876 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
79877 /*! CB0DE - Capture B0 FIFO DMA Enable
79878  */
79879 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
79880 
79881 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
79882 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
79883 /*! CB1DE - Capture B1 FIFO DMA Enable
79884  */
79885 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
79886 
79887 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
79888 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
79889 /*! CA0DE - Capture A0 FIFO DMA Enable
79890  */
79891 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
79892 
79893 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
79894 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
79895 /*! CA1DE - Capture A1 FIFO DMA Enable
79896  */
79897 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
79898 
79899 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
79900 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
79901 /*! CAPTDE - Capture DMA Enable Source Select
79902  *  0b00..Read DMA requests disabled.
79903  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
79904  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
79905  *        which watermark(s) the DMA request is sensitive.
79906  *  0b10..A local sync (VAL1 matches counter) sets the read DMA request.
79907  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
79908  */
79909 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
79910 
79911 #define PWM_DMAEN_FAND_MASK                      (0x100U)
79912 #define PWM_DMAEN_FAND_SHIFT                     (8U)
79913 /*! FAND - FIFO Watermark AND Control
79914  *  0b0..Selected FIFO watermarks are OR'ed together.
79915  *  0b1..Selected FIFO watermarks are AND'ed together.
79916  */
79917 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
79918 
79919 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
79920 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
79921 /*! VALDE - Value Registers DMA Enable
79922  *  0b0..DMA write requests disabled
79923  *  0b1..Enabled
79924  */
79925 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
79926 /*! @} */
79927 
79928 /* The count of PWM_DMAEN */
79929 #define PWM_DMAEN_COUNT                          (4U)
79930 
79931 /*! @name TCTRL - Output Trigger Control Register */
79932 /*! @{ */
79933 
79934 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
79935 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
79936 /*! OUT_TRIG_EN - Output Trigger Enables
79937  *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
79938  *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
79939  *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
79940  *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
79941  *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
79942  *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
79943  */
79944 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
79945 
79946 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
79947 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
79948 /*! TRGFRQ - Trigger frequency
79949  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
79950  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
79951  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
79952  */
79953 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
79954 
79955 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
79956 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
79957 /*! PWBOT1 - Output Trigger 1 Source Select
79958  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
79959  *  0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
79960  */
79961 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
79962 
79963 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
79964 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
79965 /*! PWAOT0 - Output Trigger 0 Source Select
79966  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
79967  *  0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
79968  */
79969 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
79970 /*! @} */
79971 
79972 /* The count of PWM_TCTRL */
79973 #define PWM_TCTRL_COUNT                          (4U)
79974 
79975 /*! @name DISMAP - Fault Disable Mapping Register 0 */
79976 /*! @{ */
79977 
79978 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
79979 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
79980 /*! DIS0A - PWM_A Fault Disable Mask 0
79981  */
79982 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
79983 
79984 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
79985 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
79986 /*! DIS0B - PWM_B Fault Disable Mask 0
79987  */
79988 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
79989 
79990 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
79991 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
79992 /*! DIS0X - PWM_X Fault Disable Mask 0
79993  */
79994 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
79995 /*! @} */
79996 
79997 /* The count of PWM_DISMAP */
79998 #define PWM_DISMAP_COUNT                         (4U)
79999 
80000 /* The count of PWM_DISMAP */
80001 #define PWM_DISMAP_COUNT2                        (1U)
80002 
80003 /*! @name DTCNT0 - Deadtime Count Register 0 */
80004 /*! @{ */
80005 
80006 #define PWM_DTCNT0_DTCNT0_MASK                   (0xFFFFU)
80007 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
80008 /*! DTCNT0 - DTCNT0
80009  */
80010 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
80011 /*! @} */
80012 
80013 /* The count of PWM_DTCNT0 */
80014 #define PWM_DTCNT0_COUNT                         (4U)
80015 
80016 /*! @name DTCNT1 - Deadtime Count Register 1 */
80017 /*! @{ */
80018 
80019 #define PWM_DTCNT1_DTCNT1_MASK                   (0xFFFFU)
80020 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
80021 /*! DTCNT1 - DTCNT1
80022  */
80023 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
80024 /*! @} */
80025 
80026 /* The count of PWM_DTCNT1 */
80027 #define PWM_DTCNT1_COUNT                         (4U)
80028 
80029 /*! @name CAPTCTRLA - Capture Control A Register */
80030 /*! @{ */
80031 
80032 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
80033 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
80034 /*! ARMA - Arm A
80035  *  0b0..Input capture operation is disabled.
80036  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
80037  */
80038 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
80039 
80040 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
80041 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
80042 /*! ONESHOTA - One Shot Mode A
80043  *  0b0..Free Running
80044  *  0b1..One Shot
80045  */
80046 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
80047 
80048 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
80049 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
80050 /*! EDGA0 - Edge A 0
80051  *  0b00..Disabled
80052  *  0b01..Capture falling edges
80053  *  0b10..Capture rising edges
80054  *  0b11..Capture any edge
80055  */
80056 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
80057 
80058 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
80059 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
80060 /*! EDGA1 - Edge A 1
80061  *  0b00..Disabled
80062  *  0b01..Capture falling edges
80063  *  0b10..Capture rising edges
80064  *  0b11..Capture any edge
80065  */
80066 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
80067 
80068 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
80069 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
80070 /*! INP_SELA - Input Select A
80071  *  0b0..Raw PWM_A input signal selected as source.
80072  *  0b1..Edge Counter
80073  */
80074 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
80075 
80076 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
80077 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
80078 /*! EDGCNTA_EN - Edge Counter A Enable
80079  *  0b0..Edge counter disabled and held in reset
80080  *  0b1..Edge counter enabled
80081  */
80082 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
80083 
80084 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
80085 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
80086 /*! CFAWM - Capture A FIFOs Water Mark
80087  */
80088 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
80089 
80090 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
80091 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
80092 /*! CA0CNT - Capture A0 FIFO Word Count
80093  */
80094 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
80095 
80096 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
80097 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
80098 /*! CA1CNT - Capture A1 FIFO Word Count
80099  */
80100 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
80101 /*! @} */
80102 
80103 /* The count of PWM_CAPTCTRLA */
80104 #define PWM_CAPTCTRLA_COUNT                      (4U)
80105 
80106 /*! @name CAPTCOMPA - Capture Compare A Register */
80107 /*! @{ */
80108 
80109 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
80110 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
80111 /*! EDGCMPA - Edge Compare A
80112  */
80113 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
80114 
80115 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
80116 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
80117 /*! EDGCNTA - Edge Counter A
80118  */
80119 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
80120 /*! @} */
80121 
80122 /* The count of PWM_CAPTCOMPA */
80123 #define PWM_CAPTCOMPA_COUNT                      (4U)
80124 
80125 /*! @name CAPTCTRLB - Capture Control B Register */
80126 /*! @{ */
80127 
80128 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
80129 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
80130 /*! ARMB - Arm B
80131  *  0b0..Input capture operation is disabled.
80132  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
80133  */
80134 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
80135 
80136 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
80137 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
80138 /*! ONESHOTB - One Shot Mode B
80139  *  0b0..Free Running
80140  *  0b1..One Shot
80141  */
80142 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
80143 
80144 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
80145 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
80146 /*! EDGB0 - Edge B 0
80147  *  0b00..Disabled
80148  *  0b01..Capture falling edges
80149  *  0b10..Capture rising edges
80150  *  0b11..Capture any edge
80151  */
80152 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
80153 
80154 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
80155 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
80156 /*! EDGB1 - Edge B 1
80157  *  0b00..Disabled
80158  *  0b01..Capture falling edges
80159  *  0b10..Capture rising edges
80160  *  0b11..Capture any edge
80161  */
80162 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
80163 
80164 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
80165 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
80166 /*! INP_SELB - Input Select B
80167  *  0b0..Raw PWM_B input signal selected as source.
80168  *  0b1..Edge Counter
80169  */
80170 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
80171 
80172 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
80173 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
80174 /*! EDGCNTB_EN - Edge Counter B Enable
80175  *  0b0..Edge counter disabled and held in reset
80176  *  0b1..Edge counter enabled
80177  */
80178 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
80179 
80180 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
80181 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
80182 /*! CFBWM - Capture B FIFOs Water Mark
80183  */
80184 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
80185 
80186 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
80187 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
80188 /*! CB0CNT - Capture B0 FIFO Word Count
80189  */
80190 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
80191 
80192 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
80193 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
80194 /*! CB1CNT - Capture B1 FIFO Word Count
80195  */
80196 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
80197 /*! @} */
80198 
80199 /* The count of PWM_CAPTCTRLB */
80200 #define PWM_CAPTCTRLB_COUNT                      (4U)
80201 
80202 /*! @name CAPTCOMPB - Capture Compare B Register */
80203 /*! @{ */
80204 
80205 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
80206 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
80207 /*! EDGCMPB - Edge Compare B
80208  */
80209 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
80210 
80211 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
80212 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
80213 /*! EDGCNTB - Edge Counter B
80214  */
80215 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
80216 /*! @} */
80217 
80218 /* The count of PWM_CAPTCOMPB */
80219 #define PWM_CAPTCOMPB_COUNT                      (4U)
80220 
80221 /*! @name CAPTCTRLX - Capture Control X Register */
80222 /*! @{ */
80223 
80224 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
80225 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
80226 /*! ARMX - Arm X
80227  *  0b0..Input capture operation is disabled.
80228  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
80229  */
80230 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
80231 
80232 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
80233 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
80234 /*! ONESHOTX - One Shot Mode Aux
80235  *  0b0..Free Running
80236  *  0b1..One Shot
80237  */
80238 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
80239 
80240 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
80241 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
80242 /*! EDGX0 - Edge X 0
80243  *  0b00..Disabled
80244  *  0b01..Capture falling edges
80245  *  0b10..Capture rising edges
80246  *  0b11..Capture any edge
80247  */
80248 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
80249 
80250 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
80251 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
80252 /*! EDGX1 - Edge X 1
80253  *  0b00..Disabled
80254  *  0b01..Capture falling edges
80255  *  0b10..Capture rising edges
80256  *  0b11..Capture any edge
80257  */
80258 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
80259 
80260 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
80261 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
80262 /*! INP_SELX - Input Select X
80263  *  0b0..Raw PWM_X input signal selected as source.
80264  *  0b1..Edge Counter
80265  */
80266 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
80267 
80268 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
80269 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
80270 /*! EDGCNTX_EN - Edge Counter X Enable
80271  *  0b0..Edge counter disabled and held in reset
80272  *  0b1..Edge counter enabled
80273  */
80274 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
80275 
80276 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
80277 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
80278 /*! CFXWM - Capture X FIFOs Water Mark
80279  */
80280 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
80281 
80282 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
80283 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
80284 /*! CX0CNT - Capture X0 FIFO Word Count
80285  */
80286 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
80287 
80288 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
80289 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
80290 /*! CX1CNT - Capture X1 FIFO Word Count
80291  */
80292 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
80293 /*! @} */
80294 
80295 /* The count of PWM_CAPTCTRLX */
80296 #define PWM_CAPTCTRLX_COUNT                      (4U)
80297 
80298 /*! @name CAPTCOMPX - Capture Compare X Register */
80299 /*! @{ */
80300 
80301 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
80302 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
80303 /*! EDGCMPX - Edge Compare X
80304  */
80305 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
80306 
80307 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
80308 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
80309 /*! EDGCNTX - Edge Counter X
80310  */
80311 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
80312 /*! @} */
80313 
80314 /* The count of PWM_CAPTCOMPX */
80315 #define PWM_CAPTCOMPX_COUNT                      (4U)
80316 
80317 /*! @name CVAL0 - Capture Value 0 Register */
80318 /*! @{ */
80319 
80320 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
80321 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
80322 /*! CAPTVAL0 - CAPTVAL0
80323  */
80324 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
80325 /*! @} */
80326 
80327 /* The count of PWM_CVAL0 */
80328 #define PWM_CVAL0_COUNT                          (4U)
80329 
80330 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
80331 /*! @{ */
80332 
80333 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
80334 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
80335 /*! CVAL0CYC - CVAL0CYC
80336  */
80337 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
80338 /*! @} */
80339 
80340 /* The count of PWM_CVAL0CYC */
80341 #define PWM_CVAL0CYC_COUNT                       (4U)
80342 
80343 /*! @name CVAL1 - Capture Value 1 Register */
80344 /*! @{ */
80345 
80346 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
80347 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
80348 /*! CAPTVAL1 - CAPTVAL1
80349  */
80350 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
80351 /*! @} */
80352 
80353 /* The count of PWM_CVAL1 */
80354 #define PWM_CVAL1_COUNT                          (4U)
80355 
80356 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
80357 /*! @{ */
80358 
80359 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
80360 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
80361 /*! CVAL1CYC - CVAL1CYC
80362  */
80363 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
80364 /*! @} */
80365 
80366 /* The count of PWM_CVAL1CYC */
80367 #define PWM_CVAL1CYC_COUNT                       (4U)
80368 
80369 /*! @name CVAL2 - Capture Value 2 Register */
80370 /*! @{ */
80371 
80372 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
80373 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
80374 /*! CAPTVAL2 - CAPTVAL2
80375  */
80376 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
80377 /*! @} */
80378 
80379 /* The count of PWM_CVAL2 */
80380 #define PWM_CVAL2_COUNT                          (4U)
80381 
80382 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
80383 /*! @{ */
80384 
80385 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
80386 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
80387 /*! CVAL2CYC - CVAL2CYC
80388  */
80389 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
80390 /*! @} */
80391 
80392 /* The count of PWM_CVAL2CYC */
80393 #define PWM_CVAL2CYC_COUNT                       (4U)
80394 
80395 /*! @name CVAL3 - Capture Value 3 Register */
80396 /*! @{ */
80397 
80398 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
80399 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
80400 /*! CAPTVAL3 - CAPTVAL3
80401  */
80402 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
80403 /*! @} */
80404 
80405 /* The count of PWM_CVAL3 */
80406 #define PWM_CVAL3_COUNT                          (4U)
80407 
80408 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
80409 /*! @{ */
80410 
80411 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
80412 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
80413 /*! CVAL3CYC - CVAL3CYC
80414  */
80415 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
80416 /*! @} */
80417 
80418 /* The count of PWM_CVAL3CYC */
80419 #define PWM_CVAL3CYC_COUNT                       (4U)
80420 
80421 /*! @name CVAL4 - Capture Value 4 Register */
80422 /*! @{ */
80423 
80424 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
80425 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
80426 /*! CAPTVAL4 - CAPTVAL4
80427  */
80428 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
80429 /*! @} */
80430 
80431 /* The count of PWM_CVAL4 */
80432 #define PWM_CVAL4_COUNT                          (4U)
80433 
80434 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
80435 /*! @{ */
80436 
80437 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
80438 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
80439 /*! CVAL4CYC - CVAL4CYC
80440  */
80441 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
80442 /*! @} */
80443 
80444 /* The count of PWM_CVAL4CYC */
80445 #define PWM_CVAL4CYC_COUNT                       (4U)
80446 
80447 /*! @name CVAL5 - Capture Value 5 Register */
80448 /*! @{ */
80449 
80450 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
80451 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
80452 /*! CAPTVAL5 - CAPTVAL5
80453  */
80454 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
80455 /*! @} */
80456 
80457 /* The count of PWM_CVAL5 */
80458 #define PWM_CVAL5_COUNT                          (4U)
80459 
80460 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
80461 /*! @{ */
80462 
80463 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
80464 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
80465 /*! CVAL5CYC - CVAL5CYC
80466  */
80467 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
80468 /*! @} */
80469 
80470 /* The count of PWM_CVAL5CYC */
80471 #define PWM_CVAL5CYC_COUNT                       (4U)
80472 
80473 /*! @name OUTEN - Output Enable Register */
80474 /*! @{ */
80475 
80476 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
80477 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
80478 /*! PWMX_EN - PWM_X Output Enables
80479  *  0b0000..PWM_X output disabled.
80480  *  0b0001..PWM_X output enabled.
80481  */
80482 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
80483 
80484 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
80485 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
80486 /*! PWMB_EN - PWM_B Output Enables
80487  *  0b0000..PWM_B output disabled.
80488  *  0b0001..PWM_B output enabled.
80489  */
80490 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
80491 
80492 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
80493 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
80494 /*! PWMA_EN - PWM_A Output Enables
80495  *  0b0000..PWM_A output disabled.
80496  *  0b0001..PWM_A output enabled.
80497  */
80498 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
80499 /*! @} */
80500 
80501 /*! @name MASK - Mask Register */
80502 /*! @{ */
80503 
80504 #define PWM_MASK_MASKX_MASK                      (0xFU)
80505 #define PWM_MASK_MASKX_SHIFT                     (0U)
80506 /*! MASKX - PWM_X Masks
80507  *  0b0000..PWM_X output normal.
80508  *  0b0001..PWM_X output masked.
80509  */
80510 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
80511 
80512 #define PWM_MASK_MASKB_MASK                      (0xF0U)
80513 #define PWM_MASK_MASKB_SHIFT                     (4U)
80514 /*! MASKB - PWM_B Masks
80515  *  0b0000..PWM_B output normal.
80516  *  0b0001..PWM_B output masked.
80517  */
80518 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
80519 
80520 #define PWM_MASK_MASKA_MASK                      (0xF00U)
80521 #define PWM_MASK_MASKA_SHIFT                     (8U)
80522 /*! MASKA - PWM_A Masks
80523  *  0b0000..PWM_A output normal.
80524  *  0b0001..PWM_A output masked.
80525  */
80526 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
80527 /*! @} */
80528 
80529 /*! @name SWCOUT - Software Controlled Output Register */
80530 /*! @{ */
80531 
80532 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
80533 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
80534 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
80535  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
80536  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
80537  */
80538 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
80539 
80540 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
80541 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
80542 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
80543  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
80544  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
80545  */
80546 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
80547 
80548 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
80549 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
80550 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
80551  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
80552  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
80553  */
80554 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
80555 
80556 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
80557 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
80558 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
80559  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
80560  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
80561  */
80562 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
80563 
80564 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
80565 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
80566 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
80567  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
80568  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
80569  */
80570 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
80571 
80572 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
80573 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
80574 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
80575  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
80576  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
80577  */
80578 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
80579 
80580 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
80581 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
80582 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
80583  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
80584  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
80585  */
80586 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
80587 
80588 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
80589 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
80590 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
80591  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
80592  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
80593  */
80594 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
80595 /*! @} */
80596 
80597 /*! @name DTSRCSEL - PWM Source Select Register */
80598 /*! @{ */
80599 
80600 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
80601 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
80602 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
80603  *  0b00..Generated SM0PWM45 signal is used by the deadtime logic.
80604  *  0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
80605  *  0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
80606  *  0b11..PWM0_EXTB signal is used by the deadtime logic.
80607  */
80608 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
80609 
80610 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
80611 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
80612 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
80613  *  0b00..Generated SM0PWM23 signal is used by the deadtime logic.
80614  *  0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
80615  *  0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
80616  *  0b11..PWM0_EXTA signal is used by the deadtime logic.
80617  */
80618 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
80619 
80620 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
80621 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
80622 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
80623  *  0b00..Generated SM1PWM45 signal is used by the deadtime logic.
80624  *  0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
80625  *  0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
80626  *  0b11..PWM1_EXTB signal is used by the deadtime logic.
80627  */
80628 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
80629 
80630 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
80631 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
80632 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
80633  *  0b00..Generated SM1PWM23 signal is used by the deadtime logic.
80634  *  0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
80635  *  0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
80636  *  0b11..PWM1_EXTA signal is used by the deadtime logic.
80637  */
80638 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
80639 
80640 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
80641 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
80642 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
80643  *  0b00..Generated SM2PWM45 signal is used by the deadtime logic.
80644  *  0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
80645  *  0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
80646  *  0b11..PWM2_EXTB signal is used by the deadtime logic.
80647  */
80648 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
80649 
80650 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
80651 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
80652 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
80653  *  0b00..Generated SM2PWM23 signal is used by the deadtime logic.
80654  *  0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
80655  *  0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
80656  *  0b11..PWM2_EXTA signal is used by the deadtime logic.
80657  */
80658 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
80659 
80660 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
80661 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
80662 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
80663  *  0b00..Generated SM3PWM45 signal is used by the deadtime logic.
80664  *  0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
80665  *  0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
80666  *  0b11..PWM3_EXTB signal is used by the deadtime logic.
80667  */
80668 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
80669 
80670 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
80671 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
80672 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
80673  *  0b00..Generated SM3PWM23 signal is used by the deadtime logic.
80674  *  0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
80675  *  0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
80676  *  0b11..PWM3_EXTA signal is used by the deadtime logic.
80677  */
80678 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
80679 /*! @} */
80680 
80681 /*! @name MCTRL - Master Control Register */
80682 /*! @{ */
80683 
80684 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
80685 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
80686 /*! LDOK - Load Okay
80687  *  0b0000..Do not load new values.
80688  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
80689  */
80690 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
80691 
80692 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
80693 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
80694 /*! CLDOK - Clear Load Okay
80695  */
80696 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
80697 
80698 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
80699 #define PWM_MCTRL_RUN_SHIFT                      (8U)
80700 /*! RUN - Run
80701  *  0b0000..PWM counter is stopped, but PWM outputs will hold the current state.
80702  *  0b0001..PWM counter is started in the corresponding submodule.
80703  */
80704 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
80705 
80706 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
80707 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
80708 /*! IPOL - Current Polarity
80709  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
80710  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
80711  */
80712 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
80713 /*! @} */
80714 
80715 /*! @name MCTRL2 - Master Control 2 Register */
80716 /*! @{ */
80717 
80718 #define PWM_MCTRL2_MONPLL_MASK                   (0x3U)
80719 #define PWM_MCTRL2_MONPLL_SHIFT                  (0U)
80720 /*! MONPLL - Monitor PLL State
80721  *  0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
80722  *  0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
80723  *  0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
80724  *        will be controlled by software. These bits are write protected until the next reset.
80725  *  0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
80726  *        encounters problems. These bits are write protected until the next reset.
80727  */
80728 #define PWM_MCTRL2_MONPLL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
80729 /*! @} */
80730 
80731 /*! @name FCTRL - Fault Control Register */
80732 /*! @{ */
80733 
80734 #define PWM_FCTRL_FIE_MASK                       (0xFU)
80735 #define PWM_FCTRL_FIE_SHIFT                      (0U)
80736 /*! FIE - Fault Interrupt Enables
80737  *  0b0000..FAULTx CPU interrupt requests disabled.
80738  *  0b0001..FAULTx CPU interrupt requests enabled.
80739  */
80740 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
80741 
80742 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
80743 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
80744 /*! FSAFE - Fault Safety Mode
80745  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
80746  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
80747  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be
80748  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
80749  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
80750  *          DISMAPn).
80751  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
80752  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
80753  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
80754  */
80755 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
80756 
80757 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
80758 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
80759 /*! FAUTO - Automatic Fault Clearing
80760  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
80761  *          at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If
80762  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by
80763  *          FCTRL[FSAFE].
80764  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
80765  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
80766  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
80767  *          cannot be cleared.
80768  */
80769 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
80770 
80771 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
80772 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
80773 /*! FLVL - Fault Level
80774  *  0b0000..A logic 0 on the fault input indicates a fault condition.
80775  *  0b0001..A logic 1 on the fault input indicates a fault condition.
80776  */
80777 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
80778 /*! @} */
80779 
80780 /*! @name FSTS - Fault Status Register */
80781 /*! @{ */
80782 
80783 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
80784 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
80785 /*! FFLAG - Fault Flags
80786  *  0b0000..No fault on the FAULTx pin.
80787  *  0b0001..Fault on the FAULTx pin.
80788  */
80789 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
80790 
80791 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
80792 #define PWM_FSTS_FFULL_SHIFT                     (4U)
80793 /*! FFULL - Full Cycle
80794  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
80795  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
80796  */
80797 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
80798 
80799 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
80800 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
80801 /*! FFPIN - Filtered Fault Pins
80802  */
80803 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
80804 
80805 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
80806 #define PWM_FSTS_FHALF_SHIFT                     (12U)
80807 /*! FHALF - Half Cycle Fault Recovery
80808  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
80809  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
80810  */
80811 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
80812 /*! @} */
80813 
80814 /*! @name FFILT - Fault Filter Register */
80815 /*! @{ */
80816 
80817 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
80818 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
80819 /*! FILT_PER - Fault Filter Period
80820  */
80821 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
80822 
80823 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
80824 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
80825 /*! FILT_CNT - Fault Filter Count
80826  */
80827 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
80828 
80829 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
80830 #define PWM_FFILT_GSTR_SHIFT                     (15U)
80831 /*! GSTR - Fault Glitch Stretch Enable
80832  *  0b0..Fault input glitch stretching is disabled.
80833  *  0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
80834  */
80835 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
80836 /*! @} */
80837 
80838 /*! @name FTST - Fault Test Register */
80839 /*! @{ */
80840 
80841 #define PWM_FTST_FTEST_MASK                      (0x1U)
80842 #define PWM_FTST_FTEST_SHIFT                     (0U)
80843 /*! FTEST - Fault Test
80844  *  0b0..No fault
80845  *  0b1..Cause a simulated fault
80846  */
80847 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
80848 /*! @} */
80849 
80850 /*! @name FCTRL2 - Fault Control 2 Register */
80851 /*! @{ */
80852 
80853 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
80854 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
80855 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
80856  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
80857  *          with the filtered and latched fault signals to disable the PWM outputs.
80858  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
80859  *          and latched fault signals are used to disable the PWM outputs.
80860  */
80861 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
80862 /*! @} */
80863 
80864 
80865 /*!
80866  * @}
80867  */ /* end of group PWM_Register_Masks */
80868 
80869 
80870 /* PWM - Peripheral instance base addresses */
80871 /** Peripheral PWM1 base address */
80872 #define PWM1_BASE                                (0x4018C000u)
80873 /** Peripheral PWM1 base pointer */
80874 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
80875 /** Peripheral PWM2 base address */
80876 #define PWM2_BASE                                (0x40190000u)
80877 /** Peripheral PWM2 base pointer */
80878 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
80879 /** Peripheral PWM3 base address */
80880 #define PWM3_BASE                                (0x40194000u)
80881 /** Peripheral PWM3 base pointer */
80882 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
80883 /** Peripheral PWM4 base address */
80884 #define PWM4_BASE                                (0x40198000u)
80885 /** Peripheral PWM4 base pointer */
80886 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
80887 /** Array initializer of PWM peripheral base addresses */
80888 #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
80889 /** Array initializer of PWM peripheral base pointers */
80890 #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
80891 /** Interrupt vectors for the PWM peripheral type */
80892 #define PWM_CMP_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
80893 #define PWM_RELOAD_IRQS                          { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
80894 #define PWM_CAPTURE_IRQS                         { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
80895 #define PWM_FAULT_IRQS                           { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
80896 #define PWM_RELOAD_ERROR_IRQS                    { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
80897 
80898 /*!
80899  * @}
80900  */ /* end of group PWM_Peripheral_Access_Layer */
80901 
80902 
80903 /* ----------------------------------------------------------------------------
80904    -- PXP Peripheral Access Layer
80905    ---------------------------------------------------------------------------- */
80906 
80907 /*!
80908  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
80909  * @{
80910  */
80911 
80912 /** PXP - Register Layout Typedef */
80913 typedef struct {
80914   __IO uint32_t CTRL;                              /**< Control Register 0, offset: 0x0 */
80915   __IO uint32_t CTRL_SET;                          /**< Control Register 0, offset: 0x4 */
80916   __IO uint32_t CTRL_CLR;                          /**< Control Register 0, offset: 0x8 */
80917   __IO uint32_t CTRL_TOG;                          /**< Control Register 0, offset: 0xC */
80918   __IO uint32_t STAT;                              /**< Status Register, offset: 0x10 */
80919   __IO uint32_t STAT_SET;                          /**< Status Register, offset: 0x14 */
80920   __IO uint32_t STAT_CLR;                          /**< Status Register, offset: 0x18 */
80921   __IO uint32_t STAT_TOG;                          /**< Status Register, offset: 0x1C */
80922   __IO uint32_t OUT_CTRL;                          /**< Output Buffer Control Register, offset: 0x20 */
80923   __IO uint32_t OUT_CTRL_SET;                      /**< Output Buffer Control Register, offset: 0x24 */
80924   __IO uint32_t OUT_CTRL_CLR;                      /**< Output Buffer Control Register, offset: 0x28 */
80925   __IO uint32_t OUT_CTRL_TOG;                      /**< Output Buffer Control Register, offset: 0x2C */
80926   __IO uint32_t OUT_BUF;                           /**< Output Frame Buffer Pointer, offset: 0x30 */
80927        uint8_t RESERVED_0[12];
80928   __IO uint32_t OUT_BUF2;                          /**< Output Frame Buffer Pointer #2, offset: 0x40 */
80929        uint8_t RESERVED_1[12];
80930   __IO uint32_t OUT_PITCH;                         /**< Output Buffer Pitch, offset: 0x50 */
80931        uint8_t RESERVED_2[12];
80932   __IO uint32_t OUT_LRC;                           /**< Output Surface Lower Right Coordinate, offset: 0x60 */
80933        uint8_t RESERVED_3[12];
80934   __IO uint32_t OUT_PS_ULC;                        /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
80935        uint8_t RESERVED_4[12];
80936   __IO uint32_t OUT_PS_LRC;                        /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
80937        uint8_t RESERVED_5[12];
80938   __IO uint32_t OUT_AS_ULC;                        /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
80939        uint8_t RESERVED_6[12];
80940   __IO uint32_t OUT_AS_LRC;                        /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
80941        uint8_t RESERVED_7[12];
80942   __IO uint32_t PS_CTRL;                           /**< Processed Surface (PS) Control Register, offset: 0xB0 */
80943   __IO uint32_t PS_CTRL_SET;                       /**< Processed Surface (PS) Control Register, offset: 0xB4 */
80944   __IO uint32_t PS_CTRL_CLR;                       /**< Processed Surface (PS) Control Register, offset: 0xB8 */
80945   __IO uint32_t PS_CTRL_TOG;                       /**< Processed Surface (PS) Control Register, offset: 0xBC */
80946   __IO uint32_t PS_BUF;                            /**< PS Input Buffer Address, offset: 0xC0 */
80947        uint8_t RESERVED_8[12];
80948   __IO uint32_t PS_UBUF;                           /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
80949        uint8_t RESERVED_9[12];
80950   __IO uint32_t PS_VBUF;                           /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
80951        uint8_t RESERVED_10[12];
80952   __IO uint32_t PS_PITCH;                          /**< Processed Surface Pitch, offset: 0xF0 */
80953        uint8_t RESERVED_11[12];
80954   __IO uint32_t PS_BACKGROUND;                     /**< PS Background Color, offset: 0x100 */
80955        uint8_t RESERVED_12[12];
80956   __IO uint32_t PS_SCALE;                          /**< PS Scale Factor Register, offset: 0x110 */
80957        uint8_t RESERVED_13[12];
80958   __IO uint32_t PS_OFFSET;                         /**< PS Scale Offset Register, offset: 0x120 */
80959        uint8_t RESERVED_14[12];
80960   __IO uint32_t PS_CLRKEYLOW;                      /**< PS Color Key Low, offset: 0x130 */
80961        uint8_t RESERVED_15[12];
80962   __IO uint32_t PS_CLRKEYHIGH;                     /**< PS Color Key High, offset: 0x140 */
80963        uint8_t RESERVED_16[12];
80964   __IO uint32_t AS_CTRL;                           /**< Alpha Surface Control, offset: 0x150 */
80965        uint8_t RESERVED_17[12];
80966   __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x160 */
80967        uint8_t RESERVED_18[12];
80968   __IO uint32_t AS_PITCH;                          /**< Alpha Surface Pitch, offset: 0x170 */
80969        uint8_t RESERVED_19[12];
80970   __IO uint32_t AS_CLRKEYLOW;                      /**< Overlay Color Key Low, offset: 0x180 */
80971        uint8_t RESERVED_20[12];
80972   __IO uint32_t AS_CLRKEYHIGH;                     /**< Overlay Color Key High, offset: 0x190 */
80973        uint8_t RESERVED_21[12];
80974   __IO uint32_t CSC1_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
80975        uint8_t RESERVED_22[12];
80976   __IO uint32_t CSC1_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
80977        uint8_t RESERVED_23[12];
80978   __IO uint32_t CSC1_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
80979        uint8_t RESERVED_24[348];
80980   __IO uint32_t POWER;                             /**< PXP Power Control Register, offset: 0x320 */
80981        uint8_t RESERVED_25[220];
80982   __IO uint32_t NEXT;                              /**< Next Frame Pointer, offset: 0x400 */
80983        uint8_t RESERVED_26[60];
80984   __IO uint32_t PORTER_DUFF_CTRL;                  /**< PXP Alpha Engine A Control Register., offset: 0x440 */
80985 } PXP_Type;
80986 
80987 /* ----------------------------------------------------------------------------
80988    -- PXP Register Masks
80989    ---------------------------------------------------------------------------- */
80990 
80991 /*!
80992  * @addtogroup PXP_Register_Masks PXP Register Masks
80993  * @{
80994  */
80995 
80996 /*! @name CTRL - Control Register 0 */
80997 /*! @{ */
80998 
80999 #define PXP_CTRL_ENABLE_MASK                     (0x1U)
81000 #define PXP_CTRL_ENABLE_SHIFT                    (0U)
81001 /*! ENABLE
81002  *  0b1..PXP is enabled
81003  *  0b0..PXP is disabled
81004  */
81005 #define PXP_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
81006 
81007 #define PXP_CTRL_IRQ_ENABLE_MASK                 (0x2U)
81008 #define PXP_CTRL_IRQ_ENABLE_SHIFT                (1U)
81009 /*! IRQ_ENABLE
81010  *  0b1..PXP interrupt is enabled
81011  *  0b0..PXP interrupt is disabled
81012  */
81013 #define PXP_CTRL_IRQ_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
81014 
81015 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            (0x4U)
81016 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           (2U)
81017 /*! NEXT_IRQ_ENABLE
81018  *  0b0..Disabled
81019  *  0b1..Enabled
81020  */
81021 #define PXP_CTRL_NEXT_IRQ_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
81022 
81023 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK       (0x10U)
81024 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT      (4U)
81025 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
81026 
81027 #define PXP_CTRL_ROTATE_MASK                     (0x300U)
81028 #define PXP_CTRL_ROTATE_SHIFT                    (8U)
81029 /*! ROTATE
81030  *  0b00..ROT_0
81031  *  0b01..ROT_90
81032  *  0b10..ROT_180
81033  *  0b11..ROT_270
81034  */
81035 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
81036 
81037 #define PXP_CTRL_HFLIP_MASK                      (0x400U)
81038 #define PXP_CTRL_HFLIP_SHIFT                     (10U)
81039 /*! HFLIP
81040  *  0b0..Horizontal Flip is disabled
81041  *  0b1..Horizontal Flip is enabled
81042  */
81043 #define PXP_CTRL_HFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
81044 
81045 #define PXP_CTRL_VFLIP_MASK                      (0x800U)
81046 #define PXP_CTRL_VFLIP_SHIFT                     (11U)
81047 /*! VFLIP
81048  *  0b0..Vertical Flip is disabled
81049  *  0b1..Vertical Flip is enabled
81050  */
81051 #define PXP_CTRL_VFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
81052 
81053 #define PXP_CTRL_ROT_POS_MASK                    (0x400000U)
81054 #define PXP_CTRL_ROT_POS_SHIFT                   (22U)
81055 #define PXP_CTRL_ROT_POS(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
81056 
81057 #define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
81058 #define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
81059 /*! BLOCK_SIZE
81060  *  0b0..Process 8x8 pixel blocks.
81061  *  0b1..Process 16x16 pixel blocks.
81062  */
81063 #define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
81064 
81065 #define PXP_CTRL_EN_REPEAT_MASK                  (0x10000000U)
81066 #define PXP_CTRL_EN_REPEAT_SHIFT                 (28U)
81067 /*! EN_REPEAT
81068  *  0b1..PXP will repeat based on the current configuration register settings
81069  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81070  */
81071 #define PXP_CTRL_EN_REPEAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
81072 
81073 #define PXP_CTRL_CLKGATE_MASK                    (0x40000000U)
81074 #define PXP_CTRL_CLKGATE_SHIFT                   (30U)
81075 /*! CLKGATE
81076  *  0b0..Normal operation
81077  *  0b1..All clocks to PXP is gated-off
81078  */
81079 #define PXP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
81080 
81081 #define PXP_CTRL_SFTRST_MASK                     (0x80000000U)
81082 #define PXP_CTRL_SFTRST_SHIFT                    (31U)
81083 /*! SFTRST
81084  *  0b0..Normal PXP operation is enabled
81085  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81086  */
81087 #define PXP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
81088 /*! @} */
81089 
81090 /*! @name CTRL_SET - Control Register 0 */
81091 /*! @{ */
81092 
81093 #define PXP_CTRL_SET_ENABLE_MASK                 (0x1U)
81094 #define PXP_CTRL_SET_ENABLE_SHIFT                (0U)
81095 /*! ENABLE
81096  *  0b1..PXP is enabled
81097  *  0b0..PXP is disabled
81098  */
81099 #define PXP_CTRL_SET_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
81100 
81101 #define PXP_CTRL_SET_IRQ_ENABLE_MASK             (0x2U)
81102 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT            (1U)
81103 /*! IRQ_ENABLE
81104  *  0b1..PXP interrupt is enabled
81105  *  0b0..PXP interrupt is disabled
81106  */
81107 #define PXP_CTRL_SET_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
81108 
81109 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK        (0x4U)
81110 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT       (2U)
81111 /*! NEXT_IRQ_ENABLE
81112  *  0b0..Disabled
81113  *  0b1..Enabled
81114  */
81115 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
81116 
81117 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81118 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81119 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
81120 
81121 #define PXP_CTRL_SET_ROTATE_MASK                 (0x300U)
81122 #define PXP_CTRL_SET_ROTATE_SHIFT                (8U)
81123 /*! ROTATE
81124  *  0b00..ROT_0
81125  *  0b01..ROT_90
81126  *  0b10..ROT_180
81127  *  0b11..ROT_270
81128  */
81129 #define PXP_CTRL_SET_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
81130 
81131 #define PXP_CTRL_SET_HFLIP_MASK                  (0x400U)
81132 #define PXP_CTRL_SET_HFLIP_SHIFT                 (10U)
81133 /*! HFLIP
81134  *  0b0..Horizontal Flip is disabled
81135  *  0b1..Horizontal Flip is enabled
81136  */
81137 #define PXP_CTRL_SET_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
81138 
81139 #define PXP_CTRL_SET_VFLIP_MASK                  (0x800U)
81140 #define PXP_CTRL_SET_VFLIP_SHIFT                 (11U)
81141 /*! VFLIP
81142  *  0b0..Vertical Flip is disabled
81143  *  0b1..Vertical Flip is enabled
81144  */
81145 #define PXP_CTRL_SET_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
81146 
81147 #define PXP_CTRL_SET_ROT_POS_MASK                (0x400000U)
81148 #define PXP_CTRL_SET_ROT_POS_SHIFT               (22U)
81149 #define PXP_CTRL_SET_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
81150 
81151 #define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
81152 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
81153 /*! BLOCK_SIZE
81154  *  0b0..Process 8x8 pixel blocks.
81155  *  0b1..Process 16x16 pixel blocks.
81156  */
81157 #define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
81158 
81159 #define PXP_CTRL_SET_EN_REPEAT_MASK              (0x10000000U)
81160 #define PXP_CTRL_SET_EN_REPEAT_SHIFT             (28U)
81161 /*! EN_REPEAT
81162  *  0b1..PXP will repeat based on the current configuration register settings
81163  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81164  */
81165 #define PXP_CTRL_SET_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
81166 
81167 #define PXP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
81168 #define PXP_CTRL_SET_CLKGATE_SHIFT               (30U)
81169 /*! CLKGATE
81170  *  0b0..Normal operation
81171  *  0b1..All clocks to PXP is gated-off
81172  */
81173 #define PXP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
81174 
81175 #define PXP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
81176 #define PXP_CTRL_SET_SFTRST_SHIFT                (31U)
81177 /*! SFTRST
81178  *  0b0..Normal PXP operation is enabled
81179  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81180  */
81181 #define PXP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
81182 /*! @} */
81183 
81184 /*! @name CTRL_CLR - Control Register 0 */
81185 /*! @{ */
81186 
81187 #define PXP_CTRL_CLR_ENABLE_MASK                 (0x1U)
81188 #define PXP_CTRL_CLR_ENABLE_SHIFT                (0U)
81189 /*! ENABLE
81190  *  0b1..PXP is enabled
81191  *  0b0..PXP is disabled
81192  */
81193 #define PXP_CTRL_CLR_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
81194 
81195 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK             (0x2U)
81196 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT            (1U)
81197 /*! IRQ_ENABLE
81198  *  0b1..PXP interrupt is enabled
81199  *  0b0..PXP interrupt is disabled
81200  */
81201 #define PXP_CTRL_CLR_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
81202 
81203 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK        (0x4U)
81204 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT       (2U)
81205 /*! NEXT_IRQ_ENABLE
81206  *  0b0..Disabled
81207  *  0b1..Enabled
81208  */
81209 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
81210 
81211 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81212 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81213 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
81214 
81215 #define PXP_CTRL_CLR_ROTATE_MASK                 (0x300U)
81216 #define PXP_CTRL_CLR_ROTATE_SHIFT                (8U)
81217 /*! ROTATE
81218  *  0b00..ROT_0
81219  *  0b01..ROT_90
81220  *  0b10..ROT_180
81221  *  0b11..ROT_270
81222  */
81223 #define PXP_CTRL_CLR_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
81224 
81225 #define PXP_CTRL_CLR_HFLIP_MASK                  (0x400U)
81226 #define PXP_CTRL_CLR_HFLIP_SHIFT                 (10U)
81227 /*! HFLIP
81228  *  0b0..Horizontal Flip is disabled
81229  *  0b1..Horizontal Flip is enabled
81230  */
81231 #define PXP_CTRL_CLR_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
81232 
81233 #define PXP_CTRL_CLR_VFLIP_MASK                  (0x800U)
81234 #define PXP_CTRL_CLR_VFLIP_SHIFT                 (11U)
81235 /*! VFLIP
81236  *  0b0..Vertical Flip is disabled
81237  *  0b1..Vertical Flip is enabled
81238  */
81239 #define PXP_CTRL_CLR_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
81240 
81241 #define PXP_CTRL_CLR_ROT_POS_MASK                (0x400000U)
81242 #define PXP_CTRL_CLR_ROT_POS_SHIFT               (22U)
81243 #define PXP_CTRL_CLR_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
81244 
81245 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
81246 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
81247 /*! BLOCK_SIZE
81248  *  0b0..Process 8x8 pixel blocks.
81249  *  0b1..Process 16x16 pixel blocks.
81250  */
81251 #define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
81252 
81253 #define PXP_CTRL_CLR_EN_REPEAT_MASK              (0x10000000U)
81254 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT             (28U)
81255 /*! EN_REPEAT
81256  *  0b1..PXP will repeat based on the current configuration register settings
81257  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81258  */
81259 #define PXP_CTRL_CLR_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
81260 
81261 #define PXP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
81262 #define PXP_CTRL_CLR_CLKGATE_SHIFT               (30U)
81263 /*! CLKGATE
81264  *  0b0..Normal operation
81265  *  0b1..All clocks to PXP is gated-off
81266  */
81267 #define PXP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
81268 
81269 #define PXP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
81270 #define PXP_CTRL_CLR_SFTRST_SHIFT                (31U)
81271 /*! SFTRST
81272  *  0b0..Normal PXP operation is enabled
81273  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81274  */
81275 #define PXP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
81276 /*! @} */
81277 
81278 /*! @name CTRL_TOG - Control Register 0 */
81279 /*! @{ */
81280 
81281 #define PXP_CTRL_TOG_ENABLE_MASK                 (0x1U)
81282 #define PXP_CTRL_TOG_ENABLE_SHIFT                (0U)
81283 /*! ENABLE
81284  *  0b1..PXP is enabled
81285  *  0b0..PXP is disabled
81286  */
81287 #define PXP_CTRL_TOG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
81288 
81289 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK             (0x2U)
81290 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT            (1U)
81291 /*! IRQ_ENABLE
81292  *  0b1..PXP interrupt is enabled
81293  *  0b0..PXP interrupt is disabled
81294  */
81295 #define PXP_CTRL_TOG_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
81296 
81297 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK        (0x4U)
81298 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT       (2U)
81299 /*! NEXT_IRQ_ENABLE
81300  *  0b0..Disabled
81301  *  0b1..Enabled
81302  */
81303 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
81304 
81305 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
81306 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
81307 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
81308 
81309 #define PXP_CTRL_TOG_ROTATE_MASK                 (0x300U)
81310 #define PXP_CTRL_TOG_ROTATE_SHIFT                (8U)
81311 /*! ROTATE
81312  *  0b00..ROT_0
81313  *  0b01..ROT_90
81314  *  0b10..ROT_180
81315  *  0b11..ROT_270
81316  */
81317 #define PXP_CTRL_TOG_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
81318 
81319 #define PXP_CTRL_TOG_HFLIP_MASK                  (0x400U)
81320 #define PXP_CTRL_TOG_HFLIP_SHIFT                 (10U)
81321 /*! HFLIP
81322  *  0b0..Horizontal Flip is disabled
81323  *  0b1..Horizontal Flip is enabled
81324  */
81325 #define PXP_CTRL_TOG_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
81326 
81327 #define PXP_CTRL_TOG_VFLIP_MASK                  (0x800U)
81328 #define PXP_CTRL_TOG_VFLIP_SHIFT                 (11U)
81329 /*! VFLIP
81330  *  0b0..Vertical Flip is disabled
81331  *  0b1..Vertical Flip is enabled
81332  */
81333 #define PXP_CTRL_TOG_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
81334 
81335 #define PXP_CTRL_TOG_ROT_POS_MASK                (0x400000U)
81336 #define PXP_CTRL_TOG_ROT_POS_SHIFT               (22U)
81337 #define PXP_CTRL_TOG_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
81338 
81339 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
81340 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
81341 /*! BLOCK_SIZE
81342  *  0b0..Process 8x8 pixel blocks.
81343  *  0b1..Process 16x16 pixel blocks.
81344  */
81345 #define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
81346 
81347 #define PXP_CTRL_TOG_EN_REPEAT_MASK              (0x10000000U)
81348 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT             (28U)
81349 /*! EN_REPEAT
81350  *  0b1..PXP will repeat based on the current configuration register settings
81351  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
81352  */
81353 #define PXP_CTRL_TOG_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
81354 
81355 #define PXP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
81356 #define PXP_CTRL_TOG_CLKGATE_SHIFT               (30U)
81357 /*! CLKGATE
81358  *  0b0..Normal operation
81359  *  0b1..All clocks to PXP is gated-off
81360  */
81361 #define PXP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
81362 
81363 #define PXP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
81364 #define PXP_CTRL_TOG_SFTRST_SHIFT                (31U)
81365 /*! SFTRST
81366  *  0b0..Normal PXP operation is enabled
81367  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
81368  */
81369 #define PXP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
81370 /*! @} */
81371 
81372 /*! @name STAT - Status Register */
81373 /*! @{ */
81374 
81375 #define PXP_STAT_IRQ_MASK                        (0x1U)
81376 #define PXP_STAT_IRQ_SHIFT                       (0U)
81377 /*! IRQ
81378  *  0b0..No interrupt
81379  *  0b1..Interrupt generated
81380  */
81381 #define PXP_STAT_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
81382 
81383 #define PXP_STAT_AXI_WRITE_ERROR_MASK            (0x2U)
81384 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT           (1U)
81385 /*! AXI_WRITE_ERROR
81386  *  0b0..AXI write is normal
81387  *  0b1..AXI write error has occurred
81388  */
81389 #define PXP_STAT_AXI_WRITE_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
81390 
81391 #define PXP_STAT_AXI_READ_ERROR_MASK             (0x4U)
81392 #define PXP_STAT_AXI_READ_ERROR_SHIFT            (2U)
81393 /*! AXI_READ_ERROR
81394  *  0b0..AXI read is normal
81395  *  0b1..AXI read error has occurred
81396  */
81397 #define PXP_STAT_AXI_READ_ERROR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
81398 
81399 #define PXP_STAT_NEXT_IRQ_MASK                   (0x8U)
81400 #define PXP_STAT_NEXT_IRQ_SHIFT                  (3U)
81401 #define PXP_STAT_NEXT_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
81402 
81403 #define PXP_STAT_AXI_ERROR_ID_MASK               (0xF0U)
81404 #define PXP_STAT_AXI_ERROR_ID_SHIFT              (4U)
81405 #define PXP_STAT_AXI_ERROR_ID(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
81406 
81407 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      (0x100U)
81408 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     (8U)
81409 /*! LUT_DMA_LOAD_DONE_IRQ
81410  *  0b0..LUT DMA LOAD transfer is active
81411  *  0b1..LUT DMA LOAD transfer is complete
81412  */
81413 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
81414 
81415 #define PXP_STAT_BLOCKY_MASK                     (0xFF0000U)
81416 #define PXP_STAT_BLOCKY_SHIFT                    (16U)
81417 #define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
81418 
81419 #define PXP_STAT_BLOCKX_MASK                     (0xFF000000U)
81420 #define PXP_STAT_BLOCKX_SHIFT                    (24U)
81421 #define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
81422 /*! @} */
81423 
81424 /*! @name STAT_SET - Status Register */
81425 /*! @{ */
81426 
81427 #define PXP_STAT_SET_IRQ_MASK                    (0x1U)
81428 #define PXP_STAT_SET_IRQ_SHIFT                   (0U)
81429 /*! IRQ
81430  *  0b0..No interrupt
81431  *  0b1..Interrupt generated
81432  */
81433 #define PXP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
81434 
81435 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK        (0x2U)
81436 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT       (1U)
81437 /*! AXI_WRITE_ERROR
81438  *  0b0..AXI write is normal
81439  *  0b1..AXI write error has occurred
81440  */
81441 #define PXP_STAT_SET_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
81442 
81443 #define PXP_STAT_SET_AXI_READ_ERROR_MASK         (0x4U)
81444 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT        (2U)
81445 /*! AXI_READ_ERROR
81446  *  0b0..AXI read is normal
81447  *  0b1..AXI read error has occurred
81448  */
81449 #define PXP_STAT_SET_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
81450 
81451 #define PXP_STAT_SET_NEXT_IRQ_MASK               (0x8U)
81452 #define PXP_STAT_SET_NEXT_IRQ_SHIFT              (3U)
81453 #define PXP_STAT_SET_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
81454 
81455 #define PXP_STAT_SET_AXI_ERROR_ID_MASK           (0xF0U)
81456 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT          (4U)
81457 #define PXP_STAT_SET_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
81458 
81459 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81460 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81461 /*! LUT_DMA_LOAD_DONE_IRQ
81462  *  0b0..LUT DMA LOAD transfer is active
81463  *  0b1..LUT DMA LOAD transfer is complete
81464  */
81465 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
81466 
81467 #define PXP_STAT_SET_BLOCKY_MASK                 (0xFF0000U)
81468 #define PXP_STAT_SET_BLOCKY_SHIFT                (16U)
81469 #define PXP_STAT_SET_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
81470 
81471 #define PXP_STAT_SET_BLOCKX_MASK                 (0xFF000000U)
81472 #define PXP_STAT_SET_BLOCKX_SHIFT                (24U)
81473 #define PXP_STAT_SET_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
81474 /*! @} */
81475 
81476 /*! @name STAT_CLR - Status Register */
81477 /*! @{ */
81478 
81479 #define PXP_STAT_CLR_IRQ_MASK                    (0x1U)
81480 #define PXP_STAT_CLR_IRQ_SHIFT                   (0U)
81481 /*! IRQ
81482  *  0b0..No interrupt
81483  *  0b1..Interrupt generated
81484  */
81485 #define PXP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
81486 
81487 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK        (0x2U)
81488 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT       (1U)
81489 /*! AXI_WRITE_ERROR
81490  *  0b0..AXI write is normal
81491  *  0b1..AXI write error has occurred
81492  */
81493 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
81494 
81495 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK         (0x4U)
81496 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT        (2U)
81497 /*! AXI_READ_ERROR
81498  *  0b0..AXI read is normal
81499  *  0b1..AXI read error has occurred
81500  */
81501 #define PXP_STAT_CLR_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
81502 
81503 #define PXP_STAT_CLR_NEXT_IRQ_MASK               (0x8U)
81504 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT              (3U)
81505 #define PXP_STAT_CLR_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
81506 
81507 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK           (0xF0U)
81508 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT          (4U)
81509 #define PXP_STAT_CLR_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
81510 
81511 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81512 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81513 /*! LUT_DMA_LOAD_DONE_IRQ
81514  *  0b0..LUT DMA LOAD transfer is active
81515  *  0b1..LUT DMA LOAD transfer is complete
81516  */
81517 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
81518 
81519 #define PXP_STAT_CLR_BLOCKY_MASK                 (0xFF0000U)
81520 #define PXP_STAT_CLR_BLOCKY_SHIFT                (16U)
81521 #define PXP_STAT_CLR_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
81522 
81523 #define PXP_STAT_CLR_BLOCKX_MASK                 (0xFF000000U)
81524 #define PXP_STAT_CLR_BLOCKX_SHIFT                (24U)
81525 #define PXP_STAT_CLR_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
81526 /*! @} */
81527 
81528 /*! @name STAT_TOG - Status Register */
81529 /*! @{ */
81530 
81531 #define PXP_STAT_TOG_IRQ_MASK                    (0x1U)
81532 #define PXP_STAT_TOG_IRQ_SHIFT                   (0U)
81533 /*! IRQ
81534  *  0b0..No interrupt
81535  *  0b1..Interrupt generated
81536  */
81537 #define PXP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
81538 
81539 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK        (0x2U)
81540 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT       (1U)
81541 /*! AXI_WRITE_ERROR
81542  *  0b0..AXI write is normal
81543  *  0b1..AXI write error has occurred
81544  */
81545 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
81546 
81547 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK         (0x4U)
81548 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT        (2U)
81549 /*! AXI_READ_ERROR
81550  *  0b0..AXI read is normal
81551  *  0b1..AXI read error has occurred
81552  */
81553 #define PXP_STAT_TOG_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
81554 
81555 #define PXP_STAT_TOG_NEXT_IRQ_MASK               (0x8U)
81556 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT              (3U)
81557 #define PXP_STAT_TOG_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
81558 
81559 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK           (0xF0U)
81560 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT          (4U)
81561 #define PXP_STAT_TOG_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
81562 
81563 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
81564 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
81565 /*! LUT_DMA_LOAD_DONE_IRQ
81566  *  0b0..LUT DMA LOAD transfer is active
81567  *  0b1..LUT DMA LOAD transfer is complete
81568  */
81569 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
81570 
81571 #define PXP_STAT_TOG_BLOCKY_MASK                 (0xFF0000U)
81572 #define PXP_STAT_TOG_BLOCKY_SHIFT                (16U)
81573 #define PXP_STAT_TOG_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
81574 
81575 #define PXP_STAT_TOG_BLOCKX_MASK                 (0xFF000000U)
81576 #define PXP_STAT_TOG_BLOCKX_SHIFT                (24U)
81577 #define PXP_STAT_TOG_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
81578 /*! @} */
81579 
81580 /*! @name OUT_CTRL - Output Buffer Control Register */
81581 /*! @{ */
81582 
81583 #define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
81584 #define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
81585 /*! FORMAT
81586  *  0b00000..32-bit pixels
81587  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81588  *  0b00101..24-bit pixels (packed 24-bit format)
81589  *  0b01000..16-bit pixels
81590  *  0b01001..16-bit pixels
81591  *  0b01100..16-bit pixels
81592  *  0b01101..16-bit pixels
81593  *  0b01110..16-bit pixels
81594  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81595  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81596  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81597  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81598  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81599  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81600  *  0b11001..16-bit pixels (2-plane UV)
81601  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81602  *  0b11011..16-bit pixels (2-plane VU)
81603  */
81604 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
81605 
81606 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
81607 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
81608 /*! INTERLACED_OUTPUT
81609  *  0b00..All data written in progressive format to the OUTBUF Pointer.
81610  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
81611  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
81612  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
81613  */
81614 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
81615 
81616 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           (0x800000U)
81617 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          (23U)
81618 /*! ALPHA_OUTPUT
81619  *  0b0..Retain
81620  *  0b1..Overwritten
81621  */
81622 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
81623 
81624 #define PXP_OUT_CTRL_ALPHA_MASK                  (0xFF000000U)
81625 #define PXP_OUT_CTRL_ALPHA_SHIFT                 (24U)
81626 #define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
81627 /*! @} */
81628 
81629 /*! @name OUT_CTRL_SET - Output Buffer Control Register */
81630 /*! @{ */
81631 
81632 #define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
81633 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
81634 /*! FORMAT
81635  *  0b00000..32-bit pixels
81636  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81637  *  0b00101..24-bit pixels (packed 24-bit format)
81638  *  0b01000..16-bit pixels
81639  *  0b01001..16-bit pixels
81640  *  0b01100..16-bit pixels
81641  *  0b01101..16-bit pixels
81642  *  0b01110..16-bit pixels
81643  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81644  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81645  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81646  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81647  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81648  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81649  *  0b11001..16-bit pixels (2-plane UV)
81650  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81651  *  0b11011..16-bit pixels (2-plane VU)
81652  */
81653 #define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
81654 
81655 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
81656 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
81657 /*! INTERLACED_OUTPUT
81658  *  0b00..All data written in progressive format to the OUTBUF Pointer.
81659  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
81660  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
81661  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
81662  */
81663 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
81664 
81665 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK       (0x800000U)
81666 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT      (23U)
81667 /*! ALPHA_OUTPUT
81668  *  0b0..Retain
81669  *  0b1..Overwritten
81670  */
81671 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
81672 
81673 #define PXP_OUT_CTRL_SET_ALPHA_MASK              (0xFF000000U)
81674 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT             (24U)
81675 #define PXP_OUT_CTRL_SET_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
81676 /*! @} */
81677 
81678 /*! @name OUT_CTRL_CLR - Output Buffer Control Register */
81679 /*! @{ */
81680 
81681 #define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
81682 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
81683 /*! FORMAT
81684  *  0b00000..32-bit pixels
81685  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81686  *  0b00101..24-bit pixels (packed 24-bit format)
81687  *  0b01000..16-bit pixels
81688  *  0b01001..16-bit pixels
81689  *  0b01100..16-bit pixels
81690  *  0b01101..16-bit pixels
81691  *  0b01110..16-bit pixels
81692  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81693  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81694  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81695  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81696  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81697  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81698  *  0b11001..16-bit pixels (2-plane UV)
81699  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81700  *  0b11011..16-bit pixels (2-plane VU)
81701  */
81702 #define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
81703 
81704 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
81705 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
81706 /*! INTERLACED_OUTPUT
81707  *  0b00..All data written in progressive format to the OUTBUF Pointer.
81708  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
81709  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
81710  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
81711  */
81712 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
81713 
81714 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK       (0x800000U)
81715 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT      (23U)
81716 /*! ALPHA_OUTPUT
81717  *  0b0..Retain
81718  *  0b1..Overwritten
81719  */
81720 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
81721 
81722 #define PXP_OUT_CTRL_CLR_ALPHA_MASK              (0xFF000000U)
81723 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT             (24U)
81724 #define PXP_OUT_CTRL_CLR_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
81725 /*! @} */
81726 
81727 /*! @name OUT_CTRL_TOG - Output Buffer Control Register */
81728 /*! @{ */
81729 
81730 #define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
81731 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
81732 /*! FORMAT
81733  *  0b00000..32-bit pixels
81734  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
81735  *  0b00101..24-bit pixels (packed 24-bit format)
81736  *  0b01000..16-bit pixels
81737  *  0b01001..16-bit pixels
81738  *  0b01100..16-bit pixels
81739  *  0b01101..16-bit pixels
81740  *  0b01110..16-bit pixels
81741  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
81742  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81743  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81744  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
81745  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81746  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
81747  *  0b11001..16-bit pixels (2-plane UV)
81748  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
81749  *  0b11011..16-bit pixels (2-plane VU)
81750  */
81751 #define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
81752 
81753 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
81754 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
81755 /*! INTERLACED_OUTPUT
81756  *  0b00..All data written in progressive format to the OUTBUF Pointer.
81757  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
81758  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
81759  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
81760  */
81761 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
81762 
81763 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK       (0x800000U)
81764 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT      (23U)
81765 /*! ALPHA_OUTPUT
81766  *  0b0..Retain
81767  *  0b1..Overwritten
81768  */
81769 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
81770 
81771 #define PXP_OUT_CTRL_TOG_ALPHA_MASK              (0xFF000000U)
81772 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT             (24U)
81773 #define PXP_OUT_CTRL_TOG_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
81774 /*! @} */
81775 
81776 /*! @name OUT_BUF - Output Frame Buffer Pointer */
81777 /*! @{ */
81778 
81779 #define PXP_OUT_BUF_ADDR_MASK                    (0xFFFFFFFFU)
81780 #define PXP_OUT_BUF_ADDR_SHIFT                   (0U)
81781 #define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
81782 /*! @} */
81783 
81784 /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
81785 /*! @{ */
81786 
81787 #define PXP_OUT_BUF2_ADDR_MASK                   (0xFFFFFFFFU)
81788 #define PXP_OUT_BUF2_ADDR_SHIFT                  (0U)
81789 #define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
81790 /*! @} */
81791 
81792 /*! @name OUT_PITCH - Output Buffer Pitch */
81793 /*! @{ */
81794 
81795 #define PXP_OUT_PITCH_PITCH_MASK                 (0xFFFFU)
81796 #define PXP_OUT_PITCH_PITCH_SHIFT                (0U)
81797 #define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
81798 /*! @} */
81799 
81800 /*! @name OUT_LRC - Output Surface Lower Right Coordinate */
81801 /*! @{ */
81802 
81803 #define PXP_OUT_LRC_Y_MASK                       (0x3FFFU)
81804 #define PXP_OUT_LRC_Y_SHIFT                      (0U)
81805 #define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
81806 
81807 #define PXP_OUT_LRC_X_MASK                       (0x3FFF0000U)
81808 #define PXP_OUT_LRC_X_SHIFT                      (16U)
81809 #define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
81810 /*! @} */
81811 
81812 /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
81813 /*! @{ */
81814 
81815 #define PXP_OUT_PS_ULC_Y_MASK                    (0x3FFFU)
81816 #define PXP_OUT_PS_ULC_Y_SHIFT                   (0U)
81817 #define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
81818 
81819 #define PXP_OUT_PS_ULC_X_MASK                    (0x3FFF0000U)
81820 #define PXP_OUT_PS_ULC_X_SHIFT                   (16U)
81821 #define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
81822 /*! @} */
81823 
81824 /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
81825 /*! @{ */
81826 
81827 #define PXP_OUT_PS_LRC_Y_MASK                    (0x3FFFU)
81828 #define PXP_OUT_PS_LRC_Y_SHIFT                   (0U)
81829 #define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
81830 
81831 #define PXP_OUT_PS_LRC_X_MASK                    (0x3FFF0000U)
81832 #define PXP_OUT_PS_LRC_X_SHIFT                   (16U)
81833 #define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
81834 /*! @} */
81835 
81836 /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
81837 /*! @{ */
81838 
81839 #define PXP_OUT_AS_ULC_Y_MASK                    (0x3FFFU)
81840 #define PXP_OUT_AS_ULC_Y_SHIFT                   (0U)
81841 #define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
81842 
81843 #define PXP_OUT_AS_ULC_X_MASK                    (0x3FFF0000U)
81844 #define PXP_OUT_AS_ULC_X_SHIFT                   (16U)
81845 #define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
81846 /*! @} */
81847 
81848 /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
81849 /*! @{ */
81850 
81851 #define PXP_OUT_AS_LRC_Y_MASK                    (0x3FFFU)
81852 #define PXP_OUT_AS_LRC_Y_SHIFT                   (0U)
81853 #define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
81854 
81855 #define PXP_OUT_AS_LRC_X_MASK                    (0x3FFF0000U)
81856 #define PXP_OUT_AS_LRC_X_SHIFT                   (16U)
81857 #define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
81858 /*! @} */
81859 
81860 /*! @name PS_CTRL - Processed Surface (PS) Control Register */
81861 /*! @{ */
81862 
81863 #define PXP_PS_CTRL_FORMAT_MASK                  (0x3FU)
81864 #define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
81865 /*! FORMAT
81866  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
81867  *  0b001100..16-bit pixels with/without alpha at high 1bit
81868  *  0b001101..16-bit pixels with/without alpha at high 4 bits
81869  *  0b001110..16-bit pixels
81870  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
81871  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81872  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81873  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
81874  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81875  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
81876  *  0b011001..16-bit pixels (2-plane UV)
81877  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
81878  *  0b011011..16-bit pixels (2-plane VU)
81879  *  0b011110..16-bit pixels (3-plane format)
81880  *  0b011111..16-bit pixels (3-plane format)
81881  *  0b100100..2-bit pixels with alpha at the low 8 bits
81882  *  0b101100..16-bit pixels with alpha at the low 1bits
81883  *  0b101101..16-bit pixels with alpha at the low 4 bits
81884  */
81885 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
81886 
81887 #define PXP_PS_CTRL_WB_SWAP_MASK                 (0x40U)
81888 #define PXP_PS_CTRL_WB_SWAP_SHIFT                (6U)
81889 /*! WB_SWAP
81890  *  0b0..Byte swap is disabled
81891  *  0b1..Byte swap is enabled
81892  */
81893 #define PXP_PS_CTRL_WB_SWAP(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
81894 
81895 #define PXP_PS_CTRL_DECY_MASK                    (0x300U)
81896 #define PXP_PS_CTRL_DECY_SHIFT                   (8U)
81897 /*! DECY
81898  *  0b00..Disable pre-decimation filter.
81899  *  0b01..Decimate PS by 2.
81900  *  0b10..Decimate PS by 4.
81901  *  0b11..Decimate PS by 8.
81902  */
81903 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
81904 
81905 #define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
81906 #define PXP_PS_CTRL_DECX_SHIFT                   (10U)
81907 /*! DECX
81908  *  0b00..Disable pre-decimation filter.
81909  *  0b01..Decimate PS by 2.
81910  *  0b10..Decimate PS by 4.
81911  *  0b11..Decimate PS by 8.
81912  */
81913 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
81914 /*! @} */
81915 
81916 /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
81917 /*! @{ */
81918 
81919 #define PXP_PS_CTRL_SET_FORMAT_MASK              (0x3FU)
81920 #define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
81921 /*! FORMAT
81922  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
81923  *  0b001100..16-bit pixels with/without alpha at high 1bit
81924  *  0b001101..16-bit pixels with/without alpha at high 4 bits
81925  *  0b001110..16-bit pixels
81926  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
81927  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81928  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81929  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
81930  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81931  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
81932  *  0b011001..16-bit pixels (2-plane UV)
81933  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
81934  *  0b011011..16-bit pixels (2-plane VU)
81935  *  0b011110..16-bit pixels (3-plane format)
81936  *  0b011111..16-bit pixels (3-plane format)
81937  *  0b100100..2-bit pixels with alpha at the low 8 bits
81938  *  0b101100..16-bit pixels with alpha at the low 1bits
81939  *  0b101101..16-bit pixels with alpha at the low 4 bits
81940  */
81941 #define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
81942 
81943 #define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x40U)
81944 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (6U)
81945 /*! WB_SWAP
81946  *  0b0..Byte swap is disabled
81947  *  0b1..Byte swap is enabled
81948  */
81949 #define PXP_PS_CTRL_SET_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
81950 
81951 #define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
81952 #define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
81953 /*! DECY
81954  *  0b00..Disable pre-decimation filter.
81955  *  0b01..Decimate PS by 2.
81956  *  0b10..Decimate PS by 4.
81957  *  0b11..Decimate PS by 8.
81958  */
81959 #define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
81960 
81961 #define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
81962 #define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
81963 /*! DECX
81964  *  0b00..Disable pre-decimation filter.
81965  *  0b01..Decimate PS by 2.
81966  *  0b10..Decimate PS by 4.
81967  *  0b11..Decimate PS by 8.
81968  */
81969 #define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
81970 /*! @} */
81971 
81972 /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
81973 /*! @{ */
81974 
81975 #define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x3FU)
81976 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
81977 /*! FORMAT
81978  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
81979  *  0b001100..16-bit pixels with/without alpha at high 1bit
81980  *  0b001101..16-bit pixels with/without alpha at high 4 bits
81981  *  0b001110..16-bit pixels
81982  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
81983  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
81984  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
81985  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
81986  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
81987  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
81988  *  0b011001..16-bit pixels (2-plane UV)
81989  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
81990  *  0b011011..16-bit pixels (2-plane VU)
81991  *  0b011110..16-bit pixels (3-plane format)
81992  *  0b011111..16-bit pixels (3-plane format)
81993  *  0b100100..2-bit pixels with alpha at the low 8 bits
81994  *  0b101100..16-bit pixels with alpha at the low 1bits
81995  *  0b101101..16-bit pixels with alpha at the low 4 bits
81996  */
81997 #define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
81998 
81999 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x40U)
82000 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (6U)
82001 /*! WB_SWAP
82002  *  0b0..Byte swap is disabled
82003  *  0b1..Byte swap is enabled
82004  */
82005 #define PXP_PS_CTRL_CLR_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
82006 
82007 #define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
82008 #define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
82009 /*! DECY
82010  *  0b00..Disable pre-decimation filter.
82011  *  0b01..Decimate PS by 2.
82012  *  0b10..Decimate PS by 4.
82013  *  0b11..Decimate PS by 8.
82014  */
82015 #define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
82016 
82017 #define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
82018 #define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
82019 /*! DECX
82020  *  0b00..Disable pre-decimation filter.
82021  *  0b01..Decimate PS by 2.
82022  *  0b10..Decimate PS by 4.
82023  *  0b11..Decimate PS by 8.
82024  */
82025 #define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
82026 /*! @} */
82027 
82028 /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
82029 /*! @{ */
82030 
82031 #define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x3FU)
82032 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
82033 /*! FORMAT
82034  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
82035  *  0b001100..16-bit pixels with/without alpha at high 1bit
82036  *  0b001101..16-bit pixels with/without alpha at high 4 bits
82037  *  0b001110..16-bit pixels
82038  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
82039  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
82040  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
82041  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
82042  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
82043  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
82044  *  0b011001..16-bit pixels (2-plane UV)
82045  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
82046  *  0b011011..16-bit pixels (2-plane VU)
82047  *  0b011110..16-bit pixels (3-plane format)
82048  *  0b011111..16-bit pixels (3-plane format)
82049  *  0b100100..2-bit pixels with alpha at the low 8 bits
82050  *  0b101100..16-bit pixels with alpha at the low 1bits
82051  *  0b101101..16-bit pixels with alpha at the low 4 bits
82052  */
82053 #define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
82054 
82055 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x40U)
82056 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (6U)
82057 /*! WB_SWAP
82058  *  0b0..Byte swap is disabled
82059  *  0b1..Byte swap is enabled
82060  */
82061 #define PXP_PS_CTRL_TOG_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
82062 
82063 #define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
82064 #define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
82065 /*! DECY
82066  *  0b00..Disable pre-decimation filter.
82067  *  0b01..Decimate PS by 2.
82068  *  0b10..Decimate PS by 4.
82069  *  0b11..Decimate PS by 8.
82070  */
82071 #define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
82072 
82073 #define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
82074 #define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
82075 /*! DECX
82076  *  0b00..Disable pre-decimation filter.
82077  *  0b01..Decimate PS by 2.
82078  *  0b10..Decimate PS by 4.
82079  *  0b11..Decimate PS by 8.
82080  */
82081 #define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
82082 /*! @} */
82083 
82084 /*! @name PS_BUF - PS Input Buffer Address */
82085 /*! @{ */
82086 
82087 #define PXP_PS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
82088 #define PXP_PS_BUF_ADDR_SHIFT                    (0U)
82089 #define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
82090 /*! @} */
82091 
82092 /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
82093 /*! @{ */
82094 
82095 #define PXP_PS_UBUF_ADDR_MASK                    (0xFFFFFFFFU)
82096 #define PXP_PS_UBUF_ADDR_SHIFT                   (0U)
82097 #define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
82098 /*! @} */
82099 
82100 /*! @name PS_VBUF - PS V/Cr Input Buffer Address */
82101 /*! @{ */
82102 
82103 #define PXP_PS_VBUF_ADDR_MASK                    (0xFFFFFFFFU)
82104 #define PXP_PS_VBUF_ADDR_SHIFT                   (0U)
82105 #define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
82106 /*! @} */
82107 
82108 /*! @name PS_PITCH - Processed Surface Pitch */
82109 /*! @{ */
82110 
82111 #define PXP_PS_PITCH_PITCH_MASK                  (0xFFFFU)
82112 #define PXP_PS_PITCH_PITCH_SHIFT                 (0U)
82113 #define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
82114 /*! @} */
82115 
82116 /*! @name PS_BACKGROUND - PS Background Color */
82117 /*! @{ */
82118 
82119 #define PXP_PS_BACKGROUND_COLOR_MASK             (0xFFFFFFU)
82120 #define PXP_PS_BACKGROUND_COLOR_SHIFT            (0U)
82121 #define PXP_PS_BACKGROUND_COLOR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
82122 /*! @} */
82123 
82124 /*! @name PS_SCALE - PS Scale Factor Register */
82125 /*! @{ */
82126 
82127 #define PXP_PS_SCALE_XSCALE_MASK                 (0x7FFFU)
82128 #define PXP_PS_SCALE_XSCALE_SHIFT                (0U)
82129 #define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
82130 
82131 #define PXP_PS_SCALE_YSCALE_MASK                 (0x7FFF0000U)
82132 #define PXP_PS_SCALE_YSCALE_SHIFT                (16U)
82133 #define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
82134 /*! @} */
82135 
82136 /*! @name PS_OFFSET - PS Scale Offset Register */
82137 /*! @{ */
82138 
82139 #define PXP_PS_OFFSET_XOFFSET_MASK               (0xFFFU)
82140 #define PXP_PS_OFFSET_XOFFSET_SHIFT              (0U)
82141 #define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
82142 
82143 #define PXP_PS_OFFSET_YOFFSET_MASK               (0xFFF0000U)
82144 #define PXP_PS_OFFSET_YOFFSET_SHIFT              (16U)
82145 #define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
82146 /*! @} */
82147 
82148 /*! @name PS_CLRKEYLOW - PS Color Key Low */
82149 /*! @{ */
82150 
82151 #define PXP_PS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
82152 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT             (0U)
82153 #define PXP_PS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
82154 /*! @} */
82155 
82156 /*! @name PS_CLRKEYHIGH - PS Color Key High */
82157 /*! @{ */
82158 
82159 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
82160 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
82161 #define PXP_PS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
82162 /*! @} */
82163 
82164 /*! @name AS_CTRL - Alpha Surface Control */
82165 /*! @{ */
82166 
82167 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
82168 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
82169 /*! ALPHA_CTRL
82170  *  0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
82171  *  0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
82172  *  0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
82173  *        alpha is multiplied by the value in the ALPHA field.
82174  *  0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
82175  */
82176 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
82177 
82178 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
82179 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
82180 /*! ENABLE_COLORKEY
82181  *  0b0..Disabled
82182  *  0b1..Enabled
82183  */
82184 #define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
82185 
82186 #define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
82187 #define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
82188 /*! FORMAT
82189  *  0b0000..32-bit pixels with alpha
82190  *  0b0001..2-bit pixel with alpha at low 8 bits
82191  *  0b0100..32-bit pixels without alpha (unpacked 24-bit format)
82192  *  0b1000..16-bit pixels with alpha
82193  *  0b1001..16-bit pixels with alpha
82194  *  0b1010..16-bit pixel with alpha at low 1 bit
82195  *  0b1011..16-bit pixel with alpha at low 4 bits
82196  *  0b1100..16-bit pixels without alpha
82197  *  0b1101..16-bit pixels without alpha
82198  *  0b1110..16-bit pixels without alpha
82199  */
82200 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
82201 
82202 #define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
82203 #define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
82204 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
82205 
82206 #define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
82207 #define PXP_AS_CTRL_ROP_SHIFT                    (16U)
82208 /*! ROP
82209  *  0b0000..AS AND PS
82210  *  0b0001..nAS AND PS
82211  *  0b0010..AS AND nPS
82212  *  0b0011..AS OR PS
82213  *  0b0100..nAS OR PS
82214  *  0b0101..AS OR nPS
82215  *  0b0110..nAS
82216  *  0b0111..nPS
82217  *  0b1000..AS NAND PS
82218  *  0b1001..AS NOR PS
82219  *  0b1010..AS XOR PS
82220  *  0b1011..AS XNOR PS
82221  */
82222 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
82223 
82224 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            (0x100000U)
82225 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           (20U)
82226 /*! ALPHA_INVERT
82227  *  0b0..Not inverted
82228  *  0b1..Inverted
82229  */
82230 #define PXP_AS_CTRL_ALPHA_INVERT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
82231 /*! @} */
82232 
82233 /*! @name AS_BUF - Alpha Surface Buffer Pointer */
82234 /*! @{ */
82235 
82236 #define PXP_AS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
82237 #define PXP_AS_BUF_ADDR_SHIFT                    (0U)
82238 #define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
82239 /*! @} */
82240 
82241 /*! @name AS_PITCH - Alpha Surface Pitch */
82242 /*! @{ */
82243 
82244 #define PXP_AS_PITCH_PITCH_MASK                  (0xFFFFU)
82245 #define PXP_AS_PITCH_PITCH_SHIFT                 (0U)
82246 #define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
82247 /*! @} */
82248 
82249 /*! @name AS_CLRKEYLOW - Overlay Color Key Low */
82250 /*! @{ */
82251 
82252 #define PXP_AS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
82253 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT             (0U)
82254 #define PXP_AS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
82255 /*! @} */
82256 
82257 /*! @name AS_CLRKEYHIGH - Overlay Color Key High */
82258 /*! @{ */
82259 
82260 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
82261 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
82262 #define PXP_AS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
82263 /*! @} */
82264 
82265 /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
82266 /*! @{ */
82267 
82268 #define PXP_CSC1_COEF0_Y_OFFSET_MASK             (0x1FFU)
82269 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            (0U)
82270 #define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
82271 
82272 #define PXP_CSC1_COEF0_UV_OFFSET_MASK            (0x3FE00U)
82273 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           (9U)
82274 #define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
82275 
82276 #define PXP_CSC1_COEF0_C0_MASK                   (0x1FFC0000U)
82277 #define PXP_CSC1_COEF0_C0_SHIFT                  (18U)
82278 #define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
82279 
82280 #define PXP_CSC1_COEF0_BYPASS_MASK               (0x40000000U)
82281 #define PXP_CSC1_COEF0_BYPASS_SHIFT              (30U)
82282 #define PXP_CSC1_COEF0_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
82283 
82284 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK           (0x80000000U)
82285 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          (31U)
82286 /*! YCBCR_MODE
82287  *  0b0..YUV to RGB
82288  *  0b1..YCbCr to RGB
82289  */
82290 #define PXP_CSC1_COEF0_YCBCR_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
82291 /*! @} */
82292 
82293 /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
82294 /*! @{ */
82295 
82296 #define PXP_CSC1_COEF1_C4_MASK                   (0x7FFU)
82297 #define PXP_CSC1_COEF1_C4_SHIFT                  (0U)
82298 #define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
82299 
82300 #define PXP_CSC1_COEF1_C1_MASK                   (0x7FF0000U)
82301 #define PXP_CSC1_COEF1_C1_SHIFT                  (16U)
82302 #define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
82303 /*! @} */
82304 
82305 /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
82306 /*! @{ */
82307 
82308 #define PXP_CSC1_COEF2_C3_MASK                   (0x7FFU)
82309 #define PXP_CSC1_COEF2_C3_SHIFT                  (0U)
82310 #define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
82311 
82312 #define PXP_CSC1_COEF2_C2_MASK                   (0x7FF0000U)
82313 #define PXP_CSC1_COEF2_C2_SHIFT                  (16U)
82314 #define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
82315 /*! @} */
82316 
82317 /*! @name POWER - PXP Power Control Register */
82318 /*! @{ */
82319 
82320 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          (0xE00U)
82321 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         (9U)
82322 /*! ROT_MEM_LP_STATE
82323  *  0b000..Memory is not in low power state.
82324  *  0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
82325  *  0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
82326  *  0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
82327  */
82328 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
82329 /*! @} */
82330 
82331 /*! @name NEXT - Next Frame Pointer */
82332 /*! @{ */
82333 
82334 #define PXP_NEXT_ENABLED_MASK                    (0x1U)
82335 #define PXP_NEXT_ENABLED_SHIFT                   (0U)
82336 #define PXP_NEXT_ENABLED(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
82337 
82338 #define PXP_NEXT_POINTER_MASK                    (0xFFFFFFFCU)
82339 #define PXP_NEXT_POINTER_SHIFT                   (2U)
82340 #define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
82341 /*! @} */
82342 
82343 /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
82344 /*! @{ */
82345 
82346 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
82347 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
82348 /*! PORTER_DUFF_ENABLE
82349  *  0b0..Disabled
82350  *  0b1..Enabled
82351  */
82352 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
82353 
82354 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
82355 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
82356 /*! S0_S1_FACTOR_MODE
82357  *  0b00..1
82358  *  0b01..0
82359  *  0b10..Straight alpha
82360  *  0b11..Inverse alpha
82361  */
82362 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
82363 
82364 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
82365 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
82366 /*! S0_GLOBAL_ALPHA_MODE
82367  *  0b00..Global alpha
82368  *  0b01..Local alpha
82369  *  0b10..Scaled alpha
82370  *  0b11..Scaled alpha
82371  */
82372 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
82373 
82374 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK  (0x20U)
82375 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
82376 /*! S0_ALPHA_MODE
82377  *  0b0..Straight mode
82378  *  0b1..Inverted mode
82379  */
82380 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
82381 
82382 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK  (0x40U)
82383 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
82384 /*! S0_COLOR_MODE
82385  *  0b0..Original pixel
82386  *  0b1..Scaled pixel
82387  */
82388 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
82389 
82390 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
82391 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
82392 /*! S1_S0_FACTOR_MODE
82393  *  0b00..1
82394  *  0b01..0
82395  *  0b10..Straight alpha
82396  *  0b11..Inverse alpha
82397  */
82398 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
82399 
82400 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
82401 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
82402 /*! S1_GLOBAL_ALPHA_MODE
82403  *  0b00..Global alpha
82404  *  0b01..Local alpha
82405  *  0b10..Scaled alpha
82406  *  0b11..Scaled alpha
82407  */
82408 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
82409 
82410 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK  (0x1000U)
82411 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
82412 /*! S1_ALPHA_MODE
82413  *  0b0..Straight mode
82414  *  0b1..Inverted mode
82415  */
82416 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
82417 
82418 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK  (0x2000U)
82419 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
82420 /*! S1_COLOR_MODE
82421  *  0b0..Original pixel
82422  *  0b1..Scaled pixel
82423  */
82424 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
82425 
82426 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
82427 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
82428 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
82429 
82430 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
82431 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
82432 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
82433 /*! @} */
82434 
82435 
82436 /*!
82437  * @}
82438  */ /* end of group PXP_Register_Masks */
82439 
82440 
82441 /* PXP - Peripheral instance base addresses */
82442 /** Peripheral PXP base address */
82443 #define PXP_BASE                                 (0x40814000u)
82444 /** Peripheral PXP base pointer */
82445 #define PXP                                      ((PXP_Type *)PXP_BASE)
82446 /** Array initializer of PXP peripheral base addresses */
82447 #define PXP_BASE_ADDRS                           { PXP_BASE }
82448 /** Array initializer of PXP peripheral base pointers */
82449 #define PXP_BASE_PTRS                            { PXP }
82450 /** Interrupt vectors for the PXP peripheral type */
82451 #define PXP_IRQ0_IRQS                            { PXP_IRQn }
82452 
82453 /*!
82454  * @}
82455  */ /* end of group PXP_Peripheral_Access_Layer */
82456 
82457 
82458 /* ----------------------------------------------------------------------------
82459    -- RDC Peripheral Access Layer
82460    ---------------------------------------------------------------------------- */
82461 
82462 /*!
82463  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
82464  * @{
82465  */
82466 
82467 /** RDC - Register Layout Typedef */
82468 typedef struct {
82469   __I  uint32_t VIR;                               /**< Version Information, offset: 0x0 */
82470        uint8_t RESERVED_0[32];
82471   __IO uint32_t STAT;                              /**< Status, offset: 0x24 */
82472   __IO uint32_t INTCTRL;                           /**< Interrupt and Control, offset: 0x28 */
82473   __IO uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x2C */
82474        uint8_t RESERVED_1[464];
82475   __IO uint32_t MDA[12];                           /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
82476        uint8_t RESERVED_2[464];
82477   __IO uint32_t PDAP[128];                         /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
82478        uint8_t RESERVED_3[512];
82479   struct {                                         /* offset: 0x800, array step: 0x10 */
82480     __IO uint32_t MRSA;                              /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
82481     __IO uint32_t MREA;                              /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
82482     __IO uint32_t MRC;                               /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
82483     __IO uint32_t MRVS;                              /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
82484   } MR[59];
82485 } RDC_Type;
82486 
82487 /* ----------------------------------------------------------------------------
82488    -- RDC Register Masks
82489    ---------------------------------------------------------------------------- */
82490 
82491 /*!
82492  * @addtogroup RDC_Register_Masks RDC Register Masks
82493  * @{
82494  */
82495 
82496 /*! @name VIR - Version Information */
82497 /*! @{ */
82498 
82499 #define RDC_VIR_NDID_MASK                        (0xFU)
82500 #define RDC_VIR_NDID_SHIFT                       (0U)
82501 /*! NDID - Number of Domains
82502  */
82503 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
82504 
82505 #define RDC_VIR_NMSTR_MASK                       (0xFF0U)
82506 #define RDC_VIR_NMSTR_SHIFT                      (4U)
82507 /*! NMSTR - Number of Masters
82508  */
82509 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
82510 
82511 #define RDC_VIR_NPER_MASK                        (0xFF000U)
82512 #define RDC_VIR_NPER_SHIFT                       (12U)
82513 /*! NPER - Number of Peripherals
82514  */
82515 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
82516 
82517 #define RDC_VIR_NRGN_MASK                        (0xFF00000U)
82518 #define RDC_VIR_NRGN_SHIFT                       (20U)
82519 /*! NRGN - Number of Memory Regions
82520  */
82521 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
82522 /*! @} */
82523 
82524 /*! @name STAT - Status */
82525 /*! @{ */
82526 
82527 #define RDC_STAT_DID_MASK                        (0xFU)
82528 #define RDC_STAT_DID_SHIFT                       (0U)
82529 /*! DID - Domain ID
82530  */
82531 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
82532 
82533 #define RDC_STAT_PDS_MASK                        (0x100U)
82534 #define RDC_STAT_PDS_SHIFT                       (8U)
82535 /*! PDS - Power Domain Status
82536  *  0b0..Power Down Domain is OFF
82537  *  0b1..Power Down Domain is ON
82538  */
82539 #define RDC_STAT_PDS(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
82540 /*! @} */
82541 
82542 /*! @name INTCTRL - Interrupt and Control */
82543 /*! @{ */
82544 
82545 #define RDC_INTCTRL_RCI_EN_MASK                  (0x1U)
82546 #define RDC_INTCTRL_RCI_EN_SHIFT                 (0U)
82547 /*! RCI_EN - Restoration Complete Interrupt
82548  *  0b0..Interrupt Disabled
82549  *  0b1..Interrupt Enabled
82550  */
82551 #define RDC_INTCTRL_RCI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
82552 /*! @} */
82553 
82554 /*! @name INTSTAT - Interrupt Status */
82555 /*! @{ */
82556 
82557 #define RDC_INTSTAT_INT_MASK                     (0x1U)
82558 #define RDC_INTSTAT_INT_SHIFT                    (0U)
82559 /*! INT - Interrupt Status
82560  *  0b0..No Interrupt Pending
82561  *  0b1..Interrupt Pending
82562  */
82563 #define RDC_INTSTAT_INT(x)                       (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
82564 /*! @} */
82565 
82566 /*! @name MDA - Master Domain Assignment */
82567 /*! @{ */
82568 
82569 #define RDC_MDA_DID_MASK                         (0x3U)
82570 #define RDC_MDA_DID_SHIFT                        (0U)
82571 /*! DID - Domain ID
82572  *  0b00..Master assigned to Processing Domain 0
82573  *  0b01..Master assigned to Processing Domain 1
82574  *  0b10..Reserved
82575  *  0b11..Reserved
82576  */
82577 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
82578 
82579 #define RDC_MDA_LCK_MASK                         (0x80000000U)
82580 #define RDC_MDA_LCK_SHIFT                        (31U)
82581 /*! LCK - Assignment Lock
82582  *  0b0..Not Locked
82583  *  0b1..Locked
82584  */
82585 #define RDC_MDA_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
82586 /*! @} */
82587 
82588 /* The count of RDC_MDA */
82589 #define RDC_MDA_COUNT                            (12U)
82590 
82591 /*! @name PDAP - Peripheral Domain Access Permissions */
82592 /*! @{ */
82593 
82594 #define RDC_PDAP_D0W_MASK                        (0x1U)
82595 #define RDC_PDAP_D0W_SHIFT                       (0U)
82596 /*! D0W - Domain 0 Write Access
82597  *  0b0..No Write Access
82598  *  0b1..Write Access Allowed
82599  */
82600 #define RDC_PDAP_D0W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
82601 
82602 #define RDC_PDAP_D0R_MASK                        (0x2U)
82603 #define RDC_PDAP_D0R_SHIFT                       (1U)
82604 /*! D0R - Domain 0 Read Access
82605  *  0b0..No Read Access
82606  *  0b1..Read Access Allowed
82607  */
82608 #define RDC_PDAP_D0R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
82609 
82610 #define RDC_PDAP_D1W_MASK                        (0x4U)
82611 #define RDC_PDAP_D1W_SHIFT                       (2U)
82612 /*! D1W - Domain 1 Write Access
82613  *  0b0..No Write Access
82614  *  0b1..Write Access Allowed
82615  */
82616 #define RDC_PDAP_D1W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
82617 
82618 #define RDC_PDAP_D1R_MASK                        (0x8U)
82619 #define RDC_PDAP_D1R_SHIFT                       (3U)
82620 /*! D1R - Domain 1 Read Access
82621  *  0b0..No Read Access
82622  *  0b1..Read Access Allowed
82623  */
82624 #define RDC_PDAP_D1R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
82625 
82626 #define RDC_PDAP_SREQ_MASK                       (0x40000000U)
82627 #define RDC_PDAP_SREQ_SHIFT                      (30U)
82628 /*! SREQ - Semaphore Required
82629  *  0b0..Semaphores have no effect
82630  *  0b1..Semaphores are enforced
82631  */
82632 #define RDC_PDAP_SREQ(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
82633 
82634 #define RDC_PDAP_LCK_MASK                        (0x80000000U)
82635 #define RDC_PDAP_LCK_SHIFT                       (31U)
82636 /*! LCK - Peripheral Permissions Lock
82637  *  0b0..Not Locked
82638  *  0b1..Locked
82639  */
82640 #define RDC_PDAP_LCK(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
82641 /*! @} */
82642 
82643 /* The count of RDC_PDAP */
82644 #define RDC_PDAP_COUNT                           (128U)
82645 
82646 /*! @name MRSA - Memory Region Start Address */
82647 /*! @{ */
82648 
82649 #define RDC_MRSA_SADR_MASK                       (0xFFFFFF80U)
82650 #define RDC_MRSA_SADR_SHIFT                      (7U)
82651 /*! SADR - Start address for memory region
82652  */
82653 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
82654 /*! @} */
82655 
82656 /* The count of RDC_MRSA */
82657 #define RDC_MRSA_COUNT                           (59U)
82658 
82659 /*! @name MREA - Memory Region End Address */
82660 /*! @{ */
82661 
82662 #define RDC_MREA_EADR_MASK                       (0xFFFFFF80U)
82663 #define RDC_MREA_EADR_SHIFT                      (7U)
82664 /*! EADR - Upper bound for memory region
82665  */
82666 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
82667 /*! @} */
82668 
82669 /* The count of RDC_MREA */
82670 #define RDC_MREA_COUNT                           (59U)
82671 
82672 /*! @name MRC - Memory Region Control */
82673 /*! @{ */
82674 
82675 #define RDC_MRC_D0W_MASK                         (0x1U)
82676 #define RDC_MRC_D0W_SHIFT                        (0U)
82677 /*! D0W - Domain 0 Write Access to Region
82678  *  0b0..Processing Domain 0 does not have Write access to the memory region
82679  *  0b1..Processing Domain 0 has Write access to the memory region
82680  */
82681 #define RDC_MRC_D0W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
82682 
82683 #define RDC_MRC_D0R_MASK                         (0x2U)
82684 #define RDC_MRC_D0R_SHIFT                        (1U)
82685 /*! D0R - Domain 0 Read Access to Region
82686  *  0b0..Processing Domain 0 does not have Read access to the memory region
82687  *  0b1..Processing Domain 0 has Read access to the memory region
82688  */
82689 #define RDC_MRC_D0R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
82690 
82691 #define RDC_MRC_D1W_MASK                         (0x4U)
82692 #define RDC_MRC_D1W_SHIFT                        (2U)
82693 /*! D1W - Domain 1 Write Access to Region
82694  *  0b0..Processing Domain 1 does not have Write access to the memory region
82695  *  0b1..Processing Domain 1 has Write access to the memory region
82696  */
82697 #define RDC_MRC_D1W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
82698 
82699 #define RDC_MRC_D1R_MASK                         (0x8U)
82700 #define RDC_MRC_D1R_SHIFT                        (3U)
82701 /*! D1R - Domain 1 Read Access to Region
82702  *  0b0..Processing Domain 1 does not have Read access to the memory region
82703  *  0b1..Processing Domain 1 has Read access to the memory region
82704  */
82705 #define RDC_MRC_D1R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
82706 
82707 #define RDC_MRC_ENA_MASK                         (0x40000000U)
82708 #define RDC_MRC_ENA_SHIFT                        (30U)
82709 /*! ENA - Region Enable
82710  *  0b0..Memory region is not defined or restricted.
82711  *  0b1..Memory boundaries, domain permissions and controls are in effect.
82712  */
82713 #define RDC_MRC_ENA(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
82714 
82715 #define RDC_MRC_LCK_MASK                         (0x80000000U)
82716 #define RDC_MRC_LCK_SHIFT                        (31U)
82717 /*! LCK - Region Lock
82718  *  0b0..No Lock. All fields in this register may be modified.
82719  *  0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
82720  */
82721 #define RDC_MRC_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
82722 /*! @} */
82723 
82724 /* The count of RDC_MRC */
82725 #define RDC_MRC_COUNT                            (59U)
82726 
82727 /*! @name MRVS - Memory Region Violation Status */
82728 /*! @{ */
82729 
82730 #define RDC_MRVS_VDID_MASK                       (0x3U)
82731 #define RDC_MRVS_VDID_SHIFT                      (0U)
82732 /*! VDID - Violating Domain ID
82733  *  0b00..Processing Domain 0
82734  *  0b01..Processing Domain 1
82735  *  0b10..Reserved
82736  *  0b11..Reserved
82737  */
82738 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
82739 
82740 #define RDC_MRVS_AD_MASK                         (0x10U)
82741 #define RDC_MRVS_AD_SHIFT                        (4U)
82742 /*! AD - Access Denied
82743  */
82744 #define RDC_MRVS_AD(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
82745 
82746 #define RDC_MRVS_VADR_MASK                       (0xFFFFFFE0U)
82747 #define RDC_MRVS_VADR_SHIFT                      (5U)
82748 /*! VADR - Violating Address
82749  */
82750 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
82751 /*! @} */
82752 
82753 /* The count of RDC_MRVS */
82754 #define RDC_MRVS_COUNT                           (59U)
82755 
82756 
82757 /*!
82758  * @}
82759  */ /* end of group RDC_Register_Masks */
82760 
82761 
82762 /* RDC - Peripheral instance base addresses */
82763 /** Peripheral RDC base address */
82764 #define RDC_BASE                                 (0x40C78000u)
82765 /** Peripheral RDC base pointer */
82766 #define RDC                                      ((RDC_Type *)RDC_BASE)
82767 /** Array initializer of RDC peripheral base addresses */
82768 #define RDC_BASE_ADDRS                           { RDC_BASE }
82769 /** Array initializer of RDC peripheral base pointers */
82770 #define RDC_BASE_PTRS                            { RDC }
82771 /** Interrupt vectors for the RDC peripheral type */
82772 #define RDC_IRQS                                 { RDC_IRQn }
82773 
82774 /*!
82775  * @}
82776  */ /* end of group RDC_Peripheral_Access_Layer */
82777 
82778 
82779 /* ----------------------------------------------------------------------------
82780    -- RDC_SEMAPHORE Peripheral Access Layer
82781    ---------------------------------------------------------------------------- */
82782 
82783 /*!
82784  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
82785  * @{
82786  */
82787 
82788 /** RDC_SEMAPHORE - Register Layout Typedef */
82789 typedef struct {
82790   __IO uint8_t GATE[64];                           /**< Gate Register, array offset: 0x0, array step: 0x1 */
82791        uint8_t RESERVED_0[2];
82792   union {                                          /* offset: 0x42 */
82793     __IO uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
82794     __IO uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
82795   };
82796 } RDC_SEMAPHORE_Type;
82797 
82798 /* ----------------------------------------------------------------------------
82799    -- RDC_SEMAPHORE Register Masks
82800    ---------------------------------------------------------------------------- */
82801 
82802 /*!
82803  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
82804  * @{
82805  */
82806 
82807 /*! @name GATE - Gate Register */
82808 /*! @{ */
82809 
82810 #define RDC_SEMAPHORE_GATE_GTFSM_MASK            (0xFU)
82811 #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT           (0U)
82812 /*! GTFSM - Gate Finite State Machine.
82813  *  0b0000..The gate is unlocked (free).
82814  *  0b0001..The gate has been locked by processor with master_index = 0.
82815  *  0b0010..The gate has been locked by processor with master_index = 1.
82816  *  0b0011..The gate has been locked by processor with master_index = 2.
82817  *  0b0100..The gate has been locked by processor with master_index = 3.
82818  *  0b0101..The gate has been locked by processor with master_index = 4.
82819  *  0b0110..The gate has been locked by processor with master_index = 5.
82820  *  0b0111..The gate has been locked by processor with master_index = 6.
82821  *  0b1000..The gate has been locked by processor with master_index = 7.
82822  *  0b1001..The gate has been locked by processor with master_index = 8.
82823  *  0b1010..The gate has been locked by processor with master_index = 9.
82824  *  0b1011..The gate has been locked by processor with master_index = 10.
82825  *  0b1100..The gate has been locked by processor with master_index = 11.
82826  *  0b1101..The gate has been locked by processor with master_index = 12.
82827  *  0b1110..The gate has been locked by processor with master_index = 13.
82828  *  0b1111..The gate has been locked by processor with master_index = 14.
82829  */
82830 #define RDC_SEMAPHORE_GATE_GTFSM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)
82831 
82832 #define RDC_SEMAPHORE_GATE_LDOM_MASK             (0x30U)
82833 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT            (4U)
82834 /*! LDOM
82835  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
82836  *  0b01..The gate has been locked by domain 1.
82837  *  0b10..Reserved
82838  *  0b11..Reserved
82839  */
82840 #define RDC_SEMAPHORE_GATE_LDOM(x)               (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)
82841 /*! @} */
82842 
82843 /* The count of RDC_SEMAPHORE_GATE */
82844 #define RDC_SEMAPHORE_GATE_COUNT                 (64U)
82845 
82846 /*! @name RSTGT_R - Reset Gate Read */
82847 /*! @{ */
82848 
82849 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        (0xFU)
82850 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       (0U)
82851 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
82852 
82853 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        (0x30U)
82854 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       (4U)
82855 /*! RSTGSM
82856  *  0b00..Idle, waiting for the first data pattern write.
82857  *  0b01..Waiting for the second data pattern write.
82858  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
82859  *        this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
82860  *        for only one clock cycle. Software will never be able to observe this state.
82861  *  0b11..This state encoding is never used and therefore reserved.
82862  */
82863 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
82864 
82865 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        (0xFF00U)
82866 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       (8U)
82867 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
82868 /*! @} */
82869 
82870 /*! @name RSTGT_W - Reset Gate Write */
82871 /*! @{ */
82872 
82873 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        (0xFFU)
82874 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       (0U)
82875 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
82876 
82877 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        (0xFF00U)
82878 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       (8U)
82879 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
82880 /*! @} */
82881 
82882 
82883 /*!
82884  * @}
82885  */ /* end of group RDC_SEMAPHORE_Register_Masks */
82886 
82887 
82888 /* RDC_SEMAPHORE - Peripheral instance base addresses */
82889 /** Peripheral RDC_SEMAPHORE1 base address */
82890 #define RDC_SEMAPHORE1_BASE                      (0x40C44000u)
82891 /** Peripheral RDC_SEMAPHORE1 base pointer */
82892 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
82893 /** Peripheral RDC_SEMAPHORE2 base address */
82894 #define RDC_SEMAPHORE2_BASE                      (0x40CCC000u)
82895 /** Peripheral RDC_SEMAPHORE2 base pointer */
82896 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
82897 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
82898 #define RDC_SEMAPHORE_BASE_ADDRS                 { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
82899 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
82900 #define RDC_SEMAPHORE_BASE_PTRS                  { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
82901 
82902 /*!
82903  * @}
82904  */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
82905 
82906 
82907 /* ----------------------------------------------------------------------------
82908    -- RTWDOG Peripheral Access Layer
82909    ---------------------------------------------------------------------------- */
82910 
82911 /*!
82912  * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
82913  * @{
82914  */
82915 
82916 /** RTWDOG - Register Layout Typedef */
82917 typedef struct {
82918   __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
82919   __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
82920   __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
82921   __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
82922 } RTWDOG_Type;
82923 
82924 /* ----------------------------------------------------------------------------
82925    -- RTWDOG Register Masks
82926    ---------------------------------------------------------------------------- */
82927 
82928 /*!
82929  * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
82930  * @{
82931  */
82932 
82933 /*! @name CS - Watchdog Control and Status Register */
82934 /*! @{ */
82935 
82936 #define RTWDOG_CS_STOP_MASK                      (0x1U)
82937 #define RTWDOG_CS_STOP_SHIFT                     (0U)
82938 /*! STOP - Stop Enable
82939  *  0b0..Watchdog disabled in chip stop mode.
82940  *  0b1..Watchdog enabled in chip stop mode.
82941  */
82942 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
82943 
82944 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
82945 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
82946 /*! WAIT - Wait Enable
82947  *  0b0..Watchdog disabled in chip wait mode.
82948  *  0b1..Watchdog enabled in chip wait mode.
82949  */
82950 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
82951 
82952 #define RTWDOG_CS_DBG_MASK                       (0x4U)
82953 #define RTWDOG_CS_DBG_SHIFT                      (2U)
82954 /*! DBG - Debug Enable
82955  *  0b0..Watchdog disabled in chip debug mode.
82956  *  0b1..Watchdog enabled in chip debug mode.
82957  */
82958 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
82959 
82960 #define RTWDOG_CS_TST_MASK                       (0x18U)
82961 #define RTWDOG_CS_TST_SHIFT                      (3U)
82962 /*! TST - Watchdog Test
82963  *  0b00..Watchdog test mode disabled.
82964  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
82965  *        use this setting to indicate that the watchdog is functioning normally in user mode.
82966  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
82967  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
82968  */
82969 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
82970 
82971 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
82972 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
82973 /*! UPDATE - Allow updates
82974  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
82975  *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
82976  */
82977 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
82978 
82979 #define RTWDOG_CS_INT_MASK                       (0x40U)
82980 #define RTWDOG_CS_INT_SHIFT                      (6U)
82981 /*! INT - Watchdog Interrupt
82982  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
82983  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
82984  */
82985 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
82986 
82987 #define RTWDOG_CS_EN_MASK                        (0x80U)
82988 #define RTWDOG_CS_EN_SHIFT                       (7U)
82989 /*! EN - Watchdog Enable
82990  *  0b0..Watchdog disabled.
82991  *  0b1..Watchdog enabled.
82992  */
82993 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
82994 
82995 #define RTWDOG_CS_CLK_MASK                       (0x300U)
82996 #define RTWDOG_CS_CLK_SHIFT                      (8U)
82997 /*! CLK - Watchdog Clock
82998  */
82999 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
83000 
83001 #define RTWDOG_CS_RCS_MASK                       (0x400U)
83002 #define RTWDOG_CS_RCS_SHIFT                      (10U)
83003 /*! RCS - Reconfiguration Success
83004  *  0b0..Reconfiguring WDOG.
83005  *  0b1..Reconfiguration is successful.
83006  */
83007 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
83008 
83009 #define RTWDOG_CS_ULK_MASK                       (0x800U)
83010 #define RTWDOG_CS_ULK_SHIFT                      (11U)
83011 /*! ULK - Unlock status
83012  *  0b0..WDOG is locked.
83013  *  0b1..WDOG is unlocked.
83014  */
83015 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
83016 
83017 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
83018 #define RTWDOG_CS_PRES_SHIFT                     (12U)
83019 /*! PRES - Watchdog prescaler
83020  *  0b0..256 prescaler disabled.
83021  *  0b1..256 prescaler enabled.
83022  */
83023 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
83024 
83025 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
83026 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
83027 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
83028  *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
83029  *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
83030  */
83031 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
83032 
83033 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
83034 #define RTWDOG_CS_FLG_SHIFT                      (14U)
83035 /*! FLG - Watchdog Interrupt Flag
83036  *  0b0..No interrupt occurred.
83037  *  0b1..An interrupt occurred.
83038  */
83039 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
83040 
83041 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
83042 #define RTWDOG_CS_WIN_SHIFT                      (15U)
83043 /*! WIN - Watchdog Window
83044  *  0b0..Window mode disabled.
83045  *  0b1..Window mode enabled.
83046  */
83047 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
83048 /*! @} */
83049 
83050 /*! @name CNT - Watchdog Counter Register */
83051 /*! @{ */
83052 
83053 #define RTWDOG_CNT_CNTLOW_MASK                   (0xFFU)
83054 #define RTWDOG_CNT_CNTLOW_SHIFT                  (0U)
83055 /*! CNTLOW - Low byte of the Watchdog Counter
83056  */
83057 #define RTWDOG_CNT_CNTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
83058 
83059 #define RTWDOG_CNT_CNTHIGH_MASK                  (0xFF00U)
83060 #define RTWDOG_CNT_CNTHIGH_SHIFT                 (8U)
83061 /*! CNTHIGH - High byte of the Watchdog Counter
83062  */
83063 #define RTWDOG_CNT_CNTHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
83064 /*! @} */
83065 
83066 /*! @name TOVAL - Watchdog Timeout Value Register */
83067 /*! @{ */
83068 
83069 #define RTWDOG_TOVAL_TOVALLOW_MASK               (0xFFU)
83070 #define RTWDOG_TOVAL_TOVALLOW_SHIFT              (0U)
83071 /*! TOVALLOW - Low byte of the timeout value
83072  */
83073 #define RTWDOG_TOVAL_TOVALLOW(x)                 (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
83074 
83075 #define RTWDOG_TOVAL_TOVALHIGH_MASK              (0xFF00U)
83076 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT             (8U)
83077 /*! TOVALHIGH - High byte of the timeout value
83078  */
83079 #define RTWDOG_TOVAL_TOVALHIGH(x)                (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
83080 /*! @} */
83081 
83082 /*! @name WIN - Watchdog Window Register */
83083 /*! @{ */
83084 
83085 #define RTWDOG_WIN_WINLOW_MASK                   (0xFFU)
83086 #define RTWDOG_WIN_WINLOW_SHIFT                  (0U)
83087 /*! WINLOW - Low byte of Watchdog Window
83088  */
83089 #define RTWDOG_WIN_WINLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
83090 
83091 #define RTWDOG_WIN_WINHIGH_MASK                  (0xFF00U)
83092 #define RTWDOG_WIN_WINHIGH_SHIFT                 (8U)
83093 /*! WINHIGH - High byte of Watchdog Window
83094  */
83095 #define RTWDOG_WIN_WINHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
83096 /*! @} */
83097 
83098 
83099 /*!
83100  * @}
83101  */ /* end of group RTWDOG_Register_Masks */
83102 
83103 
83104 /* RTWDOG - Peripheral instance base addresses */
83105 /** Peripheral RTWDOG3 base address */
83106 #define RTWDOG3_BASE                             (0x40038000u)
83107 /** Peripheral RTWDOG3 base pointer */
83108 #define RTWDOG3                                  ((RTWDOG_Type *)RTWDOG3_BASE)
83109 /** Peripheral RTWDOG4 base address */
83110 #define RTWDOG4_BASE                             (0x40C10000u)
83111 /** Peripheral RTWDOG4 base pointer */
83112 #define RTWDOG4                                  ((RTWDOG_Type *)RTWDOG4_BASE)
83113 /** Array initializer of RTWDOG peripheral base addresses */
83114 #define RTWDOG_BASE_ADDRS                        { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
83115 /** Array initializer of RTWDOG peripheral base pointers */
83116 #define RTWDOG_BASE_PTRS                         { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
83117 /** Interrupt vectors for the RTWDOG peripheral type */
83118 #define RTWDOG_IRQS                              { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn }
83119 /* Extra definition */
83120 #define RTWDOG_UPDATE_KEY                        (0xD928C520U)
83121 #define RTWDOG_REFRESH_KEY                       (0xB480A602U)
83122 
83123 
83124 /*!
83125  * @}
83126  */ /* end of group RTWDOG_Peripheral_Access_Layer */
83127 
83128 
83129 /* ----------------------------------------------------------------------------
83130    -- SEMA4 Peripheral Access Layer
83131    ---------------------------------------------------------------------------- */
83132 
83133 /*!
83134  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
83135  * @{
83136  */
83137 
83138 /** SEMA4 - Register Layout Typedef */
83139 typedef struct {
83140   __IO uint8_t GATE[16];                           /**< Semaphores Gate n Register, array offset: 0x0, array step: 0x1 */
83141        uint8_t RESERVED_0[48];
83142   struct {                                         /* offset: 0x40, array step: 0x8 */
83143     __IO uint16_t CPINE;                             /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
83144          uint8_t RESERVED_0[6];
83145   } CPINE[2];
83146        uint8_t RESERVED_1[48];
83147   struct {                                         /* offset: 0x80, array step: 0x8 */
83148     __I  uint16_t CPNTF;                             /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
83149          uint8_t RESERVED_0[6];
83150   } CPNTF[2];
83151        uint8_t RESERVED_2[112];
83152   __IO uint16_t RSTGT;                             /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
83153        uint8_t RESERVED_3[2];
83154   __IO uint16_t RSTNTF;                            /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
83155 } SEMA4_Type;
83156 
83157 /* ----------------------------------------------------------------------------
83158    -- SEMA4 Register Masks
83159    ---------------------------------------------------------------------------- */
83160 
83161 /*!
83162  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
83163  * @{
83164  */
83165 
83166 /*! @name GATE - Semaphores Gate n Register */
83167 /*! @{ */
83168 
83169 #define SEMA4_GATE_GTFSM_MASK                    (0x3U)
83170 #define SEMA4_GATE_GTFSM_SHIFT                   (0U)
83171 /*! GTFSM - Gate Finite State Machine.
83172  *  0b00..The gate is unlocked (free).
83173  *  0b01..The gate has been locked by processor 0.
83174  *  0b10..The gate has been locked by processor 1.
83175  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
83176  *        operation" and do not affect the gate state machine.
83177  */
83178 #define SEMA4_GATE_GTFSM(x)                      (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)
83179 /*! @} */
83180 
83181 /* The count of SEMA4_GATE */
83182 #define SEMA4_GATE_COUNT                         (16U)
83183 
83184 /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
83185 /*! @{ */
83186 
83187 #define SEMA4_CPINE_INE7_MASK                    (0x1U)
83188 #define SEMA4_CPINE_INE7_SHIFT                   (0U)
83189 /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
83190  *    of an interrupt notification from a failed attempt to lock gate 7.
83191  *  0b0..The generation of the notification interrupt is disabled.
83192  *  0b1..The generation of the notification interrupt is enabled.
83193  */
83194 #define SEMA4_CPINE_INE7(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
83195 
83196 #define SEMA4_CPINE_INE6_MASK                    (0x2U)
83197 #define SEMA4_CPINE_INE6_SHIFT                   (1U)
83198 /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
83199  *    of an interrupt notification from a failed attempt to lock gate 6.
83200  *  0b0..The generation of the notification interrupt is disabled.
83201  *  0b1..The generation of the notification interrupt is enabled.
83202  */
83203 #define SEMA4_CPINE_INE6(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
83204 
83205 #define SEMA4_CPINE_INE5_MASK                    (0x4U)
83206 #define SEMA4_CPINE_INE5_SHIFT                   (2U)
83207 /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
83208  *    of an interrupt notification from a failed attempt to lock gate 5.
83209  *  0b0..The generation of the notification interrupt is disabled.
83210  *  0b1..The generation of the notification interrupt is enabled.
83211  */
83212 #define SEMA4_CPINE_INE5(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
83213 
83214 #define SEMA4_CPINE_INE4_MASK                    (0x8U)
83215 #define SEMA4_CPINE_INE4_SHIFT                   (3U)
83216 /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
83217  *    of an interrupt notification from a failed attempt to lock gate 4.
83218  *  0b0..The generation of the notification interrupt is disabled.
83219  *  0b1..The generation of the notification interrupt is enabled.
83220  */
83221 #define SEMA4_CPINE_INE4(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
83222 
83223 #define SEMA4_CPINE_INE3_MASK                    (0x10U)
83224 #define SEMA4_CPINE_INE3_SHIFT                   (4U)
83225 /*! INE3
83226  *  0b0..The generation of the notification interrupt is disabled.
83227  *  0b1..The generation of the notification interrupt is enabled.
83228  */
83229 #define SEMA4_CPINE_INE3(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
83230 
83231 #define SEMA4_CPINE_INE2_MASK                    (0x20U)
83232 #define SEMA4_CPINE_INE2_SHIFT                   (5U)
83233 /*! INE2
83234  *  0b0..The generation of the notification interrupt is disabled.
83235  *  0b1..The generation of the notification interrupt is enabled.
83236  */
83237 #define SEMA4_CPINE_INE2(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
83238 
83239 #define SEMA4_CPINE_INE1_MASK                    (0x40U)
83240 #define SEMA4_CPINE_INE1_SHIFT                   (6U)
83241 /*! INE1
83242  *  0b0..The generation of the notification interrupt is disabled.
83243  *  0b1..The generation of the notification interrupt is enabled.
83244  */
83245 #define SEMA4_CPINE_INE1(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
83246 
83247 #define SEMA4_CPINE_INE0_MASK                    (0x80U)
83248 #define SEMA4_CPINE_INE0_SHIFT                   (7U)
83249 /*! INE0
83250  *  0b0..The generation of the notification interrupt is disabled.
83251  *  0b1..The generation of the notification interrupt is enabled.
83252  */
83253 #define SEMA4_CPINE_INE0(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
83254 
83255 #define SEMA4_CPINE_INE15_MASK                   (0x100U)
83256 #define SEMA4_CPINE_INE15_SHIFT                  (8U)
83257 /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
83258  *    generation of an interrupt notification from a failed attempt to lock gate 15.
83259  *  0b0..The generation of the notification interrupt is disabled.
83260  *  0b1..The generation of the notification interrupt is enabled.
83261  */
83262 #define SEMA4_CPINE_INE15(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
83263 
83264 #define SEMA4_CPINE_INE14_MASK                   (0x200U)
83265 #define SEMA4_CPINE_INE14_SHIFT                  (9U)
83266 /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
83267  *    generation of an interrupt notification from a failed attempt to lock gate 14.
83268  *  0b0..The generation of the notification interrupt is disabled.
83269  *  0b1..The generation of the notification interrupt is enabled.
83270  */
83271 #define SEMA4_CPINE_INE14(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
83272 
83273 #define SEMA4_CPINE_INE13_MASK                   (0x400U)
83274 #define SEMA4_CPINE_INE13_SHIFT                  (10U)
83275 /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
83276  *    generation of an interrupt notification from a failed attempt to lock gate 13.
83277  *  0b0..The generation of the notification interrupt is disabled.
83278  *  0b1..The generation of the notification interrupt is enabled.
83279  */
83280 #define SEMA4_CPINE_INE13(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
83281 
83282 #define SEMA4_CPINE_INE12_MASK                   (0x800U)
83283 #define SEMA4_CPINE_INE12_SHIFT                  (11U)
83284 /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
83285  *    generation of an interrupt notification from a failed attempt to lock gate 12.
83286  *  0b0..The generation of the notification interrupt is disabled.
83287  *  0b1..The generation of the notification interrupt is enabled.
83288  */
83289 #define SEMA4_CPINE_INE12(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
83290 
83291 #define SEMA4_CPINE_INE11_MASK                   (0x1000U)
83292 #define SEMA4_CPINE_INE11_SHIFT                  (12U)
83293 /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
83294  *    generation of an interrupt notification from a failed attempt to lock gate 11.
83295  *  0b0..The generation of the notification interrupt is disabled.
83296  *  0b1..The generation of the notification interrupt is enabled.
83297  */
83298 #define SEMA4_CPINE_INE11(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
83299 
83300 #define SEMA4_CPINE_INE10_MASK                   (0x2000U)
83301 #define SEMA4_CPINE_INE10_SHIFT                  (13U)
83302 /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
83303  *    generation of an interrupt notification from a failed attempt to lock gate 10.
83304  *  0b0..The generation of the notification interrupt is disabled.
83305  *  0b1..The generation of the notification interrupt is enabled.
83306  */
83307 #define SEMA4_CPINE_INE10(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
83308 
83309 #define SEMA4_CPINE_INE9_MASK                    (0x4000U)
83310 #define SEMA4_CPINE_INE9_SHIFT                   (14U)
83311 /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
83312  *    of an interrupt notification from a failed attempt to lock gate 9.
83313  *  0b0..The generation of the notification interrupt is disabled.
83314  *  0b1..The generation of the notification interrupt is enabled.
83315  */
83316 #define SEMA4_CPINE_INE9(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
83317 
83318 #define SEMA4_CPINE_INE8_MASK                    (0x8000U)
83319 #define SEMA4_CPINE_INE8_SHIFT                   (15U)
83320 /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
83321  *    of an interrupt notification from a failed attempt to lock gate 8.
83322  *  0b0..The generation of the notification interrupt is disabled.
83323  *  0b1..The generation of the notification interrupt is enabled.
83324  */
83325 #define SEMA4_CPINE_INE8(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
83326 /*! @} */
83327 
83328 /* The count of SEMA4_CPINE */
83329 #define SEMA4_CPINE_COUNT                        (2U)
83330 
83331 /*! @name CPNTF - Semaphores Processor n IRQ Notification */
83332 /*! @{ */
83333 
83334 #define SEMA4_CPNTF_GN7_MASK                     (0x1U)
83335 #define SEMA4_CPNTF_GN7_SHIFT                    (0U)
83336 #define SEMA4_CPNTF_GN7(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
83337 
83338 #define SEMA4_CPNTF_GN6_MASK                     (0x2U)
83339 #define SEMA4_CPNTF_GN6_SHIFT                    (1U)
83340 #define SEMA4_CPNTF_GN6(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
83341 
83342 #define SEMA4_CPNTF_GN5_MASK                     (0x4U)
83343 #define SEMA4_CPNTF_GN5_SHIFT                    (2U)
83344 #define SEMA4_CPNTF_GN5(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
83345 
83346 #define SEMA4_CPNTF_GN4_MASK                     (0x8U)
83347 #define SEMA4_CPNTF_GN4_SHIFT                    (3U)
83348 #define SEMA4_CPNTF_GN4(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
83349 
83350 #define SEMA4_CPNTF_GN3_MASK                     (0x10U)
83351 #define SEMA4_CPNTF_GN3_SHIFT                    (4U)
83352 #define SEMA4_CPNTF_GN3(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
83353 
83354 #define SEMA4_CPNTF_GN2_MASK                     (0x20U)
83355 #define SEMA4_CPNTF_GN2_SHIFT                    (5U)
83356 #define SEMA4_CPNTF_GN2(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
83357 
83358 #define SEMA4_CPNTF_GN1_MASK                     (0x40U)
83359 #define SEMA4_CPNTF_GN1_SHIFT                    (6U)
83360 #define SEMA4_CPNTF_GN1(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
83361 
83362 #define SEMA4_CPNTF_GN0_MASK                     (0x80U)
83363 #define SEMA4_CPNTF_GN0_SHIFT                    (7U)
83364 #define SEMA4_CPNTF_GN0(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
83365 
83366 #define SEMA4_CPNTF_GN15_MASK                    (0x100U)
83367 #define SEMA4_CPNTF_GN15_SHIFT                   (8U)
83368 #define SEMA4_CPNTF_GN15(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
83369 
83370 #define SEMA4_CPNTF_GN14_MASK                    (0x200U)
83371 #define SEMA4_CPNTF_GN14_SHIFT                   (9U)
83372 #define SEMA4_CPNTF_GN14(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
83373 
83374 #define SEMA4_CPNTF_GN13_MASK                    (0x400U)
83375 #define SEMA4_CPNTF_GN13_SHIFT                   (10U)
83376 #define SEMA4_CPNTF_GN13(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
83377 
83378 #define SEMA4_CPNTF_GN12_MASK                    (0x800U)
83379 #define SEMA4_CPNTF_GN12_SHIFT                   (11U)
83380 #define SEMA4_CPNTF_GN12(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
83381 
83382 #define SEMA4_CPNTF_GN11_MASK                    (0x1000U)
83383 #define SEMA4_CPNTF_GN11_SHIFT                   (12U)
83384 #define SEMA4_CPNTF_GN11(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
83385 
83386 #define SEMA4_CPNTF_GN10_MASK                    (0x2000U)
83387 #define SEMA4_CPNTF_GN10_SHIFT                   (13U)
83388 #define SEMA4_CPNTF_GN10(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
83389 
83390 #define SEMA4_CPNTF_GN9_MASK                     (0x4000U)
83391 #define SEMA4_CPNTF_GN9_SHIFT                    (14U)
83392 #define SEMA4_CPNTF_GN9(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
83393 
83394 #define SEMA4_CPNTF_GN8_MASK                     (0x8000U)
83395 #define SEMA4_CPNTF_GN8_SHIFT                    (15U)
83396 #define SEMA4_CPNTF_GN8(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
83397 /*! @} */
83398 
83399 /* The count of SEMA4_CPNTF */
83400 #define SEMA4_CPNTF_COUNT                        (2U)
83401 
83402 /*! @name RSTGT - Semaphores (Secure) Reset Gate n */
83403 /*! @{ */
83404 
83405 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    (0xFFU)
83406 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   (0U)
83407 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
83408 
83409 #define SEMA4_RSTGT_RSTGTN_MASK                  (0xFF00U)
83410 #define SEMA4_RSTGT_RSTGTN_SHIFT                 (8U)
83411 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
83412 /*! @} */
83413 
83414 /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
83415 /*! @{ */
83416 
83417 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   (0xFFU)
83418 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  (0U)
83419 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
83420 
83421 #define SEMA4_RSTNTF_RSTNTN_MASK                 (0xFF00U)
83422 #define SEMA4_RSTNTF_RSTNTN_SHIFT                (8U)
83423 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
83424 /*! @} */
83425 
83426 
83427 /*!
83428  * @}
83429  */ /* end of group SEMA4_Register_Masks */
83430 
83431 
83432 /* SEMA4 - Peripheral instance base addresses */
83433 /** Peripheral SEMA4 base address */
83434 #define SEMA4_BASE                               (0x40CC8000u)
83435 /** Peripheral SEMA4 base pointer */
83436 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
83437 /** Array initializer of SEMA4 peripheral base addresses */
83438 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
83439 /** Array initializer of SEMA4 peripheral base pointers */
83440 #define SEMA4_BASE_PTRS                          { SEMA4 }
83441 
83442 /*!
83443  * @}
83444  */ /* end of group SEMA4_Peripheral_Access_Layer */
83445 
83446 
83447 /* ----------------------------------------------------------------------------
83448    -- SEMC Peripheral Access Layer
83449    ---------------------------------------------------------------------------- */
83450 
83451 /*!
83452  * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
83453  * @{
83454  */
83455 
83456 /** SEMC - Register Layout Typedef */
83457 typedef struct {
83458   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
83459   __IO uint32_t IOCR;                              /**< IO MUX Control Register, offset: 0x4 */
83460   __IO uint32_t BMCR0;                             /**< Bus (AXI) Master Control Register 0, offset: 0x8 */
83461   __IO uint32_t BMCR1;                             /**< Bus (AXI) Master Control Register 1, offset: 0xC */
83462   __IO uint32_t BR[9];                             /**< Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4 */
83463   __IO uint32_t DLLCR;                             /**< DLL Control Register, offset: 0x34 */
83464   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x38 */
83465   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x3C */
83466   __IO uint32_t SDRAMCR0;                          /**< SDRAM Control Register 0, offset: 0x40 */
83467   __IO uint32_t SDRAMCR1;                          /**< SDRAM Control Register 1, offset: 0x44 */
83468   __IO uint32_t SDRAMCR2;                          /**< SDRAM Control Register 2, offset: 0x48 */
83469   __IO uint32_t SDRAMCR3;                          /**< SDRAM Control Register 3, offset: 0x4C */
83470   __IO uint32_t NANDCR0;                           /**< NAND Control Register 0, offset: 0x50 */
83471   __IO uint32_t NANDCR1;                           /**< NAND Control Register 1, offset: 0x54 */
83472   __IO uint32_t NANDCR2;                           /**< NAND Control Register 2, offset: 0x58 */
83473   __IO uint32_t NANDCR3;                           /**< NAND Control Register 3, offset: 0x5C */
83474   __IO uint32_t NORCR0;                            /**< NOR Control Register 0, offset: 0x60 */
83475   __IO uint32_t NORCR1;                            /**< NOR Control Register 1, offset: 0x64 */
83476   __IO uint32_t NORCR2;                            /**< NOR Control Register 2, offset: 0x68 */
83477   __IO uint32_t NORCR3;                            /**< NOR Control Register 3, offset: 0x6C */
83478   __IO uint32_t SRAMCR0;                           /**< SRAM Control Register 0, offset: 0x70 */
83479   __IO uint32_t SRAMCR1;                           /**< SRAM Control Register 1, offset: 0x74 */
83480   __IO uint32_t SRAMCR2;                           /**< SRAM Control Register 2, offset: 0x78 */
83481        uint32_t SRAMCR3;                           /**< SRAM Control Register 3, offset: 0x7C */
83482   __IO uint32_t DBICR0;                            /**< DBI-B Control Register 0, offset: 0x80 */
83483   __IO uint32_t DBICR1;                            /**< DBI-B Control Register 1, offset: 0x84 */
83484   __IO uint32_t DBICR2;                            /**< DBI-B Control Register 2, offset: 0x88 */
83485        uint8_t RESERVED_0[4];
83486   __IO uint32_t IPCR0;                             /**< IP Command Control Register 0, offset: 0x90 */
83487   __IO uint32_t IPCR1;                             /**< IP Command Control Register 1, offset: 0x94 */
83488   __IO uint32_t IPCR2;                             /**< IP Command Control Register 2, offset: 0x98 */
83489   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0x9C */
83490   __IO uint32_t IPTXDAT;                           /**< TX DATA Register, offset: 0xA0 */
83491        uint8_t RESERVED_1[12];
83492   __I  uint32_t IPRXDAT;                           /**< RX DATA Register, offset: 0xB0 */
83493        uint8_t RESERVED_2[12];
83494   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xC0 */
83495        uint32_t STS1;                              /**< Status Register 1, offset: 0xC4 */
83496   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xC8 */
83497        uint32_t STS3;                              /**< Status Register 3, offset: 0xCC */
83498        uint32_t STS4;                              /**< Status Register 4, offset: 0xD0 */
83499        uint32_t STS5;                              /**< Status Register 5, offset: 0xD4 */
83500        uint32_t STS6;                              /**< Status Register 6, offset: 0xD8 */
83501        uint32_t STS7;                              /**< Status Register 7, offset: 0xDC */
83502        uint32_t STS8;                              /**< Status Register 8, offset: 0xE0 */
83503        uint32_t STS9;                              /**< Status Register 9, offset: 0xE4 */
83504        uint32_t STS10;                             /**< Status Register 10, offset: 0xE8 */
83505        uint32_t STS11;                             /**< Status Register 11, offset: 0xEC */
83506   __I  uint32_t STS12;                             /**< Status Register 12, offset: 0xF0 */
83507   __I  uint32_t STS13;                             /**< Status Register 13, offset: 0xF4 */
83508        uint32_t STS14;                             /**< Status Register 14, offset: 0xF8 */
83509        uint32_t STS15;                             /**< Status Register 15, offset: 0xFC */
83510   __IO uint32_t BR9;                               /**< Base Register 9, offset: 0x100 */
83511   __IO uint32_t BR10;                              /**< Base Register 10, offset: 0x104 */
83512   __IO uint32_t BR11;                              /**< Base Register 11, offset: 0x108 */
83513        uint8_t RESERVED_3[20];
83514   __IO uint32_t SRAMCR4;                           /**< SRAM Control Register 4, offset: 0x120 */
83515   __IO uint32_t SRAMCR5;                           /**< SRAM Control Register 5, offset: 0x124 */
83516   __IO uint32_t SRAMCR6;                           /**< SRAM Control Register 6, offset: 0x128 */
83517        uint8_t RESERVED_4[36];
83518   __IO uint32_t DCCR;                              /**< Delay Chain Control Register, offset: 0x150 */
83519 } SEMC_Type;
83520 
83521 /* ----------------------------------------------------------------------------
83522    -- SEMC Register Masks
83523    ---------------------------------------------------------------------------- */
83524 
83525 /*!
83526  * @addtogroup SEMC_Register_Masks SEMC Register Masks
83527  * @{
83528  */
83529 
83530 /*! @name MCR - Module Control Register */
83531 /*! @{ */
83532 
83533 #define SEMC_MCR_SWRST_MASK                      (0x1U)
83534 #define SEMC_MCR_SWRST_SHIFT                     (0U)
83535 /*! SWRST - Software Reset
83536  *  0b0..No reset
83537  *  0b1..Reset
83538  */
83539 #define SEMC_MCR_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
83540 
83541 #define SEMC_MCR_MDIS_MASK                       (0x2U)
83542 #define SEMC_MCR_MDIS_SHIFT                      (1U)
83543 /*! MDIS - Module Disable
83544  *  0b0..Module enabled
83545  *  0b1..Module disabled
83546  */
83547 #define SEMC_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
83548 
83549 #define SEMC_MCR_DQSMD_MASK                      (0x4U)
83550 #define SEMC_MCR_DQSMD_SHIFT                     (2U)
83551 /*! DQSMD - DQS (read strobe) mode
83552  *  0b0..Dummy read strobe loopbacked internally
83553  *  0b1..Dummy read strobe loopbacked from DQS pad
83554  */
83555 #define SEMC_MCR_DQSMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
83556 
83557 #define SEMC_MCR_WPOL0_MASK                      (0x40U)
83558 #define SEMC_MCR_WPOL0_SHIFT                     (6U)
83559 /*! WPOL0 - WAIT/RDY polarity for SRAM/NOR
83560  *  0b0..WAIT/RDY polarity is not changed.
83561  *  0b1..WAIT/RDY polarity is inverted.
83562  */
83563 #define SEMC_MCR_WPOL0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
83564 
83565 #define SEMC_MCR_WPOL1_MASK                      (0x80U)
83566 #define SEMC_MCR_WPOL1_SHIFT                     (7U)
83567 /*! WPOL1 - R/B# polarity for NAND device
83568  *  0b0..R/B# polarity is not changed.
83569  *  0b1..R/B# polarity is inverted.
83570  */
83571 #define SEMC_MCR_WPOL1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
83572 
83573 #define SEMC_MCR_CTO_MASK                        (0xFF0000U)
83574 #define SEMC_MCR_CTO_SHIFT                       (16U)
83575 /*! CTO - Command Execution timeout cycles
83576  */
83577 #define SEMC_MCR_CTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
83578 
83579 #define SEMC_MCR_BTO_MASK                        (0x1F000000U)
83580 #define SEMC_MCR_BTO_SHIFT                       (24U)
83581 /*! BTO - Bus timeout cycles
83582  *  0b00000..255*1
83583  *  0b00001..255*2
83584  *  0b11111..255*231
83585  */
83586 #define SEMC_MCR_BTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
83587 /*! @} */
83588 
83589 /*! @name IOCR - IO MUX Control Register */
83590 /*! @{ */
83591 
83592 #define SEMC_IOCR_MUX_A8_MASK                    (0xFU)
83593 #define SEMC_IOCR_MUX_A8_SHIFT                   (0U)
83594 /*! MUX_A8 - SEMC_ADDR08 output selection
83595  *  0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
83596  *  0b0100..NAND CE#
83597  *  0b0101..NOR CE#
83598  *  0b0110..SRAM CE# 0
83599  *  0b0111..DBI CSX
83600  *  0b1000..SRAM CE# 1
83601  *  0b1001..SRAM CE# 2
83602  *  0b1010..SRAM CE# 3
83603  *  0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
83604  */
83605 #define SEMC_IOCR_MUX_A8(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
83606 
83607 #define SEMC_IOCR_MUX_CSX0_MASK                  (0xF0U)
83608 #define SEMC_IOCR_MUX_CSX0_SHIFT                 (4U)
83609 /*! MUX_CSX0 - SEMC_CSX0 output selection
83610  *  0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode
83611  *  0b0001..SDRAM CS1
83612  *  0b0010..SDRAM CS2
83613  *  0b0011..SDRAM CS3
83614  *  0b0100..NAND CE#
83615  *  0b0101..NOR CE#
83616  *  0b0110..SRAM CE# 0
83617  *  0b0111..DBI CSX
83618  *  0b1000..SRAM CE# 1
83619  *  0b1001..SRAM CE# 2
83620  *  0b1010..SRAM CE# 3
83621  *  0b1011-0b1111..NOR/SRAM Address bit 24 (A24)
83622  */
83623 #define SEMC_IOCR_MUX_CSX0(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
83624 
83625 #define SEMC_IOCR_MUX_CSX1_MASK                  (0xF00U)
83626 #define SEMC_IOCR_MUX_CSX1_SHIFT                 (8U)
83627 /*! MUX_CSX1 - SEMC_CSX1 output selection
83628  *  0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode
83629  *  0b0001..SDRAM CS1
83630  *  0b0010..SDRAM CS2
83631  *  0b0011..SDRAM CS3
83632  *  0b0100..NAND CE#
83633  *  0b0101..NOR CE#
83634  *  0b0110..SRAM CE# 0
83635  *  0b0111..DBI CSX
83636  *  0b1000..SRAM CE# 1
83637  *  0b1001..SRAM CE# 2
83638  *  0b1010..SRAM CE# 3
83639  *  0b1011-0b1111..NOR/SRAM Address bit 25 (A25)
83640  */
83641 #define SEMC_IOCR_MUX_CSX1(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
83642 
83643 #define SEMC_IOCR_MUX_CSX2_MASK                  (0xF000U)
83644 #define SEMC_IOCR_MUX_CSX2_SHIFT                 (12U)
83645 /*! MUX_CSX2 - SEMC_CSX2 output selection
83646  *  0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode
83647  *  0b0001..SDRAM CS1
83648  *  0b0010..SDRAM CS2
83649  *  0b0011..SDRAM CS3
83650  *  0b0100..NAND CE#
83651  *  0b0101..NOR CE#
83652  *  0b0110..SRAM CE# 0
83653  *  0b0111..DBI CSX
83654  *  0b1000..SRAM CE# 1
83655  *  0b1001..SRAM CE# 2
83656  *  0b1010..SRAM CE# 3
83657  *  0b1011-0b1111..NOR/SRAM Address bit 26 (A26)
83658  */
83659 #define SEMC_IOCR_MUX_CSX2(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
83660 
83661 #define SEMC_IOCR_MUX_CSX3_MASK                  (0xF0000U)
83662 #define SEMC_IOCR_MUX_CSX3_SHIFT                 (16U)
83663 /*! MUX_CSX3 - SEMC_CSX3 output selection
83664  *  0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
83665  *  0b0001..SDRAM CS1
83666  *  0b0010..SDRAM CS2
83667  *  0b0011..SDRAM CS3
83668  *  0b0100..NAND CE#
83669  *  0b0101..NOR CE#
83670  *  0b0110..SRAM CE# 0
83671  *  0b0111..DBI CSX
83672  *  0b1000..SRAM CE# 1
83673  *  0b1001..SRAM CE# 2
83674  *  0b1010..SRAM CE# 3
83675  *  0b1011-0b1111..NOR/SRAM Address bit 27 (A27)
83676  */
83677 #define SEMC_IOCR_MUX_CSX3(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
83678 
83679 #define SEMC_IOCR_MUX_RDY_MASK                   (0xF00000U)
83680 #define SEMC_IOCR_MUX_RDY_SHIFT                  (20U)
83681 /*! MUX_RDY - SEMC_RDY function selection
83682  *  0b0000..NAND R/B# input
83683  *  0b0001..SDRAM CS1
83684  *  0b0010..SDRAM CS2
83685  *  0b0011..SDRAM CS3
83686  *  0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
83687  *  0b0101..NOR CE#
83688  *  0b0110..SRAM CE# 0
83689  *  0b0111..DBI CSX
83690  *  0b1000..SRAM CE# 1
83691  *  0b1001..SRAM CE# 2
83692  *  0b1010..SRAM CE# 3
83693  *  0b1011-0b1111..NOR/SRAM Address bit 27
83694  */
83695 #define SEMC_IOCR_MUX_RDY(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
83696 
83697 #define SEMC_IOCR_MUX_CLKX0_MASK                 (0x3000000U)
83698 #define SEMC_IOCR_MUX_CLKX0_SHIFT                (24U)
83699 /*! MUX_CLKX0 - SEMC_CLKX0 function selection
83700  *  0b00..Keep low
83701  *  0b01..NOR clock
83702  *  0b10..SRAM clock
83703  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
83704  */
83705 #define SEMC_IOCR_MUX_CLKX0(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
83706 
83707 #define SEMC_IOCR_MUX_CLKX1_MASK                 (0xC000000U)
83708 #define SEMC_IOCR_MUX_CLKX1_SHIFT                (26U)
83709 /*! MUX_CLKX1 - SEMC_CLKX1 function selection
83710  *  0b00..Keep low
83711  *  0b01..NOR clock
83712  *  0b10..SRAM clock
83713  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
83714  */
83715 #define SEMC_IOCR_MUX_CLKX1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
83716 
83717 #define SEMC_IOCR_CLKX0_AO_MASK                  (0x10000000U)
83718 #define SEMC_IOCR_CLKX0_AO_SHIFT                 (28U)
83719 /*! CLKX0_AO - SEMC_CLKX0 Always On
83720  *  0b0..SEMC_CLKX0 is controlled by MUX_CLKX0
83721  *  0b1..SEMC_CLKX0 is always on
83722  */
83723 #define SEMC_IOCR_CLKX0_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK)
83724 
83725 #define SEMC_IOCR_CLKX1_AO_MASK                  (0x20000000U)
83726 #define SEMC_IOCR_CLKX1_AO_SHIFT                 (29U)
83727 /*! CLKX1_AO - SEMC_CLKX1 Always On
83728  *  0b0..SEMC_CLKX1 is controlled by MUX_CLKX1
83729  *  0b1..SEMC_CLKX1 is always on
83730  */
83731 #define SEMC_IOCR_CLKX1_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK)
83732 /*! @} */
83733 
83734 /*! @name BMCR0 - Bus (AXI) Master Control Register 0 */
83735 /*! @{ */
83736 
83737 #define SEMC_BMCR0_WQOS_MASK                     (0xFU)
83738 #define SEMC_BMCR0_WQOS_SHIFT                    (0U)
83739 /*! WQOS - Weight of QOS
83740  */
83741 #define SEMC_BMCR0_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
83742 
83743 #define SEMC_BMCR0_WAGE_MASK                     (0xF0U)
83744 #define SEMC_BMCR0_WAGE_SHIFT                    (4U)
83745 /*! WAGE - Weight of AGE
83746  */
83747 #define SEMC_BMCR0_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
83748 
83749 #define SEMC_BMCR0_WSH_MASK                      (0xFF00U)
83750 #define SEMC_BMCR0_WSH_SHIFT                     (8U)
83751 /*! WSH - Weight of Slave Hit without read/write switch
83752  */
83753 #define SEMC_BMCR0_WSH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
83754 
83755 #define SEMC_BMCR0_WRWS_MASK                     (0xFF0000U)
83756 #define SEMC_BMCR0_WRWS_SHIFT                    (16U)
83757 /*! WRWS - Weight of slave hit with Read/Write Switch
83758  */
83759 #define SEMC_BMCR0_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
83760 /*! @} */
83761 
83762 /*! @name BMCR1 - Bus (AXI) Master Control Register 1 */
83763 /*! @{ */
83764 
83765 #define SEMC_BMCR1_WQOS_MASK                     (0xFU)
83766 #define SEMC_BMCR1_WQOS_SHIFT                    (0U)
83767 /*! WQOS - Weight of QOS
83768  */
83769 #define SEMC_BMCR1_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
83770 
83771 #define SEMC_BMCR1_WAGE_MASK                     (0xF0U)
83772 #define SEMC_BMCR1_WAGE_SHIFT                    (4U)
83773 /*! WAGE - Weight of AGE
83774  */
83775 #define SEMC_BMCR1_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
83776 
83777 #define SEMC_BMCR1_WPH_MASK                      (0xFF00U)
83778 #define SEMC_BMCR1_WPH_SHIFT                     (8U)
83779 /*! WPH - Weight of Page Hit
83780  */
83781 #define SEMC_BMCR1_WPH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
83782 
83783 #define SEMC_BMCR1_WRWS_MASK                     (0xFF0000U)
83784 #define SEMC_BMCR1_WRWS_SHIFT                    (16U)
83785 /*! WRWS - Weight of slave hit without Read/Write Switch
83786  */
83787 #define SEMC_BMCR1_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
83788 
83789 #define SEMC_BMCR1_WBR_MASK                      (0xFF000000U)
83790 #define SEMC_BMCR1_WBR_SHIFT                     (24U)
83791 /*! WBR - Weight of Bank Rotation
83792  */
83793 #define SEMC_BMCR1_WBR(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
83794 /*! @} */
83795 
83796 /*! @name BR - Base Register 0..Base Register 8 */
83797 /*! @{ */
83798 
83799 #define SEMC_BR_VLD_MASK                         (0x1U)
83800 #define SEMC_BR_VLD_SHIFT                        (0U)
83801 /*! VLD - Valid
83802  *  0b0..The memory is invalid, can not be accessed.
83803  *  0b1..The memory is valid, can be accessed.
83804  */
83805 #define SEMC_BR_VLD(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
83806 
83807 #define SEMC_BR_MS_MASK                          (0x3EU)
83808 #define SEMC_BR_MS_SHIFT                         (1U)
83809 /*! MS - Memory size
83810  *  0b00000..4KB
83811  *  0b00001..8KB
83812  *  0b00010..16KB
83813  *  0b00011..32KB
83814  *  0b00100..64KB
83815  *  0b00101..128KB
83816  *  0b00110..256KB
83817  *  0b00111..512KB
83818  *  0b01000..1MB
83819  *  0b01001..2MB
83820  *  0b01010..4MB
83821  *  0b01011..8MB
83822  *  0b01100..16MB
83823  *  0b01101..32MB
83824  *  0b01110..64MB
83825  *  0b01111..128MB
83826  *  0b10000..256MB
83827  *  0b10001..512MB
83828  *  0b10010..1GB
83829  *  0b10011..2GB
83830  *  0b10100-0b11111..4GB
83831  */
83832 #define SEMC_BR_MS(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
83833 
83834 #define SEMC_BR_BA_MASK                          (0xFFFFF000U)
83835 #define SEMC_BR_BA_SHIFT                         (12U)
83836 /*! BA - Base Address
83837  */
83838 #define SEMC_BR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
83839 /*! @} */
83840 
83841 /* The count of SEMC_BR */
83842 #define SEMC_BR_COUNT                            (9U)
83843 
83844 /*! @name DLLCR - DLL Control Register */
83845 /*! @{ */
83846 
83847 #define SEMC_DLLCR_DLLEN_MASK                    (0x1U)
83848 #define SEMC_DLLCR_DLLEN_SHIFT                   (0U)
83849 /*! DLLEN - DLL calibration enable
83850  *  0b0..DLL calibration is disabled.
83851  *  0b1..DLL calibration is enabled.
83852  */
83853 #define SEMC_DLLCR_DLLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
83854 
83855 #define SEMC_DLLCR_DLLRESET_MASK                 (0x2U)
83856 #define SEMC_DLLCR_DLLRESET_SHIFT                (1U)
83857 /*! DLLRESET - DLL Reset
83858  *  0b0..DLL is not reset.
83859  *  0b1..DLL is reset.
83860  */
83861 #define SEMC_DLLCR_DLLRESET(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
83862 
83863 #define SEMC_DLLCR_SLVDLYTARGET_MASK             (0x78U)
83864 #define SEMC_DLLCR_SLVDLYTARGET_SHIFT            (3U)
83865 /*! SLVDLYTARGET - Delay Target for Slave
83866  */
83867 #define SEMC_DLLCR_SLVDLYTARGET(x)               (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
83868 
83869 #define SEMC_DLLCR_OVRDEN_MASK                   (0x100U)
83870 #define SEMC_DLLCR_OVRDEN_SHIFT                  (8U)
83871 /*! OVRDEN - Override Enable
83872  *  0b0..The delay cell number is not overridden.
83873  *  0b1..The delay cell number is overridden.
83874  */
83875 #define SEMC_DLLCR_OVRDEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
83876 
83877 #define SEMC_DLLCR_OVRDVAL_MASK                  (0x7E00U)
83878 #define SEMC_DLLCR_OVRDVAL_SHIFT                 (9U)
83879 /*! OVRDVAL - Override Value
83880  */
83881 #define SEMC_DLLCR_OVRDVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
83882 /*! @} */
83883 
83884 /*! @name INTEN - Interrupt Enable Register */
83885 /*! @{ */
83886 
83887 #define SEMC_INTEN_IPCMDDONEEN_MASK              (0x1U)
83888 #define SEMC_INTEN_IPCMDDONEEN_SHIFT             (0U)
83889 /*! IPCMDDONEEN - IP command done interrupt enable
83890  *  0b0..Interrupt is disabled
83891  *  0b1..Interrupt is enabled
83892  */
83893 #define SEMC_INTEN_IPCMDDONEEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
83894 
83895 #define SEMC_INTEN_IPCMDERREN_MASK               (0x2U)
83896 #define SEMC_INTEN_IPCMDERREN_SHIFT              (1U)
83897 /*! IPCMDERREN - IP command error interrupt enable
83898  *  0b0..Interrupt is disabled
83899  *  0b1..Interrupt is enabled
83900  */
83901 #define SEMC_INTEN_IPCMDERREN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
83902 
83903 #define SEMC_INTEN_AXICMDERREN_MASK              (0x4U)
83904 #define SEMC_INTEN_AXICMDERREN_SHIFT             (2U)
83905 /*! AXICMDERREN - AXI command error interrupt enable
83906  *  0b0..Interrupt is disabled
83907  *  0b1..Interrupt is enabled
83908  */
83909 #define SEMC_INTEN_AXICMDERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
83910 
83911 #define SEMC_INTEN_AXIBUSERREN_MASK              (0x8U)
83912 #define SEMC_INTEN_AXIBUSERREN_SHIFT             (3U)
83913 /*! AXIBUSERREN - AXI bus error interrupt enable
83914  *  0b0..Interrupt is disabled
83915  *  0b1..Interrupt is enabled
83916  */
83917 #define SEMC_INTEN_AXIBUSERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
83918 
83919 #define SEMC_INTEN_NDPAGEENDEN_MASK              (0x10U)
83920 #define SEMC_INTEN_NDPAGEENDEN_SHIFT             (4U)
83921 /*! NDPAGEENDEN - NAND page end interrupt enable
83922  *  0b0..Interrupt is disabled
83923  *  0b1..Interrupt is enabled
83924  */
83925 #define SEMC_INTEN_NDPAGEENDEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
83926 
83927 #define SEMC_INTEN_NDNOPENDEN_MASK               (0x20U)
83928 #define SEMC_INTEN_NDNOPENDEN_SHIFT              (5U)
83929 /*! NDNOPENDEN - NAND no pending AXI access interrupt enable
83930  *  0b0..Interrupt is disabled
83931  *  0b1..Interrupt is enabled
83932  */
83933 #define SEMC_INTEN_NDNOPENDEN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
83934 /*! @} */
83935 
83936 /*! @name INTR - Interrupt Register */
83937 /*! @{ */
83938 
83939 #define SEMC_INTR_IPCMDDONE_MASK                 (0x1U)
83940 #define SEMC_INTR_IPCMDDONE_SHIFT                (0U)
83941 /*! IPCMDDONE - IP command normal done interrupt
83942  *  0b0..IP command is not done.
83943  *  0b1..IP command is done.
83944  */
83945 #define SEMC_INTR_IPCMDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
83946 
83947 #define SEMC_INTR_IPCMDERR_MASK                  (0x2U)
83948 #define SEMC_INTR_IPCMDERR_SHIFT                 (1U)
83949 /*! IPCMDERR - IP command error done interrupt
83950  *  0b0..No IP command error.
83951  *  0b1..IP command error occurs.
83952  */
83953 #define SEMC_INTR_IPCMDERR(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
83954 
83955 #define SEMC_INTR_AXICMDERR_MASK                 (0x4U)
83956 #define SEMC_INTR_AXICMDERR_SHIFT                (2U)
83957 /*! AXICMDERR - AXI command error interrupt
83958  *  0b0..No AXI command error.
83959  *  0b1..AXI command error occurs.
83960  */
83961 #define SEMC_INTR_AXICMDERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
83962 
83963 #define SEMC_INTR_AXIBUSERR_MASK                 (0x8U)
83964 #define SEMC_INTR_AXIBUSERR_SHIFT                (3U)
83965 /*! AXIBUSERR - AXI bus error interrupt
83966  *  0b0..No AXI bus error.
83967  *  0b1..AXI bus error occurs.
83968  */
83969 #define SEMC_INTR_AXIBUSERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
83970 
83971 #define SEMC_INTR_NDPAGEEND_MASK                 (0x10U)
83972 #define SEMC_INTR_NDPAGEEND_SHIFT                (4U)
83973 /*! NDPAGEEND - NAND page end interrupt
83974  *  0b0..The last address of main space in the NAND is not written by AXI command.
83975  *  0b1..The last address of main space in the NAND is written by AXI command.
83976  */
83977 #define SEMC_INTR_NDPAGEEND(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
83978 
83979 #define SEMC_INTR_NDNOPEND_MASK                  (0x20U)
83980 #define SEMC_INTR_NDNOPEND_SHIFT                 (5U)
83981 /*! NDNOPEND - NAND no pending AXI write transaction interrupt
83982  *  0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue.
83983  *  0b1..All NAND AXI write pending transactions are finished.
83984  */
83985 #define SEMC_INTR_NDNOPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
83986 /*! @} */
83987 
83988 /*! @name SDRAMCR0 - SDRAM Control Register 0 */
83989 /*! @{ */
83990 
83991 #define SEMC_SDRAMCR0_PS_MASK                    (0x3U)
83992 #define SEMC_SDRAMCR0_PS_SHIFT                   (0U)
83993 /*! PS - Port Size
83994  *  0b00..8bit
83995  *  0b01..16bit
83996  *  0b10..32bit
83997  *  0b11..Reserved
83998  */
83999 #define SEMC_SDRAMCR0_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
84000 
84001 #define SEMC_SDRAMCR0_BL_MASK                    (0x70U)
84002 #define SEMC_SDRAMCR0_BL_SHIFT                   (4U)
84003 /*! BL - Burst Length
84004  *  0b000..1
84005  *  0b001..2
84006  *  0b010..4
84007  *  0b011..8
84008  *  0b100..8
84009  *  0b101..8
84010  *  0b110..8
84011  *  0b111..8
84012  */
84013 #define SEMC_SDRAMCR0_BL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
84014 
84015 #define SEMC_SDRAMCR0_COL8_MASK                  (0x80U)
84016 #define SEMC_SDRAMCR0_COL8_SHIFT                 (7U)
84017 /*! COL8 - Column 8 selection
84018  *  0b0..Column address bit number is decided by COL field.
84019  *  0b1..Column address bit number is 8. COL field is ignored.
84020  */
84021 #define SEMC_SDRAMCR0_COL8(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
84022 
84023 #define SEMC_SDRAMCR0_COL_MASK                   (0x300U)
84024 #define SEMC_SDRAMCR0_COL_SHIFT                  (8U)
84025 /*! COL - Column address bit number
84026  *  0b00..12
84027  *  0b01..11
84028  *  0b10..10
84029  *  0b11..9
84030  */
84031 #define SEMC_SDRAMCR0_COL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
84032 
84033 #define SEMC_SDRAMCR0_CL_MASK                    (0xC00U)
84034 #define SEMC_SDRAMCR0_CL_SHIFT                   (10U)
84035 /*! CL - CAS Latency
84036  *  0b00..1
84037  *  0b01..1
84038  *  0b10..2
84039  *  0b11..3
84040  */
84041 #define SEMC_SDRAMCR0_CL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
84042 
84043 #define SEMC_SDRAMCR0_BANK2_MASK                 (0x4000U)
84044 #define SEMC_SDRAMCR0_BANK2_SHIFT                (14U)
84045 /*! BANK2 - 2 Bank selection bit
84046  *  0b0..SDRAM device has 4 banks.
84047  *  0b1..SDRAM device has 2 banks.
84048  */
84049 #define SEMC_SDRAMCR0_BANK2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
84050 /*! @} */
84051 
84052 /*! @name SDRAMCR1 - SDRAM Control Register 1 */
84053 /*! @{ */
84054 
84055 #define SEMC_SDRAMCR1_PRE2ACT_MASK               (0xFU)
84056 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT              (0U)
84057 /*! PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time
84058  */
84059 #define SEMC_SDRAMCR1_PRE2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
84060 
84061 #define SEMC_SDRAMCR1_ACT2RW_MASK                (0xF0U)
84062 #define SEMC_SDRAMCR1_ACT2RW_SHIFT               (4U)
84063 /*! ACT2RW - ACTIVE to READ/WRITE delay
84064  */
84065 #define SEMC_SDRAMCR1_ACT2RW(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
84066 
84067 #define SEMC_SDRAMCR1_RFRC_MASK                  (0x1F00U)
84068 #define SEMC_SDRAMCR1_RFRC_SHIFT                 (8U)
84069 /*! RFRC - REFRESH recovery time
84070  */
84071 #define SEMC_SDRAMCR1_RFRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
84072 
84073 #define SEMC_SDRAMCR1_WRC_MASK                   (0xE000U)
84074 #define SEMC_SDRAMCR1_WRC_SHIFT                  (13U)
84075 /*! WRC - WRITE recovery time
84076  */
84077 #define SEMC_SDRAMCR1_WRC(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
84078 
84079 #define SEMC_SDRAMCR1_CKEOFF_MASK                (0xF0000U)
84080 #define SEMC_SDRAMCR1_CKEOFF_SHIFT               (16U)
84081 /*! CKEOFF - CKE off minimum time
84082  */
84083 #define SEMC_SDRAMCR1_CKEOFF(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
84084 
84085 #define SEMC_SDRAMCR1_ACT2PRE_MASK               (0xF00000U)
84086 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT              (20U)
84087 /*! ACT2PRE - ACTIVE to PRECHARGE minimum time
84088  */
84089 #define SEMC_SDRAMCR1_ACT2PRE(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
84090 /*! @} */
84091 
84092 /*! @name SDRAMCR2 - SDRAM Control Register 2 */
84093 /*! @{ */
84094 
84095 #define SEMC_SDRAMCR2_SRRC_MASK                  (0xFFU)
84096 #define SEMC_SDRAMCR2_SRRC_SHIFT                 (0U)
84097 /*! SRRC - SELF REFRESH recovery time
84098  */
84099 #define SEMC_SDRAMCR2_SRRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
84100 
84101 #define SEMC_SDRAMCR2_REF2REF_MASK               (0xFF00U)
84102 #define SEMC_SDRAMCR2_REF2REF_SHIFT              (8U)
84103 /*! REF2REF - REFRESH to REFRESH delay
84104  */
84105 #define SEMC_SDRAMCR2_REF2REF(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
84106 
84107 #define SEMC_SDRAMCR2_ACT2ACT_MASK               (0xFF0000U)
84108 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT              (16U)
84109 /*! ACT2ACT - ACTIVE to ACTIVE delay
84110  */
84111 #define SEMC_SDRAMCR2_ACT2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
84112 
84113 #define SEMC_SDRAMCR2_ITO_MASK                   (0xFF000000U)
84114 #define SEMC_SDRAMCR2_ITO_SHIFT                  (24U)
84115 /*! ITO - SDRAM idle timeout
84116  *  0b00000000..IDLE timeout period is 256*Prescale period.
84117  *  0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
84118  */
84119 #define SEMC_SDRAMCR2_ITO(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
84120 /*! @} */
84121 
84122 /*! @name SDRAMCR3 - SDRAM Control Register 3 */
84123 /*! @{ */
84124 
84125 #define SEMC_SDRAMCR3_REN_MASK                   (0x1U)
84126 #define SEMC_SDRAMCR3_REN_SHIFT                  (0U)
84127 /*! REN - Refresh enable
84128  *  0b0..The SEMC does not send AUTO REFRESH command automatically
84129  *  0b1..The SEMC sends AUTO REFRESH command automatically
84130  */
84131 #define SEMC_SDRAMCR3_REN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
84132 
84133 #define SEMC_SDRAMCR3_REBL_MASK                  (0xEU)
84134 #define SEMC_SDRAMCR3_REBL_SHIFT                 (1U)
84135 /*! REBL - Refresh burst length
84136  *  0b000..1
84137  *  0b001..2
84138  *  0b010..3
84139  *  0b011..4
84140  *  0b100..5
84141  *  0b101..6
84142  *  0b110..7
84143  *  0b111..8
84144  */
84145 #define SEMC_SDRAMCR3_REBL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
84146 
84147 #define SEMC_SDRAMCR3_PRESCALE_MASK              (0xFF00U)
84148 #define SEMC_SDRAMCR3_PRESCALE_SHIFT             (8U)
84149 /*! PRESCALE - Prescaler period
84150  *  0b00000000..(256*16+1) clock cycles
84151  *  0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
84152  */
84153 #define SEMC_SDRAMCR3_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
84154 
84155 #define SEMC_SDRAMCR3_RT_MASK                    (0xFF0000U)
84156 #define SEMC_SDRAMCR3_RT_SHIFT                   (16U)
84157 /*! RT - Refresh timer period
84158  *  0b00000000..(256+1)*(Prescaler period)
84159  *  0b00000001-0b11111111..(RT+1)*(Prescaler period)
84160  */
84161 #define SEMC_SDRAMCR3_RT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
84162 
84163 #define SEMC_SDRAMCR3_UT_MASK                    (0xFF000000U)
84164 #define SEMC_SDRAMCR3_UT_SHIFT                   (24U)
84165 /*! UT - Urgent refresh threshold
84166  *  0b00000000..256*(Prescaler period)
84167  *  0b00000001-0b11111111..UT*(Prescaler period)
84168  */
84169 #define SEMC_SDRAMCR3_UT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
84170 /*! @} */
84171 
84172 /*! @name NANDCR0 - NAND Control Register 0 */
84173 /*! @{ */
84174 
84175 #define SEMC_NANDCR0_PS_MASK                     (0x1U)
84176 #define SEMC_NANDCR0_PS_SHIFT                    (0U)
84177 /*! PS - Port Size
84178  *  0b0..8bit
84179  *  0b1..16bit
84180  */
84181 #define SEMC_NANDCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
84182 
84183 #define SEMC_NANDCR0_SYNCEN_MASK                 (0x2U)
84184 #define SEMC_NANDCR0_SYNCEN_SHIFT                (1U)
84185 /*! SYNCEN - Synchronous Mode Enable
84186  *  0b0..Asynchronous mode is enabled.
84187  *  0b1..Synchronous mode is enabled.
84188  */
84189 #define SEMC_NANDCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
84190 
84191 #define SEMC_NANDCR0_BL_MASK                     (0x70U)
84192 #define SEMC_NANDCR0_BL_SHIFT                    (4U)
84193 /*! BL - Burst Length
84194  *  0b000..1
84195  *  0b001..2
84196  *  0b010..4
84197  *  0b011..8
84198  *  0b100..16
84199  *  0b101..32
84200  *  0b110..64
84201  *  0b111..64
84202  */
84203 #define SEMC_NANDCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
84204 
84205 #define SEMC_NANDCR0_EDO_MASK                    (0x80U)
84206 #define SEMC_NANDCR0_EDO_SHIFT                   (7U)
84207 /*! EDO - EDO mode enabled
84208  *  0b0..EDO mode disabled
84209  *  0b1..EDO mode enabled
84210  */
84211 #define SEMC_NANDCR0_EDO(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
84212 
84213 #define SEMC_NANDCR0_COL_MASK                    (0x700U)
84214 #define SEMC_NANDCR0_COL_SHIFT                   (8U)
84215 /*! COL - Column address bit number
84216  *  0b000..16
84217  *  0b001..15
84218  *  0b010..14
84219  *  0b011..13
84220  *  0b100..12
84221  *  0b101..11
84222  *  0b110..10
84223  *  0b111..9
84224  */
84225 #define SEMC_NANDCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
84226 /*! @} */
84227 
84228 /*! @name NANDCR1 - NAND Control Register 1 */
84229 /*! @{ */
84230 
84231 #define SEMC_NANDCR1_CES_MASK                    (0xFU)
84232 #define SEMC_NANDCR1_CES_SHIFT                   (0U)
84233 /*! CES - CE# setup time
84234  */
84235 #define SEMC_NANDCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
84236 
84237 #define SEMC_NANDCR1_CEH_MASK                    (0xF0U)
84238 #define SEMC_NANDCR1_CEH_SHIFT                   (4U)
84239 /*! CEH - CE# hold time
84240  */
84241 #define SEMC_NANDCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
84242 
84243 #define SEMC_NANDCR1_WEL_MASK                    (0xF00U)
84244 #define SEMC_NANDCR1_WEL_SHIFT                   (8U)
84245 /*! WEL - WE# low time
84246  */
84247 #define SEMC_NANDCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
84248 
84249 #define SEMC_NANDCR1_WEH_MASK                    (0xF000U)
84250 #define SEMC_NANDCR1_WEH_SHIFT                   (12U)
84251 /*! WEH - WE# high time
84252  */
84253 #define SEMC_NANDCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
84254 
84255 #define SEMC_NANDCR1_REL_MASK                    (0xF0000U)
84256 #define SEMC_NANDCR1_REL_SHIFT                   (16U)
84257 /*! REL - RE# low time
84258  */
84259 #define SEMC_NANDCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
84260 
84261 #define SEMC_NANDCR1_REH_MASK                    (0xF00000U)
84262 #define SEMC_NANDCR1_REH_SHIFT                   (20U)
84263 /*! REH - RE# high time
84264  */
84265 #define SEMC_NANDCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
84266 
84267 #define SEMC_NANDCR1_TA_MASK                     (0xF000000U)
84268 #define SEMC_NANDCR1_TA_SHIFT                    (24U)
84269 /*! TA - Turnaround time
84270  */
84271 #define SEMC_NANDCR1_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
84272 
84273 #define SEMC_NANDCR1_CEITV_MASK                  (0xF0000000U)
84274 #define SEMC_NANDCR1_CEITV_SHIFT                 (28U)
84275 /*! CEITV - CE# interval time
84276  */
84277 #define SEMC_NANDCR1_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
84278 /*! @} */
84279 
84280 /*! @name NANDCR2 - NAND Control Register 2 */
84281 /*! @{ */
84282 
84283 #define SEMC_NANDCR2_TWHR_MASK                   (0x3FU)
84284 #define SEMC_NANDCR2_TWHR_SHIFT                  (0U)
84285 /*! TWHR - WE# high to RE# low time
84286  */
84287 #define SEMC_NANDCR2_TWHR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
84288 
84289 #define SEMC_NANDCR2_TRHW_MASK                   (0xFC0U)
84290 #define SEMC_NANDCR2_TRHW_SHIFT                  (6U)
84291 /*! TRHW - RE# high to WE# low time
84292  */
84293 #define SEMC_NANDCR2_TRHW(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
84294 
84295 #define SEMC_NANDCR2_TADL_MASK                   (0x3F000U)
84296 #define SEMC_NANDCR2_TADL_SHIFT                  (12U)
84297 /*! TADL - Address cycle to data loading time
84298  */
84299 #define SEMC_NANDCR2_TADL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
84300 
84301 #define SEMC_NANDCR2_TRR_MASK                    (0xFC0000U)
84302 #define SEMC_NANDCR2_TRR_SHIFT                   (18U)
84303 /*! TRR - Ready to RE# low time
84304  */
84305 #define SEMC_NANDCR2_TRR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
84306 
84307 #define SEMC_NANDCR2_TWB_MASK                    (0x3F000000U)
84308 #define SEMC_NANDCR2_TWB_SHIFT                   (24U)
84309 /*! TWB - WE# high to busy time
84310  */
84311 #define SEMC_NANDCR2_TWB(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
84312 /*! @} */
84313 
84314 /*! @name NANDCR3 - NAND Control Register 3 */
84315 /*! @{ */
84316 
84317 #define SEMC_NANDCR3_NDOPT1_MASK                 (0x1U)
84318 #define SEMC_NANDCR3_NDOPT1_SHIFT                (0U)
84319 /*! NDOPT1 - NAND option bit 1
84320  */
84321 #define SEMC_NANDCR3_NDOPT1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
84322 
84323 #define SEMC_NANDCR3_NDOPT2_MASK                 (0x2U)
84324 #define SEMC_NANDCR3_NDOPT2_SHIFT                (1U)
84325 /*! NDOPT2 - NAND option bit 2
84326  */
84327 #define SEMC_NANDCR3_NDOPT2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
84328 
84329 #define SEMC_NANDCR3_NDOPT3_MASK                 (0x4U)
84330 #define SEMC_NANDCR3_NDOPT3_SHIFT                (2U)
84331 /*! NDOPT3 - NAND option bit 3
84332  */
84333 #define SEMC_NANDCR3_NDOPT3(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
84334 
84335 #define SEMC_NANDCR3_CLE_MASK                    (0x8U)
84336 #define SEMC_NANDCR3_CLE_SHIFT                   (3U)
84337 /*! CLE - NAND CLE Option
84338  */
84339 #define SEMC_NANDCR3_CLE(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
84340 
84341 #define SEMC_NANDCR3_RDS_MASK                    (0xF0000U)
84342 #define SEMC_NANDCR3_RDS_SHIFT                   (16U)
84343 /*! RDS - Read Data Setup time
84344  */
84345 #define SEMC_NANDCR3_RDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
84346 
84347 #define SEMC_NANDCR3_RDH_MASK                    (0xF00000U)
84348 #define SEMC_NANDCR3_RDH_SHIFT                   (20U)
84349 /*! RDH - Read Data Hold time
84350  */
84351 #define SEMC_NANDCR3_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
84352 
84353 #define SEMC_NANDCR3_WDS_MASK                    (0xF000000U)
84354 #define SEMC_NANDCR3_WDS_SHIFT                   (24U)
84355 /*! WDS - Write Data Setup time
84356  */
84357 #define SEMC_NANDCR3_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
84358 
84359 #define SEMC_NANDCR3_WDH_MASK                    (0xF0000000U)
84360 #define SEMC_NANDCR3_WDH_SHIFT                   (28U)
84361 /*! WDH - Write Data Hold time
84362  */
84363 #define SEMC_NANDCR3_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
84364 /*! @} */
84365 
84366 /*! @name NORCR0 - NOR Control Register 0 */
84367 /*! @{ */
84368 
84369 #define SEMC_NORCR0_PS_MASK                      (0x1U)
84370 #define SEMC_NORCR0_PS_SHIFT                     (0U)
84371 /*! PS - Port Size
84372  *  0b0..8bit
84373  *  0b1..16bit
84374  */
84375 #define SEMC_NORCR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
84376 
84377 #define SEMC_NORCR0_SYNCEN_MASK                  (0x2U)
84378 #define SEMC_NORCR0_SYNCEN_SHIFT                 (1U)
84379 /*! SYNCEN - Synchronous Mode Enable
84380  *  0b0..Asynchronous mode is enabled.
84381  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
84382  */
84383 #define SEMC_NORCR0_SYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
84384 
84385 #define SEMC_NORCR0_BL_MASK                      (0x70U)
84386 #define SEMC_NORCR0_BL_SHIFT                     (4U)
84387 /*! BL - Burst Length
84388  *  0b000..1
84389  *  0b001..2
84390  *  0b010..4
84391  *  0b011..8
84392  *  0b100..16
84393  *  0b101..32
84394  *  0b110..64
84395  *  0b111..64
84396  */
84397 #define SEMC_NORCR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
84398 
84399 #define SEMC_NORCR0_AM_MASK                      (0x300U)
84400 #define SEMC_NORCR0_AM_SHIFT                     (8U)
84401 /*! AM - Address Mode
84402  *  0b00..Address/Data MUX mode (ADMUX)
84403  *  0b01..Advanced Address/Data MUX mode (AADM)
84404  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
84405  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
84406  */
84407 #define SEMC_NORCR0_AM(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
84408 
84409 #define SEMC_NORCR0_ADVP_MASK                    (0x400U)
84410 #define SEMC_NORCR0_ADVP_SHIFT                   (10U)
84411 /*! ADVP - ADV# Polarity
84412  *  0b0..ADV# is active low.
84413  *  0b1..ADV# is active high.
84414  */
84415 #define SEMC_NORCR0_ADVP(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
84416 
84417 #define SEMC_NORCR0_ADVH_MASK                    (0x800U)
84418 #define SEMC_NORCR0_ADVH_SHIFT                   (11U)
84419 /*! ADVH - ADV# level control during address hold state
84420  *  0b0..ADV# is high during address hold state.
84421  *  0b1..ADV# is low during address hold state.
84422  */
84423 #define SEMC_NORCR0_ADVH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
84424 
84425 #define SEMC_NORCR0_COL_MASK                     (0xF000U)
84426 #define SEMC_NORCR0_COL_SHIFT                    (12U)
84427 /*! COL - Column Address bit width
84428  *  0b0000..12 Bits
84429  *  0b0001..11 Bits
84430  *  0b0010..10 Bits
84431  *  0b0011..9 Bits
84432  *  0b0100..8 Bits
84433  *  0b0101..7 Bits
84434  *  0b0110..6 Bits
84435  *  0b0111..5 Bits
84436  *  0b1000..4 Bits
84437  *  0b1001..3 Bits
84438  *  0b1010..2 Bits
84439  *  0b1011..12 Bits
84440  *  0b1100..12 Bits
84441  *  0b1101..12 Bits
84442  *  0b1110..12 Bits
84443  *  0b1111..12 Bits
84444  */
84445 #define SEMC_NORCR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
84446 /*! @} */
84447 
84448 /*! @name NORCR1 - NOR Control Register 1 */
84449 /*! @{ */
84450 
84451 #define SEMC_NORCR1_CES_MASK                     (0xFU)
84452 #define SEMC_NORCR1_CES_SHIFT                    (0U)
84453 /*! CES - CE setup time
84454  */
84455 #define SEMC_NORCR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
84456 
84457 #define SEMC_NORCR1_CEH_MASK                     (0xF0U)
84458 #define SEMC_NORCR1_CEH_SHIFT                    (4U)
84459 /*! CEH - CE hold time
84460  */
84461 #define SEMC_NORCR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
84462 
84463 #define SEMC_NORCR1_AS_MASK                      (0xF00U)
84464 #define SEMC_NORCR1_AS_SHIFT                     (8U)
84465 /*! AS - Address setup time
84466  */
84467 #define SEMC_NORCR1_AS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
84468 
84469 #define SEMC_NORCR1_AH_MASK                      (0xF000U)
84470 #define SEMC_NORCR1_AH_SHIFT                     (12U)
84471 /*! AH - Address hold time
84472  */
84473 #define SEMC_NORCR1_AH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
84474 
84475 #define SEMC_NORCR1_WEL_MASK                     (0xF0000U)
84476 #define SEMC_NORCR1_WEL_SHIFT                    (16U)
84477 /*! WEL - WE low time
84478  */
84479 #define SEMC_NORCR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
84480 
84481 #define SEMC_NORCR1_WEH_MASK                     (0xF00000U)
84482 #define SEMC_NORCR1_WEH_SHIFT                    (20U)
84483 /*! WEH - WE high time
84484  */
84485 #define SEMC_NORCR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
84486 
84487 #define SEMC_NORCR1_REL_MASK                     (0xF000000U)
84488 #define SEMC_NORCR1_REL_SHIFT                    (24U)
84489 /*! REL - RE low time
84490  */
84491 #define SEMC_NORCR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
84492 
84493 #define SEMC_NORCR1_REH_MASK                     (0xF0000000U)
84494 #define SEMC_NORCR1_REH_SHIFT                    (28U)
84495 /*! REH - RE high time
84496  */
84497 #define SEMC_NORCR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
84498 /*! @} */
84499 
84500 /*! @name NORCR2 - NOR Control Register 2 */
84501 /*! @{ */
84502 
84503 #define SEMC_NORCR2_TA_MASK                      (0xF00U)
84504 #define SEMC_NORCR2_TA_SHIFT                     (8U)
84505 /*! TA - Turnaround time
84506  */
84507 #define SEMC_NORCR2_TA(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
84508 
84509 #define SEMC_NORCR2_AWDH_MASK                    (0xF000U)
84510 #define SEMC_NORCR2_AWDH_SHIFT                   (12U)
84511 /*! AWDH - Address to write data hold time
84512  */
84513 #define SEMC_NORCR2_AWDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
84514 
84515 #define SEMC_NORCR2_LC_MASK                      (0xF0000U)
84516 #define SEMC_NORCR2_LC_SHIFT                     (16U)
84517 /*! LC - Latency count
84518  */
84519 #define SEMC_NORCR2_LC(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
84520 
84521 #define SEMC_NORCR2_RD_MASK                      (0xF00000U)
84522 #define SEMC_NORCR2_RD_SHIFT                     (20U)
84523 /*! RD - Read time
84524  */
84525 #define SEMC_NORCR2_RD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
84526 
84527 #define SEMC_NORCR2_CEITV_MASK                   (0xF000000U)
84528 #define SEMC_NORCR2_CEITV_SHIFT                  (24U)
84529 /*! CEITV - CE# interval time
84530  */
84531 #define SEMC_NORCR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
84532 
84533 #define SEMC_NORCR2_RDH_MASK                     (0xF0000000U)
84534 #define SEMC_NORCR2_RDH_SHIFT                    (28U)
84535 /*! RDH - Read hold time
84536  */
84537 #define SEMC_NORCR2_RDH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
84538 /*! @} */
84539 
84540 /*! @name NORCR3 - NOR Control Register 3 */
84541 /*! @{ */
84542 
84543 #define SEMC_NORCR3_ASSR_MASK                    (0xFU)
84544 #define SEMC_NORCR3_ASSR_SHIFT                   (0U)
84545 /*! ASSR - Address setup time for SYNC read
84546  */
84547 #define SEMC_NORCR3_ASSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
84548 
84549 #define SEMC_NORCR3_AHSR_MASK                    (0xF0U)
84550 #define SEMC_NORCR3_AHSR_SHIFT                   (4U)
84551 /*! AHSR - Address hold time for SYNC read
84552  */
84553 #define SEMC_NORCR3_AHSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
84554 /*! @} */
84555 
84556 /*! @name SRAMCR0 - SRAM Control Register 0 */
84557 /*! @{ */
84558 
84559 #define SEMC_SRAMCR0_PS_MASK                     (0x1U)
84560 #define SEMC_SRAMCR0_PS_SHIFT                    (0U)
84561 /*! PS - Port Size
84562  *  0b0..8bit
84563  *  0b1..16bit
84564  */
84565 #define SEMC_SRAMCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
84566 
84567 #define SEMC_SRAMCR0_SYNCEN_MASK                 (0x2U)
84568 #define SEMC_SRAMCR0_SYNCEN_SHIFT                (1U)
84569 /*! SYNCEN - Synchronous Mode Enable
84570  *  0b0..Asynchronous mode is enabled.
84571  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
84572  */
84573 #define SEMC_SRAMCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
84574 
84575 #define SEMC_SRAMCR0_WAITEN_MASK                 (0x4U)
84576 #define SEMC_SRAMCR0_WAITEN_SHIFT                (2U)
84577 /*! WAITEN - Wait Enable
84578  *  0b0..The SEMC does not monitor wait pin.
84579  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
84580  */
84581 #define SEMC_SRAMCR0_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK)
84582 
84583 #define SEMC_SRAMCR0_WAITSP_MASK                 (0x8U)
84584 #define SEMC_SRAMCR0_WAITSP_SHIFT                (3U)
84585 /*! WAITSP - Wait Sample
84586  *  0b0..Wait pin is directly used by the SEMC.
84587  *  0b1..Wait pin is sampled by internal clock before it is used.
84588  */
84589 #define SEMC_SRAMCR0_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK)
84590 
84591 #define SEMC_SRAMCR0_BL_MASK                     (0x70U)
84592 #define SEMC_SRAMCR0_BL_SHIFT                    (4U)
84593 /*! BL - Burst Length
84594  *  0b000..1
84595  *  0b001..2
84596  *  0b010..4
84597  *  0b011..8
84598  *  0b100..16
84599  *  0b101..32
84600  *  0b110..64
84601  *  0b111..64
84602  */
84603 #define SEMC_SRAMCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
84604 
84605 #define SEMC_SRAMCR0_AM_MASK                     (0x300U)
84606 #define SEMC_SRAMCR0_AM_SHIFT                    (8U)
84607 /*! AM - Address Mode
84608  *  0b00..Address/Data MUX mode (ADMUX)
84609  *  0b01..Advanced Address/Data MUX mode (AADM)
84610  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
84611  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
84612  */
84613 #define SEMC_SRAMCR0_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
84614 
84615 #define SEMC_SRAMCR0_ADVP_MASK                   (0x400U)
84616 #define SEMC_SRAMCR0_ADVP_SHIFT                  (10U)
84617 /*! ADVP - ADV# polarity
84618  *  0b0..ADV# is active low.
84619  *  0b1..ADV# is active high.
84620  */
84621 #define SEMC_SRAMCR0_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
84622 
84623 #define SEMC_SRAMCR0_ADVH_MASK                   (0x800U)
84624 #define SEMC_SRAMCR0_ADVH_SHIFT                  (11U)
84625 /*! ADVH - ADV# level control during address hold state
84626  *  0b0..ADV# is high during address hold state.
84627  *  0b1..ADV# is low during address hold state.
84628  */
84629 #define SEMC_SRAMCR0_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
84630 
84631 #define SEMC_SRAMCR0_COL_MASK                    (0xF000U)
84632 #define SEMC_SRAMCR0_COL_SHIFT                   (12U)
84633 /*! COL - Column Address bit width
84634  *  0b0000..12 Bits
84635  *  0b0001..11 Bits
84636  *  0b0010..10 Bits
84637  *  0b0011..9 Bits
84638  *  0b0100..8 Bits
84639  *  0b0101..7 Bits
84640  *  0b0110..6 Bits
84641  *  0b0111..5 Bits
84642  *  0b1000..4 Bits
84643  *  0b1001..3 Bits
84644  *  0b1010..2 Bits
84645  *  0b1011..12 Bits
84646  *  0b1100..12 Bits
84647  *  0b1101..12 Bits
84648  *  0b1110..12 Bits
84649  *  0b1111..12 Bits
84650  */
84651 #define SEMC_SRAMCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
84652 /*! @} */
84653 
84654 /*! @name SRAMCR1 - SRAM Control Register 1 */
84655 /*! @{ */
84656 
84657 #define SEMC_SRAMCR1_CES_MASK                    (0xFU)
84658 #define SEMC_SRAMCR1_CES_SHIFT                   (0U)
84659 /*! CES - CE setup time
84660  */
84661 #define SEMC_SRAMCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
84662 
84663 #define SEMC_SRAMCR1_CEH_MASK                    (0xF0U)
84664 #define SEMC_SRAMCR1_CEH_SHIFT                   (4U)
84665 /*! CEH - CE hold time
84666  */
84667 #define SEMC_SRAMCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
84668 
84669 #define SEMC_SRAMCR1_AS_MASK                     (0xF00U)
84670 #define SEMC_SRAMCR1_AS_SHIFT                    (8U)
84671 /*! AS - Address setup time
84672  */
84673 #define SEMC_SRAMCR1_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
84674 
84675 #define SEMC_SRAMCR1_AH_MASK                     (0xF000U)
84676 #define SEMC_SRAMCR1_AH_SHIFT                    (12U)
84677 /*! AH - Address hold time
84678  */
84679 #define SEMC_SRAMCR1_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
84680 
84681 #define SEMC_SRAMCR1_WEL_MASK                    (0xF0000U)
84682 #define SEMC_SRAMCR1_WEL_SHIFT                   (16U)
84683 /*! WEL - WE low time
84684  */
84685 #define SEMC_SRAMCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
84686 
84687 #define SEMC_SRAMCR1_WEH_MASK                    (0xF00000U)
84688 #define SEMC_SRAMCR1_WEH_SHIFT                   (20U)
84689 /*! WEH - WE high time
84690  */
84691 #define SEMC_SRAMCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
84692 
84693 #define SEMC_SRAMCR1_REL_MASK                    (0xF000000U)
84694 #define SEMC_SRAMCR1_REL_SHIFT                   (24U)
84695 /*! REL - RE low time
84696  */
84697 #define SEMC_SRAMCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
84698 
84699 #define SEMC_SRAMCR1_REH_MASK                    (0xF0000000U)
84700 #define SEMC_SRAMCR1_REH_SHIFT                   (28U)
84701 /*! REH - RE high time
84702  */
84703 #define SEMC_SRAMCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
84704 /*! @} */
84705 
84706 /*! @name SRAMCR2 - SRAM Control Register 2 */
84707 /*! @{ */
84708 
84709 #define SEMC_SRAMCR2_WDS_MASK                    (0xFU)
84710 #define SEMC_SRAMCR2_WDS_SHIFT                   (0U)
84711 /*! WDS - Write Data setup time
84712  */
84713 #define SEMC_SRAMCR2_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
84714 
84715 #define SEMC_SRAMCR2_WDH_MASK                    (0xF0U)
84716 #define SEMC_SRAMCR2_WDH_SHIFT                   (4U)
84717 /*! WDH - Write Data hold time
84718  */
84719 #define SEMC_SRAMCR2_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
84720 
84721 #define SEMC_SRAMCR2_TA_MASK                     (0xF00U)
84722 #define SEMC_SRAMCR2_TA_SHIFT                    (8U)
84723 /*! TA - Turnaround time
84724  */
84725 #define SEMC_SRAMCR2_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
84726 
84727 #define SEMC_SRAMCR2_AWDH_MASK                   (0xF000U)
84728 #define SEMC_SRAMCR2_AWDH_SHIFT                  (12U)
84729 /*! AWDH - Address to write data hold time
84730  */
84731 #define SEMC_SRAMCR2_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
84732 
84733 #define SEMC_SRAMCR2_LC_MASK                     (0xF0000U)
84734 #define SEMC_SRAMCR2_LC_SHIFT                    (16U)
84735 /*! LC - Latency count
84736  */
84737 #define SEMC_SRAMCR2_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
84738 
84739 #define SEMC_SRAMCR2_RD_MASK                     (0xF00000U)
84740 #define SEMC_SRAMCR2_RD_SHIFT                    (20U)
84741 /*! RD - Read time
84742  */
84743 #define SEMC_SRAMCR2_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
84744 
84745 #define SEMC_SRAMCR2_CEITV_MASK                  (0xF000000U)
84746 #define SEMC_SRAMCR2_CEITV_SHIFT                 (24U)
84747 /*! CEITV - CE# interval time
84748  */
84749 #define SEMC_SRAMCR2_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
84750 
84751 #define SEMC_SRAMCR2_RDH_MASK                    (0xF0000000U)
84752 #define SEMC_SRAMCR2_RDH_SHIFT                   (28U)
84753 /*! RDH - Read hold time
84754  */
84755 #define SEMC_SRAMCR2_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
84756 /*! @} */
84757 
84758 /*! @name DBICR0 - DBI-B Control Register 0 */
84759 /*! @{ */
84760 
84761 #define SEMC_DBICR0_PS_MASK                      (0x1U)
84762 #define SEMC_DBICR0_PS_SHIFT                     (0U)
84763 /*! PS - Port Size
84764  *  0b0..8bit
84765  *  0b1..16bit
84766  */
84767 #define SEMC_DBICR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
84768 
84769 #define SEMC_DBICR0_BL_MASK                      (0x70U)
84770 #define SEMC_DBICR0_BL_SHIFT                     (4U)
84771 /*! BL - Burst Length
84772  *  0b000..1
84773  *  0b001..2
84774  *  0b010..4
84775  *  0b011..8
84776  *  0b100..16
84777  *  0b101..32
84778  *  0b110..64
84779  *  0b111..64
84780  */
84781 #define SEMC_DBICR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
84782 
84783 #define SEMC_DBICR0_COL_MASK                     (0xF000U)
84784 #define SEMC_DBICR0_COL_SHIFT                    (12U)
84785 /*! COL - Column Address bit width
84786  *  0b0000..12 Bits
84787  *  0b0001..11 Bits
84788  *  0b0010..10 Bits
84789  *  0b0011..9 Bits
84790  *  0b0100..8 Bits
84791  *  0b0101..7 Bits
84792  *  0b0110..6 Bits
84793  *  0b0111..5 Bits
84794  *  0b1000..4 Bits
84795  *  0b1001..3 Bits
84796  *  0b1010..2 Bits
84797  *  0b1011..12 Bits
84798  *  0b1100..12 Bits
84799  *  0b1101..12 Bits
84800  *  0b1110..12 Bits
84801  *  0b1111..12 Bits
84802  */
84803 #define SEMC_DBICR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
84804 /*! @} */
84805 
84806 /*! @name DBICR1 - DBI-B Control Register 1 */
84807 /*! @{ */
84808 
84809 #define SEMC_DBICR1_CES_MASK                     (0xFU)
84810 #define SEMC_DBICR1_CES_SHIFT                    (0U)
84811 /*! CES - CSX Setup Time
84812  */
84813 #define SEMC_DBICR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
84814 
84815 #define SEMC_DBICR1_CEH_MASK                     (0xF0U)
84816 #define SEMC_DBICR1_CEH_SHIFT                    (4U)
84817 /*! CEH - CSX Hold Time
84818  */
84819 #define SEMC_DBICR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
84820 
84821 #define SEMC_DBICR1_WEL_MASK                     (0xF00U)
84822 #define SEMC_DBICR1_WEL_SHIFT                    (8U)
84823 /*! WEL - WRX Low Time
84824  */
84825 #define SEMC_DBICR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
84826 
84827 #define SEMC_DBICR1_WEH_MASK                     (0xF000U)
84828 #define SEMC_DBICR1_WEH_SHIFT                    (12U)
84829 /*! WEH - WRX High Time
84830  */
84831 #define SEMC_DBICR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
84832 
84833 #define SEMC_DBICR1_REL_MASK                     (0x7F0000U)
84834 #define SEMC_DBICR1_REL_SHIFT                    (16U)
84835 /*! REL - RDX Low Time
84836  */
84837 #define SEMC_DBICR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
84838 
84839 #define SEMC_DBICR1_REH_MASK                     (0x7F000000U)
84840 #define SEMC_DBICR1_REH_SHIFT                    (24U)
84841 /*! REH - RDX High Time
84842  */
84843 #define SEMC_DBICR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
84844 /*! @} */
84845 
84846 /*! @name DBICR2 - DBI-B Control Register 2 */
84847 /*! @{ */
84848 
84849 #define SEMC_DBICR2_CEITV_MASK                   (0xFU)
84850 #define SEMC_DBICR2_CEITV_SHIFT                  (0U)
84851 /*! CEITV - CSX interval time
84852  */
84853 #define SEMC_DBICR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK)
84854 /*! @} */
84855 
84856 /*! @name IPCR0 - IP Command Control Register 0 */
84857 /*! @{ */
84858 
84859 #define SEMC_IPCR0_SA_MASK                       (0xFFFFFFFFU)
84860 #define SEMC_IPCR0_SA_SHIFT                      (0U)
84861 /*! SA - Slave address
84862  */
84863 #define SEMC_IPCR0_SA(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
84864 /*! @} */
84865 
84866 /*! @name IPCR1 - IP Command Control Register 1 */
84867 /*! @{ */
84868 
84869 #define SEMC_IPCR1_DATSZ_MASK                    (0x7U)
84870 #define SEMC_IPCR1_DATSZ_SHIFT                   (0U)
84871 /*! DATSZ - Data Size in Byte
84872  *  0b000..4
84873  *  0b001..1
84874  *  0b010..2
84875  *  0b011..3
84876  *  0b100..4
84877  *  0b101..4
84878  *  0b110..4
84879  *  0b111..4
84880  */
84881 #define SEMC_IPCR1_DATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
84882 
84883 #define SEMC_IPCR1_NAND_EXT_ADDR_MASK            (0xFF00U)
84884 #define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT           (8U)
84885 /*! NAND_EXT_ADDR - NAND Extended Address
84886  */
84887 #define SEMC_IPCR1_NAND_EXT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
84888 /*! @} */
84889 
84890 /*! @name IPCR2 - IP Command Control Register 2 */
84891 /*! @{ */
84892 
84893 #define SEMC_IPCR2_BM0_MASK                      (0x1U)
84894 #define SEMC_IPCR2_BM0_SHIFT                     (0U)
84895 /*! BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0)
84896  *  0b0..Byte is unmasked
84897  *  0b1..Byte is masked
84898  */
84899 #define SEMC_IPCR2_BM0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
84900 
84901 #define SEMC_IPCR2_BM1_MASK                      (0x2U)
84902 #define SEMC_IPCR2_BM1_SHIFT                     (1U)
84903 /*! BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8)
84904  *  0b0..Byte is unmasked
84905  *  0b1..Byte is masked
84906  */
84907 #define SEMC_IPCR2_BM1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
84908 
84909 #define SEMC_IPCR2_BM2_MASK                      (0x4U)
84910 #define SEMC_IPCR2_BM2_SHIFT                     (2U)
84911 /*! BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16)
84912  *  0b0..Byte is unmasked
84913  *  0b1..Byte is masked
84914  */
84915 #define SEMC_IPCR2_BM2(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
84916 
84917 #define SEMC_IPCR2_BM3_MASK                      (0x8U)
84918 #define SEMC_IPCR2_BM3_SHIFT                     (3U)
84919 /*! BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24)
84920  *  0b0..Byte is unmasked
84921  *  0b1..Byte is masked
84922  */
84923 #define SEMC_IPCR2_BM3(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
84924 /*! @} */
84925 
84926 /*! @name IPCMD - IP Command Register */
84927 /*! @{ */
84928 
84929 #define SEMC_IPCMD_CMD_MASK                      (0xFFFFU)
84930 #define SEMC_IPCMD_CMD_SHIFT                     (0U)
84931 #define SEMC_IPCMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
84932 
84933 #define SEMC_IPCMD_KEY_MASK                      (0xFFFF0000U)
84934 #define SEMC_IPCMD_KEY_SHIFT                     (16U)
84935 #define SEMC_IPCMD_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
84936 /*! @} */
84937 
84938 /*! @name IPTXDAT - TX DATA Register */
84939 /*! @{ */
84940 
84941 #define SEMC_IPTXDAT_DAT_MASK                    (0xFFFFFFFFU)
84942 #define SEMC_IPTXDAT_DAT_SHIFT                   (0U)
84943 #define SEMC_IPTXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
84944 /*! @} */
84945 
84946 /*! @name IPRXDAT - RX DATA Register */
84947 /*! @{ */
84948 
84949 #define SEMC_IPRXDAT_DAT_MASK                    (0xFFFFFFFFU)
84950 #define SEMC_IPRXDAT_DAT_SHIFT                   (0U)
84951 #define SEMC_IPRXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
84952 /*! @} */
84953 
84954 /*! @name STS0 - Status Register 0 */
84955 /*! @{ */
84956 
84957 #define SEMC_STS0_IDLE_MASK                      (0x1U)
84958 #define SEMC_STS0_IDLE_SHIFT                     (0U)
84959 /*! IDLE - Indicating whether the SEMC is in idle state.
84960  */
84961 #define SEMC_STS0_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
84962 
84963 #define SEMC_STS0_NARDY_MASK                     (0x2U)
84964 #define SEMC_STS0_NARDY_SHIFT                    (1U)
84965 /*! NARDY - Indicating NAND device Ready/WAIT# pin level.
84966  *  0b0..NAND device is not ready
84967  *  0b1..NAND device is ready
84968  */
84969 #define SEMC_STS0_NARDY(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
84970 /*! @} */
84971 
84972 /*! @name STS2 - Status Register 2 */
84973 /*! @{ */
84974 
84975 #define SEMC_STS2_NDWRPEND_MASK                  (0x8U)
84976 #define SEMC_STS2_NDWRPEND_SHIFT                 (3U)
84977 /*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
84978  *  0b0..No pending
84979  *  0b1..Pending
84980  */
84981 #define SEMC_STS2_NDWRPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
84982 /*! @} */
84983 
84984 /*! @name STS12 - Status Register 12 */
84985 /*! @{ */
84986 
84987 #define SEMC_STS12_NDADDR_MASK                   (0xFFFFFFFFU)
84988 #define SEMC_STS12_NDADDR_SHIFT                  (0U)
84989 /*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
84990  */
84991 #define SEMC_STS12_NDADDR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
84992 /*! @} */
84993 
84994 /*! @name STS13 - Status Register 13 */
84995 /*! @{ */
84996 
84997 #define SEMC_STS13_SLVLOCK_MASK                  (0x1U)
84998 #define SEMC_STS13_SLVLOCK_SHIFT                 (0U)
84999 /*! SLVLOCK - Sample clock slave delay line locked.
85000  *  0b0..Slave delay line is not locked.
85001  *  0b1..Slave delay line is locked.
85002  */
85003 #define SEMC_STS13_SLVLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
85004 
85005 #define SEMC_STS13_REFLOCK_MASK                  (0x2U)
85006 #define SEMC_STS13_REFLOCK_SHIFT                 (1U)
85007 /*! REFLOCK - Sample clock reference delay line locked.
85008  *  0b0..Reference delay line is not locked.
85009  *  0b1..Reference delay line is locked.
85010  */
85011 #define SEMC_STS13_REFLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
85012 
85013 #define SEMC_STS13_SLVSEL_MASK                   (0xFCU)
85014 #define SEMC_STS13_SLVSEL_SHIFT                  (2U)
85015 /*! SLVSEL - Sample clock slave delay line delay cell number selection.
85016  */
85017 #define SEMC_STS13_SLVSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
85018 
85019 #define SEMC_STS13_REFSEL_MASK                   (0x3F00U)
85020 #define SEMC_STS13_REFSEL_SHIFT                  (8U)
85021 /*! REFSEL - Sample clock reference delay line delay cell number selection.
85022  */
85023 #define SEMC_STS13_REFSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
85024 /*! @} */
85025 
85026 /*! @name BR9 - Base Register 9 */
85027 /*! @{ */
85028 
85029 #define SEMC_BR9_VLD_MASK                        (0x1U)
85030 #define SEMC_BR9_VLD_SHIFT                       (0U)
85031 /*! VLD - Valid
85032  *  0b0..The memory is invalid, can not be accessed.
85033  *  0b1..The memory is valid, can be accessed.
85034  */
85035 #define SEMC_BR9_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK)
85036 
85037 #define SEMC_BR9_MS_MASK                         (0x3EU)
85038 #define SEMC_BR9_MS_SHIFT                        (1U)
85039 /*! MS - Memory size
85040  *  0b00000..4KB
85041  *  0b00001..8KB
85042  *  0b00010..16KB
85043  *  0b00011..32KB
85044  *  0b00100..64KB
85045  *  0b00101..128KB
85046  *  0b00110..256KB
85047  *  0b00111..512KB
85048  *  0b01000..1MB
85049  *  0b01001..2MB
85050  *  0b01010..4MB
85051  *  0b01011..8MB
85052  *  0b01100..16MB
85053  *  0b01101..32MB
85054  *  0b01110..64MB
85055  *  0b01111..128MB
85056  *  0b10000..256MB
85057  *  0b10001..512MB
85058  *  0b10010..1GB
85059  *  0b10011..2GB
85060  *  0b10100-0b11111..4GB
85061  */
85062 #define SEMC_BR9_MS(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK)
85063 
85064 #define SEMC_BR9_BA_MASK                         (0xFFFFF000U)
85065 #define SEMC_BR9_BA_SHIFT                        (12U)
85066 /*! BA - Base Address
85067  */
85068 #define SEMC_BR9_BA(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK)
85069 /*! @} */
85070 
85071 /*! @name BR10 - Base Register 10 */
85072 /*! @{ */
85073 
85074 #define SEMC_BR10_VLD_MASK                       (0x1U)
85075 #define SEMC_BR10_VLD_SHIFT                      (0U)
85076 /*! VLD - Valid
85077  *  0b0..The memory is invalid, can not be accessed.
85078  *  0b1..The memory is valid, can be accessed.
85079  */
85080 #define SEMC_BR10_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK)
85081 
85082 #define SEMC_BR10_MS_MASK                        (0x3EU)
85083 #define SEMC_BR10_MS_SHIFT                       (1U)
85084 /*! MS - Memory size
85085  *  0b00000..4KB
85086  *  0b00001..8KB
85087  *  0b00010..16KB
85088  *  0b00011..32KB
85089  *  0b00100..64KB
85090  *  0b00101..128KB
85091  *  0b00110..256KB
85092  *  0b00111..512KB
85093  *  0b01000..1MB
85094  *  0b01001..2MB
85095  *  0b01010..4MB
85096  *  0b01011..8MB
85097  *  0b01100..16MB
85098  *  0b01101..32MB
85099  *  0b01110..64MB
85100  *  0b01111..128MB
85101  *  0b10000..256MB
85102  *  0b10001..512MB
85103  *  0b10010..1GB
85104  *  0b10011..2GB
85105  *  0b10100-0b11111..4GB
85106  */
85107 #define SEMC_BR10_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK)
85108 
85109 #define SEMC_BR10_BA_MASK                        (0xFFFFF000U)
85110 #define SEMC_BR10_BA_SHIFT                       (12U)
85111 /*! BA - Base Address
85112  */
85113 #define SEMC_BR10_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK)
85114 /*! @} */
85115 
85116 /*! @name BR11 - Base Register 11 */
85117 /*! @{ */
85118 
85119 #define SEMC_BR11_VLD_MASK                       (0x1U)
85120 #define SEMC_BR11_VLD_SHIFT                      (0U)
85121 /*! VLD - Valid
85122  *  0b0..The memory is invalid, can not be accessed.
85123  *  0b1..The memory is valid, can be accessed.
85124  */
85125 #define SEMC_BR11_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK)
85126 
85127 #define SEMC_BR11_MS_MASK                        (0x3EU)
85128 #define SEMC_BR11_MS_SHIFT                       (1U)
85129 /*! MS - Memory size
85130  *  0b00000..4KB
85131  *  0b00001..8KB
85132  *  0b00010..16KB
85133  *  0b00011..32KB
85134  *  0b00100..64KB
85135  *  0b00101..128KB
85136  *  0b00110..256KB
85137  *  0b00111..512KB
85138  *  0b01000..1MB
85139  *  0b01001..2MB
85140  *  0b01010..4MB
85141  *  0b01011..8MB
85142  *  0b01100..16MB
85143  *  0b01101..32MB
85144  *  0b01110..64MB
85145  *  0b01111..128MB
85146  *  0b10000..256MB
85147  *  0b10001..512MB
85148  *  0b10010..1GB
85149  *  0b10011..2GB
85150  *  0b10100-0b11111..4GB
85151  */
85152 #define SEMC_BR11_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK)
85153 
85154 #define SEMC_BR11_BA_MASK                        (0xFFFFF000U)
85155 #define SEMC_BR11_BA_SHIFT                       (12U)
85156 /*! BA - Base Address
85157  */
85158 #define SEMC_BR11_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK)
85159 /*! @} */
85160 
85161 /*! @name SRAMCR4 - SRAM Control Register 4 */
85162 /*! @{ */
85163 
85164 #define SEMC_SRAMCR4_PS_MASK                     (0x1U)
85165 #define SEMC_SRAMCR4_PS_SHIFT                    (0U)
85166 /*! PS - Port Size
85167  *  0b0..8bit
85168  *  0b1..16bit
85169  */
85170 #define SEMC_SRAMCR4_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK)
85171 
85172 #define SEMC_SRAMCR4_SYNCEN_MASK                 (0x2U)
85173 #define SEMC_SRAMCR4_SYNCEN_SHIFT                (1U)
85174 /*! SYNCEN - Synchronous Mode Enable
85175  *  0b0..Asynchronous mode is enabled.
85176  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
85177  */
85178 #define SEMC_SRAMCR4_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)
85179 
85180 #define SEMC_SRAMCR4_WAITEN_MASK                 (0x4U)
85181 #define SEMC_SRAMCR4_WAITEN_SHIFT                (2U)
85182 /*! WAITEN - Wait Enable
85183  *  0b0..The SEMC does not monitor wait pin.
85184  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
85185  */
85186 #define SEMC_SRAMCR4_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK)
85187 
85188 #define SEMC_SRAMCR4_WAITSP_MASK                 (0x8U)
85189 #define SEMC_SRAMCR4_WAITSP_SHIFT                (3U)
85190 /*! WAITSP - Wait Sample
85191  *  0b0..Wait pin is directly used by the SEMC.
85192  *  0b1..Wait pin is sampled by internal clock before it is used.
85193  */
85194 #define SEMC_SRAMCR4_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK)
85195 
85196 #define SEMC_SRAMCR4_BL_MASK                     (0x70U)
85197 #define SEMC_SRAMCR4_BL_SHIFT                    (4U)
85198 /*! BL - Burst Length
85199  *  0b000..1
85200  *  0b001..2
85201  *  0b010..4
85202  *  0b011..8
85203  *  0b100..16
85204  *  0b101..32
85205  *  0b110..64
85206  *  0b111..64
85207  */
85208 #define SEMC_SRAMCR4_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
85209 
85210 #define SEMC_SRAMCR4_AM_MASK                     (0x300U)
85211 #define SEMC_SRAMCR4_AM_SHIFT                    (8U)
85212 /*! AM - Address Mode
85213  *  0b00..Address/Data MUX mode (ADMUX)
85214  *  0b01..Advanced Address/Data MUX mode (AADM)
85215  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
85216  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
85217  */
85218 #define SEMC_SRAMCR4_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK)
85219 
85220 #define SEMC_SRAMCR4_ADVP_MASK                   (0x400U)
85221 #define SEMC_SRAMCR4_ADVP_SHIFT                  (10U)
85222 /*! ADVP - ADV# polarity
85223  *  0b0..ADV# is active low.
85224  *  0b1..ADV# is active high.
85225  */
85226 #define SEMC_SRAMCR4_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK)
85227 
85228 #define SEMC_SRAMCR4_ADVH_MASK                   (0x800U)
85229 #define SEMC_SRAMCR4_ADVH_SHIFT                  (11U)
85230 /*! ADVH - ADV# level control during address hold state
85231  *  0b0..ADV# is high during address hold state.
85232  *  0b1..ADV# is low during address hold state.
85233  */
85234 #define SEMC_SRAMCR4_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK)
85235 
85236 #define SEMC_SRAMCR4_COL_MASK                    (0xF000U)
85237 #define SEMC_SRAMCR4_COL_SHIFT                   (12U)
85238 /*! COL - Column Address bit width
85239  *  0b0000..12 Bits
85240  *  0b0001..11 Bits
85241  *  0b0010..10 Bits
85242  *  0b0011..9 Bits
85243  *  0b0100..8 Bits
85244  *  0b0101..7 Bits
85245  *  0b0110..6 Bits
85246  *  0b0111..5 Bits
85247  *  0b1000..4 Bits
85248  *  0b1001..3 Bits
85249  *  0b1010..2 Bits
85250  *  0b1011..12 Bits
85251  *  0b1100..12 Bits
85252  *  0b1101..12 Bits
85253  *  0b1110..12 Bits
85254  *  0b1111..12 Bits
85255  */
85256 #define SEMC_SRAMCR4_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK)
85257 /*! @} */
85258 
85259 /*! @name SRAMCR5 - SRAM Control Register 5 */
85260 /*! @{ */
85261 
85262 #define SEMC_SRAMCR5_CES_MASK                    (0xFU)
85263 #define SEMC_SRAMCR5_CES_SHIFT                   (0U)
85264 /*! CES - CE setup time
85265  */
85266 #define SEMC_SRAMCR5_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK)
85267 
85268 #define SEMC_SRAMCR5_CEH_MASK                    (0xF0U)
85269 #define SEMC_SRAMCR5_CEH_SHIFT                   (4U)
85270 /*! CEH - CE hold time
85271  */
85272 #define SEMC_SRAMCR5_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK)
85273 
85274 #define SEMC_SRAMCR5_AS_MASK                     (0xF00U)
85275 #define SEMC_SRAMCR5_AS_SHIFT                    (8U)
85276 /*! AS - Address setup time
85277  */
85278 #define SEMC_SRAMCR5_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK)
85279 
85280 #define SEMC_SRAMCR5_AH_MASK                     (0xF000U)
85281 #define SEMC_SRAMCR5_AH_SHIFT                    (12U)
85282 /*! AH - Address hold time
85283  */
85284 #define SEMC_SRAMCR5_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK)
85285 
85286 #define SEMC_SRAMCR5_WEL_MASK                    (0xF0000U)
85287 #define SEMC_SRAMCR5_WEL_SHIFT                   (16U)
85288 /*! WEL - WE low time
85289  */
85290 #define SEMC_SRAMCR5_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK)
85291 
85292 #define SEMC_SRAMCR5_WEH_MASK                    (0xF00000U)
85293 #define SEMC_SRAMCR5_WEH_SHIFT                   (20U)
85294 /*! WEH - WE high time
85295  */
85296 #define SEMC_SRAMCR5_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK)
85297 
85298 #define SEMC_SRAMCR5_REL_MASK                    (0xF000000U)
85299 #define SEMC_SRAMCR5_REL_SHIFT                   (24U)
85300 /*! REL - RE low time
85301  */
85302 #define SEMC_SRAMCR5_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK)
85303 
85304 #define SEMC_SRAMCR5_REH_MASK                    (0xF0000000U)
85305 #define SEMC_SRAMCR5_REH_SHIFT                   (28U)
85306 /*! REH - RE high time
85307  */
85308 #define SEMC_SRAMCR5_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK)
85309 /*! @} */
85310 
85311 /*! @name SRAMCR6 - SRAM Control Register 6 */
85312 /*! @{ */
85313 
85314 #define SEMC_SRAMCR6_WDS_MASK                    (0xFU)
85315 #define SEMC_SRAMCR6_WDS_SHIFT                   (0U)
85316 /*! WDS - Write Data setup time
85317  */
85318 #define SEMC_SRAMCR6_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK)
85319 
85320 #define SEMC_SRAMCR6_WDH_MASK                    (0xF0U)
85321 #define SEMC_SRAMCR6_WDH_SHIFT                   (4U)
85322 /*! WDH - Write Data hold time
85323  */
85324 #define SEMC_SRAMCR6_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK)
85325 
85326 #define SEMC_SRAMCR6_TA_MASK                     (0xF00U)
85327 #define SEMC_SRAMCR6_TA_SHIFT                    (8U)
85328 /*! TA - Turnaround time
85329  */
85330 #define SEMC_SRAMCR6_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK)
85331 
85332 #define SEMC_SRAMCR6_AWDH_MASK                   (0xF000U)
85333 #define SEMC_SRAMCR6_AWDH_SHIFT                  (12U)
85334 /*! AWDH - Address to write data hold time
85335  */
85336 #define SEMC_SRAMCR6_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK)
85337 
85338 #define SEMC_SRAMCR6_LC_MASK                     (0xF0000U)
85339 #define SEMC_SRAMCR6_LC_SHIFT                    (16U)
85340 /*! LC - Latency count
85341  */
85342 #define SEMC_SRAMCR6_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK)
85343 
85344 #define SEMC_SRAMCR6_RD_MASK                     (0xF00000U)
85345 #define SEMC_SRAMCR6_RD_SHIFT                    (20U)
85346 /*! RD - Read time
85347  */
85348 #define SEMC_SRAMCR6_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK)
85349 
85350 #define SEMC_SRAMCR6_CEITV_MASK                  (0xF000000U)
85351 #define SEMC_SRAMCR6_CEITV_SHIFT                 (24U)
85352 /*! CEITV - CE# interval time
85353  */
85354 #define SEMC_SRAMCR6_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK)
85355 
85356 #define SEMC_SRAMCR6_RDH_MASK                    (0xF0000000U)
85357 #define SEMC_SRAMCR6_RDH_SHIFT                   (28U)
85358 /*! RDH - Read hold time
85359  */
85360 #define SEMC_SRAMCR6_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK)
85361 /*! @} */
85362 
85363 /*! @name DCCR - Delay Chain Control Register */
85364 /*! @{ */
85365 
85366 #define SEMC_DCCR_SDRAMEN_MASK                   (0x1U)
85367 #define SEMC_DCCR_SDRAMEN_SHIFT                  (0U)
85368 /*! SDRAMEN - Delay chain insertion enable for SRAM device.
85369  *  0b0..Delay chain is not inserted.
85370  *  0b1..Delay chain is inserted.
85371  */
85372 #define SEMC_DCCR_SDRAMEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK)
85373 
85374 #define SEMC_DCCR_SDRAMVAL_MASK                  (0x3EU)
85375 #define SEMC_DCCR_SDRAMVAL_SHIFT                 (1U)
85376 /*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device.
85377  */
85378 #define SEMC_DCCR_SDRAMVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK)
85379 
85380 #define SEMC_DCCR_NOREN_MASK                     (0x100U)
85381 #define SEMC_DCCR_NOREN_SHIFT                    (8U)
85382 /*! NOREN - Delay chain insertion enable for NOR device.
85383  *  0b0..Delay chain is not inserted.
85384  *  0b1..Delay chain is inserted.
85385  */
85386 #define SEMC_DCCR_NOREN(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK)
85387 
85388 #define SEMC_DCCR_NORVAL_MASK                    (0x3E00U)
85389 #define SEMC_DCCR_NORVAL_SHIFT                   (9U)
85390 /*! NORVAL - Clock delay line delay cell number selection value for NOR device.
85391  */
85392 #define SEMC_DCCR_NORVAL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK)
85393 
85394 #define SEMC_DCCR_SRAM0EN_MASK                   (0x10000U)
85395 #define SEMC_DCCR_SRAM0EN_SHIFT                  (16U)
85396 /*! SRAM0EN - Delay chain insertion enable for SRAM device 0.
85397  *  0b0..Delay chain is not inserted.
85398  *  0b1..Delay chain is inserted.
85399  */
85400 #define SEMC_DCCR_SRAM0EN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK)
85401 
85402 #define SEMC_DCCR_SRAM0VAL_MASK                  (0x3E0000U)
85403 #define SEMC_DCCR_SRAM0VAL_SHIFT                 (17U)
85404 /*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0.
85405  */
85406 #define SEMC_DCCR_SRAM0VAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK)
85407 
85408 #define SEMC_DCCR_SRAMXEN_MASK                   (0x1000000U)
85409 #define SEMC_DCCR_SRAMXEN_SHIFT                  (24U)
85410 /*! SRAMXEN - Delay chain insertion enable for SRAM device 1-3.
85411  *  0b0..Delay chain is not inserted.
85412  *  0b1..Delay chain is inserted.
85413  */
85414 #define SEMC_DCCR_SRAMXEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK)
85415 
85416 #define SEMC_DCCR_SRAMXVAL_MASK                  (0x3E000000U)
85417 #define SEMC_DCCR_SRAMXVAL_SHIFT                 (25U)
85418 /*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3.
85419  */
85420 #define SEMC_DCCR_SRAMXVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK)
85421 /*! @} */
85422 
85423 
85424 /*!
85425  * @}
85426  */ /* end of group SEMC_Register_Masks */
85427 
85428 
85429 /* SEMC - Peripheral instance base addresses */
85430 /** Peripheral SEMC base address */
85431 #define SEMC_BASE                                (0x400D4000u)
85432 /** Peripheral SEMC base pointer */
85433 #define SEMC                                     ((SEMC_Type *)SEMC_BASE)
85434 /** Array initializer of SEMC peripheral base addresses */
85435 #define SEMC_BASE_ADDRS                          { SEMC_BASE }
85436 /** Array initializer of SEMC peripheral base pointers */
85437 #define SEMC_BASE_PTRS                           { SEMC }
85438 /** Interrupt vectors for the SEMC peripheral type */
85439 #define SEMC_IRQS                                { SEMC_IRQn }
85440 
85441 /*!
85442  * @}
85443  */ /* end of group SEMC_Peripheral_Access_Layer */
85444 
85445 
85446 /* ----------------------------------------------------------------------------
85447    -- SNVS Peripheral Access Layer
85448    ---------------------------------------------------------------------------- */
85449 
85450 /*!
85451  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
85452  * @{
85453  */
85454 
85455 /** SNVS - Register Layout Typedef */
85456 typedef struct {
85457   __IO uint32_t HPLR;                              /**< SNVS_HP Lock Register, offset: 0x0 */
85458   __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
85459   __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
85460   __IO uint32_t HPSICR;                            /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
85461   __IO uint32_t HPSVCR;                            /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
85462   __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
85463   __IO uint32_t HPSVSR;                            /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
85464   __IO uint32_t HPHACIVR;                          /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
85465   __I  uint32_t HPHACR;                            /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
85466   __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
85467   __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
85468   __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
85469   __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
85470   __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
85471   __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
85472   __IO uint32_t LPMKCR;                            /**< SNVS_LP Master Key Control Register, offset: 0x3C */
85473   __IO uint32_t LPSVCR;                            /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
85474   __IO uint32_t LPTGFCR;                           /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */
85475   __IO uint32_t LPTDCR;                            /**< SNVS_LP Tamper Detect Configuration Register, offset: 0x48 */
85476   __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
85477   __IO uint32_t LPSRTCMR;                          /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
85478   __IO uint32_t LPSRTCLR;                          /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
85479   __IO uint32_t LPTAR;                             /**< SNVS_LP Time Alarm Register, offset: 0x58 */
85480   __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
85481   __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
85482   __IO uint32_t LPLVDR;                            /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */
85483   __IO uint32_t LPGPR0_LEGACY_ALIAS;               /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
85484   __IO uint32_t LPZMKR[8];                         /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
85485        uint8_t RESERVED_0[4];
85486   __IO uint32_t LPGPR_ALIAS[4];                    /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
85487   __IO uint32_t LPTDC2R;                           /**< SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0 */
85488   __IO uint32_t LPTDSR;                            /**< SNVS_LP Tamper Detectors Status Register, offset: 0xA4 */
85489   __IO uint32_t LPTGF1CR;                          /**< SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8 */
85490   __IO uint32_t LPTGF2CR;                          /**< SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC */
85491        uint8_t RESERVED_1[16];
85492   __O  uint32_t LPATCR[5];                         /**< SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4 */
85493        uint8_t RESERVED_2[12];
85494   __IO uint32_t LPATCTLR;                          /**< SNVS_LP Active Tamper Control Register, offset: 0xE0 */
85495   __IO uint32_t LPATCLKR;                          /**< SNVS_LP Active Tamper Clock Control Register, offset: 0xE4 */
85496   __IO uint32_t LPATRC1R;                          /**< SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8 */
85497   __IO uint32_t LPATRC2R;                          /**< SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC */
85498        uint8_t RESERVED_3[16];
85499   __IO uint32_t LPGPR[4];                          /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
85500        uint8_t RESERVED_4[2792];
85501   __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
85502   __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
85503 } SNVS_Type;
85504 
85505 /* ----------------------------------------------------------------------------
85506    -- SNVS Register Masks
85507    ---------------------------------------------------------------------------- */
85508 
85509 /*!
85510  * @addtogroup SNVS_Register_Masks SNVS Register Masks
85511  * @{
85512  */
85513 
85514 /*! @name HPLR - SNVS_HP Lock Register */
85515 /*! @{ */
85516 
85517 #define SNVS_HPLR_ZMK_WSL_MASK                   (0x1U)
85518 #define SNVS_HPLR_ZMK_WSL_SHIFT                  (0U)
85519 /*! ZMK_WSL
85520  *  0b0..Write access is allowed
85521  *  0b1..Write access is not allowed
85522  */
85523 #define SNVS_HPLR_ZMK_WSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
85524 
85525 #define SNVS_HPLR_ZMK_RSL_MASK                   (0x2U)
85526 #define SNVS_HPLR_ZMK_RSL_SHIFT                  (1U)
85527 /*! ZMK_RSL
85528  *  0b0..Read access is allowed (only in software Programming mode)
85529  *  0b1..Read access is not allowed
85530  */
85531 #define SNVS_HPLR_ZMK_RSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
85532 
85533 #define SNVS_HPLR_SRTC_SL_MASK                   (0x4U)
85534 #define SNVS_HPLR_SRTC_SL_SHIFT                  (2U)
85535 /*! SRTC_SL
85536  *  0b0..Write access is allowed
85537  *  0b1..Write access is not allowed
85538  */
85539 #define SNVS_HPLR_SRTC_SL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
85540 
85541 #define SNVS_HPLR_LPCALB_SL_MASK                 (0x8U)
85542 #define SNVS_HPLR_LPCALB_SL_SHIFT                (3U)
85543 /*! LPCALB_SL
85544  *  0b0..Write access is allowed
85545  *  0b1..Write access is not allowed
85546  */
85547 #define SNVS_HPLR_LPCALB_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
85548 
85549 #define SNVS_HPLR_MC_SL_MASK                     (0x10U)
85550 #define SNVS_HPLR_MC_SL_SHIFT                    (4U)
85551 /*! MC_SL
85552  *  0b0..Write access (increment) is allowed
85553  *  0b1..Write access (increment) is not allowed
85554  */
85555 #define SNVS_HPLR_MC_SL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
85556 
85557 #define SNVS_HPLR_GPR_SL_MASK                    (0x20U)
85558 #define SNVS_HPLR_GPR_SL_SHIFT                   (5U)
85559 /*! GPR_SL
85560  *  0b0..Write access is allowed
85561  *  0b1..Write access is not allowed
85562  */
85563 #define SNVS_HPLR_GPR_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
85564 
85565 #define SNVS_HPLR_LPSVCR_SL_MASK                 (0x40U)
85566 #define SNVS_HPLR_LPSVCR_SL_SHIFT                (6U)
85567 /*! LPSVCR_SL
85568  *  0b0..Write access is allowed
85569  *  0b1..Write access is not allowed
85570  */
85571 #define SNVS_HPLR_LPSVCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
85572 
85573 #define SNVS_HPLR_LPTGFCR_SL_MASK                (0x80U)
85574 #define SNVS_HPLR_LPTGFCR_SL_SHIFT               (7U)
85575 /*! LPTGFCR_SL
85576  *  0b0..Write access is allowed
85577  *  0b1..Write access is not allowed
85578  */
85579 #define SNVS_HPLR_LPTGFCR_SL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
85580 
85581 #define SNVS_HPLR_LPSECR_SL_MASK                 (0x100U)
85582 #define SNVS_HPLR_LPSECR_SL_SHIFT                (8U)
85583 /*! LPSECR_SL
85584  *  0b0..Write access is allowed
85585  *  0b1..Write access is not allowed
85586  */
85587 #define SNVS_HPLR_LPSECR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
85588 
85589 #define SNVS_HPLR_MKS_SL_MASK                    (0x200U)
85590 #define SNVS_HPLR_MKS_SL_SHIFT                   (9U)
85591 /*! MKS_SL
85592  *  0b0..Write access is allowed
85593  *  0b1..Write access is not allowed
85594  */
85595 #define SNVS_HPLR_MKS_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
85596 
85597 #define SNVS_HPLR_HPSVCR_L_MASK                  (0x10000U)
85598 #define SNVS_HPLR_HPSVCR_L_SHIFT                 (16U)
85599 /*! HPSVCR_L
85600  *  0b0..Write access is allowed
85601  *  0b1..Write access is not allowed
85602  */
85603 #define SNVS_HPLR_HPSVCR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
85604 
85605 #define SNVS_HPLR_HPSICR_L_MASK                  (0x20000U)
85606 #define SNVS_HPLR_HPSICR_L_SHIFT                 (17U)
85607 /*! HPSICR_L
85608  *  0b0..Write access is allowed
85609  *  0b1..Write access is not allowed
85610  */
85611 #define SNVS_HPLR_HPSICR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
85612 
85613 #define SNVS_HPLR_HAC_L_MASK                     (0x40000U)
85614 #define SNVS_HPLR_HAC_L_SHIFT                    (18U)
85615 /*! HAC_L
85616  *  0b0..Write access is allowed
85617  *  0b1..Write access is not allowed
85618  */
85619 #define SNVS_HPLR_HAC_L(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
85620 
85621 #define SNVS_HPLR_AT1_SL_MASK                    (0x1000000U)
85622 #define SNVS_HPLR_AT1_SL_SHIFT                   (24U)
85623 /*! AT1_SL
85624  *  0b0..Write access is allowed.
85625  *  0b1..Write access is not allowed.
85626  */
85627 #define SNVS_HPLR_AT1_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
85628 
85629 #define SNVS_HPLR_AT2_SL_MASK                    (0x2000000U)
85630 #define SNVS_HPLR_AT2_SL_SHIFT                   (25U)
85631 /*! AT2_SL
85632  *  0b0..Write access is allowed.
85633  *  0b1..Write access is not allowed.
85634  */
85635 #define SNVS_HPLR_AT2_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
85636 
85637 #define SNVS_HPLR_AT3_SL_MASK                    (0x4000000U)
85638 #define SNVS_HPLR_AT3_SL_SHIFT                   (26U)
85639 /*! AT3_SL
85640  *  0b0..Write access is allowed.
85641  *  0b1..Write access is not allowed.
85642  */
85643 #define SNVS_HPLR_AT3_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
85644 
85645 #define SNVS_HPLR_AT4_SL_MASK                    (0x8000000U)
85646 #define SNVS_HPLR_AT4_SL_SHIFT                   (27U)
85647 /*! AT4_SL
85648  *  0b0..Write access is allowed.
85649  *  0b1..Write access is not allowed.
85650  */
85651 #define SNVS_HPLR_AT4_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
85652 
85653 #define SNVS_HPLR_AT5_SL_MASK                    (0x10000000U)
85654 #define SNVS_HPLR_AT5_SL_SHIFT                   (28U)
85655 /*! AT5_SL
85656  *  0b0..Write access is allowed.
85657  *  0b1..Write access is not allowed.
85658  */
85659 #define SNVS_HPLR_AT5_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
85660 /*! @} */
85661 
85662 /*! @name HPCOMR - SNVS_HP Command Register */
85663 /*! @{ */
85664 
85665 #define SNVS_HPCOMR_SSM_ST_MASK                  (0x1U)
85666 #define SNVS_HPCOMR_SSM_ST_SHIFT                 (0U)
85667 #define SNVS_HPCOMR_SSM_ST(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
85668 
85669 #define SNVS_HPCOMR_SSM_ST_DIS_MASK              (0x2U)
85670 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             (1U)
85671 /*! SSM_ST_DIS
85672  *  0b0..Secure to Trusted State transition is enabled
85673  *  0b1..Secure to Trusted State transition is disabled
85674  */
85675 #define SNVS_HPCOMR_SSM_ST_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
85676 
85677 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            (0x4U)
85678 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           (2U)
85679 /*! SSM_SFNS_DIS
85680  *  0b0..Soft Fail to Non-Secure State transition is enabled
85681  *  0b1..Soft Fail to Non-Secure State transition is disabled
85682  */
85683 #define SNVS_HPCOMR_SSM_SFNS_DIS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
85684 
85685 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
85686 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
85687 /*! LP_SWR
85688  *  0b0..No Action
85689  *  0b1..Reset LP section
85690  */
85691 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
85692 
85693 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
85694 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
85695 /*! LP_SWR_DIS
85696  *  0b0..LP software reset is enabled
85697  *  0b1..LP software reset is disabled
85698  */
85699 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
85700 
85701 #define SNVS_HPCOMR_SW_SV_MASK                   (0x100U)
85702 #define SNVS_HPCOMR_SW_SV_SHIFT                  (8U)
85703 #define SNVS_HPCOMR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
85704 
85705 #define SNVS_HPCOMR_SW_FSV_MASK                  (0x200U)
85706 #define SNVS_HPCOMR_SW_FSV_SHIFT                 (9U)
85707 #define SNVS_HPCOMR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
85708 
85709 #define SNVS_HPCOMR_SW_LPSV_MASK                 (0x400U)
85710 #define SNVS_HPCOMR_SW_LPSV_SHIFT                (10U)
85711 #define SNVS_HPCOMR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
85712 
85713 #define SNVS_HPCOMR_PROG_ZMK_MASK                (0x1000U)
85714 #define SNVS_HPCOMR_PROG_ZMK_SHIFT               (12U)
85715 /*! PROG_ZMK
85716  *  0b0..No Action
85717  *  0b1..Activate hardware key programming mechanism
85718  */
85719 #define SNVS_HPCOMR_PROG_ZMK(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
85720 
85721 #define SNVS_HPCOMR_MKS_EN_MASK                  (0x2000U)
85722 #define SNVS_HPCOMR_MKS_EN_SHIFT                 (13U)
85723 /*! MKS_EN
85724  *  0b0..OTP master key is selected as an SNVS master key
85725  *  0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
85726  */
85727 #define SNVS_HPCOMR_MKS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
85728 
85729 #define SNVS_HPCOMR_HAC_EN_MASK                  (0x10000U)
85730 #define SNVS_HPCOMR_HAC_EN_SHIFT                 (16U)
85731 /*! HAC_EN
85732  *  0b0..High Assurance Counter is disabled
85733  *  0b1..High Assurance Counter is enabled
85734  */
85735 #define SNVS_HPCOMR_HAC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
85736 
85737 #define SNVS_HPCOMR_HAC_LOAD_MASK                (0x20000U)
85738 #define SNVS_HPCOMR_HAC_LOAD_SHIFT               (17U)
85739 /*! HAC_LOAD
85740  *  0b0..No Action
85741  *  0b1..Load the HAC
85742  */
85743 #define SNVS_HPCOMR_HAC_LOAD(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
85744 
85745 #define SNVS_HPCOMR_HAC_CLEAR_MASK               (0x40000U)
85746 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT              (18U)
85747 /*! HAC_CLEAR
85748  *  0b0..No Action
85749  *  0b1..Clear the HAC
85750  */
85751 #define SNVS_HPCOMR_HAC_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
85752 
85753 #define SNVS_HPCOMR_HAC_STOP_MASK                (0x80000U)
85754 #define SNVS_HPCOMR_HAC_STOP_SHIFT               (19U)
85755 #define SNVS_HPCOMR_HAC_STOP(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
85756 
85757 #define SNVS_HPCOMR_NPSWA_EN_MASK                (0x80000000U)
85758 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               (31U)
85759 #define SNVS_HPCOMR_NPSWA_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
85760 /*! @} */
85761 
85762 /*! @name HPCR - SNVS_HP Control Register */
85763 /*! @{ */
85764 
85765 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
85766 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
85767 /*! RTC_EN
85768  *  0b0..RTC is disabled
85769  *  0b1..RTC is enabled
85770  */
85771 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
85772 
85773 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
85774 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
85775 /*! HPTA_EN
85776  *  0b0..HP Time Alarm Interrupt is disabled
85777  *  0b1..HP Time Alarm Interrupt is enabled
85778  */
85779 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
85780 
85781 #define SNVS_HPCR_DIS_PI_MASK                    (0x4U)
85782 #define SNVS_HPCR_DIS_PI_SHIFT                   (2U)
85783 /*! DIS_PI
85784  *  0b0..Periodic interrupt will trigger a functional interrupt
85785  *  0b1..Disable periodic interrupt in the function interrupt
85786  */
85787 #define SNVS_HPCR_DIS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
85788 
85789 #define SNVS_HPCR_PI_EN_MASK                     (0x8U)
85790 #define SNVS_HPCR_PI_EN_SHIFT                    (3U)
85791 /*! PI_EN
85792  *  0b0..HP Periodic Interrupt is disabled
85793  *  0b1..HP Periodic Interrupt is enabled
85794  */
85795 #define SNVS_HPCR_PI_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
85796 
85797 #define SNVS_HPCR_PI_FREQ_MASK                   (0xF0U)
85798 #define SNVS_HPCR_PI_FREQ_SHIFT                  (4U)
85799 /*! PI_FREQ
85800  *  0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
85801  *  0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
85802  *  0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
85803  *  0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
85804  *  0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
85805  *  0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
85806  *  0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
85807  *  0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
85808  *  0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
85809  *  0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
85810  *  0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
85811  *  0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
85812  *  0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
85813  *  0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
85814  *  0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
85815  *  0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
85816  */
85817 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
85818 
85819 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
85820 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
85821 /*! HPCALB_EN
85822  *  0b0..HP Timer calibration disabled
85823  *  0b1..HP Timer calibration enabled
85824  */
85825 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
85826 
85827 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
85828 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
85829 /*! HPCALB_VAL
85830  *  0b00000..+0 counts per each 32768 ticks of the counter
85831  *  0b00001..+1 counts per each 32768 ticks of the counter
85832  *  0b00010..+2 counts per each 32768 ticks of the counter
85833  *  0b01111..+15 counts per each 32768 ticks of the counter
85834  *  0b10000..-16 counts per each 32768 ticks of the counter
85835  *  0b10001..-15 counts per each 32768 ticks of the counter
85836  *  0b11110..-2 counts per each 32768 ticks of the counter
85837  *  0b11111..-1 counts per each 32768 ticks of the counter
85838  */
85839 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
85840 
85841 #define SNVS_HPCR_HP_TS_MASK                     (0x10000U)
85842 #define SNVS_HPCR_HP_TS_SHIFT                    (16U)
85843 /*! HP_TS
85844  *  0b0..No Action
85845  *  0b1..Synchronize the HP Time Counter to the LP Time Counter
85846  */
85847 #define SNVS_HPCR_HP_TS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
85848 
85849 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
85850 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
85851 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
85852 
85853 #define SNVS_HPCR_BTN_MASK_MASK                  (0x8000000U)
85854 #define SNVS_HPCR_BTN_MASK_SHIFT                 (27U)
85855 #define SNVS_HPCR_BTN_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
85856 /*! @} */
85857 
85858 /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
85859 /*! @{ */
85860 
85861 #define SNVS_HPSICR_CAAM_EN_MASK                 (0x1U)
85862 #define SNVS_HPSICR_CAAM_EN_SHIFT                (0U)
85863 /*! CAAM_EN
85864  *  0b0..CAAM Security Violation Interrupt is Disabled
85865  *  0b1..CAAM Security Violation Interrupt is Enabled
85866  */
85867 #define SNVS_HPSICR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
85868 
85869 #define SNVS_HPSICR_JTAGC_EN_MASK                (0x2U)
85870 #define SNVS_HPSICR_JTAGC_EN_SHIFT               (1U)
85871 /*! JTAGC_EN
85872  *  0b0..JTAG Active Interrupt is Disabled
85873  *  0b1..JTAG Active Interrupt is Enabled
85874  */
85875 #define SNVS_HPSICR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
85876 
85877 #define SNVS_HPSICR_WDOG2_EN_MASK                (0x4U)
85878 #define SNVS_HPSICR_WDOG2_EN_SHIFT               (2U)
85879 /*! WDOG2_EN
85880  *  0b0..Watchdog 2 Reset Interrupt is Disabled
85881  *  0b1..Watchdog 2 Reset Interrupt is Enabled
85882  */
85883 #define SNVS_HPSICR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
85884 
85885 #define SNVS_HPSICR_SRC_EN_MASK                  (0x10U)
85886 #define SNVS_HPSICR_SRC_EN_SHIFT                 (4U)
85887 /*! SRC_EN
85888  *  0b0..Internal Boot Interrupt is Disabled
85889  *  0b1..Internal Boot Interrupt is Enabled
85890  */
85891 #define SNVS_HPSICR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
85892 
85893 #define SNVS_HPSICR_OCOTP_EN_MASK                (0x20U)
85894 #define SNVS_HPSICR_OCOTP_EN_SHIFT               (5U)
85895 /*! OCOTP_EN
85896  *  0b0..OCOTP attack error Interrupt is Disabled
85897  *  0b1..OCOTP attack error Interrupt is Enabled
85898  */
85899 #define SNVS_HPSICR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
85900 
85901 #define SNVS_HPSICR_LPSVI_EN_MASK                (0x80000000U)
85902 #define SNVS_HPSICR_LPSVI_EN_SHIFT               (31U)
85903 /*! LPSVI_EN
85904  *  0b0..LP Security Violation Interrupt is Disabled
85905  *  0b1..LP Security Violation Interrupt is Enabled
85906  */
85907 #define SNVS_HPSICR_LPSVI_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
85908 /*! @} */
85909 
85910 /*! @name HPSVCR - SNVS_HP Security Violation Control Register */
85911 /*! @{ */
85912 
85913 #define SNVS_HPSVCR_CAAM_CFG_MASK                (0x1U)
85914 #define SNVS_HPSVCR_CAAM_CFG_SHIFT               (0U)
85915 /*! CAAM_CFG
85916  *  0b0..CAAM Security Violation is a non-fatal violation
85917  *  0b1..CAAM Security Violation is a fatal violation
85918  */
85919 #define SNVS_HPSVCR_CAAM_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
85920 
85921 #define SNVS_HPSVCR_JTAGC_CFG_MASK               (0x2U)
85922 #define SNVS_HPSVCR_JTAGC_CFG_SHIFT              (1U)
85923 /*! JTAGC_CFG
85924  *  0b0..JTAG Active is a non-fatal violation
85925  *  0b1..JTAG Active is a fatal violation
85926  */
85927 #define SNVS_HPSVCR_JTAGC_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
85928 
85929 #define SNVS_HPSVCR_WDOG2_CFG_MASK               (0x4U)
85930 #define SNVS_HPSVCR_WDOG2_CFG_SHIFT              (2U)
85931 /*! WDOG2_CFG
85932  *  0b0..Watchdog 2 Reset is a non-fatal violation
85933  *  0b1..Watchdog 2 Reset is a fatal violation
85934  */
85935 #define SNVS_HPSVCR_WDOG2_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
85936 
85937 #define SNVS_HPSVCR_SRC_CFG_MASK                 (0x10U)
85938 #define SNVS_HPSVCR_SRC_CFG_SHIFT                (4U)
85939 /*! SRC_CFG
85940  *  0b0..Internal Boot is a non-fatal violation
85941  *  0b1..Internal Boot is a fatal violation
85942  */
85943 #define SNVS_HPSVCR_SRC_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
85944 
85945 #define SNVS_HPSVCR_OCOTP_CFG_MASK               (0x60U)
85946 #define SNVS_HPSVCR_OCOTP_CFG_SHIFT              (5U)
85947 /*! OCOTP_CFG
85948  *  0b00..OCOTP attack error is disabled
85949  *  0b01..OCOTP attack error is a non-fatal violation
85950  *  0b1x..OCOTP attack error is a fatal violation
85951  */
85952 #define SNVS_HPSVCR_OCOTP_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
85953 
85954 #define SNVS_HPSVCR_LPSV_CFG_MASK                (0xC0000000U)
85955 #define SNVS_HPSVCR_LPSV_CFG_SHIFT               (30U)
85956 /*! LPSV_CFG
85957  *  0b00..LP security violation is disabled
85958  *  0b01..LP security violation is a non-fatal violation
85959  *  0b1x..LP security violation is a fatal violation
85960  */
85961 #define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
85962 /*! @} */
85963 
85964 /*! @name HPSR - SNVS_HP Status Register */
85965 /*! @{ */
85966 
85967 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
85968 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
85969 /*! HPTA
85970  *  0b0..No time alarm interrupt occurred.
85971  *  0b1..A time alarm interrupt occurred.
85972  */
85973 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
85974 
85975 #define SNVS_HPSR_PI_MASK                        (0x2U)
85976 #define SNVS_HPSR_PI_SHIFT                       (1U)
85977 /*! PI
85978  *  0b0..No periodic interrupt occurred.
85979  *  0b1..A periodic interrupt occurred.
85980  */
85981 #define SNVS_HPSR_PI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
85982 
85983 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
85984 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
85985 #define SNVS_HPSR_LPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
85986 
85987 #define SNVS_HPSR_BTN_MASK                       (0x40U)
85988 #define SNVS_HPSR_BTN_SHIFT                      (6U)
85989 #define SNVS_HPSR_BTN(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
85990 
85991 #define SNVS_HPSR_BI_MASK                        (0x80U)
85992 #define SNVS_HPSR_BI_SHIFT                       (7U)
85993 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
85994 
85995 #define SNVS_HPSR_SSM_STATE_MASK                 (0xF00U)
85996 #define SNVS_HPSR_SSM_STATE_SHIFT                (8U)
85997 /*! SSM_STATE
85998  *  0b0000..Init
85999  *  0b0001..Hard Fail
86000  *  0b0011..Soft Fail
86001  *  0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
86002  *  0b1001..Check
86003  *  0b1011..Non-Secure
86004  *  0b1101..Trusted
86005  *  0b1111..Secure
86006  */
86007 #define SNVS_HPSR_SSM_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
86008 
86009 #define SNVS_HPSR_SYS_SECURITY_CFG_MASK          (0x7000U)
86010 #define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT         (12U)
86011 /*! SYS_SECURITY_CFG
86012  *  0b000..Fab Configuration - the default configuration of newly fabricated chips
86013  *  0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown
86014  *  0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown
86015  *  0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis
86016  */
86017 #define SNVS_HPSR_SYS_SECURITY_CFG(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
86018 
86019 #define SNVS_HPSR_SYS_SECURE_BOOT_MASK           (0x8000U)
86020 #define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT          (15U)
86021 #define SNVS_HPSR_SYS_SECURE_BOOT(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
86022 
86023 #define SNVS_HPSR_OTPMK_ZERO_MASK                (0x8000000U)
86024 #define SNVS_HPSR_OTPMK_ZERO_SHIFT               (27U)
86025 /*! OTPMK_ZERO
86026  *  0b0..The OTPMK is not zero.
86027  *  0b1..The OTPMK is zero.
86028  */
86029 #define SNVS_HPSR_OTPMK_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
86030 
86031 #define SNVS_HPSR_ZMK_ZERO_MASK                  (0x80000000U)
86032 #define SNVS_HPSR_ZMK_ZERO_SHIFT                 (31U)
86033 /*! ZMK_ZERO
86034  *  0b0..The ZMK is not zero.
86035  *  0b1..The ZMK is zero.
86036  */
86037 #define SNVS_HPSR_ZMK_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
86038 /*! @} */
86039 
86040 /*! @name HPSVSR - SNVS_HP Security Violation Status Register */
86041 /*! @{ */
86042 
86043 #define SNVS_HPSVSR_CAAM_MASK                    (0x1U)
86044 #define SNVS_HPSVSR_CAAM_SHIFT                   (0U)
86045 /*! CAAM
86046  *  0b0..No CAAM Security Violation security violation was detected.
86047  *  0b1..CAAM Security Violation security violation was detected.
86048  */
86049 #define SNVS_HPSVSR_CAAM(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
86050 
86051 #define SNVS_HPSVSR_JTAGC_MASK                   (0x2U)
86052 #define SNVS_HPSVSR_JTAGC_SHIFT                  (1U)
86053 /*! JTAGC
86054  *  0b0..No JTAG Active security violation was detected.
86055  *  0b1..JTAG Active security violation was detected.
86056  */
86057 #define SNVS_HPSVSR_JTAGC(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
86058 
86059 #define SNVS_HPSVSR_WDOG2_MASK                   (0x4U)
86060 #define SNVS_HPSVSR_WDOG2_SHIFT                  (2U)
86061 /*! WDOG2
86062  *  0b0..No Watchdog 2 Reset security violation was detected.
86063  *  0b1..Watchdog 2 Reset security violation was detected.
86064  */
86065 #define SNVS_HPSVSR_WDOG2(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
86066 
86067 #define SNVS_HPSVSR_SRC_MASK                     (0x10U)
86068 #define SNVS_HPSVSR_SRC_SHIFT                    (4U)
86069 /*! SRC
86070  *  0b0..No Internal Boot security violation was detected.
86071  *  0b1..Internal Boot security violation was detected.
86072  */
86073 #define SNVS_HPSVSR_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
86074 
86075 #define SNVS_HPSVSR_OCOTP_MASK                   (0x20U)
86076 #define SNVS_HPSVSR_OCOTP_SHIFT                  (5U)
86077 /*! OCOTP
86078  *  0b0..No OCOTP attack error security violation was detected.
86079  *  0b1..OCOTP attack error security violation was detected.
86080  */
86081 #define SNVS_HPSVSR_OCOTP(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
86082 
86083 #define SNVS_HPSVSR_SW_SV_MASK                   (0x2000U)
86084 #define SNVS_HPSVSR_SW_SV_SHIFT                  (13U)
86085 #define SNVS_HPSVSR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
86086 
86087 #define SNVS_HPSVSR_SW_FSV_MASK                  (0x4000U)
86088 #define SNVS_HPSVSR_SW_FSV_SHIFT                 (14U)
86089 #define SNVS_HPSVSR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
86090 
86091 #define SNVS_HPSVSR_SW_LPSV_MASK                 (0x8000U)
86092 #define SNVS_HPSVSR_SW_LPSV_SHIFT                (15U)
86093 #define SNVS_HPSVSR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
86094 
86095 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK            (0x1FF0000U)
86096 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT           (16U)
86097 #define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
86098 
86099 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            (0x8000000U)
86100 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           (27U)
86101 /*! ZMK_ECC_FAIL
86102  *  0b0..ZMK ECC Failure was not detected.
86103  *  0b1..ZMK ECC Failure was detected.
86104  */
86105 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
86106 
86107 #define SNVS_HPSVSR_LP_SEC_VIO_MASK              (0x80000000U)
86108 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT             (31U)
86109 #define SNVS_HPSVSR_LP_SEC_VIO(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
86110 /*! @} */
86111 
86112 /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
86113 /*! @{ */
86114 
86115 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK        (0xFFFFFFFFU)
86116 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT       (0U)
86117 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
86118 /*! @} */
86119 
86120 /*! @name HPHACR - SNVS_HP High Assurance Counter Register */
86121 /*! @{ */
86122 
86123 #define SNVS_HPHACR_HAC_COUNTER_MASK             (0xFFFFFFFFU)
86124 #define SNVS_HPHACR_HAC_COUNTER_SHIFT            (0U)
86125 #define SNVS_HPHACR_HAC_COUNTER(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
86126 /*! @} */
86127 
86128 /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
86129 /*! @{ */
86130 
86131 #define SNVS_HPRTCMR_RTC_MASK                    (0x7FFFU)
86132 #define SNVS_HPRTCMR_RTC_SHIFT                   (0U)
86133 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
86134 /*! @} */
86135 
86136 /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
86137 /*! @{ */
86138 
86139 #define SNVS_HPRTCLR_RTC_MASK                    (0xFFFFFFFFU)
86140 #define SNVS_HPRTCLR_RTC_SHIFT                   (0U)
86141 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
86142 /*! @} */
86143 
86144 /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
86145 /*! @{ */
86146 
86147 #define SNVS_HPTAMR_HPTA_MS_MASK                 (0x7FFFU)
86148 #define SNVS_HPTAMR_HPTA_MS_SHIFT                (0U)
86149 #define SNVS_HPTAMR_HPTA_MS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
86150 /*! @} */
86151 
86152 /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
86153 /*! @{ */
86154 
86155 #define SNVS_HPTALR_HPTA_LS_MASK                 (0xFFFFFFFFU)
86156 #define SNVS_HPTALR_HPTA_LS_SHIFT                (0U)
86157 #define SNVS_HPTALR_HPTA_LS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
86158 /*! @} */
86159 
86160 /*! @name LPLR - SNVS_LP Lock Register */
86161 /*! @{ */
86162 
86163 #define SNVS_LPLR_ZMK_WHL_MASK                   (0x1U)
86164 #define SNVS_LPLR_ZMK_WHL_SHIFT                  (0U)
86165 /*! ZMK_WHL
86166  *  0b0..Write access is allowed.
86167  *  0b1..Write access is not allowed.
86168  */
86169 #define SNVS_LPLR_ZMK_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
86170 
86171 #define SNVS_LPLR_ZMK_RHL_MASK                   (0x2U)
86172 #define SNVS_LPLR_ZMK_RHL_SHIFT                  (1U)
86173 /*! ZMK_RHL
86174  *  0b0..Read access is allowed (only in software programming mode).
86175  *  0b1..Read access is not allowed.
86176  */
86177 #define SNVS_LPLR_ZMK_RHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
86178 
86179 #define SNVS_LPLR_SRTC_HL_MASK                   (0x4U)
86180 #define SNVS_LPLR_SRTC_HL_SHIFT                  (2U)
86181 /*! SRTC_HL
86182  *  0b0..Write access is allowed.
86183  *  0b1..Write access is not allowed.
86184  */
86185 #define SNVS_LPLR_SRTC_HL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
86186 
86187 #define SNVS_LPLR_LPCALB_HL_MASK                 (0x8U)
86188 #define SNVS_LPLR_LPCALB_HL_SHIFT                (3U)
86189 /*! LPCALB_HL
86190  *  0b0..Write access is allowed.
86191  *  0b1..Write access is not allowed.
86192  */
86193 #define SNVS_LPLR_LPCALB_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
86194 
86195 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
86196 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
86197 /*! MC_HL
86198  *  0b0..Write access (increment) is allowed.
86199  *  0b1..Write access (increment) is not allowed.
86200  */
86201 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
86202 
86203 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
86204 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
86205 /*! GPR_HL
86206  *  0b0..Write access is allowed.
86207  *  0b1..Write access is not allowed.
86208  */
86209 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
86210 
86211 #define SNVS_LPLR_LPSVCR_HL_MASK                 (0x40U)
86212 #define SNVS_LPLR_LPSVCR_HL_SHIFT                (6U)
86213 /*! LPSVCR_HL
86214  *  0b0..Write access is allowed.
86215  *  0b1..Write access is not allowed.
86216  */
86217 #define SNVS_LPLR_LPSVCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
86218 
86219 #define SNVS_LPLR_LPTGFCR_HL_MASK                (0x80U)
86220 #define SNVS_LPLR_LPTGFCR_HL_SHIFT               (7U)
86221 /*! LPTGFCR_HL
86222  *  0b0..Write access is allowed.
86223  *  0b1..Write access is not allowed.
86224  */
86225 #define SNVS_LPLR_LPTGFCR_HL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
86226 
86227 #define SNVS_LPLR_LPSECR_HL_MASK                 (0x100U)
86228 #define SNVS_LPLR_LPSECR_HL_SHIFT                (8U)
86229 /*! LPSECR_HL
86230  *  0b0..Write access is allowed.
86231  *  0b1..Write access is not allowed.
86232  */
86233 #define SNVS_LPLR_LPSECR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
86234 
86235 #define SNVS_LPLR_MKS_HL_MASK                    (0x200U)
86236 #define SNVS_LPLR_MKS_HL_SHIFT                   (9U)
86237 /*! MKS_HL
86238  *  0b0..Write access is allowed.
86239  *  0b1..Write access is not allowed.
86240  */
86241 #define SNVS_LPLR_MKS_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
86242 
86243 #define SNVS_LPLR_AT1_HL_MASK                    (0x1000000U)
86244 #define SNVS_LPLR_AT1_HL_SHIFT                   (24U)
86245 /*! AT1_HL
86246  *  0b0..Write access is allowed.
86247  *  0b1..Write access is not allowed.
86248  */
86249 #define SNVS_LPLR_AT1_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
86250 
86251 #define SNVS_LPLR_AT2_HL_MASK                    (0x2000000U)
86252 #define SNVS_LPLR_AT2_HL_SHIFT                   (25U)
86253 /*! AT2_HL
86254  *  0b0..Write access is allowed.
86255  *  0b1..Write access is not allowed.
86256  */
86257 #define SNVS_LPLR_AT2_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
86258 
86259 #define SNVS_LPLR_AT3_HL_MASK                    (0x4000000U)
86260 #define SNVS_LPLR_AT3_HL_SHIFT                   (26U)
86261 /*! AT3_HL
86262  *  0b0..Write access is allowed.
86263  *  0b1..Write access is not allowed.
86264  */
86265 #define SNVS_LPLR_AT3_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
86266 
86267 #define SNVS_LPLR_AT4_HL_MASK                    (0x8000000U)
86268 #define SNVS_LPLR_AT4_HL_SHIFT                   (27U)
86269 /*! AT4_HL
86270  *  0b0..Write access is allowed.
86271  *  0b1..Write access is not allowed.
86272  */
86273 #define SNVS_LPLR_AT4_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
86274 
86275 #define SNVS_LPLR_AT5_HL_MASK                    (0x10000000U)
86276 #define SNVS_LPLR_AT5_HL_SHIFT                   (28U)
86277 /*! AT5_HL
86278  *  0b0..Write access is allowed.
86279  *  0b1..Write access is not allowed.
86280  */
86281 #define SNVS_LPLR_AT5_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
86282 /*! @} */
86283 
86284 /*! @name LPCR - SNVS_LP Control Register */
86285 /*! @{ */
86286 
86287 #define SNVS_LPCR_SRTC_ENV_MASK                  (0x1U)
86288 #define SNVS_LPCR_SRTC_ENV_SHIFT                 (0U)
86289 /*! SRTC_ENV
86290  *  0b0..SRTC is disabled or invalid.
86291  *  0b1..SRTC is enabled and valid.
86292  */
86293 #define SNVS_LPCR_SRTC_ENV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
86294 
86295 #define SNVS_LPCR_LPTA_EN_MASK                   (0x2U)
86296 #define SNVS_LPCR_LPTA_EN_SHIFT                  (1U)
86297 /*! LPTA_EN
86298  *  0b0..LP time alarm interrupt is disabled.
86299  *  0b1..LP time alarm interrupt is enabled.
86300  */
86301 #define SNVS_LPCR_LPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
86302 
86303 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
86304 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
86305 /*! MC_ENV
86306  *  0b0..MC is disabled or invalid.
86307  *  0b1..MC is enabled and valid.
86308  */
86309 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
86310 
86311 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
86312 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
86313 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
86314 
86315 #define SNVS_LPCR_SRTC_INV_EN_MASK               (0x10U)
86316 #define SNVS_LPCR_SRTC_INV_EN_SHIFT              (4U)
86317 /*! SRTC_INV_EN
86318  *  0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)).
86319  *  0b1..SRTC is invalidated in the case of security violation.
86320  */
86321 #define SNVS_LPCR_SRTC_INV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
86322 
86323 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
86324 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
86325 /*! DP_EN
86326  *  0b0..Smart PMIC enabled.
86327  *  0b1..Dumb PMIC enabled.
86328  */
86329 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
86330 
86331 #define SNVS_LPCR_TOP_MASK                       (0x40U)
86332 #define SNVS_LPCR_TOP_SHIFT                      (6U)
86333 /*! TOP
86334  *  0b0..Leave system power on.
86335  *  0b1..Turn off system power.
86336  */
86337 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
86338 
86339 #define SNVS_LPCR_LVD_EN_MASK                    (0x80U)
86340 #define SNVS_LPCR_LVD_EN_SHIFT                   (7U)
86341 #define SNVS_LPCR_LVD_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
86342 
86343 #define SNVS_LPCR_LPCALB_EN_MASK                 (0x100U)
86344 #define SNVS_LPCR_LPCALB_EN_SHIFT                (8U)
86345 /*! LPCALB_EN
86346  *  0b0..SRTC Time calibration is disabled.
86347  *  0b1..SRTC Time calibration is enabled.
86348  */
86349 #define SNVS_LPCR_LPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
86350 
86351 #define SNVS_LPCR_LPCALB_VAL_MASK                (0x7C00U)
86352 #define SNVS_LPCR_LPCALB_VAL_SHIFT               (10U)
86353 /*! LPCALB_VAL
86354  *  0b00000..+0 counts per each 32768 ticks of the counter clock
86355  *  0b00001..+1 counts per each 32768 ticks of the counter clock
86356  *  0b00010..+2 counts per each 32768 ticks of the counter clock
86357  *  0b01111..+15 counts per each 32768 ticks of the counter clock
86358  *  0b10000..-16 counts per each 32768 ticks of the counter clock
86359  *  0b10001..-15 counts per each 32768 ticks of the counter clock
86360  *  0b11110..-2 counts per each 32768 ticks of the counter clock
86361  *  0b11111..-1 counts per each 32768 ticks of the counter clock
86362  */
86363 #define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
86364 
86365 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
86366 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
86367 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
86368 
86369 #define SNVS_LPCR_DEBOUNCE_MASK                  (0xC0000U)
86370 #define SNVS_LPCR_DEBOUNCE_SHIFT                 (18U)
86371 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
86372 
86373 #define SNVS_LPCR_ON_TIME_MASK                   (0x300000U)
86374 #define SNVS_LPCR_ON_TIME_SHIFT                  (20U)
86375 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
86376 
86377 #define SNVS_LPCR_PK_EN_MASK                     (0x400000U)
86378 #define SNVS_LPCR_PK_EN_SHIFT                    (22U)
86379 #define SNVS_LPCR_PK_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
86380 
86381 #define SNVS_LPCR_PK_OVERRIDE_MASK               (0x800000U)
86382 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              (23U)
86383 #define SNVS_LPCR_PK_OVERRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
86384 
86385 #define SNVS_LPCR_GPR_Z_DIS_MASK                 (0x1000000U)
86386 #define SNVS_LPCR_GPR_Z_DIS_SHIFT                (24U)
86387 #define SNVS_LPCR_GPR_Z_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
86388 /*! @} */
86389 
86390 /*! @name LPMKCR - SNVS_LP Master Key Control Register */
86391 /*! @{ */
86392 
86393 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          (0x3U)
86394 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         (0U)
86395 /*! MASTER_KEY_SEL
86396  *  0b0x..Select one time programmable master key.
86397  *  0b10..Select zeroizable master key when MKS_EN bit is set .
86398  *  0b11..Select combined master key when MKS_EN bit is set .
86399  */
86400 #define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
86401 
86402 #define SNVS_LPMKCR_ZMK_HWP_MASK                 (0x4U)
86403 #define SNVS_LPMKCR_ZMK_HWP_SHIFT                (2U)
86404 /*! ZMK_HWP
86405  *  0b0..ZMK is in the software programming mode.
86406  *  0b1..ZMK is in the hardware programming mode.
86407  */
86408 #define SNVS_LPMKCR_ZMK_HWP(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
86409 
86410 #define SNVS_LPMKCR_ZMK_VAL_MASK                 (0x8U)
86411 #define SNVS_LPMKCR_ZMK_VAL_SHIFT                (3U)
86412 /*! ZMK_VAL
86413  *  0b0..ZMK is not valid.
86414  *  0b1..ZMK is valid.
86415  */
86416 #define SNVS_LPMKCR_ZMK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
86417 
86418 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK              (0x10U)
86419 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             (4U)
86420 /*! ZMK_ECC_EN
86421  *  0b0..ZMK ECC check is disabled.
86422  *  0b1..ZMK ECC check is enabled.
86423  */
86424 #define SNVS_LPMKCR_ZMK_ECC_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
86425 
86426 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           (0xFF80U)
86427 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          (7U)
86428 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
86429 /*! @} */
86430 
86431 /*! @name LPSVCR - SNVS_LP Security Violation Control Register */
86432 /*! @{ */
86433 
86434 #define SNVS_LPSVCR_CAAM_EN_MASK                 (0x1U)
86435 #define SNVS_LPSVCR_CAAM_EN_SHIFT                (0U)
86436 /*! CAAM_EN
86437  *  0b0..CAAM Security Violation is disabled in the LP domain.
86438  *  0b1..CAAM Security Violation is enabled in the LP domain.
86439  */
86440 #define SNVS_LPSVCR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
86441 
86442 #define SNVS_LPSVCR_JTAGC_EN_MASK                (0x2U)
86443 #define SNVS_LPSVCR_JTAGC_EN_SHIFT               (1U)
86444 /*! JTAGC_EN
86445  *  0b0..JTAG Active is disabled in the LP domain.
86446  *  0b1..JTAG Active is enabled in the LP domain.
86447  */
86448 #define SNVS_LPSVCR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
86449 
86450 #define SNVS_LPSVCR_WDOG2_EN_MASK                (0x4U)
86451 #define SNVS_LPSVCR_WDOG2_EN_SHIFT               (2U)
86452 /*! WDOG2_EN
86453  *  0b0..Watchdog 2 Reset is disabled in the LP domain.
86454  *  0b1..Watchdog 2 Reset is enabled in the LP domain.
86455  */
86456 #define SNVS_LPSVCR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
86457 
86458 #define SNVS_LPSVCR_SRC_EN_MASK                  (0x10U)
86459 #define SNVS_LPSVCR_SRC_EN_SHIFT                 (4U)
86460 /*! SRC_EN
86461  *  0b0..Internal Boot is disabled in the LP domain.
86462  *  0b1..Internal Boot is enabled in the LP domain.
86463  */
86464 #define SNVS_LPSVCR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
86465 
86466 #define SNVS_LPSVCR_OCOTP_EN_MASK                (0x20U)
86467 #define SNVS_LPSVCR_OCOTP_EN_SHIFT               (5U)
86468 /*! OCOTP_EN
86469  *  0b0..OCOTP attack error is disabled in the LP domain.
86470  *  0b1..OCOTP attack error is enabled in the LP domain.
86471  */
86472 #define SNVS_LPSVCR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
86473 /*! @} */
86474 
86475 /*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */
86476 /*! @{ */
86477 
86478 #define SNVS_LPTGFCR_WMTGF_MASK                  (0x1FU)
86479 #define SNVS_LPTGFCR_WMTGF_SHIFT                 (0U)
86480 #define SNVS_LPTGFCR_WMTGF(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
86481 
86482 #define SNVS_LPTGFCR_WMTGF_EN_MASK               (0x80U)
86483 #define SNVS_LPTGFCR_WMTGF_EN_SHIFT              (7U)
86484 /*! WMTGF_EN
86485  *  0b0..Wire-mesh tamper glitch filter is bypassed.
86486  *  0b1..Wire-mesh tamper glitch filter is enabled.
86487  */
86488 #define SNVS_LPTGFCR_WMTGF_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
86489 
86490 #define SNVS_LPTGFCR_ETGF1_MASK                  (0x7F0000U)
86491 #define SNVS_LPTGFCR_ETGF1_SHIFT                 (16U)
86492 #define SNVS_LPTGFCR_ETGF1(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
86493 
86494 #define SNVS_LPTGFCR_ETGF1_EN_MASK               (0x800000U)
86495 #define SNVS_LPTGFCR_ETGF1_EN_SHIFT              (23U)
86496 /*! ETGF1_EN
86497  *  0b0..External tamper glitch filter 1 is bypassed.
86498  *  0b1..External tamper glitch filter 1 is enabled.
86499  */
86500 #define SNVS_LPTGFCR_ETGF1_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
86501 
86502 #define SNVS_LPTGFCR_ETGF2_MASK                  (0x7F000000U)
86503 #define SNVS_LPTGFCR_ETGF2_SHIFT                 (24U)
86504 #define SNVS_LPTGFCR_ETGF2(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
86505 
86506 #define SNVS_LPTGFCR_ETGF2_EN_MASK               (0x80000000U)
86507 #define SNVS_LPTGFCR_ETGF2_EN_SHIFT              (31U)
86508 /*! ETGF2_EN
86509  *  0b0..External tamper glitch filter 2 is bypassed.
86510  *  0b1..External tamper glitch filter 2 is enabled.
86511  */
86512 #define SNVS_LPTGFCR_ETGF2_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
86513 /*! @} */
86514 
86515 /*! @name LPTDCR - SNVS_LP Tamper Detect Configuration Register */
86516 /*! @{ */
86517 
86518 #define SNVS_LPTDCR_SRTCR_EN_MASK                (0x2U)
86519 #define SNVS_LPTDCR_SRTCR_EN_SHIFT               (1U)
86520 /*! SRTCR_EN
86521  *  0b0..SRTC rollover is disabled.
86522  *  0b1..SRTC rollover is enabled.
86523  */
86524 #define SNVS_LPTDCR_SRTCR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
86525 
86526 #define SNVS_LPTDCR_MCR_EN_MASK                  (0x4U)
86527 #define SNVS_LPTDCR_MCR_EN_SHIFT                 (2U)
86528 /*! MCR_EN
86529  *  0b0..MC rollover is disabled.
86530  *  0b1..MC rollover is enabled.
86531  */
86532 #define SNVS_LPTDCR_MCR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
86533 
86534 #define SNVS_LPTDCR_CT_EN_MASK                   (0x10U)
86535 #define SNVS_LPTDCR_CT_EN_SHIFT                  (4U)
86536 /*! CT_EN
86537  *  0b0..Clock tamper is disabled.
86538  *  0b1..Clock tamper is enabled.
86539  */
86540 #define SNVS_LPTDCR_CT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
86541 
86542 #define SNVS_LPTDCR_TT_EN_MASK                   (0x20U)
86543 #define SNVS_LPTDCR_TT_EN_SHIFT                  (5U)
86544 /*! TT_EN
86545  *  0b0..Temperature tamper is disabled.
86546  *  0b1..Temperature tamper is enabled.
86547  */
86548 #define SNVS_LPTDCR_TT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
86549 
86550 #define SNVS_LPTDCR_VT_EN_MASK                   (0x40U)
86551 #define SNVS_LPTDCR_VT_EN_SHIFT                  (6U)
86552 /*! VT_EN
86553  *  0b0..Voltage tamper is disabled.
86554  *  0b1..Voltage tamper is enabled.
86555  */
86556 #define SNVS_LPTDCR_VT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
86557 
86558 #define SNVS_LPTDCR_WMT1_EN_MASK                 (0x80U)
86559 #define SNVS_LPTDCR_WMT1_EN_SHIFT                (7U)
86560 /*! WMT1_EN
86561  *  0b0..Wire-mesh tamper 1 is disabled.
86562  *  0b1..Wire-mesh tamper 1 is enabled.
86563  */
86564 #define SNVS_LPTDCR_WMT1_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
86565 
86566 #define SNVS_LPTDCR_WMT2_EN_MASK                 (0x100U)
86567 #define SNVS_LPTDCR_WMT2_EN_SHIFT                (8U)
86568 /*! WMT2_EN
86569  *  0b0..Wire-mesh tamper 2 is disabled.
86570  *  0b1..Wire-mesh tamper 2 is enabled.
86571  */
86572 #define SNVS_LPTDCR_WMT2_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
86573 
86574 #define SNVS_LPTDCR_ET1_EN_MASK                  (0x200U)
86575 #define SNVS_LPTDCR_ET1_EN_SHIFT                 (9U)
86576 /*! ET1_EN
86577  *  0b0..External tamper 1 is disabled.
86578  *  0b1..External tamper 1 is enabled.
86579  */
86580 #define SNVS_LPTDCR_ET1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
86581 
86582 #define SNVS_LPTDCR_ET2_EN_MASK                  (0x400U)
86583 #define SNVS_LPTDCR_ET2_EN_SHIFT                 (10U)
86584 /*! ET2_EN
86585  *  0b0..External tamper 2 is disabled.
86586  *  0b1..External tamper 2 is enabled.
86587  */
86588 #define SNVS_LPTDCR_ET2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
86589 
86590 #define SNVS_LPTDCR_ET1P_MASK                    (0x800U)
86591 #define SNVS_LPTDCR_ET1P_SHIFT                   (11U)
86592 /*! ET1P
86593  *  0b0..External tamper 1 is active low.
86594  *  0b1..External tamper 1 is active high.
86595  */
86596 #define SNVS_LPTDCR_ET1P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
86597 
86598 #define SNVS_LPTDCR_ET2P_MASK                    (0x1000U)
86599 #define SNVS_LPTDCR_ET2P_SHIFT                   (12U)
86600 /*! ET2P
86601  *  0b0..External tamper 2 is active low.
86602  *  0b1..External tamper 2 is active high.
86603  */
86604 #define SNVS_LPTDCR_ET2P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
86605 
86606 #define SNVS_LPTDCR_PFD_OBSERV_MASK              (0x4000U)
86607 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT             (14U)
86608 #define SNVS_LPTDCR_PFD_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
86609 
86610 #define SNVS_LPTDCR_POR_OBSERV_MASK              (0x8000U)
86611 #define SNVS_LPTDCR_POR_OBSERV_SHIFT             (15U)
86612 #define SNVS_LPTDCR_POR_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
86613 
86614 #define SNVS_LPTDCR_LTDC_MASK                    (0x70000U)
86615 #define SNVS_LPTDCR_LTDC_SHIFT                   (16U)
86616 #define SNVS_LPTDCR_LTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
86617 
86618 #define SNVS_LPTDCR_HTDC_MASK                    (0x700000U)
86619 #define SNVS_LPTDCR_HTDC_SHIFT                   (20U)
86620 #define SNVS_LPTDCR_HTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
86621 
86622 #define SNVS_LPTDCR_VRC_MASK                     (0x7000000U)
86623 #define SNVS_LPTDCR_VRC_SHIFT                    (24U)
86624 #define SNVS_LPTDCR_VRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
86625 
86626 #define SNVS_LPTDCR_OSCB_MASK                    (0x10000000U)
86627 #define SNVS_LPTDCR_OSCB_SHIFT                   (28U)
86628 /*! OSCB
86629  *  0b0..Normal SRTC clock oscillator not bypassed.
86630  *  0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
86631  */
86632 #define SNVS_LPTDCR_OSCB(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
86633 /*! @} */
86634 
86635 /*! @name LPSR - SNVS_LP Status Register */
86636 /*! @{ */
86637 
86638 #define SNVS_LPSR_LPTA_MASK                      (0x1U)
86639 #define SNVS_LPSR_LPTA_SHIFT                     (0U)
86640 /*! LPTA
86641  *  0b0..No time alarm interrupt occurred.
86642  *  0b1..A time alarm interrupt occurred.
86643  */
86644 #define SNVS_LPSR_LPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
86645 
86646 #define SNVS_LPSR_SRTCR_MASK                     (0x2U)
86647 #define SNVS_LPSR_SRTCR_SHIFT                    (1U)
86648 /*! SRTCR
86649  *  0b0..SRTC has not reached its maximum value.
86650  *  0b1..SRTC has reached its maximum value.
86651  */
86652 #define SNVS_LPSR_SRTCR(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
86653 
86654 #define SNVS_LPSR_MCR_MASK                       (0x4U)
86655 #define SNVS_LPSR_MCR_SHIFT                      (2U)
86656 /*! MCR
86657  *  0b0..MC has not reached its maximum value.
86658  *  0b1..MC has reached its maximum value.
86659  */
86660 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
86661 
86662 #define SNVS_LPSR_LVD_MASK                       (0x8U)
86663 #define SNVS_LPSR_LVD_SHIFT                      (3U)
86664 /*! LVD
86665  *  0b0..No low voltage event detected.
86666  *  0b1..Low voltage event is detected.
86667  */
86668 #define SNVS_LPSR_LVD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
86669 
86670 #define SNVS_LPSR_CTD_MASK                       (0x10U)
86671 #define SNVS_LPSR_CTD_SHIFT                      (4U)
86672 /*! CTD
86673  *  0b0..No clock tamper.
86674  *  0b1..Clock tamper is detected.
86675  */
86676 #define SNVS_LPSR_CTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
86677 
86678 #define SNVS_LPSR_TTD_MASK                       (0x20U)
86679 #define SNVS_LPSR_TTD_SHIFT                      (5U)
86680 /*! TTD
86681  *  0b0..No temperature tamper.
86682  *  0b1..Temperature tamper is detected.
86683  */
86684 #define SNVS_LPSR_TTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
86685 
86686 #define SNVS_LPSR_VTD_MASK                       (0x40U)
86687 #define SNVS_LPSR_VTD_SHIFT                      (6U)
86688 /*! VTD
86689  *  0b0..Voltage tampering not detected.
86690  *  0b1..Voltage tampering detected.
86691  */
86692 #define SNVS_LPSR_VTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
86693 
86694 #define SNVS_LPSR_WMT1D_MASK                     (0x80U)
86695 #define SNVS_LPSR_WMT1D_SHIFT                    (7U)
86696 /*! WMT1D
86697  *  0b0..Wire-mesh tampering 1 not detected.
86698  *  0b1..Wire-mesh tampering 1 detected.
86699  */
86700 #define SNVS_LPSR_WMT1D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
86701 
86702 #define SNVS_LPSR_WMT2D_MASK                     (0x100U)
86703 #define SNVS_LPSR_WMT2D_SHIFT                    (8U)
86704 /*! WMT2D
86705  *  0b0..Wire-mesh tampering 2 not detected.
86706  *  0b1..Wire-mesh tampering 2 detected.
86707  */
86708 #define SNVS_LPSR_WMT2D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
86709 
86710 #define SNVS_LPSR_ET1D_MASK                      (0x200U)
86711 #define SNVS_LPSR_ET1D_SHIFT                     (9U)
86712 /*! ET1D
86713  *  0b0..External tampering 1 not detected.
86714  *  0b1..External tampering 1 detected.
86715  */
86716 #define SNVS_LPSR_ET1D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
86717 
86718 #define SNVS_LPSR_ET2D_MASK                      (0x400U)
86719 #define SNVS_LPSR_ET2D_SHIFT                     (10U)
86720 /*! ET2D
86721  *  0b0..External tampering 2 not detected.
86722  *  0b1..External tampering 2 detected.
86723  */
86724 #define SNVS_LPSR_ET2D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
86725 
86726 #define SNVS_LPSR_ESVD_MASK                      (0x10000U)
86727 #define SNVS_LPSR_ESVD_SHIFT                     (16U)
86728 /*! ESVD
86729  *  0b0..No external security violation.
86730  *  0b1..External security violation is detected.
86731  */
86732 #define SNVS_LPSR_ESVD(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
86733 
86734 #define SNVS_LPSR_EO_MASK                        (0x20000U)
86735 #define SNVS_LPSR_EO_SHIFT                       (17U)
86736 /*! EO
86737  *  0b0..Emergency off was not detected.
86738  *  0b1..Emergency off was detected.
86739  */
86740 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
86741 
86742 #define SNVS_LPSR_SPOF_MASK                      (0x40000U)
86743 #define SNVS_LPSR_SPOF_SHIFT                     (18U)
86744 /*! SPOF
86745  *  0b0..Set Power Off was not detected.
86746  *  0b1..Set Power Off was detected.
86747  */
86748 #define SNVS_LPSR_SPOF(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
86749 
86750 #define SNVS_LPSR_LPNS_MASK                      (0x40000000U)
86751 #define SNVS_LPSR_LPNS_SHIFT                     (30U)
86752 /*! LPNS
86753  *  0b0..LP section was not programmed in the non-secure state.
86754  *  0b1..LP section was programmed in the non-secure state.
86755  */
86756 #define SNVS_LPSR_LPNS(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
86757 
86758 #define SNVS_LPSR_LPS_MASK                       (0x80000000U)
86759 #define SNVS_LPSR_LPS_SHIFT                      (31U)
86760 /*! LPS
86761  *  0b0..LP section was not programmed in secure or trusted state.
86762  *  0b1..LP section was programmed in secure or trusted state.
86763  */
86764 #define SNVS_LPSR_LPS(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
86765 /*! @} */
86766 
86767 /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
86768 /*! @{ */
86769 
86770 #define SNVS_LPSRTCMR_SRTC_MASK                  (0x7FFFU)
86771 #define SNVS_LPSRTCMR_SRTC_SHIFT                 (0U)
86772 #define SNVS_LPSRTCMR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
86773 /*! @} */
86774 
86775 /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
86776 /*! @{ */
86777 
86778 #define SNVS_LPSRTCLR_SRTC_MASK                  (0xFFFFFFFFU)
86779 #define SNVS_LPSRTCLR_SRTC_SHIFT                 (0U)
86780 #define SNVS_LPSRTCLR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
86781 /*! @} */
86782 
86783 /*! @name LPTAR - SNVS_LP Time Alarm Register */
86784 /*! @{ */
86785 
86786 #define SNVS_LPTAR_LPTA_MASK                     (0xFFFFFFFFU)
86787 #define SNVS_LPTAR_LPTA_SHIFT                    (0U)
86788 #define SNVS_LPTAR_LPTA(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
86789 /*! @} */
86790 
86791 /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
86792 /*! @{ */
86793 
86794 #define SNVS_LPSMCMR_MON_COUNTER_MASK            (0xFFFFU)
86795 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           (0U)
86796 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
86797 
86798 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            (0xFFFF0000U)
86799 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           (16U)
86800 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
86801 /*! @} */
86802 
86803 /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
86804 /*! @{ */
86805 
86806 #define SNVS_LPSMCLR_MON_COUNTER_MASK            (0xFFFFFFFFU)
86807 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           (0U)
86808 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
86809 /*! @} */
86810 
86811 /*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */
86812 /*! @{ */
86813 
86814 #define SNVS_LPLVDR_LVD_MASK                     (0xFFFFFFFFU)
86815 #define SNVS_LPLVDR_LVD_SHIFT                    (0U)
86816 #define SNVS_LPLVDR_LVD(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
86817 /*! @} */
86818 
86819 /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
86820 /*! @{ */
86821 
86822 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK        (0xFFFFFFFFU)
86823 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT       (0U)
86824 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
86825 /*! @} */
86826 
86827 /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
86828 /*! @{ */
86829 
86830 #define SNVS_LPZMKR_ZMK_MASK                     (0xFFFFFFFFU)
86831 #define SNVS_LPZMKR_ZMK_SHIFT                    (0U)
86832 #define SNVS_LPZMKR_ZMK(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
86833 /*! @} */
86834 
86835 /* The count of SNVS_LPZMKR */
86836 #define SNVS_LPZMKR_COUNT                        (8U)
86837 
86838 /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
86839 /*! @{ */
86840 
86841 #define SNVS_LPGPR_ALIAS_GPR_MASK                (0xFFFFFFFFU)
86842 #define SNVS_LPGPR_ALIAS_GPR_SHIFT               (0U)
86843 #define SNVS_LPGPR_ALIAS_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
86844 /*! @} */
86845 
86846 /* The count of SNVS_LPGPR_ALIAS */
86847 #define SNVS_LPGPR_ALIAS_COUNT                   (4U)
86848 
86849 /*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */
86850 /*! @{ */
86851 
86852 #define SNVS_LPTDC2R_ET3_EN_MASK                 (0x1U)
86853 #define SNVS_LPTDC2R_ET3_EN_SHIFT                (0U)
86854 /*! ET3_EN
86855  *  0b0..External tamper 3 is disabled.
86856  *  0b1..External tamper 3 is enabled.
86857  */
86858 #define SNVS_LPTDC2R_ET3_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
86859 
86860 #define SNVS_LPTDC2R_ET4_EN_MASK                 (0x2U)
86861 #define SNVS_LPTDC2R_ET4_EN_SHIFT                (1U)
86862 /*! ET4_EN
86863  *  0b0..External tamper 4 is disabled.
86864  *  0b1..External tamper 4 is enabled.
86865  */
86866 #define SNVS_LPTDC2R_ET4_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
86867 
86868 #define SNVS_LPTDC2R_ET5_EN_MASK                 (0x4U)
86869 #define SNVS_LPTDC2R_ET5_EN_SHIFT                (2U)
86870 /*! ET5_EN
86871  *  0b0..External tamper 5 is disabled.
86872  *  0b1..External tamper 5 is enabled.
86873  */
86874 #define SNVS_LPTDC2R_ET5_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
86875 
86876 #define SNVS_LPTDC2R_ET6_EN_MASK                 (0x8U)
86877 #define SNVS_LPTDC2R_ET6_EN_SHIFT                (3U)
86878 /*! ET6_EN
86879  *  0b0..External tamper 6 is disabled.
86880  *  0b1..External tamper 6 is enabled.
86881  */
86882 #define SNVS_LPTDC2R_ET6_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
86883 
86884 #define SNVS_LPTDC2R_ET7_EN_MASK                 (0x10U)
86885 #define SNVS_LPTDC2R_ET7_EN_SHIFT                (4U)
86886 /*! ET7_EN
86887  *  0b0..External tamper 7 is disabled.
86888  *  0b1..External tamper 7 is enabled.
86889  */
86890 #define SNVS_LPTDC2R_ET7_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
86891 
86892 #define SNVS_LPTDC2R_ET8_EN_MASK                 (0x20U)
86893 #define SNVS_LPTDC2R_ET8_EN_SHIFT                (5U)
86894 /*! ET8_EN
86895  *  0b0..External tamper 8 is disabled.
86896  *  0b1..External tamper 8 is enabled.
86897  */
86898 #define SNVS_LPTDC2R_ET8_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
86899 
86900 #define SNVS_LPTDC2R_ET9_EN_MASK                 (0x40U)
86901 #define SNVS_LPTDC2R_ET9_EN_SHIFT                (6U)
86902 /*! ET9_EN
86903  *  0b0..External tamper 9 is disabled.
86904  *  0b1..External tamper 9 is enabled.
86905  */
86906 #define SNVS_LPTDC2R_ET9_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
86907 
86908 #define SNVS_LPTDC2R_ET10_EN_MASK                (0x80U)
86909 #define SNVS_LPTDC2R_ET10_EN_SHIFT               (7U)
86910 /*! ET10_EN
86911  *  0b0..External tamper 10 is disabled.
86912  *  0b1..External tamper 10 is enabled.
86913  */
86914 #define SNVS_LPTDC2R_ET10_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
86915 
86916 #define SNVS_LPTDC2R_ET3P_MASK                   (0x10000U)
86917 #define SNVS_LPTDC2R_ET3P_SHIFT                  (16U)
86918 /*! ET3P
86919  *  0b0..External tamper 3 active low.
86920  *  0b1..External tamper 3 active high.
86921  */
86922 #define SNVS_LPTDC2R_ET3P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
86923 
86924 #define SNVS_LPTDC2R_ET4P_MASK                   (0x20000U)
86925 #define SNVS_LPTDC2R_ET4P_SHIFT                  (17U)
86926 /*! ET4P
86927  *  0b0..External tamper 4 is active low.
86928  *  0b1..External tamper 4 is active high.
86929  */
86930 #define SNVS_LPTDC2R_ET4P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
86931 
86932 #define SNVS_LPTDC2R_ET5P_MASK                   (0x40000U)
86933 #define SNVS_LPTDC2R_ET5P_SHIFT                  (18U)
86934 /*! ET5P
86935  *  0b0..External tamper 5 is active low.
86936  *  0b1..External tamper 5 is active high.
86937  */
86938 #define SNVS_LPTDC2R_ET5P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
86939 
86940 #define SNVS_LPTDC2R_ET6P_MASK                   (0x80000U)
86941 #define SNVS_LPTDC2R_ET6P_SHIFT                  (19U)
86942 /*! ET6P
86943  *  0b0..External tamper 6 is active low.
86944  *  0b1..External tamper 6 is active high.
86945  */
86946 #define SNVS_LPTDC2R_ET6P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
86947 
86948 #define SNVS_LPTDC2R_ET7P_MASK                   (0x100000U)
86949 #define SNVS_LPTDC2R_ET7P_SHIFT                  (20U)
86950 /*! ET7P
86951  *  0b0..External tamper 7 is active low.
86952  *  0b1..External tamper 7 is active high.
86953  */
86954 #define SNVS_LPTDC2R_ET7P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
86955 
86956 #define SNVS_LPTDC2R_ET8P_MASK                   (0x200000U)
86957 #define SNVS_LPTDC2R_ET8P_SHIFT                  (21U)
86958 /*! ET8P
86959  *  0b0..External tamper 8 is active low.
86960  *  0b1..External tamper 8 is active high.
86961  */
86962 #define SNVS_LPTDC2R_ET8P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
86963 
86964 #define SNVS_LPTDC2R_ET9P_MASK                   (0x400000U)
86965 #define SNVS_LPTDC2R_ET9P_SHIFT                  (22U)
86966 /*! ET9P
86967  *  0b0..External tamper 9 is active low.
86968  *  0b1..External tamper 9 is active high.
86969  */
86970 #define SNVS_LPTDC2R_ET9P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
86971 
86972 #define SNVS_LPTDC2R_ET10P_MASK                  (0x800000U)
86973 #define SNVS_LPTDC2R_ET10P_SHIFT                 (23U)
86974 /*! ET10P
86975  *  0b0..External tamper 10 is active low.
86976  *  0b1..External tamper 10 is active high.
86977  */
86978 #define SNVS_LPTDC2R_ET10P(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
86979 /*! @} */
86980 
86981 /*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */
86982 /*! @{ */
86983 
86984 #define SNVS_LPTDSR_ET3D_MASK                    (0x1U)
86985 #define SNVS_LPTDSR_ET3D_SHIFT                   (0U)
86986 /*! ET3D
86987  *  0b0..External tamper 3 is not detected.
86988  *  0b1..External tamper 3 is detected.
86989  */
86990 #define SNVS_LPTDSR_ET3D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
86991 
86992 #define SNVS_LPTDSR_ET4D_MASK                    (0x2U)
86993 #define SNVS_LPTDSR_ET4D_SHIFT                   (1U)
86994 /*! ET4D
86995  *  0b0..External tamper 4 is not detected.
86996  *  0b1..External tamper 4 is detected.
86997  */
86998 #define SNVS_LPTDSR_ET4D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
86999 
87000 #define SNVS_LPTDSR_ET5D_MASK                    (0x4U)
87001 #define SNVS_LPTDSR_ET5D_SHIFT                   (2U)
87002 /*! ET5D
87003  *  0b0..External tamper 5 is not detected.
87004  *  0b1..External tamper 5 is detected.
87005  */
87006 #define SNVS_LPTDSR_ET5D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
87007 
87008 #define SNVS_LPTDSR_ET6D_MASK                    (0x8U)
87009 #define SNVS_LPTDSR_ET6D_SHIFT                   (3U)
87010 /*! ET6D
87011  *  0b0..External tamper 6 is not detected.
87012  *  0b1..External tamper 6 is detected.
87013  */
87014 #define SNVS_LPTDSR_ET6D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
87015 
87016 #define SNVS_LPTDSR_ET7D_MASK                    (0x10U)
87017 #define SNVS_LPTDSR_ET7D_SHIFT                   (4U)
87018 /*! ET7D
87019  *  0b0..External tamper 7 is not detected.
87020  *  0b1..External tamper 7 is detected.
87021  */
87022 #define SNVS_LPTDSR_ET7D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
87023 
87024 #define SNVS_LPTDSR_ET8D_MASK                    (0x20U)
87025 #define SNVS_LPTDSR_ET8D_SHIFT                   (5U)
87026 /*! ET8D
87027  *  0b0..External tamper 8 is not detected.
87028  *  0b1..External tamper 8 is detected.
87029  */
87030 #define SNVS_LPTDSR_ET8D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
87031 
87032 #define SNVS_LPTDSR_ET9D_MASK                    (0x40U)
87033 #define SNVS_LPTDSR_ET9D_SHIFT                   (6U)
87034 /*! ET9D
87035  *  0b0..External tamper 9 is not detected.
87036  *  0b1..External tamper 9 is detected.
87037  */
87038 #define SNVS_LPTDSR_ET9D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
87039 
87040 #define SNVS_LPTDSR_ET10D_MASK                   (0x80U)
87041 #define SNVS_LPTDSR_ET10D_SHIFT                  (7U)
87042 /*! ET10D
87043  *  0b0..External tamper 10 is not detected.
87044  *  0b1..External tamper 10 is detected.
87045  */
87046 #define SNVS_LPTDSR_ET10D(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
87047 /*! @} */
87048 
87049 /*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */
87050 /*! @{ */
87051 
87052 #define SNVS_LPTGF1CR_ETGF3_MASK                 (0x7FU)
87053 #define SNVS_LPTGF1CR_ETGF3_SHIFT                (0U)
87054 #define SNVS_LPTGF1CR_ETGF3(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
87055 
87056 #define SNVS_LPTGF1CR_ETGF3_EN_MASK              (0x80U)
87057 #define SNVS_LPTGF1CR_ETGF3_EN_SHIFT             (7U)
87058 /*! ETGF3_EN
87059  *  0b0..External tamper glitch filter 3 is bypassed.
87060  *  0b1..External tamper glitch filter 3 is enabled.
87061  */
87062 #define SNVS_LPTGF1CR_ETGF3_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
87063 
87064 #define SNVS_LPTGF1CR_ETGF4_MASK                 (0x7F00U)
87065 #define SNVS_LPTGF1CR_ETGF4_SHIFT                (8U)
87066 #define SNVS_LPTGF1CR_ETGF4(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
87067 
87068 #define SNVS_LPTGF1CR_ETGF4_EN_MASK              (0x8000U)
87069 #define SNVS_LPTGF1CR_ETGF4_EN_SHIFT             (15U)
87070 /*! ETGF4_EN
87071  *  0b0..External tamper glitch filter 4 is bypassed.
87072  *  0b1..External tamper glitch filter 4 is enabled.
87073  */
87074 #define SNVS_LPTGF1CR_ETGF4_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
87075 
87076 #define SNVS_LPTGF1CR_ETGF5_MASK                 (0x7F0000U)
87077 #define SNVS_LPTGF1CR_ETGF5_SHIFT                (16U)
87078 #define SNVS_LPTGF1CR_ETGF5(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
87079 
87080 #define SNVS_LPTGF1CR_ETGF5_EN_MASK              (0x800000U)
87081 #define SNVS_LPTGF1CR_ETGF5_EN_SHIFT             (23U)
87082 /*! ETGF5_EN
87083  *  0b0..External tamper glitch filter 5 is bypassed.
87084  *  0b1..External tamper glitch filter 5 is enabled.
87085  */
87086 #define SNVS_LPTGF1CR_ETGF5_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
87087 
87088 #define SNVS_LPTGF1CR_ETGF6_MASK                 (0x7F000000U)
87089 #define SNVS_LPTGF1CR_ETGF6_SHIFT                (24U)
87090 #define SNVS_LPTGF1CR_ETGF6(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
87091 
87092 #define SNVS_LPTGF1CR_ETGF6_EN_MASK              (0x80000000U)
87093 #define SNVS_LPTGF1CR_ETGF6_EN_SHIFT             (31U)
87094 /*! ETGF6_EN
87095  *  0b0..External tamper glitch filter 6 is bypassed.
87096  *  0b1..External tamper glitch filter 6 is enabled.
87097  */
87098 #define SNVS_LPTGF1CR_ETGF6_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
87099 /*! @} */
87100 
87101 /*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */
87102 /*! @{ */
87103 
87104 #define SNVS_LPTGF2CR_ETGF7_MASK                 (0x7FU)
87105 #define SNVS_LPTGF2CR_ETGF7_SHIFT                (0U)
87106 #define SNVS_LPTGF2CR_ETGF7(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
87107 
87108 #define SNVS_LPTGF2CR_ETGF7_EN_MASK              (0x80U)
87109 #define SNVS_LPTGF2CR_ETGF7_EN_SHIFT             (7U)
87110 /*! ETGF7_EN
87111  *  0b0..External tamper glitch filter 7 is bypassed.
87112  *  0b1..External tamper glitch filter 7 is enabled.
87113  */
87114 #define SNVS_LPTGF2CR_ETGF7_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
87115 
87116 #define SNVS_LPTGF2CR_ETGF8_MASK                 (0x7F00U)
87117 #define SNVS_LPTGF2CR_ETGF8_SHIFT                (8U)
87118 #define SNVS_LPTGF2CR_ETGF8(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
87119 
87120 #define SNVS_LPTGF2CR_ETGF8_EN_MASK              (0x8000U)
87121 #define SNVS_LPTGF2CR_ETGF8_EN_SHIFT             (15U)
87122 /*! ETGF8_EN
87123  *  0b0..External tamper glitch filter 8 is bypassed.
87124  *  0b1..External tamper glitch filter 8 is enabled.
87125  */
87126 #define SNVS_LPTGF2CR_ETGF8_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
87127 
87128 #define SNVS_LPTGF2CR_ETGF9_MASK                 (0x7F0000U)
87129 #define SNVS_LPTGF2CR_ETGF9_SHIFT                (16U)
87130 #define SNVS_LPTGF2CR_ETGF9(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
87131 
87132 #define SNVS_LPTGF2CR_ETGF9_EN_MASK              (0x800000U)
87133 #define SNVS_LPTGF2CR_ETGF9_EN_SHIFT             (23U)
87134 /*! ETGF9_EN
87135  *  0b0..External tamper glitch filter 9 is bypassed.
87136  *  0b1..External tamper glitch filter 9 is enabled.
87137  */
87138 #define SNVS_LPTGF2CR_ETGF9_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
87139 
87140 #define SNVS_LPTGF2CR_ETGF10_MASK                (0x7F000000U)
87141 #define SNVS_LPTGF2CR_ETGF10_SHIFT               (24U)
87142 #define SNVS_LPTGF2CR_ETGF10(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
87143 
87144 #define SNVS_LPTGF2CR_ETGF10_EN_MASK             (0x80000000U)
87145 #define SNVS_LPTGF2CR_ETGF10_EN_SHIFT            (31U)
87146 /*! ETGF10_EN
87147  *  0b0..External tamper glitch filter 10 is bypassed.
87148  *  0b1..External tamper glitch filter 10 is enabled.
87149  */
87150 #define SNVS_LPTGF2CR_ETGF10_EN(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
87151 /*! @} */
87152 
87153 /*! @name LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register */
87154 /*! @{ */
87155 
87156 #define SNVS_LPATCR_Seed_MASK                    (0xFFFFU)
87157 #define SNVS_LPATCR_Seed_SHIFT                   (0U)
87158 #define SNVS_LPATCR_Seed(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
87159 
87160 #define SNVS_LPATCR_Polynomial_MASK              (0xFFFF0000U)
87161 #define SNVS_LPATCR_Polynomial_SHIFT             (16U)
87162 #define SNVS_LPATCR_Polynomial(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
87163 /*! @} */
87164 
87165 /* The count of SNVS_LPATCR */
87166 #define SNVS_LPATCR_COUNT                        (5U)
87167 
87168 /*! @name LPATCTLR - SNVS_LP Active Tamper Control Register */
87169 /*! @{ */
87170 
87171 #define SNVS_LPATCTLR_AT1_EN_MASK                (0x1U)
87172 #define SNVS_LPATCTLR_AT1_EN_SHIFT               (0U)
87173 /*! AT1_EN
87174  *  0b0..Active Tamper 1 is disabled.
87175  *  0b1..Active Tamper 1 is enabled.
87176  */
87177 #define SNVS_LPATCTLR_AT1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
87178 
87179 #define SNVS_LPATCTLR_AT2_EN_MASK                (0x2U)
87180 #define SNVS_LPATCTLR_AT2_EN_SHIFT               (1U)
87181 /*! AT2_EN
87182  *  0b0..Active Tamper 2 is disabled.
87183  *  0b1..Active Tamper 2 is enabled.
87184  */
87185 #define SNVS_LPATCTLR_AT2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
87186 
87187 #define SNVS_LPATCTLR_AT3_EN_MASK                (0x4U)
87188 #define SNVS_LPATCTLR_AT3_EN_SHIFT               (2U)
87189 /*! AT3_EN
87190  *  0b0..Active Tamper 3 is disabled.
87191  *  0b1..Active Tamper 3 is enabled.
87192  */
87193 #define SNVS_LPATCTLR_AT3_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
87194 
87195 #define SNVS_LPATCTLR_AT4_EN_MASK                (0x8U)
87196 #define SNVS_LPATCTLR_AT4_EN_SHIFT               (3U)
87197 /*! AT4_EN
87198  *  0b0..Active Tamper 4 is disabled.
87199  *  0b1..Active Tamper 4 is enabled.
87200  */
87201 #define SNVS_LPATCTLR_AT4_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
87202 
87203 #define SNVS_LPATCTLR_AT5_EN_MASK                (0x10U)
87204 #define SNVS_LPATCTLR_AT5_EN_SHIFT               (4U)
87205 /*! AT5_EN
87206  *  0b0..Active Tamper 5 is disabled.
87207  *  0b1..Active Tamper 5 is enabled.
87208  */
87209 #define SNVS_LPATCTLR_AT5_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
87210 
87211 #define SNVS_LPATCTLR_AT1_PAD_EN_MASK            (0x10000U)
87212 #define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT           (16U)
87213 /*! AT1_PAD_EN
87214  *  0b0..Active Tamper 1 is disabled.
87215  *  0b1..Active Tamper 1 is enabled.
87216  */
87217 #define SNVS_LPATCTLR_AT1_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
87218 
87219 #define SNVS_LPATCTLR_AT2_PAD_EN_MASK            (0x20000U)
87220 #define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT           (17U)
87221 /*! AT2_PAD_EN
87222  *  0b0..Active Tamper 2 is disabled.
87223  *  0b1..Active Tamper 2 is enabled.
87224  */
87225 #define SNVS_LPATCTLR_AT2_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
87226 
87227 #define SNVS_LPATCTLR_AT3_PAD_EN_MASK            (0x40000U)
87228 #define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT           (18U)
87229 /*! AT3_PAD_EN
87230  *  0b0..Active Tamper 3 is disabled.
87231  *  0b1..Active Tamper 3 is enabled
87232  */
87233 #define SNVS_LPATCTLR_AT3_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
87234 
87235 #define SNVS_LPATCTLR_AT4_PAD_EN_MASK            (0x80000U)
87236 #define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT           (19U)
87237 /*! AT4_PAD_EN
87238  *  0b0..Active Tamper 4 is disabled.
87239  *  0b1..Active Tamper 4 is enabled.
87240  */
87241 #define SNVS_LPATCTLR_AT4_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
87242 
87243 #define SNVS_LPATCTLR_AT5_PAD_EN_MASK            (0x100000U)
87244 #define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT           (20U)
87245 /*! AT5_PAD_EN
87246  *  0b0..Active Tamper 5 is disabled.
87247  *  0b1..Active Tamper 5 is enabled.
87248  */
87249 #define SNVS_LPATCTLR_AT5_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
87250 /*! @} */
87251 
87252 /*! @name LPATCLKR - SNVS_LP Active Tamper Clock Control Register */
87253 /*! @{ */
87254 
87255 #define SNVS_LPATCLKR_AT1_CLK_CTL_MASK           (0x3U)
87256 #define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT          (0U)
87257 #define SNVS_LPATCLKR_AT1_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
87258 
87259 #define SNVS_LPATCLKR_AT2_CLK_CTL_MASK           (0x30U)
87260 #define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT          (4U)
87261 #define SNVS_LPATCLKR_AT2_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
87262 
87263 #define SNVS_LPATCLKR_AT3_CLK_CTL_MASK           (0x300U)
87264 #define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT          (8U)
87265 #define SNVS_LPATCLKR_AT3_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
87266 
87267 #define SNVS_LPATCLKR_AT4_CLK_CTL_MASK           (0x3000U)
87268 #define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT          (12U)
87269 #define SNVS_LPATCLKR_AT4_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
87270 
87271 #define SNVS_LPATCLKR_AT5_CLK_CTL_MASK           (0x30000U)
87272 #define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT          (16U)
87273 #define SNVS_LPATCLKR_AT5_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
87274 /*! @} */
87275 
87276 /*! @name LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register */
87277 /*! @{ */
87278 
87279 #define SNVS_LPATRC1R_ET1RCTL_MASK               (0x7U)
87280 #define SNVS_LPATRC1R_ET1RCTL_SHIFT              (0U)
87281 #define SNVS_LPATRC1R_ET1RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
87282 
87283 #define SNVS_LPATRC1R_ET2RCTL_MASK               (0x70U)
87284 #define SNVS_LPATRC1R_ET2RCTL_SHIFT              (4U)
87285 #define SNVS_LPATRC1R_ET2RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
87286 
87287 #define SNVS_LPATRC1R_ET3RCTL_MASK               (0x700U)
87288 #define SNVS_LPATRC1R_ET3RCTL_SHIFT              (8U)
87289 #define SNVS_LPATRC1R_ET3RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
87290 
87291 #define SNVS_LPATRC1R_ET4RCTL_MASK               (0x7000U)
87292 #define SNVS_LPATRC1R_ET4RCTL_SHIFT              (12U)
87293 #define SNVS_LPATRC1R_ET4RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
87294 
87295 #define SNVS_LPATRC1R_ET5RCTL_MASK               (0x70000U)
87296 #define SNVS_LPATRC1R_ET5RCTL_SHIFT              (16U)
87297 #define SNVS_LPATRC1R_ET5RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
87298 
87299 #define SNVS_LPATRC1R_ET6RCTL_MASK               (0x700000U)
87300 #define SNVS_LPATRC1R_ET6RCTL_SHIFT              (20U)
87301 #define SNVS_LPATRC1R_ET6RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
87302 
87303 #define SNVS_LPATRC1R_ET7RCTL_MASK               (0x7000000U)
87304 #define SNVS_LPATRC1R_ET7RCTL_SHIFT              (24U)
87305 #define SNVS_LPATRC1R_ET7RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
87306 
87307 #define SNVS_LPATRC1R_ET8RCTL_MASK               (0x70000000U)
87308 #define SNVS_LPATRC1R_ET8RCTL_SHIFT              (28U)
87309 #define SNVS_LPATRC1R_ET8RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
87310 /*! @} */
87311 
87312 /*! @name LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register */
87313 /*! @{ */
87314 
87315 #define SNVS_LPATRC2R_ET9RCTL_MASK               (0x7U)
87316 #define SNVS_LPATRC2R_ET9RCTL_SHIFT              (0U)
87317 #define SNVS_LPATRC2R_ET9RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
87318 
87319 #define SNVS_LPATRC2R_ET10RCTL_MASK              (0x70U)
87320 #define SNVS_LPATRC2R_ET10RCTL_SHIFT             (4U)
87321 #define SNVS_LPATRC2R_ET10RCTL(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
87322 /*! @} */
87323 
87324 /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
87325 /*! @{ */
87326 
87327 #define SNVS_LPGPR_GPR_MASK                      (0xFFFFFFFFU)
87328 #define SNVS_LPGPR_GPR_SHIFT                     (0U)
87329 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
87330 /*! @} */
87331 
87332 /* The count of SNVS_LPGPR */
87333 #define SNVS_LPGPR_COUNT                         (4U)
87334 
87335 /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
87336 /*! @{ */
87337 
87338 #define SNVS_HPVIDR1_MINOR_REV_MASK              (0xFFU)
87339 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             (0U)
87340 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
87341 
87342 #define SNVS_HPVIDR1_MAJOR_REV_MASK              (0xFF00U)
87343 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             (8U)
87344 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
87345 
87346 #define SNVS_HPVIDR1_IP_ID_MASK                  (0xFFFF0000U)
87347 #define SNVS_HPVIDR1_IP_ID_SHIFT                 (16U)
87348 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
87349 /*! @} */
87350 
87351 /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
87352 /*! @{ */
87353 
87354 #define SNVS_HPVIDR2_ECO_REV_MASK                (0xFF00U)
87355 #define SNVS_HPVIDR2_ECO_REV_SHIFT               (8U)
87356 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
87357 
87358 #define SNVS_HPVIDR2_IP_ERA_MASK                 (0xFF000000U)
87359 #define SNVS_HPVIDR2_IP_ERA_SHIFT                (24U)
87360 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
87361 /*! @} */
87362 
87363 
87364 /*!
87365  * @}
87366  */ /* end of group SNVS_Register_Masks */
87367 
87368 
87369 /* SNVS - Peripheral instance base addresses */
87370 /** Peripheral SNVS base address */
87371 #define SNVS_BASE                                (0x40C90000u)
87372 /** Peripheral SNVS base pointer */
87373 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
87374 /** Array initializer of SNVS peripheral base addresses */
87375 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
87376 /** Array initializer of SNVS peripheral base pointers */
87377 #define SNVS_BASE_PTRS                           { SNVS }
87378 /** Interrupt vectors for the SNVS peripheral type */
87379 #define SNVS_IRQS                                { SNVS_PULSE_EVENT_IRQn }
87380 #define SNVS_CONSOLIDATED_IRQS                   { SNVS_HP_NON_TZ_IRQn }
87381 #define SNVS_SECURITY_IRQS                       { SNVS_HP_TZ_IRQn }
87382 
87383 /*!
87384  * @}
87385  */ /* end of group SNVS_Peripheral_Access_Layer */
87386 
87387 
87388 /* ----------------------------------------------------------------------------
87389    -- SPDIF Peripheral Access Layer
87390    ---------------------------------------------------------------------------- */
87391 
87392 /*!
87393  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
87394  * @{
87395  */
87396 
87397 /** SPDIF - Register Layout Typedef */
87398 typedef struct {
87399   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
87400   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
87401   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
87402   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
87403   union {                                          /* offset: 0x10 */
87404     __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
87405     __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
87406   };
87407   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
87408   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
87409   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
87410   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
87411   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
87412   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
87413   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
87414   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
87415   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
87416   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
87417        uint8_t RESERVED_0[8];
87418   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
87419        uint8_t RESERVED_1[8];
87420   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
87421 } SPDIF_Type;
87422 
87423 /* ----------------------------------------------------------------------------
87424    -- SPDIF Register Masks
87425    ---------------------------------------------------------------------------- */
87426 
87427 /*!
87428  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
87429  * @{
87430  */
87431 
87432 /*! @name SCR - SPDIF Configuration Register */
87433 /*! @{ */
87434 
87435 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
87436 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
87437 /*! USrc_Sel - USrc_Sel
87438  *  0b00..No embedded U channel
87439  *  0b01..U channel from SPDIF receive block (CD mode)
87440  *  0b10..Reserved
87441  *  0b11..U channel from on chip transmitter
87442  */
87443 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
87444 
87445 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
87446 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
87447 /*! TxSel - TxSel
87448  *  0b000..Off and output 0
87449  *  0b001..Feed-through SPDIFIN
87450  *  0b101..Tx Normal operation
87451  */
87452 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
87453 
87454 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
87455 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
87456 /*! ValCtrl - ValCtrl
87457  *  0b0..Outgoing Validity always set
87458  *  0b1..Outgoing Validity always clear
87459  */
87460 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
87461 
87462 #define SPDIF_SCR_INPUTSRCSEL_MASK               (0xC0U)
87463 #define SPDIF_SCR_INPUTSRCSEL_SHIFT              (6U)
87464 /*! InputSrcSel - InputSrcSel
87465  *  0b00..SPDIF_IN
87466  *  0b01-0b11..None
87467  */
87468 #define SPDIF_SCR_INPUTSRCSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
87469 
87470 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
87471 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
87472 /*! DMA_TX_En - DMA_TX_En
87473  */
87474 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
87475 
87476 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
87477 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
87478 /*! DMA_Rx_En - DMA_Rx_En
87479  */
87480 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
87481 
87482 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
87483 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
87484 /*! TxFIFO_Ctrl - TxFIFO_Ctrl
87485  *  0b00..Send out digital zero on SPDIF Tx
87486  *  0b01..Tx Normal operation
87487  *  0b10..Reset to 1 sample remaining
87488  *  0b11..Reserved
87489  */
87490 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
87491 
87492 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
87493 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
87494 /*! soft_reset - soft_reset
87495  */
87496 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
87497 
87498 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
87499 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
87500 /*! LOW_POWER - LOW_POWER
87501  */
87502 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
87503 
87504 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
87505 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
87506 /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
87507  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
87508  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
87509  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
87510  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
87511  */
87512 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
87513 
87514 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
87515 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
87516 /*! TxAutoSync - TxAutoSync
87517  *  0b0..Tx FIFO auto sync off
87518  *  0b1..Tx FIFO auto sync on
87519  */
87520 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
87521 
87522 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
87523 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
87524 /*! RxAutoSync - RxAutoSync
87525  *  0b0..Rx FIFO auto sync off
87526  *  0b1..RxFIFO auto sync on
87527  */
87528 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
87529 
87530 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
87531 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
87532 /*! RxFIFOFull_Sel - RxFIFOFull_Sel
87533  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
87534  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
87535  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
87536  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
87537  */
87538 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
87539 
87540 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
87541 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
87542 /*! RxFIFO_Rst - RxFIFO_Rst
87543  *  0b0..Normal operation
87544  *  0b1..Reset register to 1 sample remaining
87545  */
87546 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
87547 
87548 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
87549 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
87550 /*! RxFIFO_Off_On - RxFIFO_Off_On
87551  *  0b0..SPDIF Rx FIFO is on
87552  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
87553  */
87554 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
87555 
87556 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
87557 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
87558 /*! RxFIFO_Ctrl - RxFIFO_Ctrl
87559  *  0b0..Normal operation
87560  *  0b1..Always read zero from Rx data register
87561  */
87562 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
87563 /*! @} */
87564 
87565 /*! @name SRCD - CDText Control Register */
87566 /*! @{ */
87567 
87568 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
87569 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
87570 /*! USyncMode - USyncMode
87571  *  0b0..Non-CD data
87572  *  0b1..CD user channel subcode
87573  */
87574 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
87575 /*! @} */
87576 
87577 /*! @name SRPC - PhaseConfig Register */
87578 /*! @{ */
87579 
87580 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
87581 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
87582 /*! GainSel - GainSel
87583  *  0b000..24*(2**10)
87584  *  0b001..16*(2**10)
87585  *  0b010..12*(2**10)
87586  *  0b011..8*(2**10)
87587  *  0b100..6*(2**10)
87588  *  0b101..4*(2**10)
87589  *  0b110..3*(2**10)
87590  */
87591 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
87592 
87593 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
87594 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
87595 /*! LOCK - LOCK
87596  */
87597 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
87598 
87599 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
87600 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
87601 /*! ClkSrc_Sel - ClkSrc_Sel
87602  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
87603  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
87604  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
87605  *  0b0101..REF_CLK_32K (XTALOSC)
87606  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
87607  *  0b1000..SPDIF_EXT_CLK
87608  */
87609 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
87610 /*! @} */
87611 
87612 /*! @name SIE - InterruptEn Register */
87613 /*! @{ */
87614 
87615 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
87616 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
87617 /*! RxFIFOFul - RxFIFOFul
87618  */
87619 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
87620 
87621 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
87622 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
87623 /*! TxEm - TxEm
87624  */
87625 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
87626 
87627 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
87628 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
87629 /*! LockLoss - LockLoss
87630  */
87631 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
87632 
87633 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
87634 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
87635 /*! RxFIFOResyn - RxFIFOResyn
87636  */
87637 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
87638 
87639 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
87640 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
87641 /*! RxFIFOUnOv - RxFIFOUnOv
87642  */
87643 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
87644 
87645 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
87646 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
87647 /*! UQErr - UQErr
87648  */
87649 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
87650 
87651 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
87652 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
87653 /*! UQSync - UQSync
87654  */
87655 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
87656 
87657 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
87658 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
87659 /*! QRxOv - QRxOv
87660  */
87661 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
87662 
87663 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
87664 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
87665 /*! QRxFul - QRxFul
87666  */
87667 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
87668 
87669 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
87670 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
87671 /*! URxOv - URxOv
87672  */
87673 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
87674 
87675 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
87676 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
87677 /*! URxFul - URxFul
87678  */
87679 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
87680 
87681 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
87682 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
87683 /*! BitErr - BitErr
87684  */
87685 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
87686 
87687 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
87688 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
87689 /*! SymErr - SymErr
87690  */
87691 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
87692 
87693 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
87694 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
87695 /*! ValNoGood - ValNoGood
87696  */
87697 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
87698 
87699 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
87700 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
87701 /*! CNew - CNew
87702  */
87703 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
87704 
87705 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
87706 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
87707 /*! TxResyn - TxResyn
87708  */
87709 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
87710 
87711 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
87712 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
87713 /*! TxUnOv - TxUnOv
87714  */
87715 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
87716 
87717 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
87718 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
87719 /*! Lock - Lock
87720  */
87721 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
87722 /*! @} */
87723 
87724 /*! @name SIC - InterruptClear Register */
87725 /*! @{ */
87726 
87727 #define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
87728 #define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
87729 /*! LockLoss - LockLoss
87730  */
87731 #define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
87732 
87733 #define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
87734 #define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
87735 /*! RxFIFOResyn - RxFIFOResyn
87736  */
87737 #define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
87738 
87739 #define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
87740 #define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
87741 /*! RxFIFOUnOv - RxFIFOUnOv
87742  */
87743 #define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
87744 
87745 #define SPDIF_SIC_UQERR_MASK                     (0x20U)
87746 #define SPDIF_SIC_UQERR_SHIFT                    (5U)
87747 /*! UQErr - UQErr
87748  */
87749 #define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
87750 
87751 #define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
87752 #define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
87753 /*! UQSync - UQSync
87754  */
87755 #define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
87756 
87757 #define SPDIF_SIC_QRXOV_MASK                     (0x80U)
87758 #define SPDIF_SIC_QRXOV_SHIFT                    (7U)
87759 /*! QRxOv - QRxOv
87760  */
87761 #define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
87762 
87763 #define SPDIF_SIC_URXOV_MASK                     (0x200U)
87764 #define SPDIF_SIC_URXOV_SHIFT                    (9U)
87765 /*! URxOv - URxOv
87766  */
87767 #define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
87768 
87769 #define SPDIF_SIC_BITERR_MASK                    (0x4000U)
87770 #define SPDIF_SIC_BITERR_SHIFT                   (14U)
87771 /*! BitErr - BitErr
87772  */
87773 #define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
87774 
87775 #define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
87776 #define SPDIF_SIC_SYMERR_SHIFT                   (15U)
87777 /*! SymErr - SymErr
87778  */
87779 #define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
87780 
87781 #define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
87782 #define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
87783 /*! ValNoGood - ValNoGood
87784  */
87785 #define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
87786 
87787 #define SPDIF_SIC_CNEW_MASK                      (0x20000U)
87788 #define SPDIF_SIC_CNEW_SHIFT                     (17U)
87789 /*! CNew - CNew
87790  */
87791 #define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
87792 
87793 #define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
87794 #define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
87795 /*! TxResyn - TxResyn
87796  */
87797 #define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
87798 
87799 #define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
87800 #define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
87801 /*! TxUnOv - TxUnOv
87802  */
87803 #define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
87804 
87805 #define SPDIF_SIC_LOCK_MASK                      (0x100000U)
87806 #define SPDIF_SIC_LOCK_SHIFT                     (20U)
87807 /*! Lock - Lock
87808  */
87809 #define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
87810 /*! @} */
87811 
87812 /*! @name SIS - InterruptStat Register */
87813 /*! @{ */
87814 
87815 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
87816 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
87817 /*! RxFIFOFul - RxFIFOFul
87818  */
87819 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
87820 
87821 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
87822 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
87823 /*! TxEm - TxEm
87824  */
87825 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
87826 
87827 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
87828 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
87829 /*! LockLoss - LockLoss
87830  */
87831 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
87832 
87833 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
87834 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
87835 /*! RxFIFOResyn - RxFIFOResyn
87836  */
87837 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
87838 
87839 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
87840 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
87841 /*! RxFIFOUnOv - RxFIFOUnOv
87842  */
87843 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
87844 
87845 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
87846 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
87847 /*! UQErr - UQErr
87848  */
87849 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
87850 
87851 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
87852 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
87853 /*! UQSync - UQSync
87854  */
87855 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
87856 
87857 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
87858 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
87859 /*! QRxOv - QRxOv
87860  */
87861 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
87862 
87863 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
87864 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
87865 /*! QRxFul - QRxFul
87866  */
87867 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
87868 
87869 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
87870 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
87871 /*! URxOv - URxOv
87872  */
87873 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
87874 
87875 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
87876 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
87877 /*! URxFul - URxFul
87878  */
87879 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
87880 
87881 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
87882 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
87883 /*! BitErr - BitErr
87884  */
87885 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
87886 
87887 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
87888 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
87889 /*! SymErr - SymErr
87890  */
87891 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
87892 
87893 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
87894 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
87895 /*! ValNoGood - ValNoGood
87896  */
87897 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
87898 
87899 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
87900 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
87901 /*! CNew - CNew
87902  */
87903 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
87904 
87905 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
87906 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
87907 /*! TxResyn - TxResyn
87908  */
87909 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
87910 
87911 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
87912 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
87913 /*! TxUnOv - TxUnOv
87914  */
87915 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
87916 
87917 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
87918 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
87919 /*! Lock - Lock
87920  */
87921 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
87922 /*! @} */
87923 
87924 /*! @name SRL - SPDIFRxLeft Register */
87925 /*! @{ */
87926 
87927 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
87928 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
87929 /*! RxDataLeft - RxDataLeft
87930  */
87931 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
87932 /*! @} */
87933 
87934 /*! @name SRR - SPDIFRxRight Register */
87935 /*! @{ */
87936 
87937 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
87938 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
87939 /*! RxDataRight - RxDataRight
87940  */
87941 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
87942 /*! @} */
87943 
87944 /*! @name SRCSH - SPDIFRxCChannel_h Register */
87945 /*! @{ */
87946 
87947 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
87948 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
87949 /*! RxCChannel_h - RxCChannel_h
87950  */
87951 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
87952 /*! @} */
87953 
87954 /*! @name SRCSL - SPDIFRxCChannel_l Register */
87955 /*! @{ */
87956 
87957 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
87958 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
87959 /*! RxCChannel_l - RxCChannel_l
87960  */
87961 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
87962 /*! @} */
87963 
87964 /*! @name SRU - UchannelRx Register */
87965 /*! @{ */
87966 
87967 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
87968 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
87969 /*! RxUChannel - RxUChannel
87970  */
87971 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
87972 /*! @} */
87973 
87974 /*! @name SRQ - QchannelRx Register */
87975 /*! @{ */
87976 
87977 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
87978 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
87979 /*! RxQChannel - RxQChannel
87980  */
87981 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
87982 /*! @} */
87983 
87984 /*! @name STL - SPDIFTxLeft Register */
87985 /*! @{ */
87986 
87987 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
87988 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
87989 /*! TxDataLeft - TxDataLeft
87990  */
87991 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
87992 /*! @} */
87993 
87994 /*! @name STR - SPDIFTxRight Register */
87995 /*! @{ */
87996 
87997 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
87998 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
87999 /*! TxDataRight - TxDataRight
88000  */
88001 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
88002 /*! @} */
88003 
88004 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
88005 /*! @{ */
88006 
88007 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
88008 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
88009 /*! TxCChannelCons_h - TxCChannelCons_h
88010  */
88011 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
88012 /*! @} */
88013 
88014 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
88015 /*! @{ */
88016 
88017 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
88018 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
88019 /*! TxCChannelCons_l - TxCChannelCons_l
88020  */
88021 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
88022 /*! @} */
88023 
88024 /*! @name SRFM - FreqMeas Register */
88025 /*! @{ */
88026 
88027 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
88028 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
88029 /*! FreqMeas - FreqMeas
88030  */
88031 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
88032 /*! @} */
88033 
88034 /*! @name STC - SPDIFTxClk Register */
88035 /*! @{ */
88036 
88037 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
88038 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
88039 /*! TxClk_DF - TxClk_DF
88040  *  0b0000000..divider factor is 1
88041  *  0b0000001..divider factor is 2
88042  *  0b1111111..divider factor is 128
88043  */
88044 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
88045 
88046 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
88047 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
88048 /*! tx_all_clk_en - tx_all_clk_en
88049  *  0b0..disable transfer clock.
88050  *  0b1..enable transfer clock.
88051  */
88052 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
88053 
88054 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
88055 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
88056 /*! TxClk_Source - TxClk_Source
88057  *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
88058  *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
88059  *  0b011..SPDIF_EXT_CLK, from pads
88060  *  0b101..ipg_clk input (frequency divided)
88061  */
88062 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
88063 
88064 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
88065 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
88066 /*! SYSCLK_DF - SYSCLK_DF
88067  *  0b000000000..no clock signal
88068  *  0b000000001..divider factor is 2
88069  *  0b111111111..divider factor is 512
88070  */
88071 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
88072 /*! @} */
88073 
88074 
88075 /*!
88076  * @}
88077  */ /* end of group SPDIF_Register_Masks */
88078 
88079 
88080 /* SPDIF - Peripheral instance base addresses */
88081 /** Peripheral SPDIF base address */
88082 #define SPDIF_BASE                               (0x40400000u)
88083 /** Peripheral SPDIF base pointer */
88084 #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
88085 /** Array initializer of SPDIF peripheral base addresses */
88086 #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
88087 /** Array initializer of SPDIF peripheral base pointers */
88088 #define SPDIF_BASE_PTRS                          { SPDIF }
88089 /** Interrupt vectors for the SPDIF peripheral type */
88090 #define SPDIF_IRQS                               { SPDIF_IRQn }
88091 
88092 /*!
88093  * @}
88094  */ /* end of group SPDIF_Peripheral_Access_Layer */
88095 
88096 
88097 /* ----------------------------------------------------------------------------
88098    -- SRAM Peripheral Access Layer
88099    ---------------------------------------------------------------------------- */
88100 
88101 /*!
88102  * @addtogroup SRAM_Peripheral_Access_Layer SRAM Peripheral Access Layer
88103  * @{
88104  */
88105 
88106 /** SRAM - Register Layout Typedef */
88107 typedef struct {
88108        uint8_t RESERVED_0[12288];
88109   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x3000 */
88110 } SRAM_Type;
88111 
88112 /* ----------------------------------------------------------------------------
88113    -- SRAM Register Masks
88114    ---------------------------------------------------------------------------- */
88115 
88116 /*!
88117  * @addtogroup SRAM_Register_Masks SRAM Register Masks
88118  * @{
88119  */
88120 
88121 /*! @name CTRL - Control Register */
88122 /*! @{ */
88123 
88124 #define SRAM_CTRL_RAM_RD_EN_MASK                 (0x1U)
88125 #define SRAM_CTRL_RAM_RD_EN_SHIFT                (0U)
88126 /*! RAM_RD_EN - RAM Read Enable (with lock)
88127  *  0b0..Disable read access
88128  *  0b1..Enable read access
88129  */
88130 #define SRAM_CTRL_RAM_RD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
88131 
88132 #define SRAM_CTRL_RAM_WR_EN_MASK                 (0x2U)
88133 #define SRAM_CTRL_RAM_WR_EN_SHIFT                (1U)
88134 /*! RAM_WR_EN - RAM Write Enable (with lock)
88135  *  0b0..Disable write access
88136  *  0b1..Enable write access
88137  */
88138 #define SRAM_CTRL_RAM_WR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
88139 
88140 #define SRAM_CTRL_PWR_EN_MASK                    (0x3CU)
88141 #define SRAM_CTRL_PWR_EN_SHIFT                   (2U)
88142 /*! PWR_EN - Power Enable (with lock)
88143  */
88144 #define SRAM_CTRL_PWR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
88145 
88146 #define SRAM_CTRL_TAMPER_BLOCK_EN_MASK           (0x40U)
88147 #define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT          (6U)
88148 /*! TAMPER_BLOCK_EN - Tamper Block Enable (with lock)
88149  *  0b0..Allow R/W access to secure RAM when tamper is detected
88150  *  0b1..Block R/W access to secure RAM when tamper is detected
88151  */
88152 #define SRAM_CTRL_TAMPER_BLOCK_EN(x)             (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
88153 
88154 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK         (0x80U)
88155 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT        (7U)
88156 /*! TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock)
88157  *  0b0..Disable the turn off function when tamper is detected
88158  *  0b1..Turn off power for all secure RAM banks when tamper is detected
88159  */
88160 #define SRAM_CTRL_TAMPER_PWR_OFF_EN(x)           (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
88161 
88162 #define SRAM_CTRL_LOCK_BIT_MASK                  (0xFF0000U)
88163 #define SRAM_CTRL_LOCK_BIT_SHIFT                 (16U)
88164 /*! LOCK_BIT - Lock bits
88165  */
88166 #define SRAM_CTRL_LOCK_BIT(x)                    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
88167 /*! @} */
88168 
88169 
88170 /*!
88171  * @}
88172  */ /* end of group SRAM_Register_Masks */
88173 
88174 
88175 /* SRAM - Peripheral instance base addresses */
88176 /** Peripheral SRAM base address */
88177 #define SRAM_BASE                                (0x40C9C000u)
88178 /** Peripheral SRAM base pointer */
88179 #define SRAM                                     ((SRAM_Type *)SRAM_BASE)
88180 /** Array initializer of SRAM peripheral base addresses */
88181 #define SRAM_BASE_ADDRS                          { SRAM_BASE }
88182 /** Array initializer of SRAM peripheral base pointers */
88183 #define SRAM_BASE_PTRS                           { SRAM }
88184 
88185 /*!
88186  * @}
88187  */ /* end of group SRAM_Peripheral_Access_Layer */
88188 
88189 
88190 /* ----------------------------------------------------------------------------
88191    -- SRC Peripheral Access Layer
88192    ---------------------------------------------------------------------------- */
88193 
88194 /*!
88195  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
88196  * @{
88197  */
88198 
88199 /** SRC - Register Layout Typedef */
88200 typedef struct {
88201   __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x0 */
88202   __IO uint32_t SRMR;                              /**< SRC Reset Mode Register, offset: 0x4 */
88203   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x8 */
88204   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0xC */
88205   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x10 */
88206   __IO uint32_t GPR[20];                           /**< SRC General Purpose Register, array offset: 0x14, array step: 0x4 */
88207        uint8_t RESERVED_0[412];
88208   __IO uint32_t AUTHEN_MEGA;                       /**< Slice Authentication Register, offset: 0x200 */
88209   __IO uint32_t CTRL_MEGA;                         /**< Slice Control Register, offset: 0x204 */
88210   __IO uint32_t SETPOINT_MEGA;                     /**< Slice Setpoint Config Register, offset: 0x208 */
88211   __IO uint32_t DOMAIN_MEGA;                       /**< Slice Domain Config Register, offset: 0x20C */
88212   __IO uint32_t STAT_MEGA;                         /**< Slice Status Register, offset: 0x210 */
88213        uint8_t RESERVED_1[12];
88214   __IO uint32_t AUTHEN_DISPLAY;                    /**< Slice Authentication Register, offset: 0x220 */
88215   __IO uint32_t CTRL_DISPLAY;                      /**< Slice Control Register, offset: 0x224 */
88216   __IO uint32_t SETPOINT_DISPLAY;                  /**< Slice Setpoint Config Register, offset: 0x228 */
88217   __IO uint32_t DOMAIN_DISPLAY;                    /**< Slice Domain Config Register, offset: 0x22C */
88218   __IO uint32_t STAT_DISPLAY;                      /**< Slice Status Register, offset: 0x230 */
88219        uint8_t RESERVED_2[12];
88220   __IO uint32_t AUTHEN_WAKEUP;                     /**< Slice Authentication Register, offset: 0x240 */
88221   __IO uint32_t CTRL_WAKEUP;                       /**< Slice Control Register, offset: 0x244 */
88222   __IO uint32_t SETPOINT_WAKEUP;                   /**< Slice Setpoint Config Register, offset: 0x248 */
88223   __IO uint32_t DOMAIN_WAKEUP;                     /**< Slice Domain Config Register, offset: 0x24C */
88224   __IO uint32_t STAT_WAKEUP;                       /**< Slice Status Register, offset: 0x250 */
88225        uint8_t RESERVED_3[44];
88226   __IO uint32_t AUTHEN_M4CORE;                     /**< Slice Authentication Register, offset: 0x280 */
88227   __IO uint32_t CTRL_M4CORE;                       /**< Slice Control Register, offset: 0x284 */
88228   __IO uint32_t SETPOINT_M4CORE;                   /**< Slice Setpoint Config Register, offset: 0x288 */
88229   __IO uint32_t DOMAIN_M4CORE;                     /**< Slice Domain Config Register, offset: 0x28C */
88230   __IO uint32_t STAT_M4CORE;                       /**< Slice Status Register, offset: 0x290 */
88231        uint8_t RESERVED_4[12];
88232   __IO uint32_t AUTHEN_M7CORE;                     /**< Slice Authentication Register, offset: 0x2A0 */
88233   __IO uint32_t CTRL_M7CORE;                       /**< Slice Control Register, offset: 0x2A4 */
88234   __IO uint32_t SETPOINT_M7CORE;                   /**< Slice Setpoint Config Register, offset: 0x2A8 */
88235   __IO uint32_t DOMAIN_M7CORE;                     /**< Slice Domain Config Register, offset: 0x2AC */
88236   __IO uint32_t STAT_M7CORE;                       /**< Slice Status Register, offset: 0x2B0 */
88237        uint8_t RESERVED_5[12];
88238   __IO uint32_t AUTHEN_M4DEBUG;                    /**< Slice Authentication Register, offset: 0x2C0 */
88239   __IO uint32_t CTRL_M4DEBUG;                      /**< Slice Control Register, offset: 0x2C4 */
88240   __IO uint32_t SETPOINT_M4DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2C8 */
88241   __IO uint32_t DOMAIN_M4DEBUG;                    /**< Slice Domain Config Register, offset: 0x2CC */
88242   __IO uint32_t STAT_M4DEBUG;                      /**< Slice Status Register, offset: 0x2D0 */
88243        uint8_t RESERVED_6[12];
88244   __IO uint32_t AUTHEN_M7DEBUG;                    /**< Slice Authentication Register, offset: 0x2E0 */
88245   __IO uint32_t CTRL_M7DEBUG;                      /**< Slice Control Register, offset: 0x2E4 */
88246   __IO uint32_t SETPOINT_M7DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2E8 */
88247   __IO uint32_t DOMAIN_M7DEBUG;                    /**< Slice Domain Config Register, offset: 0x2EC */
88248   __IO uint32_t STAT_M7DEBUG;                      /**< Slice Status Register, offset: 0x2F0 */
88249        uint8_t RESERVED_7[12];
88250   __IO uint32_t AUTHEN_USBPHY1;                    /**< Slice Authentication Register, offset: 0x300 */
88251   __IO uint32_t CTRL_USBPHY1;                      /**< Slice Control Register, offset: 0x304 */
88252   __IO uint32_t SETPOINT_USBPHY1;                  /**< Slice Setpoint Config Register, offset: 0x308 */
88253   __IO uint32_t DOMAIN_USBPHY1;                    /**< Slice Domain Config Register, offset: 0x30C */
88254   __IO uint32_t STAT_USBPHY1;                      /**< Slice Status Register, offset: 0x310 */
88255        uint8_t RESERVED_8[12];
88256   __IO uint32_t AUTHEN_USBPHY2;                    /**< Slice Authentication Register, offset: 0x320 */
88257   __IO uint32_t CTRL_USBPHY2;                      /**< Slice Control Register, offset: 0x324 */
88258   __IO uint32_t SETPOINT_USBPHY2;                  /**< Slice Setpoint Config Register, offset: 0x328 */
88259   __IO uint32_t DOMAIN_USBPHY2;                    /**< Slice Domain Config Register, offset: 0x32C */
88260   __IO uint32_t STAT_USBPHY2;                      /**< Slice Status Register, offset: 0x330 */
88261 } SRC_Type;
88262 
88263 /* ----------------------------------------------------------------------------
88264    -- SRC Register Masks
88265    ---------------------------------------------------------------------------- */
88266 
88267 /*!
88268  * @addtogroup SRC_Register_Masks SRC Register Masks
88269  * @{
88270  */
88271 
88272 /*! @name SCR - SRC Control Register */
88273 /*! @{ */
88274 
88275 #define SRC_SCR_BT_RELEASE_M4_MASK               (0x1U)
88276 #define SRC_SCR_BT_RELEASE_M4_SHIFT              (0U)
88277 /*! BT_RELEASE_M4
88278  *  0b0..cm4 core reset is asserted
88279  *  0b1..cm4 core reset is released
88280  */
88281 #define SRC_SCR_BT_RELEASE_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)
88282 
88283 #define SRC_SCR_BT_RELEASE_M7_MASK               (0x2U)
88284 #define SRC_SCR_BT_RELEASE_M7_SHIFT              (1U)
88285 /*! BT_RELEASE_M7
88286  *  0b0..cm7 core reset is asserted
88287  *  0b1..cm7 core reset is released
88288  */
88289 #define SRC_SCR_BT_RELEASE_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)
88290 /*! @} */
88291 
88292 /*! @name SRMR - SRC Reset Mode Register */
88293 /*! @{ */
88294 
88295 #define SRC_SRMR_WDOG_RESET_MODE_MASK            (0x3U)
88296 #define SRC_SRMR_WDOG_RESET_MODE_SHIFT           (0U)
88297 /*! WDOG_RESET_MODE - Wdog reset mode configuration
88298  *  0b00..reset system
88299  *  0b01..reserved
88300  *  0b10..reserved
88301  *  0b11..do not reset anything
88302  */
88303 #define SRC_SRMR_WDOG_RESET_MODE(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)
88304 
88305 #define SRC_SRMR_WDOG3_RESET_MODE_MASK           (0xCU)
88306 #define SRC_SRMR_WDOG3_RESET_MODE_SHIFT          (2U)
88307 /*! WDOG3_RESET_MODE - Wdog3 reset mode configuration
88308  *  0b00..reset system
88309  *  0b01..reserved
88310  *  0b10..reserved
88311  *  0b11..do not reset anything
88312  */
88313 #define SRC_SRMR_WDOG3_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)
88314 
88315 #define SRC_SRMR_WDOG4_RESET_MODE_MASK           (0x30U)
88316 #define SRC_SRMR_WDOG4_RESET_MODE_SHIFT          (4U)
88317 /*! WDOG4_RESET_MODE - Wdog4 reset mode configuration
88318  *  0b00..reset system
88319  *  0b01..reserved
88320  *  0b10..reserved
88321  *  0b11..do not reset anything
88322  */
88323 #define SRC_SRMR_WDOG4_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)
88324 
88325 #define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK        (0xC0U)
88326 #define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT       (6U)
88327 /*! M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration
88328  *  0b00..reset system
88329  *  0b01..reserved
88330  *  0b10..reserved
88331  *  0b11..do not reset anything
88332  */
88333 #define SRC_SRMR_M4LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)
88334 
88335 #define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK        (0x300U)
88336 #define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT       (8U)
88337 /*! M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration
88338  *  0b00..reset system
88339  *  0b01..reserved
88340  *  0b10..reserved
88341  *  0b11..do not reset anything
88342  */
88343 #define SRC_SRMR_M7LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)
88344 
88345 #define SRC_SRMR_M4REQ_RESET_MODE_MASK           (0xC00U)
88346 #define SRC_SRMR_M4REQ_RESET_MODE_SHIFT          (10U)
88347 /*! M4REQ_RESET_MODE - M4 request reset configuration
88348  *  0b00..reset system
88349  *  0b01..reserved
88350  *  0b10..reserved
88351  *  0b11..do not reset anything
88352  */
88353 #define SRC_SRMR_M4REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)
88354 
88355 #define SRC_SRMR_M7REQ_RESET_MODE_MASK           (0x3000U)
88356 #define SRC_SRMR_M7REQ_RESET_MODE_SHIFT          (12U)
88357 /*! M7REQ_RESET_MODE - M7 request reset configuration
88358  *  0b00..reset system
88359  *  0b01..reserved
88360  *  0b10..reserved
88361  *  0b11..do not reset anything
88362  */
88363 #define SRC_SRMR_M7REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)
88364 
88365 #define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK       (0xC000U)
88366 #define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT      (14U)
88367 /*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration
88368  *  0b00..reset system
88369  *  0b01..reserved
88370  *  0b10..reserved
88371  *  0b11..do not reset anything
88372  */
88373 #define SRC_SRMR_TEMPSENSE_RESET_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)
88374 
88375 #define SRC_SRMR_CSU_RESET_MODE_MASK             (0x30000U)
88376 #define SRC_SRMR_CSU_RESET_MODE_SHIFT            (16U)
88377 /*! CSU_RESET_MODE - CSU reset mode configuration
88378  *  0b00..reset system
88379  *  0b01..reserved
88380  *  0b10..reserved
88381  *  0b11..do not reset anything
88382  */
88383 #define SRC_SRMR_CSU_RESET_MODE(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)
88384 
88385 #define SRC_SRMR_JTAGSW_RESET_MODE_MASK          (0xC0000U)
88386 #define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT         (18U)
88387 /*! JTAGSW_RESET_MODE - Jtag SW reset mode configuration
88388  *  0b00..reset system
88389  *  0b01..reserved
88390  *  0b10..reserved
88391  *  0b11..do not reset anything
88392  */
88393 #define SRC_SRMR_JTAGSW_RESET_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)
88394 
88395 #define SRC_SRMR_OVERVOLT_RESET_MODE_MASK        (0x300000U)
88396 #define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT       (20U)
88397 /*! OVERVOLT_RESET_MODE - Jtag SW reset mode configuration
88398  *  0b00..reset system
88399  *  0b01..reserved
88400  *  0b10..reserved
88401  *  0b11..do not reset anything
88402  */
88403 #define SRC_SRMR_OVERVOLT_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)
88404 /*! @} */
88405 
88406 /*! @name SBMR1 - SRC Boot Mode Register 1 */
88407 /*! @{ */
88408 
88409 #define SRC_SBMR1_BOOT_CFG1_MASK                 (0xFFU)
88410 #define SRC_SBMR1_BOOT_CFG1_SHIFT                (0U)
88411 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
88412 
88413 #define SRC_SBMR1_BOOT_CFG2_MASK                 (0xFF00U)
88414 #define SRC_SBMR1_BOOT_CFG2_SHIFT                (8U)
88415 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
88416 
88417 #define SRC_SBMR1_BOOT_CFG3_MASK                 (0xFF0000U)
88418 #define SRC_SBMR1_BOOT_CFG3_SHIFT                (16U)
88419 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
88420 
88421 #define SRC_SBMR1_BOOT_CFG4_MASK                 (0xFF000000U)
88422 #define SRC_SBMR1_BOOT_CFG4_SHIFT                (24U)
88423 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
88424 /*! @} */
88425 
88426 /*! @name SBMR2 - SRC Boot Mode Register 2 */
88427 /*! @{ */
88428 
88429 #define SRC_SBMR2_SEC_CONFIG_MASK                (0x3U)
88430 #define SRC_SBMR2_SEC_CONFIG_SHIFT               (0U)
88431 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
88432 
88433 #define SRC_SBMR2_BT_FUSE_SEL_MASK               (0x10U)
88434 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              (4U)
88435 #define SRC_SBMR2_BT_FUSE_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
88436 
88437 #define SRC_SBMR2_BMOD_MASK                      (0x3000000U)
88438 #define SRC_SBMR2_BMOD_SHIFT                     (24U)
88439 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
88440 /*! @} */
88441 
88442 /*! @name SRSR - SRC Reset Status Register */
88443 /*! @{ */
88444 
88445 #define SRC_SRSR_IPP_RESET_B_M7_MASK             (0x1U)
88446 #define SRC_SRSR_IPP_RESET_B_M7_SHIFT            (0U)
88447 /*! IPP_RESET_B_M7
88448  *  0b0..Reset is not a result of ipp_reset_b pin.
88449  *  0b1..Reset is a result of ipp_reset_b pin.
88450  */
88451 #define SRC_SRSR_IPP_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)
88452 
88453 #define SRC_SRSR_M7_REQUEST_M7_MASK              (0x2U)
88454 #define SRC_SRSR_M7_REQUEST_M7_SHIFT             (1U)
88455 /*! M7_REQUEST_M7
88456  *  0b0..Reset is not a result of m7 reset request.
88457  *  0b1..Reset is a result of m7 reset request.
88458  */
88459 #define SRC_SRSR_M7_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)
88460 
88461 #define SRC_SRSR_M7_LOCKUP_M7_MASK               (0x4U)
88462 #define SRC_SRSR_M7_LOCKUP_M7_SHIFT              (2U)
88463 /*! M7_LOCKUP_M7
88464  *  0b0..Reset is not a result of the mentioned case.
88465  *  0b1..Reset is a result of the mentioned case.
88466  */
88467 #define SRC_SRSR_M7_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)
88468 
88469 #define SRC_SRSR_CSU_RESET_B_M7_MASK             (0x8U)
88470 #define SRC_SRSR_CSU_RESET_B_M7_SHIFT            (3U)
88471 /*! CSU_RESET_B_M7
88472  *  0b0..Reset is not a result of the csu_reset_b event.
88473  *  0b1..Reset is a result of the csu_reset_b event.
88474  */
88475 #define SRC_SRSR_CSU_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)
88476 
88477 #define SRC_SRSR_IPP_USER_RESET_B_M7_MASK        (0x10U)
88478 #define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT       (4U)
88479 /*! IPP_USER_RESET_B_M7
88480  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
88481  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
88482  */
88483 #define SRC_SRSR_IPP_USER_RESET_B_M7(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)
88484 
88485 #define SRC_SRSR_WDOG_RST_B_M7_MASK              (0x20U)
88486 #define SRC_SRSR_WDOG_RST_B_M7_SHIFT             (5U)
88487 /*! WDOG_RST_B_M7
88488  *  0b0..Reset is not a result of the watchdog time-out event.
88489  *  0b1..Reset is a result of the watchdog time-out event.
88490  */
88491 #define SRC_SRSR_WDOG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)
88492 
88493 #define SRC_SRSR_JTAG_RST_B_M7_MASK              (0x40U)
88494 #define SRC_SRSR_JTAG_RST_B_M7_SHIFT             (6U)
88495 /*! JTAG_RST_B_M7
88496  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
88497  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
88498  */
88499 #define SRC_SRSR_JTAG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)
88500 
88501 #define SRC_SRSR_JTAG_SW_RST_M7_MASK             (0x80U)
88502 #define SRC_SRSR_JTAG_SW_RST_M7_SHIFT            (7U)
88503 /*! JTAG_SW_RST_M7
88504  *  0b0..Reset is not a result of software reset from JTAG.
88505  *  0b1..Reset is a result of software reset from JTAG.
88506  */
88507 #define SRC_SRSR_JTAG_SW_RST_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)
88508 
88509 #define SRC_SRSR_WDOG3_RST_B_M7_MASK             (0x100U)
88510 #define SRC_SRSR_WDOG3_RST_B_M7_SHIFT            (8U)
88511 /*! WDOG3_RST_B_M7
88512  *  0b0..Reset is not a result of the watchdog3 time-out event.
88513  *  0b1..Reset is a result of the watchdog3 time-out event.
88514  */
88515 #define SRC_SRSR_WDOG3_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)
88516 
88517 #define SRC_SRSR_WDOG4_RST_B_M7_MASK             (0x200U)
88518 #define SRC_SRSR_WDOG4_RST_B_M7_SHIFT            (9U)
88519 /*! WDOG4_RST_B_M7
88520  *  0b0..Reset is not a result of the watchdog4 time-out event.
88521  *  0b1..Reset is a result of the watchdog4 time-out event.
88522  */
88523 #define SRC_SRSR_WDOG4_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)
88524 
88525 #define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK         (0x400U)
88526 #define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT        (10U)
88527 /*! TEMPSENSE_RST_B_M7
88528  *  0b0..Reset is not a result of software reset from Temperature Sensor.
88529  *  0b1..Reset is a result of software reset from Temperature Sensor.
88530  */
88531 #define SRC_SRSR_TEMPSENSE_RST_B_M7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)
88532 
88533 #define SRC_SRSR_M4_REQUEST_M7_MASK              (0x800U)
88534 #define SRC_SRSR_M4_REQUEST_M7_SHIFT             (11U)
88535 /*! M4_REQUEST_M7
88536  *  0b0..Reset is not a result of m4 reset request.
88537  *  0b1..Reset is a result of m4 reset request.
88538  */
88539 #define SRC_SRSR_M4_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)
88540 
88541 #define SRC_SRSR_M4_LOCKUP_M7_MASK               (0x1000U)
88542 #define SRC_SRSR_M4_LOCKUP_M7_SHIFT              (12U)
88543 /*! M4_LOCKUP_M7
88544  *  0b0..Reset is not a result of the mentioned case.
88545  *  0b1..Reset is a result of the mentioned case.
88546  */
88547 #define SRC_SRSR_M4_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)
88548 
88549 #define SRC_SRSR_OVERVOLT_RST_M7_MASK            (0x2000U)
88550 #define SRC_SRSR_OVERVOLT_RST_M7_SHIFT           (13U)
88551 /*! OVERVOLT_RST_M7
88552  *  0b0..Reset is not a result of the mentioned case.
88553  *  0b1..Reset is a result of the mentioned case.
88554  */
88555 #define SRC_SRSR_OVERVOLT_RST_M7(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)
88556 
88557 #define SRC_SRSR_CDOG_RST_M7_MASK                (0x4000U)
88558 #define SRC_SRSR_CDOG_RST_M7_SHIFT               (14U)
88559 /*! CDOG_RST_M7
88560  *  0b0..Reset is not a result of the mentioned case.
88561  *  0b1..Reset is a result of the mentioned case.
88562  */
88563 #define SRC_SRSR_CDOG_RST_M7(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)
88564 
88565 #define SRC_SRSR_IPP_RESET_B_M4_MASK             (0x10000U)
88566 #define SRC_SRSR_IPP_RESET_B_M4_SHIFT            (16U)
88567 /*! IPP_RESET_B_M4
88568  *  0b0..Reset is not a result of ipp_reset_b pin.
88569  *  0b1..Reset is a result of ipp_reset_b pin.
88570  */
88571 #define SRC_SRSR_IPP_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)
88572 
88573 #define SRC_SRSR_M4_REQUEST_M4_MASK              (0x20000U)
88574 #define SRC_SRSR_M4_REQUEST_M4_SHIFT             (17U)
88575 /*! M4_REQUEST_M4
88576  *  0b0..Reset is not a result of m4 reset request.
88577  *  0b1..Reset is a result of m4 reset request.
88578  */
88579 #define SRC_SRSR_M4_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)
88580 
88581 #define SRC_SRSR_M4_LOCKUP_M4_MASK               (0x40000U)
88582 #define SRC_SRSR_M4_LOCKUP_M4_SHIFT              (18U)
88583 /*! M4_LOCKUP_M4
88584  *  0b0..Reset is not a result of the mentioned case.
88585  *  0b1..Reset is a result of the mentioned case.
88586  */
88587 #define SRC_SRSR_M4_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)
88588 
88589 #define SRC_SRSR_CSU_RESET_B_M4_MASK             (0x80000U)
88590 #define SRC_SRSR_CSU_RESET_B_M4_SHIFT            (19U)
88591 /*! CSU_RESET_B_M4
88592  *  0b0..Reset is not a result of the csu_reset_b event.
88593  *  0b1..Reset is a result of the csu_reset_b event.
88594  */
88595 #define SRC_SRSR_CSU_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)
88596 
88597 #define SRC_SRSR_IPP_USER_RESET_B_M4_MASK        (0x100000U)
88598 #define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT       (20U)
88599 /*! IPP_USER_RESET_B_M4
88600  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
88601  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
88602  */
88603 #define SRC_SRSR_IPP_USER_RESET_B_M4(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)
88604 
88605 #define SRC_SRSR_WDOG_RST_B_M4_MASK              (0x200000U)
88606 #define SRC_SRSR_WDOG_RST_B_M4_SHIFT             (21U)
88607 /*! WDOG_RST_B_M4
88608  *  0b0..Reset is not a result of the watchdog time-out event.
88609  *  0b1..Reset is a result of the watchdog time-out event.
88610  */
88611 #define SRC_SRSR_WDOG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)
88612 
88613 #define SRC_SRSR_JTAG_RST_B_M4_MASK              (0x400000U)
88614 #define SRC_SRSR_JTAG_RST_B_M4_SHIFT             (22U)
88615 /*! JTAG_RST_B_M4
88616  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
88617  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
88618  */
88619 #define SRC_SRSR_JTAG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)
88620 
88621 #define SRC_SRSR_JTAG_SW_RST_M4_MASK             (0x800000U)
88622 #define SRC_SRSR_JTAG_SW_RST_M4_SHIFT            (23U)
88623 /*! JTAG_SW_RST_M4
88624  *  0b0..Reset is not a result of software reset from JTAG.
88625  *  0b1..Reset is a result of software reset from JTAG.
88626  */
88627 #define SRC_SRSR_JTAG_SW_RST_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)
88628 
88629 #define SRC_SRSR_WDOG3_RST_B_M4_MASK             (0x1000000U)
88630 #define SRC_SRSR_WDOG3_RST_B_M4_SHIFT            (24U)
88631 /*! WDOG3_RST_B_M4
88632  *  0b0..Reset is not a result of the watchdog3 time-out event.
88633  *  0b1..Reset is a result of the watchdog3 time-out event.
88634  */
88635 #define SRC_SRSR_WDOG3_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)
88636 
88637 #define SRC_SRSR_WDOG4_RST_B_M4_MASK             (0x2000000U)
88638 #define SRC_SRSR_WDOG4_RST_B_M4_SHIFT            (25U)
88639 /*! WDOG4_RST_B_M4
88640  *  0b0..Reset is not a result of the watchdog4 time-out event.
88641  *  0b1..Reset is a result of the watchdog4 time-out event.
88642  */
88643 #define SRC_SRSR_WDOG4_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)
88644 
88645 #define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK         (0x4000000U)
88646 #define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT        (26U)
88647 /*! TEMPSENSE_RST_B_M4
88648  *  0b0..Reset is not a result of software reset from Temperature Sensor.
88649  *  0b1..Reset is a result of software reset from Temperature Sensor.
88650  */
88651 #define SRC_SRSR_TEMPSENSE_RST_B_M4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)
88652 
88653 #define SRC_SRSR_M7_REQUEST_M4_MASK              (0x8000000U)
88654 #define SRC_SRSR_M7_REQUEST_M4_SHIFT             (27U)
88655 /*! M7_REQUEST_M4
88656  *  0b0..Reset is not a result of m7 reset request.
88657  *  0b1..Reset is a result of m7 reset request.
88658  */
88659 #define SRC_SRSR_M7_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)
88660 
88661 #define SRC_SRSR_M7_LOCKUP_M4_MASK               (0x10000000U)
88662 #define SRC_SRSR_M7_LOCKUP_M4_SHIFT              (28U)
88663 /*! M7_LOCKUP_M4
88664  *  0b0..Reset is not a result of the mentioned case.
88665  *  0b1..Reset is a result of the mentioned case.
88666  */
88667 #define SRC_SRSR_M7_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)
88668 
88669 #define SRC_SRSR_OVERVOLT_RST_M4_MASK            (0x20000000U)
88670 #define SRC_SRSR_OVERVOLT_RST_M4_SHIFT           (29U)
88671 /*! OVERVOLT_RST_M4
88672  *  0b0..Reset is not a result of the mentioned case.
88673  *  0b1..Reset is a result of the mentioned case.
88674  */
88675 #define SRC_SRSR_OVERVOLT_RST_M4(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)
88676 
88677 #define SRC_SRSR_CDOG_RST_M4_MASK                (0x40000000U)
88678 #define SRC_SRSR_CDOG_RST_M4_SHIFT               (30U)
88679 /*! CDOG_RST_M4
88680  *  0b0..Reset is not a result of the mentioned case.
88681  *  0b1..Reset is a result of the mentioned case.
88682  */
88683 #define SRC_SRSR_CDOG_RST_M4(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)
88684 /*! @} */
88685 
88686 /*! @name GPR - SRC General Purpose Register */
88687 /*! @{ */
88688 
88689 #define SRC_GPR_GPR_MASK                         (0xFFFFFFFFU)
88690 #define SRC_GPR_GPR_SHIFT                        (0U)
88691 /*! GPR - General Purpose Register.
88692  */
88693 #define SRC_GPR_GPR(x)                           (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)
88694 /*! @} */
88695 
88696 /* The count of SRC_GPR */
88697 #define SRC_GPR_COUNT                            (20U)
88698 
88699 /*! @name AUTHEN_MEGA - Slice Authentication Register */
88700 /*! @{ */
88701 
88702 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK         (0x1U)
88703 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT        (0U)
88704 /*! DOMAIN_MODE
88705  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
88706  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
88707  */
88708 #define SRC_AUTHEN_MEGA_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)
88709 
88710 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK       (0x2U)
88711 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT      (1U)
88712 /*! SETPOINT_MODE
88713  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
88714  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
88715  */
88716 #define SRC_AUTHEN_MEGA_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)
88717 
88718 #define SRC_AUTHEN_MEGA_LOCK_MODE_MASK           (0x80U)
88719 #define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT          (7U)
88720 /*! LOCK_MODE - Domain/Setpoint mode lock
88721  */
88722 #define SRC_AUTHEN_MEGA_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)
88723 
88724 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK         (0xF00U)
88725 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT        (8U)
88726 #define SRC_AUTHEN_MEGA_ASSIGN_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)
88727 
88728 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK         (0x8000U)
88729 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT        (15U)
88730 /*! LOCK_ASSIGN - Assign list lock
88731  */
88732 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)
88733 
88734 #define SRC_AUTHEN_MEGA_WHITE_LIST_MASK          (0xF0000U)
88735 #define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT         (16U)
88736 /*! WHITE_LIST - Domain ID white list
88737  */
88738 #define SRC_AUTHEN_MEGA_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)
88739 
88740 #define SRC_AUTHEN_MEGA_LOCK_LIST_MASK           (0x800000U)
88741 #define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT          (23U)
88742 /*! LOCK_LIST - White list lock
88743  */
88744 #define SRC_AUTHEN_MEGA_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)
88745 
88746 #define SRC_AUTHEN_MEGA_USER_MASK                (0x1000000U)
88747 #define SRC_AUTHEN_MEGA_USER_SHIFT               (24U)
88748 /*! USER - Allow user mode access
88749  */
88750 #define SRC_AUTHEN_MEGA_USER(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)
88751 
88752 #define SRC_AUTHEN_MEGA_NONSECURE_MASK           (0x2000000U)
88753 #define SRC_AUTHEN_MEGA_NONSECURE_SHIFT          (25U)
88754 /*! NONSECURE - Allow non-secure mode access
88755  */
88756 #define SRC_AUTHEN_MEGA_NONSECURE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)
88757 
88758 #define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK        (0x80000000U)
88759 #define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT       (31U)
88760 /*! LOCK_SETTING - Lock NONSECURE and USER
88761  */
88762 #define SRC_AUTHEN_MEGA_LOCK_SETTING(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)
88763 /*! @} */
88764 
88765 /*! @name CTRL_MEGA - Slice Control Register */
88766 /*! @{ */
88767 
88768 #define SRC_CTRL_MEGA_SW_RESET_MASK              (0x1U)
88769 #define SRC_CTRL_MEGA_SW_RESET_SHIFT             (0U)
88770 /*! SW_RESET
88771  *  0b0..do not assert slice software reset
88772  *  0b1..assert slice software reset
88773  */
88774 #define SRC_CTRL_MEGA_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)
88775 /*! @} */
88776 
88777 /*! @name SETPOINT_MEGA - Slice Setpoint Config Register */
88778 /*! @{ */
88779 
88780 #define SRC_SETPOINT_MEGA_SETPOINT0_MASK         (0x1U)
88781 #define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT        (0U)
88782 /*! SETPOINT0 - SETPOINT0
88783  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88784  *  0b1..Slice reset will be asserted when system in Setpoint n
88785  */
88786 #define SRC_SETPOINT_MEGA_SETPOINT0(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)
88787 
88788 #define SRC_SETPOINT_MEGA_SETPOINT1_MASK         (0x2U)
88789 #define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT        (1U)
88790 /*! SETPOINT1 - SETPOINT1
88791  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88792  *  0b1..Slice reset will be asserted when system in Setpoint n
88793  */
88794 #define SRC_SETPOINT_MEGA_SETPOINT1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)
88795 
88796 #define SRC_SETPOINT_MEGA_SETPOINT2_MASK         (0x4U)
88797 #define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT        (2U)
88798 /*! SETPOINT2 - SETPOINT2
88799  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88800  *  0b1..Slice reset will be asserted when system in Setpoint n
88801  */
88802 #define SRC_SETPOINT_MEGA_SETPOINT2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)
88803 
88804 #define SRC_SETPOINT_MEGA_SETPOINT3_MASK         (0x8U)
88805 #define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT        (3U)
88806 /*! SETPOINT3 - SETPOINT3
88807  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88808  *  0b1..Slice reset will be asserted when system in Setpoint n
88809  */
88810 #define SRC_SETPOINT_MEGA_SETPOINT3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)
88811 
88812 #define SRC_SETPOINT_MEGA_SETPOINT4_MASK         (0x10U)
88813 #define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT        (4U)
88814 /*! SETPOINT4 - SETPOINT4
88815  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88816  *  0b1..Slice reset will be asserted when system in Setpoint n
88817  */
88818 #define SRC_SETPOINT_MEGA_SETPOINT4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)
88819 
88820 #define SRC_SETPOINT_MEGA_SETPOINT5_MASK         (0x20U)
88821 #define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT        (5U)
88822 /*! SETPOINT5 - SETPOINT5
88823  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88824  *  0b1..Slice reset will be asserted when system in Setpoint n
88825  */
88826 #define SRC_SETPOINT_MEGA_SETPOINT5(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)
88827 
88828 #define SRC_SETPOINT_MEGA_SETPOINT6_MASK         (0x40U)
88829 #define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT        (6U)
88830 /*! SETPOINT6 - SETPOINT6
88831  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88832  *  0b1..Slice reset will be asserted when system in Setpoint n
88833  */
88834 #define SRC_SETPOINT_MEGA_SETPOINT6(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)
88835 
88836 #define SRC_SETPOINT_MEGA_SETPOINT7_MASK         (0x80U)
88837 #define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT        (7U)
88838 /*! SETPOINT7 - SETPOINT7
88839  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88840  *  0b1..Slice reset will be asserted when system in Setpoint n
88841  */
88842 #define SRC_SETPOINT_MEGA_SETPOINT7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)
88843 
88844 #define SRC_SETPOINT_MEGA_SETPOINT8_MASK         (0x100U)
88845 #define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT        (8U)
88846 /*! SETPOINT8 - SETPOINT8
88847  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88848  *  0b1..Slice reset will be asserted when system in Setpoint n
88849  */
88850 #define SRC_SETPOINT_MEGA_SETPOINT8(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)
88851 
88852 #define SRC_SETPOINT_MEGA_SETPOINT9_MASK         (0x200U)
88853 #define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT        (9U)
88854 /*! SETPOINT9 - SETPOINT9
88855  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88856  *  0b1..Slice reset will be asserted when system in Setpoint n
88857  */
88858 #define SRC_SETPOINT_MEGA_SETPOINT9(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)
88859 
88860 #define SRC_SETPOINT_MEGA_SETPOINT10_MASK        (0x400U)
88861 #define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT       (10U)
88862 /*! SETPOINT10 - SETPOINT10
88863  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88864  *  0b1..Slice reset will be asserted when system in Setpoint n
88865  */
88866 #define SRC_SETPOINT_MEGA_SETPOINT10(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)
88867 
88868 #define SRC_SETPOINT_MEGA_SETPOINT11_MASK        (0x800U)
88869 #define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT       (11U)
88870 /*! SETPOINT11 - SETPOINT11
88871  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88872  *  0b1..Slice reset will be asserted when system in Setpoint n
88873  */
88874 #define SRC_SETPOINT_MEGA_SETPOINT11(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)
88875 
88876 #define SRC_SETPOINT_MEGA_SETPOINT12_MASK        (0x1000U)
88877 #define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT       (12U)
88878 /*! SETPOINT12 - SETPOINT12
88879  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88880  *  0b1..Slice reset will be asserted when system in Setpoint n
88881  */
88882 #define SRC_SETPOINT_MEGA_SETPOINT12(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)
88883 
88884 #define SRC_SETPOINT_MEGA_SETPOINT13_MASK        (0x2000U)
88885 #define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT       (13U)
88886 /*! SETPOINT13 - SETPOINT13
88887  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88888  *  0b1..Slice reset will be asserted when system in Setpoint n
88889  */
88890 #define SRC_SETPOINT_MEGA_SETPOINT13(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)
88891 
88892 #define SRC_SETPOINT_MEGA_SETPOINT14_MASK        (0x4000U)
88893 #define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT       (14U)
88894 /*! SETPOINT14 - SETPOINT14
88895  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88896  *  0b1..Slice reset will be asserted when system in Setpoint n
88897  */
88898 #define SRC_SETPOINT_MEGA_SETPOINT14(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)
88899 
88900 #define SRC_SETPOINT_MEGA_SETPOINT15_MASK        (0x8000U)
88901 #define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT       (15U)
88902 /*! SETPOINT15 - SETPOINT15
88903  *  0b0..Slice reset will be de-asserted when system in Setpoint n
88904  *  0b1..Slice reset will be asserted when system in Setpoint n
88905  */
88906 #define SRC_SETPOINT_MEGA_SETPOINT15(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)
88907 /*! @} */
88908 
88909 /*! @name DOMAIN_MEGA - Slice Domain Config Register */
88910 /*! @{ */
88911 
88912 #define SRC_DOMAIN_MEGA_CPU0_RUN_MASK            (0x1U)
88913 #define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT           (0U)
88914 /*! CPU0_RUN - CPU mode setting for RUN
88915  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
88916  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
88917  */
88918 #define SRC_DOMAIN_MEGA_CPU0_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)
88919 
88920 #define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK           (0x2U)
88921 #define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT          (1U)
88922 /*! CPU0_WAIT - CPU mode setting for WAIT
88923  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
88924  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
88925  */
88926 #define SRC_DOMAIN_MEGA_CPU0_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)
88927 
88928 #define SRC_DOMAIN_MEGA_CPU0_STOP_MASK           (0x4U)
88929 #define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT          (2U)
88930 /*! CPU0_STOP - CPU mode setting for STOP
88931  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
88932  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
88933  */
88934 #define SRC_DOMAIN_MEGA_CPU0_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)
88935 
88936 #define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK           (0x8U)
88937 #define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT          (3U)
88938 /*! CPU0_SUSP - CPU mode setting for SUSPEND
88939  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
88940  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
88941  */
88942 #define SRC_DOMAIN_MEGA_CPU0_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)
88943 
88944 #define SRC_DOMAIN_MEGA_CPU1_RUN_MASK            (0x10U)
88945 #define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT           (4U)
88946 /*! CPU1_RUN - CPU mode setting for RUN
88947  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
88948  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
88949  */
88950 #define SRC_DOMAIN_MEGA_CPU1_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)
88951 
88952 #define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK           (0x20U)
88953 #define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT          (5U)
88954 /*! CPU1_WAIT - CPU mode setting for WAIT
88955  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
88956  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
88957  */
88958 #define SRC_DOMAIN_MEGA_CPU1_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)
88959 
88960 #define SRC_DOMAIN_MEGA_CPU1_STOP_MASK           (0x40U)
88961 #define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT          (6U)
88962 /*! CPU1_STOP - CPU mode setting for STOP
88963  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
88964  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
88965  */
88966 #define SRC_DOMAIN_MEGA_CPU1_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)
88967 
88968 #define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK           (0x80U)
88969 #define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT          (7U)
88970 /*! CPU1_SUSP - CPU mode setting for SUSPEND
88971  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
88972  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
88973  */
88974 #define SRC_DOMAIN_MEGA_CPU1_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)
88975 /*! @} */
88976 
88977 /*! @name STAT_MEGA - Slice Status Register */
88978 /*! @{ */
88979 
88980 #define SRC_STAT_MEGA_UNDER_RST_MASK             (0x1U)
88981 #define SRC_STAT_MEGA_UNDER_RST_SHIFT            (0U)
88982 /*! UNDER_RST
88983  *  0b0..the reset is finished
88984  *  0b1..the reset is in process
88985  */
88986 #define SRC_STAT_MEGA_UNDER_RST(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)
88987 
88988 #define SRC_STAT_MEGA_RST_BY_HW_MASK             (0x4U)
88989 #define SRC_STAT_MEGA_RST_BY_HW_SHIFT            (2U)
88990 /*! RST_BY_HW
88991  *  0b0..the reset is not caused by the power mode transfer
88992  *  0b1..the reset is caused by the power mode transfer
88993  */
88994 #define SRC_STAT_MEGA_RST_BY_HW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)
88995 
88996 #define SRC_STAT_MEGA_RST_BY_SW_MASK             (0x8U)
88997 #define SRC_STAT_MEGA_RST_BY_SW_SHIFT            (3U)
88998 /*! RST_BY_SW
88999  *  0b0..the reset is not caused by software setting
89000  *  0b1..the reset is caused by software setting
89001  */
89002 #define SRC_STAT_MEGA_RST_BY_SW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)
89003 /*! @} */
89004 
89005 /*! @name AUTHEN_DISPLAY - Slice Authentication Register */
89006 /*! @{ */
89007 
89008 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK      (0x1U)
89009 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT     (0U)
89010 /*! DOMAIN_MODE
89011  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89012  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89013  */
89014 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)
89015 
89016 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK    (0x2U)
89017 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT   (1U)
89018 /*! SETPOINT_MODE
89019  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89020  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89021  */
89022 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)
89023 
89024 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK        (0x80U)
89025 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT       (7U)
89026 /*! LOCK_MODE - Domain/Setpoint mode lock
89027  */
89028 #define SRC_AUTHEN_DISPLAY_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)
89029 
89030 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK      (0xF00U)
89031 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT     (8U)
89032 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)
89033 
89034 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK      (0x8000U)
89035 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT     (15U)
89036 /*! LOCK_ASSIGN - Assign list lock
89037  */
89038 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)
89039 
89040 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK       (0xF0000U)
89041 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT      (16U)
89042 /*! WHITE_LIST - Domain ID white list
89043  */
89044 #define SRC_AUTHEN_DISPLAY_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)
89045 
89046 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK        (0x800000U)
89047 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT       (23U)
89048 /*! LOCK_LIST - White list lock
89049  */
89050 #define SRC_AUTHEN_DISPLAY_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)
89051 
89052 #define SRC_AUTHEN_DISPLAY_USER_MASK             (0x1000000U)
89053 #define SRC_AUTHEN_DISPLAY_USER_SHIFT            (24U)
89054 /*! USER - Allow user mode access
89055  */
89056 #define SRC_AUTHEN_DISPLAY_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)
89057 
89058 #define SRC_AUTHEN_DISPLAY_NONSECURE_MASK        (0x2000000U)
89059 #define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT       (25U)
89060 /*! NONSECURE - Allow non-secure mode access
89061  */
89062 #define SRC_AUTHEN_DISPLAY_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)
89063 
89064 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK     (0x80000000U)
89065 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT    (31U)
89066 /*! LOCK_SETTING - Lock NONSECURE and USER
89067  */
89068 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)
89069 /*! @} */
89070 
89071 /*! @name CTRL_DISPLAY - Slice Control Register */
89072 /*! @{ */
89073 
89074 #define SRC_CTRL_DISPLAY_SW_RESET_MASK           (0x1U)
89075 #define SRC_CTRL_DISPLAY_SW_RESET_SHIFT          (0U)
89076 /*! SW_RESET
89077  *  0b0..do not assert slice software reset
89078  *  0b1..assert slice software reset
89079  */
89080 #define SRC_CTRL_DISPLAY_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)
89081 /*! @} */
89082 
89083 /*! @name SETPOINT_DISPLAY - Slice Setpoint Config Register */
89084 /*! @{ */
89085 
89086 #define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK      (0x1U)
89087 #define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT     (0U)
89088 /*! SETPOINT0 - SETPOINT0
89089  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89090  *  0b1..Slice reset will be asserted when system in Setpoint n
89091  */
89092 #define SRC_SETPOINT_DISPLAY_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)
89093 
89094 #define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK      (0x2U)
89095 #define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT     (1U)
89096 /*! SETPOINT1 - SETPOINT1
89097  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89098  *  0b1..Slice reset will be asserted when system in Setpoint n
89099  */
89100 #define SRC_SETPOINT_DISPLAY_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)
89101 
89102 #define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK      (0x4U)
89103 #define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT     (2U)
89104 /*! SETPOINT2 - SETPOINT2
89105  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89106  *  0b1..Slice reset will be asserted when system in Setpoint n
89107  */
89108 #define SRC_SETPOINT_DISPLAY_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)
89109 
89110 #define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK      (0x8U)
89111 #define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT     (3U)
89112 /*! SETPOINT3 - SETPOINT3
89113  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89114  *  0b1..Slice reset will be asserted when system in Setpoint n
89115  */
89116 #define SRC_SETPOINT_DISPLAY_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)
89117 
89118 #define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK      (0x10U)
89119 #define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT     (4U)
89120 /*! SETPOINT4 - SETPOINT4
89121  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89122  *  0b1..Slice reset will be asserted when system in Setpoint n
89123  */
89124 #define SRC_SETPOINT_DISPLAY_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)
89125 
89126 #define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK      (0x20U)
89127 #define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT     (5U)
89128 /*! SETPOINT5 - SETPOINT5
89129  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89130  *  0b1..Slice reset will be asserted when system in Setpoint n
89131  */
89132 #define SRC_SETPOINT_DISPLAY_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)
89133 
89134 #define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK      (0x40U)
89135 #define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT     (6U)
89136 /*! SETPOINT6 - SETPOINT6
89137  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89138  *  0b1..Slice reset will be asserted when system in Setpoint n
89139  */
89140 #define SRC_SETPOINT_DISPLAY_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)
89141 
89142 #define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK      (0x80U)
89143 #define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT     (7U)
89144 /*! SETPOINT7 - SETPOINT7
89145  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89146  *  0b1..Slice reset will be asserted when system in Setpoint n
89147  */
89148 #define SRC_SETPOINT_DISPLAY_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)
89149 
89150 #define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK      (0x100U)
89151 #define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT     (8U)
89152 /*! SETPOINT8 - SETPOINT8
89153  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89154  *  0b1..Slice reset will be asserted when system in Setpoint n
89155  */
89156 #define SRC_SETPOINT_DISPLAY_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)
89157 
89158 #define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK      (0x200U)
89159 #define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT     (9U)
89160 /*! SETPOINT9 - SETPOINT9
89161  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89162  *  0b1..Slice reset will be asserted when system in Setpoint n
89163  */
89164 #define SRC_SETPOINT_DISPLAY_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)
89165 
89166 #define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK     (0x400U)
89167 #define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT    (10U)
89168 /*! SETPOINT10 - SETPOINT10
89169  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89170  *  0b1..Slice reset will be asserted when system in Setpoint n
89171  */
89172 #define SRC_SETPOINT_DISPLAY_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)
89173 
89174 #define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK     (0x800U)
89175 #define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT    (11U)
89176 /*! SETPOINT11 - SETPOINT11
89177  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89178  *  0b1..Slice reset will be asserted when system in Setpoint n
89179  */
89180 #define SRC_SETPOINT_DISPLAY_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)
89181 
89182 #define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK     (0x1000U)
89183 #define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT    (12U)
89184 /*! SETPOINT12 - SETPOINT12
89185  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89186  *  0b1..Slice reset will be asserted when system in Setpoint n
89187  */
89188 #define SRC_SETPOINT_DISPLAY_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)
89189 
89190 #define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK     (0x2000U)
89191 #define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT    (13U)
89192 /*! SETPOINT13 - SETPOINT13
89193  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89194  *  0b1..Slice reset will be asserted when system in Setpoint n
89195  */
89196 #define SRC_SETPOINT_DISPLAY_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)
89197 
89198 #define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK     (0x4000U)
89199 #define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT    (14U)
89200 /*! SETPOINT14 - SETPOINT14
89201  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89202  *  0b1..Slice reset will be asserted when system in Setpoint n
89203  */
89204 #define SRC_SETPOINT_DISPLAY_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)
89205 
89206 #define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK     (0x8000U)
89207 #define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT    (15U)
89208 /*! SETPOINT15 - SETPOINT15
89209  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89210  *  0b1..Slice reset will be asserted when system in Setpoint n
89211  */
89212 #define SRC_SETPOINT_DISPLAY_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)
89213 /*! @} */
89214 
89215 /*! @name DOMAIN_DISPLAY - Slice Domain Config Register */
89216 /*! @{ */
89217 
89218 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK         (0x1U)
89219 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT        (0U)
89220 /*! CPU0_RUN - CPU mode setting for RUN
89221  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89222  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89223  */
89224 #define SRC_DOMAIN_DISPLAY_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)
89225 
89226 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK        (0x2U)
89227 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT       (1U)
89228 /*! CPU0_WAIT - CPU mode setting for WAIT
89229  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89230  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89231  */
89232 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)
89233 
89234 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK        (0x4U)
89235 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT       (2U)
89236 /*! CPU0_STOP - CPU mode setting for STOP
89237  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89238  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89239  */
89240 #define SRC_DOMAIN_DISPLAY_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)
89241 
89242 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK        (0x8U)
89243 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT       (3U)
89244 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89245  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89246  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89247  */
89248 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)
89249 
89250 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK         (0x10U)
89251 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT        (4U)
89252 /*! CPU1_RUN - CPU mode setting for RUN
89253  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89254  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89255  */
89256 #define SRC_DOMAIN_DISPLAY_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)
89257 
89258 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK        (0x20U)
89259 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT       (5U)
89260 /*! CPU1_WAIT - CPU mode setting for WAIT
89261  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89262  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89263  */
89264 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)
89265 
89266 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK        (0x40U)
89267 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT       (6U)
89268 /*! CPU1_STOP - CPU mode setting for STOP
89269  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89270  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89271  */
89272 #define SRC_DOMAIN_DISPLAY_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)
89273 
89274 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK        (0x80U)
89275 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT       (7U)
89276 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89277  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89278  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89279  */
89280 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)
89281 /*! @} */
89282 
89283 /*! @name STAT_DISPLAY - Slice Status Register */
89284 /*! @{ */
89285 
89286 #define SRC_STAT_DISPLAY_UNDER_RST_MASK          (0x1U)
89287 #define SRC_STAT_DISPLAY_UNDER_RST_SHIFT         (0U)
89288 /*! UNDER_RST
89289  *  0b0..the reset is finished
89290  *  0b1..the reset is in process
89291  */
89292 #define SRC_STAT_DISPLAY_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)
89293 
89294 #define SRC_STAT_DISPLAY_RST_BY_HW_MASK          (0x4U)
89295 #define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT         (2U)
89296 /*! RST_BY_HW
89297  *  0b0..the reset is not caused by the power mode transfer
89298  *  0b1..the reset is caused by the power mode transfer
89299  */
89300 #define SRC_STAT_DISPLAY_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)
89301 
89302 #define SRC_STAT_DISPLAY_RST_BY_SW_MASK          (0x8U)
89303 #define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT         (3U)
89304 /*! RST_BY_SW
89305  *  0b0..the reset is not caused by software setting
89306  *  0b1..the reset is caused by software setting
89307  */
89308 #define SRC_STAT_DISPLAY_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)
89309 /*! @} */
89310 
89311 /*! @name AUTHEN_WAKEUP - Slice Authentication Register */
89312 /*! @{ */
89313 
89314 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK       (0x1U)
89315 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT      (0U)
89316 /*! DOMAIN_MODE
89317  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89318  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89319  */
89320 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)
89321 
89322 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK     (0x2U)
89323 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT    (1U)
89324 /*! SETPOINT_MODE
89325  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89326  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89327  */
89328 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)
89329 
89330 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK         (0x80U)
89331 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT        (7U)
89332 /*! LOCK_MODE - Domain/Setpoint mode lock
89333  */
89334 #define SRC_AUTHEN_WAKEUP_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)
89335 
89336 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK       (0xF00U)
89337 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT      (8U)
89338 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)
89339 
89340 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK       (0x8000U)
89341 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT      (15U)
89342 /*! LOCK_ASSIGN - Assign list lock
89343  */
89344 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)
89345 
89346 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK        (0xF0000U)
89347 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT       (16U)
89348 /*! WHITE_LIST - Domain ID white list
89349  */
89350 #define SRC_AUTHEN_WAKEUP_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)
89351 
89352 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK         (0x800000U)
89353 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT        (23U)
89354 /*! LOCK_LIST - White list lock
89355  */
89356 #define SRC_AUTHEN_WAKEUP_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)
89357 
89358 #define SRC_AUTHEN_WAKEUP_USER_MASK              (0x1000000U)
89359 #define SRC_AUTHEN_WAKEUP_USER_SHIFT             (24U)
89360 /*! USER - Allow user mode access
89361  */
89362 #define SRC_AUTHEN_WAKEUP_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)
89363 
89364 #define SRC_AUTHEN_WAKEUP_NONSECURE_MASK         (0x2000000U)
89365 #define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT        (25U)
89366 /*! NONSECURE - Allow non-secure mode access
89367  */
89368 #define SRC_AUTHEN_WAKEUP_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)
89369 
89370 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK      (0x80000000U)
89371 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT     (31U)
89372 /*! LOCK_SETTING - Lock NONSECURE and USER
89373  */
89374 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)
89375 /*! @} */
89376 
89377 /*! @name CTRL_WAKEUP - Slice Control Register */
89378 /*! @{ */
89379 
89380 #define SRC_CTRL_WAKEUP_SW_RESET_MASK            (0x1U)
89381 #define SRC_CTRL_WAKEUP_SW_RESET_SHIFT           (0U)
89382 /*! SW_RESET
89383  *  0b0..do not assert slice software reset
89384  *  0b1..assert slice software reset
89385  */
89386 #define SRC_CTRL_WAKEUP_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)
89387 /*! @} */
89388 
89389 /*! @name SETPOINT_WAKEUP - Slice Setpoint Config Register */
89390 /*! @{ */
89391 
89392 #define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK       (0x1U)
89393 #define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT      (0U)
89394 /*! SETPOINT0 - SETPOINT0
89395  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89396  *  0b1..Slice reset will be asserted when system in Setpoint n
89397  */
89398 #define SRC_SETPOINT_WAKEUP_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)
89399 
89400 #define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK       (0x2U)
89401 #define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT      (1U)
89402 /*! SETPOINT1 - SETPOINT1
89403  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89404  *  0b1..Slice reset will be asserted when system in Setpoint n
89405  */
89406 #define SRC_SETPOINT_WAKEUP_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)
89407 
89408 #define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK       (0x4U)
89409 #define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT      (2U)
89410 /*! SETPOINT2 - SETPOINT2
89411  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89412  *  0b1..Slice reset will be asserted when system in Setpoint n
89413  */
89414 #define SRC_SETPOINT_WAKEUP_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)
89415 
89416 #define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK       (0x8U)
89417 #define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT      (3U)
89418 /*! SETPOINT3 - SETPOINT3
89419  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89420  *  0b1..Slice reset will be asserted when system in Setpoint n
89421  */
89422 #define SRC_SETPOINT_WAKEUP_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)
89423 
89424 #define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK       (0x10U)
89425 #define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT      (4U)
89426 /*! SETPOINT4 - SETPOINT4
89427  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89428  *  0b1..Slice reset will be asserted when system in Setpoint n
89429  */
89430 #define SRC_SETPOINT_WAKEUP_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)
89431 
89432 #define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK       (0x20U)
89433 #define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT      (5U)
89434 /*! SETPOINT5 - SETPOINT5
89435  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89436  *  0b1..Slice reset will be asserted when system in Setpoint n
89437  */
89438 #define SRC_SETPOINT_WAKEUP_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)
89439 
89440 #define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK       (0x40U)
89441 #define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT      (6U)
89442 /*! SETPOINT6 - SETPOINT6
89443  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89444  *  0b1..Slice reset will be asserted when system in Setpoint n
89445  */
89446 #define SRC_SETPOINT_WAKEUP_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)
89447 
89448 #define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK       (0x80U)
89449 #define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT      (7U)
89450 /*! SETPOINT7 - SETPOINT7
89451  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89452  *  0b1..Slice reset will be asserted when system in Setpoint n
89453  */
89454 #define SRC_SETPOINT_WAKEUP_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)
89455 
89456 #define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK       (0x100U)
89457 #define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT      (8U)
89458 /*! SETPOINT8 - SETPOINT8
89459  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89460  *  0b1..Slice reset will be asserted when system in Setpoint n
89461  */
89462 #define SRC_SETPOINT_WAKEUP_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)
89463 
89464 #define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK       (0x200U)
89465 #define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT      (9U)
89466 /*! SETPOINT9 - SETPOINT9
89467  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89468  *  0b1..Slice reset will be asserted when system in Setpoint n
89469  */
89470 #define SRC_SETPOINT_WAKEUP_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)
89471 
89472 #define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK      (0x400U)
89473 #define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT     (10U)
89474 /*! SETPOINT10 - SETPOINT10
89475  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89476  *  0b1..Slice reset will be asserted when system in Setpoint n
89477  */
89478 #define SRC_SETPOINT_WAKEUP_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)
89479 
89480 #define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK      (0x800U)
89481 #define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT     (11U)
89482 /*! SETPOINT11 - SETPOINT11
89483  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89484  *  0b1..Slice reset will be asserted when system in Setpoint n
89485  */
89486 #define SRC_SETPOINT_WAKEUP_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)
89487 
89488 #define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK      (0x1000U)
89489 #define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT     (12U)
89490 /*! SETPOINT12 - SETPOINT12
89491  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89492  *  0b1..Slice reset will be asserted when system in Setpoint n
89493  */
89494 #define SRC_SETPOINT_WAKEUP_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)
89495 
89496 #define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK      (0x2000U)
89497 #define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT     (13U)
89498 /*! SETPOINT13 - SETPOINT13
89499  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89500  *  0b1..Slice reset will be asserted when system in Setpoint n
89501  */
89502 #define SRC_SETPOINT_WAKEUP_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)
89503 
89504 #define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK      (0x4000U)
89505 #define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT     (14U)
89506 /*! SETPOINT14 - SETPOINT14
89507  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89508  *  0b1..Slice reset will be asserted when system in Setpoint n
89509  */
89510 #define SRC_SETPOINT_WAKEUP_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)
89511 
89512 #define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK      (0x8000U)
89513 #define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT     (15U)
89514 /*! SETPOINT15 - SETPOINT15
89515  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89516  *  0b1..Slice reset will be asserted when system in Setpoint n
89517  */
89518 #define SRC_SETPOINT_WAKEUP_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)
89519 /*! @} */
89520 
89521 /*! @name DOMAIN_WAKEUP - Slice Domain Config Register */
89522 /*! @{ */
89523 
89524 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK          (0x1U)
89525 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT         (0U)
89526 /*! CPU0_RUN - CPU mode setting for RUN
89527  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89528  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89529  */
89530 #define SRC_DOMAIN_WAKEUP_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)
89531 
89532 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK         (0x2U)
89533 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT        (1U)
89534 /*! CPU0_WAIT - CPU mode setting for WAIT
89535  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89536  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89537  */
89538 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)
89539 
89540 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK         (0x4U)
89541 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT        (2U)
89542 /*! CPU0_STOP - CPU mode setting for STOP
89543  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89544  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89545  */
89546 #define SRC_DOMAIN_WAKEUP_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)
89547 
89548 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK         (0x8U)
89549 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT        (3U)
89550 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89551  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89552  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89553  */
89554 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)
89555 
89556 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK          (0x10U)
89557 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT         (4U)
89558 /*! CPU1_RUN - CPU mode setting for RUN
89559  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89560  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89561  */
89562 #define SRC_DOMAIN_WAKEUP_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)
89563 
89564 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK         (0x20U)
89565 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT        (5U)
89566 /*! CPU1_WAIT - CPU mode setting for WAIT
89567  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89568  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89569  */
89570 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)
89571 
89572 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK         (0x40U)
89573 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT        (6U)
89574 /*! CPU1_STOP - CPU mode setting for STOP
89575  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89576  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89577  */
89578 #define SRC_DOMAIN_WAKEUP_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)
89579 
89580 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK         (0x80U)
89581 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT        (7U)
89582 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89583  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89584  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89585  */
89586 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)
89587 /*! @} */
89588 
89589 /*! @name STAT_WAKEUP - Slice Status Register */
89590 /*! @{ */
89591 
89592 #define SRC_STAT_WAKEUP_UNDER_RST_MASK           (0x1U)
89593 #define SRC_STAT_WAKEUP_UNDER_RST_SHIFT          (0U)
89594 /*! UNDER_RST
89595  *  0b0..the reset is finished
89596  *  0b1..the reset is in process
89597  */
89598 #define SRC_STAT_WAKEUP_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)
89599 
89600 #define SRC_STAT_WAKEUP_RST_BY_HW_MASK           (0x4U)
89601 #define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT          (2U)
89602 /*! RST_BY_HW
89603  *  0b0..the reset is not caused by the power mode transfer
89604  *  0b1..the reset is caused by the power mode transfer
89605  */
89606 #define SRC_STAT_WAKEUP_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)
89607 
89608 #define SRC_STAT_WAKEUP_RST_BY_SW_MASK           (0x8U)
89609 #define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT          (3U)
89610 /*! RST_BY_SW
89611  *  0b0..the reset is not caused by software setting
89612  *  0b1..the reset is caused by software setting
89613  */
89614 #define SRC_STAT_WAKEUP_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)
89615 /*! @} */
89616 
89617 /*! @name AUTHEN_M4CORE - Slice Authentication Register */
89618 /*! @{ */
89619 
89620 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK       (0x1U)
89621 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT      (0U)
89622 /*! DOMAIN_MODE
89623  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89624  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89625  */
89626 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)
89627 
89628 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK     (0x2U)
89629 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT    (1U)
89630 /*! SETPOINT_MODE
89631  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89632  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89633  */
89634 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)
89635 
89636 #define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK         (0x80U)
89637 #define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT        (7U)
89638 /*! LOCK_MODE - Domain/Setpoint mode lock
89639  */
89640 #define SRC_AUTHEN_M4CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)
89641 
89642 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK       (0xF00U)
89643 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT      (8U)
89644 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)
89645 
89646 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK       (0x8000U)
89647 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT      (15U)
89648 /*! LOCK_ASSIGN - Assign list lock
89649  */
89650 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)
89651 
89652 #define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK        (0xF0000U)
89653 #define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT       (16U)
89654 /*! WHITE_LIST - Domain ID white list
89655  */
89656 #define SRC_AUTHEN_M4CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)
89657 
89658 #define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK         (0x800000U)
89659 #define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT        (23U)
89660 /*! LOCK_LIST - White list lock
89661  */
89662 #define SRC_AUTHEN_M4CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)
89663 
89664 #define SRC_AUTHEN_M4CORE_USER_MASK              (0x1000000U)
89665 #define SRC_AUTHEN_M4CORE_USER_SHIFT             (24U)
89666 /*! USER - Allow user mode access
89667  */
89668 #define SRC_AUTHEN_M4CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)
89669 
89670 #define SRC_AUTHEN_M4CORE_NONSECURE_MASK         (0x2000000U)
89671 #define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT        (25U)
89672 /*! NONSECURE - Allow non-secure mode access
89673  */
89674 #define SRC_AUTHEN_M4CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)
89675 
89676 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK      (0x80000000U)
89677 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT     (31U)
89678 /*! LOCK_SETTING - Lock NONSECURE and USER
89679  */
89680 #define SRC_AUTHEN_M4CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)
89681 /*! @} */
89682 
89683 /*! @name CTRL_M4CORE - Slice Control Register */
89684 /*! @{ */
89685 
89686 #define SRC_CTRL_M4CORE_SW_RESET_MASK            (0x1U)
89687 #define SRC_CTRL_M4CORE_SW_RESET_SHIFT           (0U)
89688 /*! SW_RESET
89689  *  0b0..do not assert slice software reset
89690  *  0b1..assert slice software reset
89691  */
89692 #define SRC_CTRL_M4CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)
89693 /*! @} */
89694 
89695 /*! @name SETPOINT_M4CORE - Slice Setpoint Config Register */
89696 /*! @{ */
89697 
89698 #define SRC_SETPOINT_M4CORE_SETPOINT0_MASK       (0x1U)
89699 #define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT      (0U)
89700 /*! SETPOINT0 - SETPOINT0
89701  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89702  *  0b1..Slice reset will be asserted when system in Setpoint n
89703  */
89704 #define SRC_SETPOINT_M4CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)
89705 
89706 #define SRC_SETPOINT_M4CORE_SETPOINT1_MASK       (0x2U)
89707 #define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT      (1U)
89708 /*! SETPOINT1 - SETPOINT1
89709  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89710  *  0b1..Slice reset will be asserted when system in Setpoint n
89711  */
89712 #define SRC_SETPOINT_M4CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)
89713 
89714 #define SRC_SETPOINT_M4CORE_SETPOINT2_MASK       (0x4U)
89715 #define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT      (2U)
89716 /*! SETPOINT2 - SETPOINT2
89717  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89718  *  0b1..Slice reset will be asserted when system in Setpoint n
89719  */
89720 #define SRC_SETPOINT_M4CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)
89721 
89722 #define SRC_SETPOINT_M4CORE_SETPOINT3_MASK       (0x8U)
89723 #define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT      (3U)
89724 /*! SETPOINT3 - SETPOINT3
89725  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89726  *  0b1..Slice reset will be asserted when system in Setpoint n
89727  */
89728 #define SRC_SETPOINT_M4CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)
89729 
89730 #define SRC_SETPOINT_M4CORE_SETPOINT4_MASK       (0x10U)
89731 #define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT      (4U)
89732 /*! SETPOINT4 - SETPOINT4
89733  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89734  *  0b1..Slice reset will be asserted when system in Setpoint n
89735  */
89736 #define SRC_SETPOINT_M4CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)
89737 
89738 #define SRC_SETPOINT_M4CORE_SETPOINT5_MASK       (0x20U)
89739 #define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT      (5U)
89740 /*! SETPOINT5 - SETPOINT5
89741  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89742  *  0b1..Slice reset will be asserted when system in Setpoint n
89743  */
89744 #define SRC_SETPOINT_M4CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)
89745 
89746 #define SRC_SETPOINT_M4CORE_SETPOINT6_MASK       (0x40U)
89747 #define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT      (6U)
89748 /*! SETPOINT6 - SETPOINT6
89749  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89750  *  0b1..Slice reset will be asserted when system in Setpoint n
89751  */
89752 #define SRC_SETPOINT_M4CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)
89753 
89754 #define SRC_SETPOINT_M4CORE_SETPOINT7_MASK       (0x80U)
89755 #define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT      (7U)
89756 /*! SETPOINT7 - SETPOINT7
89757  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89758  *  0b1..Slice reset will be asserted when system in Setpoint n
89759  */
89760 #define SRC_SETPOINT_M4CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)
89761 
89762 #define SRC_SETPOINT_M4CORE_SETPOINT8_MASK       (0x100U)
89763 #define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT      (8U)
89764 /*! SETPOINT8 - SETPOINT8
89765  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89766  *  0b1..Slice reset will be asserted when system in Setpoint n
89767  */
89768 #define SRC_SETPOINT_M4CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)
89769 
89770 #define SRC_SETPOINT_M4CORE_SETPOINT9_MASK       (0x200U)
89771 #define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT      (9U)
89772 /*! SETPOINT9 - SETPOINT9
89773  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89774  *  0b1..Slice reset will be asserted when system in Setpoint n
89775  */
89776 #define SRC_SETPOINT_M4CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)
89777 
89778 #define SRC_SETPOINT_M4CORE_SETPOINT10_MASK      (0x400U)
89779 #define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT     (10U)
89780 /*! SETPOINT10 - SETPOINT10
89781  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89782  *  0b1..Slice reset will be asserted when system in Setpoint n
89783  */
89784 #define SRC_SETPOINT_M4CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)
89785 
89786 #define SRC_SETPOINT_M4CORE_SETPOINT11_MASK      (0x800U)
89787 #define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT     (11U)
89788 /*! SETPOINT11 - SETPOINT11
89789  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89790  *  0b1..Slice reset will be asserted when system in Setpoint n
89791  */
89792 #define SRC_SETPOINT_M4CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)
89793 
89794 #define SRC_SETPOINT_M4CORE_SETPOINT12_MASK      (0x1000U)
89795 #define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT     (12U)
89796 /*! SETPOINT12 - SETPOINT12
89797  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89798  *  0b1..Slice reset will be asserted when system in Setpoint n
89799  */
89800 #define SRC_SETPOINT_M4CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)
89801 
89802 #define SRC_SETPOINT_M4CORE_SETPOINT13_MASK      (0x2000U)
89803 #define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT     (13U)
89804 /*! SETPOINT13 - SETPOINT13
89805  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89806  *  0b1..Slice reset will be asserted when system in Setpoint n
89807  */
89808 #define SRC_SETPOINT_M4CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)
89809 
89810 #define SRC_SETPOINT_M4CORE_SETPOINT14_MASK      (0x4000U)
89811 #define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT     (14U)
89812 /*! SETPOINT14 - SETPOINT14
89813  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89814  *  0b1..Slice reset will be asserted when system in Setpoint n
89815  */
89816 #define SRC_SETPOINT_M4CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)
89817 
89818 #define SRC_SETPOINT_M4CORE_SETPOINT15_MASK      (0x8000U)
89819 #define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT     (15U)
89820 /*! SETPOINT15 - SETPOINT15
89821  *  0b0..Slice reset will be de-asserted when system in Setpoint n
89822  *  0b1..Slice reset will be asserted when system in Setpoint n
89823  */
89824 #define SRC_SETPOINT_M4CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)
89825 /*! @} */
89826 
89827 /*! @name DOMAIN_M4CORE - Slice Domain Config Register */
89828 /*! @{ */
89829 
89830 #define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK          (0x1U)
89831 #define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT         (0U)
89832 /*! CPU0_RUN - CPU mode setting for RUN
89833  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
89834  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
89835  */
89836 #define SRC_DOMAIN_M4CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)
89837 
89838 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK         (0x2U)
89839 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT        (1U)
89840 /*! CPU0_WAIT - CPU mode setting for WAIT
89841  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
89842  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
89843  */
89844 #define SRC_DOMAIN_M4CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)
89845 
89846 #define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK         (0x4U)
89847 #define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT        (2U)
89848 /*! CPU0_STOP - CPU mode setting for STOP
89849  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
89850  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
89851  */
89852 #define SRC_DOMAIN_M4CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)
89853 
89854 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK         (0x8U)
89855 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT        (3U)
89856 /*! CPU0_SUSP - CPU mode setting for SUSPEND
89857  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
89858  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
89859  */
89860 #define SRC_DOMAIN_M4CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)
89861 
89862 #define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK          (0x10U)
89863 #define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT         (4U)
89864 /*! CPU1_RUN - CPU mode setting for RUN
89865  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
89866  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
89867  */
89868 #define SRC_DOMAIN_M4CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)
89869 
89870 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK         (0x20U)
89871 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT        (5U)
89872 /*! CPU1_WAIT - CPU mode setting for WAIT
89873  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
89874  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
89875  */
89876 #define SRC_DOMAIN_M4CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)
89877 
89878 #define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK         (0x40U)
89879 #define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT        (6U)
89880 /*! CPU1_STOP - CPU mode setting for STOP
89881  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
89882  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
89883  */
89884 #define SRC_DOMAIN_M4CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)
89885 
89886 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK         (0x80U)
89887 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT        (7U)
89888 /*! CPU1_SUSP - CPU mode setting for SUSPEND
89889  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
89890  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
89891  */
89892 #define SRC_DOMAIN_M4CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)
89893 /*! @} */
89894 
89895 /*! @name STAT_M4CORE - Slice Status Register */
89896 /*! @{ */
89897 
89898 #define SRC_STAT_M4CORE_UNDER_RST_MASK           (0x1U)
89899 #define SRC_STAT_M4CORE_UNDER_RST_SHIFT          (0U)
89900 /*! UNDER_RST
89901  *  0b0..the reset is finished
89902  *  0b1..the reset is in process
89903  */
89904 #define SRC_STAT_M4CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)
89905 
89906 #define SRC_STAT_M4CORE_RST_BY_HW_MASK           (0x4U)
89907 #define SRC_STAT_M4CORE_RST_BY_HW_SHIFT          (2U)
89908 /*! RST_BY_HW
89909  *  0b0..the reset is not caused by the power mode transfer
89910  *  0b1..the reset is caused by the power mode transfer
89911  */
89912 #define SRC_STAT_M4CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)
89913 
89914 #define SRC_STAT_M4CORE_RST_BY_SW_MASK           (0x8U)
89915 #define SRC_STAT_M4CORE_RST_BY_SW_SHIFT          (3U)
89916 /*! RST_BY_SW
89917  *  0b0..the reset is not caused by software setting
89918  *  0b1..the reset is caused by software setting
89919  */
89920 #define SRC_STAT_M4CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)
89921 /*! @} */
89922 
89923 /*! @name AUTHEN_M7CORE - Slice Authentication Register */
89924 /*! @{ */
89925 
89926 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK       (0x1U)
89927 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT      (0U)
89928 /*! DOMAIN_MODE
89929  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
89930  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
89931  */
89932 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)
89933 
89934 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK     (0x2U)
89935 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT    (1U)
89936 /*! SETPOINT_MODE
89937  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
89938  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
89939  */
89940 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)
89941 
89942 #define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK         (0x80U)
89943 #define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT        (7U)
89944 /*! LOCK_MODE - Domain/Setpoint mode lock
89945  */
89946 #define SRC_AUTHEN_M7CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)
89947 
89948 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK       (0xF00U)
89949 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT      (8U)
89950 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)
89951 
89952 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK       (0x8000U)
89953 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT      (15U)
89954 /*! LOCK_ASSIGN - Assign list lock
89955  */
89956 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)
89957 
89958 #define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK        (0xF0000U)
89959 #define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT       (16U)
89960 /*! WHITE_LIST - Domain ID white list
89961  */
89962 #define SRC_AUTHEN_M7CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)
89963 
89964 #define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK         (0x800000U)
89965 #define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT        (23U)
89966 /*! LOCK_LIST - White list lock
89967  */
89968 #define SRC_AUTHEN_M7CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)
89969 
89970 #define SRC_AUTHEN_M7CORE_USER_MASK              (0x1000000U)
89971 #define SRC_AUTHEN_M7CORE_USER_SHIFT             (24U)
89972 /*! USER - Allow user mode access
89973  */
89974 #define SRC_AUTHEN_M7CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)
89975 
89976 #define SRC_AUTHEN_M7CORE_NONSECURE_MASK         (0x2000000U)
89977 #define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT        (25U)
89978 /*! NONSECURE - Allow non-secure mode access
89979  */
89980 #define SRC_AUTHEN_M7CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)
89981 
89982 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK      (0x80000000U)
89983 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT     (31U)
89984 /*! LOCK_SETTING - Lock NONSECURE and USER
89985  */
89986 #define SRC_AUTHEN_M7CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)
89987 /*! @} */
89988 
89989 /*! @name CTRL_M7CORE - Slice Control Register */
89990 /*! @{ */
89991 
89992 #define SRC_CTRL_M7CORE_SW_RESET_MASK            (0x1U)
89993 #define SRC_CTRL_M7CORE_SW_RESET_SHIFT           (0U)
89994 /*! SW_RESET
89995  *  0b0..do not assert slice software reset
89996  *  0b1..assert slice software reset
89997  */
89998 #define SRC_CTRL_M7CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)
89999 /*! @} */
90000 
90001 /*! @name SETPOINT_M7CORE - Slice Setpoint Config Register */
90002 /*! @{ */
90003 
90004 #define SRC_SETPOINT_M7CORE_SETPOINT0_MASK       (0x1U)
90005 #define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT      (0U)
90006 /*! SETPOINT0 - SETPOINT0
90007  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90008  *  0b1..Slice reset will be asserted when system in Setpoint n
90009  */
90010 #define SRC_SETPOINT_M7CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)
90011 
90012 #define SRC_SETPOINT_M7CORE_SETPOINT1_MASK       (0x2U)
90013 #define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT      (1U)
90014 /*! SETPOINT1 - SETPOINT1
90015  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90016  *  0b1..Slice reset will be asserted when system in Setpoint n
90017  */
90018 #define SRC_SETPOINT_M7CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)
90019 
90020 #define SRC_SETPOINT_M7CORE_SETPOINT2_MASK       (0x4U)
90021 #define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT      (2U)
90022 /*! SETPOINT2 - SETPOINT2
90023  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90024  *  0b1..Slice reset will be asserted when system in Setpoint n
90025  */
90026 #define SRC_SETPOINT_M7CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)
90027 
90028 #define SRC_SETPOINT_M7CORE_SETPOINT3_MASK       (0x8U)
90029 #define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT      (3U)
90030 /*! SETPOINT3 - SETPOINT3
90031  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90032  *  0b1..Slice reset will be asserted when system in Setpoint n
90033  */
90034 #define SRC_SETPOINT_M7CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)
90035 
90036 #define SRC_SETPOINT_M7CORE_SETPOINT4_MASK       (0x10U)
90037 #define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT      (4U)
90038 /*! SETPOINT4 - SETPOINT4
90039  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90040  *  0b1..Slice reset will be asserted when system in Setpoint n
90041  */
90042 #define SRC_SETPOINT_M7CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)
90043 
90044 #define SRC_SETPOINT_M7CORE_SETPOINT5_MASK       (0x20U)
90045 #define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT      (5U)
90046 /*! SETPOINT5 - SETPOINT5
90047  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90048  *  0b1..Slice reset will be asserted when system in Setpoint n
90049  */
90050 #define SRC_SETPOINT_M7CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)
90051 
90052 #define SRC_SETPOINT_M7CORE_SETPOINT6_MASK       (0x40U)
90053 #define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT      (6U)
90054 /*! SETPOINT6 - SETPOINT6
90055  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90056  *  0b1..Slice reset will be asserted when system in Setpoint n
90057  */
90058 #define SRC_SETPOINT_M7CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)
90059 
90060 #define SRC_SETPOINT_M7CORE_SETPOINT7_MASK       (0x80U)
90061 #define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT      (7U)
90062 /*! SETPOINT7 - SETPOINT7
90063  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90064  *  0b1..Slice reset will be asserted when system in Setpoint n
90065  */
90066 #define SRC_SETPOINT_M7CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)
90067 
90068 #define SRC_SETPOINT_M7CORE_SETPOINT8_MASK       (0x100U)
90069 #define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT      (8U)
90070 /*! SETPOINT8 - SETPOINT8
90071  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90072  *  0b1..Slice reset will be asserted when system in Setpoint n
90073  */
90074 #define SRC_SETPOINT_M7CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)
90075 
90076 #define SRC_SETPOINT_M7CORE_SETPOINT9_MASK       (0x200U)
90077 #define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT      (9U)
90078 /*! SETPOINT9 - SETPOINT9
90079  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90080  *  0b1..Slice reset will be asserted when system in Setpoint n
90081  */
90082 #define SRC_SETPOINT_M7CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)
90083 
90084 #define SRC_SETPOINT_M7CORE_SETPOINT10_MASK      (0x400U)
90085 #define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT     (10U)
90086 /*! SETPOINT10 - SETPOINT10
90087  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90088  *  0b1..Slice reset will be asserted when system in Setpoint n
90089  */
90090 #define SRC_SETPOINT_M7CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)
90091 
90092 #define SRC_SETPOINT_M7CORE_SETPOINT11_MASK      (0x800U)
90093 #define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT     (11U)
90094 /*! SETPOINT11 - SETPOINT11
90095  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90096  *  0b1..Slice reset will be asserted when system in Setpoint n
90097  */
90098 #define SRC_SETPOINT_M7CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)
90099 
90100 #define SRC_SETPOINT_M7CORE_SETPOINT12_MASK      (0x1000U)
90101 #define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT     (12U)
90102 /*! SETPOINT12 - SETPOINT12
90103  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90104  *  0b1..Slice reset will be asserted when system in Setpoint n
90105  */
90106 #define SRC_SETPOINT_M7CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)
90107 
90108 #define SRC_SETPOINT_M7CORE_SETPOINT13_MASK      (0x2000U)
90109 #define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT     (13U)
90110 /*! SETPOINT13 - SETPOINT13
90111  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90112  *  0b1..Slice reset will be asserted when system in Setpoint n
90113  */
90114 #define SRC_SETPOINT_M7CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)
90115 
90116 #define SRC_SETPOINT_M7CORE_SETPOINT14_MASK      (0x4000U)
90117 #define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT     (14U)
90118 /*! SETPOINT14 - SETPOINT14
90119  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90120  *  0b1..Slice reset will be asserted when system in Setpoint n
90121  */
90122 #define SRC_SETPOINT_M7CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)
90123 
90124 #define SRC_SETPOINT_M7CORE_SETPOINT15_MASK      (0x8000U)
90125 #define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT     (15U)
90126 /*! SETPOINT15 - SETPOINT15
90127  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90128  *  0b1..Slice reset will be asserted when system in Setpoint n
90129  */
90130 #define SRC_SETPOINT_M7CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)
90131 /*! @} */
90132 
90133 /*! @name DOMAIN_M7CORE - Slice Domain Config Register */
90134 /*! @{ */
90135 
90136 #define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK          (0x1U)
90137 #define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT         (0U)
90138 /*! CPU0_RUN - CPU mode setting for RUN
90139  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90140  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90141  */
90142 #define SRC_DOMAIN_M7CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)
90143 
90144 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK         (0x2U)
90145 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT        (1U)
90146 /*! CPU0_WAIT - CPU mode setting for WAIT
90147  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90148  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90149  */
90150 #define SRC_DOMAIN_M7CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)
90151 
90152 #define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK         (0x4U)
90153 #define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT        (2U)
90154 /*! CPU0_STOP - CPU mode setting for STOP
90155  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90156  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90157  */
90158 #define SRC_DOMAIN_M7CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)
90159 
90160 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK         (0x8U)
90161 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT        (3U)
90162 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90163  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90164  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90165  */
90166 #define SRC_DOMAIN_M7CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)
90167 
90168 #define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK          (0x10U)
90169 #define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT         (4U)
90170 /*! CPU1_RUN - CPU mode setting for RUN
90171  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90172  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90173  */
90174 #define SRC_DOMAIN_M7CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)
90175 
90176 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK         (0x20U)
90177 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT        (5U)
90178 /*! CPU1_WAIT - CPU mode setting for WAIT
90179  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90180  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90181  */
90182 #define SRC_DOMAIN_M7CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)
90183 
90184 #define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK         (0x40U)
90185 #define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT        (6U)
90186 /*! CPU1_STOP - CPU mode setting for STOP
90187  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90188  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90189  */
90190 #define SRC_DOMAIN_M7CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)
90191 
90192 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK         (0x80U)
90193 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT        (7U)
90194 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90195  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90196  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90197  */
90198 #define SRC_DOMAIN_M7CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)
90199 /*! @} */
90200 
90201 /*! @name STAT_M7CORE - Slice Status Register */
90202 /*! @{ */
90203 
90204 #define SRC_STAT_M7CORE_UNDER_RST_MASK           (0x1U)
90205 #define SRC_STAT_M7CORE_UNDER_RST_SHIFT          (0U)
90206 /*! UNDER_RST
90207  *  0b0..the reset is finished
90208  *  0b1..the reset is in process
90209  */
90210 #define SRC_STAT_M7CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)
90211 
90212 #define SRC_STAT_M7CORE_RST_BY_HW_MASK           (0x4U)
90213 #define SRC_STAT_M7CORE_RST_BY_HW_SHIFT          (2U)
90214 /*! RST_BY_HW
90215  *  0b0..the reset is not caused by the power mode transfer
90216  *  0b1..the reset is caused by the power mode transfer
90217  */
90218 #define SRC_STAT_M7CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)
90219 
90220 #define SRC_STAT_M7CORE_RST_BY_SW_MASK           (0x8U)
90221 #define SRC_STAT_M7CORE_RST_BY_SW_SHIFT          (3U)
90222 /*! RST_BY_SW
90223  *  0b0..the reset is not caused by software setting
90224  *  0b1..the reset is caused by software setting
90225  */
90226 #define SRC_STAT_M7CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)
90227 /*! @} */
90228 
90229 /*! @name AUTHEN_M4DEBUG - Slice Authentication Register */
90230 /*! @{ */
90231 
90232 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK      (0x1U)
90233 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT     (0U)
90234 /*! DOMAIN_MODE
90235  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90236  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90237  */
90238 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)
90239 
90240 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK    (0x2U)
90241 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT   (1U)
90242 /*! SETPOINT_MODE
90243  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90244  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90245  */
90246 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)
90247 
90248 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK        (0x80U)
90249 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT       (7U)
90250 /*! LOCK_MODE - Domain/Setpoint mode lock
90251  */
90252 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)
90253 
90254 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK      (0xF00U)
90255 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT     (8U)
90256 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)
90257 
90258 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
90259 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT     (15U)
90260 /*! LOCK_ASSIGN - Assign list lock
90261  */
90262 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)
90263 
90264 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK       (0xF0000U)
90265 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT      (16U)
90266 /*! WHITE_LIST - Domain ID white list
90267  */
90268 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)
90269 
90270 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK        (0x800000U)
90271 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT       (23U)
90272 /*! LOCK_LIST - White list lock
90273  */
90274 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)
90275 
90276 #define SRC_AUTHEN_M4DEBUG_USER_MASK             (0x1000000U)
90277 #define SRC_AUTHEN_M4DEBUG_USER_SHIFT            (24U)
90278 /*! USER - Allow user mode access
90279  */
90280 #define SRC_AUTHEN_M4DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)
90281 
90282 #define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK        (0x2000000U)
90283 #define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT       (25U)
90284 /*! NONSECURE - Allow non-secure mode access
90285  */
90286 #define SRC_AUTHEN_M4DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)
90287 
90288 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK     (0x80000000U)
90289 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT    (31U)
90290 /*! LOCK_SETTING - Lock NONSECURE and USER
90291  */
90292 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)
90293 /*! @} */
90294 
90295 /*! @name CTRL_M4DEBUG - Slice Control Register */
90296 /*! @{ */
90297 
90298 #define SRC_CTRL_M4DEBUG_SW_RESET_MASK           (0x1U)
90299 #define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT          (0U)
90300 /*! SW_RESET
90301  *  0b0..do not assert slice software reset
90302  *  0b1..assert slice software reset
90303  */
90304 #define SRC_CTRL_M4DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)
90305 /*! @} */
90306 
90307 /*! @name SETPOINT_M4DEBUG - Slice Setpoint Config Register */
90308 /*! @{ */
90309 
90310 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK      (0x1U)
90311 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT     (0U)
90312 /*! SETPOINT0 - SETPOINT0
90313  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90314  *  0b1..Slice reset will be asserted when system in Setpoint n
90315  */
90316 #define SRC_SETPOINT_M4DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)
90317 
90318 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK      (0x2U)
90319 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT     (1U)
90320 /*! SETPOINT1 - SETPOINT1
90321  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90322  *  0b1..Slice reset will be asserted when system in Setpoint n
90323  */
90324 #define SRC_SETPOINT_M4DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)
90325 
90326 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK      (0x4U)
90327 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT     (2U)
90328 /*! SETPOINT2 - SETPOINT2
90329  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90330  *  0b1..Slice reset will be asserted when system in Setpoint n
90331  */
90332 #define SRC_SETPOINT_M4DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)
90333 
90334 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK      (0x8U)
90335 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT     (3U)
90336 /*! SETPOINT3 - SETPOINT3
90337  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90338  *  0b1..Slice reset will be asserted when system in Setpoint n
90339  */
90340 #define SRC_SETPOINT_M4DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)
90341 
90342 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK      (0x10U)
90343 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT     (4U)
90344 /*! SETPOINT4 - SETPOINT4
90345  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90346  *  0b1..Slice reset will be asserted when system in Setpoint n
90347  */
90348 #define SRC_SETPOINT_M4DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)
90349 
90350 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK      (0x20U)
90351 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT     (5U)
90352 /*! SETPOINT5 - SETPOINT5
90353  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90354  *  0b1..Slice reset will be asserted when system in Setpoint n
90355  */
90356 #define SRC_SETPOINT_M4DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)
90357 
90358 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK      (0x40U)
90359 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT     (6U)
90360 /*! SETPOINT6 - SETPOINT6
90361  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90362  *  0b1..Slice reset will be asserted when system in Setpoint n
90363  */
90364 #define SRC_SETPOINT_M4DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)
90365 
90366 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK      (0x80U)
90367 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT     (7U)
90368 /*! SETPOINT7 - SETPOINT7
90369  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90370  *  0b1..Slice reset will be asserted when system in Setpoint n
90371  */
90372 #define SRC_SETPOINT_M4DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)
90373 
90374 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK      (0x100U)
90375 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT     (8U)
90376 /*! SETPOINT8 - SETPOINT8
90377  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90378  *  0b1..Slice reset will be asserted when system in Setpoint n
90379  */
90380 #define SRC_SETPOINT_M4DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)
90381 
90382 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK      (0x200U)
90383 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT     (9U)
90384 /*! SETPOINT9 - SETPOINT9
90385  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90386  *  0b1..Slice reset will be asserted when system in Setpoint n
90387  */
90388 #define SRC_SETPOINT_M4DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)
90389 
90390 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK     (0x400U)
90391 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT    (10U)
90392 /*! SETPOINT10 - SETPOINT10
90393  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90394  *  0b1..Slice reset will be asserted when system in Setpoint n
90395  */
90396 #define SRC_SETPOINT_M4DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)
90397 
90398 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK     (0x800U)
90399 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT    (11U)
90400 /*! SETPOINT11 - SETPOINT11
90401  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90402  *  0b1..Slice reset will be asserted when system in Setpoint n
90403  */
90404 #define SRC_SETPOINT_M4DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)
90405 
90406 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK     (0x1000U)
90407 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT    (12U)
90408 /*! SETPOINT12 - SETPOINT12
90409  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90410  *  0b1..Slice reset will be asserted when system in Setpoint n
90411  */
90412 #define SRC_SETPOINT_M4DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)
90413 
90414 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK     (0x2000U)
90415 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT    (13U)
90416 /*! SETPOINT13 - SETPOINT13
90417  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90418  *  0b1..Slice reset will be asserted when system in Setpoint n
90419  */
90420 #define SRC_SETPOINT_M4DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)
90421 
90422 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK     (0x4000U)
90423 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT    (14U)
90424 /*! SETPOINT14 - SETPOINT14
90425  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90426  *  0b1..Slice reset will be asserted when system in Setpoint n
90427  */
90428 #define SRC_SETPOINT_M4DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)
90429 
90430 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK     (0x8000U)
90431 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT    (15U)
90432 /*! SETPOINT15 - SETPOINT15
90433  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90434  *  0b1..Slice reset will be asserted when system in Setpoint n
90435  */
90436 #define SRC_SETPOINT_M4DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)
90437 /*! @} */
90438 
90439 /*! @name DOMAIN_M4DEBUG - Slice Domain Config Register */
90440 /*! @{ */
90441 
90442 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK         (0x1U)
90443 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT        (0U)
90444 /*! CPU0_RUN - CPU mode setting for RUN
90445  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90446  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90447  */
90448 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)
90449 
90450 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK        (0x2U)
90451 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT       (1U)
90452 /*! CPU0_WAIT - CPU mode setting for WAIT
90453  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90454  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90455  */
90456 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)
90457 
90458 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK        (0x4U)
90459 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT       (2U)
90460 /*! CPU0_STOP - CPU mode setting for STOP
90461  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90462  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90463  */
90464 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)
90465 
90466 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK        (0x8U)
90467 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT       (3U)
90468 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90469  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90470  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90471  */
90472 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)
90473 
90474 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK         (0x10U)
90475 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT        (4U)
90476 /*! CPU1_RUN - CPU mode setting for RUN
90477  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90478  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90479  */
90480 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)
90481 
90482 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK        (0x20U)
90483 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT       (5U)
90484 /*! CPU1_WAIT - CPU mode setting for WAIT
90485  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90486  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90487  */
90488 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)
90489 
90490 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK        (0x40U)
90491 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT       (6U)
90492 /*! CPU1_STOP - CPU mode setting for STOP
90493  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90494  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90495  */
90496 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)
90497 
90498 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK        (0x80U)
90499 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT       (7U)
90500 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90501  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90502  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90503  */
90504 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)
90505 /*! @} */
90506 
90507 /*! @name STAT_M4DEBUG - Slice Status Register */
90508 /*! @{ */
90509 
90510 #define SRC_STAT_M4DEBUG_UNDER_RST_MASK          (0x1U)
90511 #define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT         (0U)
90512 /*! UNDER_RST
90513  *  0b0..the reset is finished
90514  *  0b1..the reset is in process
90515  */
90516 #define SRC_STAT_M4DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)
90517 
90518 #define SRC_STAT_M4DEBUG_RST_BY_HW_MASK          (0x4U)
90519 #define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT         (2U)
90520 /*! RST_BY_HW
90521  *  0b0..the reset is not caused by the power mode transfer
90522  *  0b1..the reset is caused by the power mode transfer
90523  */
90524 #define SRC_STAT_M4DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)
90525 
90526 #define SRC_STAT_M4DEBUG_RST_BY_SW_MASK          (0x8U)
90527 #define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT         (3U)
90528 /*! RST_BY_SW
90529  *  0b0..the reset is not caused by software setting
90530  *  0b1..the reset is caused by software setting
90531  */
90532 #define SRC_STAT_M4DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)
90533 /*! @} */
90534 
90535 /*! @name AUTHEN_M7DEBUG - Slice Authentication Register */
90536 /*! @{ */
90537 
90538 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK      (0x1U)
90539 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT     (0U)
90540 /*! DOMAIN_MODE
90541  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90542  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90543  */
90544 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)
90545 
90546 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK    (0x2U)
90547 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT   (1U)
90548 /*! SETPOINT_MODE
90549  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90550  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90551  */
90552 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)
90553 
90554 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK        (0x80U)
90555 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT       (7U)
90556 /*! LOCK_MODE - Domain/Setpoint mode lock
90557  */
90558 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)
90559 
90560 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK      (0xF00U)
90561 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT     (8U)
90562 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)
90563 
90564 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
90565 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT     (15U)
90566 /*! LOCK_ASSIGN - Assign list lock
90567  */
90568 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)
90569 
90570 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK       (0xF0000U)
90571 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT      (16U)
90572 /*! WHITE_LIST - Domain ID white list
90573  */
90574 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)
90575 
90576 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK        (0x800000U)
90577 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT       (23U)
90578 /*! LOCK_LIST - White list lock
90579  */
90580 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)
90581 
90582 #define SRC_AUTHEN_M7DEBUG_USER_MASK             (0x1000000U)
90583 #define SRC_AUTHEN_M7DEBUG_USER_SHIFT            (24U)
90584 /*! USER - Allow user mode access
90585  */
90586 #define SRC_AUTHEN_M7DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)
90587 
90588 #define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK        (0x2000000U)
90589 #define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT       (25U)
90590 /*! NONSECURE - Allow non-secure mode access
90591  */
90592 #define SRC_AUTHEN_M7DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)
90593 
90594 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK     (0x80000000U)
90595 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT    (31U)
90596 /*! LOCK_SETTING - Lock NONSECURE and USER
90597  */
90598 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)
90599 /*! @} */
90600 
90601 /*! @name CTRL_M7DEBUG - Slice Control Register */
90602 /*! @{ */
90603 
90604 #define SRC_CTRL_M7DEBUG_SW_RESET_MASK           (0x1U)
90605 #define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT          (0U)
90606 /*! SW_RESET
90607  *  0b0..do not assert slice software reset
90608  *  0b1..assert slice software reset
90609  */
90610 #define SRC_CTRL_M7DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)
90611 /*! @} */
90612 
90613 /*! @name SETPOINT_M7DEBUG - Slice Setpoint Config Register */
90614 /*! @{ */
90615 
90616 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK      (0x1U)
90617 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT     (0U)
90618 /*! SETPOINT0 - SETPOINT0
90619  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90620  *  0b1..Slice reset will be asserted when system in Setpoint n
90621  */
90622 #define SRC_SETPOINT_M7DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)
90623 
90624 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK      (0x2U)
90625 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT     (1U)
90626 /*! SETPOINT1 - SETPOINT1
90627  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90628  *  0b1..Slice reset will be asserted when system in Setpoint n
90629  */
90630 #define SRC_SETPOINT_M7DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)
90631 
90632 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK      (0x4U)
90633 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT     (2U)
90634 /*! SETPOINT2 - SETPOINT2
90635  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90636  *  0b1..Slice reset will be asserted when system in Setpoint n
90637  */
90638 #define SRC_SETPOINT_M7DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)
90639 
90640 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK      (0x8U)
90641 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT     (3U)
90642 /*! SETPOINT3 - SETPOINT3
90643  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90644  *  0b1..Slice reset will be asserted when system in Setpoint n
90645  */
90646 #define SRC_SETPOINT_M7DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)
90647 
90648 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK      (0x10U)
90649 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT     (4U)
90650 /*! SETPOINT4 - SETPOINT4
90651  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90652  *  0b1..Slice reset will be asserted when system in Setpoint n
90653  */
90654 #define SRC_SETPOINT_M7DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)
90655 
90656 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK      (0x20U)
90657 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT     (5U)
90658 /*! SETPOINT5 - SETPOINT5
90659  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90660  *  0b1..Slice reset will be asserted when system in Setpoint n
90661  */
90662 #define SRC_SETPOINT_M7DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)
90663 
90664 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK      (0x40U)
90665 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT     (6U)
90666 /*! SETPOINT6 - SETPOINT6
90667  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90668  *  0b1..Slice reset will be asserted when system in Setpoint n
90669  */
90670 #define SRC_SETPOINT_M7DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)
90671 
90672 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK      (0x80U)
90673 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT     (7U)
90674 /*! SETPOINT7 - SETPOINT7
90675  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90676  *  0b1..Slice reset will be asserted when system in Setpoint n
90677  */
90678 #define SRC_SETPOINT_M7DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)
90679 
90680 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK      (0x100U)
90681 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT     (8U)
90682 /*! SETPOINT8 - SETPOINT8
90683  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90684  *  0b1..Slice reset will be asserted when system in Setpoint n
90685  */
90686 #define SRC_SETPOINT_M7DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)
90687 
90688 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK      (0x200U)
90689 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT     (9U)
90690 /*! SETPOINT9 - SETPOINT9
90691  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90692  *  0b1..Slice reset will be asserted when system in Setpoint n
90693  */
90694 #define SRC_SETPOINT_M7DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)
90695 
90696 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK     (0x400U)
90697 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT    (10U)
90698 /*! SETPOINT10 - SETPOINT10
90699  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90700  *  0b1..Slice reset will be asserted when system in Setpoint n
90701  */
90702 #define SRC_SETPOINT_M7DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)
90703 
90704 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK     (0x800U)
90705 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT    (11U)
90706 /*! SETPOINT11 - SETPOINT11
90707  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90708  *  0b1..Slice reset will be asserted when system in Setpoint n
90709  */
90710 #define SRC_SETPOINT_M7DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)
90711 
90712 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK     (0x1000U)
90713 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT    (12U)
90714 /*! SETPOINT12 - SETPOINT12
90715  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90716  *  0b1..Slice reset will be asserted when system in Setpoint n
90717  */
90718 #define SRC_SETPOINT_M7DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)
90719 
90720 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK     (0x2000U)
90721 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT    (13U)
90722 /*! SETPOINT13 - SETPOINT13
90723  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90724  *  0b1..Slice reset will be asserted when system in Setpoint n
90725  */
90726 #define SRC_SETPOINT_M7DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)
90727 
90728 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK     (0x4000U)
90729 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT    (14U)
90730 /*! SETPOINT14 - SETPOINT14
90731  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90732  *  0b1..Slice reset will be asserted when system in Setpoint n
90733  */
90734 #define SRC_SETPOINT_M7DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)
90735 
90736 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK     (0x8000U)
90737 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT    (15U)
90738 /*! SETPOINT15 - SETPOINT15
90739  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90740  *  0b1..Slice reset will be asserted when system in Setpoint n
90741  */
90742 #define SRC_SETPOINT_M7DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)
90743 /*! @} */
90744 
90745 /*! @name DOMAIN_M7DEBUG - Slice Domain Config Register */
90746 /*! @{ */
90747 
90748 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK         (0x1U)
90749 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT        (0U)
90750 /*! CPU0_RUN - CPU mode setting for RUN
90751  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
90752  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
90753  */
90754 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)
90755 
90756 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK        (0x2U)
90757 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT       (1U)
90758 /*! CPU0_WAIT - CPU mode setting for WAIT
90759  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
90760  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
90761  */
90762 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)
90763 
90764 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK        (0x4U)
90765 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT       (2U)
90766 /*! CPU0_STOP - CPU mode setting for STOP
90767  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
90768  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
90769  */
90770 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)
90771 
90772 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK        (0x8U)
90773 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT       (3U)
90774 /*! CPU0_SUSP - CPU mode setting for SUSPEND
90775  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
90776  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
90777  */
90778 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)
90779 
90780 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK         (0x10U)
90781 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT        (4U)
90782 /*! CPU1_RUN - CPU mode setting for RUN
90783  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
90784  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
90785  */
90786 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)
90787 
90788 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK        (0x20U)
90789 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT       (5U)
90790 /*! CPU1_WAIT - CPU mode setting for WAIT
90791  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
90792  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
90793  */
90794 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)
90795 
90796 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK        (0x40U)
90797 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT       (6U)
90798 /*! CPU1_STOP - CPU mode setting for STOP
90799  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
90800  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
90801  */
90802 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)
90803 
90804 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK        (0x80U)
90805 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT       (7U)
90806 /*! CPU1_SUSP - CPU mode setting for SUSPEND
90807  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
90808  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
90809  */
90810 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)
90811 /*! @} */
90812 
90813 /*! @name STAT_M7DEBUG - Slice Status Register */
90814 /*! @{ */
90815 
90816 #define SRC_STAT_M7DEBUG_UNDER_RST_MASK          (0x1U)
90817 #define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT         (0U)
90818 /*! UNDER_RST
90819  *  0b0..the reset is finished
90820  *  0b1..the reset is in process
90821  */
90822 #define SRC_STAT_M7DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)
90823 
90824 #define SRC_STAT_M7DEBUG_RST_BY_HW_MASK          (0x4U)
90825 #define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT         (2U)
90826 /*! RST_BY_HW
90827  *  0b0..the reset is not caused by the power mode transfer
90828  *  0b1..the reset is caused by the power mode transfer
90829  */
90830 #define SRC_STAT_M7DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)
90831 
90832 #define SRC_STAT_M7DEBUG_RST_BY_SW_MASK          (0x8U)
90833 #define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT         (3U)
90834 /*! RST_BY_SW
90835  *  0b0..the reset is not caused by software setting
90836  *  0b1..the reset is caused by software setting
90837  */
90838 #define SRC_STAT_M7DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)
90839 /*! @} */
90840 
90841 /*! @name AUTHEN_USBPHY1 - Slice Authentication Register */
90842 /*! @{ */
90843 
90844 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK      (0x1U)
90845 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT     (0U)
90846 /*! DOMAIN_MODE
90847  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
90848  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
90849  */
90850 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)
90851 
90852 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK    (0x2U)
90853 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT   (1U)
90854 /*! SETPOINT_MODE
90855  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
90856  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
90857  */
90858 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)
90859 
90860 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK        (0x80U)
90861 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT       (7U)
90862 /*! LOCK_MODE - Domain/Setpoint mode lock
90863  */
90864 #define SRC_AUTHEN_USBPHY1_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)
90865 
90866 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK      (0xF00U)
90867 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT     (8U)
90868 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)
90869 
90870 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK      (0x8000U)
90871 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT     (15U)
90872 /*! LOCK_ASSIGN - Assign list lock
90873  */
90874 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)
90875 
90876 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK       (0xF0000U)
90877 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT      (16U)
90878 /*! WHITE_LIST - Domain ID white list
90879  */
90880 #define SRC_AUTHEN_USBPHY1_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)
90881 
90882 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK        (0x800000U)
90883 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT       (23U)
90884 /*! LOCK_LIST - White list lock
90885  */
90886 #define SRC_AUTHEN_USBPHY1_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)
90887 
90888 #define SRC_AUTHEN_USBPHY1_USER_MASK             (0x1000000U)
90889 #define SRC_AUTHEN_USBPHY1_USER_SHIFT            (24U)
90890 /*! USER - Allow user mode access
90891  */
90892 #define SRC_AUTHEN_USBPHY1_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)
90893 
90894 #define SRC_AUTHEN_USBPHY1_NONSECURE_MASK        (0x2000000U)
90895 #define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT       (25U)
90896 /*! NONSECURE - Allow non-secure mode access
90897  */
90898 #define SRC_AUTHEN_USBPHY1_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)
90899 
90900 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK     (0x80000000U)
90901 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT    (31U)
90902 /*! LOCK_SETTING - Lock NONSECURE and USER
90903  */
90904 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)
90905 /*! @} */
90906 
90907 /*! @name CTRL_USBPHY1 - Slice Control Register */
90908 /*! @{ */
90909 
90910 #define SRC_CTRL_USBPHY1_SW_RESET_MASK           (0x1U)
90911 #define SRC_CTRL_USBPHY1_SW_RESET_SHIFT          (0U)
90912 /*! SW_RESET
90913  *  0b0..do not assert slice software reset
90914  *  0b1..assert slice software reset
90915  */
90916 #define SRC_CTRL_USBPHY1_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)
90917 /*! @} */
90918 
90919 /*! @name SETPOINT_USBPHY1 - Slice Setpoint Config Register */
90920 /*! @{ */
90921 
90922 #define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK      (0x1U)
90923 #define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT     (0U)
90924 /*! SETPOINT0 - SETPOINT0
90925  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90926  *  0b1..Slice reset will be asserted when system in Setpoint n
90927  */
90928 #define SRC_SETPOINT_USBPHY1_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)
90929 
90930 #define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK      (0x2U)
90931 #define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT     (1U)
90932 /*! SETPOINT1 - SETPOINT1
90933  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90934  *  0b1..Slice reset will be asserted when system in Setpoint n
90935  */
90936 #define SRC_SETPOINT_USBPHY1_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)
90937 
90938 #define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK      (0x4U)
90939 #define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT     (2U)
90940 /*! SETPOINT2 - SETPOINT2
90941  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90942  *  0b1..Slice reset will be asserted when system in Setpoint n
90943  */
90944 #define SRC_SETPOINT_USBPHY1_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)
90945 
90946 #define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK      (0x8U)
90947 #define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT     (3U)
90948 /*! SETPOINT3 - SETPOINT3
90949  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90950  *  0b1..Slice reset will be asserted when system in Setpoint n
90951  */
90952 #define SRC_SETPOINT_USBPHY1_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)
90953 
90954 #define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK      (0x10U)
90955 #define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT     (4U)
90956 /*! SETPOINT4 - SETPOINT4
90957  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90958  *  0b1..Slice reset will be asserted when system in Setpoint n
90959  */
90960 #define SRC_SETPOINT_USBPHY1_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)
90961 
90962 #define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK      (0x20U)
90963 #define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT     (5U)
90964 /*! SETPOINT5 - SETPOINT5
90965  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90966  *  0b1..Slice reset will be asserted when system in Setpoint n
90967  */
90968 #define SRC_SETPOINT_USBPHY1_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)
90969 
90970 #define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK      (0x40U)
90971 #define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT     (6U)
90972 /*! SETPOINT6 - SETPOINT6
90973  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90974  *  0b1..Slice reset will be asserted when system in Setpoint n
90975  */
90976 #define SRC_SETPOINT_USBPHY1_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)
90977 
90978 #define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK      (0x80U)
90979 #define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT     (7U)
90980 /*! SETPOINT7 - SETPOINT7
90981  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90982  *  0b1..Slice reset will be asserted when system in Setpoint n
90983  */
90984 #define SRC_SETPOINT_USBPHY1_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)
90985 
90986 #define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK      (0x100U)
90987 #define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT     (8U)
90988 /*! SETPOINT8 - SETPOINT8
90989  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90990  *  0b1..Slice reset will be asserted when system in Setpoint n
90991  */
90992 #define SRC_SETPOINT_USBPHY1_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)
90993 
90994 #define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK      (0x200U)
90995 #define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT     (9U)
90996 /*! SETPOINT9 - SETPOINT9
90997  *  0b0..Slice reset will be de-asserted when system in Setpoint n
90998  *  0b1..Slice reset will be asserted when system in Setpoint n
90999  */
91000 #define SRC_SETPOINT_USBPHY1_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)
91001 
91002 #define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK     (0x400U)
91003 #define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT    (10U)
91004 /*! SETPOINT10 - SETPOINT10
91005  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91006  *  0b1..Slice reset will be asserted when system in Setpoint n
91007  */
91008 #define SRC_SETPOINT_USBPHY1_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)
91009 
91010 #define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK     (0x800U)
91011 #define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT    (11U)
91012 /*! SETPOINT11 - SETPOINT11
91013  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91014  *  0b1..Slice reset will be asserted when system in Setpoint n
91015  */
91016 #define SRC_SETPOINT_USBPHY1_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)
91017 
91018 #define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK     (0x1000U)
91019 #define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT    (12U)
91020 /*! SETPOINT12 - SETPOINT12
91021  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91022  *  0b1..Slice reset will be asserted when system in Setpoint n
91023  */
91024 #define SRC_SETPOINT_USBPHY1_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)
91025 
91026 #define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK     (0x2000U)
91027 #define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT    (13U)
91028 /*! SETPOINT13 - SETPOINT13
91029  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91030  *  0b1..Slice reset will be asserted when system in Setpoint n
91031  */
91032 #define SRC_SETPOINT_USBPHY1_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)
91033 
91034 #define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK     (0x4000U)
91035 #define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT    (14U)
91036 /*! SETPOINT14 - SETPOINT14
91037  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91038  *  0b1..Slice reset will be asserted when system in Setpoint n
91039  */
91040 #define SRC_SETPOINT_USBPHY1_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)
91041 
91042 #define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK     (0x8000U)
91043 #define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT    (15U)
91044 /*! SETPOINT15 - SETPOINT15
91045  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91046  *  0b1..Slice reset will be asserted when system in Setpoint n
91047  */
91048 #define SRC_SETPOINT_USBPHY1_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)
91049 /*! @} */
91050 
91051 /*! @name DOMAIN_USBPHY1 - Slice Domain Config Register */
91052 /*! @{ */
91053 
91054 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK         (0x1U)
91055 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT        (0U)
91056 /*! CPU0_RUN - CPU mode setting for RUN
91057  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
91058  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
91059  */
91060 #define SRC_DOMAIN_USBPHY1_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)
91061 
91062 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK        (0x2U)
91063 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT       (1U)
91064 /*! CPU0_WAIT - CPU mode setting for WAIT
91065  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
91066  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
91067  */
91068 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)
91069 
91070 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK        (0x4U)
91071 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT       (2U)
91072 /*! CPU0_STOP - CPU mode setting for STOP
91073  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
91074  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
91075  */
91076 #define SRC_DOMAIN_USBPHY1_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)
91077 
91078 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK        (0x8U)
91079 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT       (3U)
91080 /*! CPU0_SUSP - CPU mode setting for SUSPEND
91081  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
91082  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
91083  */
91084 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)
91085 
91086 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK         (0x10U)
91087 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT        (4U)
91088 /*! CPU1_RUN - CPU mode setting for RUN
91089  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
91090  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
91091  */
91092 #define SRC_DOMAIN_USBPHY1_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)
91093 
91094 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK        (0x20U)
91095 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT       (5U)
91096 /*! CPU1_WAIT - CPU mode setting for WAIT
91097  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
91098  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
91099  */
91100 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)
91101 
91102 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK        (0x40U)
91103 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT       (6U)
91104 /*! CPU1_STOP - CPU mode setting for STOP
91105  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
91106  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
91107  */
91108 #define SRC_DOMAIN_USBPHY1_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)
91109 
91110 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK        (0x80U)
91111 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT       (7U)
91112 /*! CPU1_SUSP - CPU mode setting for SUSPEND
91113  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
91114  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
91115  */
91116 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)
91117 /*! @} */
91118 
91119 /*! @name STAT_USBPHY1 - Slice Status Register */
91120 /*! @{ */
91121 
91122 #define SRC_STAT_USBPHY1_UNDER_RST_MASK          (0x1U)
91123 #define SRC_STAT_USBPHY1_UNDER_RST_SHIFT         (0U)
91124 /*! UNDER_RST
91125  *  0b0..the reset is finished
91126  *  0b1..the reset is in process
91127  */
91128 #define SRC_STAT_USBPHY1_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)
91129 
91130 #define SRC_STAT_USBPHY1_RST_BY_HW_MASK          (0x4U)
91131 #define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT         (2U)
91132 /*! RST_BY_HW
91133  *  0b0..the reset is not caused by the power mode transfer
91134  *  0b1..the reset is caused by the power mode transfer
91135  */
91136 #define SRC_STAT_USBPHY1_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)
91137 
91138 #define SRC_STAT_USBPHY1_RST_BY_SW_MASK          (0x8U)
91139 #define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT         (3U)
91140 /*! RST_BY_SW
91141  *  0b0..the reset is not caused by software setting
91142  *  0b1..the reset is caused by software setting
91143  */
91144 #define SRC_STAT_USBPHY1_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)
91145 /*! @} */
91146 
91147 /*! @name AUTHEN_USBPHY2 - Slice Authentication Register */
91148 /*! @{ */
91149 
91150 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK      (0x1U)
91151 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT     (0U)
91152 /*! DOMAIN_MODE
91153  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
91154  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
91155  */
91156 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)
91157 
91158 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK    (0x2U)
91159 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT   (1U)
91160 /*! SETPOINT_MODE
91161  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
91162  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
91163  */
91164 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)
91165 
91166 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK        (0x80U)
91167 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT       (7U)
91168 /*! LOCK_MODE - Domain/Setpoint mode lock
91169  */
91170 #define SRC_AUTHEN_USBPHY2_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)
91171 
91172 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK      (0xF00U)
91173 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT     (8U)
91174 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)
91175 
91176 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK      (0x8000U)
91177 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT     (15U)
91178 /*! LOCK_ASSIGN - Assign list lock
91179  */
91180 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)
91181 
91182 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK       (0xF0000U)
91183 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT      (16U)
91184 /*! WHITE_LIST - Domain ID white list
91185  */
91186 #define SRC_AUTHEN_USBPHY2_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)
91187 
91188 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK        (0x800000U)
91189 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT       (23U)
91190 /*! LOCK_LIST - White list lock
91191  */
91192 #define SRC_AUTHEN_USBPHY2_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)
91193 
91194 #define SRC_AUTHEN_USBPHY2_USER_MASK             (0x1000000U)
91195 #define SRC_AUTHEN_USBPHY2_USER_SHIFT            (24U)
91196 /*! USER - Allow user mode access
91197  */
91198 #define SRC_AUTHEN_USBPHY2_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)
91199 
91200 #define SRC_AUTHEN_USBPHY2_NONSECURE_MASK        (0x2000000U)
91201 #define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT       (25U)
91202 /*! NONSECURE - Allow non-secure mode access
91203  */
91204 #define SRC_AUTHEN_USBPHY2_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)
91205 
91206 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK     (0x80000000U)
91207 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT    (31U)
91208 /*! LOCK_SETTING - Lock NONSECURE and USER
91209  */
91210 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)
91211 /*! @} */
91212 
91213 /*! @name CTRL_USBPHY2 - Slice Control Register */
91214 /*! @{ */
91215 
91216 #define SRC_CTRL_USBPHY2_SW_RESET_MASK           (0x1U)
91217 #define SRC_CTRL_USBPHY2_SW_RESET_SHIFT          (0U)
91218 /*! SW_RESET
91219  *  0b0..do not assert slice software reset
91220  *  0b1..assert slice software reset
91221  */
91222 #define SRC_CTRL_USBPHY2_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)
91223 /*! @} */
91224 
91225 /*! @name SETPOINT_USBPHY2 - Slice Setpoint Config Register */
91226 /*! @{ */
91227 
91228 #define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK      (0x1U)
91229 #define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT     (0U)
91230 /*! SETPOINT0 - SETPOINT0
91231  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91232  *  0b1..Slice reset will be asserted when system in Setpoint n
91233  */
91234 #define SRC_SETPOINT_USBPHY2_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)
91235 
91236 #define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK      (0x2U)
91237 #define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT     (1U)
91238 /*! SETPOINT1 - SETPOINT1
91239  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91240  *  0b1..Slice reset will be asserted when system in Setpoint n
91241  */
91242 #define SRC_SETPOINT_USBPHY2_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)
91243 
91244 #define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK      (0x4U)
91245 #define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT     (2U)
91246 /*! SETPOINT2 - SETPOINT2
91247  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91248  *  0b1..Slice reset will be asserted when system in Setpoint n
91249  */
91250 #define SRC_SETPOINT_USBPHY2_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)
91251 
91252 #define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK      (0x8U)
91253 #define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT     (3U)
91254 /*! SETPOINT3 - SETPOINT3
91255  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91256  *  0b1..Slice reset will be asserted when system in Setpoint n
91257  */
91258 #define SRC_SETPOINT_USBPHY2_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)
91259 
91260 #define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK      (0x10U)
91261 #define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT     (4U)
91262 /*! SETPOINT4 - SETPOINT4
91263  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91264  *  0b1..Slice reset will be asserted when system in Setpoint n
91265  */
91266 #define SRC_SETPOINT_USBPHY2_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)
91267 
91268 #define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK      (0x20U)
91269 #define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT     (5U)
91270 /*! SETPOINT5 - SETPOINT5
91271  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91272  *  0b1..Slice reset will be asserted when system in Setpoint n
91273  */
91274 #define SRC_SETPOINT_USBPHY2_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)
91275 
91276 #define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK      (0x40U)
91277 #define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT     (6U)
91278 /*! SETPOINT6 - SETPOINT6
91279  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91280  *  0b1..Slice reset will be asserted when system in Setpoint n
91281  */
91282 #define SRC_SETPOINT_USBPHY2_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)
91283 
91284 #define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK      (0x80U)
91285 #define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT     (7U)
91286 /*! SETPOINT7 - SETPOINT7
91287  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91288  *  0b1..Slice reset will be asserted when system in Setpoint n
91289  */
91290 #define SRC_SETPOINT_USBPHY2_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)
91291 
91292 #define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK      (0x100U)
91293 #define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT     (8U)
91294 /*! SETPOINT8 - SETPOINT8
91295  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91296  *  0b1..Slice reset will be asserted when system in Setpoint n
91297  */
91298 #define SRC_SETPOINT_USBPHY2_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)
91299 
91300 #define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK      (0x200U)
91301 #define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT     (9U)
91302 /*! SETPOINT9 - SETPOINT9
91303  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91304  *  0b1..Slice reset will be asserted when system in Setpoint n
91305  */
91306 #define SRC_SETPOINT_USBPHY2_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)
91307 
91308 #define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK     (0x400U)
91309 #define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT    (10U)
91310 /*! SETPOINT10 - SETPOINT10
91311  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91312  *  0b1..Slice reset will be asserted when system in Setpoint n
91313  */
91314 #define SRC_SETPOINT_USBPHY2_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)
91315 
91316 #define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK     (0x800U)
91317 #define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT    (11U)
91318 /*! SETPOINT11 - SETPOINT11
91319  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91320  *  0b1..Slice reset will be asserted when system in Setpoint n
91321  */
91322 #define SRC_SETPOINT_USBPHY2_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)
91323 
91324 #define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK     (0x1000U)
91325 #define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT    (12U)
91326 /*! SETPOINT12 - SETPOINT12
91327  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91328  *  0b1..Slice reset will be asserted when system in Setpoint n
91329  */
91330 #define SRC_SETPOINT_USBPHY2_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)
91331 
91332 #define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK     (0x2000U)
91333 #define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT    (13U)
91334 /*! SETPOINT13 - SETPOINT13
91335  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91336  *  0b1..Slice reset will be asserted when system in Setpoint n
91337  */
91338 #define SRC_SETPOINT_USBPHY2_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)
91339 
91340 #define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK     (0x4000U)
91341 #define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT    (14U)
91342 /*! SETPOINT14 - SETPOINT14
91343  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91344  *  0b1..Slice reset will be asserted when system in Setpoint n
91345  */
91346 #define SRC_SETPOINT_USBPHY2_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)
91347 
91348 #define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK     (0x8000U)
91349 #define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT    (15U)
91350 /*! SETPOINT15 - SETPOINT15
91351  *  0b0..Slice reset will be de-asserted when system in Setpoint n
91352  *  0b1..Slice reset will be asserted when system in Setpoint n
91353  */
91354 #define SRC_SETPOINT_USBPHY2_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)
91355 /*! @} */
91356 
91357 /*! @name DOMAIN_USBPHY2 - Slice Domain Config Register */
91358 /*! @{ */
91359 
91360 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK         (0x1U)
91361 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT        (0U)
91362 /*! CPU0_RUN - CPU mode setting for RUN
91363  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
91364  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
91365  */
91366 #define SRC_DOMAIN_USBPHY2_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)
91367 
91368 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK        (0x2U)
91369 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT       (1U)
91370 /*! CPU0_WAIT - CPU mode setting for WAIT
91371  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
91372  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
91373  */
91374 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)
91375 
91376 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK        (0x4U)
91377 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT       (2U)
91378 /*! CPU0_STOP - CPU mode setting for STOP
91379  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
91380  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
91381  */
91382 #define SRC_DOMAIN_USBPHY2_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)
91383 
91384 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK        (0x8U)
91385 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT       (3U)
91386 /*! CPU0_SUSP - CPU mode setting for SUSPEND
91387  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
91388  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
91389  */
91390 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)
91391 
91392 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK         (0x10U)
91393 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT        (4U)
91394 /*! CPU1_RUN - CPU mode setting for RUN
91395  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
91396  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
91397  */
91398 #define SRC_DOMAIN_USBPHY2_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)
91399 
91400 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK        (0x20U)
91401 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT       (5U)
91402 /*! CPU1_WAIT - CPU mode setting for WAIT
91403  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
91404  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
91405  */
91406 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)
91407 
91408 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK        (0x40U)
91409 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT       (6U)
91410 /*! CPU1_STOP - CPU mode setting for STOP
91411  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
91412  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
91413  */
91414 #define SRC_DOMAIN_USBPHY2_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)
91415 
91416 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK        (0x80U)
91417 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT       (7U)
91418 /*! CPU1_SUSP - CPU mode setting for SUSPEND
91419  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
91420  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
91421  */
91422 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)
91423 /*! @} */
91424 
91425 /*! @name STAT_USBPHY2 - Slice Status Register */
91426 /*! @{ */
91427 
91428 #define SRC_STAT_USBPHY2_UNDER_RST_MASK          (0x1U)
91429 #define SRC_STAT_USBPHY2_UNDER_RST_SHIFT         (0U)
91430 /*! UNDER_RST
91431  *  0b0..the reset is finished
91432  *  0b1..the reset is in process
91433  */
91434 #define SRC_STAT_USBPHY2_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)
91435 
91436 #define SRC_STAT_USBPHY2_RST_BY_HW_MASK          (0x4U)
91437 #define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT         (2U)
91438 /*! RST_BY_HW
91439  *  0b0..the reset is not caused by the power mode transfer
91440  *  0b1..the reset is caused by the power mode transfer
91441  */
91442 #define SRC_STAT_USBPHY2_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)
91443 
91444 #define SRC_STAT_USBPHY2_RST_BY_SW_MASK          (0x8U)
91445 #define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT         (3U)
91446 /*! RST_BY_SW
91447  *  0b0..the reset is not caused by software setting
91448  *  0b1..the reset is caused by software setting
91449  */
91450 #define SRC_STAT_USBPHY2_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)
91451 /*! @} */
91452 
91453 
91454 /*!
91455  * @}
91456  */ /* end of group SRC_Register_Masks */
91457 
91458 
91459 /* SRC - Peripheral instance base addresses */
91460 /** Peripheral SRC base address */
91461 #define SRC_BASE                                 (0x40C04000u)
91462 /** Peripheral SRC base pointer */
91463 #define SRC                                      ((SRC_Type *)SRC_BASE)
91464 /** Array initializer of SRC peripheral base addresses */
91465 #define SRC_BASE_ADDRS                           { SRC_BASE }
91466 /** Array initializer of SRC peripheral base pointers */
91467 #define SRC_BASE_PTRS                            { SRC }
91468 
91469 /*!
91470  * @}
91471  */ /* end of group SRC_Peripheral_Access_Layer */
91472 
91473 
91474 /* ----------------------------------------------------------------------------
91475    -- SSARC_HP Peripheral Access Layer
91476    ---------------------------------------------------------------------------- */
91477 
91478 /*!
91479  * @addtogroup SSARC_HP_Peripheral_Access_Layer SSARC_HP Peripheral Access Layer
91480  * @{
91481  */
91482 
91483 /** SSARC_HP - Register Layout Typedef */
91484 typedef struct {
91485   struct {                                         /* offset: 0x0, array step: 0x10 */
91486     __IO uint32_t SRAM0;                             /**< Description Address Register, array offset: 0x0, array step: 0x10 */
91487     __IO uint32_t SRAM1;                             /**< Description Data Register, array offset: 0x4, array step: 0x10 */
91488     __IO uint32_t SRAM2;                             /**< Description Control Register, array offset: 0x8, array step: 0x10 */
91489          uint8_t RESERVED_0[4];
91490   } DESC[1024];
91491 } SSARC_HP_Type;
91492 
91493 /* ----------------------------------------------------------------------------
91494    -- SSARC_HP Register Masks
91495    ---------------------------------------------------------------------------- */
91496 
91497 /*!
91498  * @addtogroup SSARC_HP_Register_Masks SSARC_HP Register Masks
91499  * @{
91500  */
91501 
91502 /*! @name SRAM0 - Description Address Register */
91503 /*! @{ */
91504 
91505 #define SSARC_HP_SRAM0_ADDR_MASK                 (0xFFFFFFFFU)
91506 #define SSARC_HP_SRAM0_ADDR_SHIFT                (0U)
91507 /*! ADDR - Address field
91508  */
91509 #define SSARC_HP_SRAM0_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK)
91510 /*! @} */
91511 
91512 /* The count of SSARC_HP_SRAM0 */
91513 #define SSARC_HP_SRAM0_COUNT                     (1024U)
91514 
91515 /*! @name SRAM1 - Description Data Register */
91516 /*! @{ */
91517 
91518 #define SSARC_HP_SRAM1_DATA_MASK                 (0xFFFFFFFFU)
91519 #define SSARC_HP_SRAM1_DATA_SHIFT                (0U)
91520 /*! DATA - Data field
91521  */
91522 #define SSARC_HP_SRAM1_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK)
91523 /*! @} */
91524 
91525 /* The count of SSARC_HP_SRAM1 */
91526 #define SSARC_HP_SRAM1_COUNT                     (1024U)
91527 
91528 /*! @name SRAM2 - Description Control Register */
91529 /*! @{ */
91530 
91531 #define SSARC_HP_SRAM2_TYPE_MASK                 (0x7U)
91532 #define SSARC_HP_SRAM2_TYPE_SHIFT                (0U)
91533 /*! TYPE - Type field
91534  *  0b000..SR
91535  *  0b001..WO
91536  *  0b010..RMW_OR
91537  *  0b011..RMW_AND
91538  *  0b100..DELAY
91539  *  0b101..POLLING_0
91540  *  0b110..POLLING_1
91541  *  0b111..Reserved
91542  */
91543 #define SSARC_HP_SRAM2_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK)
91544 
91545 #define SSARC_HP_SRAM2_SV_EN_MASK                (0x10U)
91546 #define SSARC_HP_SRAM2_SV_EN_SHIFT               (4U)
91547 /*! SV_EN - Save Enable
91548  *  0b0..Do not use this descriptor in the save operation
91549  *  0b1..Use this descriptor in the save operation
91550  */
91551 #define SSARC_HP_SRAM2_SV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK)
91552 
91553 #define SSARC_HP_SRAM2_RT_EN_MASK                (0x20U)
91554 #define SSARC_HP_SRAM2_RT_EN_SHIFT               (5U)
91555 /*! RT_EN - Restore Enable
91556  *  0b0..Do not use this descriptor for the restore operation
91557  *  0b1..Use this descriptor for the restore operation
91558  */
91559 #define SSARC_HP_SRAM2_RT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK)
91560 
91561 #define SSARC_HP_SRAM2_SIZE_MASK                 (0xC0U)
91562 #define SSARC_HP_SRAM2_SIZE_SHIFT                (6U)
91563 /*! SIZE - Size field
91564  *  0b00..8-bit
91565  *  0b01..16-bit
91566  *  0b10..32-bit
91567  *  0b11..Reserved
91568  */
91569 #define SSARC_HP_SRAM2_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK)
91570 /*! @} */
91571 
91572 /* The count of SSARC_HP_SRAM2 */
91573 #define SSARC_HP_SRAM2_COUNT                     (1024U)
91574 
91575 
91576 /*!
91577  * @}
91578  */ /* end of group SSARC_HP_Register_Masks */
91579 
91580 
91581 /* SSARC_HP - Peripheral instance base addresses */
91582 /** Peripheral SSARC_HP base address */
91583 #define SSARC_HP_BASE                            (0x40CB4000u)
91584 /** Peripheral SSARC_HP base pointer */
91585 #define SSARC_HP                                 ((SSARC_HP_Type *)SSARC_HP_BASE)
91586 /** Array initializer of SSARC_HP peripheral base addresses */
91587 #define SSARC_HP_BASE_ADDRS                      { SSARC_HP_BASE }
91588 /** Array initializer of SSARC_HP peripheral base pointers */
91589 #define SSARC_HP_BASE_PTRS                       { SSARC_HP }
91590 
91591 /*!
91592  * @}
91593  */ /* end of group SSARC_HP_Peripheral_Access_Layer */
91594 
91595 
91596 /* ----------------------------------------------------------------------------
91597    -- SSARC_LP Peripheral Access Layer
91598    ---------------------------------------------------------------------------- */
91599 
91600 /*!
91601  * @addtogroup SSARC_LP_Peripheral_Access_Layer SSARC_LP Peripheral Access Layer
91602  * @{
91603  */
91604 
91605 /** SSARC_LP - Register Layout Typedef */
91606 typedef struct {
91607   struct {                                         /* offset: 0x0, array step: 0x20 */
91608     __IO uint32_t DESC_CTRL0;                        /**< Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20 */
91609     __IO uint32_t DESC_CTRL1;                        /**< Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20 */
91610     __IO uint32_t DESC_ADDR_UP;                      /**< Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20 */
91611     __IO uint32_t DESC_ADDR_DOWN;                    /**< Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20 */
91612          uint8_t RESERVED_0[16];
91613   } GROUPS[16];
91614   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x200 */
91615   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x204 */
91616        uint8_t RESERVED_0[4];
91617   __IO uint32_t HP_TIMEOUT;                        /**< HP Timeout Register, offset: 0x20C */
91618        uint8_t RESERVED_1[12];
91619   __I  uint32_t HW_GROUP_PENDING;                  /**< Hardware Request Pending Register, offset: 0x21C */
91620   __I  uint32_t SW_GROUP_PENDING;                  /**< Software Request Pending Register, offset: 0x220 */
91621 } SSARC_LP_Type;
91622 
91623 /* ----------------------------------------------------------------------------
91624    -- SSARC_LP Register Masks
91625    ---------------------------------------------------------------------------- */
91626 
91627 /*!
91628  * @addtogroup SSARC_LP_Register_Masks SSARC_LP Register Masks
91629  * @{
91630  */
91631 
91632 /*! @name DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register */
91633 /*! @{ */
91634 
91635 #define SSARC_LP_DESC_CTRL0_START_MASK           (0x3FFU)
91636 #define SSARC_LP_DESC_CTRL0_START_SHIFT          (0U)
91637 /*! START - Start index
91638  */
91639 #define SSARC_LP_DESC_CTRL0_START(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK)
91640 
91641 #define SSARC_LP_DESC_CTRL0_END_MASK             (0xFFC00U)
91642 #define SSARC_LP_DESC_CTRL0_END_SHIFT            (10U)
91643 /*! END - End index
91644  */
91645 #define SSARC_LP_DESC_CTRL0_END(x)               (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK)
91646 
91647 #define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK        (0x100000U)
91648 #define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT       (20U)
91649 /*! SV_ORDER - Save Order
91650  *  0b0..Descriptors within the group are processed from start to end
91651  *  0b1..Descriptors within the group are processed from end to start
91652  */
91653 #define SSARC_LP_DESC_CTRL0_SV_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK)
91654 
91655 #define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK        (0x200000U)
91656 #define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT       (21U)
91657 /*! RT_ORDER - Restore order
91658  *  0b0..Descriptors within the group are processed from start to end
91659  *  0b1..Descriptors within the group are processed from end to start
91660  */
91661 #define SSARC_LP_DESC_CTRL0_RT_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK)
91662 /*! @} */
91663 
91664 /* The count of SSARC_LP_DESC_CTRL0 */
91665 #define SSARC_LP_DESC_CTRL0_COUNT                (16U)
91666 
91667 /*! @name DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register */
91668 /*! @{ */
91669 
91670 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK      (0x1U)
91671 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT     (0U)
91672 /*! SW_TRIG_SV - Software trigger save
91673  *  0b1..Request a software save operation/software restore operation in progress
91674  *  0b0..No software save request/software restore request complete
91675  */
91676 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK)
91677 
91678 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK      (0x2U)
91679 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT     (1U)
91680 /*! SW_TRIG_RT - Software trigger restore
91681  *  0b1..Request a software restore operation/software restore operation in progress
91682  *  0b0..No software restore request/software restore request complete
91683  */
91684 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK)
91685 
91686 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK    (0x70U)
91687 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT   (4U)
91688 /*! POWER_DOMAIN
91689  *  0b000..PGMC_BPC0
91690  *  0b001..PGMC_BPC1
91691  *  0b010..PGMC_BPC2
91692  *  0b011..PGMC_BPC3
91693  *  0b100..PGMC_BPC4
91694  *  0b101..PGMC_BPC5
91695  *  0b110..PGMC_BPC6
91696  *  0b111..PGMC_BPC7
91697  */
91698 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK)
91699 
91700 #define SSARC_LP_DESC_CTRL1_GP_EN_MASK           (0x80U)
91701 #define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT          (7U)
91702 /*! GP_EN - Group Enable
91703  *  0b0..Group disabled
91704  *  0b1..Group enabled
91705  */
91706 #define SSARC_LP_DESC_CTRL1_GP_EN(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK)
91707 
91708 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK     (0xF00U)
91709 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT    (8U)
91710 /*! SV_PRIORITY - Save Priority
91711  */
91712 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK)
91713 
91714 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK     (0xF000U)
91715 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT    (12U)
91716 /*! RT_PRIORITY - Restore Priority
91717  */
91718 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK)
91719 
91720 #define SSARC_LP_DESC_CTRL1_CPUD_MASK            (0x30000U)
91721 #define SSARC_LP_DESC_CTRL1_CPUD_SHIFT           (16U)
91722 /*! CPUD - CPU Domain
91723  */
91724 #define SSARC_LP_DESC_CTRL1_CPUD(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK)
91725 
91726 #define SSARC_LP_DESC_CTRL1_RL_MASK              (0x40000U)
91727 #define SSARC_LP_DESC_CTRL1_RL_SHIFT             (18U)
91728 /*! RL - Read Lock
91729  *  0b1..Group is locked (read access not allowed)
91730  *  0b0..Group is unlocked (read access allowed)
91731  */
91732 #define SSARC_LP_DESC_CTRL1_RL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK)
91733 
91734 #define SSARC_LP_DESC_CTRL1_WL_MASK              (0x80000U)
91735 #define SSARC_LP_DESC_CTRL1_WL_SHIFT             (19U)
91736 /*! WL - Write Lock
91737  *  0b1..Group is locked (write access not allowed)
91738  *  0b0..Group is unlocked (write access allowed)
91739  */
91740 #define SSARC_LP_DESC_CTRL1_WL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK)
91741 
91742 #define SSARC_LP_DESC_CTRL1_DL_MASK              (0x100000U)
91743 #define SSARC_LP_DESC_CTRL1_DL_SHIFT             (20U)
91744 /*! DL - Domain lock
91745  *  0b1..Lock
91746  *  0b0..Unlock
91747  */
91748 #define SSARC_LP_DESC_CTRL1_DL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK)
91749 /*! @} */
91750 
91751 /* The count of SSARC_LP_DESC_CTRL1 */
91752 #define SSARC_LP_DESC_CTRL1_COUNT                (16U)
91753 
91754 /*! @name DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register */
91755 /*! @{ */
91756 
91757 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK       (0xFFFFFFFFU)
91758 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT      (0U)
91759 /*! ADDR_UP - Address field (High)
91760  */
91761 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK)
91762 /*! @} */
91763 
91764 /* The count of SSARC_LP_DESC_ADDR_UP */
91765 #define SSARC_LP_DESC_ADDR_UP_COUNT              (16U)
91766 
91767 /*! @name DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register */
91768 /*! @{ */
91769 
91770 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK   (0xFFFFFFFFU)
91771 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT  (0U)
91772 /*! ADDR_DOWN - Address field (Low)
91773  */
91774 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK)
91775 /*! @} */
91776 
91777 /* The count of SSARC_LP_DESC_ADDR_DOWN */
91778 #define SSARC_LP_DESC_ADDR_DOWN_COUNT            (16U)
91779 
91780 /*! @name CTRL - Control Register */
91781 /*! @{ */
91782 
91783 #define SSARC_LP_CTRL_DIS_HW_REQ_MASK            (0x8000000U)
91784 #define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT           (27U)
91785 /*! DIS_HW_REQ - Save/Restore request disable
91786  *  0b0..PGMC save/restore requests enabled
91787  *  0b1..PGMC save/restore requests disabled
91788  */
91789 #define SSARC_LP_CTRL_DIS_HW_REQ(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
91790 
91791 #define SSARC_LP_CTRL_SW_RESET_MASK              (0x80000000U)
91792 #define SSARC_LP_CTRL_SW_RESET_SHIFT             (31U)
91793 /*! SW_RESET - Software reset
91794  */
91795 #define SSARC_LP_CTRL_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)
91796 /*! @} */
91797 
91798 /*! @name INT_STATUS - Interrupt Status Register */
91799 /*! @{ */
91800 
91801 #define SSARC_LP_INT_STATUS_ERR_INDEX_MASK       (0x3FFU)
91802 #define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT      (0U)
91803 /*! ERR_INDEX - Error Index
91804  */
91805 #define SSARC_LP_INT_STATUS_ERR_INDEX(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK)
91806 
91807 #define SSARC_LP_INT_STATUS_AHB_RESP_MASK        (0xC00U)
91808 #define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT       (10U)
91809 /*! AHB_RESP - AHB Bus response field
91810  */
91811 #define SSARC_LP_INT_STATUS_AHB_RESP(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK)
91812 
91813 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK  (0x8000000U)
91814 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U)
91815 /*! GROUP_CONFLICT - Group Conflict field
91816  *  0b1..A group conflict error has occurred
91817  *  0b0..No group conflict error
91818  */
91819 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x)    (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
91820 
91821 #define SSARC_LP_INT_STATUS_TIMEOUT_MASK         (0x10000000U)
91822 #define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT        (28U)
91823 /*! TIMEOUT - Timeout field
91824  *  0b1..A timeout event has occurred
91825  *  0b0..No timeout event
91826  */
91827 #define SSARC_LP_INT_STATUS_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK)
91828 
91829 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK     (0x20000000U)
91830 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT    (29U)
91831 /*! SW_REQ_DONE - Software Request Done
91832  *  0b1..Atleast one software triggered has been complete
91833  *  0b0..No software triggered requests or software triggered request still in progress
91834  */
91835 #define SSARC_LP_INT_STATUS_SW_REQ_DONE(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK)
91836 
91837 #define SSARC_LP_INT_STATUS_AHB_ERR_MASK         (0x40000000U)
91838 #define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT        (30U)
91839 /*! AHB_ERR - AHB Error field
91840  *  0b1..An AHB error has occurred
91841  *  0b0..No AHB error
91842  */
91843 #define SSARC_LP_INT_STATUS_AHB_ERR(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK)
91844 
91845 #define SSARC_LP_INT_STATUS_ADDR_ERR_MASK        (0x80000000U)
91846 #define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT       (31U)
91847 /*! ADDR_ERR - Address Error field
91848  *  0b1..An address error has occurred
91849  *  0b0..No address error
91850  */
91851 #define SSARC_LP_INT_STATUS_ADDR_ERR(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK)
91852 /*! @} */
91853 
91854 /*! @name HP_TIMEOUT - HP Timeout Register */
91855 /*! @{ */
91856 
91857 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK   (0xFFFFFFFFU)
91858 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT  (0U)
91859 /*! TIMEOUT_VALUE - Time out value
91860  */
91861 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK)
91862 /*! @} */
91863 
91864 /*! @name HW_GROUP_PENDING - Hardware Request Pending Register */
91865 /*! @{ */
91866 
91867 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU)
91868 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U)
91869 /*! HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request
91870  */
91871 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK)
91872 
91873 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U)
91874 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U)
91875 /*! HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request
91876  */
91877 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK)
91878 /*! @} */
91879 
91880 /*! @name SW_GROUP_PENDING - Software Request Pending Register */
91881 /*! @{ */
91882 
91883 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU)
91884 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U)
91885 /*! SW_SAVE_PENDING - This field indicates which groups are pending for save from software request
91886  */
91887 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK)
91888 
91889 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U)
91890 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U)
91891 /*! SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request
91892  */
91893 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK)
91894 /*! @} */
91895 
91896 
91897 /*!
91898  * @}
91899  */ /* end of group SSARC_LP_Register_Masks */
91900 
91901 
91902 /* SSARC_LP - Peripheral instance base addresses */
91903 /** Peripheral SSARC_LP base address */
91904 #define SSARC_LP_BASE                            (0x40CB8000u)
91905 /** Peripheral SSARC_LP base pointer */
91906 #define SSARC_LP                                 ((SSARC_LP_Type *)SSARC_LP_BASE)
91907 /** Array initializer of SSARC_LP peripheral base addresses */
91908 #define SSARC_LP_BASE_ADDRS                      { SSARC_LP_BASE }
91909 /** Array initializer of SSARC_LP peripheral base pointers */
91910 #define SSARC_LP_BASE_PTRS                       { SSARC_LP }
91911 
91912 /*!
91913  * @}
91914  */ /* end of group SSARC_LP_Peripheral_Access_Layer */
91915 
91916 
91917 /* ----------------------------------------------------------------------------
91918    -- TMPSNS Peripheral Access Layer
91919    ---------------------------------------------------------------------------- */
91920 
91921 /*!
91922  * @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer
91923  * @{
91924  */
91925 
91926 /** TMPSNS - Register Layout Typedef */
91927 typedef struct {
91928   __IO uint32_t CTRL0;                             /**< Temperature Sensor Control Register 0, offset: 0x0 */
91929   __IO uint32_t CTRL0_SET;                         /**< Temperature Sensor Control Register 0, offset: 0x4 */
91930   __IO uint32_t CTRL0_CLR;                         /**< Temperature Sensor Control Register 0, offset: 0x8 */
91931   __IO uint32_t CTRL0_TOG;                         /**< Temperature Sensor Control Register 0, offset: 0xC */
91932   __IO uint32_t CTRL1;                             /**< Temperature Sensor Control Register 1, offset: 0x10 */
91933   __IO uint32_t CTRL1_SET;                         /**< Temperature Sensor Control Register 1, offset: 0x14 */
91934   __IO uint32_t CTRL1_CLR;                         /**< Temperature Sensor Control Register 1, offset: 0x18 */
91935   __IO uint32_t CTRL1_TOG;                         /**< Temperature Sensor Control Register 1, offset: 0x1C */
91936   __IO uint32_t RANGE0;                            /**< Temperature Sensor Range Register 0, offset: 0x20 */
91937   __IO uint32_t RANGE0_SET;                        /**< Temperature Sensor Range Register 0, offset: 0x24 */
91938   __IO uint32_t RANGE0_CLR;                        /**< Temperature Sensor Range Register 0, offset: 0x28 */
91939   __IO uint32_t RANGE0_TOG;                        /**< Temperature Sensor Range Register 0, offset: 0x2C */
91940   __IO uint32_t RANGE1;                            /**< Temperature Sensor Range Register 1, offset: 0x30 */
91941   __IO uint32_t RANGE1_SET;                        /**< Temperature Sensor Range Register 1, offset: 0x34 */
91942   __IO uint32_t RANGE1_CLR;                        /**< Temperature Sensor Range Register 1, offset: 0x38 */
91943   __IO uint32_t RANGE1_TOG;                        /**< Temperature Sensor Range Register 1, offset: 0x3C */
91944        uint8_t RESERVED_0[16];
91945   __IO uint32_t STATUS0;                           /**< Temperature Sensor Status Register 0, offset: 0x50 */
91946 } TMPSNS_Type;
91947 
91948 /* ----------------------------------------------------------------------------
91949    -- TMPSNS Register Masks
91950    ---------------------------------------------------------------------------- */
91951 
91952 /*!
91953  * @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks
91954  * @{
91955  */
91956 
91957 /*! @name CTRL0 - Temperature Sensor Control Register 0 */
91958 /*! @{ */
91959 
91960 #define TMPSNS_CTRL0_SLOPE_CAL_MASK              (0x3FU)
91961 #define TMPSNS_CTRL0_SLOPE_CAL_SHIFT             (0U)
91962 /*! SLOPE_CAL - Ramp slope calibration control
91963  */
91964 #define TMPSNS_CTRL0_SLOPE_CAL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK)
91965 
91966 #define TMPSNS_CTRL0_V_SEL_MASK                  (0x300U)
91967 #define TMPSNS_CTRL0_V_SEL_SHIFT                 (8U)
91968 /*! V_SEL - Voltage Select
91969  *  0b00..Normal temperature measuring mode
91970  *  0b01-0b10..Reserved
91971  */
91972 #define TMPSNS_CTRL0_V_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK)
91973 
91974 #define TMPSNS_CTRL0_IBIAS_TRIM_MASK             (0xF000U)
91975 #define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT            (12U)
91976 /*! IBIAS_TRIM - Current bias trim value
91977  */
91978 #define TMPSNS_CTRL0_IBIAS_TRIM(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK)
91979 /*! @} */
91980 
91981 /*! @name CTRL0_SET - Temperature Sensor Control Register 0 */
91982 /*! @{ */
91983 
91984 #define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK          (0x3FU)
91985 #define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT         (0U)
91986 /*! SLOPE_CAL - Ramp slope calibration control
91987  */
91988 #define TMPSNS_CTRL0_SET_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK)
91989 
91990 #define TMPSNS_CTRL0_SET_V_SEL_MASK              (0x300U)
91991 #define TMPSNS_CTRL0_SET_V_SEL_SHIFT             (8U)
91992 /*! V_SEL - Voltage Select
91993  */
91994 #define TMPSNS_CTRL0_SET_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK)
91995 
91996 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK         (0xF000U)
91997 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT        (12U)
91998 /*! IBIAS_TRIM - Current bias trim value
91999  */
92000 #define TMPSNS_CTRL0_SET_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK)
92001 /*! @} */
92002 
92003 /*! @name CTRL0_CLR - Temperature Sensor Control Register 0 */
92004 /*! @{ */
92005 
92006 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK          (0x3FU)
92007 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT         (0U)
92008 /*! SLOPE_CAL - Ramp slope calibration control
92009  */
92010 #define TMPSNS_CTRL0_CLR_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK)
92011 
92012 #define TMPSNS_CTRL0_CLR_V_SEL_MASK              (0x300U)
92013 #define TMPSNS_CTRL0_CLR_V_SEL_SHIFT             (8U)
92014 /*! V_SEL - Voltage Select
92015  */
92016 #define TMPSNS_CTRL0_CLR_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK)
92017 
92018 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK         (0xF000U)
92019 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT        (12U)
92020 /*! IBIAS_TRIM - Current bias trim value
92021  */
92022 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK)
92023 /*! @} */
92024 
92025 /*! @name CTRL0_TOG - Temperature Sensor Control Register 0 */
92026 /*! @{ */
92027 
92028 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK          (0x3FU)
92029 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT         (0U)
92030 /*! SLOPE_CAL - Ramp slope calibration control
92031  */
92032 #define TMPSNS_CTRL0_TOG_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK)
92033 
92034 #define TMPSNS_CTRL0_TOG_V_SEL_MASK              (0x300U)
92035 #define TMPSNS_CTRL0_TOG_V_SEL_SHIFT             (8U)
92036 /*! V_SEL - Voltage Select
92037  */
92038 #define TMPSNS_CTRL0_TOG_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK)
92039 
92040 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK         (0xF000U)
92041 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT        (12U)
92042 /*! IBIAS_TRIM - Current bias trim value
92043  */
92044 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK)
92045 /*! @} */
92046 
92047 /*! @name CTRL1 - Temperature Sensor Control Register 1 */
92048 /*! @{ */
92049 
92050 #define TMPSNS_CTRL1_FREQ_MASK                   (0xFFFFU)
92051 #define TMPSNS_CTRL1_FREQ_SHIFT                  (0U)
92052 /*! FREQ - Temperature Measurement Frequency
92053  *  0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0.
92054  *  0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
92055  */
92056 #define TMPSNS_CTRL1_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
92057 
92058 #define TMPSNS_CTRL1_FINISH_IE_MASK              (0x10000U)
92059 #define TMPSNS_CTRL1_FINISH_IE_SHIFT             (16U)
92060 /*! FINISH_IE - Measurement finished interrupt enable
92061  *  0b0..Interrupt is disabled
92062  *  0b1..Interrupt is enabled
92063  */
92064 #define TMPSNS_CTRL1_FINISH_IE(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
92065 
92066 #define TMPSNS_CTRL1_LOW_TEMP_IE_MASK            (0x20000U)
92067 #define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT           (17U)
92068 /*! LOW_TEMP_IE - Low temperature interrupt enable
92069  *  0b0..Interrupt is disabled
92070  *  0b1..Interrupt is enabled
92071  */
92072 #define TMPSNS_CTRL1_LOW_TEMP_IE(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
92073 
92074 #define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK           (0x40000U)
92075 #define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT          (18U)
92076 /*! HIGH_TEMP_IE - High temperature interrupt enable
92077  *  0b0..Interrupt is disabled
92078  *  0b1..Interrupt is enabled
92079  */
92080 #define TMPSNS_CTRL1_HIGH_TEMP_IE(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
92081 
92082 #define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK          (0x80000U)
92083 #define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT         (19U)
92084 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92085  *  0b0..Interrupt is disabled
92086  *  0b1..Interrupt is enabled
92087  */
92088 #define TMPSNS_CTRL1_PANIC_TEMP_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
92089 
92090 #define TMPSNS_CTRL1_START_MASK                  (0x400000U)
92091 #define TMPSNS_CTRL1_START_SHIFT                 (22U)
92092 /*! START - Start Temperature Measurement
92093  *  0b0..No new temperature reading taken
92094  *  0b1..Initiate a new temperature reading
92095  */
92096 #define TMPSNS_CTRL1_START(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
92097 
92098 #define TMPSNS_CTRL1_PWD_MASK                    (0x800000U)
92099 #define TMPSNS_CTRL1_PWD_SHIFT                   (23U)
92100 /*! PWD - Temperature Sensor Power Down
92101  *  0b0..Sensor is active
92102  *  0b1..Sensor is powered down
92103  */
92104 #define TMPSNS_CTRL1_PWD(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
92105 
92106 #define TMPSNS_CTRL1_RFU_MASK                    (0x7F000000U)
92107 #define TMPSNS_CTRL1_RFU_SHIFT                   (24U)
92108 /*! RFU - Read/Writeable field. Reserved for future use
92109  */
92110 #define TMPSNS_CTRL1_RFU(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK)
92111 
92112 #define TMPSNS_CTRL1_PWD_FULL_MASK               (0x80000000U)
92113 #define TMPSNS_CTRL1_PWD_FULL_SHIFT              (31U)
92114 /*! PWD_FULL - Temperature Sensor Full Power Down
92115  *  0b0..Sensor is active
92116  *  0b1..Sensor is powered down
92117  */
92118 #define TMPSNS_CTRL1_PWD_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
92119 /*! @} */
92120 
92121 /*! @name CTRL1_SET - Temperature Sensor Control Register 1 */
92122 /*! @{ */
92123 
92124 #define TMPSNS_CTRL1_SET_FREQ_MASK               (0xFFFFU)
92125 #define TMPSNS_CTRL1_SET_FREQ_SHIFT              (0U)
92126 /*! FREQ - Temperature Measurement Frequency
92127  */
92128 #define TMPSNS_CTRL1_SET_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
92129 
92130 #define TMPSNS_CTRL1_SET_FINISH_IE_MASK          (0x10000U)
92131 #define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT         (16U)
92132 /*! FINISH_IE - Measurement finished interrupt enable
92133  */
92134 #define TMPSNS_CTRL1_SET_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
92135 
92136 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK        (0x20000U)
92137 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT       (17U)
92138 /*! LOW_TEMP_IE - Low temperature interrupt enable
92139  */
92140 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
92141 
92142 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK       (0x40000U)
92143 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT      (18U)
92144 /*! HIGH_TEMP_IE - High temperature interrupt enable
92145  */
92146 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
92147 
92148 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK      (0x80000U)
92149 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT     (19U)
92150 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92151  */
92152 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
92153 
92154 #define TMPSNS_CTRL1_SET_START_MASK              (0x400000U)
92155 #define TMPSNS_CTRL1_SET_START_SHIFT             (22U)
92156 /*! START - Start Temperature Measurement
92157  */
92158 #define TMPSNS_CTRL1_SET_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
92159 
92160 #define TMPSNS_CTRL1_SET_PWD_MASK                (0x800000U)
92161 #define TMPSNS_CTRL1_SET_PWD_SHIFT               (23U)
92162 /*! PWD - Temperature Sensor Power Down
92163  */
92164 #define TMPSNS_CTRL1_SET_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
92165 
92166 #define TMPSNS_CTRL1_SET_RFU_MASK                (0x7F000000U)
92167 #define TMPSNS_CTRL1_SET_RFU_SHIFT               (24U)
92168 /*! RFU - Read/Writeable field. Reserved for future use
92169  */
92170 #define TMPSNS_CTRL1_SET_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK)
92171 
92172 #define TMPSNS_CTRL1_SET_PWD_FULL_MASK           (0x80000000U)
92173 #define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT          (31U)
92174 /*! PWD_FULL - Temperature Sensor Full Power Down
92175  */
92176 #define TMPSNS_CTRL1_SET_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
92177 /*! @} */
92178 
92179 /*! @name CTRL1_CLR - Temperature Sensor Control Register 1 */
92180 /*! @{ */
92181 
92182 #define TMPSNS_CTRL1_CLR_FREQ_MASK               (0xFFFFU)
92183 #define TMPSNS_CTRL1_CLR_FREQ_SHIFT              (0U)
92184 /*! FREQ - Temperature Measurement Frequency
92185  */
92186 #define TMPSNS_CTRL1_CLR_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
92187 
92188 #define TMPSNS_CTRL1_CLR_FINISH_IE_MASK          (0x10000U)
92189 #define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT         (16U)
92190 /*! FINISH_IE - Measurement finished interrupt enable
92191  */
92192 #define TMPSNS_CTRL1_CLR_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
92193 
92194 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK        (0x20000U)
92195 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT       (17U)
92196 /*! LOW_TEMP_IE - Low temperature interrupt enable
92197  */
92198 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
92199 
92200 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK       (0x40000U)
92201 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT      (18U)
92202 /*! HIGH_TEMP_IE - High temperature interrupt enable
92203  */
92204 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
92205 
92206 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK      (0x80000U)
92207 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT     (19U)
92208 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92209  */
92210 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
92211 
92212 #define TMPSNS_CTRL1_CLR_START_MASK              (0x400000U)
92213 #define TMPSNS_CTRL1_CLR_START_SHIFT             (22U)
92214 /*! START - Start Temperature Measurement
92215  */
92216 #define TMPSNS_CTRL1_CLR_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
92217 
92218 #define TMPSNS_CTRL1_CLR_PWD_MASK                (0x800000U)
92219 #define TMPSNS_CTRL1_CLR_PWD_SHIFT               (23U)
92220 /*! PWD - Temperature Sensor Power Down
92221  */
92222 #define TMPSNS_CTRL1_CLR_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
92223 
92224 #define TMPSNS_CTRL1_CLR_RFU_MASK                (0x7F000000U)
92225 #define TMPSNS_CTRL1_CLR_RFU_SHIFT               (24U)
92226 /*! RFU - Read/Writeable field. Reserved for future use
92227  */
92228 #define TMPSNS_CTRL1_CLR_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK)
92229 
92230 #define TMPSNS_CTRL1_CLR_PWD_FULL_MASK           (0x80000000U)
92231 #define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT          (31U)
92232 /*! PWD_FULL - Temperature Sensor Full Power Down
92233  */
92234 #define TMPSNS_CTRL1_CLR_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
92235 /*! @} */
92236 
92237 /*! @name CTRL1_TOG - Temperature Sensor Control Register 1 */
92238 /*! @{ */
92239 
92240 #define TMPSNS_CTRL1_TOG_FREQ_MASK               (0xFFFFU)
92241 #define TMPSNS_CTRL1_TOG_FREQ_SHIFT              (0U)
92242 /*! FREQ - Temperature Measurement Frequency
92243  */
92244 #define TMPSNS_CTRL1_TOG_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
92245 
92246 #define TMPSNS_CTRL1_TOG_FINISH_IE_MASK          (0x10000U)
92247 #define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT         (16U)
92248 /*! FINISH_IE - Measurement finished interrupt enable
92249  */
92250 #define TMPSNS_CTRL1_TOG_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
92251 
92252 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK        (0x20000U)
92253 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT       (17U)
92254 /*! LOW_TEMP_IE - Low temperature interrupt enable
92255  */
92256 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
92257 
92258 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK       (0x40000U)
92259 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT      (18U)
92260 /*! HIGH_TEMP_IE - High temperature interrupt enable
92261  */
92262 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
92263 
92264 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK      (0x80000U)
92265 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT     (19U)
92266 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
92267  */
92268 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
92269 
92270 #define TMPSNS_CTRL1_TOG_START_MASK              (0x400000U)
92271 #define TMPSNS_CTRL1_TOG_START_SHIFT             (22U)
92272 /*! START - Start Temperature Measurement
92273  */
92274 #define TMPSNS_CTRL1_TOG_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
92275 
92276 #define TMPSNS_CTRL1_TOG_PWD_MASK                (0x800000U)
92277 #define TMPSNS_CTRL1_TOG_PWD_SHIFT               (23U)
92278 /*! PWD - Temperature Sensor Power Down
92279  */
92280 #define TMPSNS_CTRL1_TOG_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
92281 
92282 #define TMPSNS_CTRL1_TOG_RFU_MASK                (0x7F000000U)
92283 #define TMPSNS_CTRL1_TOG_RFU_SHIFT               (24U)
92284 /*! RFU - Read/Writeable field. Reserved for future use
92285  */
92286 #define TMPSNS_CTRL1_TOG_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK)
92287 
92288 #define TMPSNS_CTRL1_TOG_PWD_FULL_MASK           (0x80000000U)
92289 #define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT          (31U)
92290 /*! PWD_FULL - Temperature Sensor Full Power Down
92291  */
92292 #define TMPSNS_CTRL1_TOG_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
92293 /*! @} */
92294 
92295 /*! @name RANGE0 - Temperature Sensor Range Register 0 */
92296 /*! @{ */
92297 
92298 #define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK          (0xFFFU)
92299 #define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT         (0U)
92300 /*! LOW_TEMP_VAL - Low temperature threshold value
92301  */
92302 #define TMPSNS_RANGE0_LOW_TEMP_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
92303 
92304 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK         (0xFFF0000U)
92305 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT        (16U)
92306 /*! HIGH_TEMP_VAL - High temperature threshold value
92307  */
92308 #define TMPSNS_RANGE0_HIGH_TEMP_VAL(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
92309 /*! @} */
92310 
92311 /*! @name RANGE0_SET - Temperature Sensor Range Register 0 */
92312 /*! @{ */
92313 
92314 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK      (0xFFFU)
92315 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT     (0U)
92316 /*! LOW_TEMP_VAL - Low temperature threshold value
92317  */
92318 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
92319 
92320 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92321 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT    (16U)
92322 /*! HIGH_TEMP_VAL - High temperature threshold value
92323  */
92324 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
92325 /*! @} */
92326 
92327 /*! @name RANGE0_CLR - Temperature Sensor Range Register 0 */
92328 /*! @{ */
92329 
92330 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK      (0xFFFU)
92331 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT     (0U)
92332 /*! LOW_TEMP_VAL - Low temperature threshold value
92333  */
92334 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
92335 
92336 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92337 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT    (16U)
92338 /*! HIGH_TEMP_VAL - High temperature threshold value
92339  */
92340 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
92341 /*! @} */
92342 
92343 /*! @name RANGE0_TOG - Temperature Sensor Range Register 0 */
92344 /*! @{ */
92345 
92346 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK      (0xFFFU)
92347 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT     (0U)
92348 /*! LOW_TEMP_VAL - Low temperature threshold value
92349  */
92350 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
92351 
92352 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
92353 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT    (16U)
92354 /*! HIGH_TEMP_VAL - High temperature threshold value
92355  */
92356 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
92357 /*! @} */
92358 
92359 /*! @name RANGE1 - Temperature Sensor Range Register 1 */
92360 /*! @{ */
92361 
92362 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK        (0xFFFU)
92363 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT       (0U)
92364 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92365  */
92366 #define TMPSNS_RANGE1_PANIC_TEMP_VAL(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
92367 /*! @} */
92368 
92369 /*! @name RANGE1_SET - Temperature Sensor Range Register 1 */
92370 /*! @{ */
92371 
92372 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK    (0xFFFU)
92373 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT   (0U)
92374 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92375  */
92376 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
92377 /*! @} */
92378 
92379 /*! @name RANGE1_CLR - Temperature Sensor Range Register 1 */
92380 /*! @{ */
92381 
92382 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK    (0xFFFU)
92383 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT   (0U)
92384 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92385  */
92386 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
92387 /*! @} */
92388 
92389 /*! @name RANGE1_TOG - Temperature Sensor Range Register 1 */
92390 /*! @{ */
92391 
92392 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK    (0xFFFU)
92393 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT   (0U)
92394 /*! PANIC_TEMP_VAL - Panic temperature threshold value
92395  */
92396 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
92397 /*! @} */
92398 
92399 /*! @name STATUS0 - Temperature Sensor Status Register 0 */
92400 /*! @{ */
92401 
92402 #define TMPSNS_STATUS0_TEMP_VAL_MASK             (0xFFFU)
92403 #define TMPSNS_STATUS0_TEMP_VAL_SHIFT            (0U)
92404 /*! TEMP_VAL - Measured temperature value
92405  */
92406 #define TMPSNS_STATUS0_TEMP_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
92407 
92408 #define TMPSNS_STATUS0_FINISH_MASK               (0x10000U)
92409 #define TMPSNS_STATUS0_FINISH_SHIFT              (16U)
92410 /*! FINISH - Temperature measurement complete
92411  *  0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0)
92412  *  0b1..Temperature reading is complete and new temperature value available for reading
92413  */
92414 #define TMPSNS_STATUS0_FINISH(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
92415 
92416 #define TMPSNS_STATUS0_LOW_TEMP_MASK             (0x20000U)
92417 #define TMPSNS_STATUS0_LOW_TEMP_SHIFT            (17U)
92418 /*! LOW_TEMP - Low temperature alarm bit
92419  *  0b0..No Low temperature alert
92420  *  0b1..Low temperature alert
92421  */
92422 #define TMPSNS_STATUS0_LOW_TEMP(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
92423 
92424 #define TMPSNS_STATUS0_HIGH_TEMP_MASK            (0x40000U)
92425 #define TMPSNS_STATUS0_HIGH_TEMP_SHIFT           (18U)
92426 /*! HIGH_TEMP - High temperature alarm bit
92427  *  0b0..No High temperature alert
92428  *  0b1..High temperature alert
92429  */
92430 #define TMPSNS_STATUS0_HIGH_TEMP(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
92431 
92432 #define TMPSNS_STATUS0_PANIC_TEMP_MASK           (0x80000U)
92433 #define TMPSNS_STATUS0_PANIC_TEMP_SHIFT          (19U)
92434 /*! PANIC_TEMP - Panic temperature alarm bit
92435  *  0b0..No Panic temperature alert
92436  *  0b1..Panic temperature alert
92437  */
92438 #define TMPSNS_STATUS0_PANIC_TEMP(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK)
92439 /*! @} */
92440 
92441 
92442 /*!
92443  * @}
92444  */ /* end of group TMPSNS_Register_Masks */
92445 
92446 
92447 /* TMPSNS - Peripheral instance base addresses */
92448 /** Peripheral TMPSNS base address */
92449 #define TMPSNS_BASE                              (0u)
92450 /** Peripheral TMPSNS base pointer */
92451 #define TMPSNS                                   ((TMPSNS_Type *)TMPSNS_BASE)
92452 /** Array initializer of TMPSNS peripheral base addresses */
92453 #define TMPSNS_BASE_ADDRS                        { TMPSNS_BASE }
92454 /** Array initializer of TMPSNS peripheral base pointers */
92455 #define TMPSNS_BASE_PTRS                         { TMPSNS }
92456 
92457 /*!
92458  * @}
92459  */ /* end of group TMPSNS_Peripheral_Access_Layer */
92460 
92461 
92462 /* ----------------------------------------------------------------------------
92463    -- TMR Peripheral Access Layer
92464    ---------------------------------------------------------------------------- */
92465 
92466 /*!
92467  * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
92468  * @{
92469  */
92470 
92471 /** TMR - Register Layout Typedef */
92472 typedef struct {
92473   struct {                                         /* offset: 0x0, array step: 0x20 */
92474     __IO uint16_t COMP1;                             /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
92475     __IO uint16_t COMP2;                             /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
92476     __IO uint16_t CAPT;                              /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
92477     __IO uint16_t LOAD;                              /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
92478     __IO uint16_t HOLD;                              /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
92479     __IO uint16_t CNTR;                              /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
92480     __IO uint16_t CTRL;                              /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
92481     __IO uint16_t SCTRL;                             /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
92482     __IO uint16_t CMPLD1;                            /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
92483     __IO uint16_t CMPLD2;                            /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
92484     __IO uint16_t CSCTRL;                            /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
92485     __IO uint16_t FILT;                              /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
92486     __IO uint16_t DMA;                               /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
92487          uint8_t RESERVED_0[4];
92488     __IO uint16_t ENBL;                              /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
92489   } CHANNEL[4];
92490 } TMR_Type;
92491 
92492 /* ----------------------------------------------------------------------------
92493    -- TMR Register Masks
92494    ---------------------------------------------------------------------------- */
92495 
92496 /*!
92497  * @addtogroup TMR_Register_Masks TMR Register Masks
92498  * @{
92499  */
92500 
92501 /*! @name COMP1 - Timer Channel Compare Register 1 */
92502 /*! @{ */
92503 
92504 #define TMR_COMP1_COMPARISON_1_MASK              (0xFFFFU)
92505 #define TMR_COMP1_COMPARISON_1_SHIFT             (0U)
92506 /*! COMPARISON_1 - Comparison Value 1
92507  */
92508 #define TMR_COMP1_COMPARISON_1(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
92509 /*! @} */
92510 
92511 /* The count of TMR_COMP1 */
92512 #define TMR_COMP1_COUNT                          (4U)
92513 
92514 /*! @name COMP2 - Timer Channel Compare Register 2 */
92515 /*! @{ */
92516 
92517 #define TMR_COMP2_COMPARISON_2_MASK              (0xFFFFU)
92518 #define TMR_COMP2_COMPARISON_2_SHIFT             (0U)
92519 /*! COMPARISON_2 - Comparison Value 2
92520  */
92521 #define TMR_COMP2_COMPARISON_2(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
92522 /*! @} */
92523 
92524 /* The count of TMR_COMP2 */
92525 #define TMR_COMP2_COUNT                          (4U)
92526 
92527 /*! @name CAPT - Timer Channel Capture Register */
92528 /*! @{ */
92529 
92530 #define TMR_CAPT_CAPTURE_MASK                    (0xFFFFU)
92531 #define TMR_CAPT_CAPTURE_SHIFT                   (0U)
92532 /*! CAPTURE - Capture Value
92533  */
92534 #define TMR_CAPT_CAPTURE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
92535 /*! @} */
92536 
92537 /* The count of TMR_CAPT */
92538 #define TMR_CAPT_COUNT                           (4U)
92539 
92540 /*! @name LOAD - Timer Channel Load Register */
92541 /*! @{ */
92542 
92543 #define TMR_LOAD_LOAD_MASK                       (0xFFFFU)
92544 #define TMR_LOAD_LOAD_SHIFT                      (0U)
92545 /*! LOAD - Timer Load Register
92546  */
92547 #define TMR_LOAD_LOAD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
92548 /*! @} */
92549 
92550 /* The count of TMR_LOAD */
92551 #define TMR_LOAD_COUNT                           (4U)
92552 
92553 /*! @name HOLD - Timer Channel Hold Register */
92554 /*! @{ */
92555 
92556 #define TMR_HOLD_HOLD_MASK                       (0xFFFFU)
92557 #define TMR_HOLD_HOLD_SHIFT                      (0U)
92558 /*! HOLD - HOLD
92559  */
92560 #define TMR_HOLD_HOLD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
92561 /*! @} */
92562 
92563 /* The count of TMR_HOLD */
92564 #define TMR_HOLD_COUNT                           (4U)
92565 
92566 /*! @name CNTR - Timer Channel Counter Register */
92567 /*! @{ */
92568 
92569 #define TMR_CNTR_COUNTER_MASK                    (0xFFFFU)
92570 #define TMR_CNTR_COUNTER_SHIFT                   (0U)
92571 /*! COUNTER - COUNTER
92572  */
92573 #define TMR_CNTR_COUNTER(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
92574 /*! @} */
92575 
92576 /* The count of TMR_CNTR */
92577 #define TMR_CNTR_COUNT                           (4U)
92578 
92579 /*! @name CTRL - Timer Channel Control Register */
92580 /*! @{ */
92581 
92582 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
92583 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
92584 /*! OUTMODE - Output Mode
92585  *  0b000..Asserted while counter is active
92586  *  0b001..Clear OFLAG output on successful compare
92587  *  0b010..Set OFLAG output on successful compare
92588  *  0b011..Toggle OFLAG output on successful compare
92589  *  0b100..Toggle OFLAG output using alternating compare registers
92590  *  0b101..Set on compare, cleared on secondary source input edge
92591  *  0b110..Set on compare, cleared on counter rollover
92592  *  0b111..Enable gated clock output while counter is active
92593  */
92594 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
92595 
92596 #define TMR_CTRL_COINIT_MASK                     (0x8U)
92597 #define TMR_CTRL_COINIT_SHIFT                    (3U)
92598 /*! COINIT - Co-Channel Initialization
92599  *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
92600  *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
92601  */
92602 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
92603 
92604 #define TMR_CTRL_DIR_MASK                        (0x10U)
92605 #define TMR_CTRL_DIR_SHIFT                       (4U)
92606 /*! DIR - Count Direction
92607  *  0b0..Count up.
92608  *  0b1..Count down.
92609  */
92610 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
92611 
92612 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
92613 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
92614 /*! LENGTH - Count Length
92615  *  0b0..Count until roll over at $FFFF and continue from $0000.
92616  *  0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
92617  *       reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
92618  *       When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
92619  *       comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
92620  *       value is reached, re-initializes, counts until COMP1 value is reached, and so on.
92621  */
92622 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
92623 
92624 #define TMR_CTRL_ONCE_MASK                       (0x40U)
92625 #define TMR_CTRL_ONCE_SHIFT                      (6U)
92626 /*! ONCE - Count Once
92627  *  0b0..Count repeatedly.
92628  *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
92629  *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
92630  *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
92631  *       the COMP2 value, and then stops.
92632  */
92633 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
92634 
92635 #define TMR_CTRL_SCS_MASK                        (0x180U)
92636 #define TMR_CTRL_SCS_SHIFT                       (7U)
92637 /*! SCS - Secondary Count Source
92638  *  0b00..Counter 0 input pin
92639  *  0b01..Counter 1 input pin
92640  *  0b10..Counter 2 input pin
92641  *  0b11..Counter 3 input pin
92642  */
92643 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
92644 
92645 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
92646 #define TMR_CTRL_PCS_SHIFT                       (9U)
92647 /*! PCS - Primary Count Source
92648  *  0b0000..Counter 0 input pin
92649  *  0b0001..Counter 1 input pin
92650  *  0b0010..Counter 2 input pin
92651  *  0b0011..Counter 3 input pin
92652  *  0b0100..Counter 0 output
92653  *  0b0101..Counter 1 output
92654  *  0b0110..Counter 2 output
92655  *  0b0111..Counter 3 output
92656  *  0b1000..IP bus clock divide by 1 prescaler
92657  *  0b1001..IP bus clock divide by 2 prescaler
92658  *  0b1010..IP bus clock divide by 4 prescaler
92659  *  0b1011..IP bus clock divide by 8 prescaler
92660  *  0b1100..IP bus clock divide by 16 prescaler
92661  *  0b1101..IP bus clock divide by 32 prescaler
92662  *  0b1110..IP bus clock divide by 64 prescaler
92663  *  0b1111..IP bus clock divide by 128 prescaler
92664  */
92665 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
92666 
92667 #define TMR_CTRL_CM_MASK                         (0xE000U)
92668 #define TMR_CTRL_CM_SHIFT                        (13U)
92669 /*! CM - Count Mode
92670  *  0b000..No operation
92671  *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
92672  *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
92673  *         edges are counted regardless of the value of SCTRL[IPS].
92674  *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
92675  *  0b011..Count rising edges of primary source while secondary input high active
92676  *  0b100..Quadrature count mode, uses primary and secondary sources
92677  *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
92678  *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
92679  *  0b110..Edge of secondary source triggers primary count until compare
92680  *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
92681  */
92682 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
92683 /*! @} */
92684 
92685 /* The count of TMR_CTRL */
92686 #define TMR_CTRL_COUNT                           (4U)
92687 
92688 /*! @name SCTRL - Timer Channel Status and Control Register */
92689 /*! @{ */
92690 
92691 #define TMR_SCTRL_OEN_MASK                       (0x1U)
92692 #define TMR_SCTRL_OEN_SHIFT                      (0U)
92693 /*! OEN - Output Enable
92694  *  0b0..The external pin is configured as an input.
92695  *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
92696  *       their input see the driven value. The polarity of the signal is determined by OPS.
92697  */
92698 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
92699 
92700 #define TMR_SCTRL_OPS_MASK                       (0x2U)
92701 #define TMR_SCTRL_OPS_SHIFT                      (1U)
92702 /*! OPS - Output Polarity Select
92703  *  0b0..True polarity.
92704  *  0b1..Inverted polarity.
92705  */
92706 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
92707 
92708 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
92709 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
92710 /*! FORCE - Force OFLAG Output
92711  */
92712 #define TMR_SCTRL_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
92713 
92714 #define TMR_SCTRL_VAL_MASK                       (0x8U)
92715 #define TMR_SCTRL_VAL_SHIFT                      (3U)
92716 /*! VAL - Forced OFLAG Value
92717  */
92718 #define TMR_SCTRL_VAL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
92719 
92720 #define TMR_SCTRL_EEOF_MASK                      (0x10U)
92721 #define TMR_SCTRL_EEOF_SHIFT                     (4U)
92722 /*! EEOF - Enable External OFLAG Force
92723  */
92724 #define TMR_SCTRL_EEOF(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
92725 
92726 #define TMR_SCTRL_MSTR_MASK                      (0x20U)
92727 #define TMR_SCTRL_MSTR_SHIFT                     (5U)
92728 /*! MSTR - Master Mode
92729  */
92730 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
92731 
92732 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
92733 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
92734 /*! CAPTURE_MODE - Input Capture Mode
92735  *  0b00..Capture function is disabled
92736  *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
92737  *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
92738  *  0b11..Load capture register on both edges of input
92739  */
92740 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
92741 
92742 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
92743 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
92744 /*! INPUT - External Input Signal
92745  */
92746 #define TMR_SCTRL_INPUT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
92747 
92748 #define TMR_SCTRL_IPS_MASK                       (0x200U)
92749 #define TMR_SCTRL_IPS_SHIFT                      (9U)
92750 /*! IPS - Input Polarity Select
92751  */
92752 #define TMR_SCTRL_IPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
92753 
92754 #define TMR_SCTRL_IEFIE_MASK                     (0x400U)
92755 #define TMR_SCTRL_IEFIE_SHIFT                    (10U)
92756 /*! IEFIE - Input Edge Flag Interrupt Enable
92757  */
92758 #define TMR_SCTRL_IEFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
92759 
92760 #define TMR_SCTRL_IEF_MASK                       (0x800U)
92761 #define TMR_SCTRL_IEF_SHIFT                      (11U)
92762 /*! IEF - Input Edge Flag
92763  */
92764 #define TMR_SCTRL_IEF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
92765 
92766 #define TMR_SCTRL_TOFIE_MASK                     (0x1000U)
92767 #define TMR_SCTRL_TOFIE_SHIFT                    (12U)
92768 /*! TOFIE - Timer Overflow Flag Interrupt Enable
92769  */
92770 #define TMR_SCTRL_TOFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
92771 
92772 #define TMR_SCTRL_TOF_MASK                       (0x2000U)
92773 #define TMR_SCTRL_TOF_SHIFT                      (13U)
92774 /*! TOF - Timer Overflow Flag
92775  */
92776 #define TMR_SCTRL_TOF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
92777 
92778 #define TMR_SCTRL_TCFIE_MASK                     (0x4000U)
92779 #define TMR_SCTRL_TCFIE_SHIFT                    (14U)
92780 /*! TCFIE - Timer Compare Flag Interrupt Enable
92781  */
92782 #define TMR_SCTRL_TCFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
92783 
92784 #define TMR_SCTRL_TCF_MASK                       (0x8000U)
92785 #define TMR_SCTRL_TCF_SHIFT                      (15U)
92786 /*! TCF - Timer Compare Flag
92787  */
92788 #define TMR_SCTRL_TCF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
92789 /*! @} */
92790 
92791 /* The count of TMR_SCTRL */
92792 #define TMR_SCTRL_COUNT                          (4U)
92793 
92794 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
92795 /*! @{ */
92796 
92797 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK        (0xFFFFU)
92798 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT       (0U)
92799 /*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1
92800  */
92801 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
92802 /*! @} */
92803 
92804 /* The count of TMR_CMPLD1 */
92805 #define TMR_CMPLD1_COUNT                         (4U)
92806 
92807 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
92808 /*! @{ */
92809 
92810 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK        (0xFFFFU)
92811 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT       (0U)
92812 /*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2
92813  */
92814 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
92815 /*! @} */
92816 
92817 /* The count of TMR_CMPLD2 */
92818 #define TMR_CMPLD2_COUNT                         (4U)
92819 
92820 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
92821 /*! @{ */
92822 
92823 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
92824 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
92825 /*! CL1 - Compare Load Control 1
92826  *  0b00..Never preload
92827  *  0b01..Load upon successful compare with the value in COMP1
92828  *  0b10..Load upon successful compare with the value in COMP2
92829  *  0b11..Reserved
92830  */
92831 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
92832 
92833 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
92834 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
92835 /*! CL2 - Compare Load Control 2
92836  *  0b00..Never preload
92837  *  0b01..Load upon successful compare with the value in COMP1
92838  *  0b10..Load upon successful compare with the value in COMP2
92839  *  0b11..Reserved
92840  */
92841 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
92842 
92843 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
92844 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
92845 /*! TCF1 - Timer Compare 1 Interrupt Flag
92846  */
92847 #define TMR_CSCTRL_TCF1(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
92848 
92849 #define TMR_CSCTRL_TCF2_MASK                     (0x20U)
92850 #define TMR_CSCTRL_TCF2_SHIFT                    (5U)
92851 /*! TCF2 - Timer Compare 2 Interrupt Flag
92852  */
92853 #define TMR_CSCTRL_TCF2(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
92854 
92855 #define TMR_CSCTRL_TCF1EN_MASK                   (0x40U)
92856 #define TMR_CSCTRL_TCF1EN_SHIFT                  (6U)
92857 /*! TCF1EN - Timer Compare 1 Interrupt Enable
92858  */
92859 #define TMR_CSCTRL_TCF1EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
92860 
92861 #define TMR_CSCTRL_TCF2EN_MASK                   (0x80U)
92862 #define TMR_CSCTRL_TCF2EN_SHIFT                  (7U)
92863 /*! TCF2EN - Timer Compare 2 Interrupt Enable
92864  */
92865 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
92866 
92867 #define TMR_CSCTRL_UP_MASK                       (0x200U)
92868 #define TMR_CSCTRL_UP_SHIFT                      (9U)
92869 /*! UP - Counting Direction Indicator
92870  *  0b0..The last count was in the DOWN direction.
92871  *  0b1..The last count was in the UP direction.
92872  */
92873 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
92874 
92875 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
92876 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
92877 /*! TCI - Triggered Count Initialization Control
92878  *  0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
92879  *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
92880  */
92881 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
92882 
92883 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
92884 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
92885 /*! ROC - Reload on Capture
92886  *  0b0..Do not reload the counter on a capture event.
92887  *  0b1..Reload the counter on a capture event.
92888  */
92889 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
92890 
92891 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
92892 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
92893 /*! ALT_LOAD - Alternative Load Enable
92894  *  0b0..Counter can be re-initialized only with the LOAD register.
92895  *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
92896  */
92897 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
92898 
92899 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
92900 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
92901 /*! FAULT - Fault Enable
92902  *  0b0..Fault function disabled.
92903  *  0b1..Fault function enabled.
92904  */
92905 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
92906 
92907 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
92908 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
92909 /*! DBG_EN - Debug Actions Enable
92910  *  0b00..Continue with normal operation during debug mode. (default)
92911  *  0b01..Halt TMR counter during debug mode.
92912  *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
92913  *  0b11..Both halt counter and force output to 0 during debug mode.
92914  */
92915 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
92916 /*! @} */
92917 
92918 /* The count of TMR_CSCTRL */
92919 #define TMR_CSCTRL_COUNT                         (4U)
92920 
92921 /*! @name FILT - Timer Channel Input Filter Register */
92922 /*! @{ */
92923 
92924 #define TMR_FILT_FILT_PER_MASK                   (0xFFU)
92925 #define TMR_FILT_FILT_PER_SHIFT                  (0U)
92926 /*! FILT_PER - Input Filter Sample Period
92927  */
92928 #define TMR_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
92929 
92930 #define TMR_FILT_FILT_CNT_MASK                   (0x700U)
92931 #define TMR_FILT_FILT_CNT_SHIFT                  (8U)
92932 /*! FILT_CNT - Input Filter Sample Count
92933  */
92934 #define TMR_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
92935 /*! @} */
92936 
92937 /* The count of TMR_FILT */
92938 #define TMR_FILT_COUNT                           (4U)
92939 
92940 /*! @name DMA - Timer Channel DMA Enable Register */
92941 /*! @{ */
92942 
92943 #define TMR_DMA_IEFDE_MASK                       (0x1U)
92944 #define TMR_DMA_IEFDE_SHIFT                      (0U)
92945 /*! IEFDE - Input Edge Flag DMA Enable
92946  */
92947 #define TMR_DMA_IEFDE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
92948 
92949 #define TMR_DMA_CMPLD1DE_MASK                    (0x2U)
92950 #define TMR_DMA_CMPLD1DE_SHIFT                   (1U)
92951 /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable
92952  */
92953 #define TMR_DMA_CMPLD1DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
92954 
92955 #define TMR_DMA_CMPLD2DE_MASK                    (0x4U)
92956 #define TMR_DMA_CMPLD2DE_SHIFT                   (2U)
92957 /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable
92958  */
92959 #define TMR_DMA_CMPLD2DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
92960 /*! @} */
92961 
92962 /* The count of TMR_DMA */
92963 #define TMR_DMA_COUNT                            (4U)
92964 
92965 /*! @name ENBL - Timer Channel Enable Register */
92966 /*! @{ */
92967 
92968 #define TMR_ENBL_ENBL_MASK                       (0xFU)
92969 #define TMR_ENBL_ENBL_SHIFT                      (0U)
92970 /*! ENBL - Timer Channel Enable
92971  *  0b0000..Timer channel is disabled.
92972  *  0b0001..Timer channel is enabled. (default)
92973  */
92974 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
92975 /*! @} */
92976 
92977 /* The count of TMR_ENBL */
92978 #define TMR_ENBL_COUNT                           (4U)
92979 
92980 
92981 /*!
92982  * @}
92983  */ /* end of group TMR_Register_Masks */
92984 
92985 
92986 /* TMR - Peripheral instance base addresses */
92987 /** Peripheral TMR1 base address */
92988 #define TMR1_BASE                                (0x4015C000u)
92989 /** Peripheral TMR1 base pointer */
92990 #define TMR1                                     ((TMR_Type *)TMR1_BASE)
92991 /** Peripheral TMR2 base address */
92992 #define TMR2_BASE                                (0x40160000u)
92993 /** Peripheral TMR2 base pointer */
92994 #define TMR2                                     ((TMR_Type *)TMR2_BASE)
92995 /** Peripheral TMR3 base address */
92996 #define TMR3_BASE                                (0x40164000u)
92997 /** Peripheral TMR3 base pointer */
92998 #define TMR3                                     ((TMR_Type *)TMR3_BASE)
92999 /** Peripheral TMR4 base address */
93000 #define TMR4_BASE                                (0x40168000u)
93001 /** Peripheral TMR4 base pointer */
93002 #define TMR4                                     ((TMR_Type *)TMR4_BASE)
93003 /** Array initializer of TMR peripheral base addresses */
93004 #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
93005 /** Array initializer of TMR peripheral base pointers */
93006 #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
93007 /** Interrupt vectors for the TMR peripheral type */
93008 #define TMR_IRQS                                 { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
93009 
93010 /*!
93011  * @}
93012  */ /* end of group TMR_Peripheral_Access_Layer */
93013 
93014 
93015 /* ----------------------------------------------------------------------------
93016    -- USB Peripheral Access Layer
93017    ---------------------------------------------------------------------------- */
93018 
93019 /*!
93020  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
93021  * @{
93022  */
93023 
93024 /** USB - Register Layout Typedef */
93025 typedef struct {
93026   __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
93027   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
93028   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
93029   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
93030   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
93031   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
93032        uint8_t RESERVED_0[104];
93033   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
93034   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
93035   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
93036   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
93037   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
93038        uint8_t RESERVED_1[108];
93039   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
93040        uint8_t RESERVED_2[1];
93041   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
93042   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
93043   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
93044        uint8_t RESERVED_3[20];
93045   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
93046        uint8_t RESERVED_4[2];
93047   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
93048        uint8_t RESERVED_5[24];
93049   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
93050   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
93051   __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
93052   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
93053        uint8_t RESERVED_6[4];
93054   union {                                          /* offset: 0x154 */
93055     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
93056     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
93057   };
93058   union {                                          /* offset: 0x158 */
93059     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
93060     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
93061   };
93062        uint8_t RESERVED_7[4];
93063   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
93064   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
93065        uint8_t RESERVED_8[16];
93066   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
93067   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
93068   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
93069   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
93070        uint8_t RESERVED_9[28];
93071   __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
93072   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
93073   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
93074   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
93075   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
93076   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
93077   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
93078   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
93079   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
93080 } USB_Type;
93081 
93082 /* ----------------------------------------------------------------------------
93083    -- USB Register Masks
93084    ---------------------------------------------------------------------------- */
93085 
93086 /*!
93087  * @addtogroup USB_Register_Masks USB Register Masks
93088  * @{
93089  */
93090 
93091 /*! @name ID - Identification register */
93092 /*! @{ */
93093 
93094 #define USB_ID_ID_MASK                           (0x3FU)
93095 #define USB_ID_ID_SHIFT                          (0U)
93096 /*! ID - ID
93097  */
93098 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
93099 
93100 #define USB_ID_NID_MASK                          (0x3F00U)
93101 #define USB_ID_NID_SHIFT                         (8U)
93102 /*! NID - NID
93103  */
93104 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
93105 
93106 #define USB_ID_REVISION_MASK                     (0xFF0000U)
93107 #define USB_ID_REVISION_SHIFT                    (16U)
93108 /*! REVISION - REVISION
93109  */
93110 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
93111 /*! @} */
93112 
93113 /*! @name HWGENERAL - Hardware General */
93114 /*! @{ */
93115 
93116 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
93117 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
93118 /*! PHYW - PHYW
93119  *  0b00..8 bit wide data bus (Software non-programmable)
93120  *  0b01..16 bit wide data bus (Software non-programmable)
93121  *  0b10..Reset to 8 bit wide data bus (Software programmable)
93122  *  0b11..Reset to 16 bit wide data bus (Software programmable)
93123  */
93124 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
93125 
93126 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
93127 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
93128 /*! PHYM - PHYM
93129  *  0b000..UTMI/UMTI+
93130  *  0b001..ULPI DDR
93131  *  0b010..ULPI
93132  *  0b011..Serial Only
93133  *  0b100..Software programmable - reset to UTMI/UTMI+
93134  *  0b101..Software programmable - reset to ULPI DDR
93135  *  0b110..Software programmable - reset to ULPI
93136  *  0b111..Software programmable - reset to Serial
93137  */
93138 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
93139 
93140 #define USB_HWGENERAL_SM_MASK                    (0x600U)
93141 #define USB_HWGENERAL_SM_SHIFT                   (9U)
93142 /*! SM - SM
93143  *  0b00..No Serial Engine, always use parallel signalling.
93144  *  0b01..Serial Engine present, always use serial signalling for FS/LS.
93145  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
93146  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
93147  */
93148 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
93149 /*! @} */
93150 
93151 /*! @name HWHOST - Host Hardware Parameters */
93152 /*! @{ */
93153 
93154 #define USB_HWHOST_HC_MASK                       (0x1U)
93155 #define USB_HWHOST_HC_SHIFT                      (0U)
93156 /*! HC - HC
93157  *  0b1..Supported
93158  *  0b0..Not supported
93159  */
93160 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
93161 
93162 #define USB_HWHOST_NPORT_MASK                    (0xEU)
93163 #define USB_HWHOST_NPORT_SHIFT                   (1U)
93164 /*! NPORT - NPORT
93165  */
93166 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
93167 /*! @} */
93168 
93169 /*! @name HWDEVICE - Device Hardware Parameters */
93170 /*! @{ */
93171 
93172 #define USB_HWDEVICE_DC_MASK                     (0x1U)
93173 #define USB_HWDEVICE_DC_SHIFT                    (0U)
93174 /*! DC - DC
93175  *  0b1..Supported
93176  *  0b0..Not supported
93177  */
93178 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
93179 
93180 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
93181 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
93182 /*! DEVEP - DEVEP
93183  */
93184 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
93185 /*! @} */
93186 
93187 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
93188 /*! @{ */
93189 
93190 #define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
93191 #define USB_HWTXBUF_TXBURST_SHIFT                (0U)
93192 /*! TXBURST - TXBURST
93193  */
93194 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
93195 
93196 #define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
93197 #define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
93198 /*! TXCHANADD - TXCHANADD
93199  */
93200 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
93201 /*! @} */
93202 
93203 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
93204 /*! @{ */
93205 
93206 #define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
93207 #define USB_HWRXBUF_RXBURST_SHIFT                (0U)
93208 /*! RXBURST - RXBURST
93209  */
93210 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
93211 
93212 #define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
93213 #define USB_HWRXBUF_RXADD_SHIFT                  (8U)
93214 /*! RXADD - RXADD
93215  */
93216 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
93217 /*! @} */
93218 
93219 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
93220 /*! @{ */
93221 
93222 #define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
93223 #define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
93224 /*! GPTLD - GPTLD
93225  */
93226 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
93227 /*! @} */
93228 
93229 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
93230 /*! @{ */
93231 
93232 #define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
93233 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
93234 /*! GPTCNT - GPTCNT
93235  */
93236 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
93237 
93238 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
93239 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
93240 /*! GPTMODE - GPTMODE
93241  *  0b0..One Shot Mode
93242  *  0b1..Repeat Mode
93243  */
93244 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
93245 
93246 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
93247 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
93248 /*! GPTRST - GPTRST
93249  *  0b0..No action
93250  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
93251  */
93252 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
93253 
93254 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
93255 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
93256 /*! GPTRUN - GPTRUN
93257  *  0b0..Stop counting
93258  *  0b1..Run
93259  */
93260 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
93261 /*! @} */
93262 
93263 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
93264 /*! @{ */
93265 
93266 #define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
93267 #define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
93268 /*! GPTLD - GPTLD
93269  */
93270 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
93271 /*! @} */
93272 
93273 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
93274 /*! @{ */
93275 
93276 #define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
93277 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
93278 /*! GPTCNT - GPTCNT
93279  */
93280 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
93281 
93282 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
93283 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
93284 /*! GPTMODE - GPTMODE
93285  *  0b0..One Shot Mode
93286  *  0b1..Repeat Mode
93287  */
93288 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
93289 
93290 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
93291 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
93292 /*! GPTRST - GPTRST
93293  *  0b0..No action
93294  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
93295  */
93296 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
93297 
93298 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
93299 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
93300 /*! GPTRUN - GPTRUN
93301  *  0b0..Stop counting
93302  *  0b1..Run
93303  */
93304 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
93305 /*! @} */
93306 
93307 /*! @name SBUSCFG - System Bus Config */
93308 /*! @{ */
93309 
93310 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
93311 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
93312 /*! AHBBRST - AHBBRST
93313  *  0b000..Incremental burst of unspecified length only
93314  *  0b001..INCR4 burst, then single transfer
93315  *  0b010..INCR8 burst, INCR4 burst, then single transfer
93316  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
93317  *  0b100..Reserved, don't use
93318  *  0b101..INCR4 burst, then incremental burst of unspecified length
93319  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
93320  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
93321  */
93322 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
93323 /*! @} */
93324 
93325 /*! @name CAPLENGTH - Capability Registers Length */
93326 /*! @{ */
93327 
93328 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
93329 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
93330 /*! CAPLENGTH - CAPLENGTH
93331  */
93332 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
93333 /*! @} */
93334 
93335 /*! @name HCIVERSION - Host Controller Interface Version */
93336 /*! @{ */
93337 
93338 #define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
93339 #define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
93340 /*! HCIVERSION - HCIVERSION
93341  */
93342 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
93343 /*! @} */
93344 
93345 /*! @name HCSPARAMS - Host Controller Structural Parameters */
93346 /*! @{ */
93347 
93348 #define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
93349 #define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
93350 /*! N_PORTS - N_PORTS
93351  */
93352 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
93353 
93354 #define USB_HCSPARAMS_PPC_MASK                   (0x10U)
93355 #define USB_HCSPARAMS_PPC_SHIFT                  (4U)
93356 /*! PPC - PPC
93357  */
93358 #define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
93359 
93360 #define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
93361 #define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
93362 /*! N_PCC - N_PCC
93363  */
93364 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
93365 
93366 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
93367 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
93368 /*! N_CC - N_CC
93369  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
93370  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
93371  */
93372 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
93373 
93374 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
93375 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
93376 /*! PI - PI
93377  */
93378 #define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
93379 
93380 #define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
93381 #define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
93382 /*! N_PTT - N_PTT
93383  */
93384 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
93385 
93386 #define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
93387 #define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
93388 /*! N_TT - N_TT
93389  */
93390 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
93391 /*! @} */
93392 
93393 /*! @name HCCPARAMS - Host Controller Capability Parameters */
93394 /*! @{ */
93395 
93396 #define USB_HCCPARAMS_ADC_MASK                   (0x1U)
93397 #define USB_HCCPARAMS_ADC_SHIFT                  (0U)
93398 /*! ADC - ADC
93399  */
93400 #define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
93401 
93402 #define USB_HCCPARAMS_PFL_MASK                   (0x2U)
93403 #define USB_HCCPARAMS_PFL_SHIFT                  (1U)
93404 /*! PFL - PFL
93405  */
93406 #define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
93407 
93408 #define USB_HCCPARAMS_ASP_MASK                   (0x4U)
93409 #define USB_HCCPARAMS_ASP_SHIFT                  (2U)
93410 /*! ASP - ASP
93411  */
93412 #define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
93413 
93414 #define USB_HCCPARAMS_IST_MASK                   (0xF0U)
93415 #define USB_HCCPARAMS_IST_SHIFT                  (4U)
93416 /*! IST - IST
93417  */
93418 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
93419 
93420 #define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
93421 #define USB_HCCPARAMS_EECP_SHIFT                 (8U)
93422 /*! EECP - EECP
93423  */
93424 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
93425 /*! @} */
93426 
93427 /*! @name DCIVERSION - Device Controller Interface Version */
93428 /*! @{ */
93429 
93430 #define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
93431 #define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
93432 /*! DCIVERSION - DCIVERSION
93433  */
93434 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
93435 /*! @} */
93436 
93437 /*! @name DCCPARAMS - Device Controller Capability Parameters */
93438 /*! @{ */
93439 
93440 #define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
93441 #define USB_DCCPARAMS_DEN_SHIFT                  (0U)
93442 /*! DEN - DEN
93443  */
93444 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
93445 
93446 #define USB_DCCPARAMS_DC_MASK                    (0x80U)
93447 #define USB_DCCPARAMS_DC_SHIFT                   (7U)
93448 /*! DC - DC
93449  */
93450 #define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
93451 
93452 #define USB_DCCPARAMS_HC_MASK                    (0x100U)
93453 #define USB_DCCPARAMS_HC_SHIFT                   (8U)
93454 /*! HC - HC
93455  */
93456 #define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
93457 /*! @} */
93458 
93459 /*! @name USBCMD - USB Command Register */
93460 /*! @{ */
93461 
93462 #define USB_USBCMD_RS_MASK                       (0x1U)
93463 #define USB_USBCMD_RS_SHIFT                      (0U)
93464 /*! RS - RS
93465  */
93466 #define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
93467 
93468 #define USB_USBCMD_RST_MASK                      (0x2U)
93469 #define USB_USBCMD_RST_SHIFT                     (1U)
93470 /*! RST - RST
93471  */
93472 #define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
93473 
93474 #define USB_USBCMD_FS_1_MASK                     (0xCU)
93475 #define USB_USBCMD_FS_1_SHIFT                    (2U)
93476 /*! FS_1 - FS_1
93477  */
93478 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
93479 
93480 #define USB_USBCMD_PSE_MASK                      (0x10U)
93481 #define USB_USBCMD_PSE_SHIFT                     (4U)
93482 /*! PSE - PSE
93483  *  0b0..Do not process the Periodic Schedule
93484  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
93485  */
93486 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
93487 
93488 #define USB_USBCMD_ASE_MASK                      (0x20U)
93489 #define USB_USBCMD_ASE_SHIFT                     (5U)
93490 /*! ASE - ASE
93491  *  0b0..Do not process the Asynchronous Schedule.
93492  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
93493  */
93494 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
93495 
93496 #define USB_USBCMD_IAA_MASK                      (0x40U)
93497 #define USB_USBCMD_IAA_SHIFT                     (6U)
93498 /*! IAA - IAA
93499  */
93500 #define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
93501 
93502 #define USB_USBCMD_ASP_MASK                      (0x300U)
93503 #define USB_USBCMD_ASP_SHIFT                     (8U)
93504 /*! ASP - ASP
93505  */
93506 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
93507 
93508 #define USB_USBCMD_ASPE_MASK                     (0x800U)
93509 #define USB_USBCMD_ASPE_SHIFT                    (11U)
93510 /*! ASPE - ASPE
93511  */
93512 #define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
93513 
93514 #define USB_USBCMD_SUTW_MASK                     (0x2000U)
93515 #define USB_USBCMD_SUTW_SHIFT                    (13U)
93516 /*! SUTW - SUTW
93517  */
93518 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
93519 
93520 #define USB_USBCMD_ATDTW_MASK                    (0x4000U)
93521 #define USB_USBCMD_ATDTW_SHIFT                   (14U)
93522 /*! ATDTW - ATDTW
93523  */
93524 #define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
93525 
93526 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
93527 #define USB_USBCMD_FS_2_SHIFT                    (15U)
93528 /*! FS_2 - FS_2
93529  */
93530 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
93531 
93532 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
93533 #define USB_USBCMD_ITC_SHIFT                     (16U)
93534 /*! ITC - ITC
93535  *  0b00000000..Immediate (no threshold)
93536  *  0b00000001..1 micro-frame
93537  *  0b00000010..2 micro-frames
93538  *  0b00000100..4 micro-frames
93539  *  0b00001000..8 micro-frames
93540  *  0b00010000..16 micro-frames
93541  *  0b00100000..32 micro-frames
93542  *  0b01000000..64 micro-frames
93543  */
93544 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
93545 /*! @} */
93546 
93547 /*! @name USBSTS - USB Status Register */
93548 /*! @{ */
93549 
93550 #define USB_USBSTS_UI_MASK                       (0x1U)
93551 #define USB_USBSTS_UI_SHIFT                      (0U)
93552 /*! UI - UI
93553  */
93554 #define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
93555 
93556 #define USB_USBSTS_UEI_MASK                      (0x2U)
93557 #define USB_USBSTS_UEI_SHIFT                     (1U)
93558 /*! UEI - UEI
93559  */
93560 #define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
93561 
93562 #define USB_USBSTS_PCI_MASK                      (0x4U)
93563 #define USB_USBSTS_PCI_SHIFT                     (2U)
93564 /*! PCI - PCI
93565  */
93566 #define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
93567 
93568 #define USB_USBSTS_FRI_MASK                      (0x8U)
93569 #define USB_USBSTS_FRI_SHIFT                     (3U)
93570 /*! FRI - FRI
93571  */
93572 #define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
93573 
93574 #define USB_USBSTS_SEI_MASK                      (0x10U)
93575 #define USB_USBSTS_SEI_SHIFT                     (4U)
93576 /*! SEI - SEI
93577  */
93578 #define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
93579 
93580 #define USB_USBSTS_AAI_MASK                      (0x20U)
93581 #define USB_USBSTS_AAI_SHIFT                     (5U)
93582 /*! AAI - AAI
93583  */
93584 #define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
93585 
93586 #define USB_USBSTS_URI_MASK                      (0x40U)
93587 #define USB_USBSTS_URI_SHIFT                     (6U)
93588 /*! URI - URI
93589  */
93590 #define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
93591 
93592 #define USB_USBSTS_SRI_MASK                      (0x80U)
93593 #define USB_USBSTS_SRI_SHIFT                     (7U)
93594 /*! SRI - SRI
93595  */
93596 #define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
93597 
93598 #define USB_USBSTS_SLI_MASK                      (0x100U)
93599 #define USB_USBSTS_SLI_SHIFT                     (8U)
93600 /*! SLI - SLI
93601  */
93602 #define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
93603 
93604 #define USB_USBSTS_ULPII_MASK                    (0x400U)
93605 #define USB_USBSTS_ULPII_SHIFT                   (10U)
93606 /*! ULPII - ULPII
93607  */
93608 #define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
93609 
93610 #define USB_USBSTS_HCH_MASK                      (0x1000U)
93611 #define USB_USBSTS_HCH_SHIFT                     (12U)
93612 /*! HCH - HCH
93613  */
93614 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
93615 
93616 #define USB_USBSTS_RCL_MASK                      (0x2000U)
93617 #define USB_USBSTS_RCL_SHIFT                     (13U)
93618 /*! RCL - RCL
93619  */
93620 #define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
93621 
93622 #define USB_USBSTS_PS_MASK                       (0x4000U)
93623 #define USB_USBSTS_PS_SHIFT                      (14U)
93624 /*! PS - PS
93625  */
93626 #define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
93627 
93628 #define USB_USBSTS_AS_MASK                       (0x8000U)
93629 #define USB_USBSTS_AS_SHIFT                      (15U)
93630 /*! AS - AS
93631  */
93632 #define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
93633 
93634 #define USB_USBSTS_NAKI_MASK                     (0x10000U)
93635 #define USB_USBSTS_NAKI_SHIFT                    (16U)
93636 /*! NAKI - NAKI
93637  */
93638 #define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
93639 
93640 #define USB_USBSTS_TI0_MASK                      (0x1000000U)
93641 #define USB_USBSTS_TI0_SHIFT                     (24U)
93642 /*! TI0 - TI0
93643  */
93644 #define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
93645 
93646 #define USB_USBSTS_TI1_MASK                      (0x2000000U)
93647 #define USB_USBSTS_TI1_SHIFT                     (25U)
93648 /*! TI1 - TI1
93649  */
93650 #define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
93651 /*! @} */
93652 
93653 /*! @name USBINTR - Interrupt Enable Register */
93654 /*! @{ */
93655 
93656 #define USB_USBINTR_UE_MASK                      (0x1U)
93657 #define USB_USBINTR_UE_SHIFT                     (0U)
93658 /*! UE - UE
93659  */
93660 #define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
93661 
93662 #define USB_USBINTR_UEE_MASK                     (0x2U)
93663 #define USB_USBINTR_UEE_SHIFT                    (1U)
93664 /*! UEE - UEE
93665  */
93666 #define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
93667 
93668 #define USB_USBINTR_PCE_MASK                     (0x4U)
93669 #define USB_USBINTR_PCE_SHIFT                    (2U)
93670 /*! PCE - PCE
93671  */
93672 #define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
93673 
93674 #define USB_USBINTR_FRE_MASK                     (0x8U)
93675 #define USB_USBINTR_FRE_SHIFT                    (3U)
93676 /*! FRE - FRE
93677  */
93678 #define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
93679 
93680 #define USB_USBINTR_SEE_MASK                     (0x10U)
93681 #define USB_USBINTR_SEE_SHIFT                    (4U)
93682 /*! SEE - SEE
93683  */
93684 #define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
93685 
93686 #define USB_USBINTR_AAE_MASK                     (0x20U)
93687 #define USB_USBINTR_AAE_SHIFT                    (5U)
93688 /*! AAE - AAE
93689  */
93690 #define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
93691 
93692 #define USB_USBINTR_URE_MASK                     (0x40U)
93693 #define USB_USBINTR_URE_SHIFT                    (6U)
93694 /*! URE - URE
93695  */
93696 #define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
93697 
93698 #define USB_USBINTR_SRE_MASK                     (0x80U)
93699 #define USB_USBINTR_SRE_SHIFT                    (7U)
93700 /*! SRE - SRE
93701  */
93702 #define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
93703 
93704 #define USB_USBINTR_SLE_MASK                     (0x100U)
93705 #define USB_USBINTR_SLE_SHIFT                    (8U)
93706 /*! SLE - SLE
93707  */
93708 #define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
93709 
93710 #define USB_USBINTR_ULPIE_MASK                   (0x400U)
93711 #define USB_USBINTR_ULPIE_SHIFT                  (10U)
93712 /*! ULPIE - ULPIE
93713  */
93714 #define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
93715 
93716 #define USB_USBINTR_NAKE_MASK                    (0x10000U)
93717 #define USB_USBINTR_NAKE_SHIFT                   (16U)
93718 /*! NAKE - NAKE
93719  */
93720 #define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
93721 
93722 #define USB_USBINTR_UAIE_MASK                    (0x40000U)
93723 #define USB_USBINTR_UAIE_SHIFT                   (18U)
93724 /*! UAIE - UAIE
93725  */
93726 #define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
93727 
93728 #define USB_USBINTR_UPIE_MASK                    (0x80000U)
93729 #define USB_USBINTR_UPIE_SHIFT                   (19U)
93730 /*! UPIE - UPIE
93731  */
93732 #define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
93733 
93734 #define USB_USBINTR_TIE0_MASK                    (0x1000000U)
93735 #define USB_USBINTR_TIE0_SHIFT                   (24U)
93736 /*! TIE0 - TIE0
93737  */
93738 #define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
93739 
93740 #define USB_USBINTR_TIE1_MASK                    (0x2000000U)
93741 #define USB_USBINTR_TIE1_SHIFT                   (25U)
93742 /*! TIE1 - TIE1
93743  */
93744 #define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
93745 /*! @} */
93746 
93747 /*! @name FRINDEX - USB Frame Index */
93748 /*! @{ */
93749 
93750 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
93751 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
93752 /*! FRINDEX - FRINDEX
93753  *  0b00000000000000..(1024) 12
93754  *  0b00000000000001..(512) 11
93755  *  0b00000000000010..(256) 10
93756  *  0b00000000000011..(128) 9
93757  *  0b00000000000100..(64) 8
93758  *  0b00000000000101..(32) 7
93759  *  0b00000000000110..(16) 6
93760  *  0b00000000000111..(8) 5
93761  */
93762 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
93763 /*! @} */
93764 
93765 /*! @name DEVICEADDR - Device Address */
93766 /*! @{ */
93767 
93768 #define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
93769 #define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
93770 /*! USBADRA - USBADRA
93771  */
93772 #define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
93773 
93774 #define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
93775 #define USB_DEVICEADDR_USBADR_SHIFT              (25U)
93776 /*! USBADR - USBADR
93777  */
93778 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
93779 /*! @} */
93780 
93781 /*! @name PERIODICLISTBASE - Frame List Base Address */
93782 /*! @{ */
93783 
93784 #define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
93785 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
93786 /*! BASEADR - BASEADR
93787  */
93788 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
93789 /*! @} */
93790 
93791 /*! @name ASYNCLISTADDR - Next Asynch. Address */
93792 /*! @{ */
93793 
93794 #define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
93795 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
93796 /*! ASYBASE - ASYBASE
93797  */
93798 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
93799 /*! @} */
93800 
93801 /*! @name ENDPTLISTADDR - Endpoint List Address */
93802 /*! @{ */
93803 
93804 #define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
93805 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
93806 /*! EPBASE - EPBASE
93807  */
93808 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
93809 /*! @} */
93810 
93811 /*! @name BURSTSIZE - Programmable Burst Size */
93812 /*! @{ */
93813 
93814 #define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
93815 #define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
93816 /*! RXPBURST - RXPBURST
93817  */
93818 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
93819 
93820 #define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
93821 #define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
93822 /*! TXPBURST - TXPBURST
93823  */
93824 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
93825 /*! @} */
93826 
93827 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
93828 /*! @{ */
93829 
93830 #define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
93831 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
93832 /*! TXSCHOH - TXSCHOH
93833  */
93834 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
93835 
93836 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
93837 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
93838 /*! TXSCHHEALTH - TXSCHHEALTH
93839  */
93840 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
93841 
93842 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
93843 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
93844 /*! TXFIFOTHRES - TXFIFOTHRES
93845  */
93846 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
93847 /*! @} */
93848 
93849 /*! @name ENDPTNAK - Endpoint NAK */
93850 /*! @{ */
93851 
93852 #define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
93853 #define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
93854 /*! EPRN - EPRN
93855  */
93856 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
93857 
93858 #define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
93859 #define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
93860 /*! EPTN - EPTN
93861  */
93862 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
93863 /*! @} */
93864 
93865 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
93866 /*! @{ */
93867 
93868 #define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
93869 #define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
93870 /*! EPRNE - EPRNE
93871  */
93872 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
93873 
93874 #define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
93875 #define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
93876 /*! EPTNE - EPTNE
93877  */
93878 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
93879 /*! @} */
93880 
93881 /*! @name CONFIGFLAG - Configure Flag Register */
93882 /*! @{ */
93883 
93884 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
93885 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
93886 /*! CF - CF
93887  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
93888  *  0b1..Port routing control logic default-routes all ports to this host controller.
93889  */
93890 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
93891 /*! @} */
93892 
93893 /*! @name PORTSC1 - Port Status & Control */
93894 /*! @{ */
93895 
93896 #define USB_PORTSC1_CCS_MASK                     (0x1U)
93897 #define USB_PORTSC1_CCS_SHIFT                    (0U)
93898 /*! CCS - CCS
93899  */
93900 #define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
93901 
93902 #define USB_PORTSC1_CSC_MASK                     (0x2U)
93903 #define USB_PORTSC1_CSC_SHIFT                    (1U)
93904 /*! CSC - CSC
93905  */
93906 #define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
93907 
93908 #define USB_PORTSC1_PE_MASK                      (0x4U)
93909 #define USB_PORTSC1_PE_SHIFT                     (2U)
93910 /*! PE - PE
93911  */
93912 #define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
93913 
93914 #define USB_PORTSC1_PEC_MASK                     (0x8U)
93915 #define USB_PORTSC1_PEC_SHIFT                    (3U)
93916 /*! PEC - PEC
93917  */
93918 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
93919 
93920 #define USB_PORTSC1_OCA_MASK                     (0x10U)
93921 #define USB_PORTSC1_OCA_SHIFT                    (4U)
93922 /*! OCA - OCA
93923  *  0b1..This port currently has an over-current condition
93924  *  0b0..This port does not have an over-current condition.
93925  */
93926 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
93927 
93928 #define USB_PORTSC1_OCC_MASK                     (0x20U)
93929 #define USB_PORTSC1_OCC_SHIFT                    (5U)
93930 /*! OCC - OCC
93931  */
93932 #define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
93933 
93934 #define USB_PORTSC1_FPR_MASK                     (0x40U)
93935 #define USB_PORTSC1_FPR_SHIFT                    (6U)
93936 /*! FPR - FPR
93937  */
93938 #define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
93939 
93940 #define USB_PORTSC1_SUSP_MASK                    (0x80U)
93941 #define USB_PORTSC1_SUSP_SHIFT                   (7U)
93942 /*! SUSP - SUSP
93943  */
93944 #define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
93945 
93946 #define USB_PORTSC1_PR_MASK                      (0x100U)
93947 #define USB_PORTSC1_PR_SHIFT                     (8U)
93948 /*! PR - PR
93949  */
93950 #define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
93951 
93952 #define USB_PORTSC1_HSP_MASK                     (0x200U)
93953 #define USB_PORTSC1_HSP_SHIFT                    (9U)
93954 /*! HSP - HSP
93955  */
93956 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
93957 
93958 #define USB_PORTSC1_LS_MASK                      (0xC00U)
93959 #define USB_PORTSC1_LS_SHIFT                     (10U)
93960 /*! LS - LS
93961  *  0b00..SE0
93962  *  0b10..J-state
93963  *  0b01..K-state
93964  *  0b11..Undefined
93965  */
93966 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
93967 
93968 #define USB_PORTSC1_PP_MASK                      (0x1000U)
93969 #define USB_PORTSC1_PP_SHIFT                     (12U)
93970 /*! PP - PP
93971  */
93972 #define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
93973 
93974 #define USB_PORTSC1_PO_MASK                      (0x2000U)
93975 #define USB_PORTSC1_PO_SHIFT                     (13U)
93976 /*! PO - PO
93977  */
93978 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
93979 
93980 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
93981 #define USB_PORTSC1_PIC_SHIFT                    (14U)
93982 /*! PIC - PIC
93983  *  0b00..Port indicators are off
93984  *  0b01..Amber
93985  *  0b10..Green
93986  *  0b11..Undefined
93987  */
93988 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
93989 
93990 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
93991 #define USB_PORTSC1_PTC_SHIFT                    (16U)
93992 /*! PTC - PTC
93993  *  0b0000..TEST_MODE_DISABLE
93994  *  0b0001..J_STATE
93995  *  0b0010..K_STATE
93996  *  0b0011..SE0 (host) / NAK (device)
93997  *  0b0100..Packet
93998  *  0b0101..FORCE_ENABLE_HS
93999  *  0b0110..FORCE_ENABLE_FS
94000  *  0b0111..FORCE_ENABLE_LS
94001  *  0b1000-0b1111..Reserved
94002  */
94003 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
94004 
94005 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
94006 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
94007 /*! WKCN - WKCN
94008  */
94009 #define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
94010 
94011 #define USB_PORTSC1_WKDC_MASK                    (0x200000U)
94012 #define USB_PORTSC1_WKDC_SHIFT                   (21U)
94013 /*! WKDC - WKDC
94014  */
94015 #define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
94016 
94017 #define USB_PORTSC1_WKOC_MASK                    (0x400000U)
94018 #define USB_PORTSC1_WKOC_SHIFT                   (22U)
94019 /*! WKOC - WKOC
94020  */
94021 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
94022 
94023 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
94024 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
94025 /*! PHCD - PHCD
94026  *  0b1..Disable PHY clock
94027  *  0b0..Enable PHY clock
94028  */
94029 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
94030 
94031 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
94032 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
94033 /*! PFSC - PFSC
94034  *  0b1..Forced to full speed
94035  *  0b0..Normal operation
94036  */
94037 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
94038 
94039 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
94040 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
94041 /*! PTS_2 - PTS_2
94042  */
94043 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
94044 
94045 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
94046 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
94047 /*! PSPD - PSPD
94048  *  0b00..Full Speed
94049  *  0b01..Low Speed
94050  *  0b10..High Speed
94051  *  0b11..Undefined
94052  */
94053 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
94054 
94055 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
94056 #define USB_PORTSC1_PTW_SHIFT                    (28U)
94057 /*! PTW - PTW
94058  *  0b0..Select the 8-bit UTMI interface [60MHz]
94059  *  0b1..Select the 16-bit UTMI interface [30MHz]
94060  */
94061 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
94062 
94063 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
94064 #define USB_PORTSC1_STS_SHIFT                    (29U)
94065 /*! STS - STS
94066  */
94067 #define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
94068 
94069 #define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
94070 #define USB_PORTSC1_PTS_1_SHIFT                  (30U)
94071 /*! PTS_1 - PTS_1
94072  */
94073 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
94074 /*! @} */
94075 
94076 /*! @name OTGSC - On-The-Go Status & control */
94077 /*! @{ */
94078 
94079 #define USB_OTGSC_VD_MASK                        (0x1U)
94080 #define USB_OTGSC_VD_SHIFT                       (0U)
94081 /*! VD - VD
94082  */
94083 #define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
94084 
94085 #define USB_OTGSC_VC_MASK                        (0x2U)
94086 #define USB_OTGSC_VC_SHIFT                       (1U)
94087 /*! VC - VC
94088  */
94089 #define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
94090 
94091 #define USB_OTGSC_OT_MASK                        (0x8U)
94092 #define USB_OTGSC_OT_SHIFT                       (3U)
94093 /*! OT - OT
94094  */
94095 #define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
94096 
94097 #define USB_OTGSC_DP_MASK                        (0x10U)
94098 #define USB_OTGSC_DP_SHIFT                       (4U)
94099 /*! DP - DP
94100  */
94101 #define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
94102 
94103 #define USB_OTGSC_IDPU_MASK                      (0x20U)
94104 #define USB_OTGSC_IDPU_SHIFT                     (5U)
94105 /*! IDPU - IDPU
94106  */
94107 #define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
94108 
94109 #define USB_OTGSC_ID_MASK                        (0x100U)
94110 #define USB_OTGSC_ID_SHIFT                       (8U)
94111 /*! ID - ID
94112  */
94113 #define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
94114 
94115 #define USB_OTGSC_AVV_MASK                       (0x200U)
94116 #define USB_OTGSC_AVV_SHIFT                      (9U)
94117 /*! AVV - AVV
94118  */
94119 #define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
94120 
94121 #define USB_OTGSC_ASV_MASK                       (0x400U)
94122 #define USB_OTGSC_ASV_SHIFT                      (10U)
94123 /*! ASV - ASV
94124  */
94125 #define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
94126 
94127 #define USB_OTGSC_BSV_MASK                       (0x800U)
94128 #define USB_OTGSC_BSV_SHIFT                      (11U)
94129 /*! BSV - BSV
94130  */
94131 #define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
94132 
94133 #define USB_OTGSC_BSE_MASK                       (0x1000U)
94134 #define USB_OTGSC_BSE_SHIFT                      (12U)
94135 /*! BSE - BSE
94136  */
94137 #define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
94138 
94139 #define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
94140 #define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
94141 /*! TOG_1MS - TOG_1MS
94142  */
94143 #define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
94144 
94145 #define USB_OTGSC_DPS_MASK                       (0x4000U)
94146 #define USB_OTGSC_DPS_SHIFT                      (14U)
94147 /*! DPS - DPS
94148  */
94149 #define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
94150 
94151 #define USB_OTGSC_IDIS_MASK                      (0x10000U)
94152 #define USB_OTGSC_IDIS_SHIFT                     (16U)
94153 /*! IDIS - IDIS
94154  */
94155 #define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
94156 
94157 #define USB_OTGSC_AVVIS_MASK                     (0x20000U)
94158 #define USB_OTGSC_AVVIS_SHIFT                    (17U)
94159 /*! AVVIS - AVVIS
94160  */
94161 #define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
94162 
94163 #define USB_OTGSC_ASVIS_MASK                     (0x40000U)
94164 #define USB_OTGSC_ASVIS_SHIFT                    (18U)
94165 /*! ASVIS - ASVIS
94166  */
94167 #define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
94168 
94169 #define USB_OTGSC_BSVIS_MASK                     (0x80000U)
94170 #define USB_OTGSC_BSVIS_SHIFT                    (19U)
94171 /*! BSVIS - BSVIS
94172  */
94173 #define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
94174 
94175 #define USB_OTGSC_BSEIS_MASK                     (0x100000U)
94176 #define USB_OTGSC_BSEIS_SHIFT                    (20U)
94177 /*! BSEIS - BSEIS
94178  */
94179 #define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
94180 
94181 #define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
94182 #define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
94183 /*! STATUS_1MS - STATUS_1MS
94184  */
94185 #define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
94186 
94187 #define USB_OTGSC_DPIS_MASK                      (0x400000U)
94188 #define USB_OTGSC_DPIS_SHIFT                     (22U)
94189 /*! DPIS - DPIS
94190  */
94191 #define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
94192 
94193 #define USB_OTGSC_IDIE_MASK                      (0x1000000U)
94194 #define USB_OTGSC_IDIE_SHIFT                     (24U)
94195 /*! IDIE - IDIE
94196  */
94197 #define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
94198 
94199 #define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
94200 #define USB_OTGSC_AVVIE_SHIFT                    (25U)
94201 /*! AVVIE - AVVIE
94202  */
94203 #define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
94204 
94205 #define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
94206 #define USB_OTGSC_ASVIE_SHIFT                    (26U)
94207 /*! ASVIE - ASVIE
94208  */
94209 #define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
94210 
94211 #define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
94212 #define USB_OTGSC_BSVIE_SHIFT                    (27U)
94213 /*! BSVIE - BSVIE
94214  */
94215 #define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
94216 
94217 #define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
94218 #define USB_OTGSC_BSEIE_SHIFT                    (28U)
94219 /*! BSEIE - BSEIE
94220  */
94221 #define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
94222 
94223 #define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
94224 #define USB_OTGSC_EN_1MS_SHIFT                   (29U)
94225 /*! EN_1MS - EN_1MS
94226  */
94227 #define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
94228 
94229 #define USB_OTGSC_DPIE_MASK                      (0x40000000U)
94230 #define USB_OTGSC_DPIE_SHIFT                     (30U)
94231 /*! DPIE - DPIE
94232  */
94233 #define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
94234 /*! @} */
94235 
94236 /*! @name USBMODE - USB Device Mode */
94237 /*! @{ */
94238 
94239 #define USB_USBMODE_CM_MASK                      (0x3U)
94240 #define USB_USBMODE_CM_SHIFT                     (0U)
94241 /*! CM - CM
94242  *  0b00..Idle [Default for combination host/device]
94243  *  0b01..Reserved
94244  *  0b10..Device Controller [Default for device only controller]
94245  *  0b11..Host Controller [Default for host only controller]
94246  */
94247 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
94248 
94249 #define USB_USBMODE_ES_MASK                      (0x4U)
94250 #define USB_USBMODE_ES_SHIFT                     (2U)
94251 /*! ES - ES
94252  *  0b0..Little Endian [Default]
94253  *  0b1..Big Endian
94254  */
94255 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
94256 
94257 #define USB_USBMODE_SLOM_MASK                    (0x8U)
94258 #define USB_USBMODE_SLOM_SHIFT                   (3U)
94259 /*! SLOM - SLOM
94260  *  0b0..Setup Lockouts On (default);
94261  *  0b1..Setup Lockouts Off
94262  */
94263 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
94264 
94265 #define USB_USBMODE_SDIS_MASK                    (0x10U)
94266 #define USB_USBMODE_SDIS_SHIFT                   (4U)
94267 /*! SDIS - SDIS
94268  */
94269 #define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
94270 /*! @} */
94271 
94272 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
94273 /*! @{ */
94274 
94275 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
94276 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
94277 /*! ENDPTSETUPSTAT - ENDPTSETUPSTAT
94278  */
94279 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
94280 /*! @} */
94281 
94282 /*! @name ENDPTPRIME - Endpoint Prime */
94283 /*! @{ */
94284 
94285 #define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
94286 #define USB_ENDPTPRIME_PERB_SHIFT                (0U)
94287 /*! PERB - PERB
94288  */
94289 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
94290 
94291 #define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
94292 #define USB_ENDPTPRIME_PETB_SHIFT                (16U)
94293 /*! PETB - PETB
94294  */
94295 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
94296 /*! @} */
94297 
94298 /*! @name ENDPTFLUSH - Endpoint Flush */
94299 /*! @{ */
94300 
94301 #define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
94302 #define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
94303 /*! FERB - FERB
94304  */
94305 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
94306 
94307 #define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
94308 #define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
94309 /*! FETB - FETB
94310  */
94311 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
94312 /*! @} */
94313 
94314 /*! @name ENDPTSTAT - Endpoint Status */
94315 /*! @{ */
94316 
94317 #define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
94318 #define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
94319 /*! ERBR - ERBR
94320  */
94321 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
94322 
94323 #define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
94324 #define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
94325 /*! ETBR - ETBR
94326  */
94327 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
94328 /*! @} */
94329 
94330 /*! @name ENDPTCOMPLETE - Endpoint Complete */
94331 /*! @{ */
94332 
94333 #define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
94334 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
94335 /*! ERCE - ERCE
94336  */
94337 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
94338 
94339 #define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
94340 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
94341 /*! ETCE - ETCE
94342  */
94343 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
94344 /*! @} */
94345 
94346 /*! @name ENDPTCTRL0 - Endpoint Control0 */
94347 /*! @{ */
94348 
94349 #define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
94350 #define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
94351 /*! RXS - RXS
94352  */
94353 #define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
94354 
94355 #define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
94356 #define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
94357 /*! RXT - RXT
94358  */
94359 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
94360 
94361 #define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
94362 #define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
94363 /*! RXE - RXE
94364  */
94365 #define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
94366 
94367 #define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
94368 #define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
94369 /*! TXS - TXS
94370  */
94371 #define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
94372 
94373 #define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
94374 #define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
94375 /*! TXT - TXT
94376  */
94377 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
94378 
94379 #define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
94380 #define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
94381 /*! TXE - TXE
94382  */
94383 #define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
94384 /*! @} */
94385 
94386 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
94387 /*! @{ */
94388 
94389 #define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
94390 #define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
94391 /*! RXS - RXS
94392  */
94393 #define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
94394 
94395 #define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
94396 #define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
94397 /*! RXD - RXD
94398  */
94399 #define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
94400 
94401 #define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
94402 #define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
94403 /*! RXT - RXT
94404  */
94405 #define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
94406 
94407 #define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
94408 #define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
94409 /*! RXI - RXI
94410  */
94411 #define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
94412 
94413 #define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
94414 #define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
94415 /*! RXR - RXR
94416  */
94417 #define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
94418 
94419 #define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
94420 #define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
94421 /*! RXE - RXE
94422  */
94423 #define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
94424 
94425 #define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
94426 #define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
94427 /*! TXS - TXS
94428  */
94429 #define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
94430 
94431 #define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
94432 #define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
94433 /*! TXD - TXD
94434  */
94435 #define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
94436 
94437 #define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
94438 #define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
94439 /*! TXT - TXT
94440  */
94441 #define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
94442 
94443 #define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
94444 #define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
94445 /*! TXI - TXI
94446  */
94447 #define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
94448 
94449 #define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
94450 #define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
94451 /*! TXR - TXR
94452  */
94453 #define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
94454 
94455 #define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
94456 #define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
94457 /*! TXE - TXE
94458  */
94459 #define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
94460 /*! @} */
94461 
94462 /* The count of USB_ENDPTCTRL */
94463 #define USB_ENDPTCTRL_COUNT                      (7U)
94464 
94465 
94466 /*!
94467  * @}
94468  */ /* end of group USB_Register_Masks */
94469 
94470 
94471 /* USB - Peripheral instance base addresses */
94472 /** Peripheral USB_OTG1 base address */
94473 #define USB_OTG1_BASE                            (0x40430000u)
94474 /** Peripheral USB_OTG1 base pointer */
94475 #define USB_OTG1                                 ((USB_Type *)USB_OTG1_BASE)
94476 /** Peripheral USB_OTG2 base address */
94477 #define USB_OTG2_BASE                            (0x4042C000u)
94478 /** Peripheral USB_OTG2 base pointer */
94479 #define USB_OTG2                                 ((USB_Type *)USB_OTG2_BASE)
94480 /** Array initializer of USB peripheral base addresses */
94481 #define USB_BASE_ADDRS                           { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
94482 /** Array initializer of USB peripheral base pointers */
94483 #define USB_BASE_PTRS                            { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
94484 /** Interrupt vectors for the USB peripheral type */
94485 #define USB_IRQS                                 { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
94486 /* Backward compatibility */
94487 #define GPTIMER0CTL                              GPTIMER0CTRL
94488 #define GPTIMER1CTL                              GPTIMER1CTRL
94489 #define USB_SBUSCFG                              SBUSCFG
94490 #define EPLISTADDR                               ENDPTLISTADDR
94491 #define EPSETUPSR                                ENDPTSETUPSTAT
94492 #define EPPRIME                                  ENDPTPRIME
94493 #define EPFLUSH                                  ENDPTFLUSH
94494 #define EPSR                                     ENDPTSTAT
94495 #define EPCOMPLETE                               ENDPTCOMPLETE
94496 #define EPCR                                     ENDPTCTRL
94497 #define EPCR0                                    ENDPTCTRL0
94498 #define USBHS_ID_ID_MASK                         USB_ID_ID_MASK
94499 #define USBHS_ID_ID_SHIFT                        USB_ID_ID_SHIFT
94500 #define USBHS_ID_ID(x)                           USB_ID_ID(x)
94501 #define USBHS_ID_NID_MASK                        USB_ID_NID_MASK
94502 #define USBHS_ID_NID_SHIFT                       USB_ID_NID_SHIFT
94503 #define USBHS_ID_NID(x)                          USB_ID_NID(x)
94504 #define USBHS_ID_REVISION_MASK                   USB_ID_REVISION_MASK
94505 #define USBHS_ID_REVISION_SHIFT                  USB_ID_REVISION_SHIFT
94506 #define USBHS_ID_REVISION(x)                     USB_ID_REVISION(x)
94507 #define USBHS_HWGENERAL_PHYW_MASK                USB_HWGENERAL_PHYW_MASK
94508 #define USBHS_HWGENERAL_PHYW_SHIFT               USB_HWGENERAL_PHYW_SHIFT
94509 #define USBHS_HWGENERAL_PHYW(x)                  USB_HWGENERAL_PHYW(x)
94510 #define USBHS_HWGENERAL_PHYM_MASK                USB_HWGENERAL_PHYM_MASK
94511 #define USBHS_HWGENERAL_PHYM_SHIFT               USB_HWGENERAL_PHYM_SHIFT
94512 #define USBHS_HWGENERAL_PHYM(x)                  USB_HWGENERAL_PHYM(x)
94513 #define USBHS_HWGENERAL_SM_MASK                  USB_HWGENERAL_SM_MASK
94514 #define USBHS_HWGENERAL_SM_SHIFT                 USB_HWGENERAL_SM_SHIFT
94515 #define USBHS_HWGENERAL_SM(x)                    USB_HWGENERAL_SM(x)
94516 #define USBHS_HWHOST_HC_MASK                     USB_HWHOST_HC_MASK
94517 #define USBHS_HWHOST_HC_SHIFT                    USB_HWHOST_HC_SHIFT
94518 #define USBHS_HWHOST_HC(x)                       USB_HWHOST_HC(x)
94519 #define USBHS_HWHOST_NPORT_MASK                  USB_HWHOST_NPORT_MASK
94520 #define USBHS_HWHOST_NPORT_SHIFT                 USB_HWHOST_NPORT_SHIFT
94521 #define USBHS_HWHOST_NPORT(x)                    USB_HWHOST_NPORT(x)
94522 #define USBHS_HWDEVICE_DC_MASK                   USB_HWDEVICE_DC_MASK
94523 #define USBHS_HWDEVICE_DC_SHIFT                  USB_HWDEVICE_DC_SHIFT
94524 #define USBHS_HWDEVICE_DC(x)                     USB_HWDEVICE_DC(x)
94525 #define USBHS_HWDEVICE_DEVEP_MASK                USB_HWDEVICE_DEVEP_MASK
94526 #define USBHS_HWDEVICE_DEVEP_SHIFT               USB_HWDEVICE_DEVEP_SHIFT
94527 #define USBHS_HWDEVICE_DEVEP(x)                  USB_HWDEVICE_DEVEP(x)
94528 #define USBHS_HWTXBUF_TXBURST_MASK               USB_HWTXBUF_TXBURST_MASK
94529 #define USBHS_HWTXBUF_TXBURST_SHIFT              USB_HWTXBUF_TXBURST_SHIFT
94530 #define USBHS_HWTXBUF_TXBURST(x)                 USB_HWTXBUF_TXBURST(x)
94531 #define USBHS_HWTXBUF_TXCHANADD_MASK             USB_HWTXBUF_TXCHANADD_MASK
94532 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            USB_HWTXBUF_TXCHANADD_SHIFT
94533 #define USBHS_HWTXBUF_TXCHANADD(x)               USB_HWTXBUF_TXCHANADD(x)
94534 #define USBHS_HWRXBUF_RXBURST_MASK               USB_HWRXBUF_RXBURST_MASK
94535 #define USBHS_HWRXBUF_RXBURST_SHIFT              USB_HWRXBUF_RXBURST_SHIFT
94536 #define USBHS_HWRXBUF_RXBURST(x)                 USB_HWRXBUF_RXBURST(x)
94537 #define USBHS_HWRXBUF_RXADD_MASK                 USB_HWRXBUF_RXADD_MASK
94538 #define USBHS_HWRXBUF_RXADD_SHIFT                USB_HWRXBUF_RXADD_SHIFT
94539 #define USBHS_HWRXBUF_RXADD(x)                   USB_HWRXBUF_RXADD(x)
94540 #define USBHS_GPTIMER0LD_GPTLD_MASK              USB_GPTIMER0LD_GPTLD_MASK
94541 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             USB_GPTIMER0LD_GPTLD_SHIFT
94542 #define USBHS_GPTIMER0LD_GPTLD(x)                USB_GPTIMER0LD_GPTLD(x)
94543 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            USB_GPTIMER0CTRL_GPTCNT_MASK
94544 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USB_GPTIMER0CTRL_GPTCNT_SHIFT
94545 #define USBHS_GPTIMER0CTL_GPTCNT(x)              USB_GPTIMER0CTRL_GPTCNT(x)
94546 #define USBHS_GPTIMER0CTL_MODE_MASK              USB_GPTIMER0CTRL_GPTMODE_MASK
94547 #define USBHS_GPTIMER0CTL_MODE_SHIFT             USB_GPTIMER0CTRL_GPTMODE_SHIFT
94548 #define USBHS_GPTIMER0CTL_MODE(x)                USB_GPTIMER0CTRL_GPTMODE(x)
94549 #define USBHS_GPTIMER0CTL_RST_MASK               USB_GPTIMER0CTRL_GPTRST_MASK
94550 #define USBHS_GPTIMER0CTL_RST_SHIFT              USB_GPTIMER0CTRL_GPTRST_SHIFT
94551 #define USBHS_GPTIMER0CTL_RST(x)                 USB_GPTIMER0CTRL_GPTRST(x)
94552 #define USBHS_GPTIMER0CTL_RUN_MASK               USB_GPTIMER0CTRL_GPTRUN_MASK
94553 #define USBHS_GPTIMER0CTL_RUN_SHIFT              USB_GPTIMER0CTRL_GPTRUN_SHIFT
94554 #define USBHS_GPTIMER0CTL_RUN(x)                 USB_GPTIMER0CTRL_GPTRUN(x)
94555 #define USBHS_GPTIMER1LD_GPTLD_MASK              USB_GPTIMER1LD_GPTLD_MASK
94556 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             USB_GPTIMER1LD_GPTLD_SHIFT
94557 #define USBHS_GPTIMER1LD_GPTLD(x)                USB_GPTIMER1LD_GPTLD(x)
94558 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            USB_GPTIMER1CTRL_GPTCNT_MASK
94559 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USB_GPTIMER1CTRL_GPTCNT_SHIFT
94560 #define USBHS_GPTIMER1CTL_GPTCNT(x)              USB_GPTIMER1CTRL_GPTCNT(x)
94561 #define USBHS_GPTIMER1CTL_MODE_MASK              USB_GPTIMER1CTRL_GPTMODE_MASK
94562 #define USBHS_GPTIMER1CTL_MODE_SHIFT             USB_GPTIMER1CTRL_GPTMODE_SHIFT
94563 #define USBHS_GPTIMER1CTL_MODE(x)                USB_GPTIMER1CTRL_GPTMODE(x)
94564 #define USBHS_GPTIMER1CTL_RST_MASK               USB_GPTIMER1CTRL_GPTRST_MASK
94565 #define USBHS_GPTIMER1CTL_RST_SHIFT              USB_GPTIMER1CTRL_GPTRST_SHIFT
94566 #define USBHS_GPTIMER1CTL_RST(x)                 USB_GPTIMER1CTRL_GPTRST(x)
94567 #define USBHS_GPTIMER1CTL_RUN_MASK               USB_GPTIMER1CTRL_GPTRUN_MASK
94568 #define USBHS_GPTIMER1CTL_RUN_SHIFT              USB_GPTIMER1CTRL_GPTRUN_SHIFT
94569 #define USBHS_GPTIMER1CTL_RUN(x)                 USB_GPTIMER1CTRL_GPTRUN(x)
94570 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USB_SBUSCFG_AHBBRST_MASK
94571 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USB_SBUSCFG_AHBBRST_SHIFT
94572 #define USBHS_USB_SBUSCFG_BURSTMODE(x)           USB_SBUSCFG_AHBBRST(x)
94573 #define USBHS_HCIVERSION_CAPLENGTH(x)            USB_HCIVERSION_CAPLENGTH(x)
94574 #define USBHS_HCIVERSION_HCIVERSION_MASK         USB_HCIVERSION_HCIVERSION_MASK
94575 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        USB_HCIVERSION_HCIVERSION_SHIFT
94576 #define USBHS_HCIVERSION_HCIVERSION(x)           USB_HCIVERSION_HCIVERSION(x)
94577 #define USBHS_HCSPARAMS_N_PORTS_MASK             USB_HCSPARAMS_N_PORTS_MASK
94578 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            USB_HCSPARAMS_N_PORTS_SHIFT
94579 #define USBHS_HCSPARAMS_N_PORTS(x)               USB_HCSPARAMS_N_PORTS(x)
94580 #define USBHS_HCSPARAMS_PPC_MASK                 USB_HCSPARAMS_PPC_MASK
94581 #define USBHS_HCSPARAMS_PPC_SHIFT                USB_HCSPARAMS_PPC_SHIFT
94582 #define USBHS_HCSPARAMS_PPC(x)                   USB_HCSPARAMS_PPC(x)
94583 #define USBHS_HCSPARAMS_N_PCC_MASK               USB_HCSPARAMS_N_PCC_MASK
94584 #define USBHS_HCSPARAMS_N_PCC_SHIFT              USB_HCSPARAMS_N_PCC_SHIFT
94585 #define USBHS_HCSPARAMS_N_PCC(x)                 USB_HCSPARAMS_N_PCC(x)
94586 #define USBHS_HCSPARAMS_N_CC_MASK                USB_HCSPARAMS_N_CC_MASK
94587 #define USBHS_HCSPARAMS_N_CC_SHIFT               USB_HCSPARAMS_N_CC_SHIFT
94588 #define USBHS_HCSPARAMS_N_CC(x)                  USB_HCSPARAMS_N_CC(x)
94589 #define USBHS_HCSPARAMS_PI_MASK                  USB_HCSPARAMS_PI_MASK
94590 #define USBHS_HCSPARAMS_PI_SHIFT                 USB_HCSPARAMS_PI_SHIFT
94591 #define USBHS_HCSPARAMS_PI(x)                    USB_HCSPARAMS_PI(x)
94592 #define USBHS_HCSPARAMS_N_PTT_MASK               USB_HCSPARAMS_N_PTT_MASK
94593 #define USBHS_HCSPARAMS_N_PTT_SHIFT              USB_HCSPARAMS_N_PTT_SHIFT
94594 #define USBHS_HCSPARAMS_N_PTT(x)                 USB_HCSPARAMS_N_PTT(x)
94595 #define USBHS_HCSPARAMS_N_TT_MASK                USB_HCSPARAMS_N_TT_MASK
94596 #define USBHS_HCSPARAMS_N_TT_SHIFT               USB_HCSPARAMS_N_TT_SHIFT
94597 #define USBHS_HCSPARAMS_N_TT(x)                  USB_HCSPARAMS_N_TT(x)
94598 #define USBHS_HCCPARAMS_ADC_MASK                 USB_HCCPARAMS_ADC_MASK
94599 #define USBHS_HCCPARAMS_ADC_SHIFT                USB_HCCPARAMS_ADC_SHIFT
94600 #define USBHS_HCCPARAMS_ADC(x)                   USB_HCCPARAMS_ADC(x)
94601 #define USBHS_HCCPARAMS_PFL_MASK                 USB_HCCPARAMS_PFL_MASK
94602 #define USBHS_HCCPARAMS_PFL_SHIFT                USB_HCCPARAMS_PFL_SHIFT
94603 #define USBHS_HCCPARAMS_PFL(x)                   USB_HCCPARAMS_PFL(x)
94604 #define USBHS_HCCPARAMS_ASP_MASK                 USB_HCCPARAMS_ASP_MASK
94605 #define USBHS_HCCPARAMS_ASP_SHIFT                USB_HCCPARAMS_ASP_SHIFT
94606 #define USBHS_HCCPARAMS_ASP(x)                   USB_HCCPARAMS_ASP(x)
94607 #define USBHS_HCCPARAMS_IST_MASK                 USB_HCCPARAMS_IST_MASK
94608 #define USBHS_HCCPARAMS_IST_SHIFT                USB_HCCPARAMS_IST_SHIFT
94609 #define USBHS_HCCPARAMS_IST(x)                   USB_HCCPARAMS_IST(x)
94610 #define USBHS_HCCPARAMS_EECP_MASK                USB_HCCPARAMS_EECP_MASK
94611 #define USBHS_HCCPARAMS_EECP_SHIFT               USB_HCCPARAMS_EECP_SHIFT
94612 #define USBHS_HCCPARAMS_EECP(x)                  USB_HCCPARAMS_EECP(x)
94613 #define USBHS_DCIVERSION_DCIVERSION_MASK         USB_DCIVERSION_DCIVERSION_MASK
94614 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        USB_DCIVERSION_DCIVERSION_SHIFT
94615 #define USBHS_DCIVERSION_DCIVERSION(x)           USB_DCIVERSION_DCIVERSION(x)
94616 #define USBHS_DCCPARAMS_DEN_MASK                 USB_DCCPARAMS_DEN_MASK
94617 #define USBHS_DCCPARAMS_DEN_SHIFT                USB_DCCPARAMS_DEN_SHIFT
94618 #define USBHS_DCCPARAMS_DEN(x)                   USB_DCCPARAMS_DEN(x)
94619 #define USBHS_DCCPARAMS_DC_MASK                  USB_DCCPARAMS_DC_MASK
94620 #define USBHS_DCCPARAMS_DC_SHIFT                 USB_DCCPARAMS_DC_SHIFT
94621 #define USBHS_DCCPARAMS_DC(x)                    USB_DCCPARAMS_DC(x)
94622 #define USBHS_DCCPARAMS_HC_MASK                  USB_DCCPARAMS_HC_MASK
94623 #define USBHS_DCCPARAMS_HC_SHIFT                 USB_DCCPARAMS_HC_SHIFT
94624 #define USBHS_DCCPARAMS_HC(x)                    USB_DCCPARAMS_HC(x)
94625 #define USBHS_USBCMD_RS_MASK                     USB_USBCMD_RS_MASK
94626 #define USBHS_USBCMD_RS_SHIFT                    USB_USBCMD_RS_SHIFT
94627 #define USBHS_USBCMD_RS(x)                       USB_USBCMD_RS(x)
94628 #define USBHS_USBCMD_RST_MASK                    USB_USBCMD_RST_MASK
94629 #define USBHS_USBCMD_RST_SHIFT                   USB_USBCMD_RST_SHIFT
94630 #define USBHS_USBCMD_RST(x)                      USB_USBCMD_RST(x)
94631 #define USBHS_USBCMD_FS_MASK                     USB_USBCMD_FS_1_MASK
94632 #define USBHS_USBCMD_FS_SHIFT                    USB_USBCMD_FS_1_SHIFT
94633 #define USBHS_USBCMD_FS(x)                       USB_USBCMD_FS_1(x)
94634 #define USBHS_USBCMD_PSE_MASK                    USB_USBCMD_PSE_MASK
94635 #define USBHS_USBCMD_PSE_SHIFT                   USB_USBCMD_PSE_SHIFT
94636 #define USBHS_USBCMD_PSE(x)                      USB_USBCMD_PSE(x)
94637 #define USBHS_USBCMD_ASE_MASK                    USB_USBCMD_ASE_MASK
94638 #define USBHS_USBCMD_ASE_SHIFT                   USB_USBCMD_ASE_SHIFT
94639 #define USBHS_USBCMD_ASE(x)                      USB_USBCMD_ASE(x)
94640 #define USBHS_USBCMD_IAA_MASK                    USB_USBCMD_IAA_MASK
94641 #define USBHS_USBCMD_IAA_SHIFT                   USB_USBCMD_IAA_SHIFT
94642 #define USBHS_USBCMD_IAA(x)                      USB_USBCMD_IAA(x)
94643 #define USBHS_USBCMD_ASP_MASK                    USB_USBCMD_ASP_MASK
94644 #define USBHS_USBCMD_ASP_SHIFT                   USB_USBCMD_ASP_SHIFT
94645 #define USBHS_USBCMD_ASP(x)                      USB_USBCMD_ASP(x)
94646 #define USBHS_USBCMD_ASPE_MASK                   USB_USBCMD_ASPE_MASK
94647 #define USBHS_USBCMD_ASPE_SHIFT                  USB_USBCMD_ASPE_SHIFT
94648 #define USBHS_USBCMD_ASPE(x)                     USB_USBCMD_ASPE(x)
94649 #define USBHS_USBCMD_ATDTW_MASK                  USB_USBCMD_ATDTW_MASK
94650 #define USBHS_USBCMD_ATDTW_SHIFT                 USB_USBCMD_ATDTW_SHIFT
94651 #define USBHS_USBCMD_ATDTW(x)                    USB_USBCMD_ATDTW(x)
94652 #define USBHS_USBCMD_SUTW_MASK                   USB_USBCMD_SUTW_MASK
94653 #define USBHS_USBCMD_SUTW_SHIFT                  USB_USBCMD_SUTW_SHIFT
94654 #define USBHS_USBCMD_SUTW(x)                     USB_USBCMD_SUTW(x)
94655 #define USBHS_USBCMD_FS2_MASK                    USB_USBCMD_FS_2_MASK
94656 #define USBHS_USBCMD_FS2_SHIFT                   USB_USBCMD_FS_2_SHIFT
94657 #define USBHS_USBCMD_FS2(x)                      USB_USBCMD_FS_2(x)
94658 #define USBHS_USBCMD_ITC_MASK                    USB_USBCMD_ITC_MASK
94659 #define USBHS_USBCMD_ITC_SHIFT                   USB_USBCMD_ITC_SHIFT
94660 #define USBHS_USBCMD_ITC(x)                      USB_USBCMD_ITC(x)
94661 #define USBHS_USBSTS_UI_MASK                     USB_USBSTS_UI_MASK
94662 #define USBHS_USBSTS_UI_SHIFT                    USB_USBSTS_UI_SHIFT
94663 #define USBHS_USBSTS_UI(x)                       USB_USBSTS_UI(x)
94664 #define USBHS_USBSTS_UEI_MASK                    USB_USBSTS_UEI_MASK
94665 #define USBHS_USBSTS_UEI_SHIFT                   USB_USBSTS_UEI_SHIFT
94666 #define USBHS_USBSTS_UEI(x)                      USB_USBSTS_UEI(x)
94667 #define USBHS_USBSTS_PCI_MASK                    USB_USBSTS_PCI_MASK
94668 #define USBHS_USBSTS_PCI_SHIFT                   USB_USBSTS_PCI_SHIFT
94669 #define USBHS_USBSTS_PCI(x)                      USB_USBSTS_PCI(x)
94670 #define USBHS_USBSTS_FRI_MASK                    USB_USBSTS_FRI_MASK
94671 #define USBHS_USBSTS_FRI_SHIFT                   USB_USBSTS_FRI_SHIFT
94672 #define USBHS_USBSTS_FRI(x)                      USB_USBSTS_FRI(x)
94673 #define USBHS_USBSTS_SEI_MASK                    USB_USBSTS_SEI_MASK
94674 #define USBHS_USBSTS_SEI_SHIFT                   USB_USBSTS_SEI_SHIFT
94675 #define USBHS_USBSTS_SEI(x)                      USB_USBSTS_SEI(x)
94676 #define USBHS_USBSTS_AAI_MASK                    USB_USBSTS_AAI_MASK
94677 #define USBHS_USBSTS_AAI_SHIFT                   USB_USBSTS_AAI_SHIFT
94678 #define USBHS_USBSTS_AAI(x)                      USB_USBSTS_AAI(x)
94679 #define USBHS_USBSTS_URI_MASK                    USB_USBSTS_URI_MASK
94680 #define USBHS_USBSTS_URI_SHIFT                   USB_USBSTS_URI_SHIFT
94681 #define USBHS_USBSTS_URI(x)                      USB_USBSTS_URI(x)
94682 #define USBHS_USBSTS_SRI_MASK                    USB_USBSTS_SRI_MASK
94683 #define USBHS_USBSTS_SRI_SHIFT                   USB_USBSTS_SRI_SHIFT
94684 #define USBHS_USBSTS_SRI(x)                      USB_USBSTS_SRI(x)
94685 #define USBHS_USBSTS_SLI_MASK                    USB_USBSTS_SLI_MASK
94686 #define USBHS_USBSTS_SLI_SHIFT                   USB_USBSTS_SLI_SHIFT
94687 #define USBHS_USBSTS_SLI(x)                      USB_USBSTS_SLI(x)
94688 #define USBHS_USBSTS_ULPII_MASK                  USB_USBSTS_ULPII_MASK
94689 #define USBHS_USBSTS_ULPII_SHIFT                 USB_USBSTS_ULPII_SHIFT
94690 #define USBHS_USBSTS_ULPII(x)                    USB_USBSTS_ULPII(x)
94691 #define USBHS_USBSTS_HCH_MASK                    USB_USBSTS_HCH_MASK
94692 #define USBHS_USBSTS_HCH_SHIFT                   USB_USBSTS_HCH_SHIFT
94693 #define USBHS_USBSTS_HCH(x)                      USB_USBSTS_HCH(x)
94694 #define USBHS_USBSTS_RCL_MASK                    USB_USBSTS_RCL_MASK
94695 #define USBHS_USBSTS_RCL_SHIFT                   USB_USBSTS_RCL_SHIFT
94696 #define USBHS_USBSTS_RCL(x)                      USB_USBSTS_RCL(x)
94697 #define USBHS_USBSTS_PS_MASK                     USB_USBSTS_PS_MASK
94698 #define USBHS_USBSTS_PS_SHIFT                    USB_USBSTS_PS_SHIFT
94699 #define USBHS_USBSTS_PS(x)                       USB_USBSTS_PS(x)
94700 #define USBHS_USBSTS_AS_MASK                     USB_USBSTS_AS_MASK
94701 #define USBHS_USBSTS_AS_SHIFT                    USB_USBSTS_AS_SHIFT
94702 #define USBHS_USBSTS_AS(x)                       USB_USBSTS_AS(x)
94703 #define USBHS_USBSTS_NAKI_MASK                   USB_USBSTS_NAKI_MASK
94704 #define USBHS_USBSTS_NAKI_SHIFT                  USB_USBSTS_NAKI_SHIFT
94705 #define USBHS_USBSTS_NAKI(x)                     USB_USBSTS_NAKI(x)
94706 #define USBHS_USBSTS_TI0_MASK                    USB_USBSTS_TI0_MASK
94707 #define USBHS_USBSTS_TI0_SHIFT                   USB_USBSTS_TI0_SHIFT
94708 #define USBHS_USBSTS_TI0(x)                      USB_USBSTS_TI0(x)
94709 #define USBHS_USBSTS_TI1_MASK                    USB_USBSTS_TI1_MASK
94710 #define USBHS_USBSTS_TI1_SHIFT                   USB_USBSTS_TI1_SHIFT
94711 #define USBHS_USBSTS_TI1(x)                      USB_USBSTS_TI1(x)
94712 #define USBHS_USBINTR_UE_MASK                    USB_USBINTR_UE_MASK
94713 #define USBHS_USBINTR_UE_SHIFT                   USB_USBINTR_UE_SHIFT
94714 #define USBHS_USBINTR_UE(x)                      USB_USBINTR_UE(x)
94715 #define USBHS_USBINTR_UEE_MASK                   USB_USBINTR_UEE_MASK
94716 #define USBHS_USBINTR_UEE_SHIFT                  USB_USBINTR_UEE_SHIFT
94717 #define USBHS_USBINTR_UEE(x)                     USB_USBINTR_UEE(x)
94718 #define USBHS_USBINTR_PCE_MASK                   USB_USBINTR_PCE_MASK
94719 #define USBHS_USBINTR_PCE_SHIFT                  USB_USBINTR_PCE_SHIFT
94720 #define USBHS_USBINTR_PCE(x)                     USB_USBINTR_PCE(x)
94721 #define USBHS_USBINTR_FRE_MASK                   USB_USBINTR_FRE_MASK
94722 #define USBHS_USBINTR_FRE_SHIFT                  USB_USBINTR_FRE_SHIFT
94723 #define USBHS_USBINTR_FRE(x)                     USB_USBINTR_FRE(x)
94724 #define USBHS_USBINTR_SEE_MASK                   USB_USBINTR_SEE_MASK
94725 #define USBHS_USBINTR_SEE_SHIFT                  USB_USBINTR_SEE_SHIFT
94726 #define USBHS_USBINTR_SEE(x)                     USB_USBINTR_SEE(x)
94727 #define USBHS_USBINTR_AAE_MASK                   USB_USBINTR_AAE_MASK
94728 #define USBHS_USBINTR_AAE_SHIFT                  USB_USBINTR_AAE_SHIFT
94729 #define USBHS_USBINTR_AAE(x)                     USB_USBINTR_AAE(x)
94730 #define USBHS_USBINTR_URE_MASK                   USB_USBINTR_URE_MASK
94731 #define USBHS_USBINTR_URE_SHIFT                  USB_USBINTR_URE_SHIFT
94732 #define USBHS_USBINTR_URE(x)                     USB_USBINTR_URE(x)
94733 #define USBHS_USBINTR_SRE_MASK                   USB_USBINTR_SRE_MASK
94734 #define USBHS_USBINTR_SRE_SHIFT                  USB_USBINTR_SRE_SHIFT
94735 #define USBHS_USBINTR_SRE(x)                     USB_USBINTR_SRE(x)
94736 #define USBHS_USBINTR_SLE_MASK                   USB_USBINTR_SLE_MASK
94737 #define USBHS_USBINTR_SLE_SHIFT                  USB_USBINTR_SLE_SHIFT
94738 #define USBHS_USBINTR_SLE(x)                     USB_USBINTR_SLE(x)
94739 #define USBHS_USBINTR_ULPIE_MASK                 USB_USBINTR_ULPIE_MASK
94740 #define USBHS_USBINTR_ULPIE_SHIFT                USB_USBINTR_ULPIE_SHIFT
94741 #define USBHS_USBINTR_ULPIE(x)                   USB_USBINTR_ULPIE(x)
94742 #define USBHS_USBINTR_NAKE_MASK                  USB_USBINTR_NAKE_MASK
94743 #define USBHS_USBINTR_NAKE_SHIFT                 USB_USBINTR_NAKE_SHIFT
94744 #define USBHS_USBINTR_NAKE(x)                    USB_USBINTR_NAKE(x)
94745 #define USBHS_USBINTR_UAIE_MASK                  USB_USBINTR_UAIE_MASK
94746 #define USBHS_USBINTR_UAIE_SHIFT                 USB_USBINTR_UAIE_SHIFT
94747 #define USBHS_USBINTR_UAIE(x)                    USB_USBINTR_UAIE(x)
94748 #define USBHS_USBINTR_UPIE_MASK                  USB_USBINTR_UPIE_MASK
94749 #define USBHS_USBINTR_UPIE_SHIFT                 USB_USBINTR_UPIE_SHIFT
94750 #define USBHS_USBINTR_UPIE(x)                    USB_USBINTR_UPIE(x)
94751 #define USBHS_USBINTR_TIE0_MASK                  USB_USBINTR_TIE0_MASK
94752 #define USBHS_USBINTR_TIE0_SHIFT                 USB_USBINTR_TIE0_SHIFT
94753 #define USBHS_USBINTR_TIE0(x)                    USB_USBINTR_TIE0(x)
94754 #define USBHS_USBINTR_TIE1_MASK                  USB_USBINTR_TIE1_MASK
94755 #define USBHS_USBINTR_TIE1_SHIFT                 USB_USBINTR_TIE1_SHIFT
94756 #define USBHS_USBINTR_TIE1(x)                    USB_USBINTR_TIE1(x)
94757 #define USBHS_FRINDEX_FRINDEX_MASK               USB_FRINDEX_FRINDEX_MASK
94758 #define USBHS_FRINDEX_FRINDEX_SHIFT              USB_FRINDEX_FRINDEX_SHIFT
94759 #define USBHS_FRINDEX_FRINDEX(x)                 USB_FRINDEX_FRINDEX(x)
94760 #define USBHS_DEVICEADDR_USBADRA_MASK            USB_DEVICEADDR_USBADRA_MASK
94761 #define USBHS_DEVICEADDR_USBADRA_SHIFT           USB_DEVICEADDR_USBADRA_SHIFT
94762 #define USBHS_DEVICEADDR_USBADRA(x)              USB_DEVICEADDR_USBADRA(x)
94763 #define USBHS_DEVICEADDR_USBADR_MASK             USB_DEVICEADDR_USBADR_MASK
94764 #define USBHS_DEVICEADDR_USBADR_SHIFT            USB_DEVICEADDR_USBADR_SHIFT
94765 #define USBHS_DEVICEADDR_USBADR(x)               USB_DEVICEADDR_USBADR(x)
94766 #define USBHS_PERIODICLISTBASE_PERBASE_MASK      USB_PERIODICLISTBASE_BASEADR_MASK
94767 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USB_PERIODICLISTBASE_BASEADR_SHIFT
94768 #define USBHS_PERIODICLISTBASE_PERBASE(x)        USB_PERIODICLISTBASE_BASEADR(x)
94769 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USB_ASYNCLISTADDR_ASYBASE_MASK
94770 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USB_ASYNCLISTADDR_ASYBASE_SHIFT
94771 #define USBHS_ASYNCLISTADDR_ASYBASE(x)           USB_ASYNCLISTADDR_ASYBASE(x)
94772 #define USBHS_EPLISTADDR_EPBASE_MASK             USB_ENDPTLISTADDR_EPBASE_MASK
94773 #define USBHS_EPLISTADDR_EPBASE_SHIFT            USB_ENDPTLISTADDR_EPBASE_SHIFT
94774 #define USBHS_EPLISTADDR_EPBASE(x)               USB_ENDPTLISTADDR_EPBASE(x)
94775 #define USBHS_BURSTSIZE_RXPBURST_MASK            USB_BURSTSIZE_RXPBURST_MASK
94776 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           USB_BURSTSIZE_RXPBURST_SHIFT
94777 #define USBHS_BURSTSIZE_RXPBURST(x)              USB_BURSTSIZE_RXPBURST(x)
94778 #define USBHS_BURSTSIZE_TXPBURST_MASK            USB_BURSTSIZE_TXPBURST_MASK
94779 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           USB_BURSTSIZE_TXPBURST_SHIFT
94780 #define USBHS_BURSTSIZE_TXPBURST(x)              USB_BURSTSIZE_TXPBURST(x)
94781 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          USB_TXFILLTUNING_TXSCHOH_MASK
94782 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USB_TXFILLTUNING_TXSCHOH_SHIFT
94783 #define USBHS_TXFILLTUNING_TXSCHOH(x)            USB_TXFILLTUNING_TXSCHOH(x)
94784 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USB_TXFILLTUNING_TXSCHHEALTH_MASK
94785 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
94786 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USB_TXFILLTUNING_TXSCHHEALTH(x)
94787 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USB_TXFILLTUNING_TXFIFOTHRES_MASK
94788 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
94789 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USB_TXFILLTUNING_TXFIFOTHRES(x)
94790 #define USBHS_ENDPTNAK_EPRN_MASK                 USB_ENDPTNAK_EPRN_MASK
94791 #define USBHS_ENDPTNAK_EPRN_SHIFT                USB_ENDPTNAK_EPRN_SHIFT
94792 #define USBHS_ENDPTNAK_EPRN(x)                   USB_ENDPTNAK_EPRN(x)
94793 #define USBHS_ENDPTNAK_EPTN_MASK                 USB_ENDPTNAK_EPTN_MASK
94794 #define USBHS_ENDPTNAK_EPTN_SHIFT                USB_ENDPTNAK_EPTN_SHIFT
94795 #define USBHS_ENDPTNAK_EPTN(x)                   USB_ENDPTNAK_EPTN(x)
94796 #define USBHS_ENDPTNAKEN_EPRNE_MASK              USB_ENDPTNAKEN_EPRNE_MASK
94797 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USB_ENDPTNAKEN_EPRNE_SHIFT
94798 #define USBHS_ENDPTNAKEN_EPRNE(x)                USB_ENDPTNAKEN_EPRNE(x)
94799 #define USBHS_ENDPTNAKEN_EPTNE_MASK              USB_ENDPTNAKEN_EPTNE_MASK
94800 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USB_ENDPTNAKEN_EPTNE_SHIFT
94801 #define USBHS_ENDPTNAKEN_EPTNE(x)                USB_ENDPTNAKEN_EPTNE(x)
94802 #define USBHS_CONFIGFLAG_CF_MASK                 USB_CONFIGFLAG_CF_MASK
94803 #define USBHS_CONFIGFLAG_CF_SHIFT                USB_CONFIGFLAG_CF_SHIFT
94804 #define USBHS_CONFIGFLAG_CF(x)                   USB_CONFIGFLAG_CF(x)
94805 #define USBHS_PORTSC1_CCS_MASK                   USB_PORTSC1_CCS_MASK
94806 #define USBHS_PORTSC1_CCS_SHIFT                  USB_PORTSC1_CCS_SHIFT
94807 #define USBHS_PORTSC1_CCS(x)                     USB_PORTSC1_CCS(x)
94808 #define USBHS_PORTSC1_CSC_MASK                   USB_PORTSC1_CSC_MASK
94809 #define USBHS_PORTSC1_CSC_SHIFT                  USB_PORTSC1_CSC_SHIFT
94810 #define USBHS_PORTSC1_CSC(x)                     USB_PORTSC1_CSC(x)
94811 #define USBHS_PORTSC1_PE_MASK                    USB_PORTSC1_PE_MASK
94812 #define USBHS_PORTSC1_PE_SHIFT                   USB_PORTSC1_PE_SHIFT
94813 #define USBHS_PORTSC1_PE(x)                      USB_PORTSC1_PE(x)
94814 #define USBHS_PORTSC1_PEC_MASK                   USB_PORTSC1_PEC_MASK
94815 #define USBHS_PORTSC1_PEC_SHIFT                  USB_PORTSC1_PEC_SHIFT
94816 #define USBHS_PORTSC1_PEC(x)                     USB_PORTSC1_PEC(x)
94817 #define USBHS_PORTSC1_OCA_MASK                   USB_PORTSC1_OCA_MASK
94818 #define USBHS_PORTSC1_OCA_SHIFT                  USB_PORTSC1_OCA_SHIFT
94819 #define USBHS_PORTSC1_OCA(x)                     USB_PORTSC1_OCA(x)
94820 #define USBHS_PORTSC1_OCC_MASK                   USB_PORTSC1_OCC_MASK
94821 #define USBHS_PORTSC1_OCC_SHIFT                  USB_PORTSC1_OCC_SHIFT
94822 #define USBHS_PORTSC1_OCC(x)                     USB_PORTSC1_OCC(x)
94823 #define USBHS_PORTSC1_FPR_MASK                   USB_PORTSC1_FPR_MASK
94824 #define USBHS_PORTSC1_FPR_SHIFT                  USB_PORTSC1_FPR_SHIFT
94825 #define USBHS_PORTSC1_FPR(x)                     USB_PORTSC1_FPR(x)
94826 #define USBHS_PORTSC1_SUSP_MASK                  USB_PORTSC1_SUSP_MASK
94827 #define USBHS_PORTSC1_SUSP_SHIFT                 USB_PORTSC1_SUSP_SHIFT
94828 #define USBHS_PORTSC1_SUSP(x)                    USB_PORTSC1_SUSP(x)
94829 #define USBHS_PORTSC1_PR_MASK                    USB_PORTSC1_PR_MASK
94830 #define USBHS_PORTSC1_PR_SHIFT                   USB_PORTSC1_PR_SHIFT
94831 #define USBHS_PORTSC1_PR(x)                      USB_PORTSC1_PR(x)
94832 #define USBHS_PORTSC1_HSP_MASK                   USB_PORTSC1_HSP_MASK
94833 #define USBHS_PORTSC1_HSP_SHIFT                  USB_PORTSC1_HSP_SHIFT
94834 #define USBHS_PORTSC1_HSP(x)                     USB_PORTSC1_HSP(x)
94835 #define USBHS_PORTSC1_LS_MASK                    USB_PORTSC1_LS_MASK
94836 #define USBHS_PORTSC1_LS_SHIFT                   USB_PORTSC1_LS_SHIFT
94837 #define USBHS_PORTSC1_LS(x)                      USB_PORTSC1_LS(x)
94838 #define USBHS_PORTSC1_PP_MASK                    USB_PORTSC1_PP_MASK
94839 #define USBHS_PORTSC1_PP_SHIFT                   USB_PORTSC1_PP_SHIFT
94840 #define USBHS_PORTSC1_PP(x)                      USB_PORTSC1_PP(x)
94841 #define USBHS_PORTSC1_PO_MASK                    USB_PORTSC1_PO_MASK
94842 #define USBHS_PORTSC1_PO_SHIFT                   USB_PORTSC1_PO_SHIFT
94843 #define USBHS_PORTSC1_PO(x)                      USB_PORTSC1_PO(x)
94844 #define USBHS_PORTSC1_PIC_MASK                   USB_PORTSC1_PIC_MASK
94845 #define USBHS_PORTSC1_PIC_SHIFT                  USB_PORTSC1_PIC_SHIFT
94846 #define USBHS_PORTSC1_PIC(x)                     USB_PORTSC1_PIC(x)
94847 #define USBHS_PORTSC1_PTC_MASK                   USB_PORTSC1_PTC_MASK
94848 #define USBHS_PORTSC1_PTC_SHIFT                  USB_PORTSC1_PTC_SHIFT
94849 #define USBHS_PORTSC1_PTC(x)                     USB_PORTSC1_PTC(x)
94850 #define USBHS_PORTSC1_WKCN_MASK                  USB_PORTSC1_WKCN_MASK
94851 #define USBHS_PORTSC1_WKCN_SHIFT                 USB_PORTSC1_WKCN_SHIFT
94852 #define USBHS_PORTSC1_WKCN(x)                    USB_PORTSC1_WKCN(x)
94853 #define USBHS_PORTSC1_WKDS_MASK                  USB_PORTSC1_WKDC_MASK
94854 #define USBHS_PORTSC1_WKDS_SHIFT                 USB_PORTSC1_WKDC_SHIFT
94855 #define USBHS_PORTSC1_WKDS(x)                    USB_PORTSC1_WKDC(x)
94856 #define USBHS_PORTSC1_WKOC_MASK                  USB_PORTSC1_WKOC_MASK
94857 #define USBHS_PORTSC1_WKOC_SHIFT                 USB_PORTSC1_WKOC_SHIFT
94858 #define USBHS_PORTSC1_WKOC(x)                    USB_PORTSC1_WKOC(x)
94859 #define USBHS_PORTSC1_PHCD_MASK                  USB_PORTSC1_PHCD_MASK
94860 #define USBHS_PORTSC1_PHCD_SHIFT                 USB_PORTSC1_PHCD_SHIFT
94861 #define USBHS_PORTSC1_PHCD(x)                    USB_PORTSC1_PHCD(x)
94862 #define USBHS_PORTSC1_PFSC_MASK                  USB_PORTSC1_PFSC_MASK
94863 #define USBHS_PORTSC1_PFSC_SHIFT                 USB_PORTSC1_PFSC_SHIFT
94864 #define USBHS_PORTSC1_PFSC(x)                    USB_PORTSC1_PFSC(x)
94865 #define USBHS_PORTSC1_PTS2_MASK                  USB_PORTSC1_PTS_2_MASK
94866 #define USBHS_PORTSC1_PTS2_SHIFT                 USB_PORTSC1_PTS_2_SHIFT
94867 #define USBHS_PORTSC1_PTS2(x)                    USB_PORTSC1_PTS_2(x)
94868 #define USBHS_PORTSC1_PSPD_MASK                  USB_PORTSC1_PSPD_MASK
94869 #define USBHS_PORTSC1_PSPD_SHIFT                 USB_PORTSC1_PSPD_SHIFT
94870 #define USBHS_PORTSC1_PSPD(x)                    USB_PORTSC1_PSPD(x)
94871 #define USBHS_PORTSC1_PTW_MASK                   USB_PORTSC1_PTW_MASK
94872 #define USBHS_PORTSC1_PTW_SHIFT                  USB_PORTSC1_PTW_SHIFT
94873 #define USBHS_PORTSC1_PTW(x)                     USB_PORTSC1_PTW(x)
94874 #define USBHS_PORTSC1_STS_MASK                   USB_PORTSC1_STS_MASK
94875 #define USBHS_PORTSC1_STS_SHIFT                  USB_PORTSC1_STS_SHIFT
94876 #define USBHS_PORTSC1_STS(x)                     USB_PORTSC1_STS(x)
94877 #define USBHS_PORTSC1_PTS_MASK                   USB_PORTSC1_PTS_1_MASK
94878 #define USBHS_PORTSC1_PTS_SHIFT                  USB_PORTSC1_PTS_1_SHIFT
94879 #define USBHS_PORTSC1_PTS(x)                     USB_PORTSC1_PTS_1(x)
94880 #define USBHS_OTGSC_VD_MASK                      USB_OTGSC_VD_MASK
94881 #define USBHS_OTGSC_VD_SHIFT                     USB_OTGSC_VD_SHIFT
94882 #define USBHS_OTGSC_VD(x)                        USB_OTGSC_VD(x)
94883 #define USBHS_OTGSC_VC_MASK                      USB_OTGSC_VC_MASK
94884 #define USBHS_OTGSC_VC_SHIFT                     USB_OTGSC_VC_SHIFT
94885 #define USBHS_OTGSC_VC(x)                        USB_OTGSC_VC(x)
94886 #define USBHS_OTGSC_OT_MASK                      USB_OTGSC_OT_MASK
94887 #define USBHS_OTGSC_OT_SHIFT                     USB_OTGSC_OT_SHIFT
94888 #define USBHS_OTGSC_OT(x)                        USB_OTGSC_OT(x)
94889 #define USBHS_OTGSC_DP_MASK                      USB_OTGSC_DP_MASK
94890 #define USBHS_OTGSC_DP_SHIFT                     USB_OTGSC_DP_SHIFT
94891 #define USBHS_OTGSC_DP(x)                        USB_OTGSC_DP(x)
94892 #define USBHS_OTGSC_IDPU_MASK                    USB_OTGSC_IDPU_MASK
94893 #define USBHS_OTGSC_IDPU_SHIFT                   USB_OTGSC_IDPU_SHIFT
94894 #define USBHS_OTGSC_IDPU(x)                      USB_OTGSC_IDPU(x)
94895 #define USBHS_OTGSC_ID_MASK                      USB_OTGSC_ID_MASK
94896 #define USBHS_OTGSC_ID_SHIFT                     USB_OTGSC_ID_SHIFT
94897 #define USBHS_OTGSC_ID(x)                        USB_OTGSC_ID(x)
94898 #define USBHS_OTGSC_AVV_MASK                     USB_OTGSC_AVV_MASK
94899 #define USBHS_OTGSC_AVV_SHIFT                    USB_OTGSC_AVV_SHIFT
94900 #define USBHS_OTGSC_AVV(x)                       USB_OTGSC_AVV(x)
94901 #define USBHS_OTGSC_ASV_MASK                     USB_OTGSC_ASV_MASK
94902 #define USBHS_OTGSC_ASV_SHIFT                    USB_OTGSC_ASV_SHIFT
94903 #define USBHS_OTGSC_ASV(x)                       USB_OTGSC_ASV(x)
94904 #define USBHS_OTGSC_BSV_MASK                     USB_OTGSC_BSV_MASK
94905 #define USBHS_OTGSC_BSV_SHIFT                    USB_OTGSC_BSV_SHIFT
94906 #define USBHS_OTGSC_BSV(x)                       USB_OTGSC_BSV(x)
94907 #define USBHS_OTGSC_BSE_MASK                     USB_OTGSC_BSE_MASK
94908 #define USBHS_OTGSC_BSE_SHIFT                    USB_OTGSC_BSE_SHIFT
94909 #define USBHS_OTGSC_BSE(x)                       USB_OTGSC_BSE(x)
94910 #define USBHS_OTGSC_MST_MASK                     USB_OTGSC_TOG_1MS_MASK
94911 #define USBHS_OTGSC_MST_SHIFT                    USB_OTGSC_TOG_1MS_SHIFT
94912 #define USBHS_OTGSC_MST(x)                       USB_OTGSC_TOG_1MS(x)
94913 #define USBHS_OTGSC_DPS_MASK                     USB_OTGSC_DPS_MASK
94914 #define USBHS_OTGSC_DPS_SHIFT                    USB_OTGSC_DPS_SHIFT
94915 #define USBHS_OTGSC_DPS(x)                       USB_OTGSC_DPS(x)
94916 #define USBHS_OTGSC_IDIS_MASK                    USB_OTGSC_IDIS_MASK
94917 #define USBHS_OTGSC_IDIS_SHIFT                   USB_OTGSC_IDIS_SHIFT
94918 #define USBHS_OTGSC_IDIS(x)                      USB_OTGSC_IDIS(x)
94919 #define USBHS_OTGSC_AVVIS_MASK                   USB_OTGSC_AVVIS_MASK
94920 #define USBHS_OTGSC_AVVIS_SHIFT                  USB_OTGSC_AVVIS_SHIFT
94921 #define USBHS_OTGSC_AVVIS(x)                     USB_OTGSC_AVVIS(x)
94922 #define USBHS_OTGSC_ASVIS_MASK                   USB_OTGSC_ASVIS_MASK
94923 #define USBHS_OTGSC_ASVIS_SHIFT                  USB_OTGSC_ASVIS_SHIFT
94924 #define USBHS_OTGSC_ASVIS(x)                     USB_OTGSC_ASVIS(x)
94925 #define USBHS_OTGSC_BSVIS_MASK                   USB_OTGSC_BSVIS_MASK
94926 #define USBHS_OTGSC_BSVIS_SHIFT                  USB_OTGSC_BSVIS_SHIFT
94927 #define USBHS_OTGSC_BSVIS(x)                     USB_OTGSC_BSVIS(x)
94928 #define USBHS_OTGSC_BSEIS_MASK                   USB_OTGSC_BSEIS_MASK
94929 #define USBHS_OTGSC_BSEIS_SHIFT                  USB_OTGSC_BSEIS_SHIFT
94930 #define USBHS_OTGSC_BSEIS(x)                     USB_OTGSC_BSEIS(x)
94931 #define USBHS_OTGSC_MSS_MASK                     USB_OTGSC_STATUS_1MS_MASK
94932 #define USBHS_OTGSC_MSS_SHIFT                    USB_OTGSC_STATUS_1MS_SHIFT
94933 #define USBHS_OTGSC_MSS(x)                       USB_OTGSC_STATUS_1MS(x)
94934 #define USBHS_OTGSC_DPIS_MASK                    USB_OTGSC_DPIS_MASK
94935 #define USBHS_OTGSC_DPIS_SHIFT                   USB_OTGSC_DPIS_SHIFT
94936 #define USBHS_OTGSC_DPIS(x)                      USB_OTGSC_DPIS(x)
94937 #define USBHS_OTGSC_IDIE_MASK                    USB_OTGSC_IDIE_MASK
94938 #define USBHS_OTGSC_IDIE_SHIFT                   USB_OTGSC_IDIE_SHIFT
94939 #define USBHS_OTGSC_IDIE(x)                      USB_OTGSC_IDIE(x)
94940 #define USBHS_OTGSC_AVVIE_MASK                   USB_OTGSC_AVVIE_MASK
94941 #define USBHS_OTGSC_AVVIE_SHIFT                  USB_OTGSC_AVVIE_SHIFT
94942 #define USBHS_OTGSC_AVVIE(x)                     USB_OTGSC_AVVIE(x)
94943 #define USBHS_OTGSC_ASVIE_MASK                   USB_OTGSC_ASVIE_MASK
94944 #define USBHS_OTGSC_ASVIE_SHIFT                  USB_OTGSC_ASVIE_SHIFT
94945 #define USBHS_OTGSC_ASVIE(x)                     USB_OTGSC_ASVIE(x)
94946 #define USBHS_OTGSC_BSVIE_MASK                   USB_OTGSC_BSVIE_MASK
94947 #define USBHS_OTGSC_BSVIE_SHIFT                  USB_OTGSC_BSVIE_SHIFT
94948 #define USBHS_OTGSC_BSVIE(x)                     USB_OTGSC_BSVIE(x)
94949 #define USBHS_OTGSC_BSEIE_MASK                   USB_OTGSC_BSEIE_MASK
94950 #define USBHS_OTGSC_BSEIE_SHIFT                  USB_OTGSC_BSEIE_SHIFT
94951 #define USBHS_OTGSC_BSEIE(x)                     USB_OTGSC_BSEIE(x)
94952 #define USBHS_OTGSC_MSE_MASK                     USB_OTGSC_EN_1MS_MASK
94953 #define USBHS_OTGSC_MSE_SHIFT                    USB_OTGSC_EN_1MS_SHIFT
94954 #define USBHS_OTGSC_MSE(x)                       USB_OTGSC_EN_1MS(x)
94955 #define USBHS_OTGSC_DPIE_MASK                    USB_OTGSC_DPIE_MASK
94956 #define USBHS_OTGSC_DPIE_SHIFT                   USB_OTGSC_DPIE_SHIFT
94957 #define USBHS_OTGSC_DPIE(x)                      USB_OTGSC_DPIE(x)
94958 #define USBHS_USBMODE_CM_MASK                    USB_USBMODE_CM_MASK
94959 #define USBHS_USBMODE_CM_SHIFT                   USB_USBMODE_CM_SHIFT
94960 #define USBHS_USBMODE_CM(x)                      USB_USBMODE_CM(x)
94961 #define USBHS_USBMODE_ES_MASK                    USB_USBMODE_ES_MASK
94962 #define USBHS_USBMODE_ES_SHIFT                   USB_USBMODE_ES_SHIFT
94963 #define USBHS_USBMODE_ES(x)                      USB_USBMODE_ES(x)
94964 #define USBHS_USBMODE_SLOM_MASK                  USB_USBMODE_SLOM_MASK
94965 #define USBHS_USBMODE_SLOM_SHIFT                 USB_USBMODE_SLOM_SHIFT
94966 #define USBHS_USBMODE_SLOM(x)                    USB_USBMODE_SLOM(x)
94967 #define USBHS_USBMODE_SDIS_MASK                  USB_USBMODE_SDIS_MASK
94968 #define USBHS_USBMODE_SDIS_SHIFT                 USB_USBMODE_SDIS_SHIFT
94969 #define USBHS_USBMODE_SDIS(x)                    USB_USBMODE_SDIS(x)
94970 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
94971 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
94972 #define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
94973 #define USBHS_EPPRIME_PERB_MASK                  USB_ENDPTPRIME_PERB_MASK
94974 #define USBHS_EPPRIME_PERB_SHIFT                 USB_ENDPTPRIME_PERB_SHIFT
94975 #define USBHS_EPPRIME_PERB(x)                    USB_ENDPTPRIME_PERB(x)
94976 #define USBHS_EPPRIME_PETB_MASK                  USB_ENDPTPRIME_PETB_MASK
94977 #define USBHS_EPPRIME_PETB_SHIFT                 USB_ENDPTPRIME_PETB_SHIFT
94978 #define USBHS_EPPRIME_PETB(x)                    USB_ENDPTPRIME_PETB(x)
94979 #define USBHS_EPFLUSH_FERB_MASK                  USB_ENDPTFLUSH_FERB_MASK
94980 #define USBHS_EPFLUSH_FERB_SHIFT                 USB_ENDPTFLUSH_FERB_SHIFT
94981 #define USBHS_EPFLUSH_FERB(x)                    USB_ENDPTFLUSH_FERB(x)
94982 #define USBHS_EPFLUSH_FETB_MASK                  USB_ENDPTFLUSH_FETB_MASK
94983 #define USBHS_EPFLUSH_FETB_SHIFT                 USB_ENDPTFLUSH_FETB_SHIFT
94984 #define USBHS_EPFLUSH_FETB(x)                    USB_ENDPTFLUSH_FETB(x)
94985 #define USBHS_EPSR_ERBR_MASK                     USB_ENDPTSTAT_ERBR_MASK
94986 #define USBHS_EPSR_ERBR_SHIFT                    USB_ENDPTSTAT_ERBR_SHIFT
94987 #define USBHS_EPSR_ERBR(x)                       USB_ENDPTSTAT_ERBR(x)
94988 #define USBHS_EPSR_ETBR_MASK                     USB_ENDPTSTAT_ETBR_MASK
94989 #define USBHS_EPSR_ETBR_SHIFT                    USB_ENDPTSTAT_ETBR_SHIFT
94990 #define USBHS_EPSR_ETBR(x)                       USB_ENDPTSTAT_ETBR(x)
94991 #define USBHS_EPCOMPLETE_ERCE_MASK               USB_ENDPTCOMPLETE_ERCE_MASK
94992 #define USBHS_EPCOMPLETE_ERCE_SHIFT              USB_ENDPTCOMPLETE_ERCE_SHIFT
94993 #define USBHS_EPCOMPLETE_ERCE(x)                 USB_ENDPTCOMPLETE_ERCE(x)
94994 #define USBHS_EPCOMPLETE_ETCE_MASK               USB_ENDPTCOMPLETE_ETCE_MASK
94995 #define USBHS_EPCOMPLETE_ETCE_SHIFT              USB_ENDPTCOMPLETE_ETCE_SHIFT
94996 #define USBHS_EPCOMPLETE_ETCE(x)                 USB_ENDPTCOMPLETE_ETCE(x)
94997 #define USBHS_EPCR0_RXS_MASK                     USB_ENDPTCTRL0_RXS_MASK
94998 #define USBHS_EPCR0_RXS_SHIFT                    USB_ENDPTCTRL0_RXS_SHIFT
94999 #define USBHS_EPCR0_RXS(x)                       USB_ENDPTCTRL0_RXS(x)
95000 #define USBHS_EPCR0_RXT_MASK                     USB_ENDPTCTRL0_RXT_MASK
95001 #define USBHS_EPCR0_RXT_SHIFT                    USB_ENDPTCTRL0_RXT_SHIFT
95002 #define USBHS_EPCR0_RXT(x)                       USB_ENDPTCTRL0_RXT(x)
95003 #define USBHS_EPCR0_RXE_MASK                     USB_ENDPTCTRL0_RXE_MASK
95004 #define USBHS_EPCR0_RXE_SHIFT                    USB_ENDPTCTRL0_RXE_SHIFT
95005 #define USBHS_EPCR0_RXE(x)                       USB_ENDPTCTRL0_RXE(x)
95006 #define USBHS_EPCR0_TXS_MASK                     USB_ENDPTCTRL0_TXS_MASK
95007 #define USBHS_EPCR0_TXS_SHIFT                    USB_ENDPTCTRL0_TXS_SHIFT
95008 #define USBHS_EPCR0_TXS(x)                       USB_ENDPTCTRL0_TXS(x)
95009 #define USBHS_EPCR0_TXT_MASK                     USB_ENDPTCTRL0_TXT_MASK
95010 #define USBHS_EPCR0_TXT_SHIFT                    USB_ENDPTCTRL0_TXT_SHIFT
95011 #define USBHS_EPCR0_TXT(x)                       USB_ENDPTCTRL0_TXT(x)
95012 #define USBHS_EPCR0_TXE_MASK                     USB_ENDPTCTRL0_TXE_MASK
95013 #define USBHS_EPCR0_TXE_SHIFT                    USB_ENDPTCTRL0_TXE_SHIFT
95014 #define USBHS_EPCR0_TXE(x)                       USB_ENDPTCTRL0_TXE(x)
95015 #define USBHS_EPCR_RXS_MASK                      USB_ENDPTCTRL_RXS_MASK
95016 #define USBHS_EPCR_RXS_SHIFT                     USB_ENDPTCTRL_RXS_SHIFT
95017 #define USBHS_EPCR_RXS(x)                        USB_ENDPTCTRL_RXS(x)
95018 #define USBHS_EPCR_RXD_MASK                      USB_ENDPTCTRL_RXD_MASK
95019 #define USBHS_EPCR_RXD_SHIFT                     USB_ENDPTCTRL_RXD_SHIFT
95020 #define USBHS_EPCR_RXD(x)                        USB_ENDPTCTRL_RXD(x)
95021 #define USBHS_EPCR_RXT_MASK                      USB_ENDPTCTRL_RXT_MASK
95022 #define USBHS_EPCR_RXT_SHIFT                     USB_ENDPTCTRL_RXT_SHIFT
95023 #define USBHS_EPCR_RXT(x)                        USB_ENDPTCTRL_RXT(x)
95024 #define USBHS_EPCR_RXI_MASK                      USB_ENDPTCTRL_RXI_MASK
95025 #define USBHS_EPCR_RXI_SHIFT                     USB_ENDPTCTRL_RXI_SHIFT
95026 #define USBHS_EPCR_RXI(x)                        USB_ENDPTCTRL_RXI(x)
95027 #define USBHS_EPCR_RXR_MASK                      USB_ENDPTCTRL_RXR_MASK
95028 #define USBHS_EPCR_RXR_SHIFT                     USB_ENDPTCTRL_RXR_SHIFT
95029 #define USBHS_EPCR_RXR(x)                        USB_ENDPTCTRL_RXR(x)
95030 #define USBHS_EPCR_RXE_MASK                      USB_ENDPTCTRL_RXE_MASK
95031 #define USBHS_EPCR_RXE_SHIFT                     USB_ENDPTCTRL_RXE_SHIFT
95032 #define USBHS_EPCR_RXE(x)                        USB_ENDPTCTRL_RXE(x)
95033 #define USBHS_EPCR_TXS_MASK                      USB_ENDPTCTRL_TXS_MASK
95034 #define USBHS_EPCR_TXS_SHIFT                     USB_ENDPTCTRL_TXS_SHIFT
95035 #define USBHS_EPCR_TXS(x)                        USB_ENDPTCTRL_TXS(x)
95036 #define USBHS_EPCR_TXD_MASK                      USB_ENDPTCTRL_TXD_MASK
95037 #define USBHS_EPCR_TXD_SHIFT                     USB_ENDPTCTRL_TXD_SHIFT
95038 #define USBHS_EPCR_TXD(x)                        USB_ENDPTCTRL_TXD(x)
95039 #define USBHS_EPCR_TXT_MASK                      USB_ENDPTCTRL_TXT_MASK
95040 #define USBHS_EPCR_TXT_SHIFT                     USB_ENDPTCTRL_TXT_SHIFT
95041 #define USBHS_EPCR_TXT(x)                        USB_ENDPTCTRL_TXT(x)
95042 #define USBHS_EPCR_TXI_MASK                      USB_ENDPTCTRL_TXI_MASK
95043 #define USBHS_EPCR_TXI_SHIFT                     USB_ENDPTCTRL_TXI_SHIFT
95044 #define USBHS_EPCR_TXI(x)                        USB_ENDPTCTRL_TXI(x)
95045 #define USBHS_EPCR_TXR_MASK                      USB_ENDPTCTRL_TXR_MASK
95046 #define USBHS_EPCR_TXR_SHIFT                     USB_ENDPTCTRL_TXR_SHIFT
95047 #define USBHS_EPCR_TXR(x)                        USB_ENDPTCTRL_TXR(x)
95048 #define USBHS_EPCR_TXE_MASK                      USB_ENDPTCTRL_TXE_MASK
95049 #define USBHS_EPCR_TXE_SHIFT                     USB_ENDPTCTRL_TXE_SHIFT
95050 #define USBHS_EPCR_TXE(x)                        USB_ENDPTCTRL_TXE(x)
95051 #define USBHS_EPCR_COUNT                         USB_ENDPTCTRL_COUNT
95052 #define USBHS_Type                               USB_Type
95053 #define USBHS_BASE_ADDRS                         USB_BASE_ADDRS
95054 #define USBHS_IRQS                               { USB_OTG1_IRQn, USB_OTG2_IRQn }
95055 #define USBHS_IRQHandler                         USB_OTG1_IRQHandler
95056 #define USBHS_STACK_BASE_ADDRS                   { USB_OTG1_BASE, USB_OTG2_BASE }
95057 
95058 
95059 /*!
95060  * @}
95061  */ /* end of group USB_Peripheral_Access_Layer */
95062 
95063 
95064 /* ----------------------------------------------------------------------------
95065    -- USBHSDCD Peripheral Access Layer
95066    ---------------------------------------------------------------------------- */
95067 
95068 /*!
95069  * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
95070  * @{
95071  */
95072 
95073 /** USBHSDCD - Register Layout Typedef */
95074 typedef struct {
95075   __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
95076   __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
95077   __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
95078   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
95079   __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
95080   __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
95081   union {                                          /* offset: 0x18 */
95082     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
95083     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
95084   };
95085 } USBHSDCD_Type;
95086 
95087 /* ----------------------------------------------------------------------------
95088    -- USBHSDCD Register Masks
95089    ---------------------------------------------------------------------------- */
95090 
95091 /*!
95092  * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
95093  * @{
95094  */
95095 
95096 /*! @name CONTROL - Control register */
95097 /*! @{ */
95098 
95099 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
95100 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
95101 /*! IACK - Interrupt Acknowledge
95102  *  0b0..Do not clear the interrupt.
95103  *  0b1..Clear the IF bit (interrupt flag).
95104  */
95105 #define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
95106 
95107 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
95108 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
95109 /*! IF - Interrupt Flag
95110  *  0b0..No interrupt is pending.
95111  *  0b1..An interrupt is pending.
95112  */
95113 #define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
95114 
95115 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
95116 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
95117 /*! IE - Interrupt Enable
95118  *  0b0..Disable interrupts to the system.
95119  *  0b1..Enable interrupts to the system.
95120  */
95121 #define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
95122 
95123 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
95124 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
95125 /*! BC12 - BC12
95126  *  0b0..Compatible with BC1.1 (default)
95127  *  0b1..Compatible with BC1.2
95128  */
95129 #define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
95130 
95131 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
95132 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
95133 /*! START - Start Change Detection Sequence
95134  *  0b0..Do not start the sequence. Writes of this value have no effect.
95135  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
95136  */
95137 #define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
95138 
95139 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
95140 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
95141 /*! SR - Software Reset
95142  *  0b0..Do not perform a software reset.
95143  *  0b1..Perform a software reset.
95144  */
95145 #define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
95146 /*! @} */
95147 
95148 /*! @name CLOCK - Clock register */
95149 /*! @{ */
95150 
95151 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
95152 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
95153 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
95154  *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
95155  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
95156  */
95157 #define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
95158 
95159 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
95160 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
95161 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
95162  */
95163 #define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
95164 /*! @} */
95165 
95166 /*! @name STATUS - Status register */
95167 /*! @{ */
95168 
95169 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
95170 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
95171 /*! SEQ_RES - Charger Detection Sequence Results
95172  *  0b00..No results to report.
95173  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
95174  *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
95175  *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
95176  *        detection has completed.)
95177  *  0b11..Attached to a DCP.
95178  */
95179 #define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
95180 
95181 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
95182 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
95183 /*! SEQ_STAT - Charger Detection Sequence Status
95184  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
95185  *  0b01..Data pin contact detection is complete.
95186  *  0b10..Charging port detection is complete.
95187  *  0b11..Charger type detection is complete.
95188  */
95189 #define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
95190 
95191 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
95192 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
95193 /*! ERR - Error Flag
95194  *  0b0..No sequence errors.
95195  *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
95196  */
95197 #define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
95198 
95199 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
95200 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
95201 /*! TO - Timeout Flag
95202  *  0b0..The detection sequence has not been running for over 1s.
95203  *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
95204  */
95205 #define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
95206 
95207 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
95208 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
95209 /*! ACTIVE - Active Status Indicator
95210  *  0b0..The sequence is not running.
95211  *  0b1..The sequence is running.
95212  */
95213 #define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
95214 /*! @} */
95215 
95216 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
95217 /*! @{ */
95218 
95219 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
95220 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
95221 /*! PS - Phase Selection
95222  *  0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
95223  *        unexpected conditions on USB_DP and USB_DM pins. (Default)
95224  *  0b01..Reserved, not for customer use.
95225  *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
95226  *  0b11..Reserved, not for customer use.
95227  */
95228 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
95229 /*! @} */
95230 
95231 /*! @name TIMER0 - TIMER0 register */
95232 /*! @{ */
95233 
95234 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
95235 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
95236 /*! TUNITCON - Unit Connection Timer Elapse (in ms)
95237  */
95238 #define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
95239 
95240 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
95241 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
95242 /*! TSEQ_INIT - Sequence Initiation Time
95243  *  0b0000000000-0b1111111111..0ms - 1023ms
95244  */
95245 #define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
95246 /*! @} */
95247 
95248 /*! @name TIMER1 - TIMER1 register */
95249 /*! @{ */
95250 
95251 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
95252 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
95253 /*! TVDPSRC_ON - Time Period Comparator Enabled
95254  *  0b0000000001-0b1111111111..1ms - 1023ms
95255  */
95256 #define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
95257 
95258 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
95259 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
95260 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
95261  *  0b0000000001-0b1111111111..1ms - 1023ms
95262  */
95263 #define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
95264 /*! @} */
95265 
95266 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
95267 /*! @{ */
95268 
95269 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
95270 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
95271 /*! CHECK_DM - Time Before Check of D- Line
95272  *  0b0001-0b1111..1ms - 15ms
95273  */
95274 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
95275 
95276 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
95277 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
95278 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
95279  *  0b0000000001-0b1111111111..1ms - 1023ms
95280  */
95281 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
95282 /*! @} */
95283 
95284 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
95285 /*! @{ */
95286 
95287 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
95288 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
95289 /*! TVDMSRC_ON - TVDMSRC_ON
95290  *  0b0000000000-0b0000101000..0ms - 40ms
95291  */
95292 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
95293 
95294 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
95295 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
95296 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
95297  *  0b0000000001-0b1111111111..1ms - 1023ms
95298  */
95299 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
95300 /*! @} */
95301 
95302 
95303 /*!
95304  * @}
95305  */ /* end of group USBHSDCD_Register_Masks */
95306 
95307 
95308 /* USBHSDCD - Peripheral instance base addresses */
95309 /** Peripheral USBHSDCD1 base address */
95310 #define USBHSDCD1_BASE                           (0x40434800u)
95311 /** Peripheral USBHSDCD1 base pointer */
95312 #define USBHSDCD1                                ((USBHSDCD_Type *)USBHSDCD1_BASE)
95313 /** Peripheral USBHSDCD2 base address */
95314 #define USBHSDCD2_BASE                           (0x40438800u)
95315 /** Peripheral USBHSDCD2 base pointer */
95316 #define USBHSDCD2                                ((USBHSDCD_Type *)USBHSDCD2_BASE)
95317 /** Array initializer of USBHSDCD peripheral base addresses */
95318 #define USBHSDCD_BASE_ADDRS                      { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
95319 /** Array initializer of USBHSDCD peripheral base pointers */
95320 #define USBHSDCD_BASE_PTRS                       { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
95321 /* Backward compatibility */
95322 #define USBHSDCD_STACK_BASE_ADDRS                { USBHSDCD1_BASE, USBHSDCD2_BASE }
95323 
95324 
95325 /*!
95326  * @}
95327  */ /* end of group USBHSDCD_Peripheral_Access_Layer */
95328 
95329 
95330 /* ----------------------------------------------------------------------------
95331    -- USBNC Peripheral Access Layer
95332    ---------------------------------------------------------------------------- */
95333 
95334 /*!
95335  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
95336  * @{
95337  */
95338 
95339 /** USBNC - Register Layout Typedef */
95340 typedef struct {
95341   __IO uint32_t CTRL1;                             /**< USB OTG Control 1 Register, offset: 0x0 */
95342   __IO uint32_t CTRL2;                             /**< USB OTG Control 2 Register, offset: 0x4 */
95343        uint8_t RESERVED_0[8];
95344   __IO uint32_t HSIC_CTRL;                         /**< USB Host HSIC Control Register, offset: 0x10 */
95345 } USBNC_Type;
95346 
95347 /* ----------------------------------------------------------------------------
95348    -- USBNC Register Masks
95349    ---------------------------------------------------------------------------- */
95350 
95351 /*!
95352  * @addtogroup USBNC_Register_Masks USBNC Register Masks
95353  * @{
95354  */
95355 
95356 /*! @name CTRL1 - USB OTG Control 1 Register */
95357 /*! @{ */
95358 
95359 #define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
95360 #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
95361 /*! OVER_CUR_DIS - OVER_CUR_DIS
95362  *  0b1..Disables overcurrent detection
95363  *  0b0..Enables overcurrent detection
95364  */
95365 #define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
95366 
95367 #define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
95368 #define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
95369 /*! OVER_CUR_POL - OVER_CUR_POL
95370  *  0b1..Low active (low on this signal represents an overcurrent condition)
95371  *  0b0..High active (high on this signal represents an overcurrent condition)
95372  */
95373 #define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
95374 
95375 #define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
95376 #define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
95377 /*! PWR_POL - PWR_POL
95378  *  0b1..PMIC Power Pin is High active.
95379  *  0b0..PMIC Power Pin is Low active.
95380  */
95381 #define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
95382 
95383 #define USBNC_CTRL1_WIE_MASK                     (0x400U)
95384 #define USBNC_CTRL1_WIE_SHIFT                    (10U)
95385 /*! WIE - WIE
95386  *  0b1..Interrupt Enabled
95387  *  0b0..Interrupt Disabled
95388  */
95389 #define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
95390 
95391 #define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
95392 #define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
95393 /*! WKUP_SW_EN - WKUP_SW_EN
95394  *  0b1..Enable
95395  *  0b0..Disable
95396  */
95397 #define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
95398 
95399 #define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
95400 #define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
95401 /*! WKUP_SW - WKUP_SW
95402  *  0b1..Force wake-up
95403  *  0b0..Inactive
95404  */
95405 #define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
95406 
95407 #define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
95408 #define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
95409 /*! WKUP_ID_EN - WKUP_ID_EN
95410  *  0b1..Enable
95411  *  0b0..Disable
95412  */
95413 #define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
95414 
95415 #define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
95416 #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
95417 /*! WKUP_VBUS_EN - WKUP_VBUS_EN
95418  *  0b1..Enable
95419  *  0b0..Disable
95420  */
95421 #define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
95422 
95423 #define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
95424 #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
95425 /*! WKUP_DPDM_EN - Wake-up on DPDM change enable
95426  *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
95427  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
95428  */
95429 #define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
95430 
95431 #define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
95432 #define USBNC_CTRL1_WIR_SHIFT                    (31U)
95433 /*! WIR - WIR
95434  *  0b1..Wake-up Interrupt Request received
95435  *  0b0..No wake-up interrupt request received
95436  */
95437 #define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
95438 /*! @} */
95439 
95440 /*! @name CTRL2 - USB OTG Control 2 Register */
95441 /*! @{ */
95442 
95443 #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
95444 #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
95445 /*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL
95446  *  0b00..vbus_valid
95447  *  0b01..sess_valid
95448  *  0b10..sess_valid
95449  *  0b11..sess_valid
95450  */
95451 #define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
95452 
95453 #define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
95454 #define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
95455 /*! AUTURESUME_EN - Auto Resume Enable
95456  *  0b0..Default
95457  */
95458 #define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
95459 
95460 #define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
95461 #define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
95462 /*! LOWSPEED_EN - LOWSPEED_EN
95463  *  0b0..Default
95464  */
95465 #define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
95466 
95467 #define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
95468 #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
95469 /*! UTMI_CLK_VLD - UTMI_CLK_VLD
95470  *  0b0..Default
95471  */
95472 #define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
95473 /*! @} */
95474 
95475 /*! @name HSIC_CTRL - USB Host HSIC Control Register */
95476 /*! @{ */
95477 
95478 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK         (0x800U)
95479 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT        (11U)
95480 /*! HSIC_CLK_ON - HSIC_CLK_ON
95481  *  0b1..Active
95482  *  0b0..Inactive
95483  */
95484 #define USBNC_HSIC_CTRL_HSIC_CLK_ON(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
95485 
95486 #define USBNC_HSIC_CTRL_HSIC_EN_MASK             (0x1000U)
95487 #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT            (12U)
95488 /*! HSIC_EN - HSIC_EN
95489  *  0b1..Enabled
95490  *  0b0..Disabled
95491  */
95492 #define USBNC_HSIC_CTRL_HSIC_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
95493 
95494 #define USBNC_HSIC_CTRL_CLK_VLD_MASK             (0x80000000U)
95495 #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT            (31U)
95496 /*! CLK_VLD - CLK_VLD
95497  *  0b1..Valid
95498  *  0b0..Invalid
95499  */
95500 #define USBNC_HSIC_CTRL_CLK_VLD(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
95501 /*! @} */
95502 
95503 
95504 /*!
95505  * @}
95506  */ /* end of group USBNC_Register_Masks */
95507 
95508 
95509 /* USBNC - Peripheral instance base addresses */
95510 /** Peripheral USBNC_OTG1 base address */
95511 #define USBNC_OTG1_BASE                          (0x40430200u)
95512 /** Peripheral USBNC_OTG1 base pointer */
95513 #define USBNC_OTG1                               ((USBNC_Type *)USBNC_OTG1_BASE)
95514 /** Peripheral USBNC_OTG2 base address */
95515 #define USBNC_OTG2_BASE                          (0x4042C200u)
95516 /** Peripheral USBNC_OTG2 base pointer */
95517 #define USBNC_OTG2                               ((USBNC_Type *)USBNC_OTG2_BASE)
95518 /** Array initializer of USBNC peripheral base addresses */
95519 #define USBNC_BASE_ADDRS                         { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
95520 /** Array initializer of USBNC peripheral base pointers */
95521 #define USBNC_BASE_PTRS                          { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
95522 /* Backward compatibility */
95523 #define USB_OTGn_CTRL     CTRL1
95524 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK     USBNC_CTRL1_OVER_CUR_DIS_MASK
95525 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT     USBNC_CTRL1_OVER_CUR_DIS_SHIFT
95526 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)     USBNC_CTRL1_OVER_CUR_DIS(x)
95527 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK     USBNC_CTRL1_OVER_CUR_POL_MASK
95528 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT     USBNC_CTRL1_OVER_CUR_POL_SHIFT
95529 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)     USBNC_CTRL1_OVER_CUR_POL(x)
95530 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK     USBNC_CTRL1_PWR_POL_MASK
95531 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT     USBNC_CTRL1_PWR_POL_SHIFT
95532 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)     USBNC_CTRL1_PWR_POL(x)
95533 #define USBNC_USB_OTGn_CTRL_WIE_MASK     USBNC_CTRL1_WIE_MASK
95534 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT     USBNC_CTRL1_WIE_SHIFT
95535 #define USBNC_USB_OTGn_CTRL_WIE(x)     USBNC_CTRL1_WIE(x)
95536 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK     USBNC_CTRL1_WKUP_SW_EN_MASK
95537 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     USBNC_CTRL1_WKUP_SW_EN_SHIFT
95538 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)     USBNC_CTRL1_WKUP_SW_EN(x)
95539 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK     USBNC_CTRL1_WKUP_SW_MASK
95540 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT     USBNC_CTRL1_WKUP_SW_SHIFT
95541 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)     USBNC_CTRL1_WKUP_SW(x)
95542 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK     USBNC_CTRL1_WKUP_ID_EN_MASK
95543 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     USBNC_CTRL1_WKUP_ID_EN_SHIFT
95544 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)     USBNC_CTRL1_WKUP_ID_EN(x)
95545 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK     USBNC_CTRL1_WKUP_VBUS_EN_MASK
95546 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT     USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
95547 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)     USBNC_CTRL1_WKUP_VBUS_EN(x)
95548 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK     USBNC_CTRL1_WKUP_DPDM_EN_MASK
95549 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT     USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
95550 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)     USBNC_CTRL1_WKUP_DPDM_EN(x)
95551 #define USBNC_USB_OTGn_CTRL_WIR_MASK     USBNC_CTRL1_WIR_MASK
95552 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT     USBNC_CTRL1_WIR_SHIFT
95553 #define USBNC_USB_OTGn_CTRL_WIR(x)     USBNC_CTRL1_WIR(x)
95554 #define USBNC_STACK_BASE_ADDRS                { USBNC_OTG1_BASE, USBNC_OTG2_BASE }
95555 
95556 
95557 /*!
95558  * @}
95559  */ /* end of group USBNC_Peripheral_Access_Layer */
95560 
95561 
95562 /* ----------------------------------------------------------------------------
95563    -- USBPHY Peripheral Access Layer
95564    ---------------------------------------------------------------------------- */
95565 
95566 /*!
95567  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
95568  * @{
95569  */
95570 
95571 /** USBPHY - Register Layout Typedef */
95572 typedef struct {
95573   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
95574   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
95575   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
95576   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
95577   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
95578   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
95579   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
95580   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
95581   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
95582   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
95583   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
95584   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
95585   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
95586   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
95587   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
95588   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
95589   __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
95590        uint8_t RESERVED_0[12];
95591   __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
95592   __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
95593   __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
95594   __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
95595   __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
95596        uint8_t RESERVED_1[12];
95597   __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
95598   __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
95599   __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
95600   __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
95601   __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
95602        uint8_t RESERVED_2[28];
95603   __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
95604   __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
95605   __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
95606   __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
95607        uint8_t RESERVED_3[16];
95608   __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
95609   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
95610   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
95611   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
95612   __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
95613        uint8_t RESERVED_4[12];
95614   __IO uint32_t USB1_CHRG_DETECT;                  /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
95615   __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
95616   __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
95617   __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USB PHY Charger Detect Control Register, offset: 0xEC */
95618   __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
95619        uint8_t RESERVED_5[12];
95620   __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
95621   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
95622   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
95623   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
95624   __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
95625   __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
95626   __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
95627   __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
95628   __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
95629   __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
95630   __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
95631   __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
95632   __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
95633   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
95634   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
95635   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
95636 } USBPHY_Type;
95637 
95638 /* ----------------------------------------------------------------------------
95639    -- USBPHY Register Masks
95640    ---------------------------------------------------------------------------- */
95641 
95642 /*!
95643  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
95644  * @{
95645  */
95646 
95647 /*! @name PWD - USB PHY Power-Down Register */
95648 /*! @{ */
95649 
95650 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
95651 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
95652 /*! TXPWDFS - TXPWDFS
95653  *  0b0..Normal operation.
95654  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
95655  */
95656 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
95657 
95658 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
95659 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
95660 /*! TXPWDIBIAS - TXPWDIBIAS
95661  *  0b0..Normal operation
95662  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
95663  *       is in suspend mode. This effectively powers down the entire USB transmit path
95664  */
95665 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
95666 
95667 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
95668 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
95669 /*! TXPWDV2I - TXPWDV2I
95670  *  0b0..Normal operation.
95671  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
95672  */
95673 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
95674 
95675 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
95676 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
95677 /*! RXPWDENV - RXPWDENV
95678  *  0b0..Normal operation.
95679  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
95680  */
95681 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
95682 
95683 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
95684 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
95685 /*! RXPWD1PT1 - RXPWD1PT1
95686  *  0b0..Normal operation
95687  *  0b1..Power-down the USB full-speed differential receiver.
95688  */
95689 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
95690 
95691 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
95692 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
95693 /*! RXPWDDIFF - RXPWDDIFF
95694  *  0b0..Normal operation.
95695  *  0b1..Power-down the USB high-speed differential receiver
95696  */
95697 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
95698 
95699 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
95700 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
95701 /*! RXPWDRX - RXPWDRX
95702  *  0b0..Normal operation
95703  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
95704  */
95705 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
95706 /*! @} */
95707 
95708 /*! @name PWD_SET - USB PHY Power-Down Register */
95709 /*! @{ */
95710 
95711 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
95712 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
95713 /*! TXPWDFS - TXPWDFS
95714  */
95715 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
95716 
95717 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
95718 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
95719 /*! TXPWDIBIAS - TXPWDIBIAS
95720  */
95721 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
95722 
95723 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
95724 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
95725 /*! TXPWDV2I - TXPWDV2I
95726  */
95727 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
95728 
95729 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
95730 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
95731 /*! RXPWDENV - RXPWDENV
95732  */
95733 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
95734 
95735 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
95736 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
95737 /*! RXPWD1PT1 - RXPWD1PT1
95738  */
95739 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
95740 
95741 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
95742 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
95743 /*! RXPWDDIFF - RXPWDDIFF
95744  */
95745 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
95746 
95747 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
95748 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
95749 /*! RXPWDRX - RXPWDRX
95750  */
95751 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
95752 /*! @} */
95753 
95754 /*! @name PWD_CLR - USB PHY Power-Down Register */
95755 /*! @{ */
95756 
95757 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
95758 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
95759 /*! TXPWDFS - TXPWDFS
95760  */
95761 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
95762 
95763 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
95764 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
95765 /*! TXPWDIBIAS - TXPWDIBIAS
95766  */
95767 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
95768 
95769 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
95770 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
95771 /*! TXPWDV2I - TXPWDV2I
95772  */
95773 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
95774 
95775 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
95776 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
95777 /*! RXPWDENV - RXPWDENV
95778  */
95779 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
95780 
95781 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
95782 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
95783 /*! RXPWD1PT1 - RXPWD1PT1
95784  */
95785 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
95786 
95787 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
95788 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
95789 /*! RXPWDDIFF - RXPWDDIFF
95790  */
95791 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
95792 
95793 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
95794 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
95795 /*! RXPWDRX - RXPWDRX
95796  */
95797 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
95798 /*! @} */
95799 
95800 /*! @name PWD_TOG - USB PHY Power-Down Register */
95801 /*! @{ */
95802 
95803 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
95804 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
95805 /*! TXPWDFS - TXPWDFS
95806  */
95807 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
95808 
95809 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
95810 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
95811 /*! TXPWDIBIAS - TXPWDIBIAS
95812  */
95813 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
95814 
95815 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
95816 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
95817 /*! TXPWDV2I - TXPWDV2I
95818  */
95819 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
95820 
95821 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
95822 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
95823 /*! RXPWDENV - RXPWDENV
95824  */
95825 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
95826 
95827 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
95828 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
95829 /*! RXPWD1PT1 - RXPWD1PT1
95830  */
95831 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
95832 
95833 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
95834 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
95835 /*! RXPWDDIFF - RXPWDDIFF
95836  */
95837 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
95838 
95839 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
95840 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
95841 /*! RXPWDRX - RXPWDRX
95842  */
95843 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
95844 /*! @} */
95845 
95846 /*! @name TX - USB PHY Transmitter Control Register */
95847 /*! @{ */
95848 
95849 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
95850 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
95851 /*! D_CAL - D_CAL
95852  *  0b0000..Maximum current, approximately 19% above nominal.
95853  *  0b0111..Nominal
95854  *  0b1111..Minimum current, approximately 19% below nominal.
95855  */
95856 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
95857 
95858 #define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
95859 #define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
95860 /*! TXCAL45DN - TXCAL45DN
95861  */
95862 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
95863 
95864 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
95865 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
95866 /*! TXCAL45DP - TXCAL45DP
95867  */
95868 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
95869 /*! @} */
95870 
95871 /*! @name TX_SET - USB PHY Transmitter Control Register */
95872 /*! @{ */
95873 
95874 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
95875 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
95876 /*! D_CAL - D_CAL
95877  */
95878 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
95879 
95880 #define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
95881 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
95882 /*! TXCAL45DN - TXCAL45DN
95883  */
95884 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
95885 
95886 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
95887 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
95888 /*! TXCAL45DP - TXCAL45DP
95889  */
95890 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
95891 /*! @} */
95892 
95893 /*! @name TX_CLR - USB PHY Transmitter Control Register */
95894 /*! @{ */
95895 
95896 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
95897 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
95898 /*! D_CAL - D_CAL
95899  */
95900 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
95901 
95902 #define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
95903 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
95904 /*! TXCAL45DN - TXCAL45DN
95905  */
95906 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
95907 
95908 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
95909 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
95910 /*! TXCAL45DP - TXCAL45DP
95911  */
95912 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
95913 /*! @} */
95914 
95915 /*! @name TX_TOG - USB PHY Transmitter Control Register */
95916 /*! @{ */
95917 
95918 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
95919 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
95920 /*! D_CAL - D_CAL
95921  */
95922 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
95923 
95924 #define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
95925 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
95926 /*! TXCAL45DN - TXCAL45DN
95927  */
95928 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
95929 
95930 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
95931 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
95932 /*! TXCAL45DP - TXCAL45DP
95933  */
95934 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
95935 /*! @} */
95936 
95937 /*! @name RX - USB PHY Receiver Control Register */
95938 /*! @{ */
95939 
95940 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
95941 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
95942 /*! ENVADJ - ENVADJ
95943  *  0b000..Trip-Level Voltage is 0.1000 V
95944  *  0b001..Trip-Level Voltage is 0.1125 V
95945  *  0b010..Trip-Level Voltage is 0.1250 V
95946  *  0b011..Trip-Level Voltage is 0.0875 V
95947  *  0b1xx..Reserved
95948  */
95949 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
95950 
95951 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
95952 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
95953 /*! DISCONADJ - DISCONADJ
95954  *  0b000..Trip-Level Voltage is 0.56875 V
95955  *  0b001..Trip-Level Voltage is 0.55000 V
95956  *  0b010..Trip-Level Voltage is 0.58125 V
95957  *  0b011..Trip-Level Voltage is 0.60000 V
95958  *  0b1xx..Reserved
95959  */
95960 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
95961 
95962 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
95963 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
95964 /*! RXDBYPASS - RXDBYPASS
95965  *  0b0..Normal operation.
95966  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
95967  */
95968 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
95969 /*! @} */
95970 
95971 /*! @name RX_SET - USB PHY Receiver Control Register */
95972 /*! @{ */
95973 
95974 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
95975 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
95976 /*! ENVADJ - ENVADJ
95977  */
95978 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
95979 
95980 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
95981 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
95982 /*! DISCONADJ - DISCONADJ
95983  */
95984 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
95985 
95986 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
95987 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
95988 /*! RXDBYPASS - RXDBYPASS
95989  */
95990 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
95991 /*! @} */
95992 
95993 /*! @name RX_CLR - USB PHY Receiver Control Register */
95994 /*! @{ */
95995 
95996 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
95997 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
95998 /*! ENVADJ - ENVADJ
95999  */
96000 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
96001 
96002 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
96003 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
96004 /*! DISCONADJ - DISCONADJ
96005  */
96006 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
96007 
96008 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
96009 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
96010 /*! RXDBYPASS - RXDBYPASS
96011  */
96012 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
96013 /*! @} */
96014 
96015 /*! @name RX_TOG - USB PHY Receiver Control Register */
96016 /*! @{ */
96017 
96018 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
96019 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
96020 /*! ENVADJ - ENVADJ
96021  */
96022 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
96023 
96024 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
96025 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
96026 /*! DISCONADJ - DISCONADJ
96027  */
96028 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
96029 
96030 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
96031 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
96032 /*! RXDBYPASS - RXDBYPASS
96033  */
96034 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
96035 /*! @} */
96036 
96037 /*! @name CTRL - USB PHY General Control Register */
96038 /*! @{ */
96039 
96040 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
96041 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
96042 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96043  */
96044 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
96045 
96046 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
96047 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
96048 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96049  */
96050 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
96051 
96052 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
96053 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
96054 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96055  */
96056 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
96057 
96058 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
96059 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
96060 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96061  */
96062 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
96063 
96064 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
96065 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
96066 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96067  *  0b0..Disables 200kohm pullup resistors on DP and DN pins
96068  *  0b1..Enables 200kohm pullup resistors on DP and DN pins
96069  */
96070 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
96071 
96072 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
96073 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
96074 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96075  */
96076 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
96077 
96078 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
96079 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
96080 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96081  */
96082 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
96083 
96084 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
96085 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
96086 /*! ENOTGIDDETECT - ENOTGIDDETECT
96087  */
96088 #define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
96089 
96090 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
96091 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
96092 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96093  */
96094 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
96095 
96096 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
96097 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
96098 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96099  */
96100 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
96101 
96102 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
96103 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
96104 /*! RESUME_IRQ - RESUME_IRQ
96105  */
96106 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
96107 
96108 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
96109 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
96110 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96111  */
96112 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
96113 
96114 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
96115 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
96116 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96117  */
96118 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
96119 
96120 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
96121 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
96122 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96123  */
96124 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
96125 
96126 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
96127 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
96128 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96129  */
96130 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
96131 
96132 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
96133 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
96134 /*! ENIRQWAKEUP - ENIRQWAKEUP
96135  */
96136 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
96137 
96138 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
96139 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
96140 /*! WAKEUP_IRQ - WAKEUP_IRQ
96141  */
96142 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
96143 
96144 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
96145 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
96146 /*! AUTORESUME_EN - AUTORESUME_EN
96147  */
96148 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
96149 
96150 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
96151 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
96152 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96153  */
96154 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
96155 
96156 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
96157 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
96158 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96159  */
96160 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
96161 
96162 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
96163 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
96164 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96165  */
96166 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
96167 
96168 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK            (0x400000U)
96169 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           (22U)
96170 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96171  */
96172 #define USBPHY_CTRL_ENIDCHG_WKUP(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
96173 
96174 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
96175 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
96176 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96177  */
96178 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
96179 
96180 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
96181 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
96182 /*! FSDLL_RST_EN - FSDLL_RST_EN
96183  */
96184 #define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
96185 
96186 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
96187 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
96188 /*! OTG_ID_VALUE - OTG_ID_VALUE
96189  */
96190 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
96191 
96192 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
96193 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
96194 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96195  */
96196 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
96197 
96198 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
96199 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
96200 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96201  */
96202 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
96203 
96204 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
96205 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
96206 /*! CLKGATE - CLKGATE
96207  */
96208 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
96209 
96210 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
96211 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
96212 /*! SFTRST - SFTRST
96213  */
96214 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
96215 /*! @} */
96216 
96217 /*! @name CTRL_SET - USB PHY General Control Register */
96218 /*! @{ */
96219 
96220 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96221 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96222 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96223  */
96224 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
96225 
96226 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
96227 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
96228 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96229  */
96230 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
96231 
96232 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
96233 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
96234 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96235  */
96236 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
96237 
96238 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96239 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96240 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96241  */
96242 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
96243 
96244 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
96245 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
96246 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96247  */
96248 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
96249 
96250 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
96251 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
96252 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96253  */
96254 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
96255 
96256 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
96257 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
96258 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96259  */
96260 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
96261 
96262 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
96263 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
96264 /*! ENOTGIDDETECT - ENOTGIDDETECT
96265  */
96266 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
96267 
96268 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
96269 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
96270 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96271  */
96272 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
96273 
96274 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
96275 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
96276 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96277  */
96278 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
96279 
96280 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
96281 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
96282 /*! RESUME_IRQ - RESUME_IRQ
96283  */
96284 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
96285 
96286 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
96287 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
96288 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96289  */
96290 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
96291 
96292 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
96293 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
96294 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96295  */
96296 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
96297 
96298 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
96299 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
96300 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96301  */
96302 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
96303 
96304 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
96305 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
96306 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96307  */
96308 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
96309 
96310 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
96311 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
96312 /*! ENIRQWAKEUP - ENIRQWAKEUP
96313  */
96314 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
96315 
96316 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
96317 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
96318 /*! WAKEUP_IRQ - WAKEUP_IRQ
96319  */
96320 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
96321 
96322 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
96323 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
96324 /*! AUTORESUME_EN - AUTORESUME_EN
96325  */
96326 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
96327 
96328 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
96329 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
96330 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96331  */
96332 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
96333 
96334 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
96335 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
96336 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96337  */
96338 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
96339 
96340 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
96341 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
96342 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96343  */
96344 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
96345 
96346 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        (0x400000U)
96347 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       (22U)
96348 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96349  */
96350 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
96351 
96352 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
96353 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
96354 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96355  */
96356 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
96357 
96358 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
96359 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
96360 /*! FSDLL_RST_EN - FSDLL_RST_EN
96361  */
96362 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
96363 
96364 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
96365 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
96366 /*! OTG_ID_VALUE - OTG_ID_VALUE
96367  */
96368 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
96369 
96370 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
96371 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
96372 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96373  */
96374 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
96375 
96376 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
96377 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
96378 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96379  */
96380 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
96381 
96382 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
96383 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
96384 /*! CLKGATE - CLKGATE
96385  */
96386 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
96387 
96388 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
96389 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
96390 /*! SFTRST - SFTRST
96391  */
96392 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
96393 /*! @} */
96394 
96395 /*! @name CTRL_CLR - USB PHY General Control Register */
96396 /*! @{ */
96397 
96398 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96399 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96400 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96401  */
96402 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
96403 
96404 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
96405 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
96406 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96407  */
96408 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
96409 
96410 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
96411 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
96412 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96413  */
96414 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
96415 
96416 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96417 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96418 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96419  */
96420 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
96421 
96422 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
96423 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
96424 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96425  */
96426 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
96427 
96428 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
96429 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
96430 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96431  */
96432 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
96433 
96434 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
96435 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
96436 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96437  */
96438 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
96439 
96440 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
96441 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
96442 /*! ENOTGIDDETECT - ENOTGIDDETECT
96443  */
96444 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
96445 
96446 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
96447 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
96448 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96449  */
96450 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
96451 
96452 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
96453 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
96454 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96455  */
96456 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
96457 
96458 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
96459 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
96460 /*! RESUME_IRQ - RESUME_IRQ
96461  */
96462 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
96463 
96464 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
96465 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
96466 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96467  */
96468 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
96469 
96470 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
96471 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
96472 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96473  */
96474 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
96475 
96476 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
96477 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
96478 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96479  */
96480 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
96481 
96482 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
96483 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
96484 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96485  */
96486 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
96487 
96488 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
96489 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
96490 /*! ENIRQWAKEUP - ENIRQWAKEUP
96491  */
96492 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
96493 
96494 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
96495 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
96496 /*! WAKEUP_IRQ - WAKEUP_IRQ
96497  */
96498 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
96499 
96500 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
96501 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
96502 /*! AUTORESUME_EN - AUTORESUME_EN
96503  */
96504 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
96505 
96506 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
96507 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
96508 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96509  */
96510 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
96511 
96512 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
96513 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
96514 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96515  */
96516 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
96517 
96518 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
96519 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
96520 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96521  */
96522 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
96523 
96524 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        (0x400000U)
96525 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       (22U)
96526 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96527  */
96528 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
96529 
96530 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
96531 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
96532 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96533  */
96534 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
96535 
96536 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
96537 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
96538 /*! FSDLL_RST_EN - FSDLL_RST_EN
96539  */
96540 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
96541 
96542 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
96543 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
96544 /*! OTG_ID_VALUE - OTG_ID_VALUE
96545  */
96546 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
96547 
96548 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
96549 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
96550 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96551  */
96552 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
96553 
96554 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
96555 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
96556 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96557  */
96558 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
96559 
96560 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
96561 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
96562 /*! CLKGATE - CLKGATE
96563  */
96564 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
96565 
96566 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
96567 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
96568 /*! SFTRST - SFTRST
96569  */
96570 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
96571 /*! @} */
96572 
96573 /*! @name CTRL_TOG - USB PHY General Control Register */
96574 /*! @{ */
96575 
96576 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
96577 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
96578 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
96579  */
96580 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
96581 
96582 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
96583 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
96584 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
96585  */
96586 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
96587 
96588 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
96589 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
96590 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
96591  */
96592 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
96593 
96594 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
96595 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
96596 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
96597  */
96598 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
96599 
96600 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
96601 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
96602 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
96603  */
96604 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
96605 
96606 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
96607 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
96608 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
96609  */
96610 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
96611 
96612 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
96613 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
96614 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
96615  */
96616 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
96617 
96618 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
96619 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
96620 /*! ENOTGIDDETECT - ENOTGIDDETECT
96621  */
96622 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
96623 
96624 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
96625 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
96626 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
96627  */
96628 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
96629 
96630 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
96631 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
96632 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
96633  */
96634 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
96635 
96636 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
96637 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
96638 /*! RESUME_IRQ - RESUME_IRQ
96639  */
96640 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
96641 
96642 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
96643 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
96644 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
96645  */
96646 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
96647 
96648 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
96649 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
96650 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
96651  */
96652 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
96653 
96654 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
96655 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
96656 /*! ENUTMILEVEL2 - ENUTMILEVEL2
96657  */
96658 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
96659 
96660 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
96661 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
96662 /*! ENUTMILEVEL3 - ENUTMILEVEL3
96663  */
96664 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
96665 
96666 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
96667 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
96668 /*! ENIRQWAKEUP - ENIRQWAKEUP
96669  */
96670 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
96671 
96672 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
96673 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
96674 /*! WAKEUP_IRQ - WAKEUP_IRQ
96675  */
96676 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
96677 
96678 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
96679 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
96680 /*! AUTORESUME_EN - AUTORESUME_EN
96681  */
96682 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
96683 
96684 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
96685 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
96686 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
96687  */
96688 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
96689 
96690 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
96691 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
96692 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
96693  */
96694 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
96695 
96696 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
96697 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
96698 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
96699  */
96700 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
96701 
96702 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        (0x400000U)
96703 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       (22U)
96704 /*! ENIDCHG_WKUP - ENIDCHG_WKUP
96705  */
96706 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
96707 
96708 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
96709 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
96710 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
96711  */
96712 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
96713 
96714 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
96715 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
96716 /*! FSDLL_RST_EN - FSDLL_RST_EN
96717  */
96718 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
96719 
96720 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
96721 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
96722 /*! OTG_ID_VALUE - OTG_ID_VALUE
96723  */
96724 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
96725 
96726 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
96727 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
96728 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
96729  */
96730 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
96731 
96732 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
96733 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
96734 /*! UTMI_SUSPENDM - UTMI_SUSPENDM
96735  */
96736 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
96737 
96738 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
96739 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
96740 /*! CLKGATE - CLKGATE
96741  */
96742 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
96743 
96744 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
96745 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
96746 /*! SFTRST - SFTRST
96747  */
96748 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
96749 /*! @} */
96750 
96751 /*! @name STATUS - USB PHY Status Register */
96752 /*! @{ */
96753 
96754 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
96755 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
96756 /*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS
96757  *  0b0..USB cable disconnect has not been detected at the local host
96758  *  0b1..USB cable disconnect has been detected at the local host
96759  */
96760 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
96761 
96762 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
96763 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
96764 /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
96765  *  0b0..No attachment to a USB host is detected
96766  *  0b1..Cable attachment to a USB host is detected
96767  */
96768 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
96769 
96770 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
96771 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
96772 /*! OTGID_STATUS - OTGID_STATUS
96773  */
96774 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
96775 
96776 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
96777 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
96778 /*! RESUME_STATUS - RESUME_STATUS
96779  */
96780 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
96781 /*! @} */
96782 
96783 /*! @name DEBUG - USB PHY Debug Register */
96784 /*! @{ */
96785 
96786 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
96787 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
96788 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
96789  */
96790 #define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
96791 
96792 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
96793 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
96794 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
96795  */
96796 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
96797 
96798 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
96799 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
96800 /*! HSTPULLDOWN - HSTPULLDOWN
96801  */
96802 #define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
96803 
96804 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
96805 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
96806 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
96807  */
96808 #define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
96809 
96810 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
96811 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
96812 /*! TX2RXCOUNT - TX2RXCOUNT
96813  */
96814 #define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
96815 
96816 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
96817 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
96818 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
96819  */
96820 #define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
96821 
96822 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
96823 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
96824 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
96825  */
96826 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
96827 
96828 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
96829 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
96830 /*! ENSQUELCHRESET - ENSQUELCHRESET
96831  */
96832 #define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
96833 
96834 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
96835 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
96836 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
96837  */
96838 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
96839 
96840 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
96841 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
96842 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
96843  */
96844 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
96845 
96846 #define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
96847 #define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
96848 /*! CLKGATE - CLKGATE
96849  */
96850 #define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
96851 /*! @} */
96852 
96853 /*! @name DEBUG_SET - USB PHY Debug Register */
96854 /*! @{ */
96855 
96856 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
96857 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
96858 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
96859  */
96860 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
96861 
96862 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
96863 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
96864 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
96865  */
96866 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
96867 
96868 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
96869 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
96870 /*! HSTPULLDOWN - HSTPULLDOWN
96871  */
96872 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
96873 
96874 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
96875 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
96876 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
96877  */
96878 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
96879 
96880 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
96881 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
96882 /*! TX2RXCOUNT - TX2RXCOUNT
96883  */
96884 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
96885 
96886 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
96887 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
96888 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
96889  */
96890 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
96891 
96892 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
96893 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
96894 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
96895  */
96896 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
96897 
96898 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
96899 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
96900 /*! ENSQUELCHRESET - ENSQUELCHRESET
96901  */
96902 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
96903 
96904 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
96905 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
96906 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
96907  */
96908 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
96909 
96910 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
96911 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
96912 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
96913  */
96914 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
96915 
96916 #define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
96917 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
96918 /*! CLKGATE - CLKGATE
96919  */
96920 #define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
96921 /*! @} */
96922 
96923 /*! @name DEBUG_CLR - USB PHY Debug Register */
96924 /*! @{ */
96925 
96926 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
96927 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
96928 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
96929  */
96930 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
96931 
96932 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
96933 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
96934 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
96935  */
96936 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
96937 
96938 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
96939 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
96940 /*! HSTPULLDOWN - HSTPULLDOWN
96941  */
96942 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
96943 
96944 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
96945 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
96946 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
96947  */
96948 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
96949 
96950 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
96951 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
96952 /*! TX2RXCOUNT - TX2RXCOUNT
96953  */
96954 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
96955 
96956 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
96957 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
96958 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
96959  */
96960 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
96961 
96962 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
96963 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
96964 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
96965  */
96966 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
96967 
96968 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
96969 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
96970 /*! ENSQUELCHRESET - ENSQUELCHRESET
96971  */
96972 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
96973 
96974 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
96975 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
96976 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
96977  */
96978 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
96979 
96980 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
96981 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
96982 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
96983  */
96984 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
96985 
96986 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
96987 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
96988 /*! CLKGATE - CLKGATE
96989  */
96990 #define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
96991 /*! @} */
96992 
96993 /*! @name DEBUG_TOG - USB PHY Debug Register */
96994 /*! @{ */
96995 
96996 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
96997 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
96998 /*! OTGIDPIOLOCK - OTGIDPIOLOCK
96999  */
97000 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
97001 
97002 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
97003 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
97004 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
97005  */
97006 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
97007 
97008 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
97009 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
97010 /*! HSTPULLDOWN - HSTPULLDOWN
97011  */
97012 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
97013 
97014 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
97015 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
97016 /*! ENHSTPULLDOWN - ENHSTPULLDOWN
97017  */
97018 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
97019 
97020 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
97021 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
97022 /*! TX2RXCOUNT - TX2RXCOUNT
97023  */
97024 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
97025 
97026 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
97027 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
97028 /*! ENTX2RXCOUNT - ENTX2RXCOUNT
97029  */
97030 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
97031 
97032 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
97033 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
97034 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
97035  */
97036 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
97037 
97038 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
97039 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
97040 /*! ENSQUELCHRESET - ENSQUELCHRESET
97041  */
97042 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
97043 
97044 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
97045 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
97046 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
97047  */
97048 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
97049 
97050 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
97051 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
97052 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
97053  */
97054 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
97055 
97056 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
97057 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
97058 /*! CLKGATE - CLKGATE
97059  */
97060 #define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
97061 /*! @} */
97062 
97063 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
97064 /*! @{ */
97065 
97066 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
97067 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
97068 /*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT
97069  */
97070 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
97071 
97072 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
97073 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
97074 /*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT
97075  */
97076 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
97077 
97078 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
97079 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
97080 /*! SQUELCH_COUNT - SQUELCH_COUNT
97081  */
97082 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
97083 /*! @} */
97084 
97085 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
97086 /*! @{ */
97087 
97088 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
97089 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
97090 /*! ENTAILADJVD - ENTAILADJVD
97091  *  0b00..Delay is nominal
97092  *  0b01..Delay is +20%
97093  *  0b10..Delay is -20%
97094  *  0b11..Delay is -40%
97095  */
97096 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
97097 
97098 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97099 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97100 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97101  */
97102 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)
97103 
97104 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97105 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97106 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97107  */
97108 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)
97109 
97110 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
97111 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT  (17U)
97112 /*! USB2_REFBIAS_LOWPWR - to be added
97113  */
97114 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)
97115 
97116 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
97117 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
97118 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97119  */
97120 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
97121 
97122 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
97123 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
97124 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97125  */
97126 #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
97127 /*! @} */
97128 
97129 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
97130 /*! @{ */
97131 
97132 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
97133 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
97134 /*! ENTAILADJVD - ENTAILADJVD
97135  */
97136 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
97137 
97138 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97139 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97140 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97141  */
97142 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)
97143 
97144 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97145 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97146 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97147  */
97148 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)
97149 
97150 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97151 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97152 /*! USB2_REFBIAS_LOWPWR - to be added
97153  */
97154 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)
97155 
97156 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97157 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97158 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97159  */
97160 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
97161 
97162 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
97163 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
97164 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97165  */
97166 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
97167 /*! @} */
97168 
97169 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
97170 /*! @{ */
97171 
97172 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
97173 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
97174 /*! ENTAILADJVD - ENTAILADJVD
97175  */
97176 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
97177 
97178 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97179 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97180 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97181  */
97182 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)
97183 
97184 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97185 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97186 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97187  */
97188 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)
97189 
97190 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97191 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97192 /*! USB2_REFBIAS_LOWPWR - to be added
97193  */
97194 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)
97195 
97196 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97197 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97198 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97199  */
97200 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
97201 
97202 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
97203 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
97204 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97205  */
97206 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
97207 /*! @} */
97208 
97209 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
97210 /*! @{ */
97211 
97212 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
97213 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
97214 /*! ENTAILADJVD - ENTAILADJVD
97215  */
97216 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
97217 
97218 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
97219 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
97220 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
97221  */
97222 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)
97223 
97224 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
97225 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
97226 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
97227  */
97228 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)
97229 
97230 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
97231 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
97232 /*! USB2_REFBIAS_LOWPWR - to be added
97233  */
97234 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)
97235 
97236 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
97237 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
97238 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
97239  */
97240 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
97241 
97242 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
97243 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
97244 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy
97245  */
97246 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
97247 /*! @} */
97248 
97249 /*! @name VERSION - UTMI RTL Version */
97250 /*! @{ */
97251 
97252 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
97253 #define USBPHY_VERSION_STEP_SHIFT                (0U)
97254 /*! STEP - STEP
97255  */
97256 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
97257 
97258 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
97259 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
97260 /*! MINOR - MINOR
97261  */
97262 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
97263 
97264 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
97265 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
97266 /*! MAJOR - MAJOR
97267  */
97268 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
97269 /*! @} */
97270 
97271 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
97272 /*! @{ */
97273 
97274 #define USBPHY_PLL_SIC_PLL_POSTDIV_MASK          (0x1CU)
97275 #define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT         (2U)
97276 /*! PLL_POSTDIV - PLL_POSTDIV
97277  */
97278 #define USBPHY_PLL_SIC_PLL_POSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
97279 
97280 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
97281 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
97282 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97283  */
97284 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
97285 
97286 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
97287 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
97288 /*! PLL_POWER - PLL_POWER
97289  */
97290 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
97291 
97292 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
97293 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
97294 /*! PLL_ENABLE - PLL_ENABLE
97295  */
97296 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
97297 
97298 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
97299 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
97300 /*! PLL_BYPASS - PLL_BYPASS
97301  */
97302 #define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
97303 
97304 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
97305 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
97306 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97307  *  0b0..Selects PLL_POWER to control the reference bias
97308  *  0b1..Selects REFBIAS_PWD to control the reference bias.
97309  */
97310 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
97311 
97312 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
97313 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
97314 /*! REFBIAS_PWD - Power down the reference bias
97315  */
97316 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
97317 
97318 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
97319 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
97320 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97321  */
97322 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
97323 
97324 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
97325 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
97326 /*! PLL_DIV_SEL - PLL_DIV_SEL
97327  *  0b000..Divide by 13
97328  *  0b001..Divide by 15
97329  *  0b010..Divide by 16
97330  *  0b011..Divide by 20
97331  *  0b100..Divide by 22
97332  *  0b101..Divide by 25
97333  *  0b110..Divide by 30
97334  *  0b111..Divide by 240
97335  */
97336 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
97337 
97338 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
97339 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
97340 /*! PLL_LOCK - PLL_LOCK
97341  *  0b0..PLL is not currently locked
97342  *  0b1..PLL is currently locked
97343  */
97344 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
97345 /*! @} */
97346 
97347 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
97348 /*! @{ */
97349 
97350 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK      (0x1CU)
97351 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT     (2U)
97352 /*! PLL_POSTDIV - PLL_POSTDIV
97353  */
97354 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)
97355 
97356 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
97357 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
97358 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97359  */
97360 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
97361 
97362 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
97363 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
97364 /*! PLL_POWER - PLL_POWER
97365  */
97366 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
97367 
97368 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
97369 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
97370 /*! PLL_ENABLE - PLL_ENABLE
97371  */
97372 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
97373 
97374 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
97375 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
97376 /*! PLL_BYPASS - PLL_BYPASS
97377  */
97378 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
97379 
97380 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
97381 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
97382 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97383  */
97384 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
97385 
97386 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
97387 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
97388 /*! REFBIAS_PWD - Power down the reference bias
97389  */
97390 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
97391 
97392 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
97393 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
97394 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97395  */
97396 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
97397 
97398 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
97399 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
97400 /*! PLL_DIV_SEL - PLL_DIV_SEL
97401  */
97402 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
97403 
97404 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
97405 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
97406 /*! PLL_LOCK - PLL_LOCK
97407  */
97408 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
97409 /*! @} */
97410 
97411 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
97412 /*! @{ */
97413 
97414 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK      (0x1CU)
97415 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT     (2U)
97416 /*! PLL_POSTDIV - PLL_POSTDIV
97417  */
97418 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)
97419 
97420 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
97421 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
97422 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97423  */
97424 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
97425 
97426 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
97427 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
97428 /*! PLL_POWER - PLL_POWER
97429  */
97430 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
97431 
97432 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
97433 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
97434 /*! PLL_ENABLE - PLL_ENABLE
97435  */
97436 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
97437 
97438 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
97439 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
97440 /*! PLL_BYPASS - PLL_BYPASS
97441  */
97442 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
97443 
97444 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
97445 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
97446 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97447  */
97448 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
97449 
97450 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
97451 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
97452 /*! REFBIAS_PWD - Power down the reference bias
97453  */
97454 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
97455 
97456 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
97457 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
97458 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97459  */
97460 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
97461 
97462 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
97463 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
97464 /*! PLL_DIV_SEL - PLL_DIV_SEL
97465  */
97466 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
97467 
97468 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
97469 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
97470 /*! PLL_LOCK - PLL_LOCK
97471  */
97472 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
97473 /*! @} */
97474 
97475 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
97476 /*! @{ */
97477 
97478 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK      (0x1CU)
97479 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT     (2U)
97480 /*! PLL_POSTDIV - PLL_POSTDIV
97481  */
97482 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)
97483 
97484 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
97485 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
97486 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
97487  */
97488 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
97489 
97490 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
97491 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
97492 /*! PLL_POWER - PLL_POWER
97493  */
97494 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
97495 
97496 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
97497 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
97498 /*! PLL_ENABLE - PLL_ENABLE
97499  */
97500 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
97501 
97502 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
97503 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
97504 /*! PLL_BYPASS - PLL_BYPASS
97505  */
97506 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
97507 
97508 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
97509 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
97510 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
97511  */
97512 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
97513 
97514 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
97515 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
97516 /*! REFBIAS_PWD - Power down the reference bias
97517  */
97518 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
97519 
97520 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
97521 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
97522 /*! PLL_REG_ENABLE - PLL_REG_ENABLE
97523  */
97524 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
97525 
97526 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
97527 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
97528 /*! PLL_DIV_SEL - PLL_DIV_SEL
97529  */
97530 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
97531 
97532 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
97533 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
97534 /*! PLL_LOCK - PLL_LOCK
97535  */
97536 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
97537 /*! @} */
97538 
97539 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
97540 /*! @{ */
97541 
97542 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
97543 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
97544 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
97545  *  0b000..4.0 V
97546  *  0b001..4.1 V
97547  *  0b010..4.2 V
97548  *  0b011..4.3 V
97549  *  0b100..4.4 V (Default)
97550  *  0b101..4.5 V
97551  *  0b110..4.6 V
97552  *  0b111..4.7 V
97553  */
97554 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
97555 
97556 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
97557 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
97558 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
97559  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
97560  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
97561  */
97562 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
97563 
97564 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
97565 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
97566 /*! SESSEND_OVERRIDE - Override value for SESSEND
97567  */
97568 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
97569 
97570 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
97571 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
97572 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
97573  */
97574 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
97575 
97576 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
97577 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
97578 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
97579  */
97580 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
97581 
97582 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
97583 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
97584 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
97585  */
97586 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
97587 
97588 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
97589 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
97590 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97591  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
97592  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
97593  */
97594 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
97595 
97596 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
97597 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
97598 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97599  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
97600  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
97601  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
97602  *  0b11..Reserved, do not use
97603  */
97604 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
97605 
97606 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
97607 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
97608 /*! ID_OVERRIDE_EN - TBA
97609  */
97610 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
97611 
97612 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
97613 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
97614 /*! ID_OVERRIDE - TBA
97615  */
97616 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
97617 
97618 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
97619 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
97620 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
97621  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
97622  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
97623  */
97624 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
97625 
97626 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
97627 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
97628 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
97629  *  0b000..Powers down the VBUS_VALID comparator
97630  *  0b001..Enables the SESS_VALID comparator (default)
97631  *  0b010..Enables the 3Vdetect (default)
97632  */
97633 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
97634 
97635 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
97636 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
97637 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
97638  *  0b0..VBUS discharge resistor is disabled (Default)
97639  *  0b1..VBUS discharge resistor is enabled
97640  */
97641 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
97642 
97643 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
97644 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
97645 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
97646  *  0b0..Disable resistive charger detection resistors on DP and DP
97647  *  0b1..Enable resistive charger detection resistors on DP and DP
97648  */
97649 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
97650 /*! @} */
97651 
97652 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
97653 /*! @{ */
97654 
97655 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
97656 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
97657 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
97658  */
97659 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
97660 
97661 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
97662 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
97663 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
97664  */
97665 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
97666 
97667 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
97668 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
97669 /*! SESSEND_OVERRIDE - Override value for SESSEND
97670  */
97671 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
97672 
97673 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
97674 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
97675 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
97676  */
97677 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
97678 
97679 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
97680 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
97681 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
97682  */
97683 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
97684 
97685 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
97686 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
97687 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
97688  */
97689 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
97690 
97691 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
97692 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
97693 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97694  */
97695 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
97696 
97697 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
97698 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
97699 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97700  */
97701 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
97702 
97703 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
97704 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
97705 /*! ID_OVERRIDE_EN - TBA
97706  */
97707 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
97708 
97709 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
97710 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
97711 /*! ID_OVERRIDE - TBA
97712  */
97713 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
97714 
97715 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
97716 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
97717 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
97718  */
97719 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
97720 
97721 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
97722 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
97723 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
97724  */
97725 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
97726 
97727 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
97728 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
97729 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
97730  */
97731 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
97732 
97733 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
97734 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
97735 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
97736  */
97737 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
97738 /*! @} */
97739 
97740 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
97741 /*! @{ */
97742 
97743 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
97744 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
97745 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
97746  */
97747 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
97748 
97749 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
97750 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
97751 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
97752  */
97753 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
97754 
97755 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
97756 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
97757 /*! SESSEND_OVERRIDE - Override value for SESSEND
97758  */
97759 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
97760 
97761 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
97762 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
97763 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
97764  */
97765 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
97766 
97767 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
97768 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
97769 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
97770  */
97771 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
97772 
97773 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
97774 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
97775 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
97776  */
97777 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
97778 
97779 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
97780 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
97781 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97782  */
97783 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
97784 
97785 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
97786 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
97787 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97788  */
97789 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
97790 
97791 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
97792 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
97793 /*! ID_OVERRIDE_EN - TBA
97794  */
97795 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
97796 
97797 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
97798 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
97799 /*! ID_OVERRIDE - TBA
97800  */
97801 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
97802 
97803 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
97804 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
97805 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
97806  */
97807 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
97808 
97809 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
97810 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
97811 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
97812  */
97813 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
97814 
97815 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
97816 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
97817 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
97818  */
97819 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
97820 
97821 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
97822 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
97823 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
97824  */
97825 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
97826 /*! @} */
97827 
97828 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
97829 /*! @{ */
97830 
97831 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
97832 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
97833 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
97834  */
97835 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
97836 
97837 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
97838 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
97839 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
97840  */
97841 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
97842 
97843 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
97844 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
97845 /*! SESSEND_OVERRIDE - Override value for SESSEND
97846  */
97847 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
97848 
97849 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
97850 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
97851 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid
97852  */
97853 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
97854 
97855 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
97856 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
97857 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid
97858  */
97859 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
97860 
97861 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
97862 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
97863 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
97864  */
97865 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
97866 
97867 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
97868 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
97869 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97870  */
97871 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
97872 
97873 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
97874 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
97875 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
97876  */
97877 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
97878 
97879 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
97880 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
97881 /*! ID_OVERRIDE_EN - TBA
97882  */
97883 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
97884 
97885 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
97886 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
97887 /*! ID_OVERRIDE - TBA
97888  */
97889 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
97890 
97891 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
97892 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
97893 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
97894  */
97895 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
97896 
97897 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
97898 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
97899 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
97900  */
97901 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
97902 
97903 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
97904 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
97905 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
97906  */
97907 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
97908 
97909 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
97910 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
97911 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
97912  */
97913 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
97914 /*! @} */
97915 
97916 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
97917 /*! @{ */
97918 
97919 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
97920 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
97921 /*! SESSEND - Session End indicator
97922  *  0b0..The VBUS voltage is above the Session Valid threshold
97923  *  0b1..The VBUS voltage is below the Session Valid threshold
97924  */
97925 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
97926 
97927 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
97928 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
97929 /*! BVALID - B-Device Session Valid status
97930  *  0b0..The VBUS voltage is below the Session Valid threshold
97931  *  0b1..The VBUS voltage is above the Session Valid threshold
97932  */
97933 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
97934 
97935 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
97936 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
97937 /*! AVALID - A-Device Session Valid status
97938  *  0b0..The VBUS voltage is below the Session Valid threshold
97939  *  0b1..The VBUS voltage is above the Session Valid threshold
97940  */
97941 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
97942 
97943 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
97944 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
97945 /*! VBUS_VALID - VBUS voltage status
97946  *  0b0..VBUS is below the comparator threshold
97947  *  0b1..VBUS is above the comparator threshold
97948  */
97949 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
97950 
97951 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
97952 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
97953 /*! VBUS_VALID_3V - VBUS_VALID_3V detector status
97954  *  0b0..VBUS voltage is below VBUS_VALID_3V threshold
97955  *  0b1..VBUS voltage is above VBUS_VALID_3V threshold
97956  */
97957 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
97958 /*! @} */
97959 
97960 /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
97961 /*! @{ */
97962 
97963 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
97964 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
97965 /*! PULLUP_DP - PULLUP_DP
97966  */
97967 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
97968 
97969 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK    (0x800000U)
97970 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT   (23U)
97971 /*! BGR_BIAS - BGR_BIAS
97972  *  0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default)
97973  *  0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference
97974  */
97975 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)
97976 /*! @} */
97977 
97978 /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
97979 /*! @{ */
97980 
97981 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
97982 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
97983 /*! PULLUP_DP - PULLUP_DP
97984  */
97985 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
97986 
97987 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
97988 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
97989 /*! BGR_BIAS - BGR_BIAS
97990  */
97991 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)
97992 /*! @} */
97993 
97994 /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
97995 /*! @{ */
97996 
97997 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
97998 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
97999 /*! PULLUP_DP - PULLUP_DP
98000  */
98001 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
98002 
98003 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
98004 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
98005 /*! BGR_BIAS - BGR_BIAS
98006  */
98007 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)
98008 /*! @} */
98009 
98010 /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
98011 /*! @{ */
98012 
98013 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
98014 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
98015 /*! PULLUP_DP - PULLUP_DP
98016  */
98017 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
98018 
98019 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
98020 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
98021 /*! BGR_BIAS - BGR_BIAS
98022  */
98023 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)
98024 /*! @} */
98025 
98026 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
98027 /*! @{ */
98028 
98029 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
98030 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
98031 /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
98032  *  0b0..No USB cable attachment has been detected
98033  *  0b1..A USB cable attachment between the device and host has been detected
98034  */
98035 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
98036 
98037 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
98038 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
98039 /*! CHRG_DETECTED - Battery Charging Primary Detection phase output
98040  *  0b0..Standard Downstream Port (SDP) has been detected
98041  *  0b1..Charging Port has been detected
98042  */
98043 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
98044 
98045 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK  (0x4U)
98046 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
98047 /*! DN_STATE - DN_STATE
98048  *  0b0..DN pin voltage is < 0.8V
98049  *  0b1..DN pin voltage is > 2.0V
98050  */
98051 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)
98052 
98053 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
98054 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
98055 /*! DP_STATE - DP_STATE
98056  *  0b0..DP pin voltage is < 0.8V
98057  *  0b1..DP pin voltage is > 2.0V
98058  */
98059 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
98060 
98061 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
98062 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
98063 /*! SECDET_DCP - Battery Charging Secondary Detection phase output
98064  *  0b0..Charging Downstream Port (CDP) has been detected
98065  *  0b1..Downstream Charging Port (DCP) has been detected
98066  */
98067 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
98068 /*! @} */
98069 
98070 /*! @name ANACTRL - USB PHY Analog Control Register */
98071 /*! @{ */
98072 
98073 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
98074 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
98075 /*! DEV_PULLDOWN - DEV_PULLDOWN
98076  *  0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode.
98077  *  0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode.
98078  */
98079 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
98080 /*! @} */
98081 
98082 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
98083 /*! @{ */
98084 
98085 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
98086 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
98087 /*! DEV_PULLDOWN - DEV_PULLDOWN
98088  */
98089 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
98090 /*! @} */
98091 
98092 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
98093 /*! @{ */
98094 
98095 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
98096 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
98097 /*! DEV_PULLDOWN - DEV_PULLDOWN
98098  */
98099 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
98100 /*! @} */
98101 
98102 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
98103 /*! @{ */
98104 
98105 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
98106 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
98107 /*! DEV_PULLDOWN - DEV_PULLDOWN
98108  */
98109 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
98110 /*! @} */
98111 
98112 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
98113 /*! @{ */
98114 
98115 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
98116 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
98117 /*! UTMI_TESTSTART - UTMI_TESTSTART
98118  */
98119 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
98120 
98121 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
98122 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
98123 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98124  */
98125 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
98126 
98127 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
98128 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
98129 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98130  */
98131 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
98132 
98133 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
98134 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
98135 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98136  */
98137 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
98138 
98139 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
98140 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
98141 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98142  */
98143 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
98144 
98145 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
98146 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
98147 /*! TSTI_TX_EN - TSTI_TX_EN
98148  */
98149 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
98150 
98151 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
98152 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
98153 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98154  */
98155 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
98156 
98157 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
98158 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
98159 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98160  */
98161 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
98162 
98163 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
98164 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
98165 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98166  */
98167 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
98168 
98169 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98170 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
98171 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98172  */
98173 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
98174 
98175 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
98176 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
98177 /*! TSTPKT - TSTPKT
98178  */
98179 #define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
98180 /*! @} */
98181 
98182 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
98183 /*! @{ */
98184 
98185 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
98186 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
98187 /*! UTMI_TESTSTART - UTMI_TESTSTART
98188  */
98189 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
98190 
98191 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
98192 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
98193 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98194  */
98195 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
98196 
98197 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
98198 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
98199 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98200  */
98201 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
98202 
98203 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
98204 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
98205 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98206  */
98207 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
98208 
98209 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
98210 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
98211 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98212  */
98213 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
98214 
98215 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
98216 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
98217 /*! TSTI_TX_EN - TSTI_TX_EN
98218  */
98219 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
98220 
98221 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
98222 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
98223 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98224  */
98225 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
98226 
98227 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
98228 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
98229 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98230  */
98231 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
98232 
98233 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
98234 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
98235 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98236  */
98237 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
98238 
98239 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98240 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
98241 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98242  */
98243 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
98244 
98245 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
98246 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
98247 /*! TSTPKT - TSTPKT
98248  */
98249 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
98250 /*! @} */
98251 
98252 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
98253 /*! @{ */
98254 
98255 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
98256 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
98257 /*! UTMI_TESTSTART - UTMI_TESTSTART
98258  */
98259 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
98260 
98261 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
98262 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
98263 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98264  */
98265 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
98266 
98267 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
98268 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
98269 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98270  */
98271 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
98272 
98273 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
98274 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
98275 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98276  */
98277 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
98278 
98279 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
98280 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
98281 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98282  */
98283 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
98284 
98285 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
98286 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
98287 /*! TSTI_TX_EN - TSTI_TX_EN
98288  */
98289 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
98290 
98291 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
98292 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
98293 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98294  */
98295 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
98296 
98297 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
98298 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
98299 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98300  */
98301 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
98302 
98303 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
98304 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
98305 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98306  */
98307 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
98308 
98309 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98310 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
98311 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98312  */
98313 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
98314 
98315 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
98316 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
98317 /*! TSTPKT - TSTPKT
98318  */
98319 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
98320 /*! @} */
98321 
98322 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
98323 /*! @{ */
98324 
98325 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
98326 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
98327 /*! UTMI_TESTSTART - UTMI_TESTSTART
98328  */
98329 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
98330 
98331 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
98332 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
98333 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0
98334  */
98335 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
98336 
98337 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
98338 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
98339 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1
98340  */
98341 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
98342 
98343 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
98344 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
98345 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
98346  */
98347 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
98348 
98349 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
98350 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
98351 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
98352  */
98353 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
98354 
98355 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
98356 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
98357 /*! TSTI_TX_EN - TSTI_TX_EN
98358  */
98359 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
98360 
98361 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
98362 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
98363 /*! TSTI_TX_HIZ - TSTI_TX_HIZ
98364  */
98365 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
98366 
98367 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
98368 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
98369 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0
98370  */
98371 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
98372 
98373 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
98374 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
98375 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1
98376  */
98377 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
98378 
98379 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
98380 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
98381 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
98382  */
98383 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
98384 
98385 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
98386 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
98387 /*! TSTPKT - TSTPKT
98388  */
98389 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
98390 /*! @} */
98391 
98392 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
98393 /*! @{ */
98394 
98395 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
98396 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
98397 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98398  */
98399 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
98400 
98401 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98402 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
98403 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98404  */
98405 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
98406 /*! @} */
98407 
98408 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
98409 /*! @{ */
98410 
98411 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
98412 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
98413 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98414  */
98415 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
98416 
98417 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98418 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
98419 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98420  */
98421 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
98422 /*! @} */
98423 
98424 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
98425 /*! @{ */
98426 
98427 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
98428 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
98429 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98430  */
98431 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
98432 
98433 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98434 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
98435 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98436  */
98437 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
98438 /*! @} */
98439 
98440 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
98441 /*! @{ */
98442 
98443 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
98444 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
98445 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
98446  */
98447 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
98448 
98449 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
98450 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
98451 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
98452  */
98453 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
98454 /*! @} */
98455 
98456 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
98457 /*! @{ */
98458 
98459 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98460 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98461 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98462  */
98463 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
98464 
98465 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98466 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98467 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98468  */
98469 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98470 
98471 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98472 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98473 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98474  */
98475 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
98476 
98477 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98478 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98479 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98480  */
98481 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98482 
98483 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98484 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98485 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98486  */
98487 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98488 
98489 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98490 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98491 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98492  */
98493 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98494 
98495 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98496 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98497 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98498  */
98499 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98500 
98501 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98502 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98503 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98504  */
98505 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98506 
98507 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98508 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98509 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98510  */
98511 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
98512 
98513 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98514 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98515 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98516  */
98517 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98518 
98519 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98520 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98521 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98522  */
98523 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98524 
98525 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98526 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98527 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98528  */
98529 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
98530 
98531 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98532 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98533 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98534  */
98535 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
98536 
98537 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98538 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98539 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98540  */
98541 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
98542 /*! @} */
98543 
98544 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
98545 /*! @{ */
98546 
98547 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98548 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98549 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98550  */
98551 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
98552 
98553 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98554 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98555 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98556  */
98557 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98558 
98559 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98560 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98561 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98562  */
98563 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
98564 
98565 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98566 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98567 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98568  */
98569 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98570 
98571 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98572 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98573 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98574  */
98575 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98576 
98577 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98578 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98579 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98580  */
98581 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98582 
98583 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98584 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98585 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98586  */
98587 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98588 
98589 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98590 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98591 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98592  */
98593 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98594 
98595 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98596 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98597 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98598  */
98599 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
98600 
98601 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98602 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98603 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98604  */
98605 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98606 
98607 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98608 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98609 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98610  */
98611 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98612 
98613 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98614 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98615 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98616  */
98617 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
98618 
98619 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98620 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98621 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98622  */
98623 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
98624 
98625 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98626 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98627 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98628  */
98629 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
98630 /*! @} */
98631 
98632 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
98633 /*! @{ */
98634 
98635 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98636 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98637 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98638  */
98639 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
98640 
98641 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98642 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98643 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98644  */
98645 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98646 
98647 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98648 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98649 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98650  */
98651 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
98652 
98653 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98654 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98655 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98656  */
98657 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98658 
98659 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98660 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98661 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98662  */
98663 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98664 
98665 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98666 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98667 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98668  */
98669 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98670 
98671 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98672 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98673 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98674  */
98675 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98676 
98677 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98678 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98679 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98680  */
98681 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98682 
98683 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98684 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98685 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98686  */
98687 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
98688 
98689 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98690 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98691 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98692  */
98693 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98694 
98695 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98696 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98697 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98698  */
98699 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98700 
98701 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98702 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98703 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98704  */
98705 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
98706 
98707 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98708 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98709 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98710  */
98711 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
98712 
98713 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98714 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98715 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98716  */
98717 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
98718 /*! @} */
98719 
98720 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
98721 /*! @{ */
98722 
98723 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
98724 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
98725 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
98726  */
98727 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
98728 
98729 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
98730 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
98731 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
98732  */
98733 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
98734 
98735 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
98736 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
98737 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
98738  */
98739 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
98740 
98741 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
98742 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
98743 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
98744  */
98745 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
98746 
98747 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
98748 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
98749 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
98750  */
98751 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)
98752 
98753 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
98754 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
98755 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
98756  */
98757 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
98758 
98759 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
98760 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
98761 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
98762  */
98763 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
98764 
98765 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
98766 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
98767 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
98768  */
98769 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
98770 
98771 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
98772 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
98773 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
98774  */
98775 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
98776 
98777 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
98778 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
98779 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
98780  */
98781 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
98782 
98783 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
98784 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
98785 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
98786  */
98787 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
98788 
98789 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
98790 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
98791 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
98792  */
98793 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
98794 
98795 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
98796 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
98797 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
98798  */
98799 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
98800 
98801 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
98802 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
98803 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
98804  */
98805 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
98806 /*! @} */
98807 
98808 
98809 /*!
98810  * @}
98811  */ /* end of group USBPHY_Register_Masks */
98812 
98813 
98814 /* USBPHY - Peripheral instance base addresses */
98815 /** Peripheral USBPHY1 base address */
98816 #define USBPHY1_BASE                             (0x40434000u)
98817 /** Peripheral USBPHY1 base pointer */
98818 #define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
98819 /** Peripheral USBPHY2 base address */
98820 #define USBPHY2_BASE                             (0x40438000u)
98821 /** Peripheral USBPHY2 base pointer */
98822 #define USBPHY2                                  ((USBPHY_Type *)USBPHY2_BASE)
98823 /** Array initializer of USBPHY peripheral base addresses */
98824 #define USBPHY_BASE_ADDRS                        { 0u, USBPHY1_BASE, USBPHY2_BASE }
98825 /** Array initializer of USBPHY peripheral base pointers */
98826 #define USBPHY_BASE_PTRS                         { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
98827 /** Interrupt vectors for the USBPHY peripheral type */
98828 #define USBPHY_IRQS                              { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
98829 /* Backward compatibility */
98830 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
98831 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
98832 #define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
98833 #define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
98834 #define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
98835 #define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)
98836 #define USBPHY_STACK_BASE_ADDRS             { USBPHY1_BASE, USBPHY2_BASE }
98837 
98838 
98839 /*!
98840  * @}
98841  */ /* end of group USBPHY_Peripheral_Access_Layer */
98842 
98843 
98844 /* ----------------------------------------------------------------------------
98845    -- USDHC Peripheral Access Layer
98846    ---------------------------------------------------------------------------- */
98847 
98848 /*!
98849  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
98850  * @{
98851  */
98852 
98853 /** USDHC - Register Layout Typedef */
98854 typedef struct {
98855   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
98856   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
98857   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
98858   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
98859   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
98860   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
98861   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
98862   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
98863   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
98864   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
98865   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
98866   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
98867   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
98868   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
98869   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
98870   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
98871   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
98872   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
98873   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
98874        uint8_t RESERVED_0[4];
98875   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
98876   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
98877   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
98878        uint8_t RESERVED_1[4];
98879   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
98880   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
98881   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
98882        uint8_t RESERVED_2[4];
98883   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
98884   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
98885        uint8_t RESERVED_3[72];
98886   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
98887   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
98888   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
98889   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
98890 } USDHC_Type;
98891 
98892 /* ----------------------------------------------------------------------------
98893    -- USDHC Register Masks
98894    ---------------------------------------------------------------------------- */
98895 
98896 /*!
98897  * @addtogroup USDHC_Register_Masks USDHC Register Masks
98898  * @{
98899  */
98900 
98901 /*! @name DS_ADDR - DMA System Address */
98902 /*! @{ */
98903 
98904 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
98905 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
98906 /*! DS_ADDR - System address
98907  */
98908 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
98909 /*! @} */
98910 
98911 /*! @name BLK_ATT - Block Attributes */
98912 /*! @{ */
98913 
98914 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
98915 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
98916 /*! BLKSIZE - Transfer block size
98917  *  0b1000000000000..4096 bytes
98918  *  0b0100000000000..2048 bytes
98919  *  0b0001000000000..512 bytes
98920  *  0b0000111111111..511 bytes
98921  *  0b0000000000100..4 bytes
98922  *  0b0000000000011..3 bytes
98923  *  0b0000000000010..2 bytes
98924  *  0b0000000000001..1 byte
98925  *  0b0000000000000..No data transfer
98926  */
98927 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
98928 
98929 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
98930 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
98931 /*! BLKCNT - Blocks count for current transfer
98932  *  0b1111111111111111..65535 blocks
98933  *  0b0000000000000010..2 blocks
98934  *  0b0000000000000001..1 block
98935  *  0b0000000000000000..Stop count
98936  */
98937 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
98938 /*! @} */
98939 
98940 /*! @name CMD_ARG - Command Argument */
98941 /*! @{ */
98942 
98943 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
98944 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
98945 /*! CMDARG - Command argument
98946  */
98947 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
98948 /*! @} */
98949 
98950 /*! @name CMD_XFR_TYP - Command Transfer Type */
98951 /*! @{ */
98952 
98953 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
98954 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
98955 /*! RSPTYP - Response type select
98956  *  0b00..No response
98957  *  0b01..Response length 136
98958  *  0b10..Response length 48
98959  *  0b11..Response length 48, check busy after response
98960  */
98961 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
98962 
98963 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
98964 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
98965 /*! CCCEN - Command CRC check enable
98966  *  0b1..Enables command CRC check
98967  *  0b0..Disables command CRC check
98968  */
98969 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
98970 
98971 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
98972 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
98973 /*! CICEN - Command index check enable
98974  *  0b1..Enables command index check
98975  *  0b0..Disable command index check
98976  */
98977 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
98978 
98979 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
98980 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
98981 /*! DPSEL - Data present select
98982  *  0b1..Data present
98983  *  0b0..No data present
98984  */
98985 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
98986 
98987 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
98988 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
98989 /*! CMDTYP - Command type
98990  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
98991  *  0b10..Resume CMD52 for writing function select in CCCR
98992  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
98993  *  0b00..Normal other commands
98994  */
98995 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
98996 
98997 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
98998 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
98999 /*! CMDINX - Command index
99000  */
99001 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
99002 /*! @} */
99003 
99004 /*! @name CMD_RSP0 - Command Response0 */
99005 /*! @{ */
99006 
99007 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
99008 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
99009 /*! CMDRSP0 - Command response 0
99010  */
99011 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
99012 /*! @} */
99013 
99014 /*! @name CMD_RSP1 - Command Response1 */
99015 /*! @{ */
99016 
99017 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
99018 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
99019 /*! CMDRSP1 - Command response 1
99020  */
99021 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
99022 /*! @} */
99023 
99024 /*! @name CMD_RSP2 - Command Response2 */
99025 /*! @{ */
99026 
99027 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
99028 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
99029 /*! CMDRSP2 - Command response 2
99030  */
99031 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
99032 /*! @} */
99033 
99034 /*! @name CMD_RSP3 - Command Response3 */
99035 /*! @{ */
99036 
99037 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
99038 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
99039 /*! CMDRSP3 - Command response 3
99040  */
99041 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
99042 /*! @} */
99043 
99044 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
99045 /*! @{ */
99046 
99047 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
99048 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
99049 /*! DATCONT - Data content
99050  */
99051 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
99052 /*! @} */
99053 
99054 /*! @name PRES_STATE - Present State */
99055 /*! @{ */
99056 
99057 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
99058 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
99059 /*! CIHB - Command inhibit (CMD)
99060  *  0b1..Cannot issue command
99061  *  0b0..Can issue command using only CMD line
99062  */
99063 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
99064 
99065 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
99066 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
99067 /*! CDIHB - Command Inhibit Data (DATA)
99068  *  0b1..Cannot issue command that uses the DATA line
99069  *  0b0..Can issue command that uses the DATA line
99070  */
99071 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
99072 
99073 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
99074 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
99075 /*! DLA - Data line active
99076  *  0b1..DATA line active
99077  *  0b0..DATA line inactive
99078  */
99079 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
99080 
99081 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
99082 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
99083 /*! SDSTB - SD clock stable
99084  *  0b1..Clock is stable.
99085  *  0b0..Clock is changing frequency and not stable.
99086  */
99087 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
99088 
99089 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
99090 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
99091 /*! IPGOFF - Peripheral clock gated off internally
99092  *  0b1..Peripheral clock is gated off.
99093  *  0b0..Peripheral clock is active.
99094  */
99095 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
99096 
99097 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
99098 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
99099 /*! HCKOFF - HCLK gated off internally
99100  *  0b1..HCLK is gated off.
99101  *  0b0..HCLK is active.
99102  */
99103 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
99104 
99105 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
99106 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
99107 /*! PEROFF - IPG_PERCLK gated off internally
99108  *  0b1..IPG_PERCLK is gated off.
99109  *  0b0..IPG_PERCLK is active.
99110  */
99111 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
99112 
99113 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
99114 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
99115 /*! SDOFF - SD clock gated off internally
99116  *  0b1..SD clock is gated off.
99117  *  0b0..SD clock is active.
99118  */
99119 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
99120 
99121 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
99122 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
99123 /*! WTA - Write transfer active
99124  *  0b1..Transferring data
99125  *  0b0..No valid data
99126  */
99127 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
99128 
99129 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
99130 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
99131 /*! RTA - Read transfer active
99132  *  0b1..Transferring data
99133  *  0b0..No valid data
99134  */
99135 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
99136 
99137 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
99138 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
99139 /*! BWEN - Buffer write enable
99140  *  0b1..Write enable
99141  *  0b0..Write disable
99142  */
99143 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
99144 
99145 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
99146 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
99147 /*! BREN - Buffer read enable
99148  *  0b1..Read enable
99149  *  0b0..Read disable
99150  */
99151 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
99152 
99153 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
99154 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
99155 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
99156  *  0b1..Sampling clock needs re-tuning
99157  *  0b0..Fixed or well tuned sampling clock
99158  */
99159 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
99160 
99161 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
99162 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
99163 /*! TSCD - Tap select change done
99164  *  0b1..Delay cell select change is finished.
99165  *  0b0..Delay cell select change is not finished.
99166  */
99167 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
99168 
99169 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
99170 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
99171 /*! CINST - Card inserted
99172  *  0b1..Card inserted
99173  *  0b0..Power on reset or no card
99174  */
99175 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
99176 
99177 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
99178 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
99179 /*! CDPL - Card detect pin level
99180  *  0b1..Card present (CD_B = 0)
99181  *  0b0..No card present (CD_B = 1)
99182  */
99183 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
99184 
99185 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
99186 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
99187 /*! WPSPL - Write protect switch pin level
99188  *  0b1..Write enabled (WP = 0)
99189  *  0b0..Write protected (WP = 1)
99190  */
99191 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
99192 
99193 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
99194 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
99195 /*! CLSL - CMD line signal level
99196  */
99197 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
99198 
99199 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
99200 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
99201 /*! DLSL - DATA[7:0] line signal level
99202  *  0b00000111..Data 7 line signal level
99203  *  0b00000110..Data 6 line signal level
99204  *  0b00000101..Data 5 line signal level
99205  *  0b00000100..Data 4 line signal level
99206  *  0b00000011..Data 3 line signal level
99207  *  0b00000010..Data 2 line signal level
99208  *  0b00000001..Data 1 line signal level
99209  *  0b00000000..Data 0 line signal level
99210  */
99211 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
99212 /*! @} */
99213 
99214 /*! @name PROT_CTRL - Protocol Control */
99215 /*! @{ */
99216 
99217 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
99218 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
99219 /*! DTW - Data transfer width
99220  *  0b10..8-bit mode
99221  *  0b01..4-bit mode
99222  *  0b00..1-bit mode
99223  *  0b11..Reserved
99224  */
99225 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
99226 
99227 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
99228 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
99229 /*! D3CD - DATA3 as card detection pin
99230  *  0b1..DATA3 as card detection pin
99231  *  0b0..DATA3 does not monitor card insertion
99232  */
99233 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
99234 
99235 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
99236 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
99237 /*! EMODE - Endian mode
99238  *  0b00..Big endian mode
99239  *  0b01..Half word big endian mode
99240  *  0b10..Little endian mode
99241  *  0b11..Reserved
99242  */
99243 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
99244 
99245 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
99246 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
99247 /*! CDTL - Card detect test level
99248  *  0b1..Card detect test level is 1, card inserted
99249  *  0b0..Card detect test level is 0, no card inserted
99250  */
99251 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
99252 
99253 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
99254 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
99255 /*! CDSS - Card detect signal selection
99256  *  0b1..Card detection test level is selected (for test purpose).
99257  *  0b0..Card detection level is selected (for normal purpose).
99258  */
99259 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
99260 
99261 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
99262 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
99263 /*! DMASEL - DMA select
99264  *  0b00..No DMA or simple DMA is selected.
99265  *  0b01..ADMA1 is selected.
99266  *  0b10..ADMA2 is selected.
99267  *  0b11..Reserved
99268  */
99269 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
99270 
99271 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
99272 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
99273 /*! SABGREQ - Stop at block gap request
99274  *  0b1..Stop
99275  *  0b0..Transfer
99276  */
99277 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
99278 
99279 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
99280 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
99281 /*! CREQ - Continue request
99282  *  0b1..Restart
99283  *  0b0..No effect
99284  */
99285 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
99286 
99287 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
99288 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
99289 /*! RWCTL - Read wait control
99290  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
99291  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
99292  */
99293 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
99294 
99295 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
99296 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
99297 /*! IABG - Interrupt at block gap
99298  *  0b1..Enables interrupt at block gap
99299  *  0b0..Disables interrupt at block gap
99300  */
99301 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
99302 
99303 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
99304 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
99305 /*! RD_DONE_NO_8CLK - Read performed number 8 clock
99306  */
99307 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
99308 
99309 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
99310 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
99311 /*! WECINT - Wakeup event enable on card interrupt
99312  *  0b1..Enables wakeup event enable on card interrupt
99313  *  0b0..Disables wakeup event enable on card interrupt
99314  */
99315 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
99316 
99317 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
99318 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
99319 /*! WECINS - Wakeup event enable on SD card insertion
99320  *  0b1..Enable wakeup event enable on SD card insertion
99321  *  0b0..Disable wakeup event enable on SD card insertion
99322  */
99323 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
99324 
99325 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
99326 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
99327 /*! WECRM - Wakeup event enable on SD card removal
99328  *  0b1..Enables wakeup event enable on SD card removal
99329  *  0b0..Disables wakeup event enable on SD card removal
99330  */
99331 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
99332 
99333 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
99334 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
99335 /*! NON_EXACT_BLK_RD - Non-exact block read
99336  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
99337  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
99338  */
99339 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
99340 /*! @} */
99341 
99342 /*! @name SYS_CTRL - System Control */
99343 /*! @{ */
99344 
99345 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
99346 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
99347 /*! DVS - Divisor
99348  *  0b0000..Divide-by-1
99349  *  0b0001..Divide-by-2
99350  *  0b1110..Divide-by-15
99351  *  0b1111..Divide-by-16
99352  */
99353 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
99354 
99355 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
99356 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
99357 /*! SDCLKFS - SDCLK frequency select
99358  */
99359 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
99360 
99361 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
99362 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
99363 /*! DTOCV - Data timeout counter value
99364  *  0b1111..SDCLK x 2 29
99365  *  0b1110..SDCLK x 2 28
99366  *  0b1101..SDCLK x 2 27
99367  *  0b1100..SDCLK x 2 26
99368  *  0b1011..SDCLK x 2 25
99369  *  0b1010..SDCLK x 2 24
99370  *  0b1001..SDCLK x 2 23
99371  *  0b1000..SDCLK x 2 22
99372  *  0b0111..SDCLK x 2 21
99373  *  0b0110..SDCLK x 2 20
99374  *  0b0101..SDCLK x 2 19
99375  *  0b0100..SDCLK x 2 18
99376  *  0b0011..SDCLK x 2 17
99377  *  0b0010..SDCLK x 2 16
99378  *  0b0001..SDCLK x 2 15
99379  *  0b0000..SDCLK x 2 14
99380  */
99381 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
99382 
99383 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
99384 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
99385 /*! IPP_RST_N - Hardware reset
99386  */
99387 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
99388 
99389 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
99390 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
99391 /*! RSTA - Software reset for all
99392  *  0b1..Reset
99393  *  0b0..No reset
99394  */
99395 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
99396 
99397 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
99398 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
99399 /*! RSTC - Software reset for CMD line
99400  *  0b1..Reset
99401  *  0b0..No reset
99402  */
99403 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
99404 
99405 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
99406 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
99407 /*! RSTD - Software reset for data line
99408  *  0b1..Reset
99409  *  0b0..No reset
99410  */
99411 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
99412 
99413 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
99414 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
99415 /*! INITA - Initialization active
99416  */
99417 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
99418 
99419 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
99420 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
99421 /*! RSTT - Reset tuning
99422  */
99423 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
99424 /*! @} */
99425 
99426 /*! @name INT_STATUS - Interrupt Status */
99427 /*! @{ */
99428 
99429 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
99430 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
99431 /*! CC - Command complete
99432  *  0b1..Command complete
99433  *  0b0..Command not complete
99434  */
99435 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
99436 
99437 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
99438 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
99439 /*! TC - Transfer complete
99440  *  0b1..Transfer complete
99441  *  0b0..Transfer does not complete
99442  */
99443 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
99444 
99445 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
99446 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
99447 /*! BGE - Block gap event
99448  *  0b1..Transaction stopped at block gap
99449  *  0b0..No block gap event
99450  */
99451 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
99452 
99453 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
99454 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
99455 /*! DINT - DMA interrupt
99456  *  0b1..DMA interrupt is generated.
99457  *  0b0..No DMA interrupt
99458  */
99459 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
99460 
99461 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
99462 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
99463 /*! BWR - Buffer write ready
99464  *  0b1..Ready to write buffer
99465  *  0b0..Not ready to write buffer
99466  */
99467 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
99468 
99469 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
99470 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
99471 /*! BRR - Buffer read ready
99472  *  0b1..Ready to read buffer
99473  *  0b0..Not ready to read buffer
99474  */
99475 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
99476 
99477 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
99478 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
99479 /*! CINS - Card insertion
99480  *  0b1..Card inserted
99481  *  0b0..Card state unstable or removed
99482  */
99483 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
99484 
99485 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
99486 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
99487 /*! CRM - Card removal
99488  *  0b1..Card removed
99489  *  0b0..Card state unstable or inserted
99490  */
99491 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
99492 
99493 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
99494 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
99495 /*! CINT - Card interrupt
99496  *  0b1..Generate card interrupt
99497  *  0b0..No card interrupt
99498  */
99499 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
99500 
99501 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
99502 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
99503 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
99504  *  0b1..Re-tuning should be performed.
99505  *  0b0..Re-tuning is not required.
99506  */
99507 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
99508 
99509 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
99510 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
99511 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
99512  */
99513 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
99514 
99515 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
99516 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
99517 /*! CTOE - Command timeout error
99518  *  0b1..Time out
99519  *  0b0..No error
99520  */
99521 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
99522 
99523 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
99524 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
99525 /*! CCE - Command CRC error
99526  *  0b1..CRC error generated
99527  *  0b0..No error
99528  */
99529 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
99530 
99531 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
99532 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
99533 /*! CEBE - Command end bit error
99534  *  0b1..End bit error generated
99535  *  0b0..No error
99536  */
99537 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
99538 
99539 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
99540 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
99541 /*! CIE - Command index error
99542  *  0b1..Error
99543  *  0b0..No error
99544  */
99545 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
99546 
99547 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
99548 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
99549 /*! DTOE - Data timeout error
99550  *  0b1..Time out
99551  *  0b0..No error
99552  */
99553 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
99554 
99555 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
99556 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
99557 /*! DCE - Data CRC error
99558  *  0b1..Error
99559  *  0b0..No error
99560  */
99561 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
99562 
99563 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
99564 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
99565 /*! DEBE - Data end bit error
99566  *  0b1..Error
99567  *  0b0..No error
99568  */
99569 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
99570 
99571 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
99572 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
99573 /*! AC12E - Auto CMD12 error
99574  *  0b1..Error
99575  *  0b0..No error
99576  */
99577 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
99578 
99579 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
99580 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
99581 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
99582  */
99583 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
99584 
99585 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
99586 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
99587 /*! DMAE - DMA error
99588  *  0b1..Error
99589  *  0b0..No error
99590  */
99591 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
99592 /*! @} */
99593 
99594 /*! @name INT_STATUS_EN - Interrupt Status Enable */
99595 /*! @{ */
99596 
99597 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
99598 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
99599 /*! CCSEN - Command complete status enable
99600  *  0b1..Enabled
99601  *  0b0..Masked
99602  */
99603 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
99604 
99605 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
99606 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
99607 /*! TCSEN - Transfer complete status enable
99608  *  0b1..Enabled
99609  *  0b0..Masked
99610  */
99611 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
99612 
99613 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
99614 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
99615 /*! BGESEN - Block gap event status enable
99616  *  0b1..Enabled
99617  *  0b0..Masked
99618  */
99619 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
99620 
99621 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
99622 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
99623 /*! DINTSEN - DMA interrupt status enable
99624  *  0b1..Enabled
99625  *  0b0..Masked
99626  */
99627 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
99628 
99629 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
99630 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
99631 /*! BWRSEN - Buffer write ready status enable
99632  *  0b1..Enabled
99633  *  0b0..Masked
99634  */
99635 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
99636 
99637 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
99638 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
99639 /*! BRRSEN - Buffer read ready status enable
99640  *  0b1..Enabled
99641  *  0b0..Masked
99642  */
99643 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
99644 
99645 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
99646 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
99647 /*! CINSSEN - Card insertion status enable
99648  *  0b1..Enabled
99649  *  0b0..Masked
99650  */
99651 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
99652 
99653 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
99654 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
99655 /*! CRMSEN - Card removal status enable
99656  *  0b1..Enabled
99657  *  0b0..Masked
99658  */
99659 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
99660 
99661 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
99662 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
99663 /*! CINTSEN - Card interrupt status enable
99664  *  0b1..Enabled
99665  *  0b0..Masked
99666  */
99667 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
99668 
99669 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
99670 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
99671 /*! RTESEN - Re-tuning event status enable
99672  *  0b1..Enabled
99673  *  0b0..Masked
99674  */
99675 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
99676 
99677 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
99678 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
99679 /*! TPSEN - Tuning pass status enable
99680  *  0b1..Enabled
99681  *  0b0..Masked
99682  */
99683 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
99684 
99685 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
99686 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
99687 /*! CTOESEN - Command timeout error status enable
99688  *  0b1..Enabled
99689  *  0b0..Masked
99690  */
99691 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
99692 
99693 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
99694 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
99695 /*! CCESEN - Command CRC error status enable
99696  *  0b1..Enabled
99697  *  0b0..Masked
99698  */
99699 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
99700 
99701 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
99702 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
99703 /*! CEBESEN - Command end bit error status enable
99704  *  0b1..Enabled
99705  *  0b0..Masked
99706  */
99707 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
99708 
99709 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
99710 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
99711 /*! CIESEN - Command index error status enable
99712  *  0b1..Enabled
99713  *  0b0..Masked
99714  */
99715 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
99716 
99717 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
99718 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
99719 /*! DTOESEN - Data timeout error status enable
99720  *  0b1..Enabled
99721  *  0b0..Masked
99722  */
99723 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
99724 
99725 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
99726 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
99727 /*! DCESEN - Data CRC error status enable
99728  *  0b1..Enabled
99729  *  0b0..Masked
99730  */
99731 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
99732 
99733 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
99734 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
99735 /*! DEBESEN - Data end bit error status enable
99736  *  0b1..Enabled
99737  *  0b0..Masked
99738  */
99739 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
99740 
99741 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
99742 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
99743 /*! AC12ESEN - Auto CMD12 error status enable
99744  *  0b1..Enabled
99745  *  0b0..Masked
99746  */
99747 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
99748 
99749 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
99750 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
99751 /*! TNESEN - Tuning error status enable
99752  *  0b1..Enabled
99753  *  0b0..Masked
99754  */
99755 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
99756 
99757 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
99758 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
99759 /*! DMAESEN - DMA error status enable
99760  *  0b1..Enabled
99761  *  0b0..Masked
99762  */
99763 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
99764 /*! @} */
99765 
99766 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
99767 /*! @{ */
99768 
99769 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
99770 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
99771 /*! CCIEN - Command complete interrupt enable
99772  *  0b1..Enabled
99773  *  0b0..Masked
99774  */
99775 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
99776 
99777 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
99778 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
99779 /*! TCIEN - Transfer complete interrupt enable
99780  *  0b1..Enabled
99781  *  0b0..Masked
99782  */
99783 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
99784 
99785 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
99786 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
99787 /*! BGEIEN - Block gap event interrupt enable
99788  *  0b1..Enabled
99789  *  0b0..Masked
99790  */
99791 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
99792 
99793 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
99794 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
99795 /*! DINTIEN - DMA interrupt enable
99796  *  0b1..Enabled
99797  *  0b0..Masked
99798  */
99799 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
99800 
99801 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
99802 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
99803 /*! BWRIEN - Buffer write ready interrupt enable
99804  *  0b1..Enabled
99805  *  0b0..Masked
99806  */
99807 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
99808 
99809 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
99810 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
99811 /*! BRRIEN - Buffer read ready interrupt enable
99812  *  0b1..Enabled
99813  *  0b0..Masked
99814  */
99815 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
99816 
99817 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
99818 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
99819 /*! CINSIEN - Card insertion interrupt enable
99820  *  0b1..Enabled
99821  *  0b0..Masked
99822  */
99823 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
99824 
99825 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
99826 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
99827 /*! CRMIEN - Card removal interrupt enable
99828  *  0b1..Enabled
99829  *  0b0..Masked
99830  */
99831 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
99832 
99833 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
99834 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
99835 /*! CINTIEN - Card interrupt enable
99836  *  0b1..Enabled
99837  *  0b0..Masked
99838  */
99839 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
99840 
99841 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
99842 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
99843 /*! RTEIEN - Re-tuning event interrupt enable
99844  *  0b1..Enabled
99845  *  0b0..Masked
99846  */
99847 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
99848 
99849 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
99850 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
99851 /*! TPIEN - Tuning Pass interrupt enable
99852  *  0b1..Enabled
99853  *  0b0..Masked
99854  */
99855 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
99856 
99857 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
99858 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
99859 /*! CTOEIEN - Command timeout error interrupt enable
99860  *  0b1..Enabled
99861  *  0b0..Masked
99862  */
99863 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
99864 
99865 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
99866 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
99867 /*! CCEIEN - Command CRC error interrupt enable
99868  *  0b1..Enabled
99869  *  0b0..Masked
99870  */
99871 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
99872 
99873 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
99874 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
99875 /*! CEBEIEN - Command end bit error interrupt enable
99876  *  0b1..Enabled
99877  *  0b0..Masked
99878  */
99879 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
99880 
99881 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
99882 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
99883 /*! CIEIEN - Command index error interrupt enable
99884  *  0b1..Enabled
99885  *  0b0..Masked
99886  */
99887 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
99888 
99889 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
99890 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
99891 /*! DTOEIEN - Data timeout error interrupt enable
99892  *  0b1..Enabled
99893  *  0b0..Masked
99894  */
99895 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
99896 
99897 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
99898 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
99899 /*! DCEIEN - Data CRC error interrupt enable
99900  *  0b1..Enabled
99901  *  0b0..Masked
99902  */
99903 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
99904 
99905 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
99906 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
99907 /*! DEBEIEN - Data end bit error interrupt enable
99908  *  0b1..Enabled
99909  *  0b0..Masked
99910  */
99911 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
99912 
99913 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
99914 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
99915 /*! AC12EIEN - Auto CMD12 error interrupt enable
99916  *  0b1..Enabled
99917  *  0b0..Masked
99918  */
99919 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
99920 
99921 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
99922 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
99923 /*! TNEIEN - Tuning error interrupt enable
99924  *  0b1..Enabled
99925  *  0b0..Masked
99926  */
99927 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
99928 
99929 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
99930 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
99931 /*! DMAEIEN - DMA error interrupt enable
99932  *  0b1..Enable
99933  *  0b0..Masked
99934  */
99935 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
99936 /*! @} */
99937 
99938 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
99939 /*! @{ */
99940 
99941 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
99942 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
99943 /*! AC12NE - Auto CMD12 not executed
99944  *  0b1..Not executed
99945  *  0b0..Executed
99946  */
99947 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
99948 
99949 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
99950 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
99951 /*! AC12TOE - Auto CMD12 / 23 timeout error
99952  *  0b1..Time out
99953  *  0b0..No error
99954  */
99955 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
99956 
99957 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
99958 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
99959 /*! AC12EBE - Auto CMD12 / 23 end bit error
99960  *  0b1..End bit error generated
99961  *  0b0..No error
99962  */
99963 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
99964 
99965 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
99966 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
99967 /*! AC12CE - Auto CMD12 / 23 CRC error
99968  *  0b1..CRC error met in Auto CMD12/23 response
99969  *  0b0..No CRC error
99970  */
99971 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
99972 
99973 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
99974 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
99975 /*! AC12IE - Auto CMD12 / 23 index error
99976  *  0b1..Error, the CMD index in response is not CMD12/23
99977  *  0b0..No error
99978  */
99979 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
99980 
99981 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
99982 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
99983 /*! CNIBAC12E - Command not issued by Auto CMD12 error
99984  *  0b1..Not issued
99985  *  0b0..No error
99986  */
99987 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
99988 
99989 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
99990 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
99991 /*! EXECUTE_TUNING - Execute tuning
99992  *  0b1..Start tuning procedure
99993  *  0b0..Tuning procedure is aborted
99994  */
99995 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
99996 
99997 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
99998 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
99999 /*! SMP_CLK_SEL - Sample clock select
100000  *  0b1..Tuned clock is used to sample data
100001  *  0b0..Fixed clock is used to sample data
100002  */
100003 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
100004 /*! @} */
100005 
100006 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
100007 /*! @{ */
100008 
100009 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
100010 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
100011 /*! SDR50_SUPPORT - SDR50 support
100012  */
100013 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
100014 
100015 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
100016 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
100017 /*! SDR104_SUPPORT - SDR104 support
100018  */
100019 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
100020 
100021 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
100022 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
100023 /*! DDR50_SUPPORT - DDR50 support
100024  */
100025 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
100026 
100027 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
100028 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
100029 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
100030  *  0b1..SDR50 supports tuning
100031  *  0b0..SDR50 does not support tuning
100032  */
100033 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
100034 
100035 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
100036 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
100037 /*! MBL - Max block length
100038  *  0b000..512 bytes
100039  *  0b001..1024 bytes
100040  *  0b010..2048 bytes
100041  *  0b011..4096 bytes
100042  */
100043 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
100044 
100045 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
100046 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
100047 /*! ADMAS - ADMA support
100048  *  0b1..Advanced DMA supported
100049  *  0b0..Advanced DMA not supported
100050  */
100051 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
100052 
100053 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
100054 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
100055 /*! HSS - High speed support
100056  *  0b1..High speed supported
100057  *  0b0..High speed not supported
100058  */
100059 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
100060 
100061 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
100062 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
100063 /*! DMAS - DMA support
100064  *  0b1..DMA supported
100065  *  0b0..DMA not supported
100066  */
100067 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
100068 
100069 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
100070 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
100071 /*! SRS - Suspend / resume support
100072  *  0b1..Supported
100073  *  0b0..Not supported
100074  */
100075 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
100076 
100077 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
100078 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
100079 /*! VS33 - Voltage support 3.3 V
100080  *  0b1..3.3 V supported
100081  *  0b0..3.3 V not supported
100082  */
100083 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
100084 
100085 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
100086 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
100087 /*! VS30 - Voltage support 3.0 V
100088  *  0b1..3.0 V supported
100089  *  0b0..3.0 V not supported
100090  */
100091 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
100092 
100093 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
100094 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
100095 /*! VS18 - Voltage support 1.8 V
100096  *  0b1..1.8 V supported
100097  *  0b0..1.8 V not supported
100098  */
100099 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
100100 /*! @} */
100101 
100102 /*! @name WTMK_LVL - Watermark Level */
100103 /*! @{ */
100104 
100105 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
100106 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
100107 /*! RD_WML - Read watermark level
100108  */
100109 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
100110 
100111 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
100112 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
100113 /*! WR_WML - Write watermark level
100114  */
100115 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
100116 /*! @} */
100117 
100118 /*! @name MIX_CTRL - Mixer Control */
100119 /*! @{ */
100120 
100121 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
100122 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
100123 /*! DMAEN - DMA enable
100124  *  0b1..Enable
100125  *  0b0..Disable
100126  */
100127 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
100128 
100129 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
100130 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
100131 /*! BCEN - Block count enable
100132  *  0b1..Enable
100133  *  0b0..Disable
100134  */
100135 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
100136 
100137 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
100138 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
100139 /*! AC12EN - Auto CMD12 enable
100140  *  0b1..Enable
100141  *  0b0..Disable
100142  */
100143 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
100144 
100145 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
100146 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
100147 /*! DDR_EN - Dual data rate mode selection
100148  */
100149 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
100150 
100151 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
100152 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
100153 /*! DTDSEL - Data transfer direction select
100154  *  0b1..Read (Card to host)
100155  *  0b0..Write (Host to card)
100156  */
100157 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
100158 
100159 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
100160 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
100161 /*! MSBSEL - Multi / Single block select
100162  *  0b1..Multiple blocks
100163  *  0b0..Single block
100164  */
100165 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
100166 
100167 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
100168 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
100169 /*! NIBBLE_POS - Nibble position indication
100170  */
100171 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
100172 
100173 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
100174 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
100175 /*! AC23EN - Auto CMD23 enable
100176  */
100177 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
100178 
100179 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
100180 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
100181 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
100182  *  0b1..Execute tuning
100183  *  0b0..Not tuned or tuning completed
100184  */
100185 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
100186 
100187 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
100188 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
100189 /*! SMP_CLK_SEL - Clock selection
100190  *  0b1..Tuned clock is used to sample data / cmd
100191  *  0b0..Fixed clock is used to sample data / cmd
100192  */
100193 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
100194 
100195 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
100196 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
100197 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
100198  *  0b1..Enable auto tuning
100199  *  0b0..Disable auto tuning
100200  */
100201 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
100202 
100203 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
100204 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
100205 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
100206  *  0b1..Feedback clock comes from the ipp_card_clk_out
100207  *  0b0..Feedback clock comes from the loopback CLK
100208  */
100209 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
100210 
100211 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
100212 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
100213 /*! HS400_MODE - Enable HS400 mode
100214  */
100215 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
100216 /*! @} */
100217 
100218 /*! @name FORCE_EVENT - Force Event */
100219 /*! @{ */
100220 
100221 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
100222 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
100223 /*! FEVTAC12NE - Force event auto command 12 not executed
100224  */
100225 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
100226 
100227 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
100228 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
100229 /*! FEVTAC12TOE - Force event auto command 12 time out error
100230  */
100231 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
100232 
100233 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
100234 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
100235 /*! FEVTAC12CE - Force event auto command 12 CRC error
100236  */
100237 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
100238 
100239 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
100240 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
100241 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error
100242  */
100243 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
100244 
100245 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
100246 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
100247 /*! FEVTAC12IE - Force event Auto Command 12 index error
100248  */
100249 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
100250 
100251 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
100252 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
100253 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
100254  */
100255 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
100256 
100257 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
100258 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
100259 /*! FEVTCTOE - Force event command time out error
100260  */
100261 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
100262 
100263 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
100264 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
100265 /*! FEVTCCE - Force event command CRC error
100266  */
100267 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
100268 
100269 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
100270 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
100271 /*! FEVTCEBE - Force event command end bit error
100272  */
100273 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
100274 
100275 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
100276 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
100277 /*! FEVTCIE - Force event command index error
100278  */
100279 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
100280 
100281 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
100282 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
100283 /*! FEVTDTOE - Force event data time out error
100284  */
100285 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
100286 
100287 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
100288 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
100289 /*! FEVTDCE - Force event data CRC error
100290  */
100291 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
100292 
100293 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
100294 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
100295 /*! FEVTDEBE - Force event data end bit error
100296  */
100297 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
100298 
100299 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
100300 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
100301 /*! FEVTAC12E - Force event Auto Command 12 error
100302  */
100303 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
100304 
100305 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
100306 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
100307 /*! FEVTTNE - Force tuning error
100308  */
100309 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
100310 
100311 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
100312 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
100313 /*! FEVTDMAE - Force event DMA error
100314  */
100315 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
100316 
100317 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
100318 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
100319 /*! FEVTCINT - Force event card interrupt
100320  */
100321 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
100322 /*! @} */
100323 
100324 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
100325 /*! @{ */
100326 
100327 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
100328 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
100329 /*! ADMAES - ADMA error state (when ADMA error is occurred)
100330  */
100331 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
100332 
100333 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
100334 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
100335 /*! ADMALME - ADMA length mismatch error
100336  *  0b1..Error
100337  *  0b0..No error
100338  */
100339 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
100340 
100341 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
100342 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
100343 /*! ADMADCE - ADMA descriptor error
100344  *  0b1..Error
100345  *  0b0..No error
100346  */
100347 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
100348 /*! @} */
100349 
100350 /*! @name ADMA_SYS_ADDR - ADMA System Address */
100351 /*! @{ */
100352 
100353 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
100354 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
100355 /*! ADS_ADDR - ADMA system address
100356  */
100357 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
100358 /*! @} */
100359 
100360 /*! @name DLL_CTRL - DLL (Delay Line) Control */
100361 /*! @{ */
100362 
100363 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
100364 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
100365 /*! DLL_CTRL_ENABLE - DLL and delay chain
100366  */
100367 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
100368 
100369 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
100370 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
100371 /*! DLL_CTRL_RESET - DLL reset
100372  */
100373 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
100374 
100375 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
100376 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
100377 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
100378  */
100379 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
100380 
100381 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
100382 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
100383 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
100384  */
100385 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
100386 
100387 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
100388 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
100389 /*! DLL_CTRL_GATE_UPDATE - DLL gate update
100390  */
100391 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
100392 
100393 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
100394 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
100395 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
100396  */
100397 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
100398 
100399 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
100400 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
100401 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
100402  */
100403 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
100404 
100405 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
100406 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
100407 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
100408  */
100409 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
100410 
100411 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
100412 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
100413 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
100414  */
100415 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
100416 
100417 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
100418 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
100419 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
100420  */
100421 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
100422 /*! @} */
100423 
100424 /*! @name DLL_STATUS - DLL Status */
100425 /*! @{ */
100426 
100427 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
100428 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
100429 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status
100430  */
100431 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
100432 
100433 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
100434 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
100435 /*! DLL_STS_REF_LOCK - Reference DLL lock status
100436  */
100437 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
100438 
100439 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
100440 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
100441 /*! DLL_STS_SLV_SEL - Slave delay line select status
100442  */
100443 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
100444 
100445 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
100446 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
100447 /*! DLL_STS_REF_SEL - Reference delay line select taps
100448  */
100449 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
100450 /*! @} */
100451 
100452 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
100453 /*! @{ */
100454 
100455 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
100456 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
100457 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
100458  */
100459 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
100460 
100461 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
100462 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
100463 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
100464  */
100465 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
100466 
100467 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
100468 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
100469 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
100470  */
100471 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
100472 
100473 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
100474 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
100475 /*! NXT_ERR - NXT error
100476  */
100477 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
100478 
100479 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
100480 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
100481 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
100482  */
100483 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
100484 
100485 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
100486 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
100487 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
100488  */
100489 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
100490 
100491 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
100492 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
100493 /*! TAP_SEL_PRE - TAP_SEL_PRE
100494  */
100495 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
100496 
100497 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
100498 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
100499 /*! PRE_ERR - PRE error
100500  */
100501 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
100502 /*! @} */
100503 
100504 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
100505 /*! @{ */
100506 
100507 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
100508 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
100509 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
100510  */
100511 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
100512 
100513 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
100514 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
100515 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
100516  */
100517 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
100518 
100519 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
100520 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
100521 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
100522  */
100523 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
100524 
100525 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
100526 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
100527 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
100528  */
100529 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
100530 
100531 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
100532 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
100533 /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update
100534  */
100535 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
100536 
100537 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
100538 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
100539 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
100540  */
100541 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
100542 
100543 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
100544 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
100545 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
100546  */
100547 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
100548 
100549 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
100550 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
100551 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
100552  */
100553 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
100554 
100555 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
100556 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
100557 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
100558  */
100559 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
100560 /*! @} */
100561 
100562 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
100563 /*! @{ */
100564 
100565 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
100566 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
100567 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
100568  */
100569 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
100570 
100571 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
100572 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
100573 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
100574  */
100575 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
100576 
100577 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
100578 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
100579 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
100580  */
100581 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
100582 
100583 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
100584 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
100585 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
100586  */
100587 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
100588 /*! @} */
100589 
100590 /*! @name VEND_SPEC - Vendor Specific Register */
100591 /*! @{ */
100592 
100593 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
100594 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
100595 /*! VSELECT - Voltage selection
100596  *  0b1..Change the voltage to low voltage range, around 1.8 V
100597  *  0b0..Change the voltage to high voltage range, around 3.0 V
100598  */
100599 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
100600 
100601 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
100602 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
100603 /*! CONFLICT_CHK_EN - Conflict check enable
100604  *  0b0..Conflict check disable
100605  *  0b1..Conflict check enable
100606  */
100607 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
100608 
100609 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
100610 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
100611 /*! AC12_WR_CHKBUSY_EN - Check busy enable
100612  *  0b0..Do not check busy after auto CMD12 for write data packet
100613  *  0b1..Check busy after auto CMD12 for write data packet
100614  */
100615 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
100616 
100617 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
100618 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
100619 /*! FRC_SDCLK_ON - Force CLK
100620  *  0b0..CLK active or inactive is fully controlled by the hardware.
100621  *  0b1..Force CLK active
100622  */
100623 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
100624 
100625 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
100626 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
100627 /*! CRC_CHK_DIS - CRC Check Disable
100628  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
100629  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
100630  */
100631 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
100632 
100633 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
100634 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
100635 /*! CMD_BYTE_EN - Byte access
100636  *  0b0..Disable
100637  *  0b1..Enable
100638  */
100639 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
100640 /*! @} */
100641 
100642 /*! @name MMC_BOOT - MMC Boot */
100643 /*! @{ */
100644 
100645 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
100646 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
100647 /*! DTOCV_ACK - Boot ACK time out
100648  *  0b0000..SDCLK x 2^14
100649  *  0b0001..SDCLK x 2^15
100650  *  0b0010..SDCLK x 2^16
100651  *  0b0011..SDCLK x 2^17
100652  *  0b0100..SDCLK x 2^18
100653  *  0b0101..SDCLK x 2^19
100654  *  0b0110..SDCLK x 2^20
100655  *  0b0111..SDCLK x 2^21
100656  *  0b1110..SDCLK x 2^28
100657  *  0b1111..SDCLK x 2^29
100658  */
100659 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
100660 
100661 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
100662 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
100663 /*! BOOT_ACK - BOOT ACK
100664  *  0b0..No ack
100665  *  0b1..Ack
100666  */
100667 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
100668 
100669 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
100670 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
100671 /*! BOOT_MODE - Boot mode
100672  *  0b0..Normal boot
100673  *  0b1..Alternative boot
100674  */
100675 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
100676 
100677 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
100678 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
100679 /*! BOOT_EN - Boot enable
100680  *  0b0..Fast boot disable
100681  *  0b1..Fast boot enable
100682  */
100683 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
100684 
100685 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
100686 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
100687 /*! AUTO_SABG_EN - Auto stop at block gap
100688  */
100689 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
100690 
100691 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
100692 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
100693 /*! DISABLE_TIME_OUT - Time out
100694  *  0b0..Enable time out
100695  *  0b1..Disable time out
100696  */
100697 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
100698 
100699 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
100700 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
100701 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
100702  */
100703 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
100704 /*! @} */
100705 
100706 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
100707 /*! @{ */
100708 
100709 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
100710 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
100711 /*! CARD_INT_D3_TEST - Card interrupt detection test
100712  *  0b0..Check the card interrupt only when DATA3 is high.
100713  *  0b1..Check the card interrupt by ignoring the status of DATA3.
100714  */
100715 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
100716 
100717 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
100718 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
100719 /*! TUNING_8bit_EN - Tuning 8bit enable
100720  */
100721 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
100722 
100723 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
100724 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
100725 /*! TUNING_1bit_EN - Tuning 1bit enable
100726  */
100727 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
100728 
100729 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
100730 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
100731 /*! TUNING_CMD_EN - Tuning command enable
100732  *  0b0..Auto tuning circuit does not check the CMD line.
100733  *  0b1..Auto tuning circuit checks the CMD line.
100734  */
100735 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
100736 
100737 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
100738 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
100739 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
100740  */
100741 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
100742 
100743 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
100744 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
100745 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
100746  */
100747 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
100748 
100749 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
100750 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
100751 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
100752  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
100753  *  0b0..Disable
100754  */
100755 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
100756 /*! @} */
100757 
100758 /*! @name TUNING_CTRL - Tuning Control */
100759 /*! @{ */
100760 
100761 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
100762 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
100763 /*! TUNING_START_TAP - Tuning start
100764  */
100765 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
100766 
100767 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
100768 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
100769 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning
100770  */
100771 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
100772 
100773 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
100774 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
100775 /*! TUNING_COUNTER - Tuning counter
100776  */
100777 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
100778 
100779 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
100780 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
100781 /*! TUNING_STEP - TUNING_STEP
100782  */
100783 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
100784 
100785 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
100786 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
100787 /*! TUNING_WINDOW - Data window
100788  */
100789 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
100790 
100791 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
100792 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
100793 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable
100794  */
100795 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
100796 /*! @} */
100797 
100798 
100799 /*!
100800  * @}
100801  */ /* end of group USDHC_Register_Masks */
100802 
100803 
100804 /* USDHC - Peripheral instance base addresses */
100805 /** Peripheral USDHC1 base address */
100806 #define USDHC1_BASE                              (0x40418000u)
100807 /** Peripheral USDHC1 base pointer */
100808 #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
100809 /** Peripheral USDHC2 base address */
100810 #define USDHC2_BASE                              (0x4041C000u)
100811 /** Peripheral USDHC2 base pointer */
100812 #define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
100813 /** Array initializer of USDHC peripheral base addresses */
100814 #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE, USDHC2_BASE }
100815 /** Array initializer of USDHC peripheral base pointers */
100816 #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1, USDHC2 }
100817 /** Interrupt vectors for the USDHC peripheral type */
100818 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
100819 
100820 /*!
100821  * @}
100822  */ /* end of group USDHC_Peripheral_Access_Layer */
100823 
100824 
100825 /* ----------------------------------------------------------------------------
100826    -- VIDEO_MUX Peripheral Access Layer
100827    ---------------------------------------------------------------------------- */
100828 
100829 /*!
100830  * @addtogroup VIDEO_MUX_Peripheral_Access_Layer VIDEO_MUX Peripheral Access Layer
100831  * @{
100832  */
100833 
100834 /** VIDEO_MUX - Register Layout Typedef */
100835 typedef struct {
100836   struct {                                         /* offset: 0x0 */
100837     __IO uint32_t RW;                                /**< Video mux Control Register, offset: 0x0 */
100838     __IO uint32_t SET;                               /**< Video mux Control Register, offset: 0x4 */
100839     __IO uint32_t CLR;                               /**< Video mux Control Register, offset: 0x8 */
100840     __IO uint32_t TOG;                               /**< Video mux Control Register, offset: 0xC */
100841   } VID_MUX_CTRL;
100842        uint8_t RESERVED_0[16];
100843   struct {                                         /* offset: 0x20 */
100844     __IO uint32_t RW;                                /**< Pixel Link Master(PLM) Control Register, offset: 0x20 */
100845     __IO uint32_t SET;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x24 */
100846     __IO uint32_t CLR;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x28 */
100847     __IO uint32_t TOG;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x2C */
100848   } PLM_CTRL;
100849   struct {                                         /* offset: 0x30 */
100850     __IO uint32_t RW;                                /**< YUV420 Control Register, offset: 0x30 */
100851     __IO uint32_t SET;                               /**< YUV420 Control Register, offset: 0x34 */
100852     __IO uint32_t CLR;                               /**< YUV420 Control Register, offset: 0x38 */
100853     __IO uint32_t TOG;                               /**< YUV420 Control Register, offset: 0x3C */
100854   } YUV420_CTRL;
100855        uint8_t RESERVED_1[16];
100856   struct {                                         /* offset: 0x50 */
100857     __IO uint32_t RW;                                /**< Data Disable Register, offset: 0x50 */
100858     __IO uint32_t SET;                               /**< Data Disable Register, offset: 0x54 */
100859     __IO uint32_t CLR;                               /**< Data Disable Register, offset: 0x58 */
100860     __IO uint32_t TOG;                               /**< Data Disable Register, offset: 0x5C */
100861   } CFG_DT_DISABLE;
100862        uint8_t RESERVED_2[16];
100863   struct {                                         /* offset: 0x70 */
100864     __IO uint32_t RW;                                /**< MIPI DSI Control Register, offset: 0x70 */
100865     __IO uint32_t SET;                               /**< MIPI DSI Control Register, offset: 0x74 */
100866     __IO uint32_t CLR;                               /**< MIPI DSI Control Register, offset: 0x78 */
100867     __IO uint32_t TOG;                               /**< MIPI DSI Control Register, offset: 0x7C */
100868   } MIPI_DSI_CTRL;
100869 } VIDEO_MUX_Type;
100870 
100871 /* ----------------------------------------------------------------------------
100872    -- VIDEO_MUX Register Masks
100873    ---------------------------------------------------------------------------- */
100874 
100875 /*!
100876  * @addtogroup VIDEO_MUX_Register_Masks VIDEO_MUX Register Masks
100877  * @{
100878  */
100879 
100880 /*! @name VID_MUX_CTRL - Video mux Control Register */
100881 /*! @{ */
100882 
100883 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK      (0x1U)
100884 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT     (0U)
100885 /*! CSI_SEL - CSI sensor data input mux selector
100886  *  0b0..CSI sensor data is from Parallel CSI
100887  *  0b1..CSI sensor data is from MIPI CSI
100888  */
100889 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
100890 
100891 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
100892 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT  (1U)
100893 /*! LCDIF2_SEL - LCDIF2 sensor data input mux selector
100894  *  0b0..LCDIFv2 sensor data is from Parallel CSI
100895  *  0b1..LCDIFv2 sensor data is from MIPI CSI
100896  */
100897 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
100898 
100899 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U)
100900 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U)
100901 /*! MIPI_DSI_SEL - MIPI DSI video data input mux selector
100902  *  0b0..MIPI DSI video data is from eLCDIF
100903  *  0b1..MIPI DSI video data is from LCDIFv2
100904  */
100905 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
100906 
100907 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U)
100908 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U)
100909 /*! PARA_LCD_SEL - Parallel LCDIF video data input mux selector
100910  *  0b0..Parallel LCDIF video data is from eLCDIF
100911  *  0b1..Parallel LCDIF video data is from LCDIFv2
100912  */
100913 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
100914 /*! @} */
100915 
100916 /*! @name PLM_CTRL - Pixel Link Master(PLM) Control Register */
100917 /*! @{ */
100918 
100919 #define VIDEO_MUX_PLM_CTRL_ENABLE_MASK           (0x1U)
100920 #define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT          (0U)
100921 /*! ENABLE - Enable the output of HYSNC and VSYNC
100922  *  0b0..No active HSYNC and VSYNC output
100923  *  0b1..Active HSYNC and VSYNC output
100924  */
100925 #define VIDEO_MUX_PLM_CTRL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
100926 
100927 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
100928 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT  (1U)
100929 /*! VSYNC_OVERRIDE - VSYNC override
100930  *  0b1..VSYNC is asserted
100931  *  0b0..VSYNC is not asserted
100932  */
100933 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
100934 
100935 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
100936 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT  (2U)
100937 /*! HSYNC_OVERRIDE - HSYNC override
100938  *  0b1..HSYNC is asserted
100939  *  0b0..HSYNC is not asserted
100940  */
100941 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
100942 
100943 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
100944 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT  (3U)
100945 /*! VALID_OVERRIDE - Valid override
100946  *  0b0..HSYNC and VSYNC is asserted
100947  *  0b1..HSYNC and VSYNC is not asserted
100948  */
100949 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
100950 
100951 #define VIDEO_MUX_PLM_CTRL_POLARITY_MASK         (0x10U)
100952 #define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT        (4U)
100953 /*! POLARITY - Polarity of HYSNC/VSYNC
100954  *  0b0..Keep the current polarity of HSYNC and VSYNC
100955  *  0b1..Invert the polarity of HSYNC and VSYNC
100956  */
100957 #define VIDEO_MUX_PLM_CTRL_POLARITY(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
100958 /*! @} */
100959 
100960 /*! @name YUV420_CTRL - YUV420 Control Register */
100961 /*! @{ */
100962 
100963 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U)
100964 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U)
100965 /*! FST_LN_DATA_TYPE - Data type of First Line
100966  *  0b0..Odd (default)
100967  *  0b1..Even
100968  */
100969 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
100970 /*! @} */
100971 
100972 /*! @name CFG_DT_DISABLE - Data Disable Register */
100973 /*! @{ */
100974 
100975 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU)
100976 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U)
100977 /*! CFG_DT_DISABLE - Data Type Disable
100978  */
100979 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
100980 /*! @} */
100981 
100982 /*! @name MIPI_DSI_CTRL - MIPI DSI Control Register */
100983 /*! @{ */
100984 
100985 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK      (0x1U)
100986 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT     (0U)
100987 /*! DPI_SD - Shut Down - Control to shutdown display (type 4 only)
100988  *  0b0..No effect
100989  *  0b1..Send shutdown command
100990  */
100991 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
100992 
100993 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK      (0x2U)
100994 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT     (1U)
100995 /*! DPI_CM - Color Mode control
100996  *  0b0..Normal Mode
100997  *  0b1..Low-color mode
100998  */
100999 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
101000 /*! @} */
101001 
101002 
101003 /*!
101004  * @}
101005  */ /* end of group VIDEO_MUX_Register_Masks */
101006 
101007 
101008 /* VIDEO_MUX - Peripheral instance base addresses */
101009 /** Peripheral VIDEO_MUX base address */
101010 #define VIDEO_MUX_BASE                           (0x40818000u)
101011 /** Peripheral VIDEO_MUX base pointer */
101012 #define VIDEO_MUX                                ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
101013 /** Array initializer of VIDEO_MUX peripheral base addresses */
101014 #define VIDEO_MUX_BASE_ADDRS                     { VIDEO_MUX_BASE }
101015 /** Array initializer of VIDEO_MUX peripheral base pointers */
101016 #define VIDEO_MUX_BASE_PTRS                      { VIDEO_MUX }
101017 
101018 /*!
101019  * @}
101020  */ /* end of group VIDEO_MUX_Peripheral_Access_Layer */
101021 
101022 
101023 /* ----------------------------------------------------------------------------
101024    -- VIDEO_PLL Peripheral Access Layer
101025    ---------------------------------------------------------------------------- */
101026 
101027 /*!
101028  * @addtogroup VIDEO_PLL_Peripheral_Access_Layer VIDEO_PLL Peripheral Access Layer
101029  * @{
101030  */
101031 
101032 /** VIDEO_PLL - Register Layout Typedef */
101033 typedef struct {
101034   struct {                                         /* offset: 0x0 */
101035     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
101036     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
101037     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
101038     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
101039   } CTRL0;
101040   struct {                                         /* offset: 0x10 */
101041     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
101042     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
101043     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
101044     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
101045   } SPREAD_SPECTRUM;
101046   struct {                                         /* offset: 0x20 */
101047     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
101048     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
101049     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
101050     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
101051   } NUMERATOR;
101052   struct {                                         /* offset: 0x30 */
101053     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
101054     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
101055     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
101056     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
101057   } DENOMINATOR;
101058 } VIDEO_PLL_Type;
101059 
101060 /* ----------------------------------------------------------------------------
101061    -- VIDEO_PLL Register Masks
101062    ---------------------------------------------------------------------------- */
101063 
101064 /*!
101065  * @addtogroup VIDEO_PLL_Register_Masks VIDEO_PLL Register Masks
101066  * @{
101067  */
101068 
101069 /*! @name CTRL0 - Fractional PLL Control Register */
101070 /*! @{ */
101071 
101072 #define VIDEO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
101073 #define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
101074 /*! DIV_SELECT - DIV_SELECT
101075  */
101076 #define VIDEO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK)
101077 
101078 #define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
101079 #define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
101080 /*! ENABLE_ALT - ENABLE_ALT
101081  *  0b0..Disable the alternate clock output
101082  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
101083  */
101084 #define VIDEO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK)
101085 
101086 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
101087 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
101088 /*! HOLD_RING_OFF - PLL Start up initialization
101089  *  0b0..Normal operation
101090  *  0b1..Initialize PLL start up
101091  */
101092 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK)
101093 
101094 #define VIDEO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
101095 #define VIDEO_PLL_CTRL0_POWERUP_SHIFT            (14U)
101096 /*! POWERUP - POWERUP
101097  *  0b1..Power Up the PLL
101098  *  0b0..Power down the PLL
101099  */
101100 #define VIDEO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK)
101101 
101102 #define VIDEO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
101103 #define VIDEO_PLL_CTRL0_ENABLE_SHIFT             (15U)
101104 /*! ENABLE - ENABLE
101105  *  0b1..Enable the clock output
101106  *  0b0..Disable the clock output
101107  */
101108 #define VIDEO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK)
101109 
101110 #define VIDEO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
101111 #define VIDEO_PLL_CTRL0_BYPASS_SHIFT             (16U)
101112 /*! BYPASS - BYPASS
101113  *  0b1..Bypass the PLL
101114  *  0b0..No Bypass
101115  */
101116 #define VIDEO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK)
101117 
101118 #define VIDEO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
101119 #define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
101120 /*! DITHER_EN - DITHER_EN
101121  *  0b0..Disable Dither
101122  *  0b1..Enable Dither
101123  */
101124 #define VIDEO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK)
101125 
101126 #define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
101127 #define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
101128 /*! BIAS_TRIM - BIAS_TRIM
101129  */
101130 #define VIDEO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK)
101131 
101132 #define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
101133 #define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
101134 /*! PLL_REG_EN - PLL_REG_EN
101135  */
101136 #define VIDEO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK)
101137 
101138 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
101139 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
101140 /*! POST_DIV_SEL - Post Divide Select
101141  *  0b000..Divide by 1
101142  *  0b001..Divide by 2
101143  *  0b010..Divide by 4
101144  *  0b011..Divide by 8
101145  *  0b100..Divide by 16
101146  *  0b101..Divide by 32
101147  */
101148 #define VIDEO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK)
101149 
101150 #define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
101151 #define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
101152 /*! BIAS_SELECT - BIAS_SELECT
101153  *  0b0..Used in SoCs with a bias current of 10uA
101154  *  0b1..Used in SoCs with a bias current of 2uA
101155  */
101156 #define VIDEO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK)
101157 /*! @} */
101158 
101159 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
101160 /*! @{ */
101161 
101162 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
101163 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
101164 /*! STEP - Step
101165  */
101166 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK)
101167 
101168 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
101169 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
101170 /*! ENABLE - Enable
101171  */
101172 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
101173 
101174 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
101175 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
101176 /*! STOP - Stop
101177  */
101178 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK)
101179 /*! @} */
101180 
101181 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
101182 /*! @{ */
101183 
101184 #define VIDEO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
101185 #define VIDEO_PLL_NUMERATOR_NUM_SHIFT            (0U)
101186 /*! NUM - Numerator
101187  */
101188 #define VIDEO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK)
101189 /*! @} */
101190 
101191 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
101192 /*! @{ */
101193 
101194 #define VIDEO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
101195 #define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
101196 /*! DENOM - Denominator
101197  */
101198 #define VIDEO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK)
101199 /*! @} */
101200 
101201 
101202 /*!
101203  * @}
101204  */ /* end of group VIDEO_PLL_Register_Masks */
101205 
101206 
101207 /* VIDEO_PLL - Peripheral instance base addresses */
101208 /** Peripheral VIDEO_PLL base address */
101209 #define VIDEO_PLL_BASE                           (0u)
101210 /** Peripheral VIDEO_PLL base pointer */
101211 #define VIDEO_PLL                                ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
101212 /** Array initializer of VIDEO_PLL peripheral base addresses */
101213 #define VIDEO_PLL_BASE_ADDRS                     { VIDEO_PLL_BASE }
101214 /** Array initializer of VIDEO_PLL peripheral base pointers */
101215 #define VIDEO_PLL_BASE_PTRS                      { VIDEO_PLL }
101216 
101217 /*!
101218  * @}
101219  */ /* end of group VIDEO_PLL_Peripheral_Access_Layer */
101220 
101221 
101222 /* ----------------------------------------------------------------------------
101223    -- VMBANDGAP Peripheral Access Layer
101224    ---------------------------------------------------------------------------- */
101225 
101226 /*!
101227  * @addtogroup VMBANDGAP_Peripheral_Access_Layer VMBANDGAP Peripheral Access Layer
101228  * @{
101229  */
101230 
101231 /** VMBANDGAP - Register Layout Typedef */
101232 typedef struct {
101233   struct {                                         /* offset: 0x0 */
101234     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
101235     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
101236     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
101237     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
101238   } CTRL0;
101239        uint8_t RESERVED_0[64];
101240   struct {                                         /* offset: 0x50 */
101241     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
101242     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
101243     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
101244     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
101245   } STAT0;
101246 } VMBANDGAP_Type;
101247 
101248 /* ----------------------------------------------------------------------------
101249    -- VMBANDGAP Register Masks
101250    ---------------------------------------------------------------------------- */
101251 
101252 /*!
101253  * @addtogroup VMBANDGAP_Register_Masks VMBANDGAP Register Masks
101254  * @{
101255  */
101256 
101257 /*! @name CTRL0 - Analog Control Register CTRL0 */
101258 /*! @{ */
101259 
101260 #define VMBANDGAP_CTRL0_REFTOP_PWD_MASK          (0x1U)
101261 #define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT         (0U)
101262 /*! REFTOP_PWD - Master power-down for bandgap module
101263  */
101264 #define VMBANDGAP_CTRL0_REFTOP_PWD(x)            (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
101265 
101266 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
101267 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
101268 /*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer
101269  */
101270 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)  (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
101271 
101272 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK     (0x4U)
101273 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT    (2U)
101274 /*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap
101275  */
101276 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
101277 
101278 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK     (0x8U)
101279 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT    (3U)
101280 /*! REFTOP_LOWPOWER - Low-power control bit
101281  */
101282 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
101283 
101284 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK  (0x10U)
101285 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
101286 /*! REFTOP_SELFBIASOFF - bandgap self-bias control bit
101287  */
101288 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)    (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
101289 /*! @} */
101290 
101291 /*! @name STAT0 - Analog Status Register STAT0 */
101292 /*! @{ */
101293 
101294 #define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK        (0x1U)
101295 #define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT       (0U)
101296 /*! REFTOP_VBGUP - Brief description here
101297  */
101298 #define VMBANDGAP_STAT0_REFTOP_VBGUP(x)          (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
101299 
101300 #define VMBANDGAP_STAT0_VDD1_PORB_MASK           (0x2U)
101301 #define VMBANDGAP_STAT0_VDD1_PORB_SHIFT          (1U)
101302 /*! VDD1_PORB - Brief description here
101303  */
101304 #define VMBANDGAP_STAT0_VDD1_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
101305 
101306 #define VMBANDGAP_STAT0_VDD2_PORB_MASK           (0x4U)
101307 #define VMBANDGAP_STAT0_VDD2_PORB_SHIFT          (2U)
101308 /*! VDD2_PORB - Brief description here
101309  */
101310 #define VMBANDGAP_STAT0_VDD2_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
101311 
101312 #define VMBANDGAP_STAT0_VDD3_PORB_MASK           (0x8U)
101313 #define VMBANDGAP_STAT0_VDD3_PORB_SHIFT          (3U)
101314 /*! VDD3_PORB - Brief description here
101315  */
101316 #define VMBANDGAP_STAT0_VDD3_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK)
101317 /*! @} */
101318 
101319 
101320 /*!
101321  * @}
101322  */ /* end of group VMBANDGAP_Register_Masks */
101323 
101324 
101325 /* VMBANDGAP - Peripheral instance base addresses */
101326 /** Peripheral VMBANDGAP base address */
101327 #define VMBANDGAP_BASE                           (0u)
101328 /** Peripheral VMBANDGAP base pointer */
101329 #define VMBANDGAP                                ((VMBANDGAP_Type *)VMBANDGAP_BASE)
101330 /** Array initializer of VMBANDGAP peripheral base addresses */
101331 #define VMBANDGAP_BASE_ADDRS                     { VMBANDGAP_BASE }
101332 /** Array initializer of VMBANDGAP peripheral base pointers */
101333 #define VMBANDGAP_BASE_PTRS                      { VMBANDGAP }
101334 
101335 /*!
101336  * @}
101337  */ /* end of group VMBANDGAP_Peripheral_Access_Layer */
101338 
101339 
101340 /* ----------------------------------------------------------------------------
101341    -- WDOG Peripheral Access Layer
101342    ---------------------------------------------------------------------------- */
101343 
101344 /*!
101345  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
101346  * @{
101347  */
101348 
101349 /** WDOG - Register Layout Typedef */
101350 typedef struct {
101351   __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
101352   __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
101353   __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
101354   __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
101355   __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
101356 } WDOG_Type;
101357 
101358 /* ----------------------------------------------------------------------------
101359    -- WDOG Register Masks
101360    ---------------------------------------------------------------------------- */
101361 
101362 /*!
101363  * @addtogroup WDOG_Register_Masks WDOG Register Masks
101364  * @{
101365  */
101366 
101367 /*! @name WCR - Watchdog Control Register */
101368 /*! @{ */
101369 
101370 #define WDOG_WCR_WDZST_MASK                      (0x1U)
101371 #define WDOG_WCR_WDZST_SHIFT                     (0U)
101372 /*! WDZST - WDZST
101373  *  0b0..Continue timer operation (Default).
101374  *  0b1..Suspend the watchdog timer.
101375  */
101376 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
101377 
101378 #define WDOG_WCR_WDBG_MASK                       (0x2U)
101379 #define WDOG_WCR_WDBG_SHIFT                      (1U)
101380 /*! WDBG - WDBG
101381  *  0b0..Continue WDOG timer operation (Default).
101382  *  0b1..Suspend the watchdog timer.
101383  */
101384 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
101385 
101386 #define WDOG_WCR_WDE_MASK                        (0x4U)
101387 #define WDOG_WCR_WDE_SHIFT                       (2U)
101388 /*! WDE - WDE
101389  *  0b0..Disable the Watchdog (Default).
101390  *  0b1..Enable the Watchdog.
101391  */
101392 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
101393 
101394 #define WDOG_WCR_WDT_MASK                        (0x8U)
101395 #define WDOG_WCR_WDT_SHIFT                       (3U)
101396 /*! WDT - WDT
101397  *  0b0..No effect on WDOG_B (Default).
101398  *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
101399  */
101400 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
101401 
101402 #define WDOG_WCR_SRS_MASK                        (0x10U)
101403 #define WDOG_WCR_SRS_SHIFT                       (4U)
101404 /*! SRS - SRS
101405  *  0b0..Assert system reset signal.
101406  *  0b1..No effect on the system (Default).
101407  */
101408 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
101409 
101410 #define WDOG_WCR_WDA_MASK                        (0x20U)
101411 #define WDOG_WCR_WDA_SHIFT                       (5U)
101412 /*! WDA - WDA
101413  *  0b0..Assert WDOG_B output.
101414  *  0b1..No effect on system (Default).
101415  */
101416 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
101417 
101418 #define WDOG_WCR_SRE_MASK                        (0x40U)
101419 #define WDOG_WCR_SRE_SHIFT                       (6U)
101420 /*! SRE - Software Reset Extension, an optional way to generate software reset
101421  *  0b0..using original way to generate software reset (default)
101422  *  0b1..using new way to generate software reset.
101423  */
101424 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
101425 
101426 #define WDOG_WCR_WDW_MASK                        (0x80U)
101427 #define WDOG_WCR_WDW_SHIFT                       (7U)
101428 /*! WDW - WDW
101429  *  0b0..Continue WDOG timer operation (Default).
101430  *  0b1..Suspend WDOG timer operation.
101431  */
101432 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
101433 
101434 #define WDOG_WCR_WT_MASK                         (0xFF00U)
101435 #define WDOG_WCR_WT_SHIFT                        (8U)
101436 /*! WT - WT
101437  *  0b00000000..- 0.5 Seconds (Default).
101438  *  0b00000001..- 1.0 Seconds.
101439  *  0b00000010..- 1.5 Seconds.
101440  *  0b00000011..- 2.0 Seconds.
101441  *  0b11111111..- 128 Seconds.
101442  */
101443 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
101444 /*! @} */
101445 
101446 /*! @name WSR - Watchdog Service Register */
101447 /*! @{ */
101448 
101449 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
101450 #define WDOG_WSR_WSR_SHIFT                       (0U)
101451 /*! WSR - WSR
101452  *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
101453  *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
101454  */
101455 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
101456 /*! @} */
101457 
101458 /*! @name WRSR - Watchdog Reset Status Register */
101459 /*! @{ */
101460 
101461 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
101462 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
101463 /*! SFTW - SFTW
101464  *  0b0..Reset is not the result of a software reset.
101465  *  0b1..Reset is the result of a software reset.
101466  */
101467 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
101468 
101469 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
101470 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
101471 /*! TOUT - TOUT
101472  *  0b0..Reset is not the result of a WDOG timeout.
101473  *  0b1..Reset is the result of a WDOG timeout.
101474  */
101475 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
101476 
101477 #define WDOG_WRSR_POR_MASK                       (0x10U)
101478 #define WDOG_WRSR_POR_SHIFT                      (4U)
101479 /*! POR - POR
101480  *  0b0..Reset is not the result of a power on reset.
101481  *  0b1..Reset is the result of a power on reset.
101482  */
101483 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
101484 /*! @} */
101485 
101486 /*! @name WICR - Watchdog Interrupt Control Register */
101487 /*! @{ */
101488 
101489 #define WDOG_WICR_WICT_MASK                      (0xFFU)
101490 #define WDOG_WICR_WICT_SHIFT                     (0U)
101491 /*! WICT - WICT
101492  *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
101493  *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
101494  *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
101495  *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
101496  */
101497 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
101498 
101499 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
101500 #define WDOG_WICR_WTIS_SHIFT                     (14U)
101501 /*! WTIS - WTIS
101502  *  0b0..No interrupt has occurred (Default).
101503  *  0b1..Interrupt has occurred
101504  */
101505 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
101506 
101507 #define WDOG_WICR_WIE_MASK                       (0x8000U)
101508 #define WDOG_WICR_WIE_SHIFT                      (15U)
101509 /*! WIE - WIE
101510  *  0b0..Disable Interrupt (Default).
101511  *  0b1..Enable Interrupt.
101512  */
101513 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
101514 /*! @} */
101515 
101516 /*! @name WMCR - Watchdog Miscellaneous Control Register */
101517 /*! @{ */
101518 
101519 #define WDOG_WMCR_PDE_MASK                       (0x1U)
101520 #define WDOG_WMCR_PDE_SHIFT                      (0U)
101521 /*! PDE - PDE
101522  *  0b0..Power Down Counter of WDOG is disabled.
101523  *  0b1..Power Down Counter of WDOG is enabled (Default).
101524  */
101525 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
101526 /*! @} */
101527 
101528 
101529 /*!
101530  * @}
101531  */ /* end of group WDOG_Register_Masks */
101532 
101533 
101534 /* WDOG - Peripheral instance base addresses */
101535 /** Peripheral WDOG1 base address */
101536 #define WDOG1_BASE                               (0x40030000u)
101537 /** Peripheral WDOG1 base pointer */
101538 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
101539 /** Peripheral WDOG2 base address */
101540 #define WDOG2_BASE                               (0x40034000u)
101541 /** Peripheral WDOG2 base pointer */
101542 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
101543 /** Array initializer of WDOG peripheral base addresses */
101544 #define WDOG_BASE_ADDRS                          { 0u, WDOG1_BASE, WDOG2_BASE }
101545 /** Array initializer of WDOG peripheral base pointers */
101546 #define WDOG_BASE_PTRS                           { (WDOG_Type *)0u, WDOG1, WDOG2 }
101547 /** Interrupt vectors for the WDOG peripheral type */
101548 #define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
101549 
101550 /*!
101551  * @}
101552  */ /* end of group WDOG_Peripheral_Access_Layer */
101553 
101554 
101555 /* ----------------------------------------------------------------------------
101556    -- XBARA Peripheral Access Layer
101557    ---------------------------------------------------------------------------- */
101558 
101559 /*!
101560  * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
101561  * @{
101562  */
101563 
101564 /** XBARA - Register Layout Typedef */
101565 typedef struct {
101566   __IO uint16_t SEL0;                              /**< Crossbar A Select Register 0, offset: 0x0 */
101567   __IO uint16_t SEL1;                              /**< Crossbar A Select Register 1, offset: 0x2 */
101568   __IO uint16_t SEL2;                              /**< Crossbar A Select Register 2, offset: 0x4 */
101569   __IO uint16_t SEL3;                              /**< Crossbar A Select Register 3, offset: 0x6 */
101570   __IO uint16_t SEL4;                              /**< Crossbar A Select Register 4, offset: 0x8 */
101571   __IO uint16_t SEL5;                              /**< Crossbar A Select Register 5, offset: 0xA */
101572   __IO uint16_t SEL6;                              /**< Crossbar A Select Register 6, offset: 0xC */
101573   __IO uint16_t SEL7;                              /**< Crossbar A Select Register 7, offset: 0xE */
101574   __IO uint16_t SEL8;                              /**< Crossbar A Select Register 8, offset: 0x10 */
101575   __IO uint16_t SEL9;                              /**< Crossbar A Select Register 9, offset: 0x12 */
101576   __IO uint16_t SEL10;                             /**< Crossbar A Select Register 10, offset: 0x14 */
101577   __IO uint16_t SEL11;                             /**< Crossbar A Select Register 11, offset: 0x16 */
101578   __IO uint16_t SEL12;                             /**< Crossbar A Select Register 12, offset: 0x18 */
101579   __IO uint16_t SEL13;                             /**< Crossbar A Select Register 13, offset: 0x1A */
101580   __IO uint16_t SEL14;                             /**< Crossbar A Select Register 14, offset: 0x1C */
101581   __IO uint16_t SEL15;                             /**< Crossbar A Select Register 15, offset: 0x1E */
101582   __IO uint16_t SEL16;                             /**< Crossbar A Select Register 16, offset: 0x20 */
101583   __IO uint16_t SEL17;                             /**< Crossbar A Select Register 17, offset: 0x22 */
101584   __IO uint16_t SEL18;                             /**< Crossbar A Select Register 18, offset: 0x24 */
101585   __IO uint16_t SEL19;                             /**< Crossbar A Select Register 19, offset: 0x26 */
101586   __IO uint16_t SEL20;                             /**< Crossbar A Select Register 20, offset: 0x28 */
101587   __IO uint16_t SEL21;                             /**< Crossbar A Select Register 21, offset: 0x2A */
101588   __IO uint16_t SEL22;                             /**< Crossbar A Select Register 22, offset: 0x2C */
101589   __IO uint16_t SEL23;                             /**< Crossbar A Select Register 23, offset: 0x2E */
101590   __IO uint16_t SEL24;                             /**< Crossbar A Select Register 24, offset: 0x30 */
101591   __IO uint16_t SEL25;                             /**< Crossbar A Select Register 25, offset: 0x32 */
101592   __IO uint16_t SEL26;                             /**< Crossbar A Select Register 26, offset: 0x34 */
101593   __IO uint16_t SEL27;                             /**< Crossbar A Select Register 27, offset: 0x36 */
101594   __IO uint16_t SEL28;                             /**< Crossbar A Select Register 28, offset: 0x38 */
101595   __IO uint16_t SEL29;                             /**< Crossbar A Select Register 29, offset: 0x3A */
101596   __IO uint16_t SEL30;                             /**< Crossbar A Select Register 30, offset: 0x3C */
101597   __IO uint16_t SEL31;                             /**< Crossbar A Select Register 31, offset: 0x3E */
101598   __IO uint16_t SEL32;                             /**< Crossbar A Select Register 32, offset: 0x40 */
101599   __IO uint16_t SEL33;                             /**< Crossbar A Select Register 33, offset: 0x42 */
101600   __IO uint16_t SEL34;                             /**< Crossbar A Select Register 34, offset: 0x44 */
101601   __IO uint16_t SEL35;                             /**< Crossbar A Select Register 35, offset: 0x46 */
101602   __IO uint16_t SEL36;                             /**< Crossbar A Select Register 36, offset: 0x48 */
101603   __IO uint16_t SEL37;                             /**< Crossbar A Select Register 37, offset: 0x4A */
101604   __IO uint16_t SEL38;                             /**< Crossbar A Select Register 38, offset: 0x4C */
101605   __IO uint16_t SEL39;                             /**< Crossbar A Select Register 39, offset: 0x4E */
101606   __IO uint16_t SEL40;                             /**< Crossbar A Select Register 40, offset: 0x50 */
101607   __IO uint16_t SEL41;                             /**< Crossbar A Select Register 41, offset: 0x52 */
101608   __IO uint16_t SEL42;                             /**< Crossbar A Select Register 42, offset: 0x54 */
101609   __IO uint16_t SEL43;                             /**< Crossbar A Select Register 43, offset: 0x56 */
101610   __IO uint16_t SEL44;                             /**< Crossbar A Select Register 44, offset: 0x58 */
101611   __IO uint16_t SEL45;                             /**< Crossbar A Select Register 45, offset: 0x5A */
101612   __IO uint16_t SEL46;                             /**< Crossbar A Select Register 46, offset: 0x5C */
101613   __IO uint16_t SEL47;                             /**< Crossbar A Select Register 47, offset: 0x5E */
101614   __IO uint16_t SEL48;                             /**< Crossbar A Select Register 48, offset: 0x60 */
101615   __IO uint16_t SEL49;                             /**< Crossbar A Select Register 49, offset: 0x62 */
101616   __IO uint16_t SEL50;                             /**< Crossbar A Select Register 50, offset: 0x64 */
101617   __IO uint16_t SEL51;                             /**< Crossbar A Select Register 51, offset: 0x66 */
101618   __IO uint16_t SEL52;                             /**< Crossbar A Select Register 52, offset: 0x68 */
101619   __IO uint16_t SEL53;                             /**< Crossbar A Select Register 53, offset: 0x6A */
101620   __IO uint16_t SEL54;                             /**< Crossbar A Select Register 54, offset: 0x6C */
101621   __IO uint16_t SEL55;                             /**< Crossbar A Select Register 55, offset: 0x6E */
101622   __IO uint16_t SEL56;                             /**< Crossbar A Select Register 56, offset: 0x70 */
101623   __IO uint16_t SEL57;                             /**< Crossbar A Select Register 57, offset: 0x72 */
101624   __IO uint16_t SEL58;                             /**< Crossbar A Select Register 58, offset: 0x74 */
101625   __IO uint16_t SEL59;                             /**< Crossbar A Select Register 59, offset: 0x76 */
101626   __IO uint16_t SEL60;                             /**< Crossbar A Select Register 60, offset: 0x78 */
101627   __IO uint16_t SEL61;                             /**< Crossbar A Select Register 61, offset: 0x7A */
101628   __IO uint16_t SEL62;                             /**< Crossbar A Select Register 62, offset: 0x7C */
101629   __IO uint16_t SEL63;                             /**< Crossbar A Select Register 63, offset: 0x7E */
101630   __IO uint16_t SEL64;                             /**< Crossbar A Select Register 64, offset: 0x80 */
101631   __IO uint16_t SEL65;                             /**< Crossbar A Select Register 65, offset: 0x82 */
101632   __IO uint16_t SEL66;                             /**< Crossbar A Select Register 66, offset: 0x84 */
101633   __IO uint16_t SEL67;                             /**< Crossbar A Select Register 67, offset: 0x86 */
101634   __IO uint16_t SEL68;                             /**< Crossbar A Select Register 68, offset: 0x88 */
101635   __IO uint16_t SEL69;                             /**< Crossbar A Select Register 69, offset: 0x8A */
101636   __IO uint16_t SEL70;                             /**< Crossbar A Select Register 70, offset: 0x8C */
101637   __IO uint16_t SEL71;                             /**< Crossbar A Select Register 71, offset: 0x8E */
101638   __IO uint16_t SEL72;                             /**< Crossbar A Select Register 72, offset: 0x90 */
101639   __IO uint16_t SEL73;                             /**< Crossbar A Select Register 73, offset: 0x92 */
101640   __IO uint16_t SEL74;                             /**< Crossbar A Select Register 74, offset: 0x94 */
101641   __IO uint16_t SEL75;                             /**< Crossbar A Select Register 75, offset: 0x96 */
101642   __IO uint16_t SEL76;                             /**< Crossbar A Select Register 76, offset: 0x98 */
101643   __IO uint16_t SEL77;                             /**< Crossbar A Select Register 77, offset: 0x9A */
101644   __IO uint16_t SEL78;                             /**< Crossbar A Select Register 78, offset: 0x9C */
101645   __IO uint16_t SEL79;                             /**< Crossbar A Select Register 79, offset: 0x9E */
101646   __IO uint16_t SEL80;                             /**< Crossbar A Select Register 80, offset: 0xA0 */
101647   __IO uint16_t SEL81;                             /**< Crossbar A Select Register 81, offset: 0xA2 */
101648   __IO uint16_t SEL82;                             /**< Crossbar A Select Register 82, offset: 0xA4 */
101649   __IO uint16_t SEL83;                             /**< Crossbar A Select Register 83, offset: 0xA6 */
101650   __IO uint16_t SEL84;                             /**< Crossbar A Select Register 84, offset: 0xA8 */
101651   __IO uint16_t SEL85;                             /**< Crossbar A Select Register 85, offset: 0xAA */
101652   __IO uint16_t SEL86;                             /**< Crossbar A Select Register 86, offset: 0xAC */
101653   __IO uint16_t SEL87;                             /**< Crossbar A Select Register 87, offset: 0xAE */
101654   __IO uint16_t CTRL0;                             /**< Crossbar A Control Register 0, offset: 0xB0 */
101655   __IO uint16_t CTRL1;                             /**< Crossbar A Control Register 1, offset: 0xB2 */
101656 } XBARA_Type;
101657 
101658 /* ----------------------------------------------------------------------------
101659    -- XBARA Register Masks
101660    ---------------------------------------------------------------------------- */
101661 
101662 /*!
101663  * @addtogroup XBARA_Register_Masks XBARA Register Masks
101664  * @{
101665  */
101666 
101667 /*! @name SEL0 - Crossbar A Select Register 0 */
101668 /*! @{ */
101669 
101670 #define XBARA_SEL0_SEL0_MASK                     (0xFFU)
101671 #define XBARA_SEL0_SEL0_SHIFT                    (0U)
101672 #define XBARA_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
101673 
101674 #define XBARA_SEL0_SEL1_MASK                     (0xFF00U)
101675 #define XBARA_SEL0_SEL1_SHIFT                    (8U)
101676 #define XBARA_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
101677 /*! @} */
101678 
101679 /*! @name SEL1 - Crossbar A Select Register 1 */
101680 /*! @{ */
101681 
101682 #define XBARA_SEL1_SEL2_MASK                     (0xFFU)
101683 #define XBARA_SEL1_SEL2_SHIFT                    (0U)
101684 #define XBARA_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
101685 
101686 #define XBARA_SEL1_SEL3_MASK                     (0xFF00U)
101687 #define XBARA_SEL1_SEL3_SHIFT                    (8U)
101688 #define XBARA_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
101689 /*! @} */
101690 
101691 /*! @name SEL2 - Crossbar A Select Register 2 */
101692 /*! @{ */
101693 
101694 #define XBARA_SEL2_SEL4_MASK                     (0xFFU)
101695 #define XBARA_SEL2_SEL4_SHIFT                    (0U)
101696 #define XBARA_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
101697 
101698 #define XBARA_SEL2_SEL5_MASK                     (0xFF00U)
101699 #define XBARA_SEL2_SEL5_SHIFT                    (8U)
101700 #define XBARA_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
101701 /*! @} */
101702 
101703 /*! @name SEL3 - Crossbar A Select Register 3 */
101704 /*! @{ */
101705 
101706 #define XBARA_SEL3_SEL6_MASK                     (0xFFU)
101707 #define XBARA_SEL3_SEL6_SHIFT                    (0U)
101708 #define XBARA_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
101709 
101710 #define XBARA_SEL3_SEL7_MASK                     (0xFF00U)
101711 #define XBARA_SEL3_SEL7_SHIFT                    (8U)
101712 #define XBARA_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
101713 /*! @} */
101714 
101715 /*! @name SEL4 - Crossbar A Select Register 4 */
101716 /*! @{ */
101717 
101718 #define XBARA_SEL4_SEL8_MASK                     (0xFFU)
101719 #define XBARA_SEL4_SEL8_SHIFT                    (0U)
101720 #define XBARA_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
101721 
101722 #define XBARA_SEL4_SEL9_MASK                     (0xFF00U)
101723 #define XBARA_SEL4_SEL9_SHIFT                    (8U)
101724 #define XBARA_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
101725 /*! @} */
101726 
101727 /*! @name SEL5 - Crossbar A Select Register 5 */
101728 /*! @{ */
101729 
101730 #define XBARA_SEL5_SEL10_MASK                    (0xFFU)
101731 #define XBARA_SEL5_SEL10_SHIFT                   (0U)
101732 #define XBARA_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
101733 
101734 #define XBARA_SEL5_SEL11_MASK                    (0xFF00U)
101735 #define XBARA_SEL5_SEL11_SHIFT                   (8U)
101736 #define XBARA_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
101737 /*! @} */
101738 
101739 /*! @name SEL6 - Crossbar A Select Register 6 */
101740 /*! @{ */
101741 
101742 #define XBARA_SEL6_SEL12_MASK                    (0xFFU)
101743 #define XBARA_SEL6_SEL12_SHIFT                   (0U)
101744 #define XBARA_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
101745 
101746 #define XBARA_SEL6_SEL13_MASK                    (0xFF00U)
101747 #define XBARA_SEL6_SEL13_SHIFT                   (8U)
101748 #define XBARA_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
101749 /*! @} */
101750 
101751 /*! @name SEL7 - Crossbar A Select Register 7 */
101752 /*! @{ */
101753 
101754 #define XBARA_SEL7_SEL14_MASK                    (0xFFU)
101755 #define XBARA_SEL7_SEL14_SHIFT                   (0U)
101756 #define XBARA_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
101757 
101758 #define XBARA_SEL7_SEL15_MASK                    (0xFF00U)
101759 #define XBARA_SEL7_SEL15_SHIFT                   (8U)
101760 #define XBARA_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
101761 /*! @} */
101762 
101763 /*! @name SEL8 - Crossbar A Select Register 8 */
101764 /*! @{ */
101765 
101766 #define XBARA_SEL8_SEL16_MASK                    (0xFFU)
101767 #define XBARA_SEL8_SEL16_SHIFT                   (0U)
101768 #define XBARA_SEL8_SEL16(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
101769 
101770 #define XBARA_SEL8_SEL17_MASK                    (0xFF00U)
101771 #define XBARA_SEL8_SEL17_SHIFT                   (8U)
101772 #define XBARA_SEL8_SEL17(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
101773 /*! @} */
101774 
101775 /*! @name SEL9 - Crossbar A Select Register 9 */
101776 /*! @{ */
101777 
101778 #define XBARA_SEL9_SEL18_MASK                    (0xFFU)
101779 #define XBARA_SEL9_SEL18_SHIFT                   (0U)
101780 #define XBARA_SEL9_SEL18(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
101781 
101782 #define XBARA_SEL9_SEL19_MASK                    (0xFF00U)
101783 #define XBARA_SEL9_SEL19_SHIFT                   (8U)
101784 #define XBARA_SEL9_SEL19(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
101785 /*! @} */
101786 
101787 /*! @name SEL10 - Crossbar A Select Register 10 */
101788 /*! @{ */
101789 
101790 #define XBARA_SEL10_SEL20_MASK                   (0xFFU)
101791 #define XBARA_SEL10_SEL20_SHIFT                  (0U)
101792 #define XBARA_SEL10_SEL20(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
101793 
101794 #define XBARA_SEL10_SEL21_MASK                   (0xFF00U)
101795 #define XBARA_SEL10_SEL21_SHIFT                  (8U)
101796 #define XBARA_SEL10_SEL21(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
101797 /*! @} */
101798 
101799 /*! @name SEL11 - Crossbar A Select Register 11 */
101800 /*! @{ */
101801 
101802 #define XBARA_SEL11_SEL22_MASK                   (0xFFU)
101803 #define XBARA_SEL11_SEL22_SHIFT                  (0U)
101804 #define XBARA_SEL11_SEL22(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
101805 
101806 #define XBARA_SEL11_SEL23_MASK                   (0xFF00U)
101807 #define XBARA_SEL11_SEL23_SHIFT                  (8U)
101808 #define XBARA_SEL11_SEL23(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
101809 /*! @} */
101810 
101811 /*! @name SEL12 - Crossbar A Select Register 12 */
101812 /*! @{ */
101813 
101814 #define XBARA_SEL12_SEL24_MASK                   (0xFFU)
101815 #define XBARA_SEL12_SEL24_SHIFT                  (0U)
101816 #define XBARA_SEL12_SEL24(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
101817 
101818 #define XBARA_SEL12_SEL25_MASK                   (0xFF00U)
101819 #define XBARA_SEL12_SEL25_SHIFT                  (8U)
101820 #define XBARA_SEL12_SEL25(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
101821 /*! @} */
101822 
101823 /*! @name SEL13 - Crossbar A Select Register 13 */
101824 /*! @{ */
101825 
101826 #define XBARA_SEL13_SEL26_MASK                   (0xFFU)
101827 #define XBARA_SEL13_SEL26_SHIFT                  (0U)
101828 #define XBARA_SEL13_SEL26(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
101829 
101830 #define XBARA_SEL13_SEL27_MASK                   (0xFF00U)
101831 #define XBARA_SEL13_SEL27_SHIFT                  (8U)
101832 #define XBARA_SEL13_SEL27(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
101833 /*! @} */
101834 
101835 /*! @name SEL14 - Crossbar A Select Register 14 */
101836 /*! @{ */
101837 
101838 #define XBARA_SEL14_SEL28_MASK                   (0xFFU)
101839 #define XBARA_SEL14_SEL28_SHIFT                  (0U)
101840 #define XBARA_SEL14_SEL28(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
101841 
101842 #define XBARA_SEL14_SEL29_MASK                   (0xFF00U)
101843 #define XBARA_SEL14_SEL29_SHIFT                  (8U)
101844 #define XBARA_SEL14_SEL29(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
101845 /*! @} */
101846 
101847 /*! @name SEL15 - Crossbar A Select Register 15 */
101848 /*! @{ */
101849 
101850 #define XBARA_SEL15_SEL30_MASK                   (0xFFU)
101851 #define XBARA_SEL15_SEL30_SHIFT                  (0U)
101852 #define XBARA_SEL15_SEL30(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
101853 
101854 #define XBARA_SEL15_SEL31_MASK                   (0xFF00U)
101855 #define XBARA_SEL15_SEL31_SHIFT                  (8U)
101856 #define XBARA_SEL15_SEL31(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
101857 /*! @} */
101858 
101859 /*! @name SEL16 - Crossbar A Select Register 16 */
101860 /*! @{ */
101861 
101862 #define XBARA_SEL16_SEL32_MASK                   (0xFFU)
101863 #define XBARA_SEL16_SEL32_SHIFT                  (0U)
101864 #define XBARA_SEL16_SEL32(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
101865 
101866 #define XBARA_SEL16_SEL33_MASK                   (0xFF00U)
101867 #define XBARA_SEL16_SEL33_SHIFT                  (8U)
101868 #define XBARA_SEL16_SEL33(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
101869 /*! @} */
101870 
101871 /*! @name SEL17 - Crossbar A Select Register 17 */
101872 /*! @{ */
101873 
101874 #define XBARA_SEL17_SEL34_MASK                   (0xFFU)
101875 #define XBARA_SEL17_SEL34_SHIFT                  (0U)
101876 #define XBARA_SEL17_SEL34(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
101877 
101878 #define XBARA_SEL17_SEL35_MASK                   (0xFF00U)
101879 #define XBARA_SEL17_SEL35_SHIFT                  (8U)
101880 #define XBARA_SEL17_SEL35(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
101881 /*! @} */
101882 
101883 /*! @name SEL18 - Crossbar A Select Register 18 */
101884 /*! @{ */
101885 
101886 #define XBARA_SEL18_SEL36_MASK                   (0xFFU)
101887 #define XBARA_SEL18_SEL36_SHIFT                  (0U)
101888 #define XBARA_SEL18_SEL36(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
101889 
101890 #define XBARA_SEL18_SEL37_MASK                   (0xFF00U)
101891 #define XBARA_SEL18_SEL37_SHIFT                  (8U)
101892 #define XBARA_SEL18_SEL37(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
101893 /*! @} */
101894 
101895 /*! @name SEL19 - Crossbar A Select Register 19 */
101896 /*! @{ */
101897 
101898 #define XBARA_SEL19_SEL38_MASK                   (0xFFU)
101899 #define XBARA_SEL19_SEL38_SHIFT                  (0U)
101900 #define XBARA_SEL19_SEL38(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
101901 
101902 #define XBARA_SEL19_SEL39_MASK                   (0xFF00U)
101903 #define XBARA_SEL19_SEL39_SHIFT                  (8U)
101904 #define XBARA_SEL19_SEL39(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
101905 /*! @} */
101906 
101907 /*! @name SEL20 - Crossbar A Select Register 20 */
101908 /*! @{ */
101909 
101910 #define XBARA_SEL20_SEL40_MASK                   (0xFFU)
101911 #define XBARA_SEL20_SEL40_SHIFT                  (0U)
101912 #define XBARA_SEL20_SEL40(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
101913 
101914 #define XBARA_SEL20_SEL41_MASK                   (0xFF00U)
101915 #define XBARA_SEL20_SEL41_SHIFT                  (8U)
101916 #define XBARA_SEL20_SEL41(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
101917 /*! @} */
101918 
101919 /*! @name SEL21 - Crossbar A Select Register 21 */
101920 /*! @{ */
101921 
101922 #define XBARA_SEL21_SEL42_MASK                   (0xFFU)
101923 #define XBARA_SEL21_SEL42_SHIFT                  (0U)
101924 #define XBARA_SEL21_SEL42(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
101925 
101926 #define XBARA_SEL21_SEL43_MASK                   (0xFF00U)
101927 #define XBARA_SEL21_SEL43_SHIFT                  (8U)
101928 #define XBARA_SEL21_SEL43(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
101929 /*! @} */
101930 
101931 /*! @name SEL22 - Crossbar A Select Register 22 */
101932 /*! @{ */
101933 
101934 #define XBARA_SEL22_SEL44_MASK                   (0xFFU)
101935 #define XBARA_SEL22_SEL44_SHIFT                  (0U)
101936 #define XBARA_SEL22_SEL44(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
101937 
101938 #define XBARA_SEL22_SEL45_MASK                   (0xFF00U)
101939 #define XBARA_SEL22_SEL45_SHIFT                  (8U)
101940 #define XBARA_SEL22_SEL45(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
101941 /*! @} */
101942 
101943 /*! @name SEL23 - Crossbar A Select Register 23 */
101944 /*! @{ */
101945 
101946 #define XBARA_SEL23_SEL46_MASK                   (0xFFU)
101947 #define XBARA_SEL23_SEL46_SHIFT                  (0U)
101948 #define XBARA_SEL23_SEL46(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
101949 
101950 #define XBARA_SEL23_SEL47_MASK                   (0xFF00U)
101951 #define XBARA_SEL23_SEL47_SHIFT                  (8U)
101952 #define XBARA_SEL23_SEL47(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
101953 /*! @} */
101954 
101955 /*! @name SEL24 - Crossbar A Select Register 24 */
101956 /*! @{ */
101957 
101958 #define XBARA_SEL24_SEL48_MASK                   (0xFFU)
101959 #define XBARA_SEL24_SEL48_SHIFT                  (0U)
101960 #define XBARA_SEL24_SEL48(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
101961 
101962 #define XBARA_SEL24_SEL49_MASK                   (0xFF00U)
101963 #define XBARA_SEL24_SEL49_SHIFT                  (8U)
101964 #define XBARA_SEL24_SEL49(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
101965 /*! @} */
101966 
101967 /*! @name SEL25 - Crossbar A Select Register 25 */
101968 /*! @{ */
101969 
101970 #define XBARA_SEL25_SEL50_MASK                   (0xFFU)
101971 #define XBARA_SEL25_SEL50_SHIFT                  (0U)
101972 #define XBARA_SEL25_SEL50(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
101973 
101974 #define XBARA_SEL25_SEL51_MASK                   (0xFF00U)
101975 #define XBARA_SEL25_SEL51_SHIFT                  (8U)
101976 #define XBARA_SEL25_SEL51(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
101977 /*! @} */
101978 
101979 /*! @name SEL26 - Crossbar A Select Register 26 */
101980 /*! @{ */
101981 
101982 #define XBARA_SEL26_SEL52_MASK                   (0xFFU)
101983 #define XBARA_SEL26_SEL52_SHIFT                  (0U)
101984 #define XBARA_SEL26_SEL52(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
101985 
101986 #define XBARA_SEL26_SEL53_MASK                   (0xFF00U)
101987 #define XBARA_SEL26_SEL53_SHIFT                  (8U)
101988 #define XBARA_SEL26_SEL53(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
101989 /*! @} */
101990 
101991 /*! @name SEL27 - Crossbar A Select Register 27 */
101992 /*! @{ */
101993 
101994 #define XBARA_SEL27_SEL54_MASK                   (0xFFU)
101995 #define XBARA_SEL27_SEL54_SHIFT                  (0U)
101996 #define XBARA_SEL27_SEL54(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
101997 
101998 #define XBARA_SEL27_SEL55_MASK                   (0xFF00U)
101999 #define XBARA_SEL27_SEL55_SHIFT                  (8U)
102000 #define XBARA_SEL27_SEL55(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
102001 /*! @} */
102002 
102003 /*! @name SEL28 - Crossbar A Select Register 28 */
102004 /*! @{ */
102005 
102006 #define XBARA_SEL28_SEL56_MASK                   (0xFFU)
102007 #define XBARA_SEL28_SEL56_SHIFT                  (0U)
102008 #define XBARA_SEL28_SEL56(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
102009 
102010 #define XBARA_SEL28_SEL57_MASK                   (0xFF00U)
102011 #define XBARA_SEL28_SEL57_SHIFT                  (8U)
102012 #define XBARA_SEL28_SEL57(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
102013 /*! @} */
102014 
102015 /*! @name SEL29 - Crossbar A Select Register 29 */
102016 /*! @{ */
102017 
102018 #define XBARA_SEL29_SEL58_MASK                   (0xFFU)
102019 #define XBARA_SEL29_SEL58_SHIFT                  (0U)
102020 #define XBARA_SEL29_SEL58(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
102021 
102022 #define XBARA_SEL29_SEL59_MASK                   (0xFF00U)
102023 #define XBARA_SEL29_SEL59_SHIFT                  (8U)
102024 #define XBARA_SEL29_SEL59(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
102025 /*! @} */
102026 
102027 /*! @name SEL30 - Crossbar A Select Register 30 */
102028 /*! @{ */
102029 
102030 #define XBARA_SEL30_SEL60_MASK                   (0xFFU)
102031 #define XBARA_SEL30_SEL60_SHIFT                  (0U)
102032 #define XBARA_SEL30_SEL60(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
102033 
102034 #define XBARA_SEL30_SEL61_MASK                   (0xFF00U)
102035 #define XBARA_SEL30_SEL61_SHIFT                  (8U)
102036 #define XBARA_SEL30_SEL61(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
102037 /*! @} */
102038 
102039 /*! @name SEL31 - Crossbar A Select Register 31 */
102040 /*! @{ */
102041 
102042 #define XBARA_SEL31_SEL62_MASK                   (0xFFU)
102043 #define XBARA_SEL31_SEL62_SHIFT                  (0U)
102044 #define XBARA_SEL31_SEL62(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
102045 
102046 #define XBARA_SEL31_SEL63_MASK                   (0xFF00U)
102047 #define XBARA_SEL31_SEL63_SHIFT                  (8U)
102048 #define XBARA_SEL31_SEL63(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
102049 /*! @} */
102050 
102051 /*! @name SEL32 - Crossbar A Select Register 32 */
102052 /*! @{ */
102053 
102054 #define XBARA_SEL32_SEL64_MASK                   (0xFFU)
102055 #define XBARA_SEL32_SEL64_SHIFT                  (0U)
102056 #define XBARA_SEL32_SEL64(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
102057 
102058 #define XBARA_SEL32_SEL65_MASK                   (0xFF00U)
102059 #define XBARA_SEL32_SEL65_SHIFT                  (8U)
102060 #define XBARA_SEL32_SEL65(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
102061 /*! @} */
102062 
102063 /*! @name SEL33 - Crossbar A Select Register 33 */
102064 /*! @{ */
102065 
102066 #define XBARA_SEL33_SEL66_MASK                   (0xFFU)
102067 #define XBARA_SEL33_SEL66_SHIFT                  (0U)
102068 #define XBARA_SEL33_SEL66(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
102069 
102070 #define XBARA_SEL33_SEL67_MASK                   (0xFF00U)
102071 #define XBARA_SEL33_SEL67_SHIFT                  (8U)
102072 #define XBARA_SEL33_SEL67(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
102073 /*! @} */
102074 
102075 /*! @name SEL34 - Crossbar A Select Register 34 */
102076 /*! @{ */
102077 
102078 #define XBARA_SEL34_SEL68_MASK                   (0xFFU)
102079 #define XBARA_SEL34_SEL68_SHIFT                  (0U)
102080 #define XBARA_SEL34_SEL68(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
102081 
102082 #define XBARA_SEL34_SEL69_MASK                   (0xFF00U)
102083 #define XBARA_SEL34_SEL69_SHIFT                  (8U)
102084 #define XBARA_SEL34_SEL69(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
102085 /*! @} */
102086 
102087 /*! @name SEL35 - Crossbar A Select Register 35 */
102088 /*! @{ */
102089 
102090 #define XBARA_SEL35_SEL70_MASK                   (0xFFU)
102091 #define XBARA_SEL35_SEL70_SHIFT                  (0U)
102092 #define XBARA_SEL35_SEL70(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
102093 
102094 #define XBARA_SEL35_SEL71_MASK                   (0xFF00U)
102095 #define XBARA_SEL35_SEL71_SHIFT                  (8U)
102096 #define XBARA_SEL35_SEL71(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
102097 /*! @} */
102098 
102099 /*! @name SEL36 - Crossbar A Select Register 36 */
102100 /*! @{ */
102101 
102102 #define XBARA_SEL36_SEL72_MASK                   (0xFFU)
102103 #define XBARA_SEL36_SEL72_SHIFT                  (0U)
102104 #define XBARA_SEL36_SEL72(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
102105 
102106 #define XBARA_SEL36_SEL73_MASK                   (0xFF00U)
102107 #define XBARA_SEL36_SEL73_SHIFT                  (8U)
102108 #define XBARA_SEL36_SEL73(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
102109 /*! @} */
102110 
102111 /*! @name SEL37 - Crossbar A Select Register 37 */
102112 /*! @{ */
102113 
102114 #define XBARA_SEL37_SEL74_MASK                   (0xFFU)
102115 #define XBARA_SEL37_SEL74_SHIFT                  (0U)
102116 #define XBARA_SEL37_SEL74(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
102117 
102118 #define XBARA_SEL37_SEL75_MASK                   (0xFF00U)
102119 #define XBARA_SEL37_SEL75_SHIFT                  (8U)
102120 #define XBARA_SEL37_SEL75(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
102121 /*! @} */
102122 
102123 /*! @name SEL38 - Crossbar A Select Register 38 */
102124 /*! @{ */
102125 
102126 #define XBARA_SEL38_SEL76_MASK                   (0xFFU)
102127 #define XBARA_SEL38_SEL76_SHIFT                  (0U)
102128 #define XBARA_SEL38_SEL76(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
102129 
102130 #define XBARA_SEL38_SEL77_MASK                   (0xFF00U)
102131 #define XBARA_SEL38_SEL77_SHIFT                  (8U)
102132 #define XBARA_SEL38_SEL77(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
102133 /*! @} */
102134 
102135 /*! @name SEL39 - Crossbar A Select Register 39 */
102136 /*! @{ */
102137 
102138 #define XBARA_SEL39_SEL78_MASK                   (0xFFU)
102139 #define XBARA_SEL39_SEL78_SHIFT                  (0U)
102140 #define XBARA_SEL39_SEL78(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
102141 
102142 #define XBARA_SEL39_SEL79_MASK                   (0xFF00U)
102143 #define XBARA_SEL39_SEL79_SHIFT                  (8U)
102144 #define XBARA_SEL39_SEL79(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
102145 /*! @} */
102146 
102147 /*! @name SEL40 - Crossbar A Select Register 40 */
102148 /*! @{ */
102149 
102150 #define XBARA_SEL40_SEL80_MASK                   (0xFFU)
102151 #define XBARA_SEL40_SEL80_SHIFT                  (0U)
102152 #define XBARA_SEL40_SEL80(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
102153 
102154 #define XBARA_SEL40_SEL81_MASK                   (0xFF00U)
102155 #define XBARA_SEL40_SEL81_SHIFT                  (8U)
102156 #define XBARA_SEL40_SEL81(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
102157 /*! @} */
102158 
102159 /*! @name SEL41 - Crossbar A Select Register 41 */
102160 /*! @{ */
102161 
102162 #define XBARA_SEL41_SEL82_MASK                   (0xFFU)
102163 #define XBARA_SEL41_SEL82_SHIFT                  (0U)
102164 #define XBARA_SEL41_SEL82(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
102165 
102166 #define XBARA_SEL41_SEL83_MASK                   (0xFF00U)
102167 #define XBARA_SEL41_SEL83_SHIFT                  (8U)
102168 #define XBARA_SEL41_SEL83(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
102169 /*! @} */
102170 
102171 /*! @name SEL42 - Crossbar A Select Register 42 */
102172 /*! @{ */
102173 
102174 #define XBARA_SEL42_SEL84_MASK                   (0xFFU)
102175 #define XBARA_SEL42_SEL84_SHIFT                  (0U)
102176 #define XBARA_SEL42_SEL84(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
102177 
102178 #define XBARA_SEL42_SEL85_MASK                   (0xFF00U)
102179 #define XBARA_SEL42_SEL85_SHIFT                  (8U)
102180 #define XBARA_SEL42_SEL85(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
102181 /*! @} */
102182 
102183 /*! @name SEL43 - Crossbar A Select Register 43 */
102184 /*! @{ */
102185 
102186 #define XBARA_SEL43_SEL86_MASK                   (0xFFU)
102187 #define XBARA_SEL43_SEL86_SHIFT                  (0U)
102188 #define XBARA_SEL43_SEL86(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
102189 
102190 #define XBARA_SEL43_SEL87_MASK                   (0xFF00U)
102191 #define XBARA_SEL43_SEL87_SHIFT                  (8U)
102192 #define XBARA_SEL43_SEL87(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
102193 /*! @} */
102194 
102195 /*! @name SEL44 - Crossbar A Select Register 44 */
102196 /*! @{ */
102197 
102198 #define XBARA_SEL44_SEL88_MASK                   (0xFFU)
102199 #define XBARA_SEL44_SEL88_SHIFT                  (0U)
102200 #define XBARA_SEL44_SEL88(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
102201 
102202 #define XBARA_SEL44_SEL89_MASK                   (0xFF00U)
102203 #define XBARA_SEL44_SEL89_SHIFT                  (8U)
102204 #define XBARA_SEL44_SEL89(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
102205 /*! @} */
102206 
102207 /*! @name SEL45 - Crossbar A Select Register 45 */
102208 /*! @{ */
102209 
102210 #define XBARA_SEL45_SEL90_MASK                   (0xFFU)
102211 #define XBARA_SEL45_SEL90_SHIFT                  (0U)
102212 #define XBARA_SEL45_SEL90(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
102213 
102214 #define XBARA_SEL45_SEL91_MASK                   (0xFF00U)
102215 #define XBARA_SEL45_SEL91_SHIFT                  (8U)
102216 #define XBARA_SEL45_SEL91(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
102217 /*! @} */
102218 
102219 /*! @name SEL46 - Crossbar A Select Register 46 */
102220 /*! @{ */
102221 
102222 #define XBARA_SEL46_SEL92_MASK                   (0xFFU)
102223 #define XBARA_SEL46_SEL92_SHIFT                  (0U)
102224 #define XBARA_SEL46_SEL92(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
102225 
102226 #define XBARA_SEL46_SEL93_MASK                   (0xFF00U)
102227 #define XBARA_SEL46_SEL93_SHIFT                  (8U)
102228 #define XBARA_SEL46_SEL93(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
102229 /*! @} */
102230 
102231 /*! @name SEL47 - Crossbar A Select Register 47 */
102232 /*! @{ */
102233 
102234 #define XBARA_SEL47_SEL94_MASK                   (0xFFU)
102235 #define XBARA_SEL47_SEL94_SHIFT                  (0U)
102236 #define XBARA_SEL47_SEL94(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
102237 
102238 #define XBARA_SEL47_SEL95_MASK                   (0xFF00U)
102239 #define XBARA_SEL47_SEL95_SHIFT                  (8U)
102240 #define XBARA_SEL47_SEL95(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
102241 /*! @} */
102242 
102243 /*! @name SEL48 - Crossbar A Select Register 48 */
102244 /*! @{ */
102245 
102246 #define XBARA_SEL48_SEL96_MASK                   (0xFFU)
102247 #define XBARA_SEL48_SEL96_SHIFT                  (0U)
102248 #define XBARA_SEL48_SEL96(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
102249 
102250 #define XBARA_SEL48_SEL97_MASK                   (0xFF00U)
102251 #define XBARA_SEL48_SEL97_SHIFT                  (8U)
102252 #define XBARA_SEL48_SEL97(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
102253 /*! @} */
102254 
102255 /*! @name SEL49 - Crossbar A Select Register 49 */
102256 /*! @{ */
102257 
102258 #define XBARA_SEL49_SEL98_MASK                   (0xFFU)
102259 #define XBARA_SEL49_SEL98_SHIFT                  (0U)
102260 #define XBARA_SEL49_SEL98(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
102261 
102262 #define XBARA_SEL49_SEL99_MASK                   (0xFF00U)
102263 #define XBARA_SEL49_SEL99_SHIFT                  (8U)
102264 #define XBARA_SEL49_SEL99(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
102265 /*! @} */
102266 
102267 /*! @name SEL50 - Crossbar A Select Register 50 */
102268 /*! @{ */
102269 
102270 #define XBARA_SEL50_SEL100_MASK                  (0xFFU)
102271 #define XBARA_SEL50_SEL100_SHIFT                 (0U)
102272 #define XBARA_SEL50_SEL100(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
102273 
102274 #define XBARA_SEL50_SEL101_MASK                  (0xFF00U)
102275 #define XBARA_SEL50_SEL101_SHIFT                 (8U)
102276 #define XBARA_SEL50_SEL101(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
102277 /*! @} */
102278 
102279 /*! @name SEL51 - Crossbar A Select Register 51 */
102280 /*! @{ */
102281 
102282 #define XBARA_SEL51_SEL102_MASK                  (0xFFU)
102283 #define XBARA_SEL51_SEL102_SHIFT                 (0U)
102284 #define XBARA_SEL51_SEL102(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
102285 
102286 #define XBARA_SEL51_SEL103_MASK                  (0xFF00U)
102287 #define XBARA_SEL51_SEL103_SHIFT                 (8U)
102288 #define XBARA_SEL51_SEL103(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
102289 /*! @} */
102290 
102291 /*! @name SEL52 - Crossbar A Select Register 52 */
102292 /*! @{ */
102293 
102294 #define XBARA_SEL52_SEL104_MASK                  (0xFFU)
102295 #define XBARA_SEL52_SEL104_SHIFT                 (0U)
102296 #define XBARA_SEL52_SEL104(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
102297 
102298 #define XBARA_SEL52_SEL105_MASK                  (0xFF00U)
102299 #define XBARA_SEL52_SEL105_SHIFT                 (8U)
102300 #define XBARA_SEL52_SEL105(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
102301 /*! @} */
102302 
102303 /*! @name SEL53 - Crossbar A Select Register 53 */
102304 /*! @{ */
102305 
102306 #define XBARA_SEL53_SEL106_MASK                  (0xFFU)
102307 #define XBARA_SEL53_SEL106_SHIFT                 (0U)
102308 #define XBARA_SEL53_SEL106(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
102309 
102310 #define XBARA_SEL53_SEL107_MASK                  (0xFF00U)
102311 #define XBARA_SEL53_SEL107_SHIFT                 (8U)
102312 #define XBARA_SEL53_SEL107(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
102313 /*! @} */
102314 
102315 /*! @name SEL54 - Crossbar A Select Register 54 */
102316 /*! @{ */
102317 
102318 #define XBARA_SEL54_SEL108_MASK                  (0xFFU)
102319 #define XBARA_SEL54_SEL108_SHIFT                 (0U)
102320 #define XBARA_SEL54_SEL108(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
102321 
102322 #define XBARA_SEL54_SEL109_MASK                  (0xFF00U)
102323 #define XBARA_SEL54_SEL109_SHIFT                 (8U)
102324 #define XBARA_SEL54_SEL109(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
102325 /*! @} */
102326 
102327 /*! @name SEL55 - Crossbar A Select Register 55 */
102328 /*! @{ */
102329 
102330 #define XBARA_SEL55_SEL110_MASK                  (0xFFU)
102331 #define XBARA_SEL55_SEL110_SHIFT                 (0U)
102332 #define XBARA_SEL55_SEL110(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
102333 
102334 #define XBARA_SEL55_SEL111_MASK                  (0xFF00U)
102335 #define XBARA_SEL55_SEL111_SHIFT                 (8U)
102336 #define XBARA_SEL55_SEL111(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
102337 /*! @} */
102338 
102339 /*! @name SEL56 - Crossbar A Select Register 56 */
102340 /*! @{ */
102341 
102342 #define XBARA_SEL56_SEL112_MASK                  (0xFFU)
102343 #define XBARA_SEL56_SEL112_SHIFT                 (0U)
102344 #define XBARA_SEL56_SEL112(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
102345 
102346 #define XBARA_SEL56_SEL113_MASK                  (0xFF00U)
102347 #define XBARA_SEL56_SEL113_SHIFT                 (8U)
102348 #define XBARA_SEL56_SEL113(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
102349 /*! @} */
102350 
102351 /*! @name SEL57 - Crossbar A Select Register 57 */
102352 /*! @{ */
102353 
102354 #define XBARA_SEL57_SEL114_MASK                  (0xFFU)
102355 #define XBARA_SEL57_SEL114_SHIFT                 (0U)
102356 #define XBARA_SEL57_SEL114(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
102357 
102358 #define XBARA_SEL57_SEL115_MASK                  (0xFF00U)
102359 #define XBARA_SEL57_SEL115_SHIFT                 (8U)
102360 #define XBARA_SEL57_SEL115(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
102361 /*! @} */
102362 
102363 /*! @name SEL58 - Crossbar A Select Register 58 */
102364 /*! @{ */
102365 
102366 #define XBARA_SEL58_SEL116_MASK                  (0xFFU)
102367 #define XBARA_SEL58_SEL116_SHIFT                 (0U)
102368 #define XBARA_SEL58_SEL116(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
102369 
102370 #define XBARA_SEL58_SEL117_MASK                  (0xFF00U)
102371 #define XBARA_SEL58_SEL117_SHIFT                 (8U)
102372 #define XBARA_SEL58_SEL117(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
102373 /*! @} */
102374 
102375 /*! @name SEL59 - Crossbar A Select Register 59 */
102376 /*! @{ */
102377 
102378 #define XBARA_SEL59_SEL118_MASK                  (0xFFU)
102379 #define XBARA_SEL59_SEL118_SHIFT                 (0U)
102380 #define XBARA_SEL59_SEL118(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
102381 
102382 #define XBARA_SEL59_SEL119_MASK                  (0xFF00U)
102383 #define XBARA_SEL59_SEL119_SHIFT                 (8U)
102384 #define XBARA_SEL59_SEL119(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
102385 /*! @} */
102386 
102387 /*! @name SEL60 - Crossbar A Select Register 60 */
102388 /*! @{ */
102389 
102390 #define XBARA_SEL60_SEL120_MASK                  (0xFFU)
102391 #define XBARA_SEL60_SEL120_SHIFT                 (0U)
102392 #define XBARA_SEL60_SEL120(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
102393 
102394 #define XBARA_SEL60_SEL121_MASK                  (0xFF00U)
102395 #define XBARA_SEL60_SEL121_SHIFT                 (8U)
102396 #define XBARA_SEL60_SEL121(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
102397 /*! @} */
102398 
102399 /*! @name SEL61 - Crossbar A Select Register 61 */
102400 /*! @{ */
102401 
102402 #define XBARA_SEL61_SEL122_MASK                  (0xFFU)
102403 #define XBARA_SEL61_SEL122_SHIFT                 (0U)
102404 #define XBARA_SEL61_SEL122(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
102405 
102406 #define XBARA_SEL61_SEL123_MASK                  (0xFF00U)
102407 #define XBARA_SEL61_SEL123_SHIFT                 (8U)
102408 #define XBARA_SEL61_SEL123(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
102409 /*! @} */
102410 
102411 /*! @name SEL62 - Crossbar A Select Register 62 */
102412 /*! @{ */
102413 
102414 #define XBARA_SEL62_SEL124_MASK                  (0xFFU)
102415 #define XBARA_SEL62_SEL124_SHIFT                 (0U)
102416 #define XBARA_SEL62_SEL124(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
102417 
102418 #define XBARA_SEL62_SEL125_MASK                  (0xFF00U)
102419 #define XBARA_SEL62_SEL125_SHIFT                 (8U)
102420 #define XBARA_SEL62_SEL125(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
102421 /*! @} */
102422 
102423 /*! @name SEL63 - Crossbar A Select Register 63 */
102424 /*! @{ */
102425 
102426 #define XBARA_SEL63_SEL126_MASK                  (0xFFU)
102427 #define XBARA_SEL63_SEL126_SHIFT                 (0U)
102428 #define XBARA_SEL63_SEL126(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
102429 
102430 #define XBARA_SEL63_SEL127_MASK                  (0xFF00U)
102431 #define XBARA_SEL63_SEL127_SHIFT                 (8U)
102432 #define XBARA_SEL63_SEL127(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
102433 /*! @} */
102434 
102435 /*! @name SEL64 - Crossbar A Select Register 64 */
102436 /*! @{ */
102437 
102438 #define XBARA_SEL64_SEL128_MASK                  (0xFFU)
102439 #define XBARA_SEL64_SEL128_SHIFT                 (0U)
102440 #define XBARA_SEL64_SEL128(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
102441 
102442 #define XBARA_SEL64_SEL129_MASK                  (0xFF00U)
102443 #define XBARA_SEL64_SEL129_SHIFT                 (8U)
102444 #define XBARA_SEL64_SEL129(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
102445 /*! @} */
102446 
102447 /*! @name SEL65 - Crossbar A Select Register 65 */
102448 /*! @{ */
102449 
102450 #define XBARA_SEL65_SEL130_MASK                  (0xFFU)
102451 #define XBARA_SEL65_SEL130_SHIFT                 (0U)
102452 #define XBARA_SEL65_SEL130(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
102453 
102454 #define XBARA_SEL65_SEL131_MASK                  (0xFF00U)
102455 #define XBARA_SEL65_SEL131_SHIFT                 (8U)
102456 #define XBARA_SEL65_SEL131(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
102457 /*! @} */
102458 
102459 /*! @name SEL66 - Crossbar A Select Register 66 */
102460 /*! @{ */
102461 
102462 #define XBARA_SEL66_SEL132_MASK                  (0xFFU)
102463 #define XBARA_SEL66_SEL132_SHIFT                 (0U)
102464 #define XBARA_SEL66_SEL132(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)
102465 
102466 #define XBARA_SEL66_SEL133_MASK                  (0xFF00U)
102467 #define XBARA_SEL66_SEL133_SHIFT                 (8U)
102468 #define XBARA_SEL66_SEL133(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)
102469 /*! @} */
102470 
102471 /*! @name SEL67 - Crossbar A Select Register 67 */
102472 /*! @{ */
102473 
102474 #define XBARA_SEL67_SEL134_MASK                  (0xFFU)
102475 #define XBARA_SEL67_SEL134_SHIFT                 (0U)
102476 #define XBARA_SEL67_SEL134(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)
102477 
102478 #define XBARA_SEL67_SEL135_MASK                  (0xFF00U)
102479 #define XBARA_SEL67_SEL135_SHIFT                 (8U)
102480 #define XBARA_SEL67_SEL135(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)
102481 /*! @} */
102482 
102483 /*! @name SEL68 - Crossbar A Select Register 68 */
102484 /*! @{ */
102485 
102486 #define XBARA_SEL68_SEL136_MASK                  (0xFFU)
102487 #define XBARA_SEL68_SEL136_SHIFT                 (0U)
102488 #define XBARA_SEL68_SEL136(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)
102489 
102490 #define XBARA_SEL68_SEL137_MASK                  (0xFF00U)
102491 #define XBARA_SEL68_SEL137_SHIFT                 (8U)
102492 #define XBARA_SEL68_SEL137(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)
102493 /*! @} */
102494 
102495 /*! @name SEL69 - Crossbar A Select Register 69 */
102496 /*! @{ */
102497 
102498 #define XBARA_SEL69_SEL138_MASK                  (0xFFU)
102499 #define XBARA_SEL69_SEL138_SHIFT                 (0U)
102500 #define XBARA_SEL69_SEL138(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)
102501 
102502 #define XBARA_SEL69_SEL139_MASK                  (0xFF00U)
102503 #define XBARA_SEL69_SEL139_SHIFT                 (8U)
102504 #define XBARA_SEL69_SEL139(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)
102505 /*! @} */
102506 
102507 /*! @name SEL70 - Crossbar A Select Register 70 */
102508 /*! @{ */
102509 
102510 #define XBARA_SEL70_SEL140_MASK                  (0xFFU)
102511 #define XBARA_SEL70_SEL140_SHIFT                 (0U)
102512 #define XBARA_SEL70_SEL140(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)
102513 
102514 #define XBARA_SEL70_SEL141_MASK                  (0xFF00U)
102515 #define XBARA_SEL70_SEL141_SHIFT                 (8U)
102516 #define XBARA_SEL70_SEL141(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)
102517 /*! @} */
102518 
102519 /*! @name SEL71 - Crossbar A Select Register 71 */
102520 /*! @{ */
102521 
102522 #define XBARA_SEL71_SEL142_MASK                  (0xFFU)
102523 #define XBARA_SEL71_SEL142_SHIFT                 (0U)
102524 #define XBARA_SEL71_SEL142(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)
102525 
102526 #define XBARA_SEL71_SEL143_MASK                  (0xFF00U)
102527 #define XBARA_SEL71_SEL143_SHIFT                 (8U)
102528 #define XBARA_SEL71_SEL143(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)
102529 /*! @} */
102530 
102531 /*! @name SEL72 - Crossbar A Select Register 72 */
102532 /*! @{ */
102533 
102534 #define XBARA_SEL72_SEL144_MASK                  (0xFFU)
102535 #define XBARA_SEL72_SEL144_SHIFT                 (0U)
102536 #define XBARA_SEL72_SEL144(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)
102537 
102538 #define XBARA_SEL72_SEL145_MASK                  (0xFF00U)
102539 #define XBARA_SEL72_SEL145_SHIFT                 (8U)
102540 #define XBARA_SEL72_SEL145(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)
102541 /*! @} */
102542 
102543 /*! @name SEL73 - Crossbar A Select Register 73 */
102544 /*! @{ */
102545 
102546 #define XBARA_SEL73_SEL146_MASK                  (0xFFU)
102547 #define XBARA_SEL73_SEL146_SHIFT                 (0U)
102548 #define XBARA_SEL73_SEL146(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)
102549 
102550 #define XBARA_SEL73_SEL147_MASK                  (0xFF00U)
102551 #define XBARA_SEL73_SEL147_SHIFT                 (8U)
102552 #define XBARA_SEL73_SEL147(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)
102553 /*! @} */
102554 
102555 /*! @name SEL74 - Crossbar A Select Register 74 */
102556 /*! @{ */
102557 
102558 #define XBARA_SEL74_SEL148_MASK                  (0xFFU)
102559 #define XBARA_SEL74_SEL148_SHIFT                 (0U)
102560 #define XBARA_SEL74_SEL148(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)
102561 
102562 #define XBARA_SEL74_SEL149_MASK                  (0xFF00U)
102563 #define XBARA_SEL74_SEL149_SHIFT                 (8U)
102564 #define XBARA_SEL74_SEL149(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)
102565 /*! @} */
102566 
102567 /*! @name SEL75 - Crossbar A Select Register 75 */
102568 /*! @{ */
102569 
102570 #define XBARA_SEL75_SEL150_MASK                  (0xFFU)
102571 #define XBARA_SEL75_SEL150_SHIFT                 (0U)
102572 #define XBARA_SEL75_SEL150(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)
102573 
102574 #define XBARA_SEL75_SEL151_MASK                  (0xFF00U)
102575 #define XBARA_SEL75_SEL151_SHIFT                 (8U)
102576 #define XBARA_SEL75_SEL151(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)
102577 /*! @} */
102578 
102579 /*! @name SEL76 - Crossbar A Select Register 76 */
102580 /*! @{ */
102581 
102582 #define XBARA_SEL76_SEL152_MASK                  (0xFFU)
102583 #define XBARA_SEL76_SEL152_SHIFT                 (0U)
102584 #define XBARA_SEL76_SEL152(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)
102585 
102586 #define XBARA_SEL76_SEL153_MASK                  (0xFF00U)
102587 #define XBARA_SEL76_SEL153_SHIFT                 (8U)
102588 #define XBARA_SEL76_SEL153(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)
102589 /*! @} */
102590 
102591 /*! @name SEL77 - Crossbar A Select Register 77 */
102592 /*! @{ */
102593 
102594 #define XBARA_SEL77_SEL154_MASK                  (0xFFU)
102595 #define XBARA_SEL77_SEL154_SHIFT                 (0U)
102596 #define XBARA_SEL77_SEL154(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)
102597 
102598 #define XBARA_SEL77_SEL155_MASK                  (0xFF00U)
102599 #define XBARA_SEL77_SEL155_SHIFT                 (8U)
102600 #define XBARA_SEL77_SEL155(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)
102601 /*! @} */
102602 
102603 /*! @name SEL78 - Crossbar A Select Register 78 */
102604 /*! @{ */
102605 
102606 #define XBARA_SEL78_SEL156_MASK                  (0xFFU)
102607 #define XBARA_SEL78_SEL156_SHIFT                 (0U)
102608 #define XBARA_SEL78_SEL156(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)
102609 
102610 #define XBARA_SEL78_SEL157_MASK                  (0xFF00U)
102611 #define XBARA_SEL78_SEL157_SHIFT                 (8U)
102612 #define XBARA_SEL78_SEL157(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)
102613 /*! @} */
102614 
102615 /*! @name SEL79 - Crossbar A Select Register 79 */
102616 /*! @{ */
102617 
102618 #define XBARA_SEL79_SEL158_MASK                  (0xFFU)
102619 #define XBARA_SEL79_SEL158_SHIFT                 (0U)
102620 #define XBARA_SEL79_SEL158(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)
102621 
102622 #define XBARA_SEL79_SEL159_MASK                  (0xFF00U)
102623 #define XBARA_SEL79_SEL159_SHIFT                 (8U)
102624 #define XBARA_SEL79_SEL159(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)
102625 /*! @} */
102626 
102627 /*! @name SEL80 - Crossbar A Select Register 80 */
102628 /*! @{ */
102629 
102630 #define XBARA_SEL80_SEL160_MASK                  (0xFFU)
102631 #define XBARA_SEL80_SEL160_SHIFT                 (0U)
102632 #define XBARA_SEL80_SEL160(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)
102633 
102634 #define XBARA_SEL80_SEL161_MASK                  (0xFF00U)
102635 #define XBARA_SEL80_SEL161_SHIFT                 (8U)
102636 #define XBARA_SEL80_SEL161(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)
102637 /*! @} */
102638 
102639 /*! @name SEL81 - Crossbar A Select Register 81 */
102640 /*! @{ */
102641 
102642 #define XBARA_SEL81_SEL162_MASK                  (0xFFU)
102643 #define XBARA_SEL81_SEL162_SHIFT                 (0U)
102644 #define XBARA_SEL81_SEL162(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)
102645 
102646 #define XBARA_SEL81_SEL163_MASK                  (0xFF00U)
102647 #define XBARA_SEL81_SEL163_SHIFT                 (8U)
102648 #define XBARA_SEL81_SEL163(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)
102649 /*! @} */
102650 
102651 /*! @name SEL82 - Crossbar A Select Register 82 */
102652 /*! @{ */
102653 
102654 #define XBARA_SEL82_SEL164_MASK                  (0xFFU)
102655 #define XBARA_SEL82_SEL164_SHIFT                 (0U)
102656 #define XBARA_SEL82_SEL164(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)
102657 
102658 #define XBARA_SEL82_SEL165_MASK                  (0xFF00U)
102659 #define XBARA_SEL82_SEL165_SHIFT                 (8U)
102660 #define XBARA_SEL82_SEL165(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)
102661 /*! @} */
102662 
102663 /*! @name SEL83 - Crossbar A Select Register 83 */
102664 /*! @{ */
102665 
102666 #define XBARA_SEL83_SEL166_MASK                  (0xFFU)
102667 #define XBARA_SEL83_SEL166_SHIFT                 (0U)
102668 #define XBARA_SEL83_SEL166(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)
102669 
102670 #define XBARA_SEL83_SEL167_MASK                  (0xFF00U)
102671 #define XBARA_SEL83_SEL167_SHIFT                 (8U)
102672 #define XBARA_SEL83_SEL167(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)
102673 /*! @} */
102674 
102675 /*! @name SEL84 - Crossbar A Select Register 84 */
102676 /*! @{ */
102677 
102678 #define XBARA_SEL84_SEL168_MASK                  (0xFFU)
102679 #define XBARA_SEL84_SEL168_SHIFT                 (0U)
102680 #define XBARA_SEL84_SEL168(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)
102681 
102682 #define XBARA_SEL84_SEL169_MASK                  (0xFF00U)
102683 #define XBARA_SEL84_SEL169_SHIFT                 (8U)
102684 #define XBARA_SEL84_SEL169(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)
102685 /*! @} */
102686 
102687 /*! @name SEL85 - Crossbar A Select Register 85 */
102688 /*! @{ */
102689 
102690 #define XBARA_SEL85_SEL170_MASK                  (0xFFU)
102691 #define XBARA_SEL85_SEL170_SHIFT                 (0U)
102692 #define XBARA_SEL85_SEL170(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)
102693 
102694 #define XBARA_SEL85_SEL171_MASK                  (0xFF00U)
102695 #define XBARA_SEL85_SEL171_SHIFT                 (8U)
102696 #define XBARA_SEL85_SEL171(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)
102697 /*! @} */
102698 
102699 /*! @name SEL86 - Crossbar A Select Register 86 */
102700 /*! @{ */
102701 
102702 #define XBARA_SEL86_SEL172_MASK                  (0xFFU)
102703 #define XBARA_SEL86_SEL172_SHIFT                 (0U)
102704 #define XBARA_SEL86_SEL172(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)
102705 
102706 #define XBARA_SEL86_SEL173_MASK                  (0xFF00U)
102707 #define XBARA_SEL86_SEL173_SHIFT                 (8U)
102708 #define XBARA_SEL86_SEL173(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)
102709 /*! @} */
102710 
102711 /*! @name SEL87 - Crossbar A Select Register 87 */
102712 /*! @{ */
102713 
102714 #define XBARA_SEL87_SEL174_MASK                  (0xFFU)
102715 #define XBARA_SEL87_SEL174_SHIFT                 (0U)
102716 #define XBARA_SEL87_SEL174(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)
102717 
102718 #define XBARA_SEL87_SEL175_MASK                  (0xFF00U)
102719 #define XBARA_SEL87_SEL175_SHIFT                 (8U)
102720 #define XBARA_SEL87_SEL175(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)
102721 /*! @} */
102722 
102723 /*! @name CTRL0 - Crossbar A Control Register 0 */
102724 /*! @{ */
102725 
102726 #define XBARA_CTRL0_DEN0_MASK                    (0x1U)
102727 #define XBARA_CTRL0_DEN0_SHIFT                   (0U)
102728 /*! DEN0 - DMA Enable for XBAR_OUT0
102729  *  0b0..DMA disabled
102730  *  0b1..DMA enabled
102731  */
102732 #define XBARA_CTRL0_DEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
102733 
102734 #define XBARA_CTRL0_IEN0_MASK                    (0x2U)
102735 #define XBARA_CTRL0_IEN0_SHIFT                   (1U)
102736 /*! IEN0 - Interrupt Enable for XBAR_OUT0
102737  *  0b0..Interrupt disabled
102738  *  0b1..Interrupt enabled
102739  */
102740 #define XBARA_CTRL0_IEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
102741 
102742 #define XBARA_CTRL0_EDGE0_MASK                   (0xCU)
102743 #define XBARA_CTRL0_EDGE0_SHIFT                  (2U)
102744 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0
102745  *  0b00..STS0 never asserts
102746  *  0b01..STS0 asserts on rising edges of XBAR_OUT0
102747  *  0b10..STS0 asserts on falling edges of XBAR_OUT0
102748  *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
102749  */
102750 #define XBARA_CTRL0_EDGE0(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
102751 
102752 #define XBARA_CTRL0_STS0_MASK                    (0x10U)
102753 #define XBARA_CTRL0_STS0_SHIFT                   (4U)
102754 /*! STS0 - Edge detection status for XBAR_OUT0
102755  *  0b0..Active edge not yet detected on XBAR_OUT0
102756  *  0b1..Active edge detected on XBAR_OUT0
102757  */
102758 #define XBARA_CTRL0_STS0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
102759 
102760 #define XBARA_CTRL0_DEN1_MASK                    (0x100U)
102761 #define XBARA_CTRL0_DEN1_SHIFT                   (8U)
102762 /*! DEN1 - DMA Enable for XBAR_OUT1
102763  *  0b0..DMA disabled
102764  *  0b1..DMA enabled
102765  */
102766 #define XBARA_CTRL0_DEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
102767 
102768 #define XBARA_CTRL0_IEN1_MASK                    (0x200U)
102769 #define XBARA_CTRL0_IEN1_SHIFT                   (9U)
102770 /*! IEN1 - Interrupt Enable for XBAR_OUT1
102771  *  0b0..Interrupt disabled
102772  *  0b1..Interrupt enabled
102773  */
102774 #define XBARA_CTRL0_IEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
102775 
102776 #define XBARA_CTRL0_EDGE1_MASK                   (0xC00U)
102777 #define XBARA_CTRL0_EDGE1_SHIFT                  (10U)
102778 /*! EDGE1 - Active edge for edge detection on XBAR_OUT1
102779  *  0b00..STS1 never asserts
102780  *  0b01..STS1 asserts on rising edges of XBAR_OUT1
102781  *  0b10..STS1 asserts on falling edges of XBAR_OUT1
102782  *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
102783  */
102784 #define XBARA_CTRL0_EDGE1(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
102785 
102786 #define XBARA_CTRL0_STS1_MASK                    (0x1000U)
102787 #define XBARA_CTRL0_STS1_SHIFT                   (12U)
102788 /*! STS1 - Edge detection status for XBAR_OUT1
102789  *  0b0..Active edge not yet detected on XBAR_OUT1
102790  *  0b1..Active edge detected on XBAR_OUT1
102791  */
102792 #define XBARA_CTRL0_STS1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
102793 /*! @} */
102794 
102795 /*! @name CTRL1 - Crossbar A Control Register 1 */
102796 /*! @{ */
102797 
102798 #define XBARA_CTRL1_DEN2_MASK                    (0x1U)
102799 #define XBARA_CTRL1_DEN2_SHIFT                   (0U)
102800 /*! DEN2 - DMA Enable for XBAR_OUT2
102801  *  0b0..DMA disabled
102802  *  0b1..DMA enabled
102803  */
102804 #define XBARA_CTRL1_DEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
102805 
102806 #define XBARA_CTRL1_IEN2_MASK                    (0x2U)
102807 #define XBARA_CTRL1_IEN2_SHIFT                   (1U)
102808 /*! IEN2 - Interrupt Enable for XBAR_OUT2
102809  *  0b0..Interrupt disabled
102810  *  0b1..Interrupt enabled
102811  */
102812 #define XBARA_CTRL1_IEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
102813 
102814 #define XBARA_CTRL1_EDGE2_MASK                   (0xCU)
102815 #define XBARA_CTRL1_EDGE2_SHIFT                  (2U)
102816 /*! EDGE2 - Active edge for edge detection on XBAR_OUT2
102817  *  0b00..STS2 never asserts
102818  *  0b01..STS2 asserts on rising edges of XBAR_OUT2
102819  *  0b10..STS2 asserts on falling edges of XBAR_OUT2
102820  *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
102821  */
102822 #define XBARA_CTRL1_EDGE2(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
102823 
102824 #define XBARA_CTRL1_STS2_MASK                    (0x10U)
102825 #define XBARA_CTRL1_STS2_SHIFT                   (4U)
102826 /*! STS2 - Edge detection status for XBAR_OUT2
102827  *  0b0..Active edge not yet detected on XBAR_OUT2
102828  *  0b1..Active edge detected on XBAR_OUT2
102829  */
102830 #define XBARA_CTRL1_STS2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
102831 
102832 #define XBARA_CTRL1_DEN3_MASK                    (0x100U)
102833 #define XBARA_CTRL1_DEN3_SHIFT                   (8U)
102834 /*! DEN3 - DMA Enable for XBAR_OUT3
102835  *  0b0..DMA disabled
102836  *  0b1..DMA enabled
102837  */
102838 #define XBARA_CTRL1_DEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
102839 
102840 #define XBARA_CTRL1_IEN3_MASK                    (0x200U)
102841 #define XBARA_CTRL1_IEN3_SHIFT                   (9U)
102842 /*! IEN3 - Interrupt Enable for XBAR_OUT3
102843  *  0b0..Interrupt disabled
102844  *  0b1..Interrupt enabled
102845  */
102846 #define XBARA_CTRL1_IEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
102847 
102848 #define XBARA_CTRL1_EDGE3_MASK                   (0xC00U)
102849 #define XBARA_CTRL1_EDGE3_SHIFT                  (10U)
102850 /*! EDGE3 - Active edge for edge detection on XBAR_OUT3
102851  *  0b00..STS3 never asserts
102852  *  0b01..STS3 asserts on rising edges of XBAR_OUT3
102853  *  0b10..STS3 asserts on falling edges of XBAR_OUT3
102854  *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
102855  */
102856 #define XBARA_CTRL1_EDGE3(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
102857 
102858 #define XBARA_CTRL1_STS3_MASK                    (0x1000U)
102859 #define XBARA_CTRL1_STS3_SHIFT                   (12U)
102860 /*! STS3 - Edge detection status for XBAR_OUT3
102861  *  0b0..Active edge not yet detected on XBAR_OUT3
102862  *  0b1..Active edge detected on XBAR_OUT3
102863  */
102864 #define XBARA_CTRL1_STS3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
102865 /*! @} */
102866 
102867 
102868 /*!
102869  * @}
102870  */ /* end of group XBARA_Register_Masks */
102871 
102872 
102873 /* XBARA - Peripheral instance base addresses */
102874 /** Peripheral XBARA1 base address */
102875 #define XBARA1_BASE                              (0x4003C000u)
102876 /** Peripheral XBARA1 base pointer */
102877 #define XBARA1                                   ((XBARA_Type *)XBARA1_BASE)
102878 /** Array initializer of XBARA peripheral base addresses */
102879 #define XBARA_BASE_ADDRS                         { 0u, XBARA1_BASE }
102880 /** Array initializer of XBARA peripheral base pointers */
102881 #define XBARA_BASE_PTRS                          { (XBARA_Type *)0u, XBARA1 }
102882 
102883 /*!
102884  * @}
102885  */ /* end of group XBARA_Peripheral_Access_Layer */
102886 
102887 
102888 /* ----------------------------------------------------------------------------
102889    -- XBARB Peripheral Access Layer
102890    ---------------------------------------------------------------------------- */
102891 
102892 /*!
102893  * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
102894  * @{
102895  */
102896 
102897 /** XBARB - Register Layout Typedef */
102898 typedef struct {
102899   __IO uint16_t SEL0;                              /**< Crossbar B Select Register 0, offset: 0x0 */
102900   __IO uint16_t SEL1;                              /**< Crossbar B Select Register 1, offset: 0x2 */
102901   __IO uint16_t SEL2;                              /**< Crossbar B Select Register 2, offset: 0x4 */
102902   __IO uint16_t SEL3;                              /**< Crossbar B Select Register 3, offset: 0x6 */
102903   __IO uint16_t SEL4;                              /**< Crossbar B Select Register 4, offset: 0x8 */
102904   __IO uint16_t SEL5;                              /**< Crossbar B Select Register 5, offset: 0xA */
102905   __IO uint16_t SEL6;                              /**< Crossbar B Select Register 6, offset: 0xC */
102906   __IO uint16_t SEL7;                              /**< Crossbar B Select Register 7, offset: 0xE */
102907 } XBARB_Type;
102908 
102909 /* ----------------------------------------------------------------------------
102910    -- XBARB Register Masks
102911    ---------------------------------------------------------------------------- */
102912 
102913 /*!
102914  * @addtogroup XBARB_Register_Masks XBARB Register Masks
102915  * @{
102916  */
102917 
102918 /*! @name SEL0 - Crossbar B Select Register 0 */
102919 /*! @{ */
102920 
102921 #define XBARB_SEL0_SEL0_MASK                     (0x7FU)
102922 #define XBARB_SEL0_SEL0_SHIFT                    (0U)
102923 #define XBARB_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
102924 
102925 #define XBARB_SEL0_SEL1_MASK                     (0x7F00U)
102926 #define XBARB_SEL0_SEL1_SHIFT                    (8U)
102927 #define XBARB_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
102928 /*! @} */
102929 
102930 /*! @name SEL1 - Crossbar B Select Register 1 */
102931 /*! @{ */
102932 
102933 #define XBARB_SEL1_SEL2_MASK                     (0x7FU)
102934 #define XBARB_SEL1_SEL2_SHIFT                    (0U)
102935 #define XBARB_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
102936 
102937 #define XBARB_SEL1_SEL3_MASK                     (0x7F00U)
102938 #define XBARB_SEL1_SEL3_SHIFT                    (8U)
102939 #define XBARB_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
102940 /*! @} */
102941 
102942 /*! @name SEL2 - Crossbar B Select Register 2 */
102943 /*! @{ */
102944 
102945 #define XBARB_SEL2_SEL4_MASK                     (0x7FU)
102946 #define XBARB_SEL2_SEL4_SHIFT                    (0U)
102947 #define XBARB_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
102948 
102949 #define XBARB_SEL2_SEL5_MASK                     (0x7F00U)
102950 #define XBARB_SEL2_SEL5_SHIFT                    (8U)
102951 #define XBARB_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
102952 /*! @} */
102953 
102954 /*! @name SEL3 - Crossbar B Select Register 3 */
102955 /*! @{ */
102956 
102957 #define XBARB_SEL3_SEL6_MASK                     (0x7FU)
102958 #define XBARB_SEL3_SEL6_SHIFT                    (0U)
102959 #define XBARB_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
102960 
102961 #define XBARB_SEL3_SEL7_MASK                     (0x7F00U)
102962 #define XBARB_SEL3_SEL7_SHIFT                    (8U)
102963 #define XBARB_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
102964 /*! @} */
102965 
102966 /*! @name SEL4 - Crossbar B Select Register 4 */
102967 /*! @{ */
102968 
102969 #define XBARB_SEL4_SEL8_MASK                     (0x7FU)
102970 #define XBARB_SEL4_SEL8_SHIFT                    (0U)
102971 #define XBARB_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
102972 
102973 #define XBARB_SEL4_SEL9_MASK                     (0x7F00U)
102974 #define XBARB_SEL4_SEL9_SHIFT                    (8U)
102975 #define XBARB_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
102976 /*! @} */
102977 
102978 /*! @name SEL5 - Crossbar B Select Register 5 */
102979 /*! @{ */
102980 
102981 #define XBARB_SEL5_SEL10_MASK                    (0x7FU)
102982 #define XBARB_SEL5_SEL10_SHIFT                   (0U)
102983 #define XBARB_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
102984 
102985 #define XBARB_SEL5_SEL11_MASK                    (0x7F00U)
102986 #define XBARB_SEL5_SEL11_SHIFT                   (8U)
102987 #define XBARB_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
102988 /*! @} */
102989 
102990 /*! @name SEL6 - Crossbar B Select Register 6 */
102991 /*! @{ */
102992 
102993 #define XBARB_SEL6_SEL12_MASK                    (0x7FU)
102994 #define XBARB_SEL6_SEL12_SHIFT                   (0U)
102995 #define XBARB_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
102996 
102997 #define XBARB_SEL6_SEL13_MASK                    (0x7F00U)
102998 #define XBARB_SEL6_SEL13_SHIFT                   (8U)
102999 #define XBARB_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
103000 /*! @} */
103001 
103002 /*! @name SEL7 - Crossbar B Select Register 7 */
103003 /*! @{ */
103004 
103005 #define XBARB_SEL7_SEL14_MASK                    (0x7FU)
103006 #define XBARB_SEL7_SEL14_SHIFT                   (0U)
103007 #define XBARB_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
103008 
103009 #define XBARB_SEL7_SEL15_MASK                    (0x7F00U)
103010 #define XBARB_SEL7_SEL15_SHIFT                   (8U)
103011 #define XBARB_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
103012 /*! @} */
103013 
103014 
103015 /*!
103016  * @}
103017  */ /* end of group XBARB_Register_Masks */
103018 
103019 
103020 /* XBARB - Peripheral instance base addresses */
103021 /** Peripheral XBARB2 base address */
103022 #define XBARB2_BASE                              (0x40040000u)
103023 /** Peripheral XBARB2 base pointer */
103024 #define XBARB2                                   ((XBARB_Type *)XBARB2_BASE)
103025 /** Peripheral XBARB3 base address */
103026 #define XBARB3_BASE                              (0x40044000u)
103027 /** Peripheral XBARB3 base pointer */
103028 #define XBARB3                                   ((XBARB_Type *)XBARB3_BASE)
103029 /** Array initializer of XBARB peripheral base addresses */
103030 #define XBARB_BASE_ADDRS                         { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
103031 /** Array initializer of XBARB peripheral base pointers */
103032 #define XBARB_BASE_PTRS                          { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
103033 
103034 /*!
103035  * @}
103036  */ /* end of group XBARB_Peripheral_Access_Layer */
103037 
103038 
103039 /* ----------------------------------------------------------------------------
103040    -- XECC Peripheral Access Layer
103041    ---------------------------------------------------------------------------- */
103042 
103043 /*!
103044  * @addtogroup XECC_Peripheral_Access_Layer XECC Peripheral Access Layer
103045  * @{
103046  */
103047 
103048 /** XECC - Register Layout Typedef */
103049 typedef struct {
103050   __IO uint32_t ECC_CTRL;                          /**< ECC Control Register, offset: 0x0 */
103051   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x4 */
103052   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x8 */
103053   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0xC */
103054   __IO uint32_t ERR_DATA_INJ;                      /**< Error Injection On Write Data, offset: 0x10 */
103055   __IO uint32_t ERR_ECC_INJ;                       /**< Error Injection On ECC Code of Write Data, offset: 0x14 */
103056   __I  uint32_t SINGLE_ERR_ADDR;                   /**< Single Error Address, offset: 0x18 */
103057   __I  uint32_t SINGLE_ERR_DATA;                   /**< Single Error Read Data, offset: 0x1C */
103058   __I  uint32_t SINGLE_ERR_ECC;                    /**< Single Error ECC Code, offset: 0x20 */
103059   __I  uint32_t SINGLE_ERR_POS;                    /**< Single Error Bit Position, offset: 0x24 */
103060   __I  uint32_t SINGLE_ERR_BIT_FIELD;              /**< Single Error Bit Field, offset: 0x28 */
103061   __I  uint32_t MULTI_ERR_ADDR;                    /**< Multiple Error Address, offset: 0x2C */
103062   __I  uint32_t MULTI_ERR_DATA;                    /**< Multiple Error Read Data, offset: 0x30 */
103063   __I  uint32_t MULTI_ERR_ECC;                     /**< Multiple Error ECC code, offset: 0x34 */
103064   __I  uint32_t MULTI_ERR_BIT_FIELD;               /**< Multiple Error Bit Field, offset: 0x38 */
103065   __IO uint32_t ECC_BASE_ADDR0;                    /**< ECC Region 0 Base Address, offset: 0x3C */
103066   __IO uint32_t ECC_END_ADDR0;                     /**< ECC Region 0 End Address, offset: 0x40 */
103067   __IO uint32_t ECC_BASE_ADDR1;                    /**< ECC Region 1 Base Address, offset: 0x44 */
103068   __IO uint32_t ECC_END_ADDR1;                     /**< ECC Region 1 End Address, offset: 0x48 */
103069   __IO uint32_t ECC_BASE_ADDR2;                    /**< ECC Region 2 Base Address, offset: 0x4C */
103070   __IO uint32_t ECC_END_ADDR2;                     /**< ECC Region 2 End Address, offset: 0x50 */
103071   __IO uint32_t ECC_BASE_ADDR3;                    /**< ECC Region 3 Base Address, offset: 0x54 */
103072   __IO uint32_t ECC_END_ADDR3;                     /**< ECC Region 3 End Address, offset: 0x58 */
103073 } XECC_Type;
103074 
103075 /* ----------------------------------------------------------------------------
103076    -- XECC Register Masks
103077    ---------------------------------------------------------------------------- */
103078 
103079 /*!
103080  * @addtogroup XECC_Register_Masks XECC Register Masks
103081  * @{
103082  */
103083 
103084 /*! @name ECC_CTRL - ECC Control Register */
103085 /*! @{ */
103086 
103087 #define XECC_ECC_CTRL_ECC_EN_MASK                (0x1U)
103088 #define XECC_ECC_CTRL_ECC_EN_SHIFT               (0U)
103089 /*! ECC_EN - ECC Function Enable
103090  *  0b0..Disable
103091  *  0b1..Enable
103092  */
103093 #define XECC_ECC_CTRL_ECC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK)
103094 
103095 #define XECC_ECC_CTRL_WECC_EN_MASK               (0x2U)
103096 #define XECC_ECC_CTRL_WECC_EN_SHIFT              (1U)
103097 /*! WECC_EN - Write ECC Encode Function Enable
103098  *  0b0..Disable
103099  *  0b1..Enable
103100  */
103101 #define XECC_ECC_CTRL_WECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK)
103102 
103103 #define XECC_ECC_CTRL_RECC_EN_MASK               (0x4U)
103104 #define XECC_ECC_CTRL_RECC_EN_SHIFT              (2U)
103105 /*! RECC_EN - Read ECC Function Enable
103106  *  0b0..Disable
103107  *  0b1..Enable
103108  */
103109 #define XECC_ECC_CTRL_RECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK)
103110 
103111 #define XECC_ECC_CTRL_SWAP_EN_MASK               (0x8U)
103112 #define XECC_ECC_CTRL_SWAP_EN_SHIFT              (3U)
103113 /*! SWAP_EN - Swap Data Enable
103114  *  0b0..Disable
103115  *  0b1..Enable
103116  */
103117 #define XECC_ECC_CTRL_SWAP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK)
103118 /*! @} */
103119 
103120 /*! @name ERR_STATUS - Error Interrupt Status Register */
103121 /*! @{ */
103122 
103123 #define XECC_ERR_STATUS_SINGLE_ERR_MASK          (0x1U)
103124 #define XECC_ERR_STATUS_SINGLE_ERR_SHIFT         (0U)
103125 /*! SINGLE_ERR - Single Bit Error
103126  *  0b0..Single bit error does not happen.
103127  *  0b1..Single bit error happens.
103128  */
103129 #define XECC_ERR_STATUS_SINGLE_ERR(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)
103130 
103131 #define XECC_ERR_STATUS_MULTI_ERR_MASK           (0x2U)
103132 #define XECC_ERR_STATUS_MULTI_ERR_SHIFT          (1U)
103133 /*! MULTI_ERR - Multiple Bits Error
103134  *  0b0..Multiple bits error does not happen.
103135  *  0b1..Multiple bits error happens.
103136  */
103137 #define XECC_ERR_STATUS_MULTI_ERR(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)
103138 
103139 #define XECC_ERR_STATUS_Reserved1_MASK           (0xFFFFFFFCU)
103140 #define XECC_ERR_STATUS_Reserved1_SHIFT          (2U)
103141 /*! Reserved1 - Reserved
103142  */
103143 #define XECC_ERR_STATUS_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)
103144 /*! @} */
103145 
103146 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
103147 /*! @{ */
103148 
103149 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)
103150 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)
103151 /*! SINGLE_ERR_STAT_EN - Single Bit Error Status Enable
103152  *  0b0..Masked
103153  *  0b1..Enabled
103154  */
103155 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)
103156 
103157 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK  (0x2U)
103158 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)
103159 /*! MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable
103160  *  0b0..Masked
103161  *  0b1..Enabled
103162  */
103163 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)
103164 
103165 #define XECC_ERR_STAT_EN_Reserved1_MASK          (0xFFFFFFFCU)
103166 #define XECC_ERR_STAT_EN_Reserved1_SHIFT         (2U)
103167 /*! Reserved1 - Reserved
103168  */
103169 #define XECC_ERR_STAT_EN_Reserved1(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)
103170 /*! @} */
103171 
103172 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
103173 /*! @{ */
103174 
103175 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK   (0x1U)
103176 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT  (0U)
103177 /*! SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable
103178  *  0b0..Masked
103179  *  0b1..Enabled
103180  */
103181 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)
103182 
103183 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK    (0x2U)
103184 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT   (1U)
103185 /*! MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable
103186  *  0b0..Masked
103187  *  0b1..Enabled
103188  */
103189 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)
103190 
103191 #define XECC_ERR_SIG_EN_Reserved1_MASK           (0xFFFFFFFCU)
103192 #define XECC_ERR_SIG_EN_Reserved1_SHIFT          (2U)
103193 /*! Reserved1 - Reserved
103194  */
103195 #define XECC_ERR_SIG_EN_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)
103196 /*! @} */
103197 
103198 /*! @name ERR_DATA_INJ - Error Injection On Write Data */
103199 /*! @{ */
103200 
103201 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK      (0xFFFFFFFFU)
103202 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT     (0U)
103203 /*! ERR_DATA_INJ - Error Injection On Write Data
103204  */
103205 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ(x)        (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK)
103206 /*! @} */
103207 
103208 /*! @name ERR_ECC_INJ - Error Injection On ECC Code of Write Data */
103209 /*! @{ */
103210 
103211 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK        (0xFFFFFFFFU)
103212 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT       (0U)
103213 /*! ERR_ECC_INJ - Error Injection On ECC Code of Write Data
103214  */
103215 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ(x)          (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK)
103216 /*! @} */
103217 
103218 /*! @name SINGLE_ERR_ADDR - Single Error Address */
103219 /*! @{ */
103220 
103221 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU)
103222 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U)
103223 /*! SINGLE_ERR_ADDR - Single Error Address
103224  */
103225 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK)
103226 /*! @} */
103227 
103228 /*! @name SINGLE_ERR_DATA - Single Error Read Data */
103229 /*! @{ */
103230 
103231 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
103232 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U)
103233 /*! SINGLE_ERR_DATA - Single Error Read Data
103234  */
103235 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK)
103236 /*! @} */
103237 
103238 /*! @name SINGLE_ERR_ECC - Single Error ECC Code */
103239 /*! @{ */
103240 
103241 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK  (0xFFFFFFFFU)
103242 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U)
103243 /*! SINGLE_ERR_ECC - Single Error ECC code
103244  */
103245 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK)
103246 /*! @} */
103247 
103248 /*! @name SINGLE_ERR_POS - Single Error Bit Position */
103249 /*! @{ */
103250 
103251 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK  (0xFFFFFFFFU)
103252 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U)
103253 /*! SINGLE_ERR_POS - Single Error bit Position
103254  */
103255 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK)
103256 /*! @} */
103257 
103258 /*! @name SINGLE_ERR_BIT_FIELD - Single Error Bit Field */
103259 /*! @{ */
103260 
103261 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU)
103262 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U)
103263 /*! SINGLE_ERR_BIT_FIELD - Single Error Bit Field
103264  */
103265 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK)
103266 
103267 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
103268 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
103269 /*! Reserved1 - Reserved
103270  */
103271 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x)   (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK)
103272 /*! @} */
103273 
103274 /*! @name MULTI_ERR_ADDR - Multiple Error Address */
103275 /*! @{ */
103276 
103277 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK  (0xFFFFFFFFU)
103278 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U)
103279 /*! MULTI_ERR_ADDR - Multiple Error Address
103280  */
103281 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK)
103282 /*! @} */
103283 
103284 /*! @name MULTI_ERR_DATA - Multiple Error Read Data */
103285 /*! @{ */
103286 
103287 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK  (0xFFFFFFFFU)
103288 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U)
103289 /*! MULTI_ERR_DATA - Multiple Error Read Data
103290  */
103291 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK)
103292 /*! @} */
103293 
103294 /*! @name MULTI_ERR_ECC - Multiple Error ECC code */
103295 /*! @{ */
103296 
103297 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK    (0xFFFFFFFFU)
103298 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT   (0U)
103299 /*! MULTI_ERR_ECC - Multiple Error ECC code
103300  */
103301 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x)      (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK)
103302 /*! @} */
103303 
103304 /*! @name MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */
103305 /*! @{ */
103306 
103307 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU)
103308 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U)
103309 /*! MULTI_ERR_BIT_FIELD - Multiple Error Bit Field
103310  */
103311 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK)
103312 
103313 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK  (0xFFFFFF00U)
103314 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
103315 /*! Reserved1 - Reserved
103316  */
103317 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK)
103318 /*! @} */
103319 
103320 /*! @name ECC_BASE_ADDR0 - ECC Region 0 Base Address */
103321 /*! @{ */
103322 
103323 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK  (0xFFFFFFFFU)
103324 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U)
103325 /*! ECC_BASE_ADDR0 - ECC Region 0 Base Address
103326  */
103327 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK)
103328 /*! @} */
103329 
103330 /*! @name ECC_END_ADDR0 - ECC Region 0 End Address */
103331 /*! @{ */
103332 
103333 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK    (0xFFFFFFFFU)
103334 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT   (0U)
103335 /*! ECC_END_ADDR0 - ECC Region 0 End Address
103336  */
103337 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK)
103338 /*! @} */
103339 
103340 /*! @name ECC_BASE_ADDR1 - ECC Region 1 Base Address */
103341 /*! @{ */
103342 
103343 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK  (0xFFFFFFFFU)
103344 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U)
103345 /*! ECC_BASE_ADDR1 - ECC Region 1 Base Address
103346  */
103347 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK)
103348 /*! @} */
103349 
103350 /*! @name ECC_END_ADDR1 - ECC Region 1 End Address */
103351 /*! @{ */
103352 
103353 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK    (0xFFFFFFFFU)
103354 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT   (0U)
103355 /*! ECC_END_ADDR1 - ECC Region 1 End Address
103356  */
103357 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK)
103358 /*! @} */
103359 
103360 /*! @name ECC_BASE_ADDR2 - ECC Region 2 Base Address */
103361 /*! @{ */
103362 
103363 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK  (0xFFFFFFFFU)
103364 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U)
103365 /*! ECC_BASE_ADDR2 - ECC Region 2 Base Address
103366  */
103367 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK)
103368 /*! @} */
103369 
103370 /*! @name ECC_END_ADDR2 - ECC Region 2 End Address */
103371 /*! @{ */
103372 
103373 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK    (0xFFFFFFFFU)
103374 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT   (0U)
103375 /*! ECC_END_ADDR2 - ECC Region 2 End Address
103376  */
103377 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK)
103378 /*! @} */
103379 
103380 /*! @name ECC_BASE_ADDR3 - ECC Region 3 Base Address */
103381 /*! @{ */
103382 
103383 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK  (0xFFFFFFFFU)
103384 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U)
103385 /*! ECC_BASE_ADDR3 - ECC Region 3 Base Address
103386  */
103387 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK)
103388 /*! @} */
103389 
103390 /*! @name ECC_END_ADDR3 - ECC Region 3 End Address */
103391 /*! @{ */
103392 
103393 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK    (0xFFFFFFFFU)
103394 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT   (0U)
103395 /*! ECC_END_ADDR3 - ECC Region 3 End Address
103396  */
103397 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK)
103398 /*! @} */
103399 
103400 
103401 /*!
103402  * @}
103403  */ /* end of group XECC_Register_Masks */
103404 
103405 
103406 /* XECC - Peripheral instance base addresses */
103407 /** Peripheral XECC_FLEXSPI1 base address */
103408 #define XECC_FLEXSPI1_BASE                       (0x4001C000u)
103409 /** Peripheral XECC_FLEXSPI1 base pointer */
103410 #define XECC_FLEXSPI1                            ((XECC_Type *)XECC_FLEXSPI1_BASE)
103411 /** Peripheral XECC_FLEXSPI2 base address */
103412 #define XECC_FLEXSPI2_BASE                       (0x40020000u)
103413 /** Peripheral XECC_FLEXSPI2 base pointer */
103414 #define XECC_FLEXSPI2                            ((XECC_Type *)XECC_FLEXSPI2_BASE)
103415 /** Peripheral XECC_SEMC base address */
103416 #define XECC_SEMC_BASE                           (0x40024000u)
103417 /** Peripheral XECC_SEMC base pointer */
103418 #define XECC_SEMC                                ((XECC_Type *)XECC_SEMC_BASE)
103419 /** Array initializer of XECC peripheral base addresses */
103420 #define XECC_BASE_ADDRS                          { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
103421 /** Array initializer of XECC peripheral base pointers */
103422 #define XECC_BASE_PTRS                           { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
103423 
103424 /*!
103425  * @}
103426  */ /* end of group XECC_Peripheral_Access_Layer */
103427 
103428 
103429 /* ----------------------------------------------------------------------------
103430    -- XRDC2 Peripheral Access Layer
103431    ---------------------------------------------------------------------------- */
103432 
103433 /*!
103434  * @addtogroup XRDC2_Peripheral_Access_Layer XRDC2 Peripheral Access Layer
103435  * @{
103436  */
103437 
103438 /** XRDC2 - Register Layout Typedef */
103439 typedef struct {
103440   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
103441   __I  uint32_t SR;                                /**< Status Register, offset: 0x4 */
103442        uint8_t RESERVED_0[4088];
103443   struct {                                         /* offset: 0x1000, array step: 0x8 */
103444     __IO uint32_t MSC_MSAC_W0;                       /**< Memory Slot Access Control, array offset: 0x1000, array step: 0x8 */
103445     __IO uint32_t MSC_MSAC_W1;                       /**< Memory Slot Access Control, array offset: 0x1004, array step: 0x8 */
103446   } MSCI_MSAC_WK[128];
103447        uint8_t RESERVED_1[3072];
103448   struct {                                         /* offset: 0x2000, array step: index*0x100, index2*0x8 */
103449     __IO uint32_t MDAC_MDA_W0;                       /**< Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8 */
103450     __IO uint32_t MDAC_MDA_W1;                       /**< Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8 */
103451   } MDACI_MDAJ[32][32];
103452   struct {                                         /* offset: 0x4000, array step: index*0x800, index2*0x8 */
103453     __IO uint32_t PAC_PDAC_W0;                       /**< Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8 */
103454     __IO uint32_t PAC_PDAC_W1;                       /**< Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8 */
103455   } PACI_PDACJ[8][256];
103456   struct {                                         /* offset: 0x8000, array step: index*0x400, index2*0x20 */
103457     __IO uint32_t MRC_MRGD_W0;                       /**< Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20 */
103458     __IO uint32_t MRC_MRGD_W1;                       /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */
103459     __IO uint32_t MRC_MRGD_W2;                       /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */
103460     __IO uint32_t MRC_MRGD_W3;                       /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */
103461          uint8_t RESERVED_0[4];
103462     __IO uint32_t MRC_MRGD_W5;                       /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */
103463     __IO uint32_t MRC_MRGD_W6;                       /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */
103464          uint8_t RESERVED_1[4];
103465   } MRCI_MRGDJ[32][32];
103466 } XRDC2_Type;
103467 
103468 /* ----------------------------------------------------------------------------
103469    -- XRDC2 Register Masks
103470    ---------------------------------------------------------------------------- */
103471 
103472 /*!
103473  * @addtogroup XRDC2_Register_Masks XRDC2 Register Masks
103474  * @{
103475  */
103476 
103477 /*! @name MCR - Module Control Register */
103478 /*! @{ */
103479 
103480 #define XRDC2_MCR_GVLDM_MASK                     (0x1U)
103481 #define XRDC2_MCR_GVLDM_SHIFT                    (0U)
103482 /*! GVLDM - Global Valid MDAC
103483  *  0b0..MDACs are disabled.
103484  *  0b1..MDACs are enabled.
103485  */
103486 #define XRDC2_MCR_GVLDM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
103487 
103488 #define XRDC2_MCR_GVLDC_MASK                     (0x2U)
103489 #define XRDC2_MCR_GVLDC_SHIFT                    (1U)
103490 /*! GVLDC - Global Valid Access Control
103491  *  0b0..Access controls are disabled, XRDC2 allows all transactions.
103492  *  0b1..Access controls are enabled.
103493  */
103494 #define XRDC2_MCR_GVLDC(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
103495 
103496 #define XRDC2_MCR_GCL_MASK                       (0x30U)
103497 #define XRDC2_MCR_GCL_SHIFT                      (4U)
103498 /*! GCL - Global Configuration Lock
103499  *  0b00..Lock disabled, registers can be written by any domain.
103500  *  0b01..Lock disabled until the next reset, registers can be written by any domain.
103501  *  0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers.
103502  *  0b11..Lock enabled, all registers are read only until the next reset.
103503  */
103504 #define XRDC2_MCR_GCL(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)
103505 /*! @} */
103506 
103507 /*! @name SR - Status Register */
103508 /*! @{ */
103509 
103510 #define XRDC2_SR_DIN_MASK                        (0xFU)
103511 #define XRDC2_SR_DIN_SHIFT                       (0U)
103512 /*! DIN - Domain Identifier Number
103513  */
103514 #define XRDC2_SR_DIN(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
103515 
103516 #define XRDC2_SR_HRL_MASK                        (0xF0U)
103517 #define XRDC2_SR_HRL_SHIFT                       (4U)
103518 /*! HRL - Hardware Revision Level
103519  */
103520 #define XRDC2_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
103521 
103522 #define XRDC2_SR_GCLO_MASK                       (0xF00U)
103523 #define XRDC2_SR_GCLO_SHIFT                      (8U)
103524 /*! GCLO - Global Configuration Lock Owner
103525  */
103526 #define XRDC2_SR_GCLO(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)
103527 /*! @} */
103528 
103529 /*! @name MSC_MSAC_W0 - Memory Slot Access Control */
103530 /*! @{ */
103531 
103532 #define XRDC2_MSC_MSAC_W0_D0ACP_MASK             (0x7U)
103533 #define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT            (0U)
103534 /*! D0ACP - Domain "x" access control policy
103535  */
103536 #define XRDC2_MSC_MSAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
103537 
103538 #define XRDC2_MSC_MSAC_W0_D1ACP_MASK             (0x38U)
103539 #define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT            (3U)
103540 /*! D1ACP - Domain "x" access control policy
103541  */
103542 #define XRDC2_MSC_MSAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
103543 
103544 #define XRDC2_MSC_MSAC_W0_D2ACP_MASK             (0x1C0U)
103545 #define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT            (6U)
103546 /*! D2ACP - Domain "x" access control policy
103547  */
103548 #define XRDC2_MSC_MSAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
103549 
103550 #define XRDC2_MSC_MSAC_W0_D3ACP_MASK             (0xE00U)
103551 #define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT            (9U)
103552 /*! D3ACP - Domain "x" access control policy
103553  */
103554 #define XRDC2_MSC_MSAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
103555 
103556 #define XRDC2_MSC_MSAC_W0_D4ACP_MASK             (0x7000U)
103557 #define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT            (12U)
103558 /*! D4ACP - Domain "x" access control policy
103559  */
103560 #define XRDC2_MSC_MSAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
103561 
103562 #define XRDC2_MSC_MSAC_W0_D5ACP_MASK             (0x38000U)
103563 #define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT            (15U)
103564 /*! D5ACP - Domain "x" access control policy
103565  */
103566 #define XRDC2_MSC_MSAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
103567 
103568 #define XRDC2_MSC_MSAC_W0_D6ACP_MASK             (0x1C0000U)
103569 #define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT            (18U)
103570 /*! D6ACP - Domain "x" access control policy
103571  */
103572 #define XRDC2_MSC_MSAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
103573 
103574 #define XRDC2_MSC_MSAC_W0_D7ACP_MASK             (0xE00000U)
103575 #define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT            (21U)
103576 /*! D7ACP - Domain "x" access control policy
103577  */
103578 #define XRDC2_MSC_MSAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
103579 
103580 #define XRDC2_MSC_MSAC_W0_EALO_MASK              (0xF000000U)
103581 #define XRDC2_MSC_MSAC_W0_EALO_SHIFT             (24U)
103582 /*! EALO - Exclusive Access Lock Owner
103583  */
103584 #define XRDC2_MSC_MSAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)
103585 /*! @} */
103586 
103587 /* The count of XRDC2_MSC_MSAC_W0 */
103588 #define XRDC2_MSC_MSAC_W0_COUNT                  (128U)
103589 
103590 /*! @name MSC_MSAC_W1 - Memory Slot Access Control */
103591 /*! @{ */
103592 
103593 #define XRDC2_MSC_MSAC_W1_D8ACP_MASK             (0x7U)
103594 #define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT            (0U)
103595 /*! D8ACP - Domain "x" access control policy
103596  */
103597 #define XRDC2_MSC_MSAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
103598 
103599 #define XRDC2_MSC_MSAC_W1_D9ACP_MASK             (0x38U)
103600 #define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT            (3U)
103601 /*! D9ACP - Domain "x" access control policy
103602  */
103603 #define XRDC2_MSC_MSAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
103604 
103605 #define XRDC2_MSC_MSAC_W1_D10ACP_MASK            (0x1C0U)
103606 #define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT           (6U)
103607 /*! D10ACP - Domain "x" access control policy
103608  */
103609 #define XRDC2_MSC_MSAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
103610 
103611 #define XRDC2_MSC_MSAC_W1_D11ACP_MASK            (0xE00U)
103612 #define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT           (9U)
103613 /*! D11ACP - Domain "x" access control policy
103614  */
103615 #define XRDC2_MSC_MSAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
103616 
103617 #define XRDC2_MSC_MSAC_W1_D12ACP_MASK            (0x7000U)
103618 #define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT           (12U)
103619 /*! D12ACP - Domain "x" access control policy
103620  */
103621 #define XRDC2_MSC_MSAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
103622 
103623 #define XRDC2_MSC_MSAC_W1_D13ACP_MASK            (0x38000U)
103624 #define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT           (15U)
103625 /*! D13ACP - Domain "x" access control policy
103626  */
103627 #define XRDC2_MSC_MSAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
103628 
103629 #define XRDC2_MSC_MSAC_W1_D14ACP_MASK            (0x1C0000U)
103630 #define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT           (18U)
103631 /*! D14ACP - Domain "x" access control policy
103632  */
103633 #define XRDC2_MSC_MSAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
103634 
103635 #define XRDC2_MSC_MSAC_W1_D15ACP_MASK            (0xE00000U)
103636 #define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT           (21U)
103637 /*! D15ACP - Domain "x" access control policy
103638  */
103639 #define XRDC2_MSC_MSAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
103640 
103641 #define XRDC2_MSC_MSAC_W1_EAL_MASK               (0x3000000U)
103642 #define XRDC2_MSC_MSAC_W1_EAL_SHIFT              (24U)
103643 /*! EAL - Exclusive Access Lock
103644  *  0b00..Lock disabled.
103645  *  0b01..Lock disabled until next reset.
103646  *  0b10..Lock enabled, lock state = available.
103647  *  0b11..Lock enabled, lock state = not available.
103648  */
103649 #define XRDC2_MSC_MSAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
103650 
103651 #define XRDC2_MSC_MSAC_W1_DL2_MASK               (0x60000000U)
103652 #define XRDC2_MSC_MSAC_W1_DL2_SHIFT              (29U)
103653 /*! DL2 - Descriptor Lock
103654  *  0b00..Lock disabled, descriptor registers can be written.
103655  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
103656  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
103657  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
103658  */
103659 #define XRDC2_MSC_MSAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
103660 
103661 #define XRDC2_MSC_MSAC_W1_VLD_MASK               (0x80000000U)
103662 #define XRDC2_MSC_MSAC_W1_VLD_SHIFT              (31U)
103663 /*! VLD - Valid
103664  *  0b0..The MSAC assignment is invalid.
103665  *  0b1..The MSAC assignment is valid.
103666  */
103667 #define XRDC2_MSC_MSAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)
103668 /*! @} */
103669 
103670 /* The count of XRDC2_MSC_MSAC_W1 */
103671 #define XRDC2_MSC_MSAC_W1_COUNT                  (128U)
103672 
103673 /*! @name MDAC_MDA_W0 - Master Domain Assignment */
103674 /*! @{ */
103675 
103676 #define XRDC2_MDAC_MDA_W0_MASK_MASK              (0xFFFFU)
103677 #define XRDC2_MDAC_MDA_W0_MASK_SHIFT             (0U)
103678 /*! MASK - Mask
103679  */
103680 #define XRDC2_MDAC_MDA_W0_MASK(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
103681 
103682 #define XRDC2_MDAC_MDA_W0_MATCH_MASK             (0xFFFF0000U)
103683 #define XRDC2_MDAC_MDA_W0_MATCH_SHIFT            (16U)
103684 /*! MATCH - Match
103685  */
103686 #define XRDC2_MDAC_MDA_W0_MATCH(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)
103687 /*! @} */
103688 
103689 /* The count of XRDC2_MDAC_MDA_W0 */
103690 #define XRDC2_MDAC_MDA_W0_COUNT                  (32U)
103691 
103692 /* The count of XRDC2_MDAC_MDA_W0 */
103693 #define XRDC2_MDAC_MDA_W0_COUNT2                 (32U)
103694 
103695 /*! @name MDAC_MDA_W1 - Master Domain Assignment */
103696 /*! @{ */
103697 
103698 #define XRDC2_MDAC_MDA_W1_DID_MASK               (0xF0000U)
103699 #define XRDC2_MDAC_MDA_W1_DID_SHIFT              (16U)
103700 /*! DID - Domain Identifier
103701  */
103702 #define XRDC2_MDAC_MDA_W1_DID(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
103703 
103704 #define XRDC2_MDAC_MDA_W1_PA_MASK                (0x3000000U)
103705 #define XRDC2_MDAC_MDA_W1_PA_SHIFT               (24U)
103706 /*! PA - Privileged attribute
103707  *  0b00..Use the bus master's privileged/user attribute directly.
103708  *  0b01..Use the bus master's privileged/user attribute directly.
103709  *  0b10..Force the bus attribute for this master to user.
103710  *  0b11..Force the bus attribute for this master to privileged.
103711  */
103712 #define XRDC2_MDAC_MDA_W1_PA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
103713 
103714 #define XRDC2_MDAC_MDA_W1_SA_MASK                (0xC000000U)
103715 #define XRDC2_MDAC_MDA_W1_SA_SHIFT               (26U)
103716 /*! SA - Secure attribute
103717  *  0b00..Use the bus master's secure/nonsecure attribute directly.
103718  *  0b01..Use the bus master's secure/nonsecure attribute directly.
103719  *  0b10..Force the bus attribute for this master to secure.
103720  *  0b11..Force the bus attribute for this master to nonsecure.
103721  */
103722 #define XRDC2_MDAC_MDA_W1_SA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
103723 
103724 #define XRDC2_MDAC_MDA_W1_DL_MASK                (0x40000000U)
103725 #define XRDC2_MDAC_MDA_W1_DL_SHIFT               (30U)
103726 /*! DL - Descriptor Lock
103727  *  0b0..Lock disabled, registers can be written.
103728  *  0b1..Lock enabled, registers are read-only until the next reset.
103729  */
103730 #define XRDC2_MDAC_MDA_W1_DL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
103731 
103732 #define XRDC2_MDAC_MDA_W1_VLD_MASK               (0x80000000U)
103733 #define XRDC2_MDAC_MDA_W1_VLD_SHIFT              (31U)
103734 /*! VLD - Valid
103735  *  0b0..The MDA is invalid.
103736  *  0b1..The MDA is valid.
103737  */
103738 #define XRDC2_MDAC_MDA_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)
103739 /*! @} */
103740 
103741 /* The count of XRDC2_MDAC_MDA_W1 */
103742 #define XRDC2_MDAC_MDA_W1_COUNT                  (32U)
103743 
103744 /* The count of XRDC2_MDAC_MDA_W1 */
103745 #define XRDC2_MDAC_MDA_W1_COUNT2                 (32U)
103746 
103747 /*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */
103748 /*! @{ */
103749 
103750 #define XRDC2_PAC_PDAC_W0_D0ACP_MASK             (0x7U)
103751 #define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT            (0U)
103752 /*! D0ACP - Domain "x" access control policy
103753  */
103754 #define XRDC2_PAC_PDAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
103755 
103756 #define XRDC2_PAC_PDAC_W0_D1ACP_MASK             (0x38U)
103757 #define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT            (3U)
103758 /*! D1ACP - Domain "x" access control policy
103759  */
103760 #define XRDC2_PAC_PDAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
103761 
103762 #define XRDC2_PAC_PDAC_W0_D2ACP_MASK             (0x1C0U)
103763 #define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT            (6U)
103764 /*! D2ACP - Domain "x" access control policy
103765  */
103766 #define XRDC2_PAC_PDAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
103767 
103768 #define XRDC2_PAC_PDAC_W0_D3ACP_MASK             (0xE00U)
103769 #define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT            (9U)
103770 /*! D3ACP - Domain "x" access control policy
103771  */
103772 #define XRDC2_PAC_PDAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
103773 
103774 #define XRDC2_PAC_PDAC_W0_D4ACP_MASK             (0x7000U)
103775 #define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT            (12U)
103776 /*! D4ACP - Domain "x" access control policy
103777  */
103778 #define XRDC2_PAC_PDAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
103779 
103780 #define XRDC2_PAC_PDAC_W0_D5ACP_MASK             (0x38000U)
103781 #define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT            (15U)
103782 /*! D5ACP - Domain "x" access control policy
103783  */
103784 #define XRDC2_PAC_PDAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
103785 
103786 #define XRDC2_PAC_PDAC_W0_D6ACP_MASK             (0x1C0000U)
103787 #define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT            (18U)
103788 /*! D6ACP - Domain "x" access control policy
103789  */
103790 #define XRDC2_PAC_PDAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
103791 
103792 #define XRDC2_PAC_PDAC_W0_D7ACP_MASK             (0xE00000U)
103793 #define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT            (21U)
103794 /*! D7ACP - Domain "x" access control policy
103795  */
103796 #define XRDC2_PAC_PDAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
103797 
103798 #define XRDC2_PAC_PDAC_W0_EALO_MASK              (0xF000000U)
103799 #define XRDC2_PAC_PDAC_W0_EALO_SHIFT             (24U)
103800 /*! EALO - Exclusive Access Lock Owner
103801  */
103802 #define XRDC2_PAC_PDAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)
103803 /*! @} */
103804 
103805 /* The count of XRDC2_PAC_PDAC_W0 */
103806 #define XRDC2_PAC_PDAC_W0_COUNT                  (8U)
103807 
103808 /* The count of XRDC2_PAC_PDAC_W0 */
103809 #define XRDC2_PAC_PDAC_W0_COUNT2                 (256U)
103810 
103811 /*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */
103812 /*! @{ */
103813 
103814 #define XRDC2_PAC_PDAC_W1_D8ACP_MASK             (0x7U)
103815 #define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT            (0U)
103816 /*! D8ACP - Domain "x" access control policy
103817  */
103818 #define XRDC2_PAC_PDAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
103819 
103820 #define XRDC2_PAC_PDAC_W1_D9ACP_MASK             (0x38U)
103821 #define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT            (3U)
103822 /*! D9ACP - Domain "x" access control policy
103823  */
103824 #define XRDC2_PAC_PDAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
103825 
103826 #define XRDC2_PAC_PDAC_W1_D10ACP_MASK            (0x1C0U)
103827 #define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT           (6U)
103828 /*! D10ACP - Domain "x" access control policy
103829  */
103830 #define XRDC2_PAC_PDAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
103831 
103832 #define XRDC2_PAC_PDAC_W1_D11ACP_MASK            (0xE00U)
103833 #define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT           (9U)
103834 /*! D11ACP - Domain "x" access control policy
103835  */
103836 #define XRDC2_PAC_PDAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
103837 
103838 #define XRDC2_PAC_PDAC_W1_D12ACP_MASK            (0x7000U)
103839 #define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT           (12U)
103840 /*! D12ACP - Domain "x" access control policy
103841  */
103842 #define XRDC2_PAC_PDAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
103843 
103844 #define XRDC2_PAC_PDAC_W1_D13ACP_MASK            (0x38000U)
103845 #define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT           (15U)
103846 /*! D13ACP - Domain "x" access control policy
103847  */
103848 #define XRDC2_PAC_PDAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
103849 
103850 #define XRDC2_PAC_PDAC_W1_D14ACP_MASK            (0x1C0000U)
103851 #define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT           (18U)
103852 /*! D14ACP - Domain "x" access control policy
103853  */
103854 #define XRDC2_PAC_PDAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
103855 
103856 #define XRDC2_PAC_PDAC_W1_D15ACP_MASK            (0xE00000U)
103857 #define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT           (21U)
103858 /*! D15ACP - Domain "x" access control policy
103859  */
103860 #define XRDC2_PAC_PDAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
103861 
103862 #define XRDC2_PAC_PDAC_W1_EAL_MASK               (0x3000000U)
103863 #define XRDC2_PAC_PDAC_W1_EAL_SHIFT              (24U)
103864 /*! EAL - Exclusive Access Lock
103865  *  0b00..Lock disabled.
103866  *  0b01..Lock disabled until next reset.
103867  *  0b10..Lock enabled, lock state = available.
103868  *  0b11..Lock enabled, lock state = not available.
103869  */
103870 #define XRDC2_PAC_PDAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
103871 
103872 #define XRDC2_PAC_PDAC_W1_DL2_MASK               (0x60000000U)
103873 #define XRDC2_PAC_PDAC_W1_DL2_SHIFT              (29U)
103874 /*! DL2 - Descriptor Lock
103875  *  0b00..Lock disabled, descriptor registers can be written..
103876  *  0b01..Lock disabled until the next reset, descriptor registers can be written..
103877  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written..
103878  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
103879  */
103880 #define XRDC2_PAC_PDAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
103881 
103882 #define XRDC2_PAC_PDAC_W1_VLD_MASK               (0x80000000U)
103883 #define XRDC2_PAC_PDAC_W1_VLD_SHIFT              (31U)
103884 /*! VLD - Valid
103885  *  0b0..The PDAC assignment is invalid.
103886  *  0b1..The PDAC assignment is valid.
103887  */
103888 #define XRDC2_PAC_PDAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)
103889 /*! @} */
103890 
103891 /* The count of XRDC2_PAC_PDAC_W1 */
103892 #define XRDC2_PAC_PDAC_W1_COUNT                  (8U)
103893 
103894 /* The count of XRDC2_PAC_PDAC_W1 */
103895 #define XRDC2_PAC_PDAC_W1_COUNT2                 (256U)
103896 
103897 /*! @name MRC_MRGD_W0 - Memory Region Descriptor */
103898 /*! @{ */
103899 
103900 #define XRDC2_MRC_MRGD_W0_SRTADDR_MASK           (0xFFFFF000U)
103901 #define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT          (12U)
103902 /*! SRTADDR - Start Address
103903  */
103904 #define XRDC2_MRC_MRGD_W0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)
103905 /*! @} */
103906 
103907 /* The count of XRDC2_MRC_MRGD_W0 */
103908 #define XRDC2_MRC_MRGD_W0_COUNT                  (32U)
103909 
103910 /* The count of XRDC2_MRC_MRGD_W0 */
103911 #define XRDC2_MRC_MRGD_W0_COUNT2                 (32U)
103912 
103913 /*! @name MRC_MRGD_W1 - Memory Region Descriptor */
103914 /*! @{ */
103915 
103916 #define XRDC2_MRC_MRGD_W1_SRTADDR_MASK           (0xFU)
103917 #define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT          (0U)
103918 /*! SRTADDR - Start Address
103919  */
103920 #define XRDC2_MRC_MRGD_W1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)
103921 /*! @} */
103922 
103923 /* The count of XRDC2_MRC_MRGD_W1 */
103924 #define XRDC2_MRC_MRGD_W1_COUNT                  (32U)
103925 
103926 /* The count of XRDC2_MRC_MRGD_W1 */
103927 #define XRDC2_MRC_MRGD_W1_COUNT2                 (32U)
103928 
103929 /*! @name MRC_MRGD_W2 - Memory Region Descriptor */
103930 /*! @{ */
103931 
103932 #define XRDC2_MRC_MRGD_W2_ENDADDR_MASK           (0xFFFFF000U)
103933 #define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT          (12U)
103934 /*! ENDADDR - End Address
103935  */
103936 #define XRDC2_MRC_MRGD_W2_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)
103937 /*! @} */
103938 
103939 /* The count of XRDC2_MRC_MRGD_W2 */
103940 #define XRDC2_MRC_MRGD_W2_COUNT                  (32U)
103941 
103942 /* The count of XRDC2_MRC_MRGD_W2 */
103943 #define XRDC2_MRC_MRGD_W2_COUNT2                 (32U)
103944 
103945 /*! @name MRC_MRGD_W3 - Memory Region Descriptor */
103946 /*! @{ */
103947 
103948 #define XRDC2_MRC_MRGD_W3_ENDADDR_MASK           (0xFU)
103949 #define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT          (0U)
103950 /*! ENDADDR - End Address
103951  */
103952 #define XRDC2_MRC_MRGD_W3_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)
103953 /*! @} */
103954 
103955 /* The count of XRDC2_MRC_MRGD_W3 */
103956 #define XRDC2_MRC_MRGD_W3_COUNT                  (32U)
103957 
103958 /* The count of XRDC2_MRC_MRGD_W3 */
103959 #define XRDC2_MRC_MRGD_W3_COUNT2                 (32U)
103960 
103961 /*! @name MRC_MRGD_W5 - Memory Region Descriptor */
103962 /*! @{ */
103963 
103964 #define XRDC2_MRC_MRGD_W5_D0ACP_MASK             (0x7U)
103965 #define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT            (0U)
103966 /*! D0ACP - Domain "x" access control policy
103967  */
103968 #define XRDC2_MRC_MRGD_W5_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
103969 
103970 #define XRDC2_MRC_MRGD_W5_D1ACP_MASK             (0x38U)
103971 #define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT            (3U)
103972 /*! D1ACP - Domain "x" access control policy
103973  */
103974 #define XRDC2_MRC_MRGD_W5_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
103975 
103976 #define XRDC2_MRC_MRGD_W5_D2ACP_MASK             (0x1C0U)
103977 #define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT            (6U)
103978 /*! D2ACP - Domain "x" access control policy
103979  */
103980 #define XRDC2_MRC_MRGD_W5_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
103981 
103982 #define XRDC2_MRC_MRGD_W5_D3ACP_MASK             (0xE00U)
103983 #define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT            (9U)
103984 /*! D3ACP - Domain "x" access control policy
103985  */
103986 #define XRDC2_MRC_MRGD_W5_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
103987 
103988 #define XRDC2_MRC_MRGD_W5_D4ACP_MASK             (0x7000U)
103989 #define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT            (12U)
103990 /*! D4ACP - Domain "x" access control policy
103991  */
103992 #define XRDC2_MRC_MRGD_W5_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
103993 
103994 #define XRDC2_MRC_MRGD_W5_D5ACP_MASK             (0x38000U)
103995 #define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT            (15U)
103996 /*! D5ACP - Domain "x" access control policy
103997  */
103998 #define XRDC2_MRC_MRGD_W5_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
103999 
104000 #define XRDC2_MRC_MRGD_W5_D6ACP_MASK             (0x1C0000U)
104001 #define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT            (18U)
104002 /*! D6ACP - Domain "x" access control policy
104003  */
104004 #define XRDC2_MRC_MRGD_W5_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
104005 
104006 #define XRDC2_MRC_MRGD_W5_D7ACP_MASK             (0xE00000U)
104007 #define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT            (21U)
104008 /*! D7ACP - Domain "x" access control policy
104009  */
104010 #define XRDC2_MRC_MRGD_W5_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
104011 
104012 #define XRDC2_MRC_MRGD_W5_EALO_MASK              (0xF000000U)
104013 #define XRDC2_MRC_MRGD_W5_EALO_SHIFT             (24U)
104014 /*! EALO - Exclusive Access Lock Owner
104015  */
104016 #define XRDC2_MRC_MRGD_W5_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)
104017 /*! @} */
104018 
104019 /* The count of XRDC2_MRC_MRGD_W5 */
104020 #define XRDC2_MRC_MRGD_W5_COUNT                  (32U)
104021 
104022 /* The count of XRDC2_MRC_MRGD_W5 */
104023 #define XRDC2_MRC_MRGD_W5_COUNT2                 (32U)
104024 
104025 /*! @name MRC_MRGD_W6 - Memory Region Descriptor */
104026 /*! @{ */
104027 
104028 #define XRDC2_MRC_MRGD_W6_D8ACP_MASK             (0x7U)
104029 #define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT            (0U)
104030 /*! D8ACP - Domain "x" access control policy
104031  */
104032 #define XRDC2_MRC_MRGD_W6_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
104033 
104034 #define XRDC2_MRC_MRGD_W6_D9ACP_MASK             (0x38U)
104035 #define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT            (3U)
104036 /*! D9ACP - Domain "x" access control policy
104037  */
104038 #define XRDC2_MRC_MRGD_W6_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
104039 
104040 #define XRDC2_MRC_MRGD_W6_D10ACP_MASK            (0x1C0U)
104041 #define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT           (6U)
104042 /*! D10ACP - Domain "x" access control policy
104043  */
104044 #define XRDC2_MRC_MRGD_W6_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
104045 
104046 #define XRDC2_MRC_MRGD_W6_D11ACP_MASK            (0xE00U)
104047 #define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT           (9U)
104048 /*! D11ACP - Domain "x" access control policy
104049  */
104050 #define XRDC2_MRC_MRGD_W6_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
104051 
104052 #define XRDC2_MRC_MRGD_W6_D12ACP_MASK            (0x7000U)
104053 #define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT           (12U)
104054 /*! D12ACP - Domain "x" access control policy
104055  */
104056 #define XRDC2_MRC_MRGD_W6_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
104057 
104058 #define XRDC2_MRC_MRGD_W6_D13ACP_MASK            (0x38000U)
104059 #define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT           (15U)
104060 /*! D13ACP - Domain "x" access control policy
104061  */
104062 #define XRDC2_MRC_MRGD_W6_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
104063 
104064 #define XRDC2_MRC_MRGD_W6_D14ACP_MASK            (0x1C0000U)
104065 #define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT           (18U)
104066 /*! D14ACP - Domain "x" access control policy
104067  */
104068 #define XRDC2_MRC_MRGD_W6_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
104069 
104070 #define XRDC2_MRC_MRGD_W6_D15ACP_MASK            (0xE00000U)
104071 #define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT           (21U)
104072 /*! D15ACP - Domain "x" access control policy
104073  */
104074 #define XRDC2_MRC_MRGD_W6_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
104075 
104076 #define XRDC2_MRC_MRGD_W6_EAL_MASK               (0x3000000U)
104077 #define XRDC2_MRC_MRGD_W6_EAL_SHIFT              (24U)
104078 /*! EAL - Exclusive Access Lock
104079  *  0b00..Lock disabled.
104080  *  0b01..Lock disabled until next reset.
104081  *  0b10..Lock enabled, lock state = available.
104082  *  0b11..Lock enabled, lock state = not available.
104083  */
104084 #define XRDC2_MRC_MRGD_W6_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
104085 
104086 #define XRDC2_MRC_MRGD_W6_DL2_MASK               (0x60000000U)
104087 #define XRDC2_MRC_MRGD_W6_DL2_SHIFT              (29U)
104088 /*! DL2 - Descriptor Lock
104089  *  0b00..Lock disabled, descriptor registers can be written.
104090  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
104091  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
104092  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
104093  */
104094 #define XRDC2_MRC_MRGD_W6_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
104095 
104096 #define XRDC2_MRC_MRGD_W6_VLD_MASK               (0x80000000U)
104097 #define XRDC2_MRC_MRGD_W6_VLD_SHIFT              (31U)
104098 /*! VLD - Valid
104099  *  0b0..The MRGD is invalid.
104100  *  0b1..The MRGD is valid.
104101  */
104102 #define XRDC2_MRC_MRGD_W6_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)
104103 /*! @} */
104104 
104105 /* The count of XRDC2_MRC_MRGD_W6 */
104106 #define XRDC2_MRC_MRGD_W6_COUNT                  (32U)
104107 
104108 /* The count of XRDC2_MRC_MRGD_W6 */
104109 #define XRDC2_MRC_MRGD_W6_COUNT2                 (32U)
104110 
104111 
104112 /*!
104113  * @}
104114  */ /* end of group XRDC2_Register_Masks */
104115 
104116 
104117 /* XRDC2 - Peripheral instance base addresses */
104118 /** Peripheral XRDC2_D0 base address */
104119 #define XRDC2_D0_BASE                            (0x40CE0000u)
104120 /** Peripheral XRDC2_D0 base pointer */
104121 #define XRDC2_D0                                 ((XRDC2_Type *)XRDC2_D0_BASE)
104122 /** Peripheral XRDC2_D1 base address */
104123 #define XRDC2_D1_BASE                            (0x40CD0000u)
104124 /** Peripheral XRDC2_D1 base pointer */
104125 #define XRDC2_D1                                 ((XRDC2_Type *)XRDC2_D1_BASE)
104126 /** Array initializer of XRDC2 peripheral base addresses */
104127 #define XRDC2_BASE_ADDRS                         { XRDC2_D0_BASE, XRDC2_D1_BASE }
104128 /** Array initializer of XRDC2 peripheral base pointers */
104129 #define XRDC2_BASE_PTRS                          { XRDC2_D0, XRDC2_D1 }
104130 
104131 /*!
104132  * @}
104133  */ /* end of group XRDC2_Peripheral_Access_Layer */
104134 
104135 
104136 /*
104137 ** End of section using anonymous unions
104138 */
104139 
104140 #if defined(__ARMCC_VERSION)
104141   #if (__ARMCC_VERSION >= 6010050)
104142     #pragma clang diagnostic pop
104143   #else
104144     #pragma pop
104145   #endif
104146 #elif defined(__CWCC__)
104147   #pragma pop
104148 #elif defined(__GNUC__)
104149   /* leave anonymous unions enabled */
104150 #elif defined(__IAR_SYSTEMS_ICC__)
104151   #pragma language=default
104152 #else
104153   #error Not supported compiler type
104154 #endif
104155 
104156 /*!
104157  * @}
104158  */ /* end of group Peripheral_access_layer */
104159 
104160 
104161 /* ----------------------------------------------------------------------------
104162    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
104163    ---------------------------------------------------------------------------- */
104164 
104165 /*!
104166  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
104167  * @{
104168  */
104169 
104170 #if defined(__ARMCC_VERSION)
104171   #if (__ARMCC_VERSION >= 6010050)
104172     #pragma clang system_header
104173   #endif
104174 #elif defined(__IAR_SYSTEMS_ICC__)
104175   #pragma system_include
104176 #endif
104177 
104178 /**
104179  * @brief Mask and left-shift a bit field value for use in a register bit range.
104180  * @param field Name of the register bit field.
104181  * @param value Value of the bit field.
104182  * @return Masked and shifted value.
104183  */
104184 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
104185 /**
104186  * @brief Mask and right-shift a register value to extract a bit field value.
104187  * @param field Name of the register bit field.
104188  * @param value Value of the register.
104189  * @return Masked and shifted bit field value.
104190  */
104191 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
104192 
104193 /*!
104194  * @}
104195  */ /* end of group Bit_Field_Generic_Macros */
104196 
104197 
104198 /* ----------------------------------------------------------------------------
104199    -- SDK Compatibility
104200    ---------------------------------------------------------------------------- */
104201 
104202 /*!
104203  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
104204  * @{
104205  */
104206 
104207 /* No SDK compatibility issues. */
104208 
104209 /*!
104210  * @}
104211  */ /* end of group SDK_Compatibility_Symbols */
104212 
104213 
104214 #endif  /* _MIMXRT1176_CM7_H_ */
104215 
104216